AMRUTVAHINI COLLEGE OF ENGINEERING, SANGAMNER

ELEX/COMP-DTo write VHDL code and test bench, synthesis, simulate and down load it into PLD: (Period Measurement). Semester - I Page 1 of 2

Experiment No.: 06

Rev.: 00 Date: 03-07-10

Aim of Experiment: To write VHDL code and test bench, synthesis, simulate and down load it into PLD Period Measurement of a signal. Objectives: After performing this experiment, student should be able to write VHDL code and test bench, synthesis, simulate and down load into PLD: Period Measurement of a signal. Get familiar with EDA tool XILINX ISE. Theory: VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity periodm is Port ( A,clk,reset : in STD_LOGIC; q : out STD_LOGIC_VECTOR (3 downto 0)); end periodm; architecture Behavioral of periodm is signal s:std_logic_vector(3 downto 0); signal clk1:std_logic := '0'; signal count : integer := 1; begin p1 :process(clk) begin if clk 'event and clk = '1' then count <= count + 1 ; if count = 4000000 then clk1 <= not clk1; count <=1; end if; end if; end process p1; p2: process(clk1,reset,A) begin if reset='1' then s<="0000"; elsif clk1'event and clk1='1' then
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AMRUTVAHINI COLLEGE OF ENGINEERING, SANGAMNER

ELEX/COMP-DTo write VHDL code and test bench, synthesis, simulate and down load it into PLD: (Period Measurement). Semester - I Page 2 of 2

Experiment No.: 06

Rev.: 00 Date: 03-07-10

if A='1' then s<=s+1; end if; end if; end process p2; q<=s; end Behavioral; References: 1. Charles Roth, Digital System Design using VHDL, McGraw Hill Publication. 2. Perry, VHDL, McGraw Hill Publication. 3. Stefen Brown, Fundamentals of Digital Logic Design using VHDL,TATA McGraw Hill Publication.

Conclusion: Thus we have simulated and implemented VHDL code for Period Measurement of a signal on FPGA.

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