PROJECT PRESENTATION ON

Universal Asynchronous Receiver/Transmitter (UART)

Project Guide:
Er. Jay Kumar

Submitted by:
Mayank Sharma-0800431042 Uday Bhan Singh-0800431074 Shantanu Tripathi-0800431063 Chandra Prakash-0800431016
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CONTENTS
INTRODUCTION UART BLOCK DIAGRAM TRANSMITTER MODULE RECEIVER MODULE INPUT / OUTPUT PORTS APPLICATIONS OF UART DESIGNING TOOL: VHDL REFERENCES

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INTRODUCTION
The UART (universal asynchronous receiver and transmitter) module provides asynchronous serial communication with external devices such as modems and other computers. The UART can be used to control the process of breaking parallel data from the PC down into serial data that can be transmitted and vice versa for receiving data. The UART allows the devices to communicate without the need to be synchronized. The UART consists of one receiver module and one transmitter module. Those two modules have separate inputs and outputs for most of their control lines, the lines that are shared by both modules are the bidirectional data bus, master clock (mclkx16) and reset.

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Need of UART
A UART may be used when: High speed is not required An inexpensive communication link between two devices is required UART communication is very cheap Single wire for each direction (plus ground wire. Asynchronous because no clock signal is transmitted Relatively simple hardware

PC devices such as mouse and modems used to often use UARTs for communication to the PC

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BLOCK DIAGRAM

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UART Functions
Transmitter

Convert from parallel to serial Add start and stop delineators (bits) Add parity bit Receiver Convert from serial to parallel Remove start and stop delineators (bits) Check and remove parity bit

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TRANSMITTER MODULE
As soon as data is deposited in the shift register after completion of the previous character, the UART hardware generates a start bit, shifts the required number of data bits out to the line, generates and appends the parity bit (if used), and appends the stop bits

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UART Transmitter
Specifications

Parameters: 8 data bits, 1 stop bit, even or odd parity

Inputs: Din[7:0]: 8-bit parallel data input Send: Instructs transmitter to initiate a transmission Parity Select: Selects even parity (Parity Select=0) or odd parity (Parity Select=1) Outputs: Dout: Serial data output Busy: Tells the host its busy sending a character

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RECEIVER MODULE

The receiver tests the state of the incoming signal on each clock pulse, looking for the beginning of the start bit

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UART Receiver
Specifications

Parameters: 8 data bits, 1 start bit, even or odd parity

Inputs: Din: Serial data output overrun: Tells the host its busy receiving a character Outputs: Dout[7:0]: 8-bit parallel data input read: Instructs receiver to initiate a reception of data. Parity Select: Selects even parity (Parity Select=0) or odd parity (Parity Select=1)

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Input/output module

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Symbol
mclkx16 reset parityerr

Type
Input Input output

Description
Master input clock for internal baud rate generation Master reset Indicates whether a parity error was detected during the receiving of a data frame Indicates if the serial data format sent to the rx input did not match the proper UART data format

framingerr

output

overrun

output

Indicates whether new data sent in is overwriting the previous data received that has not been read out yet.
Indicates new data has been received and is ready to be read out. Indicates new data has been written to the transmitter

rxrdy

output

txrdy

output

Symbol
read

Type
Input

Description
Active low strobe signal, used for reading data out from the receiver.

write

Input

Active low strobe signal, used for writing data in to transmitter.

data (7 down In/Out to 0)

Bi-directional data bus for sending/receiving data across the UART

tx

Output

Transmitter serial output. Held high when no transmission occurring and when resetting

rx

Input

Receiver serial input. Pulled-up when no transmissions taking place.

UART Uses
PC serial port is a UART!
Serializes data to be sent over serial cable De-serializes received data
Serial Port

Serial Cable

Serial Port

Serial Cable

Device

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(contd..)
Communication between distant computers
Serializes data to be sent to modem De-serializes data received from modem
Phone Line
Phone Line Serial Cable

Serial Cable

Modem

Modem

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(contd..)
Used to be commonly used for internet access

Phone Line Phone Line

Internet
Server

Serial Cable

Modem

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UART Character Transmission

In the configuration shown, it takes 11 bits to send 8 bits of data Transmission efficiency is 8/11, or 72.72%

Start bit

8 data bits

Parity bit

Stop bit

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UART Transmission Example

Send the ASCII letter W (10101110)
Line idling
Mark 0 Space 8 data bits Least significant bit first Line idling again 1 1 1 0 1 0 1 0

Start bit

Parity bit
(odd parity)

Stop bit

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UART Character Reception

Start bit says a character is coming, receiver resets its timers

Receiver should sample in middle of bits

Mark
Space

Receiver uses a timer (counter) to time when it samples. Transmission rate (i.e., bit duration) must be known!
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UART Options
UARTs usually have programmable options:
Data: 7 or 8 bits Parity: even, odd, none Stop bits: 1, 2 Baud rate: 300, 1200, 2400, 4800, 9600, 19.2k, 38.4k, 57.6k, 115.2k

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UART Options
Baud Rate
The symbol rate of the transmission system For a UART, same as the number of bits per second (bps) Each bit is 1/(rate) seconds wide

Example:

9600 baud 9600 Hz 9600 bits per second (bps) Each bit is 1/(9600 Hz) 104.17 s long
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Not the data throughput rate!

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Tool Used VHDL :- Very high speed integrated circuit hardware description language
An initiative funded by the United States Department of Defense in the 1980s that led to the creation of VHDL. Its first version was VHDL 87, later upgraded to the so-called VHDL 93. VHDL was the original and first hardware description language to be standardized by the Institute of Electrical and Electronics Engineers, through the IEEE 1076 standard. VHDL is a hardware description language. It describes the behavior of an electronic circuit or system, from which the physical circuit or system can then be attained (implemented).
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Design Flow
VHDL :- Very high speed integrated circuit hardware description language.

Specification

programming

Simulation (Compile) Synthesis

Implementation on FPGA/CPLD

Hardware
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Modeling of VHDL
1. Data Flow modeling (Boolean Expression or Small Circuit)

2.

Behavioural Modeling ( Truth Table or input / output relation (for sequential )

3.

Structural Modeling (Large circuits, Interconnections of small modular (circuits)

4.

Mixed Modeling

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REFERENCES
1.Doughlas L. Perry VHDL programming 4TH Edition. 2. Karen Parnell & Nick Mehta Programmable Logic Design 2nd Edition. 3. Norhuzaimin, J, Maimun, H.H, Dept. of Electron., Univ. Malaysia Sarawak, Applied Electromagnetics, 2005. APACE 2005. Asia-Pacific Conference on uart. 4. Peter J. Ashenden VHDL Quick Start 2nd Edition. 5. Shouqian Yu, Lili Yi, Weihai Chen, Zhaojin Wen Beijing Univ. of Aeronaut. & Astronaut., Beijing, Industrial Electronics and Applications, 2007. ICIEA 2007. 2nd IEEE Conference on uart. 6. Teemu Pitkanen VHDL Basics. 7. Zhichao Zhang, Wuchen Wu VLSI & Syst. Lab., Beijing Univ. of Technol., Beijing, China Computer Engineering and Technology (ICCET), 2010 2nd International Conference on uart. 8. www.ieeeexplore.com 9.www.howstuffworks.com
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Thanks