module trafficlight(clk,vehi_count1,vehi_count2,vehi_count3,vehi_count4,light1,lig ht2,light3,light4); input [4:0]vehi_count1; input [4:0]vehi_count2; input [4:0]vehi_count3; input [4:0]vehi_count4; input clk; output reg

[2:0]light1; output reg [2:0]light2; output reg [2:0]light3; output reg [2:0]light4; parameter s0=2'd00; parameter s1=2'd01; parameter s2=2'd10; parameter s3=2'd11; parameter green=3'd000; parameter red=3'd111; reg [1:0]pres_state =2'd00; reg [1:0]next_state =2'd00; always @(posedge clk) pres_state<=next_state; always @ (pres_state or vehi_count1 or vehi_count2 or vehi_count3 or vehi_count4) case(pres_state)

s0:begin if(vehi_count1>vehi_count2 & vehi_count1>vehi_count2 & vehi_count1>vehi_count4) begin next_state<=s1; light1<=green; light2<=red; light3<=red; light4<=red; end next_state<=s1; end s1:begin if(vehi_count2>vehi_count3 & vehi_count2>vehi_count1 & vehi_count2>vehi_count4) begin next_state<=s2; light1<=red; light2<=green; light3<=red; light4<=red; end next_state<=s2; end s2:begin

if(vehi_count3>vehi_count4 & vehi_count3>vehi_count1 & vehi_count3>vehi_count2) begin next_state<=s3; light1<=red; light3<=green; light2<=red; light4<=red; end next_state<=s3; end

s3:begin if(vehi_count4>vehi_count3 & vehi_count4>vehi_count1 & vehi_count4>vehi_count2) begin next_state<=s0; light1<=red; light4<=green; light2<=red; light3<=red; end next_state<=s0; end endcase

endmodule

test bench: module traff7(); reg clk=1'b0; reg [4:0]vehi_count1; reg [4:0]vehi_count2; reg [4:0]vehi_count3; reg [4:0]vehi_count4; wire [2:0]light1; wire [2:0]light2; wire [2:0]light3; wire [2:0]light4; trafficlight v1(clk,vehi_count1,vehi_count2,vehi_count3,vehi_co unt4,light1,light2,light3,light4);

always #20 clk=~clk; initial begin

vehi_count1=5'd20; vehi_count2=5'd30; vehi_count3=5'd10; vehi_count4=5'd05;

end endmodule