Half Subtractor Half Subtractor - Gate Level Modelling module halfsub(a,b1,diff,borrow); input(a,b1); output(diff,borrow); wire Anot; not(Anot,a); xor(diff,a,b1);

and(borrow,Anot,b1); endmodule Half Subtractor - Data Flow Modelling module halfsub(a,b1, diff,borrow); input a,b1; output diff,borrow; assign diff=a^b1; assign borrow=~a&b1; endmodule

Half Adder Half Adder - Gate Level Modelling module halfadd(a,b1,sum,carry); input(a,b); output(sum,carry); xor(sum,a,b); and(carry,a,b); endmodule Half Adder - Data Flow Modelling module halfadd(a,b,sum,carry); input a,b; output sum,carry; assign sum=a^b1; assign carry=a&b1; endmodule

Full Adder

Full adder Dataflow Modelling module Fulladder(a,b,c,sum,carry); input a,b,c; output sum,carry; assign sum=a^b^c; assign carry=a&b|b&c|a&c; endmodule

Full Subtractor Full Subtractor Gate level Modelling module fullsubtractor(a,b,c,diff,Borrow); input a,b,c; output diff,Borrow; wire w1,w2,w3,w4; xor (diff,a,b,c); not (w1,a); and (w2,w1,b); and (w3,w1,c); and (w4,b,c); or (Borrow,w3,w2,w4); endmodule Full Subtractor Dataflow Modelling module FullSubtractor(a,b,c, diff,Borrow); input a,b,c; output diff,Borrow; assign diff=a^b^c; assign Borrow=~a&b|b&c|a&c; endmodule

module siso(din,clk,rst,dout); input din,rst,clk; output dout; reg dout; reg [7:0]x; always @ (posedge(clk) or posedge(rst)) begin if (rst == 1b1) begin dout = 8hzz; end else begin x={x[6:0],din}; dout=x[7:0]; end end endmodule

module sipo(din,clk,rst,dout); input din,rst,clk; output [7:0] dout; reg [7:0] dout; reg [7:0]x; always @ (posedge(clk) or posedge(rst)) begin if (rst) begin dout = 8hzz; end else begin x={x[6:0],din}; dout=x; end end endmodule

module pipo(din,clk,rst,dout); input [7:0] din input rst,clk; output [7:0] dout; reg [7:0] dout; always @ (posedge(clk) or posedge(rst)) begin if (rst==1b1) begin dout = 8hzz; end else begin dout=din; end end endmodule

module piso(din,clk,rst,load,dout); input [7:0] din; input load,rst,clk; output dout; reg dout; reg [8:0]x; always @ (posedge(clk) or posedge(rst)) begin if (rst==1b1) begin dout = 1bz; end else begin if (load==1b0) begin x=din; end else x={x[7:0],1hz}; dout=x[8:0]; end end endmodule

JK Flip Flop

module jkff(q,q1,j,k,c); output q,q1; input j,k,c; reg q,q1; initial begin q=1'b0; q1=1'b1; end always @ (posedge c) begin case({j,k}) {1'b0,1'b0}:begin q=q; q1=q1; end {1'b0,1'b1}: begin q=1'b0; q1=1'b1; end {1'b1,1'b0}:begin q=1'b1; q1=1'b0; end {1'b1,1'b1}: begin q=~q; q1=~q1; end endcase end endmodule

D Flip Flop

module dff(q,q1,d,c); output q,q1; input d,c; reg q,q1; initial begin q=1'b0; q1=1'b1; end always @ (posedge c) begin q=d; q1= ~d; end endmodule