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B.Sc. Electrical Engineering (2nd Year)

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DIGIAL LOGIC & DESIGN (EE-204)

Boolean Algebra & Logic Gates

Dr. Abdul Sattar Malik

Parallel Binary Adder

x3x2x1x0 y3y2y1y0 Binary Adder S3S2S 1S0 Carry Propag ate Additio n x1 y1 FA
c3 c2 c1 . + x3 x2 x1 x0 + y3 y2 y1 y0 Cy S3 S2 S1 S0

C y

C 0 x2 y2

x3 x0y3 y0 FA

0 FA FA

C4 C1

S3 S0

C3

S2

C2

S1

Carry Propagation
(Parallel Binary Adder)

Carry Propagate Adder

x7 x6 x5 y7 y6 y5 y4 x4 A3 A2 A1 B3 B2 B1 CPA A0 B0 C C y 0 S3 S2 S1 S0 S7 S6 S5 S4

x3 x2 x1 x0

y3 y2 y1 y0

A3 A2 A1 B3 B2 B1 CPA A0 B0 C C y 0 S3 S2 S1 S0 S3 S2 S1 S0

Look Ahead Carry Generator

(Parallel Binary Adder)

Look Ahead Carry Generator

(Parallel Binary Adder)

BCD Adder
4-bits plus 4-bits Operands and Result: 0 to
+ x3 x2 x1 x0 + y3 y2 y1 y0 Cy S3 S2 S1 S0

X +Y 0+0 0+1 0+2 0+9 1+0 1+1 1+8 1+9 2+0 9+9

x3 x2 x1 y3 y2 y1 y0 x0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 0 0

Sum Cy =0 =1 =2 =9 =1 =2 0 0 0 0 0 0

S3 S2 S1 S0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0

=9 0 =A 0 =2 0

Invalid Code Wrong BCD Value

1 0 0 1 = 12 1

0001

BCD Adder
X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy 9+0 9+1 9+2 9+3 9+4 9+5 9+6 9+7 9+8 9+9 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 =9 = 10 = 11 = 12 = 13 = 14 = 15 = 16 = 17 = 18 0 0 0 0 0 0 0 1 1 1 S3 S2 S1 Required BCD Output Value S0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 =9 = 16 = 17 = 18 = 19 = 20 = 21 = 22 = 23 = 24

+6

BCD Adder
Correct Binary Adders

Output (+6)
If the result is between A

S3 S2 S1 S0 If Cy = 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

and F

Err 0 0 0 1 1 1 1 1 1

S1

S3

1 1

1 1

S2

S0 Err = S3 S2 + S3 S1

BCD Adder

Parallel Binary Adder/ Subtractor

Use 2s complement with

binary adder
x y = x + (-y) = x + y + 1

Binary Adder/Subtractor
M: Control Signal

(Mode)

M=0 F = x + y

x M=1 F = x xy x x

y y y y

A A AA B B B B Cy Ci Binary Adder S SS S FFFF

Overflow
x3 x0y3 y0 x2 y2 FA x1 y1 0 FA FA

Unsigned Binary

FA

Numbers

Car ry

C4

S3 x3 x0 y3 y0

C3 x2

S2

C2

S1 x1

C1

S0

y2 FA

y1 0 FA FA

2s Complement

FA

Numbers

Overflo w

C4

S3

C3

S2

C2

S1

C1

S0

Magnitude Comparator
Compare 4-bit number to 4-

bit number
3 Outputs: A<B , A=B , A>B Expandable to more number

A3A2A1A0 B3B2B1B0 Magnitude Comparator A<B A=B A>B

x= A of bits B+ AB x= AB+ AB

x = AB+ AB

x = AB+ AB ( A = B ) = xxxx ( A > B ) = AB+ xAB+ xxAB+ xxxAB ( A < B) = AB+ xAB+ xxAB+ xxxAB

Magnitude Comparator
A B A B A (A<B) x x

B A B (A=B)

(A>B)

Magnitude Comparator

0 1 0

x7 x6 x5 y7 y6 y5 x4 y4 A3 A2 B3 B2 Magnitude I( A1 A0 B1 B0 A Comparator > A<B A=B B) A>B I( A = B) I( A < B)

x3 x2 x1 y3 y2 y1 x0 y0 A3 A2 A1 B3 B2 B1 Magnitude I(A A0 B0 Comparator >B ) I(A A<B A=B A>B =B ) I(A A<B A=B <B A>B )

Decoders
Extract Information from

the code
Binary Decoder
Example: 2-bit Binary

Number

Only one lamp will turn on

0
0 x 1 x 0 0 Binary 1 Decoder 0 0 0

Decoders
2-to-4 Line

Decoder

Binary Decoder

I 1

I I1 0 I0 0 0 1 1 0 1 0 1

y 3 y 2

Y Y Y

Y3 Y2y Y1 Y0 1 0 0 y 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0

I I

Y= II Y= II

Y = II Y = II

Decoders
3-to-8 Line Decoder
Y = Y =

I II

I II I II I II I II I II I II I II

Binary Decoder

I 2 I 1 I 0

Y 7 Y 6 Y 5 Y 4 Y 3 Y

Y = Y = Y = Y = Y = Y =

I I I

Decoders
Enable Control

Binary Decoder

E 0 1 1 1 1

I 1 I 0 I1 I0 Y3 Y2 Y1 Y0 E Y x x 0 01 0 0 Y 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0

Y 3 Y 2

Y Y Y Y

I I E

Decoders
Expansion

I2 I1 I0

Binary Decoder

I 0 I 1

Binary Decoder

I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0

I 0 I 1 E

Y 3 Y 2

Y 7 Y 6 Y 5 Y 4

Y Y 1 3 Y Y 0 2

Decoders
Active-High /

Active-Low

I1 I0 Y3 Y2 Y1 Y0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 Y 3 Y 2 Y

I1 I0 Y3 Y2 Y1 Y0 0 0 1 1 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 0 1 1 1 Y 3 Y 2 Y

Y Y Y

I 0

I 0

Binary Decoder

Binary Decoder

I 1

I 1

I I

Implementation Using Decoders

Each output is a

Minterm

Binary Decode r

All Minterms are

produced

Sum the required

Minterms Example: Full Adder S(x, y, z) = (1, 2, 4, 7) C(x, y, z) = (3, 5, 6, 7)

x y z

I 2 I 1 I 0

Y 7 Y 6 Y 5 Y 4 Y 3 Y 2

S C

Implementation Using Decoders

Binary Decoder Binary Decoder

x y z

I 2 I 1 I 0

Y 7 Y 6 Y 5 Y 4 Y 3 Y 2

x y z

I 2 I 1 I 0

Y 7 Y 6 Y 5 Y 4 Y 3 Y 2

S C

S C

Encoders
Put Information into

code
Binary Encoder
Example: 4-to-2 Binary

1 2 3

Encoder

x 1 x 2 x 3

Binary Encoder y 1 y 0

x3 x2 0 0 0 1 0 0 1 0

Only one switch should be activate x1 y1 y0 d at a 0 time0 0 1 0 1 0 1 0 0 1 1

Encoders
Octal-to-Binary Encoder

Y = I + I + I + I Y= I + I + I + I Y = I + I + I + I

I I I I I I I I

Binary Encoder

(8-to-3) I7 I6 I5 I4 I3 I2 I1 I0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0

Y2 Y1 Y0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

I 7 I 6 I 5 I 4 I 3 I 2

Y 2 Y 1 Y 0
Y Y Y

Priority Encoders
4-Input Priority

Encoder

I I I

Y1

I1

Y= I + I Y = I + I I
I2

I 1 I 0

1 1 1 1

I3

1 1 1 1 1 1 1 1

V = I + I + I+ I

I0

Priority Encoder

I3 I2 I1 I0 Y1 Y0 V 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 x 0 1 1 0 1 x x 1 0 1 1 x x x 1 1 1

I 3 I 2

V Y 1 Y 0
Y

Y V

Encoder / Decoder Pairs

Binary Encod er Binary Decod er Y 7 Y 6 Y 5 Y 4 Y 3 Y

7 6 5 4 3 2 1 0

I 7 I 6 I 5 I 4 I 3

Y 2 Y 1 Y 0

I 2 I 1 I 0

7 6 5 4 3 2 1 0

Multiplexers

S1 S0 0 0 1 1 0 1 0 1

Y I0 I1 I2 I3

I MUX 0 Y I 1 S1 S0 I 2

Multiplexers
2-to-1

MUX

I MUX Y 0 I S 1 I MUX 0 Y I 1 S1 S0 I 2 I

Y I S
I I I I Y

4-to-1

MUX

Multiplexers
Quad 2-to-1

MUX

x 3 y 3 x 2 y 2 x 1 y 1

MUX I 0 I S 1 MUX I 0 I S 1 MUX I 0 I S 1 MUX I 0 I S 1 S

A A A

Y Y Y Y

A B

MUX A 3 A 2 A B 1 3 A B 0 2 B 1 B 0

B B B

Y 3 Y 2 Y 1 Y 0

Y
S E

S E

Multiplexers
Quad 2-to-1
A MUX A A A B B B B Y Y Y Y

MUX A 3 A 2 A B 1 3 A B 0 2 B 1 B

Y 3 Y 2 Y 1 Y 0

Extra Buffers
S E

S E

Implementation Using Multiplexers

Example

F(x, y) = (0, 1, 3)

x y 0 0 1 1 0 1 0 1

F 1 1 0 1

1 1 0 1

MUX I 0 Y I 1 S1 S0 I 2 x I y 3

Implementation Using Multiplexers

Example

F(x, y, z) = (1, 2, 6, 7)

x 0 0 0 0 1 1 1 1

y 0 0 1 1 0 0 1 1

z 0 1 0 1 0 1 0 1

F 0 1 1 0 0 0 1 1

0 1 1 0 0 0 1 1

MUX I 0 I 1 I 2 I 3 I 4 I 5

S2 S1 S0 x y z

Implementation Using Multiplexers

Example

F(x, y, z) = (1, 2, 6, 7)

x 0 0 0 0 1 1 1 1

y 0 0 1 1 0 0 1 1

z 0 1 0 1 0 1 0 1

F 0 1 1 0 0 0 1 1

F= z F= z F= 0 F= 1

z z 0 1

MUX I 0 Y I 1 S1 S0 I 2 x I y 3

Implementation Using Multiplexers

Example

F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F 0 1 0 1 1 0 0 0 0 0 0 1 1 1 1 1

F= D F= D F= D F= 0 F= 0 F= D F= 1 F= 1

D D D 0 0 D 1 1

MUX I 0 I 1 I 2 I 3 I 4 I 5

S2 S1 S0 A B C

Multiplexer Expansion
8-to-1 MUX using Dual 4-

to-1 MUX

I 0 I 1 I 2 I 3 I 4 I

MUX I 0 Y I 1 S1 S0 I 2 MUX I I 0 3 Y I 1 S1 S0 I 2 1 0 S2 S1 S0 0 I

MUX I 0 I S 1

DeMultiplexers
DeMUX I S1 S0 Y 3 Y 2 Y 1 Y 0

Y Y Y Y

S1 S0 Y3 Y2 Y1 Y0 0 0 1 1 0 1 0 1 0 0 0 I 0 0 I 0 0 I 0 0 I 0 0 0

S S

Multiplexer / DeMultiplexer Pairs

MU X DEMU X Y 7 Y 6 Y 5 Y S2 S14 S0 Y 3 Y y2 y12 y0 I

7 6 5 4 3 2 1 0

I 7 I 6

I 5 I 4 S2 S1 I S0 3 I x1 x2 2 x0

7 6 5 4 3 2 1 0

Synchroni ze

DeMultiplexers / Decoders
DeMUX I S1 S0 S1 S0 Y3 0 0 1 1 0 1 0 1 0 0 0 I Y 3 Y 2 Y 1 Y Y2 0 0 0 I 0 Y 3 Y 2

E Y1 Y0 0 I 0 0 I 0 0 0 0 1 1 1 1

I 1 I 0 I1 E Y3 Y2 Y1 Y0 I0 Y x x 0 0 1 0 0 0 0 0 0 Y0 1 0 1 0 0 01 0 1 0 0 1 0 0 1 1 1 0 0 0 Binary Decoder

QUESTIONS