Library IEEE; use IEEE.STD_LOGIC_1164.

ALL; entity mux_4 is port ( A,B,C,D : in std_logic; sel : in std_logic_vector(1 downto 0); bitout : out std_logic ); end mux_4; architecture behavioral of mux_4 is begin process(A,B,C,D,sel) begin case sel is when "00" => bitout <= A; when "01" => bitout <= B; when "10" => bitout <= C; when others => bitout <= D; end case; end process; end behavioral;