Vlsi

9/10/2012
1
Very Large Scale Integration
Lecture-1
Shailendra Kumar Tiwari
9/10/2012 S.K.Tiwari(Asst.Prof.ECEMITManipal) 1
1. ReferenceBooks.
2. Whatisthereforme?
3. Whatisexpected?
4. Designabstractionlevel
5. Devicegenerations
6. Technologygeneration
7. Mooreslaw
8. Scaling
9. DisplayTechnology
Outline
10. Questions.
11. Summary.
9/10/2012
2
BasicVLSIDesign,3
rd
Ed.,PHI
By:PUCKNELLDOUGLASA.ESHRAGHIAN,
KAMRAN
CMOSDIGITALINTEGRATED
CIRCUITS:Analysis andDesign
3
rd
Ed.McGrawHill.
By:SUNGMO (STEVE)KANG
ReferenceBooks
DigitalIntegratedCircuits ADesignPerspective,
2nded.byJ.Rabaey,A.Chandrakasan,B.Nikolic
CMOSLOGICCIRCUITDESIGN
KLUWERACADEMICPUBLISHERS
By:JohnP.Uyemura
ReferenceBooks
9/10/2012
3
CMOS VLSI Design:A Circuits and Systems
Perspective 4
th
ed. AddisonWesley
By: Neil H. E. Weste, David Money Harris
ReferenceBooks
1.WorldSemiconductorIndustry
9/10/2012
4
Thefirstcomputer
DifferenceEngines
ThefirstElectroniccomputer(ENIC)1946
9/10/2012
5
TheFirstTransistor(1948)
John Bardeen, William
Shockley and Walter
Brattain at Bell Labs,
1948.
FirstIntegratedCircuit(IC)
ECL3Input
Logicby
Motorola
1966
9/10/2012
6
9/10/2012
7
9/10/2012
8
Whatisexpected?
Power
Min
Min Design Time
Cost
Min
Complexity
Min
Delay
Size Min
9/10/2012
9
DEVICE GENERATIONS
Vacuum Tubes
BJT
FET
MOSFET
CMOS
TECHNOLOGYGENERATIONS
Integrationlevel Year No.oftransistors DRAMIntegration
SSI 1950s Lessthan10
2
MSI 1960s 10
2
~ 10
3
LSI 1970s 10
3
~ 10
5
4K,16K,64K
VLSI 1980s 10
5
~ 10
7
256K,1M,4M
ULSI 1990s 10
7
~ 10
9
16M,64M,256M
SLSI 2000s Over10
9
1G,4GandAbove
9/10/2012
10
The evolution of MOS technology has followed the famous Moores law that
predicts a steady decrease in gate length. As predicted by Gordon Moore in
the 1960s, integrated circuit (IC) densities have been doubling
approximately every 18 months, and this doubling in size has been
accompanied by a similar exponential increase in circuit speed (or more
precisely, clock frequency).
Mooreslaw
OnchiptransistorcountincreasefortheIntelprocessors(Source:Intel).
TechnologyScaling
GATE
SOURCE
BODY
DRAIN
Xj
Tox D
GATE
SOURCE
DRAIN
Leff
BODY
Dimensions scale down
by 30%
Doubles transistor density
Oxide thickness scales
down
Faster transistor, higher
performance
Vdd & Vt scaling Lower active power
Technology has scaled well, will it in the future?
9/10/2012
11
Scaling
W=0.7, L=0.7, T
ox
=0.7
=> Lateral and vertical dimensions reduce 30 %
Area Cap = C = 0.7 X 0.7 = 0.7
0.7
=> Capacitance reduces by 30 %
Die Area = X x Y = 0.7x0.7 = 0.7
2
=> Die area reduces by 50 %
V
dd
=0.7, V
t
=0.7, T
ox
=0.7, I=(W/L) (C
ox
)(V-V
t
)
2
= 0.7
T= C x V
dd
= 0.7, Power = CV
2
f = 0.7 x 0.7
2
= 0.7
2
I 0.7
=> Delay reduces by 30 % and Power reduces by 50 %
= 0.7
Technology ThenandNow
1981 2000 RATIO
Technology p-well
CMOS
Dual Well CMOS
Gate Oxide 40 nm 2 nm 20X
Poly Dimension 2.5 m 0.12 m 20X
Metal Layers 1 6
SRAM-Density

Cell Area
Access Time
4 K

1000 m
2

40 nS
16 M

5 m
2

1 nS
4000X

200X
40X

November2000 Pentium4releasedwithclockspeed:1.5GHz
Numberoftransistors:42million
9/10/2012
12
TransistorCountTrend
FromS.E.Thompson,Sub100nmCMOS
MicroprocessorFrequencyTrend
FromS.E.Thompson,Sub100nmCMOS,IEDM1999ShortCourse
9/10/2012
13
MinimumFeatureSizeTrend
FromS.E.Thompson,Sub100nmCMOS
TransistorIntegrationCapacity
0.001
0.01
0.1
1
10
100
1000
10 5 2 1 0.5 0.25 0.13 0.07
Technology ()
T
r
a
n
s
i
s
t
o
r
s

(
M
i
l
l
i
o
n
)
1 Billion
On track for 1B transistor integration capacity
9/10/2012
14
IEDM 2003
Power Extrapolation
Sony e-Reader
DisplayTechnology
9/10/2012
15
MOSVs BJT
Factors CMOS Bipolar
StaticPower
Dissipation
Low High
Input
Impedance
High Low
NoiseMargin High Low
PackingDensity High Low
Fanout Low High
Direction Bidirectional Unidirectional
Micro
Electronics
Active
Substrate
Silicon
MOS
NMOS
PMOS
CMOS
Bipolar
TTL
ECL
GaAs
VeryFast
Devices
Inert
Substrate
Good
resistors
MicroelectronicsTechnology
9/10/2012
16
MOSCapacitor
A negative voltage is applied to the gate, so there is negative
charge on the gate. The mobile positively charged holes are
attracted to the region beneath the gate. This is called the
accumulation mode
i.Accumulation
C
g
=
e
ox
tox
9/10/2012
17
A small positive voltage is applied to the gate, resulting in some
positive charge on the gate. The holes in the body are repelled from
the region directly beneath the gate, resulting in a depletion region
forming below the gate.
ii.Depletion
MOSCapacitor
C
dcp
=
e
s
XJ
C
g
=
e
ox
tox
A higher positive potential exceeding a critical threshold
voltage V
t
is applied, attracting more positive charge to the
gate. The holes are repelled further and some free electrons
in the body are attracted to the region beneath the gate.
This conductive layer of electrons in the ptype body is
called the inversion layer
iii.inversion
MOSCapacitor
C
g
=
e
ox
tox
9/10/2012
18
MOSCapacitor
36
CrosssectionalViewofaTypical
NMOSFET
CentralregionofdeviceconsistofaMetalOxideSemiconductor
Subsystemmadeupofaconductingregioncalledthegate[M],
ontopofaninsulatingsilicondioxidelayer[O]
ptypesilicon[S]epitaxiallayerontopofaP
+
substrate.
n
+
regionsconstitutethedrain andsource terminals
Ithasfourterminalsviz.GateG,DrainD,SourceSand
SubstrateB.
9/10/2012 S.K.Tiwari(Asst.Prof.ECEMITManipal)
9/10/2012
19
37
p
+
regionsconstitutethedrain andsource terminals
Ithasfourterminalsviz.GateG,DrainD,SourceSand
SubstrateB.
CrosssectionalViewofaTypical
PMOSFET
ArrowsalwayspointfromPtoN,soanNMOS(Nchannel
inPwellorPsubstrate)hasthearrowpointingin(from
thebulktothechannel)
9/10/2012
20
39
ForPchannelMOSsubstrateisofNtypeandsource,drainare
formedwithPtypematerial.
ForNchannelMOSsubstrateisofPtypewhilesource&drainareformed
withNtypematerial.
Gateispolycrystallinesiliconelectrodeandisinsulatedfrom
substratebythinlayerofsilicondioxideSiO
2
Sincethegateisinsulated,MOSFETsarealsocalledas
InsulatedGateFieldEffectTransistors(IGFET)
Itisavoltagecontrolleddevice,thecurrentthroughchanneliscontrolledby
voltageappliedtogate.
MOSFETscanbeconfiguredeitheras
EnhancementtypeMOSFETOR
DepletiontypeMOSFET
MetalOxideSemiconductor
FieldEffectTransistor
40
EnhancementNMOS
Lightly doped p-type material forms substrate
Highly doped n
+
regions separated by substrate form drain & source
When gate voltage V
GS
= 0, drain current is zero.
Since the gate is insulated, any positive voltage applied to
gate, will produce electric field across substrate.
Source
Drain
Gate
PMOS
Gate
Drain
Source
NMOS
G
D
S
9/10/2012
21
41
This field will end on induced negative charges in p substrate.
These negatively charged electrons, which are minority carriers in p
substrate, form an inversion layer. Current flows from source to drain
through this induced channel.
More the positive voltage, More is the induced charge & hence more
current flows from source to drain.
This is also called Normally Off MOS, since drain current is zero for
zero gate voltage.
CMOS integrated circuits use enhancement type transistors only.
EnhancementMOS
42
EnhancementNMOS
Channel
Region
p-type substrate
(Body)
n+ n+
Source (S)
Gate (G) Drain (D)
L
Body (B)
Oxide (SiO
2
)
Metal
9/10/2012
22
43
In Depletion MOS structure, the source & drain are diffused on
P- substrate as shown above.
Positive voltages enhances number of electrons from source to
drain.
Negative voltage applied to gate reduces the drain current
This is called as normally ON MOS.
DepletionTypeMOS
G
D
S
NMOS
Source
Drain
Gate
PMOS
Gate
Drain
Source
NMOS
p-type substrate
(Body)
n+ n+
Source (S)
Gate (G) Drain (D)
L
Body (B)
Oxide (SiO
2
)
Metal
DepletionTypenMOS
9/10/2012
23
45
OperationOfNMOSTransistor
Depending on the relative voltages of the source, drain and gate, the
NMOS transistor may operate in any of three regions viz :
Cut_off : Current flow is essentially zero (also called
accumulation region)
Linear : (Non saturated region)-It is weak inversion region
drain current depends on gate and drain voltage.
Saturation : It is strong inversion region where drain current
is independent of drain-source voltage.
46
CutoffRegion
With zero gate bias (V
GS
=0) , no current flows between source
and drain, only the source to drain leakage current exists.
Current-voltage relation : I
DS
= 0 V
GS
< V
T
p-type substrate
(Body)
Source (S)
V
DS
=0
n+
n+
n+
n+
V
GS
=0
9/10/2012
24
47
LinearRegion
Formation of Depletion layer
Small positive voltage applied to gate causes electric field to be
produced across the substrate
This in turn causes holes in P region to be repelled. This forms
the depletion layer under the gate.
V
DS
=0
0 < V
GS
< V
t
p-type substrate
(Body)
Source (S)
n+
n+
n+
n+
Depletion Layer
48
LinearRegion
Formation of Inversion layer :
As the gate voltage is further increased, at particular voltage V
T
,
electrons are attracted to the region of substrate under gate thus forming
conduction path between source and drain.
This induced layer is called inversion layer. The gate voltage necessary
to form this layer is known as Threshold voltage (V
T
).
As application of electric field at gate causes formation of inversion
layer, the junction is known as field induced junction.
V
DS
=0
V
GS
> V
t
p-type substrate
(Body)
Source (S)
n+
n+
n+
n+
Inversion Layer
9/10/2012
25
49
LinearRegion
When V
DS
is applied, the horizontal component of electric field (due
to source-drain voltage) and vertical component (due to gate-
substrate voltage) interact, causing conduction to occur along the
channel.
When effective gate voltage (V
GS
- V
T
) is greater than drain
voltage, current through the channel increases. This is non
saturated mode. I
D
= f (V
GS
,V
DS
)
V
DS
< V
GS
- V
t
V
GS
> V
t
p-type substrate
(Body)
Source (S)
n+
n+
n+
n+
Inversion Layer
50
As V
DS
is increased, the induced Channel acquires a tapered shape and
its resistance increases with Increase in V
DS
.
Here V
GS
is kept constant at value > V
T
Saturation
V
DS
= V
GS
- V
t
V
GS
> V
t
p-type substrate
(Body)
Source (S)
n+
n+
n+
n+
n- channel
9/10/2012
26
51
Saturation
WhenV
DS
>V
GS
V
T
,V
GD
<V
T
,thechannelbecomespinched off&
transistorissaidtobeinsaturation.
Conductionisbroughtbydriftmechanismofelectronsundertheinfluenceof
positivedrainvoltageandeffectivechannellengthis
modulated.
p
V
DS
> V
GS
- V
t
V
GS
> V
t
p-type substrate
(Body)
Source (S)
n+
n+
n+
n+
n- channel
DraintoSourceCurrentI
DS
Currentisflowofcharges.
I
DS
=f(V
GS
,V
DS
)
I
S
= -I
S
=
Cborgc InJuccJ in tbc Cbonncl(
c
)
Elcctron Ironsit Iimc()
S
=
Icngtb o Cbonncl (I)
Iclocity(:)
Continued..
9/10/2012
27
Velocityvisgivenby
: = E
S
=electronorholemobility(surface)
E
DS
=DraintoSourceElectricField
E
S
=
I
S
I
: =
I
S
I
DS
Continued..
S
=
I
2
I
S
n
=650cm
2
/VSec
p
=240cm
2
/VSec
TheNonSaturatedRegion
ChargeinducedinchannelduetoV
GS
.
VoltagealongthechannelvarieslinearlywithdistanceX
fromsourceduetoIRdropinthechannel.
TheaveragevalueofIRdropinthechannel
I
S
2
I
S
< (I
uS
- I
1
)
Continued..
DS
9/10/2012
28
Theeffectivegatevoltage
V
G
=V
GS
V
T
Charge/unitarea=E
G
c
ins
c
0
Chargeinducedinchannel=WLE
G
c
ins
c
0
E
G
=Averageelectricfieldgatetochannel.
c
0
=8.8510
14
F/cm(Permittivityoffreespace)
c
ins
= c
0
4.0
E
u
=
I
uS
-I
1
-
I
S
2
D=Thicknessofoxidelayer Continued..
DS
c
=
wIe
ns
e
0
I
uS
-I
1
-
I
S
2
I
S
=
e
ns
e
0
w
I
I
uS
- I
1
-
I
S
2
I
S
I
S
= K
w
I
I
uS
- I
1
-
I
S
2
I
S
K =
e
ns
e
0
[ = K
w
I
I
S
= [ I
uS
- I
1
-
I
S
2
I
S
Continued..
DS
9/10/2012
29
C
u
=
e
ns
e
0
wI
K =
C
u
wI
I
S
=
C
u
I
2
I
uS
- I
1
-
I
S
2
I
S
C
u
= C
0
wI
I
S
=
C
0
w
I
I
uS
- I
1
-
I
S
2
I
S
Continued..
DS
SaturationRegionI
S
(I
uS
-I
1
)
I
S
= K
w
I
(I
uS
-I
1
)
2
2
I
S
=
C
u
2I
2
(I
uS
-I
1
)
2
I
S
=
[
2
(I
uS
-I
1
)
2
I
S
=
C
0
w
2I
(I
uS
-I
1
)
2
DS
9/10/2012
30
59
N-CHANNEL MOSFET
Cut- off Region (V
GS
< V
T
)
I
DS
~ 0
Linear Region (V
GS
> V
T
) & (V
DS
< V
GS
- V
T
)
I
DS
= |
n
[2.(V
GS
V
T
) V
DS
V
DS
2
]
Saturation Region (V
GS
> V
T
) & (V
DS
> V
GS
- V
T
)
I
DS
= |
n
[(V
GS
V
T
)
2
(1 + V
DS
)]
is an empirical constant called as channel length modulation
MOSFETDrainCurrentEquations
60
P-CHANNEL MOSFET
Cut- off Region (V
GS
>
V
T
)
I
DS
~ 0
Linear Region (V
GS
s V
T
) & (V
DS
> V
GS
- V
T
)
I
DS
= |
p
[2.(V
GS
V
T
) V
DS
V
DS
2
]
Saturation Region (V
GS
s V
T
) & (V
DS
s V
GS
- V
T
)
I
DS
= |
p
[(V
GS
V
T
)
2
(1 + V
DS
)]
is an empirical constant called as channel length modulation
MOSFETDrainCurrentEquations
9/10/2012
31
61
Where | =k W/L;calledasgainfactorofthedevice
k =e
ox
/t
ox
calledprocesstransconductanceparameter
t
ox
=Thicknessofthegateinsulator
L=Lengthofchannel
e
ox
=Permitivityofgateinsulator
LinearRegion
Since
n
=2
p
=>k
n
=2k
p
thus |
n
=2|
p
62
DraincurveforNMOSoperatedwith
V
GS
>V
T
9/10/2012
32
63
I
D
V
DS
characteristics
CUTOFF REGION
64
I
GS
= 0
I
S
= I
D +
-
+
-
IVcharacteristicsofNMOS
Transconductance curve
9/10/2012
33
DeterminetheRegionofOperationofM
1
1
OffbecauseV
GS
=0V
2
SaturationV
GS
V
t
=(10.4)V=0.6V
V
DS
=1.5V;(V
GS
V
t
)<V
DS
3
NonSaturationV
GS
V
t
=(10.4)V=0.6V
V
DS
=0V;(V
GS
V
t
)>V
DS
4
NonSaturationV
GS
V
t
=(10.4)V=0.6V
V
DS
=0.5V;(V
GS
V
t
)>V
DS
4
NonSaturationV
GS
V
t
=(1.50.4)V=1.1V
V
DS
=0.5V;(V
GS
V
t
)>V
DS
5
CutOffV
GS
=0V
6
SaturationV
GS
V
t
=(0.50.4)V=0.1V
V
DS
=0.5V;(V
GS
V
t
)<V
DS
7
SaturationV
GS
V
t
=(10.4)V=0.6V
V
DS
=1V;(V
GS
V
t
)<V
DS
9/10/2012
34
91
68
Mask
CommonmaterialusedformasksarePhotoresist,Polysilicon,Silicon
dioxide,Siliconnitride.
Tocreatemask:
(a)depositmaskmaterialoverentiresurface
(b)cutwindowsinthemasktocreateexposedareas
(c)depositdopant
(d)removeunrequiredmaskmaterial
Masksplaysimportantroleinprocesscalledselective
diffusions.
Theselectivediffusioninvolves
1. Patterningwindowsinamaskmaterialonthesurfaceofthe
wafer.
2. Subjectingtheexposedareastoadopantsource.
3. Removinganyunrequiredmaskmaterial.
9/10/2012
35
69
Photolithography
The Process of using an optical image and a photosensitive
film to produce a pattern on a substrate is photolithography
Photolithography depends on a photosensitive film called a
photo-resist.
Types of resist
Positive resist, a resist that become soluble when exposed
and forms a positive image of the plate.
Negative resist, a resist that lose solubility when
illuminated forms a negative image of the plate.
70
Photolithography
ptype body
Substrate
9/10/2012
36
71
Resistapplication
ptype body
Photolithography
72
Exposure
ptype body
Photolithography
9/10/2012
37
73
PositiveResist
ptype body
Etching
Photolithography
74
NegativeResist
ptype body
Etching
Photolithography
9/10/2012
38
Si(100)
PType
NMOSFabricationSteps
1.SelectionofSubstrate
2.Cleaning
3.Oxidation
Si(100)
PType
SiO
2
Si+O
2
SiO
2
(goodquality)
Si+2H
2
OSiO
2
+2H
2
(poorquality)
4.LithographywithMASK1
Si(100)
PType
SiO
2
+VEPhotoresist
UV
MASK1
A A
9/10/2012
39
PhotoresistdevelopmentandOxideEtching
Si(100)
PType
PhotoresistEtching
Si(100)
PType
GateOxidation
Si(100)
PType
PolySiliconDeposition
Si(100)
PType
SiH
4
Si+2H
2
9/10/2012
40
Si(100)
PType
PolySi
LithographyforGateElectrode
+VEPhotoresist
MASK2
UV
Si(100)
PType
PolyPatterning
PhotoresistCleaning
Si(100)
PType
9/10/2012
41
LithographyforSourceandDrainregion
Si(100)
PType
UV
MASK3
S D
Si(100)
PType
Oxideetching(HFCleaning)
Photoresistcleaning
Si(100)
PType
9/10/2012
42
Si(100)
PType
N
+
N
+
IonImplantation
Si(100)
PType
N
+
N
+
ThickOxideDeposition
LithographyandContactViaOpening
Si(100)
PType
N
+
N
+
UV
MASK4
S G D
9/10/2012
43
Si(100)
PType
N
+
N
+
MetallizationandPatterning
S
G
D
Bodyterminalisnotshown..
86
FabricationofCMOSDevices
Technologies used for CMOS fabrications include
N-well process
P-well process
Twin-tub process
Silicon on insulator.
9/10/2012
44
87
In order to have both types of transistors on the same substrate, the
substrate is divided into well regions (Shaded region in the
standard cells)
Two types of wells are available n well and p well
In a p substrate, an n well is used to create a local region of n type
substrate, wherein the designer can create p transistors
In a n substrate, a p well creates a local p type substrate region, to
accommodate the n transistors.
Hence, every p device is surrounded by an n well, that must be
connected to V
DD
via a V
DD
substrate contact.
Similarly, n devices are surrounded by p well connected to GND
using a GND substrate contact.
PWellsandNWells
88
PWellsandNWells
Ap transistorisbuiltonann substrateandann transistoris
builtonapsubstrate
P-well N-well
P substrate
contact
[P
+
]
N substrate
contact
[n
+
]
OUT
IN
G G
D S
n
+
n
+ p
+
p
+
9/10/2012
45
MASKforCMOSInverter
NWellCMOSInverter
1
SubstrateSelectionSi(100)
2
CleaningoftheSubstrate
3
Oxidation(1m)
4
Lithography(MASK1)
5
HF(Oxide)Cleaning&PREtching
6
NWellimplantation
7
OxideEtching
8
GateOxideDeposition
9
PolySiDeposition
10
LithographyandOxidePatterning
11
Lithography(MASK2)
12
PolySiPatterning
13
Lithography(MASK3)
14
15
Ionimplantation NMOS
16
Repeat12to14forPMOS
17
DepositionofThickOxide
18
9/10/2012
46
Si(100)
Ptype
90
2.CleaningofSubstrate
The nwell CMOS process starts with a moderately doped
(with impurity concentration typically less than 10
15
cm
3
)
Ptype silicon substrate.
3.Oxidation(1m)
Si(100)
P
type
SiO
2
90
9/10/2012
47
Lithography(MASK1)
Si(100)
P
type
SiO
2
PositivePhotoresist PositivePhotoresist
MASK1
UV
90
Si(100)
P
type
SiO
2
Si(100)
P
type
SiO
2
90
9/10/2012
48
Si(100)
P
type
SiO
2
90
NWellImplantation
Si(100)
P
type
SiO
2
NWell
Ntypeimpurityimplantation
OxideCleaning
Si(100)
P
type
NWell
GateOxidation
Si(100)
P
type
NWell
90
9/10/2012
49
Si(100)
P
type
NWell
90
Si(100)
P
type
NWell
Lithography(MASK2)
90
9/10/2012
50
Si(100)
P
type
NWell
Si(100)
P
type
NWell
90
Lithography(MASK3)
Si(100)
P
type
NWell
90
9/10/2012
51
Si(100)
P
type
NWell
Si(100)
P
type
NWell
90
IonImplantation
Si(100)
P
type
NWell
N
+
N
+
N
+
90
9/10/2012
52
Repeat12to14forPMOS
Si(100)
P
type
NWell
N
+
N
+
N
+
P
+
P
+
P
+
90
Si(100)
P
type
NWell
N
+
N
+
N
+
P
+
P
+
P
+
90
9/10/2012
53
Si(100)
P
type
NWell
N
+
N
+
N
+
P
+
P
+
P
+
90
Si(100)
P
type
NWell
N
+
N
+
N
+
P
+
P
+
P
+
V
SS
V
DD
90
9/10/2012
54
TwinTubCMOSFabrication
1
SelectionofSubstrate
2
3
EpitaxialLayer
4
Oxidation(1m)
5
Lithography(MASK1)
6
7
NWellimplantation
8
OxideEtching
9
Repeatsteps4to6
10
PWellimplantation
1
SubstrateSelectionSi(100)
2
3
Oxidation(1m)
4
Lithography(MASK1)
5
6
NWellimplantation
7
OxideEtching
8
GateOxideDeposition
9
PolySiDeposition
2.CleaningofSubstrate
The twintub CMOS process starts with a high resistive ntype
(100) silicon substrate.
Si(100)
Ntype
9/10/2012
55
EpitaxialLayerDeposition
Epitaxiallayer
Si(100)
Ntype
3.Oxidation(1m)
Epitaxiallayer
SiO
2
Si(100)
Ntype
9/10/2012
56
Lithography(MASK1)
SiO
2
PositivePhotoresist PositivePhotoresist
MASK1
UV
90
Si(100)
Ntype
SiO
2
90
Si(100)
Ntype
9/10/2012
57
SiO
2
Si(100)
Ntype
Si(100)
P
type
SiO
2
90
Si(100)
Ntype
9/10/2012
58
9/10/2012
S.K.Tiwari(Asst.Prof.ECEMITManipal) 115
NWellImplantation
SiO
2
NWell
Ntypeimpurityimplantation
Si(100)
Ntype
OxideCleaning
GateOxidation
NWell PWell
NWell PWell
Si(100)
Ntype
Si(100)
Ntype
9/10/2012
59
NWell PWell
Si(100)
Ntype
Lithography(MASK2)
NWell PWell
Si(100)
Ntype
9/10/2012
60
NWell PWell
NWell PWell
Si(100)
Ntype
Si(100)
Ntype
Lithography(MASK3)
NWell PWell
Si(100)
Ntype
9/10/2012
61
9/10/2012 S.K.Tiwari(Asst.Prof.ECEMITManipal) 121 90
NWell PWell
Si(100)
Ntype
IonImplantation
NWell PWell
N
+
N
+
N
+
Si(100)
Ntype
9/10/2012
62
NWell
N
+
P
+
P
+
P
+
PWell
N
+
N
+
P
+
Si(100)
Ntype
NWell
N
+
N
+
N
+
P
+
P
+
P
+
Si(100)
Ntype
PWell
N
+
N
+
P
+
9/10/2012
63
NWell
N
+
N
+
N
+
P
+
P
+
P
+
90
PWell
N
+
N
+
P
+
Si(100)
Ntype
NWell
N
+
N
+
N
+
P
+
P
+
P
+
V
SS
V
DD
90
PWell
N
+
N
+
P
+
Si(100)
Ntype
9/10/2012
64
LatchUp
Tendency of CMOS chips to
develop lowresistance paths
between V
DD
and V
SS
Called Latch
up
LatchUp
These BJTs form a siliconcontrolled
rectifier (SCR) with positive feedback and
virtually short circuit the power rail to
ground, thus causing excessive current
flows and even permanent device
damage.
PNP transistor whose base is formed by
the nwell with its basetocollector
current gain (
1
) as high as several
hundreds.
NPN transistor with its base formed by the
ptype substrate. The basetocollector
current gain
2
of this lateral transistor
may range from a few tenths to tens
9/10/2012
65
Latchup
Rwell representstheparasiticresistanceinthenwellstructure
withitsvaluerangingfrom1k to20k.
Rsub canbeashighasseveralhundredohms.
Unless the SCR is triggered by an external disturbance, the
collector currents of both transistors consist of the reverse
leakage currents of the collectorbase junctions and therefore,
their current gains are very low.
If the collector current of one of the transistors is temporarily
increased by an external disturbance, however, the resulting
feedback loop causes this current perturbation to be multiplied
by (
1

2
). This event is called the triggering of the SCR.
Latchup
Once triggered, each transistor drives the other transistor with
positive feedback, eventually creating and sustaining a low
impedance path between the power and the ground rails, resulting
in latchup. It can be seen that if the condition
9/10/2012
66
TechniquetoovercomeLatchup
Use p+ guardband rings connected to ground around nMOS
transistors and n+ guard rings connected to VDD around pMOS
transistors to reduce R and R
SUb
and to capture injected
minority carriers before they reach the base of the parasitic
BJTs.
Place substrate and well contacts as close as possible to the
source connections of MOS transistors to reduce the values of
R
well
and Rsub.
SOIDevices
SOIfabrication
Refer:PrinciplesofCMOSVLSIDesignAsystemperspective2
nd
Ed.ByNeilH.E.Weste and
KamranEshraghian Pageno.125129
9/10/2012
67
SOIfabrication
SOIfabrication
9/10/2012
68
SOIfabrication
SOIfabrication
9/10/2012
69
VLSIDesign
Inverters
ShailendraKumarTiwari
9/10/2012
70
Outline
Passtransistors
Transmissiongate
ResistiveLoadNMOSInverter
EnhancementLoadNMOSinverter
DepletionLoadNMOSinverter
CMOSInverter
PassTransistors(NMOS)
9/10/2012
71
PassTransistors(NMOS)
NMOS
NMOSPasstransistorpassesstronglogic0.
NMOSPasstransistorpassesweaklogic1.
9/10/2012
72
PassTransistors(PMOS)
PassTransistors(PMOS)
9/10/2012
73
PMOS
PMOSPasstransistorpassesweaklogic0.
PMOSPasstransistorpassesstronglogic1.
PassTransistor
SWITCH G INPUT (SOURCE) OUTPUT(DRAIN)
N - Switch
X Z
V
SS
STRONG 0
V
DD
WEAK 1
P - Switch
X Z
V
DD
STRONG 1
V
SS
WEAK 0
I/P O/P
G=1
G=0
G=0
G=1
Gate
G
D
Drain
S
Source
Gate
G
D
Drain
S
Source
9/10/2012
74
TransmissionGate
PMOSPasstransistorpassesstronglogic1.
NMOSPasstransistorpassesstronglogic0.
Inverters
9/10/2012
75
NMOSInverter
Generalcircuitstructureof
annMOS inverter.
Typicalvoltagetransfercharacteristic(VTC)of
arealisticnMOS inverter.
(Notinsyllabus)
9/10/2012
76
V
OH
: Maximum output voltage when the
output level is logic " 1"
V
OL
: Minimum output voltage when the output
level is logic "0"
V
IL
: Maximum input voltage which can be
interpreted as logic "0"
V
IH
: Minimum input voltage which can be
interpreted as logic " 1"
inverterthresholdvoltageV
TINV
pointwhere
V
in
=V
out
ontheVTC.
CalculationofV
OH
thedrivertransistoriscutoff
9/10/2012
77
CalculationofV
OL
CalculationofV
IL
9/10/2012
78
CalculationofV
IH
V
IH
isthelargerofthetwovoltagepointsonVTCatwhichthe
slopeisequalto(1).
CalculationofV
IH
9/10/2012
79
NoiseMargin
Where
9/10/2012
80
DepletionLoadNMOSInverter
This is an alternate form of the
NMOS inverter that uses an
depletionmode MOSFET load
device with gate and source terminal
connected.
Resistiveload inverter is not a suitable
candidate for most digital VLSI system
applications, because of the large area
occupied by the load resistor.
9/10/2012
81
When the input voltage Vin is smaller than the driver
threshold voltage V
T0
, the driver transistor is turned off and
does not conduct any drain current. Consequently, the load
device, which operates in the linear region, also has zero drain
current.
SubstitutingV
OH
forV
out
CalculationofV
OH
CalculationofV
OL
WeassumethattheinputvoltageV
in
oftheinverterisequaltoV
OH
=V
DD
Drivertransistorlinearregion
Depletiontypeloadsaturationregion
ThissecondorderequationinV
OL
canbesolvedbytemporarily
neglectingthedependenceofV
Tload
onV
OL
,asfollows.
9/10/2012
82
CalculationofV
IL
CalculationofV
IL
9/10/2012
83
CalculationofV
IH
CalculationofV
IH
9/10/2012
84
CMOSInverter
V
OH
: Maximum output voltage when the output level is logic " 1"
V
OL
: Minimum output voltage when the output level is logic "0"
V
IL
: Maximum input voltage which can be interpreted as logic "0"
V
IH
: Minimum input voltage which can be interpreted as logic " 1"
9/10/2012
85
RegionA
PMOS Nonsaturation Region
NMOS Cutoff
V
out
=V
DD
I
D
R
CPMOS
V
out
=V
DD
RegionBV
IL
PMOS Nonsaturation Region
NMOS SaturationRegion
TheslopeoftheVTCisequalto(1),
whentheinputvoltageisV=V
IL
.
9/10/2012
86
TosatisfythederivativeconditionatVILwedifferentiateboth
sideswithrespecttoVin.
Where
RegionCV
th
PMOS SaturationRegion
NMOS SaturationRegion
9/10/2012
87
Where
RegionDV
IH
PMOS SaturationRegion
NMOS NonsaturationRegion
9/10/2012
88
Where
whentheinputvoltageexceedsVDDthepMOS transistoris
turnedoff.Inthiscase,thenMOS transistorisoperatinginthe
linearregion,butitsdrainto sourcevoltageisequaltozero
because
Theoutputvoltageofthecircuitis
RegionEV
OL
9/10/2012
89
NoiseMargin
MOSSecondordereffect
BodyEffect.
Subthresholdregion
Channellengthmodulation
Mobilityvariation
FowlerNordheim tunneling
Drainpunchthrough
ImpactIonizationHotelectrons.
Refer:PrinciplesofCMOSVLSIDesignAsystemperspective2
nd
Ed.ByNeilH.E.Weste and
KamranEshraghian Pageno.53to58.
9/10/2012
90
Determination of pullup to pull down ratio
(Z
PU
/Z
PD
) for an NMOS inverter driven by
another NMOS inverter
Determination of pullup to pull down ratio for
an NMOS inverter driven by through one or
more pass transistor
ReferBasicVLSIDesign3
rd
Ed.by:DouglasA.Pucknenn andKamranEshraghian
PageNo.3738
ReferBasicVLSIDesign3
rd
Ed.by:DouglasA.Pucknenn andKamranEshraghian
PageNo.3841
Designingofarbitrarylogicusing
CMOS
ReferClassnotes
CMOSDIGITALINTEGRATED
CIRCUITS:Analysis andDesign3
rd
Ed.
McGrawHill.By:SUNGMO (STEVE)KANG
Chapter7

Vlsi

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Vlsi

Uploaded by

Copyright:

Available Formats

9/10/2012

You might also like