Chapter2 Handout

KIN TRC MY TNH
ET4270
TS. Nguyn c Minh
[Adapted from Computer Organization and Design, 4
th
Edition, Patterson & Hennessy, 2008, MK]
[Adapted from Computer Architecture lecture slides, Mary Jane Irwin, 2008, PennState University]
T chc lp
S tn ch 3 (3-1-1-6)
Ging vin TS. Nguyn c Minh
Vn phng C9-401
Email minhnd1@gmail,com
Website https://sites.google.com/site/fethutca/home
Username: ca.fet.hut@gmail.com
Pass: dungkhoiminh
Sch Computer Org and Design, 3
rd
Ed., Patterson &Hennessy, 2007
Digital Design and Computer Architecture, David Money Harris
Th nghim 3 bi
Bi tp Theo chng, bi xem trn trang web
HUST-FET, 13/02/2011 2 Gii thiu
im s
iu kin thi Lab
Bi thi gia k 30%
Bi tp 20% (Ti a 100 im)
Tin trnh 10%
Ti a: 100 im,
Bt u: 50 im
Tch ly, tr qua tr li cu hi trn lp v ng gp t chc lp
Bi thi cui k 70%
Lch hc
Thi gian:
T 14h00 n 17h20
L thuyt: 11 bui x 135 pht / 1 bui
Bi tp: 4 bui x 135 pht / 1 bui
Thay i lch (ngh, hc b) s c thng bo trn website
trc 2 ngy
Kt lun chng 1
H thng my tnh c xy dng t phn cp cc lp tru
tng. Cc chi tit trin khai lp di b che khut khi lp trn.
Kin trc tp lnh lp giao tip gia phn cng v phn mm
mc thp l lp tru tng quan trng trong h thng my tnh.
Phn cng my tnh gm 5 thnh phn: ng d liu, khi iu
khin, b nh, khi vo, v khi ra. 5 thnh phn kt ni vi
nhau bng h thng bus theo m hnh vonNeumann hoc m hnh
Havard.
Phng php nh gi hiu nng mt h thng my tnh l dng
thi gian thc hin 1 chng trnh. Thi gian thc hin chng
trnh c tnh bng cng thc:
HUST-FET, 13/02/2011 5 Chng 2. Ngn ng my tnh v cc php ton
c cpu
T CPI I T =
Ni dung
1. H m v biu din s trong my tnh
(nhc li)
2. Kin trc tp lnh
1. Yu cu chc nng my tnh vonNeumman
2. Yu cu chung ca kin trc tp lnh
3. Kin trc tp lnh MIPS
4. Bin dch
3. Cc php ton v cch thc hin trong
my tnh
H m c s r
Mt s biu din trong h m c s r gm m
ch s trc du phy v n ch s sau du
phy:
Trong
0 d
i
r-1 l cc ch s
d
m-1
: ch s c ngha ln nht
d
-n
: ch s c ngha nh nht
Gi tr ca D trong h c s 10:
=
=
1 m
n i
i
i
r d D
r n m m
d d d d d d d D ) , (
2 1 0 1 2 1
=
Cc h m thng dng
H c s 10: r = 10; 0 d
i
9
H c s 2: r = 2; d
i
e (0,1); d
i
c gi l cc bit
H c s 8: r = 8; 0 d
i
7
H c s 16: r = 16; d
i
e (0,,9,A,B,C,D,E,F)
My tnh dng h c s 2, v 16
Chuyn t thp phn sang nh phn
Bc 1 - Phn nguyn: Chia s cn i cho 2 ly phn
d; Ly thng chia tip cho 2 ly phn d; Lp li cho
n khi thng bng 0; Phn d cui cng l bit c gi
tr ln nht (MSB), phn d u tin l bit c gi tr nh
nht (trc du phy)
Bc 2 - Phn thp phn: Nhn s cn i vi 2, ly
phn nguyn ca tch; Ly phn thp phn ca tch nhn
tip vi 2, ly phn nguyn; Lp li n khi tch bng 0
hoc tch b lp li; Phn nguyn u tin l bit u tin,
phn nguyn cui cng l bt cui cng (sau du phy).
Chuyn t nh phn sang h 16
Nhm s thp phn thnh cc nhm 4 bt, ln lt t
phi sang tri.
Nhm cui cng c th c s bit nh hn 4
Chuyn mi nhm 4 bt thnh 1 ch s h 16
) , , , , , , , , , , , (
0 1 1 4 /
0 1 2 3 4 5 6 7 4 3 2 1

h h h
m m m m
b b b b b b b b b b b b
m

H 2 H 16 H 2 H 16 H 2 H 16 H 2 H 16
0001 1 0101 5 1001 9 1101 D
0010 2 0110 6 1010 A 1110 E
0011 3 0111 7 1011 B 1111 F
0100 4 1000 8 1100 C
V d 2.1 Chuyn i h m
Chuyn i cc s sau gia cc c s 10, 2 v 16
(241,625)
10
(1101 0101,1001)
2
(4A,3F)
16
Biu din s nguyn khng du
Hex Binary Decimal
0x00000000 00000 0
0x00000001 00001 1
0x00000002 00010 2
0x00000003 00011 3
0x00000004 00100 4
0x00000005 00101 5
0x00000006 00110 6
0x00000007 00111 7
0x00000008 01000 8
0x00000009 01001 9
0xFFFFFFFC 11100
0xFFFFFFFD 11101
0xFFFFFFFE 11110
0xFFFFFFFF 11111 2
32
- 1
2
32
- 2
2
32
- 3
2
32
- 4
2
32
- 1
1 1 1 . . . 1 1 1 1 bit
31 30 29 . . . 3 2 1 0 v tr
2
31
2
30
2
29
. . . 2
3
2
2
2
1
2
0
trng s
1 0 0 0 . . . 0 0 0 0 - 1
Cc s dng khng
cn bt du
Khong biu din: [0, 2
m
-1]
Biu din s nguyn bng 1 bt du v ln
Trong :
Bt MSB b
m-1
l bt du; b
m-1
= 0 biu din s dng, b
m-1
= 1
biu din s m
Cc bt cn li biu din 1 s nh phn khng du
C 2 biu din s 0: 100 (-0) v 000(+0)
Khong biu din [-(2
m-1
-1), 2
m-1
-1]
=

=

2
0
0 1 , 2 1
2 ) 1 ( ) , , , (
1
m
i
i
i
b
m m
b b b b b
m
Biu din s nguyn bng m b 2

Trong :
Bt MSB b
m-1
l bt du; b
m-1
= 0 biu din s dng, b
m-1
= 1
biu din s m
Cc bt cn li biu din gi tr ca s dng m b 2
C 1 biu din s 0: 000
Khong biu din [-2
m-1
, 2
m-1
-1]
Quy tc tm biu din b 2, m bt :
i s dng sang m nh phn, thm cc bt 0 m bt. (Bt
ln nht l bt du = 0)
Tm m b 1 bng cch o cc bt
M b 2 = m b 1 + 1

+ =
2
0
1
1 bit m 2, b 0 1 , 2 1
2 2 ) , , , (
m
i
i
i
m
m m m
b b b b b b
Biu din s nguyn bng m b 2
Quy tc tm biu din b 2, 4 bt :
1000 -8
1001 -7
1010 -6
1011 -5
1100 -4
1101 -3
1110 -2
1111 -1
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7 =2
3
- 1
=-(2
3
- 1)
=-2
3
Biu din s nguyn m lch (bias)
Trong : bias l lch v thng bng 2
m-1
Khng c bit du
Khong biu din: [-2
m-1
, 2
m-1
-1]
bias b b b b b
m
i
i
i ,bias m m
=
=

1
0
2 0 1 , 2 1
2 ) , , , (
V d 2.2 Biu din s nguyn
Chuyn cc s sau sang dng m b 1, m b 2 v m
2 lch 127 di 8 bt
123
-8
-3
-126
129
-129
Biu din s thc chun IEEE-754
chnh xc n dng 32 bit nh phn
Bao gm:
1 bt du s: 0 s dng; 1 s m
8 bt biu din s m theo m lch 127:
23 bt biu din phn ln c chun ha 1 M < 2
M = (1,f
22
f
21
f
0
)
2
0 22 23 30 31
S M exp: s nguyn lch 127 ln chun ha M
M R
s
IEEE
=
exp
754
2 ) 1 (
127 2 ) ( exp
7
0
127 , 2 0 6 7
= =

= i
i
i
bias
e e e e
s
e
7
e
6
e
0
f
22
f
21
f
0
Biu din cc s c bit
S m lch 127 ln S c biu din
0 0 0
1 to 254 Bt k S chun ha
255 0
255 S khc 0 NaN
0 S khc 0 S khng chun ha
Khong biu din
chnh xc n chnh xc kp
Machine epsilon
chnh xc
2
-23
or 1.192 x 10
-7
2
-52
or 2.220 x 10
-16
Smallest positive
S dng nh
nht
2
-126
or 1.175 x 10
-38
2
-1022
or 2.225 x 10
-308
Largest positive
S dong ln
nht
(2- 2
-23
) 2
127
or 3.403 x
10
38
(2- 2
-52
) 2
1023
or 1.798 x
10
308
Decimal
Precision
chnh xc
thp phn
6 significant digits
6 ch s sau du phy
15 significant digits
15 ch s sau du phy
V d 2.3 Biu din s thc dng IEEE-754
i cc s sau thnh biu din s thc du phy ng
chnh xc n
125,50
-56,25
i cc biu din s thc du phy ng chnh xc
n sau thnh s thc h 10
1 1101 1001 110000 (tng cng 32 bt)
0 1001 1101 101000 (tng cng 32 bt)
Biu din k t, ch s
M ASCII: 7 bit hoc 8 bt
M Unicode: 16 bt
M BCD
b3b2b1b0 000 001 010 011 100 101 110 111
0000 NUL DLE SP 0 @ P p
0001 SOH DC1 ! 1 A Q a q
0010 STX DC2 2 B R b r
0011 ETX DC3 # 3 C S c s
0100 EOT DC4 $ 4 D T d t
0101 ENQ NAK % 5 E U e u
0110 ACK SYN & 6 F V f V
0111 BEL ETB 7 G W g w
1000 BS CAN ( 8 H X h x
1001 HT EM ) 9 I Y i y
1010 LF SUB * : J Z j z
1011 VT ESC + ; K [ k {
1100 FF FS , < L \ l |
1101 CR GS - = M ] m }
1110 SO RS . > N ^ n ~
1111 SI US / ? O _ o DEL
Decimal
digit
BCD
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
My tnh vonNeumann: Hot ng c bn
Np ch th t b nh chng trnh
Xc nh hnh ng v kch thc ch
th
nh v v np d liu ton hng
Tnh gi tr kt qu hoc trng thi
Lu d liu vo b nh s dng
sau
Xc nh lnh tip theo
Instruction
Fetch
Instruction
Decode
Operand
Fetch
Execute
Result
Store
Next
Instruction
My tnh vonNeumann: Yu cu chc nng
Yu cu nguyn tc:
My tnh hot ng theo cc ch th my
Ch th c biu din bng cc s khng phn bit
vi d liu
Chng trnh c lu tr trong b nh
Khi nim v chng trnh c lu tr (eng.
stored-program):
Chng trnh c cung cp nh l 1 tp cc s
nh phn.
My tnh c th chy cc chng trnh to sn
nu chng tng thch vi 1 kin trc tp lnh
S lng t cc kin trc tp lnh chun
Xc nh yu cu chc nng: Kin trc tp lnh
Accounting prg
(machine code)
C compiler
(machine code)
Payroll
data
Source code in
C for Acct prg
Memory
Kin trc tp lnh: nh gi
Thng s khi thit k:
C th trin khai c khng? Mt bao lu? Gi thnh?
C th lp trnh c khng? C d bin dch?
Thng s tnh:
ln chng trnh trong b nh?
Thng s ng:
S lng ch th c thc hin? S lng byte cn np
chy chng trnh?
S chu k ng h cn cho mi ch th?
Tc ng h?
Thng s tt nht: Thi gian thc hin!
CPI
Inst. Count Cycle Time
Kin trc tp lnh: Yu cu
Kch thc v kiu d liu
Php ton: loi no c h tr
nh dng v m ha ch th:
Ch th c gii m th no?
V tr ton hng v kt qu
S lng ton hng?
Gi tr ton hng c lu u?
Kt qu c lu v tr no?
Cc ton hng b nh c nh v th no?
Ch th tip theo: nhy, iu kin, r nhnh
D liu: Kiu & kch thc
Byte
Hal fword
Word
Doubleword
Byte = 8 bits
Word = 4 bytes
Doubleword = 8 bytes
Quadword (16 bytes) t c s dng
Halfword = 2 bytes
S dng lu d liu du
phy ng
Kch thc v kiu d liu
S lng ton hng?
Kt qu c lu v tr no?
Cc php ton
Load/Store: c v ghi b nh
Computational: Tnh ton s hc v logic, so snh
C lnh nhn chia hay khng?
Cc lnh so snh no?
Jump and Branch: Nhy v r nhnh
Floating Point: Lnh du phy ng
coprocessor
Memory Management: Qun l b nh
Special: Lnh c bit
Cc php ton
Dch chuyn d liu c (t b nh), Ghi (ti b nh)
Chuyn gia cc nh
Chuyn gia cc thanh ghi
Vo (t thit b I/O), Ra (ti thit b I/O)
push, pop (t/ti ngn xp)
S hc S nguyn (nh phn, thp phn), S thc du
phy ng. Cng, tr, nhn chi
Dch Dch tri/phi, Quay tri/phi
Logic not, and, or, set, clear
iu khin (nhy, r nhnh) Khng iu kin, C iu kin
Lin kt vi th tc call, return
Ngt trap, return
ng b test & set
Chui search, translate
ha (MMX) Php ton song song
Cc php ton
Cc php ton n gin c s dng nhiu v
chim a s trong cc ch th ca chng trnh
Cn tp trung vo cc php ton:
load, store
move register-register
add, subtract, and, shift
compare equal, compare not equal
branch, jump, call, return
Kch thc v kiu d liu
S lng ton hng?
Kt qu c lu v tr no?
nh dng lnh: cc trng
M lnh ch ra nhim v (chc nng) ca lnh
Tham chiu ton hng ngun ch ra cc ton hng c
x l bi lnh
Tham chiu kt qu ch ra ni lu tr kt qu ca lnh
Tham chiu lnh k tip ch ra cch tnh ton hoc ni
lu tr lnh s c thc hin tip theo
Thng khng c ch ra r rng trong lnh m c ngm coi
l lnh lin sau lnh hin ti trong chui lnh
Trong mt s loi lnh, a ch ca lnh tip theo s c ch ra
Kch thc v kiu d liu
S lng ton hng?
Kt qu c lu v tr no?
S lng ton hng (1)
3 ton hng:
a ch ca 2 ton hng, v kt qu u c cha trong m lnh
OP A, B, C A B OP C
D bin dch t ngn ng bc cao sang lnh my
Gi tr ton hng lu trong cc thanh ghi
Lnh ch ra ch s thanh ghi
2 ton hng: (gi tr trong cc thanh ghi, hoc a ch nh)
Mt a ch c dng cho ton hng v kt qu
OP A, B A A OP B
Bin dch i hi thm lnh v thanh ghi lu tr tm thi
Gi tr ton hng lu trong thanh ghi hoc trong nh.
Lnh ch ra ch s thanh ghi hoc a ch nh
S lng ton hng (2)
Mt ton hng: lnh tch ly (accumulator)
Mt ton hng v kt qu c quy nh ngm c lu trong 1 thanh
ghi c bit (Accumulator AC)
Ton hng cn li lu trong thanh ghi
OP A AC AC OP A
Thng dng trong b x l tn hiu s
Khng ton hng: lnh ngn xp (stack)
Tt c cc a ch c quy nh ngm
Kt qu v ton hng th hai nm a ch nh ca stack: T
Ton hng th nht nm a ch th 2 ca stack: T-1
OP T T-1 OP T
S lng ton hng quyt nh: di lnh, I v CPI
V d 2.4: So snh s lng ton hng
Xt cu lnh ngn ng bc cao: Y = (A B)/(C+D*E)
Bin dch thnh hp ng:
3 a ch
SUB Y, A, B
MUL T, D, E
ADD T, T, C
DIV Y, Y, T
2 a ch
MOV Y, A
SUB Y, B
MOV T, D
MUL T, E
ADD T, C
DIV Y, T
1 a ch
LOAD D
MUL E
ADD C
STORE Y
LOAD A
SUB B
DIV Y
STORE Y
0 a ch
Chuyn sang dng ton t sau:
Y = AB-CDE*+/
PUSH A
PUSH B
SUB
PUSH C
PUSH D
PUSH E
MUL
ADD
DIV
POP Y
Kch thc v kiu d liu
S lng ton hng?
Kt qu c lu v tr no?
Gi tr ton hng Ch a ch
Register Add R4,R3
R4 R4+R3
Immediate Add R4,#3
R4 R4+3
Displacement Add R4,100(R1)
R4 R4+Mem[100+R1]
Register indirect Add R4,(R1)
R4 R4+Mem[R1]
Indexed / Base Add R3,(R1+R2)
R3 R3+Mem[R1+R2]
Direct or absolute Add R1,(1001)
R1 R1+Mem[1001]
Memory indirect Add R1,@(R3)
R1 R1+Mem[Mem[R3]]
Auto-increment Add R1,(R2)+
R1 R1+Mem[R2]; R2 R2+d
Auto-decrement Add R1,(R2)
R2 R2d; R1 R1+Mem[R2]
Scaled
Add R1,100(R2)[R3]
R1 R1+Mem[100+R2+R3*d]
Ch a ch tc th (Immediate)
Gi tr ca ton hng (ton hng) l trng ton hng
ca cu lnh
Operand = Operand field
Khng tham chiu n b nh np d liu
Ton hng lun l hng s trong khi chy chng trnh
Tc cao
Khong gi tr ca ton hng nh
V d: ADD R4, #3: R4 R4+3
Operand Opcode Instruction
Ch a ch thanh ghi (Register)
Ton hng c cha trong thanh ghi ch ra bi trng
a ch
Operand = R[n] (Rn)
Khng truy cp b nh
Thc thi nhanh
Trng a ch dng t bit
Lnh ngn hn
Np lnh nhanh hn
S lng thanh ghi b hn ch
Register index: n Opcode Instruction Register file
Operand
Ch a ch dch chuyn (Displacement)

Trng a ch cha gm 2 phn c s v lch
A cha gi tr c s dng trc tip
n cha ch s ca thanh ghi s dng gin tip
A, Rn c th l c s v lch hoc ngc li
a ch ca ton hng EA = R[n] + A
Operand = MEM[EA]
Register index: n Opcode Instruction
Register file
Pointer to operand
Operand
Memory
Offset: A
Ch a ch tng i (Relative)
Phin bn ca a ch dch chuyn
R = PC, c ngm nh trong m lnh (opcode)
operand = MEM[A + PC]
Ly ton hng t a ch cch v tr chng trnh hin ti
A nh
Dng truy cp cc hng s, bin, a ch a phng
Opcode Instruction
Register file
PC
Operand
Memory Address A
a ch b nh
a ch b nh:
a ch byte: nh a ch cho cc nh kch thc 1 byte
a ch word: nh a ch cho cc nh kch thc 1 word
2 cu hi khi thit k ISA:
Cc kiu d liu ln hn byte c lu tr th no?
a ch khc byte c tnh ton th no?
Cc kiu d liu ln c c lu tr v tr a ch byte bt k
hay khng? (Vn alighment)
31 23 15 7 0
x x+1 x+2 x+3 x+4 byte address
word
a ch b nh: Endianess v Alignment
Big Endian:
a ch word = a ch ca byte c ngha ln nht trong word
(Most Significant Byte)
IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA
Litle Endian:
a ch word = a ch ca byte c ngha nh nht trong word
(Least Significant Byte)
Intel 80x86, DEC Vax, DEC Alpha
Alignment:
D liu c lu tr a ch
byte chia ht cho kch thc.
Big Endian:
Litle Endian:
Alignment:
D liu c lu tr a ch
Big Endian:
Litle Endian:
Alignment:
D liu c lu tr a ch
0 1 2 3
Aligned
Not
Aligned
S dng ch a ch
Displacement: 42% avg, 32% to 55%
Immediate: 33% avg, 17% to 43%
Register deferred (indirect): 13% avg, 3% to 24%
Scaled: 7% avg, 0% to 16%
Memory indirect: 3% avg, 1% to 6%
Misc: 2% avg, 0% to 3%
75% displacement & immediate
88% displacement, immediate & register indirect
88%
75%
Thng k ch a ch
Kch thc trng ton hng trc tip
8 bit: 50-60%
16 bit; 75%-80%
Cc ch a ch quan trng
Dch chuyn (Displacement)
Trc tip (Immediate)
Thanh ghi gin tip (Register indirect)
Kch thc lch trong ch a ch: 12-16
bt
Kch thc ton hng trc tip: 8-16 bt
nh dng ch th
di ch th:
C nh
Thay i
Lai: gm 1 vi loi ch th c di c nh khc nhau
Khi kch thc chng trnh quan trng: dng ch di
thay i
Khi hiu nng quan trng: dng di c nh
Variable:
Fixed:
Hybrid:
Mt s kin trc tp lnh

Kin trc RISC
Reduce Instruction Set Computer
DEC Alpha, AMD 29k, ARC, ARM, Atmel AVR, MIPS, PA-RISC,
Power (PowerPC), SuperH, v SPARC.
nh dng lnh v di lnh c nh, n gin
D gii m lnh
Cc thanh ghi chung mc ch c th s dng trong nhiu ng cnh
D thit k phn mm bin dch
C th cn cc thanh ghi du phy ng ring bit
Ch a ch n gin
Cc ch a ch phc tp c thc hin thng qua chui lnh s
hc v lnh np/ghi
t h tr cc loi d liu phc tp
Kin trc CISC
Complex Instruction Set Computer
System/360, z/Architecture, PDP-11, VAX, Motorola 68k, v x86.
Lnh c di thay i, phc tp
C th bao gm 1 vi php ton nh
Gn ngn ng lp trnh bc cao
Nhiu ch a ch phc tp
H tr cc loi d liu phc tp
CISC vs. RISC
RISC CISC
- Tp ln cc thanh ghi
- Tp lnh n gin
- Tp trung trao i d liu gia thanh ghi
- Cc lnh thc hin trong mt chu k my
- Cc lnh LOAD/STORE n gin truy
cp b nh
- Gii hn ch a ch
- T m c chiu di c nh
- Gii hn s thanh ghi
- Tp lnh phc tp
- Nhn mnh vo cc hot ng truy cp
b nh
- Lnh c th c thc hin trong nhiu
chu k my
- Mt lnh c th tng ng vi nhiu
lnh ca RISC
- Nhiu ch a ch
- M lnh c chiu di thay i ty vo
tng lnh
CISC vs. RISC
RISC CISC
- M lnh thc hin nhanh
- n v iu khin n gin
- Gii m nhanh
- X l song song ng ng hiu sut cao
- Thit k, pht trin v kim tra nhanh
- H tr trnh dch tng cng s ti u
- Gim cc li r nhnh ca ng ng
- Tng tc truyn tham s cho cc th tc
- Ngn ng lp trnh assembly mnh
- Gim cc yu cu khi thit k trnh dch
- Cc tnh nng vi du phy ng mnh
- Tng kh nng ca cache
V d 2.4. So snh hiu nng RISV vs. CISC
Kin trc tp lnh ISA c 2 lp ch th phc tp (C) v n gin (S).
Trong 1 chng trnh thi gian thc hin ch th S chim 95%. trin
khai ISA bng kin trc RISC ta s trin khai cc ch th S bng phn
cng v ch th C bng phn mm (dng on ch th S v coi nh 1 ch
th gi C). So snh vi kin trc CISC, cc ch th S s c thc hin
nhanh hn 20% v cc ch th CISC b chm i 3 ln. Kin trc no c
hiu nng cao hn v cao hn bao nhiu ln?
Kin trc tp lnh MIPS
nh dng ch th:
32 bit
3 loi nh dng:
R-ch th thanh ghi: 2 ton hng ngun thanh ghi, 1 ton hng
ch thanh ghi
I-ch th trc tip: 1 ton hng ngun thanh ghi, 1 ton hng
ngun trc tip, 1 ton hng ch thanh ghi
J-ch th nhy: 1 ton hng ngun trc tip
op
op
op
rs
rt
rd sa funct
rs
rt
immediate
jump target
R format
I format
J format
Nguyn tc thit k MIPS (RISC)
Tnh n gin quan trng hn tnh quy tc(Simplicity favors regularity)
Ch th kch thc c nh (32 bit)
t nh dng ch th (3 loi nh dng)
M lnh v tr c nh (6 bit u)
Nh hn th nhanh hn
S ch th gii hn
S thanh ghi gii hn
S ch a ch gii hn
Tng tc cc trng hp thng dng
Cc ton hng s hc ly t thanh ghi (my tnh da trn c ch load-
store)
Cc ch th c th cha ton hng trc tip
Thit k tt i hi s tha hip
3 loi nh dng ch th
Ch th s hc ca MIPS
HUST-FET, 13/02/2011 59
M hp ng ca ch th s hc
add $t0, $s1, $s2
sub $t0, $s1, $s2
Mi ch th s hc thc hin mt php ton
Mi ch th cha chnh xc ba ch s ca cc thanh ghi
trong tp thanh ghi ca ng d liu ($t0,$s1,$s2)
destination source1 op source2
nh dng ch th loi thanh ghi (R format)
0 17 18 8 0 0x22
Cc trng trong ch th MIPS
Cc trng trong 1 ch th MIPS c t tn:
op rs rt rd shamt funct
op 6-bits m lnh xc nh php ton (opcode)
rs 5-bits ch s thanh ghi cha ton hng ngun 1 trong
tp thanh ghi
rt 5-bits ch s thanh ghi cha ton hng ngun 2 trong
tp thanh ghi
rd 5-bits ch s thanh ghi s lu kt qu trong tp thanh ghi
shamt 5-bits s lng dch (cho ch th dch)
funct 6-bits m chc nng thm cho phn m lnh
Tp thanh ghi ca MIPS
Register File
src1 addr
src2 addr
dst addr
write data
32 bits
src1
data
src2
data
32
locations
32
5
32
5
5
32
write control
Gm 32 thanh ghi 32-bit
2 cng c
1 cng ghi
Thanh ghi:
Nhanh hn b nh chnh
- Nhiu thanh ghi s chm hn
(VD., 1 tp gm 64 thanh ghi word s
chm hn tp gm 32 thanh ghi khong 50%)
- S lng cng c ghi nh hng bc 2 n tc
D bin dch
- VD., (A*B) (C*D) (E*F) c th thc hin php nhn theo th
t bt k, khng ging nh ngn xp
Cha bin chng trnh
- ci thin ln m chng trnh
Cc thanh ghi MIPS
Tn Ch s Cng dng Preserve
on call?
$zero 0 constant 0 (hardware) n.a.
$at 1 reserved for assembler n.a.
$v0 - $v1 2-3 returned values no
$a0 - $a3 4-7 arguments yes
$t0 - $t7 8-15 temporaries no
$s0 - $s7 16-23 saved values yes
$t8 - $t9 24-25 temporaries no
$gp 28 global pointer yes
$sp 29 stack pointer yes
$fp 30 frame pointer yes
$ra 31 return addr (hardware) yes
Truy cp b nh
2 ch th dch chuyn d liu truy cp b nh
o lw $t0, 4($s3) #c 1 t t b nh
o sw $t0, 8($s3) #ghi 1 t vo b nh
D liu c c vo (lw) hoc ghi ra t (sw) 1 thanh ghi
trong tp thanh ghi 5 bit ch s thanh ghi
32 bit a ch b nh c to ra bng cch cng gi tr
thanh ghi c s (base register) vi gi tr offset
Trng offset rng 16 bit s gii hn cc nh trong khong 2
13
hay 8,192 words (2
15
hay 32,768 bytes) tnh t gi tr ca thanh
ghi c s
nh dng lnh truy cp b nh
nh dng ch th Load/Store (nh dng I):
lw $t0, 24($s3)
35 19 8 24
10
Memory
data word address (hex)
0x00000000
0x00000004
0x00000008
0x0000000c
0xf f f f f f f f
$s3
0x12004094
24
10
+ $s3 =
. . . 0001 1000
+ . . . 1001 0100
. . . 1010 1100 =
0x120040ac
0x120040ac
$t0
V d 2.5. Truy cp bng (array)
HUST-FET, 13/02/2011 65
Cho A[ ] = l 1 mng bt u ti a ch c s lu trong
thanh ghi $s3;
Bin h c gn vi thanh ghi $s2;
Dch: A[5] = h + A[8]
Thnh m hp ng MIPS:
lw $t0, 32 ($s3) # $t0 A[8]
add $t0, $s2, $t0 # $t0 h+$t0
sw $t0, 20 ($s3) # A[5] $t0
OP rs
rt
immediate
I-type
8
7
6
5
4
3
2
1
V d 2.6. Truy cp mng vi ch s thay i
HUST-FET, 13/02/2011 66
A[ ] = array with base address in $s3;
variables g, h, i associated with registers $s1, $s2, $s4
Compile: g = h + A[i]
into MIPS instructions:
add $t1, $s4, $s4 # $t1 i+i = 2i
add $t1, $t1, $t1 # $t1 2i+2i = 4i
add $t1, $t1, $s3 # $t1 address of A[i]
lw $t0, 0 ($t1) # $t0 A[i]
add $s1, $s2, $t0 # $s1 h + A[i]
Lu tr byte: Endianess (Nhc li)
HUST-FET, 13/02/2011 67
Big Endian: leftmost byte is word address
Little Endian: rightmost byte is word address
Thanh ghi lsb
3 2 1 0
a ch:little endian byte 0
0 1 2 3
a ch:big endian byte 0
msb
c v ghi byte
HUST-FET, 13/02/2011 68
MIPS cc lnh c bit dch chuyn bytes
lb $t0, 1($s3) #load byte from memory
sb $t0, 6($s3) #store byte to memory
op rs rt 16 bit number
Cc byte 8bit no c c v ghi?
Lnh c a byte c c vo 8 bit ngoi cng bn
phi t b nh vo thanh ghi ch
- Cc bit khc ca thanh ghi?
Lnh ghi ly 8 bit ngoi cng bn phi ca thanh ghi
ngun v ghi vo b nh
- Gi cc byte khc trong t nh khng thay i
V d 2.7. c ghi byte
HUST-FET, 13/02/2011 69
Cho on m sau v trng thi b nh. Xc nh
trng thi b nh sau khi thc hin on m
add $s3, $zero, $zero
lb $t0, 1($s3)
sb $t0, 6($s3)
Memory
0x 0 0 9 0 1 2 A 0
Data Word
Address (Decimal)
0
4
8
12
16
20
24
0x F F F F F F F F
0x 0 1 0 0 0 4 0 2
0x 1 0 0 0 0 0 1 0
0x 0 0 0 0 0 0 0 0
0x 0 0 0 0 0 0 0 0
0x 0 0 0 0 0 0 0 0
Gi tr lu trong $t0?
iu g xy ra khi my tnh l loi little
Endian?
T no c ghi vo b nh v tr
no?
c ghi na t
HUST-FET, 13/02/2011 70
MIPS also provides special instructions to move
half words
lh $t0, 1($s3) #load half word from memory
sh $t0, 6($s3) #store half word to memory
op rs rt 16 bit number
What 16 bits get loaded and stored?
load half word places the half word from memory in the
rightmost 16 bits of the destination register
- what happens to the other bits in the register?
store half word takes the half word from the rightmost
16 bits of the register and writes it to the half word in
memory
- leaving the other half word in the memory word unchanged
Lnh trc tip
addi $sp, $sp, 4 #$sp = $sp + 4
slti $t0, $s2, 15 #$t0 = 1 if $s2<15
nh dng m my (nh dng I):
Cc hng s trong chng trnh thng c gi tr nh
Cc phng php lu tr v s dng hng s:
Lu cc hng thng dng trong b nh v c chng
To 1 thanh ghi kt ni cng (nh $zero) lu hng s
Dng cc lnh c bit c cha hng s
0x0A 18 8 0x0F
Hng s c cha trong lnh!
nh dng trc tip gii hn gi tr trong khong +2
15
1 to -2
15
Lnh dch
Shifts move all the bits in a word left or right
sll $t2, $s0, 8 #$t2 = $s0 << 8 bits
srl $t2, $s0, 8 #$t2 = $s0 >> 8 bits
Instruction Format (R format)
Such shifts are called logical because they fill with
zeros
Notice that a 5-bit shamt field is enough to shift a 32-bit value
2
5
1 or 31 bit positions
0 16 10 8 0x00
Lnh logic
There are a number of bit-wise logical operations in the
MIPS ISA
and $t0, $t1, $t2 #$t0 = $t1 & $t2
or $t0, $t1, $t2 #$t0 = $t1 | $t2
nor $t0, $t1, $t2 #$t0 = not($t1 | $t2)
Instruction Format (R format)
andi $t0, $t1, 0xFF00 #$t0 = $t1 & ff00
ori $t0, $t1, 0xFF00 #$t0 = $t1 | ff00
Instruction Format (I format)
0 9 10 8 0 0x24
0x0D 9 8 0xFF00
S dng cc hng s ln
HUST-FET, 13/02/2011 74
a 1 hng s 32 bit vo 1 thanh ghi
S dng 2 lnh:
Lnh np vo phn cao "load upper immediate
lui $t0, 0xaaaa
Lnh np vo phn thp:
ori $t0, $t0, 0xaaaa
16 0 8 1010101010101010
1010101010101010
0000000000000000 1010101010101010
0000000000000000
1010101010101010 1010101010101010
Lnh iu khin dng chng trnh
Lnh r nhnh c iu kin:
bne $s0, $s1, Lbl #go to Lbl if $s0=$s1
beq $s0, $s1, Lbl #go to Lbl if $s0=$s1
Ex: if (i==j) h = i + j;
bne $s0, $s1, Lbl1
add $s3, $s0, $s1
Lbl1: ...
nh dng lnh (nh dng I):
0x05 16 17 16 bit offset
a ch n c xc nh nh th no ?
Xc nh a ch r nhnh n
HUST-FET, 13/02/2011 76
S dng 1 thanh ghi (ging nh lw v sw) cng vi 16-bit offset
Thanh ghi a ch lnh PC (Instruction Address Register )
- Vic s dng PC c t ng bao hm trong lnh
- PC c cp nht (PC+4) khi lnh c np v vy khi tnh ton n cha gi
tr a ch ca lnh k tip
gii hn khong cch r nhnh trong khong -2
15
n +2
15
-1 (word) lnh
k t lnh sau lnh r nhnh. Tuy nhin phn ln cc r nhnh l a
phng.
PC
Add
32
32
32
32
32
offset
16
32
00
sign-extend
Trng 16 bit thp ca lnh r nhnh
branch dst
address
?
Add
4
32
So snh h tr lnh r nhnh
HUST-FET, 13/02/2011 77
C lnh beq, bne, cc loi iu kin khc? (VD., r nhnh
nu nh hn)? Cn 1 lnh so snh khc: slt
Set on less than:
slt $t0, $s0, $s1 # if $s0 < $s1 then
# $t0 = 1 else
# $t0 = 0
Instruction format (R format):
Cc phin bn khc ca slt
slti $t0, $s0, 25 # if $s0 < 25 then $t0=1 ...
sltu $t0, $s0, $s1 # if $s0 < $s1 then $t0=1 ...
sltiu $t0, $s0, 25 # if $s0 < 25 then $t0=1 ...
0 16 17 8 0x24
S dng slt
HUST-FET, 13/02/2011 78
Dng slt, beq, bne, v gi tr 0 trong thanh ghi $zero
to ra cc iu kin r nhnh khc
less than blt $s1, $s2, Label
less than or equal to ble $s1, $s2, Label
greater than bgt $s1, $s2, Label
great than or equal to bge $s1, $s2, Label
Cc lnh r nhnh c thm vo tp lnh nh cc lnh
gi, c nhn dng v m rng bng trnh dch
assembler
Trnh dch assembler cn thanh ghi ring ($at)
slt $at, $s1, $s2 #$at set to 1 if
bne $at, $zero, Label #$s1 < $s2
Lnh nhy khng iu kin
HUST-FET, 13/02/2011 79
Lnh nhy khng iu kin:
j label #go to label
nh dng lnh (J Format):
0x02 26-bit address
PC
4
32
26
32
00
t trng 26 bits thp ca lnh nhy
Nhy n a ch xa
HUST-FET, 13/02/2011 80
Khi a ch nhy n xa hn, v khng th biu din
bng 16 bits?
Phn mm assembler h tr n chn 1 lnh nhy khng
iu kin n a ch nhy n v o iu kin r nhnh
beq $s0, $s1, L1
tr thnh
bne $s0, $s1, L2
j L1
L2:
Nhy n a ch thay i
HUST-FET, 13/02/2011 81
Cc ngn ng bc cao c cc lnh nh case
hay switch cho php la chn trong nhiu
trng hp ph thuc vo 1 bin
Lnh:
jr $t1 #go to address in $t1
M my:
op rs funct
0 9 0 0 0 8 = 0x08
R format
Lnh case (switch) ngn ng bc cao
HUST-FET, 13/02/2011 82
switch (k) {
case 0: h=i+j; break; /*k=0*/
case 1: h=i+h; break; /*k=1*/
case 2: h=i-j; break; /*k=2*/
Gi s 3 t lin tip trong b nh bt u t a ch lu
trong $t4 cha gi tr ca cc nhn L0, L1, v L2 v k
lu trong $s2
$t4
L2
L1
L0
Memory
add $t1, $s2, $s2 #$t1 = 2*k
add $t1, $t1, $t1 #$t1 = 4*k
add $t1, $t1, $t4 #$t1 = addr of JumpT[k]
lw $t0, 0($t1) #$t0 = JumpT[k]
jr $t0 #jump based on $t0
L0: add $s3, $s0, $s1 #k=0 so h=i+j
j Exit
L1: add $s3, $s0, $s3 #k=1 so h=i+h
j Exit
L2: sub $s3, $s0, $s1 #k=2 so h=i-j
Exit: . . .
Cc t lu a ch cc nhn nh trn gi l bng a ch nhy (jump address
table)
Bng ny cha d liu nhng thng nm chung vi on m chng trnh
Gi hm hoc th tc
HUST-FET, 13/02/2011 83
1. Hm chnh (hm gi, caller) t cc tham s vo v tr
m th tc (hm b gi, callee) c th truy cp
$a0 - $a3: 4 thanh ghi tham s
2. Hm gi chuyn quyn iu khin cho hm b gi
3. Hm b gi c cp ch lu tr cn thit
4. Hm b gi thc hin cng vic mong mun
5. Hm b gi t kt qu vo v tr hm gi c th truy cp
$v0 - $v1: 2 thanh ghi kt qu
6. Hm b gi tr iu khin cho hm gi
$ra: 1 thanh ghi a ch tr v quay v v tr xut pht
Lnh gi 1 hm
HUST-FET, 13/02/2011 84
MIPS procedure call instruction:
jal ProcAddress #jump and link
Lu PC+4 vo thanh ghi $ra nh l ng dn
n lnh k tip khi tr v t hm
nh dng m my:
Hm s tr v hm gi bng:
jr $ra #return
op 26 bit address
J format
3 ????
Tng kt MIPS
HUST-FET, 13/02/2011 85
Cc loi lnh
Load/Store
Computational
Jump and Branch
Floating Point
- coprocessor
Memory Management
Special
3 nh dng lnh: rng 32 bit
R0 - R31
PC
HI
LO
OP rs
rt
rd shamt funct
OP rs
rt
16 bit number
OP 26 bit jump target
Registers
R format
I format
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
J format
Tng kt cc lnh MIPS
HUST-FET, 13/02/2011 86
Category Instr OpC Example Meaning
Arithmetic
(R & I
format)
add 0 & 20 add $s1, $s2, $s3 $s1 = $s2 + $s3
subtract 0 & 22 sub $s1, $s2, $s3 $s1 = $s2 - $s3
add immediate 8 addi $s1, $s2, 4 $s1 = $s2 + 4
shift left logical 0 & 00 sll $s1, $s2, 4 $s1 = $s2 << 4
shift right
logical
0 & 02 srl $s1, $s2, 4 $s1 = $s2 >> 4 (fill with
zeros)
shift right
arithmetic
0 & 03 sra $s1, $s2, 4 $s1 = $s2 >> 4 (fill with
sign bit)
and 0 & 24 and $s1, $s2, $s3 $s1 = $s2 & $s3
or 0 & 25 or $s1, $s2, $s3 $s1 = $s2 | $s3
nor 0 & 27 nor $s1, $s2, $s3 $s1 = not ($s2 | $s3)
and immediate c and $s1, $s2, ff00 $s1 = $s2 & 0xff00
or immediate d or $s1, $s2, ff00 $s1 = $s2 | 0xff00
load upper
immediate
f lui $s1, 0xffff $s1 = 0xffff0000
Tng kt cc lnh MIPS
HUST-FET, 13/02/2011 87
Category Instr OpC Example Meaning
Data
transfer
(I format)
load word 23 lw $s1, 100($s2) $s1 = Memory($s2+100)
store word 2b sw $s1, 100($s2) Memory($s2+100) = $s1
load byte 20 lb $s1, 101($s2) $s1 = Memory($s2+101)
store byte 28 sb $s1, 101($s2) Memory($s2+101) = $s1
load half 21 lh $s1, 101($s2) $s1 = Memory($s2+102)
store half 29 sh $s1, 101($s2) Memory($s2+102) = $s1
Cond.
branch
(I & R
format)
br on equal 4 beq $s1, $s2, L if ($s1==$s2) go to L
br on not equal 5 bne $s1, $s2, L if ($s1 !=$s2) go to L
set on less
than immediate
a slti $s1, $s2,
100
if ($s2<100) $s1=1;
else $s1=0
set on less
than
0 & 2a slt $s1, $s2, $s3 if ($s2<$s3) $s1=1;
else $s1=0
Uncond.
jump
jump 2 j 2500 go to 10000
jump register 0 & 08 jr $t1 go to $t1
jump and link 3 jal 2500 go to 10000; $ra=PC+4
T chc my tnh MIPS
HUST-FET, 13/02/2011 88
Processor
Memory
32 bits
2
30
words
read/write
addr
read data
write data
word address
(binary)
00000
00100
01000
01100
11100
Register File
src1 addr
src2 addr
dst addr
write data
32 bits
src1
data
src2
data
32
registers
($zero - $ra)
32
32
32
32
32
32
5
5
5
PC
ALU
32 32
32
32
32
0 1 2 3
7 6 5 4
byte address
(big Endian)
Fetch
PC = PC+4
Decode Exec
Add
32
32
4
Add
32
32
br offset
Ch a ch MIPS
HUST-FET, 13/02/2011 89
1. Register addressing
op rs rt rd funct
Register
word operand
op rs rt offset
2. Base addressing
base register
Memory
word or byte operand
3. Immediate addressing
op rs rt operand
4. PC-relative addressing
Program Counter (PC)
Memory
branch destination instruction
5. Pseudo-direct addressing
op jump address
Program Counter (PC)
Memory
jump destination instruction ||
op rs rt offset
Nguyn tc thit k RISC
HUST-FET, 13/02/2011 90
Simplicity favors regularity
fixed size instructions 32-bits
small number of instruction formats
Smaller is faster
limited instruction set
limited number of registers in register file
limited number of addressing modes
Good design demands good compromises
three instruction formats
Make the common case fast
arithmetic operands from the register file (load-store
machine)
allow instructions to contain immediate operands
Bin dch
HUST-FET, 13/02/2011 91
C program
compiler
assembly code
Bin i chng trnh C thnh
hp ng
Cc u im ca chng trnh ngn ng bc cao
S dng m t hn rt nhiu
d hiu d bin dch

Ngy nay cc trnh bin dch ti u c th to ra m hp
ng tt nh chuyn gia lp trnh v thng tt hn khi
dch cc chng trnh ln
Kch thc m nh hn, tc nhanh hn
Assembler
HUST-FET, 13/02/2011 92
C program
compiler
assembly code
assembler
object code
Kim tra c php m hp ng v
chuyn i m biu tng (m hp
ng) thnh m i tng (m my).
Ch : Khi xc nh hiu nng cn m s ch th c
thc thi ch khng phi kch thc m chng trnh.
u im ca assembler
D nh
S dng nhn a ch - gi tr a
ch c tnh bi assembler
S dng ch th gi
- VD., move $t0, $t1 ch c trong
assembler v s c chuyn
thnh ch th add $t0,$t1,$zero)
Nhim v chnh ca assembler
HUST-FET, 13/02/2011 93
1. To bng biu tng (symbol table) cha tn
biu tng (nhn) v a ch tng ng
1 biu tng a phng c s dng trong tp n
c nh ngha. Biu tng c quy c mc nh
l a phng.
1 biu tng ton cc (ngoi) tham chiu/c tham
chiu n m hoc d liu 1 tp. Cc biu tng
ton cc c khai bo r rng l ton cc (VD.,
.globl main)
2. Dch cc lnh m hp ng thnh ngn ng
my bng cch lp ghp cc gi tr s tng
ng vi m lnh (opcode), ch s thanh ghi
(register specifiers), s bt dch (shift amounts),
v lch cc lnh jump/branch.
Cc nhim v khc ca Assembler
HUST-FET, 13/02/2011 94
Thay m gi lnh bng m hp ng hp l
Thanh ghi $at c dnh ring cho assembler lm vic ny
Thay lnh r nhnh xa bng 1 lnh r nhnh gn theo sau
bi 1 lnh nhy
Thay lnh vi gi tr tc thi ln bng lnh lui theo sau
bi 1 lnh ori
i cc s dng thp phn v h 16 thnh cc s dng
nh phn v k t thnh m ASCII tng ng.
X l cc dn hng sp xp d liu (e.g., .asciiz)
Trin khai cc macro thnh cc chui ch th
S b nh MIPS
HUST-FET, 13/02/2011 95
Memory
2
30
words
0000 0000
f f f f f f f c
Text
Segment
Reserved
Static data
Mem Map I/O
0040 0000
1000 0000
1000 8000
7f f f f f fc
Stack
Dynamic data
$sp
$gp
PC
Kernel Code
& Data
Cu trc 1 tp m my
HUST-FET, 13/02/2011 96
Object file header: kch thc v v tr cc phn sau trong
tp
Text (code) segment (.text) : m my
Data segment (.data) : d liu i km vi m
D liu tnh (static data) c cp pht trong ton b qu trnh
chy
D liu ng (dynamic data) cp pht khi cn thit
Relocation information: xc nh cc lnh (d liu) s
dng (nm ti v tr) a ch tuyt i khng lin quan n
1 thanh ghi (k c PC)
Trn MIPS cc lnh j, jal, v 1 s lnh c ghi (VD., lw $t1,
100($zero) ) s dng a ch tuyt i
Symbol table: cc nh ton cc cng vi a ch (nu
c nh ngha cng trong on m) hoc khng cng
a ch (nu c nh ngha ngoi on m)
Debugging information
V d 2.8. Cu trc tp m my
HUST-FET, 13/02/2011 97
.data
.align 0
str: .asciiz "The answer is "
cr: .asciiz "\n"
.text
.align 2
.globl main
.globl printf
main: ori $2, $0, 5
syscall
move $8, $2
loop: beq $8, $9, done
blt $8, $9, brnc
sub $8, $8, $9
j loop
brnc: sub $9, $9, $8
j loop
done: jal printf
Gbl? Symbol Address
str
1000 0000
cr
1000 000b
yes
main
0040 0000
loop
0040 000c
brnc
0040 001c
done
0040 0024
yes
printf
???? ????
Relocation Info
Address Data/Instr
1000 0000
str
1000 000b
cr
0040 0018
j loop
0040 0020
j loop
0040 0024
jal printf
Lin kt (linker)
HUST-FET, 13/02/2011 98
C program
compiler
assembly code
assembler
object code library routines
executable
linker
machine code
main text segment
printf text segment
Lin kt
HUST-FET, 13/02/2011 99
Lin kt cc on m my c lp vi nhau
Ch cn bin dch v assemble li cc on m c thay i:
nhanh hn
1. Quyt nh mu cp pht b nh cho on m v on
d liu ca tng m un.
Ch : Cc m un c assemble c lp, mi m un u c
on m bt u ti 0x0040 0000 v d liu tnh bt u ti
0x1000 0000
2. Cp pht li a ch tuyt i phn nh ng a ch
bt u ca on m v on d liu
3. S dng bng biu tng xc nh cc nhn cha
c xc nh
Cc a ch d liu, r nhnh nhy ti cc m un ngoi
Linker to ra tp thc hin c
Lin kt
HUST-FET, 13/02/2011 100
printf:
.
.
.
main:
.
.
.
jal ????
call, printf
Linker
Object file
C library
Relocation
info
main:
.
.
.
jal printf
printf:
.
.
.
Executable file
Lin kt 2 tp m lnh
HUST-FET, 13/02/2011 101
H
d
r

T
x
t
s
e
g

D
s
e
g

R
e
l
o
c

S
m
t
b
l

D
b
g
File 1
H
d
r
T
x
t
s
e
g
D
s
e
g
R
e
l
o
c
S
m
t
b
l
D
b
g
File 2
+
Executable
H
d
r

T
x
t
s
e
g

D
s
e
g

R
e
l
o
c
Np chng trnh
HUST-FET, 13/02/2011 102
C program
compiler
assembly code
assembler
object code library routines
executable
linker
loader
memory
machine code
Np chng trnh
HUST-FET, 13/02/2011 103
Np (sao chp) m thc hin t a vo b nh
ti a ch bt u c xc nh bi h iu hnh
Sao chp cc tham s (nu c) ca hm chnh
vo ngn xp
Khi to cc thanh ghi v t con tr ngn xp
vo v tr trng (0x7fff fffc)
Nhy n hm khi to (ti PC = 0x0040 0000).
Hm khi to s chp cc tham s vo thanh ghi
tham s v gi hm chnh bng lnh jal main
Php ton v cch thc hin
Php ton dch
Php ton s hc
Cng, tr
Nhn
Chia
Php ton du phy ng
D liu my tnh: Vector bit
Lu tr trong thanh ghi hoc t nh
Truyn dn trn ng bus

X l bng php ton
Php ton dch
Kim tra 1 bit, t 1 bit, xa 1 bit
Sao chp cc bit
Hin tng trn
Php ton dch
Dch logic
Cc ch s trng c in bng 0
Sang phi1 bit: srl
1
(a
n-1
,a
n-2
,,a
0
) = (0,a
n-1
,a
n-2
,,a
1
)
Sang tri 1 bit: sll
1
(a
n-1
,a
n-2
,,a
0
) = (a
n-2
,a
n-3
,,a
0
,0)
Dng trin khai b nhn v chia khng du
Dch s hc
Bt du (MSB) khng c thay i
dch phi sao chp bt du vo cc ch s trng
dch tri khng dch bt du
Sang phi 1 bit: sra
1
(a
n-1
,a
n-2
,,a
0
) = (a
n-1
,a
n-1
,a
n-2
,,a
1
)
Sang tri 1 bit: sla
1
(a
n-1
,a
n-2
,,a
0
) = (a
n-1
,a
n-3
,,a
0
,0)
Dng trin khai b nhn v chia c du
Kt qu sai v xy ra hin tng trn nu: a
n-1
a
n-2
a
n-1
a
n-2
a
0
0 a
1
a
n-1
a
n-2
0 a
1
a
0
a
n-1
a
n-2
a
0
a
n-1
a
1
a
n-1
a
n-2
0 a
n-3
a
0
B dch
Dch tri 0 hoc 1 bt
C th thit k b dch c tri v phi
B dch
B dch tri 1 bt, v dch phi 2 bt
B cng na, cng 2 s 1 bit
HUST-FET, 13/02/2011 109
Tn hiu vo: a, b
Tn hiu ra: s (sum), c
o
(carry out)
Cu hi:
Xc nh biu thc Bool cho s, v c
o
Half Adder
(HA)
a
b
s
c
o
a b s c
o
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
s
b
a
c
o
B cng y , cng 3 s 1 bit
Tn hiu vo: a, b, c
i
(carry in)
Tn hiu ra: s (sum), c
o
(carry out)
Cu hi:
Xc nh biu thc Bool cho s, v c
o
HUST-FET, 13/02/2011 110
Full Adder
(FA)
a
c
i
s
c
o
b
a b c
i
s c
o
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
b
c
i
s
c
o
a
Php cng, tr 2 s c du
2 s biu din dng m b 2.
Cng tng bit t bit LSB n bit MSB; Nh sang ct k
tip
Kt qu sai v trn xy ra khi 2 bit nh cui cng khc
nhau: c
o,3
c
i,3
Cng 2 s khc du lun khng xy ra trn
Php tr l php cng vi s o (dng m b 2)
0 1 1 1
5 0 1 0 1
3 0 0 1 1
-8 1 0 0 0
Trn
1 0 0 0
-7 1 0 0 1
-2 1 1 1 0
7 0 1 1 1
Trn
1 1 1 1
-3 1 1 0 1
-5 1 0 1 1
-8 1 0 0 0
Khng trn
0 0 0 0
5 0 1 0 1
2 0 0 1 0
7 0 1 1 1
Khng trn
B cng 2 s n bt dng b 2
B cng ni tip gm
n b cng
n cng logic xor tnh s o khi tr
Cng logic xor pht hin trn
FA FA FA FA
...
...
a
n-1
b
n-1 a
2
b
2
a
1
b
1
a
0
b
0
add/
subtract
c
n-1
c
n-2
c
2
c
1
c
0
C
-1
s
2
s
1
s
0 s
n-1
overflow
b
c
i
s
c
o
a
Tc b cng
B cng ni tip
Tn hiu nh lan truyn (ripples) qua tt c cc b cng "ripple
carry adder"
tr tng tuyn tnh vi s lng b cng (s bit ca mi ton
hng)
Bt nh: t
ar
(c
n
) = t
ar
(c
n-1
) + 2 = 3 + 2*(n-1)
Bt tng: t
ar
(s
n
) = t
ar
(c
n
) + 1 = 4 + 2*(n-1)
Tng tc bng b cng tnh bit nh trc (Carry
lookahead Adder)
B cng CLA
Vi Ripple-Carry Adder, bit nh c tnh da trn cc
bt nh trc tc chm
Tng tc , tnh bit nh mi ct trc tip t tn hiu
u vo
Bit nh u ra ca ct i c tnh t tn hiu to nh v
tn hiu lan truyn nh c
i
= g
i
+c
i-1
p
i
s
i
= a
i
b
i
c
i-1
c
i
= a
i
b
i
+ a
i
c
i-1
+ b
i
c
i-1
= a
i
b
i
+ c
i-1
(a
i
+ b
i
)
= a
i
b
i
+ c
i-1
(a
i
b
i
)
Tn hiu to nh: g
i
= a
i
b
i
To ra c
i
khi a
i
= b
i
= 1
Lan truyn nh: p
i
= (a
i
b
i
)
Truyn nh t u vo n
u ra khi a
i
b
i
= 1
B cng CLA
Tnh ton bit nh
Mi cng thc nh trn c th c trin bi mt mch logic 2 mc
tnh ton p
i
, g
i
ta cn mch logic 1 mc t u vo
Vy cn ti a 3 mc t u vo tnh c tn hiu nh
Tng tc
Cn cng AND n+2 u vo cho c
n
!
c
0
= g
0
+ p
0
c
-1
c
1
= g
1
+ p
1
c
0
= g
1
+ p
1
g
0
+ p
1
p
0
c
-1
c
2
= g
2
+ p
2
c
1
= g
2
+ p
2
g
1
+ p
2
p
1
g
0
+ p
2
p
1
p
0
c
-1
c
3
= g
3
+ p
3
c
2
= g
3
+ p
3
g
2
+ p
3
p
2
g
1
+ p
3
p
2
p
1
g
0
+ p
3
p
2
p
1
p
0
c
-1
B cng CLA
p
i
b
i
c
i-1
s
i
a
i
g
i
p
0
g
0
c
-1
c
0
p
1
g
1
g
0
c
1
p
0
p
1
c
-1
c
2
p
2
g
2
g
1
p
1
p
2
g
0
p
0
p
1
c
-1
p
2
c
3
p
3
g
3
g
2
p
2
p
3
g
1
p
1
p
2
g
0
p
3
p
0
p
1
c
-1
p
2
p
3
Gm2 tng
Tng 1: Tnh ton tng, tnh hiu to nh v truyn nh (1 mc logic) - PFA
Tng 2: Tnh ton bit nh (2 mc logic) - CLA
Php nhn khng du
Nhn ln lt cc ct ca s b nhn v s nhn c tch cc b
Cc tch cc b c cng vi nhau theo ct
V d
a
3
a
2
a
1
a
0
* b
3
b
2
b
1
b
0
a
3
b
0
a
2
b
0
a
1
b
0
a
0
b
0
+ a
3
b
1
a
2
b
1
a
1
b
1
a
0
b
1
+ a
3
b
2
a
2
b
2
a
1
b
2
a
0
b
2
+ a
3
b
3
a
2
b
3
a
1
b
3
a
0
b
3
s
7
s
6
s
5
s
4
s
3
s
2
s
1
s
0
a b a*b
0 0 0
0 1 0
1 0 0
1 1 1
1 0 1 1 * 0 0 1 1 11*3
1 0 1 1
+ 1 0 1 1
+ 0 0 0 0
+ 0 0 0 0
0 0 1 0 0 0 0 1 33
B nhn khng du song song
S dng logic t hp
FA
a b
c
i
c
o
s
b
0
a
0
b
1
a
1
b
0
a
2
b
0
a
3
b
1
a
2
b
2
a
0
b
2
a
1
b
3
a
0
FA
a b
c
i
c
o
s
FA
a b
c
i
c
o
s
FA
a b
c
i
c
o
s
FA
a b
c
i
c
o
s
FA
a b
c
i
c
o
s
b
1
a
0
b
0
a
1
b
1
a
3
b
2
a
2
b
3
a
1
FA
a b
c
i
c
o
s
FA
a b
c
i
c
o
s
FA
a b
c
i
c
o
s
b
2
a
3
b
3
a
2
FA
a b
c
i
c
o
s
FA
a b
c
i
c
o
s
b
3
a
3
FA
a b
c
i
c
o
s
p
7
p
6
p
5
p
4
p
3
p
2
p
1
p
0
Php nhn c du
M rng bt du cho cc tch cc b
Vi tch cc b ca bit du s b
3
, cn ly s i (s b 2)
a
3
a
2
a
1
a
0
* b
3
b
2
b
1
b
0
a
3
b
0
a
3
b
0
a
3
b
0
a
3
b
0
a
3
b
0
a
2
b
0
a
1
b
0
a
0
b
0
+ a
3
b
1
a
3
b
1
a
3
b
1
a
3
b
1
a
2
b
1
a
1
b
1
a
0
b
1
+ a
3
b
2
a
3
b
2
a
3
b
2
a
2
b
2
a
1
b
2
a
0
b
2
+ a
3
b
3
a
3
b
3
a
2
b
3
a
1
b
3
a
0
b
3
+ 1
p
7
p
6
p
5
p
4
p
3
p
2
p
1
p
0
V d 2.9 Php nhn c du
1 0 1 1 * 0 0 1 1 -5*3
1 1 1 1 1 0 1 1
+ 1 1 1 1 0 1 1
+ 0 0 0 0 0 0
+ 1 1 1 1 1
1
1
1
1 0
1
1 0
1
1 1 1 1 0 0 0 1 -15
Php nhn c du
n gin ha
a
3
a
2
a
1
a
0
* b
3
b
2
b
1
b
0
a
3
b
0
a
3
b
0
a
3
b
0
a
3
b
0
a
3
b
0
a
2
b
0
a
1
b
0
a
0
b
0
+ a
3
b
1
a
3
b
1
a
3
b
1
a
3
b
1
a
2
b
1
a
1
b
1
a
0
b
1
+ a
3
b
2
a
3
b
2
a
3
b
2
a
2
b
2
a
1
b
2
a
0
b
2
+ a
3
b
3
a
3
b
3
a
2
b
3
a
1
b
3
a
0
b
3
+ 1
p
7
p
6
p
5
p
4
p
3
p
2
p
1
p
0
a
3
a
2
a
1
a
0
* b
3
b
2
b
1
b
0
a
2
b
0
a
1
b
0
a
0
b
0
+ a
2
b
1
a
1
b
1
a
0
b
1
+ a
2
b
2
a
1
b
2
a
0
b
2
+ a
2
b
3
a
1
b
3
a
0
b
3
+ 1
- a
3
b
0
- a
3
b
1
- a
3
b
2
- a
3
b
3
p
7
p
6
p
5
p
4
p
3
p
2
p
1
p
0
Php nhn c du
n gin ha
a
3
a
2
a
1
a
0
* b
3
b
2
b
1
b
0
a
2
b
0
a
1
b
0
a
0
b
0
+ a
2
b
1
a
1
b
1
a
0
b
1
+ a
2
b
2
a
1
b
2
a
0
b
2
+ a
2
b
3
a
1
b
3
a
0
b
3
+ 1
- a
3
b
0
- a
3
b
1
- a
3
b
2
- a
3
b
3
p
7
p
6
p
5
p
4
p
3
p
2
p
1
p
0
a
3
a
2
a
1
a
0
* b
3
b
2
b
1
b
0
a
2
b
0
a
1
b
0
a
0
b
0
+ a
2
b
1
a
1
b
1
a
0
b
1
+ a
2
b
2
a
1
b
2
a
0
b
2
+ a
2
b
3
a
1
b
3
a
0
b
3
+ 1
- 0 a
3
b
3
a
3
b
2
a
3
b
1
a
3
b
0
p
7
p
6
p
5
p
4
p
3
p
2
p
1
p
0
Php nhn c du
n gin ha
a
3
a
2
a
1
a
0
* b
3
b
2
b
1
b
0
a
2
b
0
a
1
b
0
a
0
b
0
+ a
2
b
1
a
1
b
1
a
0
b
1
+ a
2
b
2
a
1
b
2
a
0
b
2
+ a
2
b
3
a
1
b
3
a
0
b
3
+ 1
- 0 a
3
b
3
a
3
b
2
a
3
b
1
a
3
b
0
p
7
p
6
p
5
p
4
p
3
p
2
p
1
p
0
a
3
a
2
a
1
a
0
* b
3
b
2
b
1
b
0
a
2
b
0
a
1
b
0
a
0
b
0
+ a
2
b
1
a
1
b
1
a
0
b
1
+ a
2
b
2
a
1
b
2
a
0
b
2
+ a
2
b
3
a
1
b
3
a
0
b
3
+ 1
+ 1 a
3
b
3
a
3
b
2
a
3
b
1
a
3
b
0
1
p
7
p
6
p
5
p
4
p
3
p
2
p
1
p
0
Php nhn c du
n gin ha
a
3
a
2
a
1
a
0
* b
3
b
2
b
1
b
0
a
2
b
0
a
1
b
0
a
0
b
0
+ a
2
b
1
a
1
b
1
a
0
b
1
+ a
2
b
2
a
1
b
2
a
0
b
2
+ a
2
b
3
a
1
b
3
a
0
b
3
+ 1
+ 1 a
3
b
3
a
3
b
2
a
3
b
1
a
3
b
0
1
p
7
p
6
p
5
p
4
p
3
p
2
p
1
P
0
a
3
a
2
a
1
a
0
* b
3
b
2
b
1
b
0
a
3
b
0
a
2
b
0
a
1
b
0
a
0
b
0
+ a
3
b
1
a
2
b
1
a
1
b
1
a
0
b
1
+ a
3
b
2
a
2
b
2
a
1
b
2
a
0
b
2
+ a
3
b
3
a
2
b
3
a
1
b
3
a
0
b
3
+ 1 1
p
7
p
6
p
5
p
4
p
3
p
2
p
1
p
0
B nhn c du
B nhn ni tip
S dng b cng cng cc tch cc b
Thc hin php nhn trong vi chu k ng h
Lu s b nhn, s nhn v kt qu tm thi trong cc
thanh ghi
Vi mi bit b
i
ca s nhn B (t phi qua tri)
Nhn b
i
vi s b nhn A v cng tch vi kt qu tng tm thi
Y Nu b
i
= 1 th cng A vo Y
Dch A sang tri 1 bit
B nhn ni tip
Dch tri
A[2n-1:0]
2n-bit ALU
Dch phi
B[n-1:0]
Y[2n-1:0] control
Start
A[n-1:0] SBN
B[n-1:0] SN
Y[2n-1:0] 0
Count n
B
0
= 1 YY+A
Dch phi B
Dch tri A
Count Count - 1
Count = 0
Stop
Y
N
Y
N
Trin khai gm:
2 thanh ghi 2n bit
1 thanh ghi n bit
1 b cng 2n bit
1 khi iu khin
V d 2.10 - B nhn ni tip
Nhn xt:
Mt na s bit ca A lun bng 0
Khi A dch tri, bit 0 c thm vo bn phi
cc bit LSB ca tch khng b nh hng
tng: Gi A pha tri ca tch v dch tch sang phi
1
Start
A[n-1:0] SBN
B[n-1:0] SN
Y[2n-1:0] 0
Count n
B
0
= 1 YY+A
Dch phi B
Dch tri A
Count Count - 1
Count = 0
Stop
Y
N
Y
N
0 1 1 0 0 0 0 1 1 0 1
0 0 0 0 0 0 0 0
0 0 0 0 1 1 0 1
0 0 0 1 1 0 1 0 0 1 0 1
0 0 1 0 0 1 1 1
0 0 1 1 0 1 0 0 0 0 1 0
0 0 1 0 0 1 1 1
0 1 1 0 1 0 0 0 0 0 0 1
1 0 0 0 1 1 1 1
1 1 0 1 0 0 0 0 0 0 0 0
Counter=4
Counter=3
Counter=2
Counter=1
Counter=0
Y
A
B
B
B
B
B
Y
A
Y
A
Y
A
Y
A
Dch tri
A[2n-1:0]
2n-bit ALU
Dch phi
B[n-1:0]
Y[2n-1:0] control
B nhn ni tip Dng n-bit ALU
HUST-FET, 13/02/2011 129
A[n-1:0]
n-bit ALU
B[n-1:0]
C,Y[2n-1:0] control
Start
A[n-1:0] SBN
B[n-1:0] SN
C,Y[2n-1:0] 0
Count n
B
0
= 1
C,Y[2n-1:n]
Y[2n-1:n]+A
Dch phi B
Dch phi C,Y
Count Count - 1
Count = 0
Stop
Y
N
Y
N
Trin khai gm:
2 thanh ghi n bit
1 thanh ghi 2n+1 bit
1 b cng n bit
1 khi iu khin
V d 2.11 B nhn ni tip
HUST-FET, 13/02/2011 130
Nhn xt: Trong qu trnh nhn ch mt s bit
ca Y c ngha vi kt qu
Counter=4
Counter=3
Counter=2
Counter=1
Counter=0
1 1 0 1 A
1 1 0 1 A
1 1 0 1 A 0 0 1 0 B
0 0 0 1 B
0 1 0 1 B
1 0 1 1 B
0 0 0 0 B
Y 0 0 1 1 1 0 0 0 1
Y 1 0 0 1 1 1 0 0 0
1 1 0 1 A
0 0 0 0 0 0 0 0 Y 0
1 1 0 1 0 0 0 0 Y 0
0 1 1 0 1 0 0 0 Y 0
1 0 0 1 1 1 0 0 0 Y
0 1 0 0 1 1 1 0 0 Y
0 0 0 1 1 1 1 0 1 Y
1 0 0 0 1 1 1 1 0 Y
A[n-1:0]
n-bit ALU
B[n-1:0]
C,Y[2n-1:0] control
Start
A[n-1:0] SBN
B[n-1:0] SN
C,Y[2n-1:0] 0
Count n
B
0
= 1
C,Y[2n-1:n]
Y[2n-1:n]+A
Dch phi B
Dch phi C,Y
Count Count - 1
Count = 0
Stop
Y
N
Y
N
B nhn ni tip
HUST-FET, 13/02/2011 131
Start
A[n-1:0] SBN
C,Y[n-1:0],B[n-1:0] 0,SN
Count n
B
0
= 1
C,Y[n-1:0]
Y[n-1:0]+A
Dch phi C,Y,B
Count Count - 1
Count = 0
Stop
Y
N
Y
N
a
n-1
a
0
B tng n bit
y
n-1
y
0
b
n-1
b
0
Logic iu khin cng v
dch phi
c
n
S b nhn A
S nhn B
Trin khai gm:
1 thanh ghi n bit
1 thanh ghi 2n+1 bit
1 b cng n bit
1 khi iu khin
V d 2.12 B nhn ni tip
HUST-FET, 13/02/2011 132
Counter=4
Counter=3
Counter=2
Counter=1
Counter=0
1 1 0 1 A
1 1 0 1 A
1 1 0 1 A
1 1 1 0
1 1 1 1
1 0 1 1
1 0 1 1
Y 0 0 1 1 1
Y 1 0 0 1 0
1 1 0 1 A
0 0 0 0 Y 0
1 1 0 1 Y 0
0 1 1 0 Y 0
1 0 0 1 0 Y
0 1 0 0 0 Y
0 0 0 1 1 Y
1 0 0 0 0 Y
Start
A[n-1:0] SBN
C,Y[n-1:0],B[n-1:0] 0,SN
Count n
B
0
= 1
C,Y[n-1:0]
Y[n-1:0]+A
Dch phi C,Y,B
Count Count - 1
Count = 0
Stop
Y
N
Y
N
a
n-1
a
0
B tng n bit
y
n-1
y
0
b
n-1
b
0
Logic iu khin cng v
dch phi
c
n
S b nhn A
S nhn B
1 1 0 1
1 1 0 1
1 1 1 0
1 1 1 1
1 1 1 1
Nhn Booth
Nhn vi mt chui s 1
A * 1111 = A * (2
4
2
0
) = A * 2
4
A
Dch A sang tri 4 bit v tr i A
S b nhn B cha chui s 1 t bit v tr v n bit v tr u
(b
n-1
, b
n-2
, b
u+1
,b
u
,,b
v
,b
v-1
,..,b
0
) = (b
n-1
, b
n-2
,0,1,,1,0,..,b
0
)
Chui bit c th thay th bng 2
u+1
2
v
Cc php nhn v cng cho cc bt b
u
n b
v
c th c thay
bng php dch tri v php tr
V d:
B = 001110 (14
10
), u = 3, v = 2 A x B = A* 2
4
A*2
1
HUST-FET, 13/02/2011 133
V d 2.13 B nhn Booth
HUST-FET, 13/02/2011 134
0 +1 0 0 -1 0
0 1 0 1 0 1 A
0 0 1 1 1 0 B
B
1 1 0 1 0 1 1 0 1 1 1 1
0 0 1 0 1 0 1 0 0 0 0 0
0 1 0 1 0 0 0 0 1 0 0 0
0 0 1 0 0 1 1 0 1 0 0 0
Thc hin
1. Bt u chui s 1 (chuyn t 0 sang 1, hai bit lin tip l
01): tr i s b nhn
2. Trong chui s 0, hoc chui s 1 (2 bit lin tip l 00 hoc
11): dch tri s b nhn
3. Kt thc chui s 1 (chuyn t 1 sang 0, hai bit lin tip l
10): cng vi s b nhn
Thut ton nhn Booth
HUST-FET, 13/02/2011 135
Start
A[n-1:0] SBN
B[n-1:0] SN
C,Y[n-1:0],B
-1
0
Count n
B
0
B
-1
C,Y[n-1:0]
Y[n-1:0]+A
Dch phi C,Y,B,B
-1
Count Count - 1
Count = 0
Stop
Y
N
01
N
C,Y[n-1:0]
Y[n-1:0]-A
10
00,11
a
n-1
a
0
B tng n bit
y
n-1
y
0
b
n-1
b
0
Logic iu khin cng, tr
v dch phi
c
n
S b nhn A
S nhn B b
-1
V d 2.14 Minh ha thut ton Booth
HUST-FET, 13/02/2011 136
Start
A[n-1:0] SBN
B[n-1:0] SN
C,Y[n-1:0],B
-1
0
Count n
B
0
B
-1
C,Y[n-1:0]
Y[n-1:0]+A
Dch phi C,Y,B,B
-1
Count Count - 1
Count = 0
Stop
Y
N
01
N
C,Y[n-1:0]
Y[n-1:0]-A
10
00,11
a
n-1
a
0
B tng n bit
y
n-1
y
0
b
n-1
b
0
Logic iu khin cng, tr
v dch phi
c
n
S b nhn A
S nhn B b
-1
Counter=6
Counter=5
Counter=1
1 0 0 A 1 1 0
0 1 1 -A 0 1 1
0 0 0 0 Y 0 0 0 1 1 1 0 0 0 0
0 1 1 1 0 0 0 0 Y 0 0 0 0 0 0
0 1 1 1 1 0 1 1 Y 0 0 0 1 1 0
Counter=4 0 0 1 1 0 1 0 1 Y 1 0 1 1 1 1
Counter=3 0 0 0 1 1 0 1 0 Y 1 1 1 1 1 1
Counter=2 1 0 0 0 1 1 0 1 Y 1 1 1 1 1 0
1 0 0 +A 1 1 0
1 0 0 0 0 0 1 0 Y 1 1 1 0 0 0
1 1 0 0 0 0 1 0 Y 1 0 0 0 0 0
Counter=0 0 1 1 0 1 0 0 0 Y 0 0 0 0 0 1
Nhn Booth: Nhn c du
HUST-FET, 13/02/2011 137
V a, b l 2 s c du dng b 2:
a = -2
n-1
*a
n
+ 2
n-2
*a
n-2
+ ... + 2*a
1
+ a
0
Xt 2 bit lin tip (a
i ,
a
i-1
), hiu ca chng v hot ng nhn:
Gi tr c tnh ton bi b nhn Booth:
(0 - a
0
) * b + (a
0
- a
1
) * b * 2 + (a
1
a
2
) * b * 2
2
... +
(a
n-3
a
n-2
) * b * 2
n-2
+ (a
n-2
a
n-1
) * b * 2
n-1
Trin khai cc s hng v ti gin:
b * (-2
n-1
*a
n
+ 2
n-2
*a
n-2
+ ... + 2*a
1
+ a
0
)= b * a.
which is exactly the product of a and b.
a
i
a
i-1
a
i
a
i-1
action
1 0 -1 Tr b, v dch
0 1 1 Cng b v dch
0 0 0 B qua
1 1 1 B qua
Php chia
HUST-FET, 13/02/2011 138
Php nhn
Cng vi s b nhn v dch tri s b nhn
Ti u phn cng: cng vi s b nhn v dch phi tch
Php chia
Tr cho s chia v dch phi s chia
V d: Y = A / B
Ti u phn cng: tr cho s chia v dch tri phn d
Y 0
B 1 1
1 1 1 A 0 0
B 0 1 1 0 Y 0
B 0 0 1 1
0 0 1 A 0 0
0 1 Y 0
B 0 0 1 1 0 0 1 Y 0 0
Thut ton chia ni tip
HUST-FET, 13/02/2011 139
Start
B[n:0] SC
C, Y[n-1:0],A[n-1:0] 0,SBC
Count n
C = 1
A
0
0
Phc hi Y = Y+B
Count Count - 1
Count = 0
Stop
Y
N
Y
N
Dch tri C,Y,A
C,Y[n-1:0]
C,Y[n-1:0]-B
A
0
1
Tr Y = Y B v kim tra bit du C ca kt qu
Nu C = 1 (php tr kt qu m)
Bt kt qu a
0
=0
Phc hi s b chia: Y = Y + B
Nu C = 0 (php tr kt qu dng)
Bt kt qu a
0
=1
b
n-1
b
0
B tr n+1 bit
C y
0
a
n-1
a
0
Logic iu khin tr v
dch tri
S chia B
S b chia A
0
y
n-1
V d 2.15 B chia ni tip
HUST-FET, 13/02/2011 140
Counter=4
Counter=3
Counter=2
Counter=1
0 0 1 1 B
1 1 1 0
1 0 0 0
1 1 1 0
0 1 1 1
Y 1 1 1 0 1
0 0 0 0 Y 0
0 0 0 0 Y 0
1 1 0 1 Y 1
0 0 0 1 0 Y
0 0 1 1 0 Y
0 0 0 0 0 Y
0 0 0 0 0 Y
1 1 1 0
0 0 1 0
1 0 0 0
1 0 0 1
1 1 1 0 0 0 0 0 Y 0
1 1 0 1 -B 1
1 1 0 0 0 0 0 1 Y 0
1 1 0 1 -B 1
1 1 0 0 0 0 0 1 Y 0
1 1 0 1 -B 1
1 1 0 1 -B 1
1 1 1 0 1 Y 0 0 1 0
0 0 0 1 0 Y 0 0 1 0 Counter=0
Start
B[n:0] SC
C, Y[n-1:0],A[n-1:0] 0,SBC
Count n
C = 1
A
0
0
Phc hi Y = Y+B
Count Count - 1
Count = 0
Stop
Y
N
Y
N
Dch tri C,Y,A
C,Y[n-1:0]
C,Y[n-1:0]-B
A
0
1
b
n-1
b
0
B tr n+1 bit
C y
0
a
n-1
a
0
Logic iu khin tr v
dch tri
S chia B
S b chia A
0
y
n-1
Chia c du
1. Chia phn gi tr tuyt i
2. Xc nh du ca kt qu
Du ca thng:
Dng nu s chia v s b chia cng du
m nu s chia v s b chia khc du
Du ca phn d: lun cng du vi s b chia
3. o kt qu nu cn thit
HUST-FET, 13/02/2011 141
Php ton du phy ng
HUST-FET, 13/02/2011 142
Php cng tr: gi s E
A
> E
B
S du phy ng:
Php nhn
Php chia
Chun ha kt qu: a nh tr v dng chun ha v iu chnh s m
tng ng
B A
E
B
E
A
M B M A 2 ; 2 = =
( )
A
E
B
A
M M B A 2
'
= +
( ) ( )
B A
E E
B A
M M B A

= 2 / /
( ) ( )
B A
E E
B A
M M B A
+
= 2
B A
E E
B
B M M

= 2
'
trong

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KIN TRC MY TNH

Biu din s nguyn bng m b 2

Ch a ch dch chuyn (Displacement)

Mt s kin trc tp lnh

Truyn dn trn ng bus

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