Chapter4 Handout

KIN TRC MY TNH
ET4270
TS. Nguyn c Minh
[Adapted from Computer Organization and Design, 4th Edition, Patterson & Hennessy, 2008, MK] [Adapted from Computer Architecture lecture slides, Mary Jane Irwin, 2008, PennState University]
Chng 4. B nh - Phn cp b nh
SET-HUST, 22/03/2011
T chc lp
S tn ch Ging vin Vn phng Email 3 (3-1-1-6) TS. Nguyn c Minh C9-401 minhnd1@gmail,com
Website
https://sites.google.com/site/fethutca/home
Sch
Computer Org and Design, 3rd Ed., Patterson &Hennessy, 2007 Digital Design and Computer Architecture, David Money Harris
Th nghim
3 bi
Bi tp
Theo chng, bi xem trn trang web
Gii thiu
HUST-FET, 17/04/2011
im s iu kin thi Bi thi gia k

Bi tp Tin trnh
Ti a: 100 im, Bt u: 50 im Tch ly, tr qua tr li cu hi trn lp v ng gp t chc lp
Lab 30%
20% 10% (Ti a 100 im)
Bi thi cui k
70%
Gii thiu
HUST-FET, 17/04/2011
Lch hc
Thi gian:

T 14h00 n 17h20 L thuyt: 11 bui x 135 pht / 1 bui Bi tp: 4 bui x 135 pht / 1 bui Thay i lch (ngh, hc b) s c thng bo trn website trc 2 ngy
Gii thiu
HUST-FET, 17/04/2011
Tng kt chng 3
Tt c cc b x l hin i u dng pipeline tng hiu sut (CPI=1 v ng h nhanh - fc ln) Tc ng h pipeline b gii hn bi giai on pipeline chm nht thit k pipeline cn bng l rt quan trng Cn pht hin v gii quyt xung t trong pipeline
Xung cu trc gii quyt: thit k pipeline ng Xung t d liu

- Dng (nh hng CPI) - Chuyn tip (cn phn cng h tr)
Xung t iu khin t phn cng quyt nh r nhnh ln cc trng thi u trong pipeline
- Dng (nh hng CPI) - R nhnh chm (cn h tr ca trnh dch) - D on r nhnh tnh v ng (cn phn cng h tr)
X l ngt trong pipeline phc tp
HUST-FET, 17/04/2011
Nhc li: Cc thnh phn c bn ca my tnh

Processor
Control
Devices Memory Input Output
Datapath
Main Memory
Cache
Secondary Memory (Disk)
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Ni dung
Phn cp b nh trong my tnh

Mc ch Tnh kh thi
Processor
Devices
B m c bn

Nguyn l Cu trc Hot ng Hiu nng
Control
Memory
Input
Datapath
Output
Phng php tng hiu nng

Cache
Main Memory
B m kt hp B m a mc
Secondary Memory (Disk)
B nh o
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Processor-Memory Performance Gap

Proc 55%/year (2X/1.5yr)
10000
Performance
1000 100 10 1
Moores Law
Processor-Memory Performance Gap (grows 50%/year) DRAM 7%/year (2X/10yrs)
1980 1984 1988 1992 1996 2000 2004 Year

Chng 4. B nh - Phn cp b nh 8 SET-HUST, 22/03/2011
Bc tng b nh
Chnh lch tc b x l v RAM ng tip tc tng

Clocks per DRAM access
2010+
SET-HUST, 22/03/2011
1000
Clocks per instruction
100 10 1 0.1 0.01 VAX/1980 PPro/1996

Core Memory
Phn cp b nh (b m) ngy cng quan trng tng hiu nng chung

9
Mc tiu ca phn cp b nh
Thc t: B nh ln chm, b nh nhanh nh
Bng cch no to ra 1 b nh c v ln, r v nhanh (trong hu ht thi gian)?
Bng phn cp b nh Bng song song
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Phn cp b nh thng thng
Tp dng nguyn tc cc b cung cp cho ngi dng kch thc b nh ln nh cng ngh b nh r rt nhng tc cao nh cng ngh b nh nhanh nht
On-Chip Components Control Instr Data Cache Cache Second Level Cache (SRAM) Secondary Memory (Disk) ITLB DTLB
Datapath
Main Memory (DRAM)
Speed (%cycles): s
Size (bytes): Cost: 100s highest
RegFile
1s
10Ks
10s
Ms
100s
Gs
10,000s
Ts lowest
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Phn cp b nh: Ti sao n hot ng?
Cc b theo thi gian

Nu mt v tr b nh c truy cp th n s sm c truy cp li Lu cc d liu va c truy cp nhiu nht gn b x l
Cc b theo khng gian

Nu mt v tr b nh c truy cp th cc v tr c a ch gn s sm c truy cp a cc khi b nh cha cc t cnh nhau n gn b x l hn
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Tnh cc b
Tnh cc b theo khng gian v thi gian
Address mapping (many-to-one)
9-instruction program loop
Cache memory Main memory
Cache line/ block (unit of t rans fer between main and cache memories)
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Cc mc phn cp b nh
Processor
Tng khong cch t b x l theo thi gian truy cp
Secondary Memory
Tnh bao hm 4-8 bytes (word) Ni dung trong L1$ l 1 L1$ tp con ca 8-32 bytes (block) ni dung L2$ trong L2$; l tp con ni 1 to 4 blocks dung trong Main Memory MM; l tp 1,024+ bytes (disk sector = page)ni dung con trong SM
Kch thc (tng i) ca b nh mi mc

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Phn cp b nh: Khi nim
Khi (hoc ng): n v thng tin nh nht c (hoc khng c) trong b m lng thng tin nh nht c di chuyn gia 2 b nh 2 mc lin tip trong phn cp T l trng (Hit Rate): T l s ln truy cp b nh tm thy 1 mc trong phn cp b nh
Thi gian trng (Hit Time): Thi gian truy cp mc b nh trong phn cp b nh
Thi gian truy cp 1 khi + Thi gian xc nh trng/trt
T l trt (Miss Rate): T l s ln truy cp b nh khng tm thy 1 mc trong phn cp b nh 1 - (Hit Rate)
Tn tht trt (Miss Penalty): Thi gian thay th 1 khi mc b nh bng khi tng ng t mc b nh thp hn
Thi gian truy cp khi mc thp hn + Thi gian truyn khi n mc b nh c s trt + Thi gian chn khi vo mc + Thi gian a d liu ti ni yu cu
Hit Time << Miss Penalty

Qun l s dch chuyn d liu gia cc mc
Thanh ghi B nh
Trnh bin dch (ngi lp trnh?)
B m b nh chnh
Phn cng iu khin b m
B nh chnh a
H iu hnh (b nh o) nh x a ch o v a ch vt l nh phn cng (Translation Lookaside Buffer) Ngi lp trnh (cc tp)
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C s b m
Tr li 2 cu hi phn cng:

Q1: Mt mc d liu c trong b m hay khng? Q2: Mt mc d liu u trong b m? Mi khi b nh c nh x vo chnh xc 1 khi trong b m
- Nhiu khi trong b nh mc thp cng chia s 1 khi trong b m
nh x trc tip
nh x b nh (tr li cu hi Q2): (block address) modulo (# of blocks in the cache) C trng th(tag) gn vi mi khi b m, cha thng tin a ch (cc bt cao ca a ch) cn cho vic xc nh khi (tr li cu hi Q1)
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V d 4.1. B m nh x trc tip n gin

B m: 4 khi nh Index Valid Tag Data B nh chnh: 16 khi 1 t 0000xx 0001xx Cc khi 1 t: 2 bt 0010xx thp dng xc nh cc byte trong t (32b 0011xx words) 0100xx 0101xx 0110xx 0111xx Q2: V tr cc t trong 1000xx b m? 1001xx 1010xx Dng 2 bt thp tip 1011xx theo ca a ch ch 1100xx s xc nh khi 1101xx b m no (i.e., chia 1110xx ly d cho s khi 1111xx trong b m) (block address) modulo (# of blocks in the cache)
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00
01 10 11
Q1: C trong b m khng? So snh trng th b m vi 2 bit cao ca a ch b nh xc nh khi d liu c trong b m khng?
Truy cp nh vi b m nh x trc tip
Xt vic truy cp cc nh trong b nh

0 1 2 3 4 3 4 15
2 3
Bt u vi b m rng tt c cc khi trong b m c nh du khng hp l
15
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V d 4.2. B m nh x trc tip MIPS
Cc khi 1 t, kch thc b m = 1K t (hay 4KB)

31 30 ... 13 12 11 ... 2 1 0
Byte offset Data
Hit
Tag
20 Index
Tag
10
Data
Index Valid
0 1 2 . . . 1021 1022 1023
20
32
Tnh cc b no s c tn dng?
B m nh x trc tip khi nhiu t
Hit Tag
Khi 4 t, Kch thc b m = 1K words

31 30 . . . 13 12 11 ... 4 32 10
Byte offset Block offset

Data
Data
20 Index
Index Valid Tag

0 1 2 . . . 253 254 255
20
32
Tnh cc b no s c tn dng?
Tn dng tnh cc b khng gian
Cc khi trong b m cha hn 1 t

0 1 2 3 4 3 4 15
1
2
Bt u vi b m rng tt c cc khi trong b m c nh du khng hp l
15
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T l trt vs Kch thc khi vs Kch thc b m

10
8 KB 16 KB 64 KB 256 KB
Miss rate (%)
0 16 32 64 Block size (bytes) 128 256
T l trt tng khi kch thc khi tr nn ng k so vi kch thc b m v vi cng kch thc b m s khi c th lu gi gim (tng trt do dung lng) Tng kch thc khi lm tn tht trt
Kch thc cc trng trong b m
S bit trong b m gm bit cho d liu v bit cho cc trng th

a ch byte 32 bit B m nh x trc tip 2n khi, n bits cho trng index Kch thc khi l 2m t (2m+2 bytes), m bits cho trng block offset xc nh v tr t trong khi; 2 bits cho trng byte offset xc nh v tr byte trong t
Kch thc trng tag s l? Tng s bt trong b m nh x trc tip s l

Cn bao nhiu bit cho b m nh x trc tip kch thc 16KB d liu, kch thc khi l 4 t v d liu c nh a ch bng 32 bit?
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X l trng b m
c trng (I$ v D$)
l iu ta cn!
Ghi trng (ch vi D$)
yu cu b m v b nh phi thng nht

- lun ghi d liu vo c khi b m v vo b nh mc k tip (ghi xuyn - write-through) - ghi vi tc ca b nh mc k tip chm hn! s dng b m ghi (write buffer) v ch dng khi b m ghi y
cho php b m v b nh khng thng nht

- ch ghi d liu vo b m (ghi li write-back khi b m vo b nh mc k tip khi khi b m b ly li)
- cn 1 bt bn (dirty) cho mi khi b m ch ra l khi cn c ghi li vo b nh khi n b ly li c th dng b m ghi tng tc vic ghi li cc khi b m bn
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X l trt b m (Khi kch thc 1 t)
c trt (I$ v D$): mt thi gian read_miss_penalty
dng ng ng, np khi t b nh mc k tip, a vo b m v gi t c yu cu ti b x l, tip tc ng ng
Ghi trt (D$) mt thi gian write_miss_penalty v write_buffer_stalls
Cp pht v ghi u tin c khi t b nh v ghi t vo khi
or
Khng cp pht v ghi b qua vic ghi vo b m; ghi t vo b m ghi (tc l s ghi vo b nh mc kt tip), khng cn dng nu b m ghi khng y
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o hiu nng b m
Gi s thi gian truy cp b nh khi trng b m c bao gm trong 1 chu k thc hin thng thng ca CPU th:
Tcpu I CPI Tc
I (CPI ideal MemStallC ) Tc

CPIstall
S chu k MemStallC l tn tht trt l tng ca readstalls v write-stalls
Vi b m ghi xuyn, ta c cng thc n gin

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nh hng ca hiu nng b m
Tn tht tng i ca b m s tng khi hiu nng b x l tng (tng tc ng h v/hoc gim CPI)
Tc b nh khng c ci thin nhanh nhu tc b x l. Tn tht trt dng tnh CPIstall c o theo s chu k b x l cn thit x l trt CPIideal cng thp th nh hng ca dng do trt cng ln
B x l vi CPIideal = 2, tn tht trt l 100, 36% l lnh load/store, t l trt b nh I$ l 2% v b nh D$ l 4%
Nu CPIideal gim xung 1? 0.5? 0.25? Nu t l trt b nh D$ tng ln 1%? 2%? Nu tc ng h CPU tng gp 2 (tn hao trt tng gp 2)?
Thi gian truy cp b nh trung bnh (AMAT)

B m ln s c thi gian truy cp ln. Lm tng thi gian truy cp khi trng cn 1 giai on pipeline. Khi tng kch thc b m
ci tin t l trng nhng lm tng thi gian truy cp trng s n im m thi gian truy cp b m ln s vt qua ci tin do tng t l trng lm gim hiu nng
Thi gian truy cp b nh trung bnh (Average Memory Access Time - AMAT) l thi gian truy cp b nh khi tnh c 2 trng hp trng v trt b m
Tnh AMAT cho 1 b x l c chu k ng h 20 psec, tn tht trt 50 chu k, t l trt 0.02/1 lnh v thi gian truy cp b m 1 chu k?
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Nguyn nhn trt b m
Khng trnh c:
Ln u truy cp khi Gii php: tng kch thc khi (lm tng tn tht trt, khi rt ln lm tng t l trt)
Dung lng:
B m khng th cha ton b cc khi truy cp bi chng trnh Gii php: tng kch thc b m (c th lm tng thi gian truy cp)
Xung t:

Nhiu v tr b nh cng c nh x vo 1 v tr b m Gii php 1: tng kch thc b m Gii php 2: tng kt hp trong b m (c th tng thi gian truy cp)
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Yu cu vi h thng b nh
Tng thch vi cc c im ca b m
b m truy cp 1 khi mi ln (nhiu hn 1 t)
Tng thch vi c im ca DRAM
S dng DRAM h tr truy cp nhanh nhiu t, u tin cc DRAM tng thch vi kch thc khi ca b m
Tng thch vi c im ca bus b nh

Bus b nh phi h tr c tc truy cp DRAM v cch truy cp Cho php tng bng thng gia bus b nh v b m
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H thng b nh h tr b m
Kt ni bn ngoi chip v kin trc b nh nh hng n hiu nng tng th ca h thng rt nhiu
on-chip
Cu trc 1 t (bus rng 1 t v b nh c cc nh 1 t)
CPU
Gi s
1.
Cache
2.
32-bit data & 32-bit addr per cycle
bus
DRAM Memory
3.
1 chu k bus b nh dng gi a ch addr 15 chu k c t th nht trong khi t DRAM (thi gian chu k 1 dng), 5 chu k cho cc t th 2, 3, 4 (thi gian truy cp ct) 1 chu k tr v 1 t d liu s byte truy cp t b nh v c truyn n b m/CPU trong mi chu k bus
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Bng thng t bus b nh n b m
Hot ng ca (DDR) SDRAM
Truy cp dng: c vo thanh ghi SRAM Truy cp ct
Column Address
+1 N cols
DRAM
Chuyn 1 chui cc d liu (l tng l 1 khi b m) cc a ch lin tip trong hng

- ng h bus b nh s iu khin vic chuyn chui cc d liu
Cycle Time
N rows
Row Address
N x M SRAM M bit planes M-bit Output
1st M-bit Access 2nd M-bit 3rd M-bit RAS

CAS Row Address Col Address
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4th M-bit
Row Add
SET-HUST, 22/03/2011
Bus rng 1 t; Khi 1 t
on-chip
CPU
Khi kch thc khi l 1 t, truy cp b nh gy ra trt b m s gy ra dng pipeline trong s chu k cn tr v 1 t d liu t b nh
1 15 1 17 chu k bus b nh gi a ch chu k bus b nh c hng DRAM chu k bus b nh tr v d liu tng s chu k tn tht trt
Cache bus
DRAM Memory
S byte chuyn trong 1 chu k (bng thng) cho 1 ln trt l

4/17 = 0.235 byte/chu k bus b nh
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on-chip
Khi cc t ca khi nm cc hng khc nhau?

1 4 x 15 = 60 1 62
15 cycles 15 cycles 15 cycles
CPU
Cache bus
chu k gi a ch 1st chu k c t hng DRAM chu k tr v t cui tng chu k tn tht trt
DRAM Memory
15 cycles

(4 x 4)/62 = 0.258 byte/chu k
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on-chip
Khi cc khi cng 1 hng?

1 chu k gi a ch 1st 15 + 3*5 = 30 chu k c t hng DRAM 1 chu k tr v t cui 32 tng chu k tn tht trt
15 cycles 5 cycles 5 cycles
CPU
Cache bus
DRAM Memory
5 cycles

(4 x 4)/32 = 0.5 byte/chu k
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B nh xen k; Bus rng 4 t
on-chip
4 hng trong cc bng c c ng thi

1 chu k gi a ch th 1st 15 chu k c cc bng DRAM
CPU
Cache bus
4*1 =
4 chu k tr v d liu
20 tng chu k tn tht trt
15 cycles
DRAM DRAM DRAM DRAM Memory Memory Memory Memory bank 0 bank 1 bank 2 bank 3
15 cycles
15 cycles
15 cycles

(4 x 4)/20 = 0.8 byte/ chu k
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Gim t l trt b m #1
1.
Cho php t cc khi linh hot hn
b m nh x trc tip 1 khi b nh c nh x vo chnh xc 1 khi b m
1 thi cc khc, 1 khi b nh c th c nh x vo bt c khi b m no b m kt hp ton phn (fully associative cache) Cch tha hip: chia b m thnh cc tp (sets); mi tp gm n ng (kt hp n ng - n-way set associative). Mi khi b nh c nh x vo 1 tp duy nht (xc nh bng trng index) v c th c t vo ng bt k trong tp (c n la chn)
index = (block address) modulo (# sets in the cache)
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Truy cp nh trong b m nh x trc tip
Gi s truy cp vo cc nh 0 4 0 4 0 4 0 4
Bt u vi b m rng tt c cc khi c nh du khng hp l
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B m kt hp n ng
B nh chnh 16 khi 1 t B m: 4 khi, 2 tp Way Set V Tag 0 1 Data 0000xx 0001xx 0010xx 0011xx 0100xx 0101xx 0110xx 0111xx 1000xx 1001xx 1010xx 1011xx 1100xx 1101xx 1110xx 1111xx Khi 1 t, 2 bit thp cui dng xc nh byte trong t (t 32b)
0 1
0 1
Q2: V tr t trong b m?
Q1: C trong b m khng? So snh tt c cc th trong tp vi 3 bt a ch cao
S dng bt thp tip theo xc nh tp (i.e., chia ly phn d cho s tp trong b m)
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Truy cp nh trong b m kt hp 2 ng
Gi s truy cp vo cc nh 0 4 0 4 0 4 0 4
Bt u vi b m rng tt c cc khi c nh du khng hp l
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B m kt hp 4 ng
28 = 256 tp 4 ng (mi ng cha 1 khi)

31 30 ... 13 12 11 ... 2 1 0
Byte offset
Tag
Index V Tag
0 1 2 . . . 253 254 255
22
8 V Tag
0 1 2 . . . 253 254 255
Index
Data
0 1 2 . . . 253 254 255
V Tag
Data
Data
0 1 2 . . . 253 254 255
V Tag
Data
Way 0
Way 1
Way 2
Way 3
32
4x1 select Hit

Chng 4. B nh - Phn cp b nh 43
Data
SET-HUST, 22/03/2011
B tr b m kt hp
Vi kch thc b m c nh, tng kt hp theo h s 2 s tng s khi trong mi tp (tng s ng) v gim s tp gim kch thc trng index 1 bt v tng kch thc trng tag 1 bit
Tag
Index
Block offset Byte offset
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Gi thnh ca b m kt hp
Khi xut hin trt, ng (khi) no s b thay th?
Least Recently Used (LRU): khi b thay th l khi khng c s dng trong thi gian di nht
- Cn phn cng theo di khi c s dng khi no so vi cc khi khc trong cng tp - Vi kt hp 2 ng, dng mt bit cho mi tp t bit khi mt khi c truy cp
Gi thnh b m kt hp N ng
N khi so snh (tr v din tch) Tr khi MUX (chn tp) trc khi d liu sn sng D liu sn sng sau khi chn tp (v quyt nh Hit/Miss). Trong b m trc tip, khi b m sn sng trc khi quyt nh Hit/Miss
- Khng th gi s l trng tip tc v sau khi phc nu l trt
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Li ch ca b m kt hp
La trn gia b m kt hp v b m trc tip ph thuc vo tn tht trt v gi thnh trin khai
12 10 4KB 8KB 16KB 32KB 64KB 128KB 256KB 512KB
Data from Hennessy & Patterson, Computer Architecture, 2003
Miss Rate
8 6 4 2 0 1-way 2-way 4-way 8-way Associativity
Li ch ln nht l khi chuyn t b m trc tip sang kt hp 2 ng (t l trt gim 20%+)

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Gim t l trt #2
2.
S dng b m a mc Mch tch hp ngy nay c th cha c b m mc 1 (L1 cache) ln hn hoc b m mc 2 thng nht (i.e., n cha c chng trnh v d liu); v thm ch c b m L3 thng nht V d:

CPIideal = 2 Tn tht trt = 100 chu k (truy cp b nh chnh) Tn tht trt truy cp UL2$ = 25 chu k 36% load/stores T l trt: L1-I$ = 2%, L1-D$ = 4%, UL2$ = 0.5% (t l trt ton cc)
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Thit k b m a mc
B m L1 v L2 c thit k rt khc nhau
B m c s tp trung vo ti thiu ha thi gian truy cp khi trng h tr chu k ngn hn

- Nh hn v c khi kch thc nh hn
B m mc 2 tp trung vo gim t l trt gim tn tht trt do phi truy cp b nh chnh

- Ln hn vi khi kch thc ln hn - kt hp cao hn
Tn tht trt b m L1 c gim rt nhiu khi c b m L2 v th n c th nh hn (nhanh hn) nhng c t l trt cao hn Vi b m L2, thi gian truy cp khi trng khng quan trng bng t l trt
Thi gian truy cp trng L2$ xc nh tn tht trt L1$
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Two Machines Cache Parameters

Intel Nehalem L1 cache organization & size Split I$ and D$; 32KB for each per core; 64B blocks AMD Barcelona Split I$ and D$; 64KB for each per core; 64B blocks
L1 associativity
L1 write policy L2 cache organization & size L2 associativity L2 write policy L2 write policy L3 cache organization & size L3 associativity L3 write policy
4-way (I), 8-way (D) set assoc.; ~LRU replacement

write-back, write-allocate Unified; 256MB (0.25MB) per core; 64B blocks 8-way set assoc.; ~LRU write-back write-back, write-allocate Unified; 8192KB (8MB) shared by cores; 64B blocks 16-way set assoc. write-back, write-allocate
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2-way set assoc.; LRU replacement

write-back, write-allocate Unified; 512KB (0.5MB) per core; 64B blocks 16-way set assoc.; ~LRU write-back write-back, write-allocate Unified; 2048KB (2MB) shared by cores; 64B blocks 32-way set assoc.; evict block shared by fewest cores write-back; write-allocate
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Tng kt: Ci thin hiu nng b m

0. Gim thi gian truy cp trng

B m kch thc nh B m nh x trc tip Khi kch thc nh Khi ghi

- Khng cp pht v ghi khng truy cp trng b m, ch ghi vo b m ghi - Cp pht v ghi khng cn 2 chu k (1. kim tra trng, 2. ghi), ng ng ghi s dng b m ghi tr
1. Gim t l trt
B m kch thc ln t khi linh hot hn (tng kt hp) Khi kch thc ln (thng thng 16 n 64 bytes) Thm b m victim b m nh lu cc khi va b b
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Tng kt: Ci thin hiu nng b m

2. Gim tn tht trt

Khi kch thc nh S dng b m ghi lu khi dirty (khi b thay i-cn ghi vo b nh) khng cn i kt thc ghi trc khi c khi mi Kim tra b m ghi (v/hoc b m victim) trong trng hp c trt Vi cc khi ln, np cc t quan trng trc S dng b m a mc Tng tc v bng thng b nh
- Bus rng hn - B nh xen k, DDR SDRAMs
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Dch chuyn d liu gia cc mc b nh
Thanh ghi B nh
Trnh bin dch (ngi lp trnh?)
B m b nh chnh
Phn cng iu khin b m
B nh chnh a
H iu hnh (b nh o) nh x a ch o v a ch vt l nh phn cng (Translation Lookaside Buffer) Ngi lp trnh (cc tp)
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SET-HUST, 22/03/2011
Review: The Memory Hierarchy
Tp dng nguyn tc cc b cung cp cho ngi dng kch thc b nh ln nh cng ngh b nh r rt nhng tc cao nh cng ngh b nh nhanh nht
Processor
4-8 bytes (word)
Tng khong cch t b x l theo thi gian truy cp
Tnh bao hm Ni dung L1$ trong L1$ l 1 8-32 bytes (block) tp con ca ni L2$ dung trong L2$; l tp con 1 to 4 blocks ni dung trong Main Memory MM; l tp con ni dung trong 1,024+ bytes (disk sector = page) SM Secondary Memory Kch thc (tng i) ca b nh mi mc
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SET-HUST, 22/03/2011
B nh o
S dng b nh chnh nh b m cho b nh th cp

Cho php chia s an ton v hiu qu b nh gia cc chng trnh Cho php chy chng trnh ln hn kch thc b nh vt l n gin ha vic np chng trnh chy (i.e., m chng trnh c th c a vo bt k ch no trong b nh chnh) 1 chng trnh thng truy cp vo mt khng gian a ch nh ti trong 1 khong thi gian
Ti sao c hiu qu? Tnh cc b
Mi chng trnh s dng 1 khng gian a ch ring bit khng gian a ch o.

Trong thi gian chy, a ch o c dch thnh a ch vt l (a ch b nh chnh) Khng gian o a ch ca chng trnh c chia thnh cc trang (kch thc c nh) hoc cc on (kch thc thay i)
54 SET-HUST, 22/03/2011
Dch a ch
Mt a ch o c dch thnh 1 a ch vt l bng c phn cng v phn mm Virtual Address (VA)

31 30 . . . 12 11 . . . 0
Virtual page number

Translation
Page offset
Physical page number

29 . . .
Page offset
12 11 0
Physical Address (PA) Mi yu cu b nh, u tin cn yu cu 1 s dch b nh t khng gian o thnh khng gian vt l
Trt b nh o (trang khng c trong b nh vt l) gi l li trang (page fault)

55 SET-HUST, 22/03/2011
Nguyn l dch a ch
Virtual page # Offset Physical page # Page table register Offset
Physical page V base addr
1 1 1 1 1 1 0 1 0 1 0
Main memory
Page Table (in main memory) Disk storage

a ch o vi b m
Cn thm 1 ln truy cp b nh dch a ch o thnh a ch vt l

VA
CPU Translation hit data
PA
Cache
miss Main Memory
Truy cp b nh (b m) rt tn km (mi ln truy cp thc cht l hai ln truy cp) S dng b m nhc v (Translation Lookaside Buffer TLB) mt b m nh lu tr cc chuyn i a ch va c s dng gn y trch vic tm trong bng trang
57 SET-HUST, 22/03/2011
Tng tc dch a ch
Virtual page # V
1 1 1 0 1
Tag
Physical page base addr
Page table register
Physical page V base addr

1 1 1 1 1 1 0 1 0 1 0
TLB
Main memory
Page Table (in physical memory)

Disk storage
SET-HUST, 22/03/2011
TLB trong phn cp b nh

t TLB Lookup miss Translation hit PA t Cache hit
VA CPU
miss Main Memory
data
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SET-HUST, 22/03/2011
Bn cu hi trong phn cp b m
Q1: Mt mc d liu c t vo u trong mc cao hn? (Entry placement)
Q2: Mt mc d liu c tm nh th no trong mc cao hn? (Entry identification)
Q3: Thay th mc no khi c trt? (Entry replacement)
Q4: Lm g khi ghi? (Write strategy)
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Q1&Q2: V tr t/tm mt mc d liu?

S tp nh x trc tip Tng s mc 1 S mc / 1 tp
Kt hp a ng
Kt hp ton phn
(Tng s mc)/ kt hp
1
kt hp (thng t 2 n 16)
Tng s mc
Phng php tm nh x trc tip Kt hp a ng Kt hp ton phn nh ch s (index) nh ch s tp; So snh th ca tp So snh th ca tt c cc mc. 1
S b so snh kt hp Tng s mc
Hoc bng (trang) tra cu ring

SET-HUST, 22/03/2011
Q3: Thay th mc no khi c trt

nh x trc tip duy nht 1 la chn Lun thay th Kt hp tp hoc kt hp ton phn

Ngu nhin LRU (Least Recently Used): thay th khi t c s dng nht trong thi gian di nht
Vi b m kt hp 2 ng, phng php thay th ngu nhin c t l trt cao hn 1,1 ln so vi phng php LRU LRU c chi ph (phn cng) cao khi p dng cho b m c kt hp cao (> 4-ng) v theo di thng tin s dng rt tn km
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Q4: Lm g khi ghi?
Write-through: Ghi xuyn Thng tin c ghi vo mc d liu c mc b nh hin ti v mc b nh k tip trong phn cp b nh.
Lun c kt hp cng b m ghi loi b thi gian ch ghi vo b nh mc k tip (cho n khi b m ghi cha y)
Write-back: Ghi sau Thng tin ch c ghi vo mc d liu mc b nh hin ti. Mc b thay i c ghi vo mc b nh k tip khi n b thay th.

Cn bit bn theo di 1 mc l b thay i hay khng H thng b nh o lun dng phng php ghi sau vi cc trang c nh du bn Ghi xuyn: trt khi c khng gy ra vic ghi d liu: n gin, r v d trin khai Ghi sau: ghi c cng tc ca b m, ghi lp li cn 1 ln ghi vo b nh mc thp
u nhc im?
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SET-HUST, 22/03/2011
Tng kt
Nguyn l cc b:
Chng trnh c th truy cp vo mt phn kh nh khng gian a ch ti 1 thi im.

Cc b thi gian - Temporal Locality Cc b khng gian - Spatial Locality
Hiu b m, TLBs, b nh o bng cch nghin cu cch chng x l 4 cu hi:

1. 2. 3. 4.
Mc d liu c t u? Mc d liu c tm nh th no? Thay th mc no khi trt? Thc hin ghi nh th no?
Bng trang nh x a ch o vo a ch vt l
TLBs dng thc hin vic dch nhanh
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SET-HUST, 22/03/2011

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KIN TRC MY TNH

Theo chng, bi xem trn trang web

im s iu kin thi Bi thi gia k

Xung cu trc gii quyt: thit k pipeline ng Xung t d liu

X l ngt trong pipeline phc tp

Nhc li: Cc thnh phn c bn ca my tnh

Devices Memory Input Output

Secondary Memory (Disk)

Phn cp b nh trong my tnh

Nguyn l Cu trc Hot ng Hiu nng

Phng php tng hiu nng

Secondary Memory (Disk)

Processor-Memory Performance Gap

1980 1984 1988 1992 1996 2000 2004 Year

Chnh lch tc b x l v RAM ng tip tc tng

Clocks per instruction

100 10 1 0.1 0.01 VAX/1980 PPro/1996

Phn cp b nh (b m) ngy cng quan trng tng hiu nng chung

Thc t: B nh ln chm, b nh nhanh nh

Bng cch no to ra 1 b nh c v ln, r v nhanh (trong hu ht thi gian)?

Bng phn cp b nh Bng song song

Phn cp b nh thng thng

Main Memory (DRAM)

Phn cp b nh: Ti sao n hot ng?

Cc b theo thi gian

Cc b theo khng gian

Tnh cc b theo khng gian v thi gian

Address mapping (many-to-one)

9-instruction program loop

Cache memory Main memory

Tng khong cch t b x l theo thi gian truy cp

Kch thc (tng i) ca b nh mi mc

Phn cp b nh: Khi nim

Hit Time << Miss Penalty

Qun l s dch chuyn d liu gia cc mc

Trnh bin dch (ngi lp trnh?)

Phn cng iu khin b m

V d 4.1. B m nh x trc tip n gin

Truy cp nh vi b m nh x trc tip

Xt vic truy cp cc nh trong b nh

Bt u vi b m rng tt c cc khi trong b m c nh du khng hp l

V d 4.2. B m nh x trc tip MIPS

Cc khi 1 t, kch thc b m = 1K t (hay 4KB)

Byte offset Data

B m nh x trc tip khi nhiu t

Khi 4 t, Kch thc b m = 1K words

Byte offset Block offset

Index Valid Tag

Tn dng tnh cc b khng gian

Cc khi trong b m cha hn 1 t

Bt u vi b m rng tt c cc khi trong b m c nh du khng hp l

T l trt vs Kch thc khi vs Kch thc b m

Miss rate (%)

0 16 32 64 Block size (bytes) 128 256

Chng 4. B nh - Phn cp b nh 23 SET-HUST, 22/03/2011

Kch thc cc trng trong b m

S bit trong b m gm bit cho d liu v bit cho cc trng th

Kch thc trng tag s l? Tng s bt trong b m nh x trc tip s l

c trng (I$ v D$)

Ghi trng (ch vi D$)

yu cu b m v b nh phi thng nht

cho php b m v b nh khng thng nht

X l trt b m (Khi kch thc 1 t)