Embedded Processing and DSP Resource Guide 2013 Edition PDF

Embedded Processing & DSP
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2 Embedded Processing & DSP Resource Guide 2013
Embedded Processing & DSP
Resource Guide 2013 Edition
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The Embedded Processing & DSP Resource Guide 2013 Edition is published by
Extension Media LLC. Extension Media makes no warranty for the use of its products
and assumes no responsibility for any errors which may appear in this Catalog nor
does it make a commitment to update the information contained herein. Embedded
Processing & DSP Resource Guide 2013 Edition is Copyright
2012 Extension Media

LLC. No information in this Catalog may be reproduced without expressed written
permission from Extension Media @ 1786 18th Street, San Francisco, CA 94107-
2343.All registered trademarks and trademarks included in this Catalog are held by
their respective companies. Every attempt was made to include all trademarks and
registered trademarks where indicated by their companies.
All registered trademarks and trademarks included in this Catalog are held by their
respective companies. Every attempt was made to include all trademarks and
registered trademarks where indicated by their companies.
C2000, DaVinci, OMAP, TMS320C2000, TMS320C24x, TMS320C28x, C24x,
C28x, C5000, TMS320C5000, TMS320C54x, TMS320C55x, C54x, C55x, C6000,
TMS320C6000, TMS320C62x, TMS320C64x, TMS320C64x+, TMS320C67x,
C62x, C64x, C64x+, C67x, TMS320DM64x, DM64x, TMS320C5x, Code Composer
Studio, DSP/BIOS, eXpressDSP, MicroStar BGA, NanoFree, NanoStar, ProbePoint,
RTDX, TMS320, XDAIS, XDS510 and XDS560 are trademarks of Texas Instruments. All
other trademarks are property of their respective owners.
Welcome to the 2013 Embedded Processing
& DSP Resource Guide
Texas Instruments is pleased to be the ofcial sponsor of the Embedded Processing & DSP Resource
Guide. This guide provides engineers, designers and embedded developers with a purchasing guide on
TI processor-based development tools, embedded software, engineering services and end-equipment
solutions provided by our worldwide TI Design Network members.
TI Design Network members offer various levels of system integration, optimization and system exper-
tise on products to enable you to meet project demands, reduce costs and get to market quickly. Please
contact the companies listed in the guide for more information on TI platforms including, C2000 real-
time control microcontrollers, MSP430 ultra-low-power microcontrollers, Stellaris 32-bit ARM
Cortex-M microcontrollers and Hercules safety microcontrollers, Sitara ARM Cortex-A pro-
cessors, TMS320C6000 high-performance, single core and multicore processors, TMS320C5000
ultra-low power DSPs and DaVinci video processors. For the latest products and information, visit the
TI Design Network homepage at http://www.ti.com/tidesignnetwork.
Selection and Solution Guides
APM - Do you heed ah APM-based soluIioh IhaI is low-power ahd cosI eIIecIive or ohe IhaI is
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The Newest Products for Your Newest Designs
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Contents
Extending System Trace to Blackhawk USB560m Emulators on Multicore TI C66xx Key-
Stone SoCs
By Andrew Ferrari, Blackhawk ................................................................................................................................................. 8
Small Cells Connecting a Big World Require Huge Integration
By Chris Ciufo, Senior Editor .................................................................................................................................................. 12
Analysis of LTE Base Station Software Deployment on Multicore SoCs
By Sneha Namakaje and Zhihong Lin, Texas Instruments ..................................................................................................... 18
Top 3 Mistakes with Static Analysis for Embedded and Safety-Critical Development
By Arthur Hicken, Evangelist, Parasoft ................................................................................................................................... 23
Embedded Processing Overview
Embedded Processors
Texas Instruments
Embedded Processing Overview ........................................................................................................................................... 25
TMS320C6000 and TMS302C5000 DSPs, Fixed- and Floating-Point .................................................................................. 26
C2000 Microcontrollers, Fixed-Point and Floating-Point....................................................................................................27
MSP430 Microcontrollers ..................................................................................................................................................28
Sitara ARM
Cortex-A8 and ARM9 Processors ..........................................................................................................30

Stellaris
32-Bit ARM
Cortex-M MCUs ........................................................................................................................... 31

TMS320C66x Multicore DSP, Fixed- and Floating-Point ....................................................................................................... 32
Hercules Safety Microcontrollers .......................................................................................................................................33
DaVinci Video Processors: Optimized for Digital Video .....................................................................................................34
Products and Services
Development Tools
Daughter Cards
Kentec Display
LM4F232/LM4F120 LCD Interface Expansion Board
(Stellaris Boosterpack) .......................................................... 35
Link Research
Multi-channel Data Acquisition daughtercard for the
F2812/F28335 eZdsp Development Kit .............................. 36
Development Boards
Xilinx
Avnet Spartan-6 FPGA DSP Kit ............................................. 37
Avnet TI OMAP Processor / Spartan-6 FPGA
Co-Processing Kit .................................................................. 37
Development Boards/EVMs
D.SignT GmbH & Co. KG
D.Module2 High-Performance DSP Processor and I/O
Boards ................................................................................... 38
Traquair Data Systems, Inc.
micro-line TMS320C641x-based Integer DSP/FPGA Boards ..... 39
micro-line TMS320C6713 DSP-based Floating-Point
DSP/FPGA Boards ................................................................. 40
Xilinx
Avnet Kintex-7 FPGA DSP Kit with High-Speed Analog ....... 41
mouser.com/ti
Mouser and Mouser Electronics are registered trademarks of Mouser Electronics, lnc. Other products, logos, and company names mentioned herein, may be trademarks of their respective owners.
;OL5L^LZ[7YVK\J[ZMVY@V\Y5L^LZ[+LZPNUZ
mouser.com
Semiconductors and electronic
components for design engineers.
Authorized Distributor
Over 29,000 Tl Products in Stock
Over 2,300 Tl Dev Tools in Stock
Find the Newest Tl Technologies. Faster.
Texas Instruments
|n Stock.
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6
Development Tools
Signum Systems
Signum Systems Emulators for TI DSPs, OMAP and
DaVinci Processors ............................................................ 42
Sundance Digital Signal Processing Inc
Hand-coded, Optimized DSP/Vector, LINPACK, EISPACK,
and CBLAS Libraries .............................................................. 43
Emulators/Analyzers
Blackhawk
Advanced JTAG XDS510 Emulators ...................................... 44
Blackhawk Emulator Product Matrix ..................................... 45
High Performance JTAG Emulators ....................................... 46
USB100v2 JTAG Controllers ................................................. 47
XDS560v2 System Trace (STM) ............................................ 48
Kane Computing Ltd
Kane Computing Company Profle ......................................... 49
Signum Systems
JTAGjet In-Circuit Debuggers for DSP, OMAP and
DaVinci Processors ............................................................ 50
Embedded Software
Algorithms/Codecs
Adaptive Digital Technologies
Adaptive Digital Echo Cancellation Library: Acoustic,
Packet, Network, & Line ....................................................... 51
Voice Algorithms and Solutions on the Texas Instruments
TMS320 Family of DSPs, OMAP, DM-Series,
Multi-Core, and ARM processors ...................................... 52
DSP Innovations Inc.
New TWELP Vocoder (6009600 bps) ................................ 53
Application-Specifc Libraries
IP phone/intercom/ATA for OMAP3530, OMAP3730,
DM814X, DM816X, and Stellaris devices. ........................ 54
DelCom Systems, Inc.
GSM/EGPRS/EDGE LayerONE Physical Layer Software ...... 55
Drivers/IO/Control Software
D.SignT TCP/IP Stack for TI C2000 MCUs, C5000, and
C6000 DSPs ........................................................................ 56
Framework Software
G.PAK bridges the gap between infexible fxed-function
chips and custom programmed solutions ............................. 57
HCC Embedded
Advanced Embedded Middleware ........................................ 58
End-Equipment Solutions
End-Equipment Solutions
Anaren
Anaren Integratec Radio 110L Series ................................... 59
Critical Link
MityARM System on Modules based on TI AM335x
processors ............................................................................. 60
MityDSP and MityARM System on Modules
with FPGA .............................................................................. 60
Z3 Technology, LLC
Compact Low-Power Software- Enabled HD Multimedia
Module .................................................................................. 61
Engineering Services
Digital Hardware / Board Design
Advantech Co., Ltd.
DSPC-8681 Half-length PCI Express Multimedia
Processing Card .................................................................... 62
Full Turnkey Designs
Benchmark Electronics
World Wide Electronics Design and Manufacturing
Services ................................................................................. 63
Micross Components
DSP & Microcontroller Die and Alternative Packaging ........ 64
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System Trace
The System Trace (STM) capability offered by Texas Instru-
ments employs the MIPI System Trace Protocol, which
provides developers with a printf capability. In a multicore
environment, information from each core can by analyzed
because they are globally time stamped. This is a powerful
tool for looking at what
each core is processing in a
common timeline. TI offers
STM for CTools-enabled
devices.
This article provides a
brief overview of how
to configure a Black-
hawk USB560m JTAG
emulator to collect STM
data via embedded trace
buffer (ETB) on TI C66xx
KeyStone multicore
architecture.
For additional TI STM
information or to down-
load the complete demo
project code and examples
mentioned in this article,
please visit: www.black-
hawk-dsp.com/STM.
CCS Project Creation (Code Composer
Studio IDE)
To demonstrate how easy it is to add STM data collection to
an application, a simple, hello world-type project for the
C6678 will be used.
To recreate the demo project for this or a different STM sup-
ported target:
1. Start Code Composer Studio IDE v5.x
2. Select the main menu option File New CCS Project. Tis will
display the New CCS Project wizard dialog (Figure 1) where you
can enter a project name, select the Family (demo uses C6000)
and its variant (demo uses Generic C66xx Device).
3. Leave the default advanced settings and choose Empty
Project from the Project Templates and Examples.
4. Click fnished when done. Tis will create a main.c fle with
a single function, main() and add it to the eclipse Project
Explorer window.
5. Now locate a C66xx linker command fle, copy it to the
project workspace and specify the fle in the project prop-
erties (demo uses a fle downloaded in one of the TI C667x
CTools Examples). Te project will now build successfully.
Adding STMLib to the Project
After the project is configured in CCS:
1. Download and install the STMLib fles.
2. Include the STM header fle and add and the path of the STM
library fle to the linker in project.
3. Add the STM API calls to the code. Te projects main.c fle
will look something like the following code snippet.
#include StmLibrary.h
#include <stdio.h>
#include <stdlib.h>
void main(void) {
int jj=0;
pSTMhdl=STMXport_open(pSTMBufInfo, &STMConfg-
Info);
STMXport_printf(pSTMhdl, STM_HelperCh, %s, C667x
Demo1 - BEG LOOP );
for (ii=0; ii<880000; ii++) {
if ((ii%250) == 0) {
STMXport_putShort(pSTMhdl, STM_HelperCh, (short)jj );
jj++;
}
}
STMXport_printf(pSTMhdl, STM_HelperCh, %s, C667x
Demo1 - END LOOP );
STMXport_fush(pSTMhdl);
STMXport_close(pSTMhdl);
exit (0)
}
Extending System Trace to
Blackhawk USB560m Emulators on
TIs C66x KeyStone Multicore SoCs
By Andrew Ferrari, Blackhawk
Figure 1 - New CCS Project Dialog
Figure 2 - New Target Confgura-
tion Dialog
www.eecatalog.com/dsp 9
Advertorial
Confguring CCS
To create a target configura-
tion and setup trace:
1. Select the main menu
option, File New Target
Confguration File, and
choose the emulator connec-
tion and device (see Figure 2).
2. Launch the debug session.
3. Connect to the neces-
sary devices to enable STM
collection using the ETB
(see Figure 3). Tese devices should be labeled similar
to C66xx_0 (frst CPU core), CSSTM_0 (STM node), and
TETB_STM (ETB node).
You may need to select
the option to Show all
cores.
4. Confgure set-
tings in the trace system
control dialog from the
main menu Tools Trace
Control (see Figure 4).
5. Select the CSSTM_0 tab. If the ETB settings are not dis-
played, select the Receiver button and choose ETB from
the list (Figure 6). Make sure the ETB type is Auto and
Synchronize trace with target execution is selected.
6. Press the OK button to apply these settings.
Collecting STM Data
1. Open the trace display window for the CSSTM_0 node from
the main menu (Tools Trace Analyzer Open Trace
Connection in New View CSSTM_0). Tis is where the col-
lected STM data will be
displayed (Figure 5).
2. Load the demo
program to C66xx_0 and
run (Resume | F8) the
program. Because the
option to synchronize
with target execution
was selected in the trace
controls, the trace display
will update automatically
with the STM data collected in the ETB when the program
terminates or is halted.
Te Data Message column of the trace display (Figure 5) shows
the output from the function STMXport_printf() and the Data
column is from the function STMXport_putShort ().
That is all that is required to begin collecting STM debug
information from your application using a Blackhawk
USB560m JTAG emulator (or any Blackhawk XDS560-class
emulator).
Multicore STM Data Collection
To collect STM from more than one core, simply connect to
another CPU core (i.e. C66xx_1) prior to setting up the trace
controls. It is also helpful to group the CPUs in the debug
window to synchronize program load and target execution.
In the trace display, the Master Name column will differ-
entiate the data for each CPU and the time stamp will order
each debug message in the proper sequence.
XDS560v2 STM Data Collection
This article describes how to extend Blackhawk XDS560-
class emulators to collect STM data using the ETB. If you
own a Blackhawk XDS560v2 STM model, you can collect
STM data directly, without using the ETB.
The setup requires that you change the target connection to
the Blackhawk XDS560v2 STM Emulator, selecting 560v2
System Trace as the trace receiver and only connecting to
the CSSTM_0 and C66xx_0 devices (do not connect to the
TETB_STM node).
For more information, visit: www.blackhawk-dsp.com/STM.
Figure 3 - Debug Window
Figure 4 - Trace System Control
Figure 5 - Trace Display Window with
STM Data
Figure 6 - Trace Receiver Selection
Dialog
CONTACT INFORMATION
Blackhawk
123 Gaither Drive
Mt. Laurel, NJ 08054
USA
856-234-2629 Telephone
856-866-1100 Fax
info@blackhawk-dsp.com
http://www.blackhawk-dsp.com
Spectrum Digital, Inc.
12502 Exchange Drive, Suite 440
Stafford, TX. 77477 USA
Tel: 281.494.4500 x-113
Fax: 281.494.5310
www.spectrumdigital.com Copyright Spectrum Digital 2012, 09/05/2012 sales@spectrumdigital.com
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Part Number 701041 701121 702302 702305 701902 701014 701900 701910 701905 702597 702598 702592
Price in USD $ 1299 $ 2499 $ 89 $ 129 $ 249 $ 495 $989 $ 1995 $1199 $ 695 $ 1199 $ 1495
PC Interface
Parallel
Port
Parallel
Port
USB USB USB
Parallel
Port
USB USB USB USB USB
USB,
Ethernet
Powered by PS PS USB USB USB PS/Target USB USB USB USB USB PS
TMS320C30-32 Yes Yes
TMS320VC33 Yes Yes Yes
TMS320C4x Yes
TMS320C5x Yes
TMS320F24x/F240x Yes Yes Yes Yes Yes
TMS320F28xx Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
TMS320C54x
TM
Yes Yes Yes Yes Yes Yes Yes Yes Yes
TMS320C55xx
TM
TMS320C64xx/C64x+ C64x+ C64x+ Yes Yes Yes Yes Yes Yes Yes
TMS320C64+, C66xx Yes Yes Yes Yes Yes Yes Yes Yes Yes
TMS470 ARM7 Yes Yes Yes Yes Yes Yes Yes
TMS470 ARM9/11 ARM 9 ARM 9 Yes Yes Yes Yes Yes Yes Yes
ARM Cortex / OMAP
TM
DaVinci
TM
Processors Yes Yes Yes * Yes * Yes * Yes * Yes Yes Yes
Sitara
TM
Processors Yes Yes Yes Yes Yes Yes Yes Yes Yes
C6-Integra
TM
+3.3V to +5V Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
+1.8V to +3.3V Yes Yes Yes Yes Yes Yes
Supports CCS v4.x v5.x Yes Yes Yes Yes Yes v4.2+ v4.2+ v4.2+
System Trace Spt Yes Yes
Embedded Trace Buf Yes Yes Yes Yes Yes Yes Yes Yes
C-JTAG Spt (CCS5.x) Yes Yes Yes Yes
SDFlash Support Yes Yes Yes Yes Yes
XMLGUI Support Yes Yes Yes Yes Yes
Boundary Scan Spt Yes
Spectrum Digital Emulators for TI Processors
Accessories Part Number Price
TI14 Pin Low Voltage Adapter for JTAG Emulators (LVA) 701208 $ 99
TI14-TI14 Pin LVA with Adapti ve clock for OMAP
TM
/DaVinci
TM
Processors 701210 $ 149
TI14-CTI20 Pin LVA with Adaptive clock for OMAP
TM
/DaVinci
TM
Processors 701212
$ 149
CTI20(in)-TI14(out) 701218 $ 69
TI14(in)-CTI20(out) 701219 $ 69
CTI20(in)-TI60(out) 701220 $ 74
CTI20(in)-ARM20(out) 701222 $ 69
TI14(in)-ARM20(out) 701280
$ 69
XDS560v2 STM adapter kit, MIPI60 to TI14, CTI20, ARM20, TI60 701238 $ 299
4 Channel JTAG Ex Emulator pander for JTAG Emulators 701204 $ 995
Spectrum Digital, Inc.
Stafford, TX. 77477 USA
Tel: 281.494.4500 x-113
Fax: 281.494.5310
Spectrum Digital TI Processor Target Platforms
Processor Family Target Module Scan/Interface Part Number Price
TMS320C3x D.Module.C31eco (OEM) MPSD Call Call
TMS320VC33 eZdsp
TM
VC33 PP/J TAG 701385 $ 519
D.Module.VC33 J TAG Call Call
TMS320F24x eZdsp
TM
LF2401A PP/J TAG 761120A $ 515
eZdsp
TM
LF2407A PP/J TAG 761119 $ 319
TMS320F28xx eZdsp
TM
F2808 USB/J TAG 761131 $ 249
eZdsp
TM
F2808/socket USB/J TAG 761132 $ 469
eZdsp
TM
F2812 PP/J TAG 761128 $ 325
eZdsp
TM
F2812/socket PP/J TAG 761129 $ 469
eZdsp
TM
R2812 USB/J TAG 761130 $ 469
eZdsp
TM
F28335 USB/J TAG 761136 $ 325
eZdsp
TM
F28335/socket USB/J TAG 761135 $ 515
TMS320VC54x DSK VC5416 USB/J TAG 701840 $ 415
TMS320VC55x EVM320VC5502 J TAG 701860 $ 995
EVM320VC5505 USB/J TAG 701883 $ 474
DSK VC5509A USB/J TAG 701882 $ 515
DSK VC5510 USB/J TAG 701880 $ 415
C5515 eZdsp
TM
USB Stick USB 702359 $ 89
C5502 eZdsp
TM
USB Stick USB 702362 $ 125
EVM320C5515 USB/J TAG 702260 $ 415
TMS320C6000
TM
D.Module.C6201 (OEM) J TAG Call Call
D.Module.C6203 J TAG Call Call
D.Module.C6701 (OEM) J TAG Call Call
DSK C6713 USB/J TAG 701895 $ 415
TMS320C64x DSK C6416T, 1Ghz. USB/J TAG 701891 $ 515
EVM DM642, 720 Mhz. J TAG 702002 $ 1995
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EECatalog
SPECIAL FEATURE
Take a look at the growth of the Internet, smartphone hand-
sets, tablet computers, M2M, or just about any device that
connects to the Internet and there are two common traits: 1.
growth ranges from up to really up!; and 2. its the need
for data exchange that is driving demand. Increasingly, this
data moves wirelessly over Wi-Fi when inside a building,
and over cellular when outside or traveling around. Wireless
operators are frantically looking for ways to handle increased
demand without investing in expensive wholesale buildout
of their networks. One way to add more bandwidth is by
intelligently handling device data requirements through DPI,
compression, local routing, RF spectrum optimization, and
heterogeneous cellular networks that self-organize.
According to documentation from AirHop Communica-
tions, a provider of intelligent Radio Access Network
(RAN) software for multi, small, and macro cell networks:
network operators are turning to small cell base sta-
tions to increase capacity and
complement existing macro-
cell networks. The resulting
HetNet (heterogeneous net-
work) requires self-organizing
network (SON) technology spe-
cifically designed for small cell
networks to actively optimize
system capacity and power, and
manage inter-cell interference
when so many cell sites are
situated close by each other.
Analysts predict a ratio of 10:1
in favor of small cells vs tradi-
tional macro cell base stations.
TI claims to have captured some
50 percent of the designs for small cells, and aims to win
over 70 percent of the total market. With devices like their
new KeyStone TCI6612 and TCI6614, its understandable
why the company is so enthusiastic.
AirHop has partnered with Texas Instruments, making
their eSON software available on TIs KeyStone multicore
architecture TMS320C66x/ARM Cortex-A8-based SOCs
for small cell base stations. Tere are two devices the
TMS320 TCI6612 and TMS320 TCI6614 SoCs that pro-
vide wireline to RF solutions for 3G, 4G, and LTE radio nets.
Te density and array of features in these devices is simply
astounding, showcasing a balance of on-chip DSP, RISC CPU,
packet processing, and hierarchical crossbar fabric engines.
Most impressive is how optimized the chips are for making
decisions, moving data, and autonomously handling the task
at hand: making RAN SON small cells work efciently.
Functional Block Party
TIs small cell family consists of three devices (Figure 1),
including the TCI6636 designed for up to 256 users. Te
system organization of the 6614 shown in Figure 2 shows a
highly integrated SOC broken in several major functional
blocks, all interconnected by the TeraNet fabric crossbar sup-
porting up to 2 Tbits/s data. TeraNet is hierarchical and low
latency, moving the most important data so that on-chip accel-
erator resources avoid starvation. As well, power consumption
is lower in idle states.
The devices are organized as: processor resources; multi-
core shared memory; external memory and low-speed I/O;
high speed I/O; Layer 1 and 2 Bit Rate Coprocessor (BCP)/
network coprocessors. All of the onboard functional
blocks, connected by the TeraNet fabric, are under the con-
trol of a packet-based manager called Multicore Navigator.
Navigator handles fire and forget communications,
job management and data transfers to assure dynamic
resource scheduling, load balancing, and hardware-based
task prioritization. Between Navigator and TeraNet, data
Small Cells Connecting a Big
World Require Huge Integration
While Texas Instruments no longer calls itself a DSP company, it still leverages
DSP expertise and IP to create dense, feature-packed KeyStone SOCs targeting
small cell base stations.
By Chris A. Ciufo, Senior Editor
Figure 1: TIs KeyStone multicore architecture small cell portfolio includes the TMS320 TCI6612/14 dis-
cussed here, plus the TCI6636 designed for high capacity small cells and green power macro cells. The 12
and 14 use ARM Cortex-A8 cores, while the 36 uses an industry-leading ARM Cortex-A15.
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and engineering teams.
EECatalog
SPECIAL FEATURE
is designed to flow into and out of the SOC as quickly as
possible with minimal latency or bottlenecks.
According to TIs Tom Flannigan, Director of Technology
Strategy, MultiCore processors: For 2G, 2.5G, 3G and 4G
standards a lot is done in hardware, not software. Tat means
that packet processing is done in hardware in a network pro-
cessor-like way; however, unlike the often proprietary nature
of NPUs, standard Eclipse-based tools are used to program the
TI devices, along with the popular and expansive ecosystem
available for C66x and ARM-based platforms.
We ll discuss a few of the chips subsystems below.
KeyStone Multicore Architecture - DSP
and ARM
Processors Married Once Again

Perhaps no company has so successfully married DSP with
ARM cores as TI, as exemplified in their handset OMAP
processors and SOCs. Theyre again hitched together in
the 6612/14 where the C66x boasts four times the pro-
cessing power of previous generations of DSPs. The ARM
Cortex-A8 (and A15 in the TCI6636) handles control plane
processing with 32 KB of L1 SRAM for each C66x core. As
well, there are two C66x cores in the 12, and four in the
14, with each core supported by its own 1 MB L2 memory
giving a total of 4.8 GHz of DSP processing and up to 153.6
16-bit GMACs per second. And these are floating point
cores folks, churning out a whopping 76.8 GFLOPs. They
also handle fixed point math, and TI claims a 5x increase
over standalone fixed point solutions.
L3 SRAM memory is shared between the cores for data
and for ARM processor program stores. The L3 multi-
core shared memory is under the control of a dedicated
controller (MSMC) to prevent memory contention, data
starvation, and arbitrates accesses between L2, L3 and
the three (in the 12) or five (in the 14) cores. The MSMC
also performs another high-performance function in that
it keeps memory data off of the TeraNet fabric, allowing
atomic movement between the cores and freeing up the
fabric for moving packet data between the rest of the
peripherals. TI claims the MSMC has L3 latency thats
nearly identical to the local L2 memories.
Lastly, theres a 64-bit, 1,600 MHz bus external memory
interface for off-board DDR3 memory under the MSMCs
control. Because advanced 3G and 4G small cells handle
loads of data, latency is kept low with this interface. The
EMIF can also control 16-bit external NAND and NOR flash.
Garden Variety Peripherals
Before we get to the really fun peripherals, its important
to mention the more common interfaces, without which
the chip wouldnt make a very cooperative system player.
Here again, TI shows off the companys expertise in
building high density SOCs. On the low-speed side, theres
I2C, SPI and twin UARTs. Theres also a 32-pin GPIO port
with programmable interrupts fired from key events.
On the high-speed side are four serial RapidIO lanes at 5
Gbits/s, PCI Express (two lanes, GEN1 and GEN2), and the
obligatory Gigabit Ethernet ports (two). Since getting data
between the Ethernet backbone and the air interface is
the ICs primary function, additional on-chip accelerators
speed network data handling functions.
There are two Ethernet media access controllers to pipeline
data between the PHY and the DSP cores. This is partly
handled by a data I/O module that continuously polls all
32 addresses in order to enumerate all PHY devices in the
system. A packet processor can classify Layer 2 to Layer
4 data at up to 1.5 Gbits/s, while an embedded security
accelerator works at 1 Gbits/s (wire speed) performing
IPSec, SRTP, and 3GPP air interface security protocols.
TI also includes HyperLink and AIF2 ports. The former
is the proprietary 12.5 Gbaud/lane inter-processor back-
bone used to connect multiple SOCs together. The low
protocol/high rate link between TI KeyStone SoC devices
allows scalable small cell solutions with MultiCore Navi-
gator software dispatching tasks to multiple devices which
appear as local resources in a multiprocessing fashion.
The AIF2 interface is a peripheral module used for trans-
ferring baseband IQ data between baseband DSPs and a
Figure 2: Block diagram of the TCI6612 and TCI6614. The 12 has two
C66x cores whereas the 14 has four.

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software| hardware| turnkey systems
EECatalog
SPECIAL FEATURE
high-speed serial interface. On the 12 and 14, the AIF2
second-generation SERDES-based antenna interface is
capable of up to 6.144 Gbits/s per link, and there are six
links available. AIF2 supports OBSAI RP3 and CPRI pro-
tocols for the following RF standards: WCDMA/FDD, LTE
(FDD and TDD), WiMax, TD-SCDMA, and GSM/Edge. AIF2
connects externally to either RF units or other baseband
devices. The AIF2 interface is so important that it has its
own 433 page manual, separate from the rest of the chip.
Not So Garden Variety Peripherals
While the garden variety peripherals are impressive,
even more so are the accelerators and co-processors TI
packs into the twin devices. Designed for bit rate pro-
cessing that avoids disturbing the DSP cores, they are
lumped together into the bit rate coprocessor (BCP) block
shown in Figure 2 as Layer 1 and Layer 2. The BCPs
top-level functions are shown in Figure 3 which includes
a CRC engine, turbo interference cancellation for MIMO
equalization - a critical function of small cell
base stations - and various mod/demodula-
tors and interleaver/deinterleavers.
Collectively, the configurable accelerators
and co-processors maximize flow-through
system performance while also reducing
base station complexity through single chip
operation. For example, theres no need to
implement in off-board FPGAs FFT or DFT
transforms, Viterbi decoders, or LTE decode
logic. Some typical performance numbers are
shown in Figure 4.
Summary
As on-the-go Internet traffic increases
through data transfers, theres an acute need
for small cell base stations. These offload
macro cells by cost effectively adding users,
bridging wireless standards, and increasing
coverage. Seizing the market with high-inte-
gration, high intelligence peripherals, Texas
Instruments TMS320TCI6612/14 SOCs offer
barn-burning performance without con-
suming much power. Taking advantage of all
on-board resources, TI quotes small cell base
station power levels at 26mW per Mbits/s of
data transferred. Thats a tidy way to connect
a big worlds huge demand for wireless data,
one cell site at a time.
Chris A. Ciufo is senior editor for em-
bedded content at Extension Media,
which includes the EECatalog print
and digital publications and web-
site, Embedded Intel Solutions, and
other related blogs and embedded
channels. He has 29 years of embedded technology
experience split between the semiconductor industry
(AMD, Sharp Microelectronics) and the defense in-
dustry (VISTA Controls and Dy4 Systems), and in content creation.
He co-founded and ran COTS Journal, created and ran Military
Embedded Systems, and most recently oversaw the Embedded
franchise at UBM Electronics. Hes considered the foremost expert
on critically applying COTS to the military and aerospace industries,
and is a sought-after speaker at tech conferences. He has degrees in
electrical engineering, and in materials science, emphasizing solid
state physics. He can be reached at cciufo@extensionmedia.com.
Figure 3: The on-board bit-rate coprocessor (BCP) is designed to move and process data
through the chips without burdening the DSP cores. As such, the BCP includes Layer 1
and Layer 2 processing engines tied together via the TeraNet fabric.
Figure 4: On-board coprocessors and accelerators, coupled with the TCI6612/14s fow-
through architecture, returns impressive performance numbers for typical small cell
operations. TIs goal was to build an SOC needing no external FPGA or ASIC.
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EECatalog
SPECIAL FEATURE
Figure 1: E-UTRAN Architecture
Figure 2: eNB Protocol Stack
Analysis of LTE Base Station Software
Deployment on Multicore SoCs
To achieve full multicore entitlement, SoCs require a hardware infrastructure
without bottlenecks, as well as a simplifed software infrastructure.
By Sneha Narnakaje and Zhihong Lin, Texas Instruments
The advent of high-speed cellular services
like 4G LTE is driving a paradigm change
in the complexity of wireless base station
design. As wireless technology continues
to evolve, the demand for higher data rates
increases, causing growth in data traffic.
The data deluge has significant implica-
tions on the type of processing required.
Data traffic is packet-based and allows
for hundreds of users to be connected to a
base station at the same time, all sharing
the airwaves. Managing data traffic effi-
ciently requires the system to handle large
volumes of data packets moving through all
processing layers. It is becoming increas-
ingly important for OEMs and operators
to effectively handle LTE technology using
multicore systems-on-chip (SoCs), as
multicore architectures bring new levels
of efficiency to base station designs. To
achieve full multicore entitlement, SoCs
require a hardware infrastructure without
bottlenecks, as well as a simplified software infrastruc-
ture. This article discusses the challenges encountered
in traditional software implementation of LTE base sta-
tion on a multicore SoC. Further, this paper will show an
example of software implementation on a multicore SoC,
leveraging the hardware infrastructure to effectively and
efficiently overcome those challenges.
LTE Base Station Overview
4G LTE is defined
by 3GPP 36 series
technical specifica-
tions. LTE provides
increased data
rate and capacity,
better spectrum
efficiency, reduced
latency and sim-
plified network
architecture.
LTE base stations,
also referred to as
eNodeB (E-UTRAN
NodeB), provide user-plane and control-plane protocol
terminations (Uu) toward the user equipment (UE,
mobile) as well as transport terminations (Iu) toward
the core network. eNodeBs are interconnected through
X2 interface and also connected to core network EPC
through S1 interface.
The eNodeB protocol structure is comprised of two main
layers: the radio network layer and the transport net-
work layer. The radio interface is implemented within
three protocol layers: physical layer (Layer 1, PHY), data
link layer (Layer 2) and network layer (Layer 3). Layer
2 is partitioned into sublayers called media access con-
trol (MAC), radio link control (RLC) and packet data
convergence protocol (PDCP). Layer 3 includes the radio
resource control (RRC) sublayer
eNodeB Implementation Challenges on a
Multicore SoC
Traditionally, eNodeB implementation in the macro
space has been based on multiple fragmented devices.
While multicore DSP devices are used for baseband
(PHY) processing, multicore general-purpose processors
are used for radio protocol stack processing. In addition,
EECatalog
SPECIAL FEATURE
Figure 3: eNodeB Software Deployment on a Multicore SoC
Operators and base station
vendors are focusing on the
SoC concept to reduce system
cost, power and complexity,
expediting time to market.
dedicated network processor units, ASIC and FPGA, are
used as bridging devices for transport/backhaul and
radio processing. A combination of fragmented devices
increases the system cost, system power and complexity
to implement the eNodeB on multiple multicore devices.
With the emergence of heterogeneous networks in the
base station market, operators and base station vendors
are focusing on the SoC concept to reduce system cost,
power and complexity, expediting time to market. A basic
approach is to integrate all, if not most, of the functions
on a single chip. Today, we see many SoC architectures
with multicore DSP and RISC cores integrated with a
hardware infrastructure to
enable parallel access to all
cores.
eNodeB implementation
on a multicore SoC brings
significant challenges. LTE
brings a paradigm shift for
base station vendors and
their suppliers, with more
complex data processing
and scheduling to achieve
spectral efficiency. While
data processing requires low
latency and higher throughput, scheduling needs to be
dynamic and channel-aware. Multicore SoC architectures
come with their own complexity with parallelism across
cores, hardware abstraction for full multicore entitle-
ment, partitioning of application software, inter-process
communication and shared resource management. A
traditional approach to solving these challenges uses
shared memory-based multithreading. LTE eNodeB func-
tional tasks are distributed across the cores with data
distribution and handled by shared memory. However,
the performance is dependent on the memory access
times, bus bandwidth and cache effectiveness. Hardware
infrastructure bottlenecks have
also made it nearly impossible
to achieve the low latency and
higher throughput required by
LTE data processing.
An Example of Soft-
ware Implementation
of eNodeB on a Multi-
core SoC
The example of software imple-
mentation of eNodeB is based
on a multicore SoC for small
cells. The architecture for this
multicore SoC integrates four
DSP cores with an ARM core.
The hardware infrastructure
includes a network and security
accelerator and a queue manager
with dedicated packet DMA subsystem. LTE baseband
processing (PHY) is running on two DSP cores, while LTE
user-plane processing (layer 2) is running on the other
two DSP cores. An ARM core runs the LTE control-plane
processing (layer 3 and application). This example of
software implementation of eNodeB leverages high-level
operating system (Linux) services on the ARM core for
the LTE control-plane processing, with real-time oper-
ating system (RTOS) on DSPs for the hard real-time layer
2 and PHY processing. The layer 2 downlink timing is
constrained by HARQ retransmission loop and supplying
PDSCH data load to the PHY, while uplink timing is
constrained PUSCH HARQ
process. By allocating layer
2 on the DSP core closer to
the PHY processing, latency
is minimized.
Many SoC architectures
today harden the network
and security functionality
for eNodeB. However these
hardware accelerators follow
the look-aside approach
requiring CPU cycles to
perform pre- and post-pro-
cessing for each functional block (e.g., IPSec, Ciphering).
With this approach, the throughput varies with the
packet size. Instead, hardware accelerators enabled with
flow-through fast-path processing can achieve maximum
throughput for all packet sizes. In addition, after all the
fast-path processing, if the packets land in dedicated pri-
oritized hardware queues, the CPU is not burdened with
data handling.
Hardware queues play an important role in implementing
eNodeB packet processing. When eNodeB packet processing
(PHY, layer 2 and 3) tasks are distributed across multiple
EECatalog
SPECIAL FEATURE
cores, packets need to be handled efficiently and effectively,
without any bottlenecks. Hardware queues in this architec-
ture guarantee the multicore atomicity of all accesses to the
queues, enabling the zero-copy approach for the eNodeB
packet processing. The zero-copy RLC/MAC concept lever-
ages the fact that the data payload requires no processing
between the PDCP (de)ciphering and the CRC generation
(or check) at the PHY encoder/decoder. RLC and MAC sub-
layers need to aggregate/deaggregate, segment/desegment,
multiplex/demultiplex data packets and add/remove con-
trol information and headers. Accomplishing this without
touching the payload data (zero-copy) saves 90-95 percent
of processing cycles. Therefore, payload data resides in DDR
and can never be touched by layer 2 software. For example,
in the downlink direction, packets are received, IPSec
decrypted, classified, GTPU processed, air ciphered by
network and security accelerator, then allocated and deliv-
ered to the per radio bearer hardware queue by dedicated
packet DMA. All steps above are performed without soft-
ware intervention. RLC/MAC software operates on packet
descriptors and does not need to access the packet payload.
It builds MAC PDUs, which are sent out and reassembled
back to contiguous memory by the packet DMA.
With key benefits such as spectral efficiency, flexible
channel bandwidth and capital expenditure savings, LTE is
driving operators to deploy LTE networks. While effective
LTE systems can be designed on a multicore architecture,
achieving full multicore entitlement is the key to unleashing
multicore performance and reaping the benefits of 4G sys-
tems. Supporting efficient and effective LTE system designs
require a number of innovations in multicore architecture
design. One such innovation is a hardware infrastructure
without bottlenecks, enabling packet processing, memory
access and core-to-core communication.
Based on a presentation at the 2012 Multicore DevCon.
Sneha Narnakaje is the software product man-
ager for TIs wireless base station infrastructure
team. In this role, she is responsible for TIs com-
mon software strategy and roadmap across the
wireless base station infrastructure team and
driving business development activities. She
earned her MBA from the University of Maryland (Smith) and
BS in computer engineering from Mangalore University, India.

As a strategic marketing manager for TIs multi-
core processors group, Zhihong Lin is responsible
for defining and planning key requirement for
multicore SoC for wireless base station applica-
tions. Zhihong has over 18 years of experience
in both communications and networking in-
dustries. Zhihong holds a US patent on communications and
received her MSEE degrade from University of Texas at Dallas.
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EECatalog
SPECIAL FEATURE
The high cost of repairing defects shipped in embedded
devices, paired with the increasing need to follow regula-
tory compliance initiatives for safety-critical embedded
systems software (FDA, DO-178B/C, IEC 61508) has
driven many organizations to adopt static analysis as a
key part of their quality strategies.
Static analysis is one of the most effective and least bur-
densome of such industry-standard best practices. In fact,
it is often explicitly recommended (e.g., per the FDA's rec-
ommendation for infusion pumps) as one key component
of a comprehensive quality strategy. When properly imple-
mented, static analysis is a very powerful tool for exposing
error-prone code. Finding and fixing such code from the
earliest phases of the software development lifecycle has
been proven to be a very effective (and cost-efficient) way
to prevent defects from being shipped in the final product.
Static analysis is a critical component of a comprehensive
quality process...but it is just one component. It's important
to remember that most effective quality processes involve
a combination of test and analysis practices embedded
throughout the SDLC. In addition to static analysis, an
effective quality strategy covers practices such as:
- UniL LcsLing (hosL and LargcL)
- Rcgrcssion LcsLing
- Pccr codc rcvicw
- Covcragc analysis
- RunLimc crror dcLccLion
- RcquircmcnLs LraccabiliLy
At Parasoft, we've been assisting software develop-
ment organizations to implement and optimize static
analysis since 1996. Over the years of analyzing static
analysis deployments across safety critical, embedded,
and enterprise software development organizations, we've
determined what mistakes are most likely to result in
failed static analysis initiatives. Here's what we've found
to be the top three reasons why static analysis initiatives
dont deliver real value in embedded and safety-critical
development environmentsand some critically impor-
tant tips for avoiding these common pitfalls.
3. Starting With Too Many Rules
Some eager teams take the "big bang" approach to static
analysis. With all the best intentions, they plan to invest
considerable time and resources into carving out the
penultimate static analysis implementation from the
startone that is so good, it will last them for years.
Tey assemble a team of their best engineers. Tey read stacks
of programming best practices books. Tey vow to examine
all of their reported defects and review the rule descriptions
for all of the rules that their selected vendor provides.
I've found that teams who take this approach have too
many rules to start with and too few implemented later
on. It's much better to start with a very small rule set, and
as you come into compliance with it, phase in more rules.
Static analysis actually delivers better results if you don't
bite off more than you can chew. When you perform static
analysis, it's like you're having an experienced engineer
stand over the shoulder of an inexperienced engineer and
give him tips as he writes code. If the experienced engi-
neer is constantly harping on nitpicky issues in every few
lines of code, the junior engineer will soon become over-
whelmed and start filtering out all advicegood and bad.
However, if the experienced engineer focuses on one or
two issues that he knows are likely to cause serious prob-
lems, the junior engineer is much more likely to remember
what advice he was given, start writing better code, and
actually appreciate receiving this kind of feedback.
It's the same for static analysis. Work incrementallywith
an initial focus on truly critical issuesand you' ll end up
teaching your engineers more and having them resent the
process much less. Would you rather have a smaller set of
rules that are followed, or a larger set that isn't?
Top 3 Mistakes with Static
Analysis for Embedded and
Safety-Critical Development
By Arthur Hicken, Evangelist, Parasoft
EECatalog
SPECIAL FEATURE
Out of the hundreds or sometimes even thousands of rules
that are available with many static analysis tools, how do
you know where to start? Here are a few simple guidelines:
1. Would team leaders stop shipping if a violation of this
rule was found?
2. (In the beginning only) Does everyone agree that a vio-
lation of this rule should be fixed?
3. Are there too many violations from this rule?
In regulated environments, this rule is elevated to the
status of a commandment. The more you get into the habit
of frequently suppressing or ignoring rule violations, the
more likely you are to have to tell an auditor or attorney
why you ignored reports of an issue that ultimately caused
a serious defect in the field. From a negligence perspec-
tive, it's much safer to define a tight rule set and ensure
that every violation is addressed than to have a large one
that is loosely followed.
2. No Automated Process Enforcement
Without automated process enforcement, engineers
are likely to perform static analysis sporadically and
inconsistentlywhich is not only problematic from a
compliance perspective, but also diminishes your ability
to derive maximum defect-prevention value from static
analysis. The more you can automate the tedious static
analysis process, the less it will burden engineers and
distract them from the more challenging tasks they truly
enjoy. Plus, the added automation will help you achieve
consistent results across the team and organization.
Avoid the false economy of an automated run that still
requires a manual triage process at the end. A tighter
configuration will provide more value without the need
for manual review and selection of what to fix.
Many organizations follow a multi-level automated
process. Each day, as the engineer works on code in the
development environment, he or she can run analysis
on demandor configure an automated analysis to run
continuously in the background (like spell check does).
Engineers clean these violations before adding new or
modified code to source control.
Then, a server-based analysis can run as part of con-
tinuous integration, or on a nightly basis, to make sure
nothing slipped through the cracks.
Assuming that you have a policy requiring that all viola-
tions from the designated rule set are cleaned before check
in, any violations reported at this level indicate that the
policy is not being followed. If this occurs, don't just have
the engineers fix the reported problems. Take the extra
step to figure out where the process is breaking down, and
how you can fix it (e.g., by fine-tuning the rule set, using
suppressions judiciously).
1. Lack of a Clear Policy
It's common for organizations to overlook policy because
they think that simply making the tool available is suffi-
cient. It's not. Even though static analysis (done properly)
will save engineers time in the long run, they're not going
to be attracted to the extra work it adds upfront. If you
really want to ensure that static analysis is performed as
you expecteven when the team's in crunch mode, scram-
bling to just take care of the essentialspolicy is key.
Every team has a policy, whether or not it's formally
defined. You might as well codify the process and make it
official. After all, it's a lot easier to identify and diagnose
problems with a formalized policy than an unwritten one.
Ideally, you want your policy to have a direct correlation to
the problems you're currently experiencing (and/or com-
mitted to preventing). This way, there's a good rationale
behind both the general policy and the specific ways that
it's implemented.
With these goals in mind, the policy should clarify:
- WhaL Lcams nccd Lo pcrorm sLaLic analysis
- WhaL projccLs rcquirc sLaLic analysis
- WhaL rulcs arc rcquircd
- WhaL dcgrcc o compliancc is rcquircd
- Whcn supprcssions arc allowcd
- Whcn violaLions in lcgacy codc nccd Lo bc ixcd
- WhcLhcr you ship codc wiLh sLaLic analysis violaLions
Arthur Hicken, Evangelist for Parasoft, has
been involved in automating various practices
at Parasoft for almost 20 years. He has worked
on projects including database development, the
software development lifecycle, web publishing
and monitoring, and integration with legacy sys-
tems.
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DaVinci

Video
Processors
C6000

Digital Signal
Processors
C5000

Digital Signal
Processors
C2000

Microcontrollers
MSP430

Microcontrollers
Sitara

32-bit ARM

Cortex
-A
Processors
Stellaris
32-Bit
ARM

Cortex-M
MCUs
Hercules

Safety
Microcontrollers
Audio
Automotive
Communications
Industrial
Medical
Security
Video
Wireless
Key Feature
Video
processing
High
performance
Ultra-low
power
Performance,
integration for
greener industrial
applications
Ultra-low power
Low power,
high
performance
Open architec-
ture software,
rich communica-
tions options
Safety Integrated
in H/W
Embedded Processing Overview
Texas Instruments has the broadest portfolio of scalable DSP, MCU, differentiated ARM
and complementary analog products, offering

complete system solutions for electronics manufacturers. This portfolio offers the full range of power/performance requirements ensuring
the right combination of attributes for the smallest portable devices to the largest multichannel systems and everything in between. In
addition, TI offers design resources including extensive software (including open source), tools, technical training, in-person and online tech
support, and engineer-to-engineer forums at www.e2e.ti.com. Visit www.ti.com for technical literature, system block diagrams and more.
Applications Matrix Guideline
DaVinci
Video Processors:
Optimized for Digital Video
DaVinci
video processor solutions are tailored

for digital video, imaging, and vision applications.
Optimized for video encode and decode applications,
the DaVinci platform includes a general purpose
processor, video accelerators, an optional DSP,
and related peripherals. A wide range of devices
are available, offering a variety of performance,
power and price points.
High Performance: TMS320C6000

DSP Platform
The C6000
DSP platform offers the industrys

highest-performance single- and multicore DSPs,
ideal for networking, telecommunication, video,
imaging, infrastructure, test and equipment,
military, and industrial applications. The platform
includes C64x high-performance DSPs,
C674x fixed-/floating-point DSPs and C66x
fixed-/floating-point multicore DSPs. It also
includes the OMAPL series which combines
a C674x DSP with an ARM9
processor to handle
networking and control for computational efficiency.
Ultra-Low-Power TMS320C5000

DSP Platform
The C5000
DSP platform provides a broad

portfolio of the industrys lowest power 16-bit DSPs.
Total active core power at less than 0.15 mW/MHz
at 1.05V and standby power at less than 0.15mW
extends the battery life of portable applications.
Increase processing capability with C5000 DSP
processors that offer up to 300MHz (600 MIPs).
High peripheral integration and large on-chip
memory helps reduce overall system cost. Ultra low
cost development boards, system development kits,
free and highly mature software libraries with an
extensive database of code examples enables fast
time to market. With these advantages, the C5000
has become a very popular choice for a variety of
low-power and cost-efficient embedded signal
processing solutions, including portable devices in
audio, voice, communications, medical, security
and industrial applications.
C2000
32-Bit Micro controller for

Real-Time Control
The C2000
microcontroller family combines

advanced control peripherals with the processing
power of a 32-bit core. With the low-cost,
high-integration Piccolo
MCUs, the powerful

Delfino
floating-point MCUs and the connectivity

and control featured in the Concerto
MCUs, C2000
MCUs offer a broad range of options and are ideal for
embedded industrial control and green
energy applications such as digital motor control,
digital power supplies, solar and wind energy, LED
lighting, and automotive HEV/EV.
MSP430
Ultra-Low-Power
Microcontroller Platform
The MSP430 family of ultra-low-power
16-bit RISC mixed-signal processors provides
the ultimate solution for battery-powered
measurement applications. Using leadership
in both mixed-signal and digital technologies,
TI has created the MSP430 MCU, enabling system
designers to simultaneously interface to analog
signals, sensors and digital components while
maintaining unmatched low power.
Sitara
ARM
Processors
The high-performance Sitara ARM-based
processors include solutions based on the
ARM Cortex
-A8 and ARM9
. The platform
includes the AM1x, AM35x, AM37x and AM335x
processors, which offer a software-compatible
roadmap for customers using TIs OMAP35x
and OMAP-L1x processors.

Stellaris
32-Bit ARM Cortex-M MCUs

Texas Instruments is the industry leader in
bringing 32-bit capabilities and the full benefits
of ARM
Cortex
-M microcontrollers (MCUs) to
the deepest reach of the microcontroller market.
With more than 220 compatible ARM Cortex-M
Stellaris MCUs and more than 30 Stellaris evaluation,
development, and reference design kits, Stellaris fits
the performance, integration, power, and price-point
requirements of nearly any industrial application.
Stellaris with Cortex-M offers a direct path to the
strongest ecosystem of development tools, software
and knowledge in the industry. Designers who
migrate to Stellaris benefit from great tools, small
code footprint, and outstanding performance. With
StellarisWare
Software, Stellaris gives developers

a huge jump start by providing a free, royalty-free
software package that includes a peripheral driver
library, graphics library, USB library, code examples,
and much more.
Hercules
Safety Microcontrollers
Hercules safety microcontrollers are based on
TIs 20+ years of safety-critical system expertise,
industry collaboration and proven hardware for the
automotive market. The platform consists of three
ARM
Cortex
-based microcontroller families

(RM48x, TMS570 and TMS470M) that deliver
scalable performance, connectivity, memory and
safety features. Unlike many microcontrollers that
rely heavily on software for safety capabilities,
Hercules microcontrollers implement safety in
hardware to maximize performance and reduce
software overhead.
Software and Development Tools
TMS320
DSPs are supported by eXpressDSP

software and development tools, including Code
Composer Studio
IDE, DSP/BIOS
kernel, the
TMS320 DSP algorithm standard and numerous
reusable, modular software from the largest
developer network in the industry.
Complementary Analog Products
TI offers a range of complementary data
converter, power management, amplifiers,
interface and logic products to complete
your design.
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Specifications
CO000
high performance fixed/

floating-point DSP
Co000
ultra-low power fixed-point

DSP; industrys lowest cost and
lowest power DSPs
Rcou| c||Wa|e a|d |cc|, Ccde
Composer Studio
IDE, Software
Development Kits, Application
Software and Libraries
S]B|0S, S|a||e|wa|e, a|d |||u/
software development kits, developed
and supported by TI
Rea|-||re ||a| p|c:e||
Targeted Applications
Biometric Security, Smart E-Meter
AMR/AMI, Industrial Drives, Portable
audio/voice, Portable Medical
Key Features
C5000 Ultra-low-power DSPs
Up |c 800 |H/
1O-o||
||/ed-pc||| + ||T A::e|e|a|c|
Up |c 820 |B RA|
Up |c 2oO |B R0|
SP|, |
2
C, I
2
S
HS USB 2.0
|CO
|:BSP
$1.9o |c $10.00
C6000 High-performance DSPs
Up |c 800 |H/
||/ed-/||ca|||-pc||| OSP
Up |c 2oO |B RA| + 128|B
internal RAM
OOR2, |OOR
|:BSP, |:ASP, 1
2
C, SPI
|CO :c|||c||e|, .|dec |/0, UPP
$o.00 |c $2o.00
C6000 DSP+ARM9

Up |c 4oO |H/
fixed-/floating-point DSP
Up |c 4oO |H/ AR|9
|:ASP, |:BSP, |
2
C, SPI
|CO :c|||c||e|, .|dec |/0, UPP
128| |a|ed RA|
USB 2.0, USB 1.1,
ethernet MAC, SATA
OOR2, |OOR
$8.00 |c $1o.00
TMS320C6x and TMS320C5x DSPs, Fixed- and Floating-Point
High-Performance, Low-Power DSPs
Get samples, data sheets, tools and app reports at: www.ti.com/singlecore
Singlecore DSP Roadmap
Single-core DSP focuses on real-time applications, driving the lowest system cost and power, with
differentiated solutions.
C5000 C5000 C5000
C66x
C66x+ARM
C674x+ARM9
C6000
C5000 C5000
Ultra-Low
Power DSPs
General
Purpose
DSPs
DSP + ARM
SoCs
C6424/1
0SP: 0p to 700Nhz
0NA, NA0,
NcASP, 1
2
0, VPSS
0p to 1N8 L2
32b-0082
0NAP-L13x
C674x+ARM9
0SP: 0p to 456Nhz
A8N9: 0p to 456Nhz
10l100 NA0, 0S8,
PRU
L00, VP|F, SATA
S08ANlLP0081l0082
C5504/5/14/15
0p to 150 Nhz, 0S8,
SDRAM
FFT, L00, L00s
0p to 320k8S8AN
0.15mwlNhz
C674x
Production
Samp||og
P|o 0ompat|b|e
0eve|opmeot
F0t0re
C6000
0SP: 0p to 456Nhz
10l100 NA0, 0S8,
PRU
L00, VP|F, SATA
S08ANlLP0081l
DDR2
05532l3l4l5
0p to 50l100 Nhz,
0S8, S08AN
FFT, L00
0p to 320k8 S8AN
0.15mwlNhz
DSP+
Low Power ARM
C66x+ARM
|ocreased PerIormaoce
|ocreased 0oooect|v|ty
C6xx DSP
|ocreased PerIormaoce
|ocreased 0oooect|v|ty
C5xx Next
*00h0PT
150-200 Nhz, 0S8
FFT, L00, SP|
512k8 S8AN
<0.14mwlNhz
C5517
0p to 200 Nhz, 0S8,
SDRAM
FFT, L00s, hP|, SP|
0p to 320k8 S8AN
0.30mwlNhz
05537
0p to 150 Nhz, 0S8,
SDRAM
FFT, L00s, SP|
0p to 320k8S8AN
0.30mmwlNhz
Low $ Low $ Low $
2h12 2h13
*00h0PT*
TMS320C553x DSP Block Diagram
The C553x ultra-low-power DSP generation featuring the lowest power and lowest cost DSP in the
industry, starting at $1.95/1ku, offers the industrys lowest power with active power less than 0.15
mW/MHz at 1.05V and standby power less than 0.15 mW. These highly integrated processors
enable developers to get DSP sophistication at a microcontroller price and power consumption.
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Specifications
82-o|| C28/
MCU core with

floating-point option
|CU |a||| ||cr 40 |H/ up |c
800 |H/ a|d O00 |||0P
||du||] |ead|| Pw| a|d AOC
control peripherals
0||] p|c:ec| W||| |u|| c||Wa|e
compatibility between fixed-point and
floating-point
A|| C28/ :c|||c||e| a|e AEC 0-100
qualified for automotive applications
Applications
Green energy (solar, wind, fuel cells), digital
motor control (home appliances, industrial
drives, medical), Intelligent LED Lighting,
digital power supplies (telecom and server
rectifiers, wireless basestations, UPS),
automotive (HEV/EV, electric power
steering, drivers assistance radar, wipers,
HVAC), Power Line Communications
Features
||du||]' rc| e|||:|e|| C :crp||e|
for 32-bit controllers
Up |c 800-|H/ cpe|a||c|
S|||e-p|e:||c| 82-o|| ||ca|||-pc|||
unit on select devices
U|||a-|a| |||e||up| |epc|e ||re
|||e|a|ed |ea|-||re deou|| |rp||||e
control system development
S|||e-:]:|e 82 / 82-o||
multiply-accumulate
|u|||p|e :crru||:a||c| |||e||a:e
including Ethernet and USB
A|a|c |||e|a||c| |c |edu:e o||| c|
materials costs and simply design
Cc|:e||c AR| + C28/ de.|:e c||e|||
the best ofC28x control and ARM
connectivity
Peripherals
Up |c o12-|B ||a| a|d O8-|B RA|
U|||a-|a| 12-o|| A/O :c|.e||e| W||| up
to 80-ns conversion time
H||-|ec|u||c| Pw| a||cW du|]-:]:|e
modulation down to 55-ps accuracy
||e/|o|e Pw| e|e|a||c| a||cW ea]
generation of any switching waveform
0uad|a|u|e e|:cde| |||e||a:e a|d
capture peripherals for easy motor
feedback
Ccde e:u|||] rcdu|e W||| 128-o||
password protection
|u|||p|e :crru||:a||c| |||e||a:e
C2000
Microcontrollers, Fixed-Point and Floating-Point

MCU Real-time Control, 32-Bit Performance
Get samples, data sheets, tools and app guides at: www.ti.com/c2000
Concerto
(144 pins)
$<7 $20
MIPS
300
150
100
80
60
40
Connectivity and
performance
Delno
(176 256 pins)

$9 $16
Floating Point
performance
Piccolo
(38 100 pins)

$<2 $8
Floating Point
with co-processor
options
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100+ Code compatible devices All pricing is to be considered budgetary and subject to change. Pricing is 1KU -40 to 50 C.
Fixed- Point
with co-processor
options
Fixed- Point
low cost
C2834x
F28M35x
Sampling
Next
Future
Next
F28M35x Next
60-100 MHz M3
60-150 MHz28x FPU
Industrial safety
512 KB-1MB Flash
Ethrnet, USB OTG, VCU
Performance
Connectivity
Safety enhancements
Next
C2834x F2833x
Up to 600 MFLOPS
196-516 KB SRAM
External ADC
Low active power
Up to 300 MFLOPS
128-512 KB Flash
52-68 KB SRAM
F2806x Next
90 MHz 28x, 90 MHz CLA
Co-processor, FPU, VCU
128-256 KB Flash
36-100 KB RAM
DMA, USB FS host
Performance
Memory
Connectivity
F2803x
60 MHz 28x
60 MHz CLA co-processor,
64-128 KB Flash,
20kB RAM
F2802x Next
40-60 MHz,
32-64 KB Flash,
6-12 KB RAM
Low power
Small packaging
More analog
F2833x
F2806x
F2803x
F2802x Development Production
ENET
USB
CAN
CAN
CAN
CAN
CAN
USB
F2823x
F281x
F280x
F2801x
TMS320C2000 Microcontroller Platform Roadmap
The C2000
controller platform provides an optimized combination of DSP performance

and MCU integration for digital control systems.
High Voltage Motor
Control & PFC Kit
DC/DC LED
Lighting Kit
High Voltage
Bridgeless PFC Kit
F28069 Piccolo
USB Stick
Access the latest C2000 MCU software, documentation, and more through controlSUITE software.
Download today at www.ti.com/controlsuite
Piccolo
Microcontrollers
Real Control. Real Time. For Real Systems.
Highly-integrated microcontrollers for real-time control
of cost-sensitive power electronics applications. With
control-optimized performance, specialized peripherals,
and a control-focused architecture, Piccolo MCUs bring
innovation solutions to demanding control challenges.
Delno
Microcontrollers
High Performance. For High End Control.
The leading microcontroller platform for high performance
control needs. With up to 300 MHz performance, industry
leading PWM control resolution, and blazing ADC conver-
sion speeds, Delno MCUs tackle the toughest control
challenges.
Concerto
Microcontrollers
Connectivity. Control. No Compromise.
Differentiated microcontroller platform combining the
ARM
Cortex
-M3 core with C2000s C28x core in

a single MCU package. Concerto MCUs bring together
leading host communications and leading real-time
control without compromise of control performance or
communications.
Starting
at $1.50
Packages
from 38
to 100
pins
Starting
at $8.95
Packages
from 176
to 256
pins
Starting
at $6.71
Packages
from 144
pins
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Key Applications
|cW-pcWe| W||e|e app||:a||c|
Cc|ure| e|e:||c||:
U|||||] re|e|||
|||e|||e|| e||| a|d :c|||c|
Pc||ao|e red|:a| a|d ||||ure||a||c|
Se:u|||] ]|er
Key Features
Ultra-low-power (ULP) architecture
and flexible clock system extend
battery life:
0.1-A RAM retention
<1-A RTC mode
<100 A MHz
Integrated intelligent peripherals
including a wide range of high-per-
formance analog and digital peripher-
als that off-load the CPU
asy-to-0se 16-bit RISC CPU
architecture enables new applications
with industry-leading code density
asy to get started: Complete
development ecosystem with tools
|a|||| a| $4.80
ohaoced ||brar|es to benefit several
applications such as capacitive touch,
metering metrology, low power
design and debugging
MSP430
Microcontrollers
Ultra-Low Power, Easy-to-Use, 16-Bit RISC Microcontrollers
Get samples, data sheets, tools and app reports at: www.ti.com/msp430
MSP430 portfolio overview
L092
0.9V-1.65V
Speed: 4 MHz
ROM: Up to 2Kb
RAM: Up to 2Kb
GPIO: 11
F1xx
Speed: 8 MHz
Flash: 1-60Kb
RAM: Up to 10Kb
GPIO: 14-48
FRAM
Speed 24 MHz
FRAM 4-16kB
GPIO 14-28
Non-volatile
memory
MSP430
16-bit RISC CPU

All devices feature:
DAC8
Comp
SVS
BOR
WDT
A-POOL
ADC8
G2xxx
Speed: 16 MHz
Flash: 0.5-16Kb
RAM: Up to 512b
GPIO: 10-24
F2xx
Speed: 16 MHz
Flash: 1-120Kb
RAM: Up to 8Kb
GPIO: 10-64
BOR BOR
ADC10, 12
Comp
DAC12
DMA
MPY
SVS
USART
BOR
SVM
LDO
ADC10
ADC12
USCI
DMA
SVS
BOR
ADC10
Comp
Temp
USCI
UART
Cap sense
I/Os
ADC10,12
SD24
Comp
DAC12
DMA
F4xx
Speed: 8/16 MHz
Flash: 4-120Kb
RAM: Up to 8Kb
GPIO: 14-80
ADC10,12
BOR
All Devices
LCD
SD16
Comp
DAC12
OpAmp
MPY
SVS
USART
USCI
SIF
ESP430
Basic
Timer
WDT+
WDT
RTC_C
F5xx/6xx
Speed: 25 MHz
Flash: 8-256Kb
RAM: Up to 18Kb
GPIO: 32-83
SVM
SVS
LDO
MPY
USCI
DMA
Some Devices
Comp
RTC
MPY
OpAmp
SVS
USCI
USI
DMA
OpAmp
MPY
SVS
USART
USCI
SCAN_IF
ESP430
Basic
Timer
WDT+
RTC
Ultra-Low Power Performance Analog Integration Easy-to-Use
BOR BOR
P
M
M
LCD LCD
SD24
CC430
Speed: 20 MHz
Flash: 8-16Kb
RAM: Up to 4Kb
GPIO: 40
SVM
SVS
LDO
MPY
USCI
DMA
Sub 1 GHz
RF
AES
ADC12
Comp
RTC
P
M
M
16-b|t t|mers
watchdog t|mer
|oteroa| 0|g|ta||y
Controlled Oscillator
xteroa|
crystal support
<50 oA p|o |eakage
<6 s wake0p
ADC10
USB
P
M
M
MSP430x1xx - ||a|/R0|-oaed |CU
offering 1.8-V to 3.6-V operation, up to 60
KB, 8 MIPS and a wide range of peripherals.
MSP430F2xx - ||a|-oaed |ar||] |ea|u|-
ing even lower power and up to 16 MIPS
with 1.8-V to 3.6-V operation. Additional
enhancements in clude 1 percent on-chip
very-low-power oscillator, internal pull-up/
pull-down resistors and low-pin-count
cp||c|. ||a|-oaed |CU W||| 1.8V - 8.OV
cpe|a||c|, up |c 1O|B ||a| a|d up |c o12
B RAM. MSP430G2xx2 and MSP43G2xx3
provide unique capacitive touch sense I/O
ports.
MSP430x4xx - ||a|/R0|-oaed de.|:e
offering 1.8-V to 3.6-V operation, up to
120-|B ||a|/R0|, 8 a|d 1O ||PS W||| |||
+ SVS along with an integrated LCD control-
ler. Ideal for low-power metering and medical
applications.
MSP430F5xx/6xx New flash-based
microcontroller family featuring the lowest
power consumption and performance up to
25 MIPS. It offers a wide operating voltage
|a|e ||cr 1.8 V |c 8.O V. |ea|u|e ||:|ude
an innovative power management module
for optimizing power consumption, an inter-
nally controlled voltage regulator, integrated
LDC driver on select devices and a wide
range of memory options up to 256 KB.
MSP430FR57xx 16-bit microcontroller
|ar||] |ea|u||| eroedded |RA| rerc|].
Cuts the industrys lowest active power con-
sumption by 50%, operating at less than
100uA/|H/. |ea|u|e W|||e peed 100/
faster than flash-based MCUs and virtually
unlimited write endurance. True unified
memory means designers can partition the
memory between code or data depending
on the application.
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|a|e |e||e| |||e e||r||a|e
accumulator bottleneck
0p||r|/ed |c| C a|d aero|e|
programming
Ccrpa:| :c|e de|| |edu:e pcWe|
and cost
Up |c 1O ||PS c| pe||c|ra|:e a.a||ao|e
The MSP430
MCUs orthogonal architec-

ture provides the flexibility of 16 fully
addressable, single-cycle 16-bit CPU
registers and the power of a RISC. The
modern design of the CPU offers versatility
using only 27 easy-to-understand instruc-
tions and seven consistent addressing
modes. This results in a 16-bit low-power
CPU that has more effective processing, is
smaller-sized and more code-efficient than
other microcontrollers. Develop new ultra-
low power, high-performance applications
at a fraction of the code size.
16-Bit RISC CPU
R15
R4 General Purpose
General Purpose
RO/PC Program Counter
R1/SP Stack Pointer
R2/SR/CG1 Status
R3/CG2 Constant Generator
0 15
The MSP430 microcontroller is designed
to provide industry-leading ultra-low
power perform ance. A flexible clocking
system, multiple operating modes and
zero-power always-on brown-out reset
(BOR) are implemented to reduce power
consumption and dramatically extend
battery life. The MSP430 BOR function
is always active, even in all low-power
modes, to ensure the most reliable perfor-
mance possible. The MSP430 CPU archi-
tecture with 16 registers, 16-bit data and
16-/20-bit address buses minimizes
power consuming fetches to memory,
while a fast vectored-interrupt structure
reduces the need for wasteful CPU soft-
ware flag polling. Intelligent hardware
peripheral features were also designed to
allow tasks to be completed more effi-
ciently and independent of the CPU. Many
MSP430 customers have developed
battery-based products that will last for
over 10 years from the original battery.
Ultra-Low Power Checklist:
|u|||p|e cpe|a||| rcde
0.1-A RAM retention
<1-A real-time clock mode
<100A/MHz
|||a||-c| |ao|e |||-peed :|c:|
1.8-V |c 8.O-V cpe|a||c|
Ze|c-pcWe| B0R
<o0-|A p|| |ea|ae
CPU ||a| r|||r|/e CPU :]:|e pe| |a|
|cW-pcWe| pe||p|e|a| cp||c|
Ultra-Low Power Performance
|cW-||e(ue|:] au/|||a|] :|c:| |c|
ultra-low power standby mode
H||-peed ra|e| :|c:| |c|
high-performance processing
S|ao||||] c.e| ||re a|d |erpe|a|u|e
The MSP430 MCU clock system is
designed specifically for battery-powered
applications. Multiple oscillators are uti-
lized to support event-driven burst activity.
A low-frequency auxiliary clock (ACLK) is
driven directly from a common 32-kHz
watch crystal or the internal very-low-
power oscillator (VLO) with no additional
external components. The ACLK can be
used for a background real-time clock self
wake-up function. An integrated high-
speed digitally controlled oscillator (DCO)
can source the master clock (MCLK) used
by the CPU and sub-main clock (SMCLK)
used by the high-speed peripherals. By
design, the DCO is active and stable in
1 , (|2//, c| < O , (/1//, /4//, |o//,.
MSP430 device-based solutions efficiently
use 16-bit RISC CPU high performance
in very short burst intervals. This results
in very high performance and ultra-low
power consumption.
Flexible Clock System
32.768 kHz
Control
Crystal
Digitally
Controlled
Oscillator
Very-Low Power
Oscillator (VLO)
Up to 20 kHz
f
ACLK 32 kHz
MCLK 100 kHz 16 MHz
Low-Power Peripherals
CPU and Peripherals
Multiple oscillator clock system
The MSP430 CPU core with sixteen 16-bit
registers, 27 core instructions and seven
addressing modes results in higher processing
efficiency and code density.
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Production
Sampling
Development
Concept
Available now
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2012 2013
AM37x
16hz
LP0081
10k0 $12 - $24
Cortex-A8
AM35x
600Nhz
10l100 oet, 0Ah
LP0081l0082
10k0 $12 - $17
Cortex-A8
AM18x
375l450Nhz
10l100 oet, SATA
S08ANlLP0081l0082
10k0 $5 - $8
A8N9
Cortex-A8
AM335x
0p to 720 Nhz
16-oet sw|tch,
TS0lA00
LP0081l0082l0083
10k0 $8 - $20
ICSS = P80 |od0str|a| comm0o|cat|oo
s0b system
= 30 graph|cs acce|erator
= 8eceot|y aooo0oced
3D
0ortex-A9
AN43x hext
|ocreased A8N
performance
|ocreased |oterIace
opt|oos
|ocreased sec0r|ty
Ieat0res
ARM
Cortex-A8
up to
720* MHz
L3/L4 Interconnect
32K/32K L1 w/ SED
PowerVR
SGX
3D Gfx
20 M/Tri/s
24-bit LCD Control (WXGA)
EtherCAT
PROFINET
Ethernet/IP
and more
Touch Scr. Control (TSC)**
USB 2.0 OTG
+ PHY 2
EMAC 2port
10/100/1G
w/1588 and
switch
(MII, RMII, RGMII)
256K L2 w/ ECC
64K RAM
Graphics Display
AM335x Processor
PRU-ICSS
MMC/SD/
SDIO 3
GPIO
Parallel
LPDDR1/DDR2/DDR3
NAND/NOR
(16b ECC)
Memory Interface
EDMA
Ti mers 8
WDT
RTC
eHRPWM 3
eQEP 3
eCAP 3
JTAG/ETB
ADC (8 ch)
12-bit SAR**
System
UART6
SPI 2
I
2
C 3
McASP 2
(4 ch)
CAN 2
(2.0B)
Serial Interface
* 720 MHz only available on 15x15 package. 13x13 is planned for 500 MHz.
** Use of TSC will limit available ADC channels.
SED: Single error detection/parity.
Security
w/crypto acc.
64K
Shared RAM
Sitara
ARM
Cortex
-A8 and ARM9

Processors
High-Performance, Low-Power Processors
Get samples, data sheets, tools and app reports at: www.ti.com/sitara
Sitara ARM Microprocessor Roadmap
By utilizing ARM processors and common peripheral sets, Sitara ARM processors offer highly
reusable software code bases that allow designers to easily scale within the product family.
Multiple operating frequencies, 3-D graphics acceleration, multiple packaging options and
temperature operating points further provide optimal flexibility to fit most application requirements.
Specifications
Cc||e/-A8 a|d AR|9 p|c:ec|
0p||c|a| |||-pe||c|ra|:e 8-O |ap||:
accelerator
P|c|arrao|e |ea|-||re u||| |CSS
Rcou| d|p|a] cp||c|
0p||r|/ed |c| |cW-pcWe| app||:a||c|
A|d|c|d, |||u/ a|d oaepc||
Automation and control, human machine
interface, medical, portable data terminals
Key Features
AM335x ARM Cortex-A8 processors
Up |c /20|H/ AR| Cc||e/-A8
Optional 3D Graphics Accelerator with
up to 20M/tri/s performance
Suppc|| |c| |POOR1/OOR2/OOR8
Memory < 7mW standby power
PRU-|CSS Suo]|er p|c.|de
additional device flexibility
0p||c|a| uppc|| |c| oc|| E||e|CAT
a|d PR0||BUS
|||e|a|ed oE 2-pc|| SW||:|
CA\ / 2, USB+PH\ / 2, C|]p|c
800-|H/ a|d 1-H/ p|c:ec|
Up |c 80 pe|:e|| |cWe| pcWe|
O|p|a] uo]|er W||| p|:|u|e-||-p|:|u|e
8-O |ap||: e|||e oaed c| |ra||a||c|
Technologys POWERVR SGX graphics
accelerator
O00-|H/ p|c:ec|
Suo-1-w pcWe| :c|urp||c|
8.8-V a|d 1.8-V |/0
O|p|a] uo]|er W||| p|:|u|e-||-p|:|u|e
AM18x and ARM9 processors
8/o-|H/ a|d 4o0-|H/ AR|9 p|c:ec|
SORA|/OOR2/rOOR rerc|] cp||c|
Key Peripherals
ARM Cortex-A8 processors
Gigabit Ethernet MAC
PCIe2.0 + PHY
DMA
CAN
SATAII + PHY
USB |c| /8, USB 2.0 0T, ||C/SO :a|d
interface x3, 1.8-V input/output and display
subsystem with LCD controller and video
encoder with composite and S-video support
OOR2 uppc||, |||e|a|ed CA\ :c|||c||e|,
Cc||e:||.||] cp||c| W||| |||-peed USB
2.0 0|-T|e-c (0T, W||| ou|||-|| PH\,
10/100 EMAC
AM18x ARM9 processors
SATA, uPP, .|dec |/0 |c| :are|a a|d c||e|
video input options
AM17x ARM9 processors
USB 1.1 a|d USB 2.0 :c||e:||.||], 10/100
Ethernet MAC, LCD controller
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Why Choose Cortex-M?
Cortex-M is the MCU version of ARMs V7
instruction set architecture family of cores:
0p||r|/ed |c| |||e-:]:|e ||a| uae
Oe|e|r|||||:, |a| |||e||up| p|c:e||.
always 12 cycles, or just 6 cycles with
tail chaining
T||ee |eep rcde W||| :|c:| a|||
for low power
S|||e-:]:|e ru|||p|] ||||u:||c| a|d
hardware divide
A|cr|: cpe|a||c|
AR| T|uro2 r|/ed 1O-/82-o||
instruction set
1.2o O||PS/|H/ - oe||e| ||a|
ARM7 and ARM9
E/||a deou|| uppc|| ||:|ud||
data watchpoints and flash patching
Capao|||||e c| ||e ||4| e||e u|| ||e
Cc||e/-|4| |e:||c|c].
S|||e-:]:|e ru|||p|]-a::uru|a|e
(MAC) instructions
0p||r|/ed S||O a||||re||: a|d
saturating arithmetic instructions
|EEE /o4 |a|da|d :crp||a|| |||e
precision floating point unit
Why Choose the Stellaris
Family?
Designed for serious microcontroller
applications, the Stellaris family provides
the entry into the industrys strongest
ecosystem, with code compatibility
|a||| ||cr $1USO |c 1 H/.
Supe||c| |||e|a||c| a.e up |c
$8.28 USO || ]|er :c|
|c|e ||a| 180 S|e||a|| |ar||]
members to choose from
Rea| |CU P|0 - a|| :a| e|e|a|e
interrupts, are 5-V-tolerant and have
programmable drive strength and
slew- rate control
Ad.a|:ed :crru||:a||c| :apao|||||e,
||:|ud|| 10/100 E||e||e| |AC/PH\,
USB and USB OTG and CAN controllers
Scp||||:a|ed rc||c|-:c|||c| uppc|| ||
hardware and software
Bc|| a|a|c :crpa|a|c| a|d AOC
functionality provide on-chip system
options to balance hardware and
software performance
Oe.e|cpre|| | ea] W||| ||e
royalty-free StellarisWare
Software
Stellaris
family block diagram

Overview
TI Stellaris MCUs are the industrys
leading family of robust, real-time
microcontrollers based on the
revolutionary Cortex-M technology
from ARM. The award-winning
Stellaris 32-bit MCUs combine
sophisticated, flexible mixed-signal
system-on-chip integration with
unparalleled real-time multitasking
capabilities. Complex applications
previously impossible with legacy
MCUs can now be accommodated
with ease by powerful, cost-effective
and simple-to-program Stellaris
MCUs. With more than 280 devices,
the Stellaris family offers the widest
selection of precisely compatible
MCUs in the industry.
The Stellaris family is positioned for
cost-conscious applications requiring
significant control processing and
connectivity capabilities, including
motion control, monitoring (remote,
fire/security, etc.), HVAC and
building controls, power and energy
monitoring and conversion, network
appliances and switches, factory
automation, electronic point-of-sale
machines, test and measurement
equipment, medical instrumentation,
and gaming equipment.
In addition to MCUs configured for
general-purpose real-time systems,
the Stellaris family offers distinct
solutions for advanced motion control
and energy-conversion applications,
real-time networking and real-time
internetworking, and combinations
of these applications including
connected motion control and hard
real-time networking. Welcome to the
future of microcontrollers.
Stellaris
32-Bit ARM
Cortex
-M MCUs
Get samples, data sheets, tools and app reports at: www.ti.com/stellaris
ARM Cortex-M4F MCU -
Evaluate Cortex-M4 with floating point
with the EK-LM4F232 kit
ARM Cortex-M3 MCU -
Evaluate with the fun EK-EVALBOT kit
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Communications
Optimized
Multicore
General
Purpose
Multicore
High
Performance
Single Core
C6670
4 066x core 1.2 6hz
A|F2, P0|e, 8ap|d|0
6N8 oI L2 Packet,
crypto and
Communications
accelerator
40om
Production
Sampling
F0t0re
Development
06654
S|og|e core @850
MHz
Power opt|m|zed
06672
2 066x core 1.256hz
P0|e, TS|P, 0083
8ap|d|0, S6N||
5N8 oI L2
Packet, crypto acc.
40om
06671
1 066x core @1.256hz
P0|e, 0083, 8ap|d|0,
GbE
4.5 N8 oI L2
40om
06674
4 066x core 1.256hz
P0|e, TS|P, 0083
8ap|d|0, S6N||
8N8 oI L2
Packet, crypto
co-processor
40om
C6655
2x 066x core @1.0
GHz each
Power eg0|pmeot
0667x
8+ 066x core at
1.25+ 6hz
06678 shr|ok to
28om
066xx
(S|og|e core oext)
1 066x+ core at
1.4+ 6hz
008-3
06678
8 066x core 1.256hz
P0|e, TS|P, 0083
8ap|d|0, 6b
8N8 oI L2
Packet, crypto acc.
40om
066xx (oext)
0omm0o|cat|oos
So0 hext
066x +
0omm0o|cat|oos
aod 8ad|o
28om
Ava||ab|e oow 2h12
Specifications
Ccde :crpa||o|e oe|Wee| CO4/
and
C66x platforms
||du||]' |||| 10|/ OSP W|||
820 |AC /1O0 ||0P
COO/ | a ||ue ||/ed a|d ||ca|||
point DSP
Suppc|| T|' |eW |e]S|c|e
multicore architecture
Be| pcWe| pe| pe||c|ra|:e
|u|| e| c| de.e|cpre|| c||Wa|e,
tools & complier
Target Markets
t .JTTJPO$SJUJDBM
Military & defense
Public safety
Satellite
5FTU"VUPNBUJPO
Smart camera
Currency counter
Video analytics server
)JHI1FSGPSNBODF$PNQVUF
Counterfeit & verification
Composition & purity
Oil & gas
$PNNVOJDBUJPOT/FUXPSLJOH
Small cell base station
Media gateway
Session border controller
$MPVE$PNQVUJOH
Cloud computing server
Cloud RAN
Thin client server
C66x KeyStone Features
|e]S|c|e A|:|||e:|u|e - |u|||:c|e
SoC architecture for highest
performance
|e]S|c|e Sc||Wa|e - Sc||Wa|e &
programming model support for ease
of use & performance
|e]S|c|e Tcc| - Tcc| |c| de||.e|-
ing singe core simplicity for multi-
core performance
|e]S|c|e Pa|||e| - Pa|||e|
network for quick development
C6678 Processor Block Diagram
For developers of products in mission critical, medical imaging, test and automation and high-
perfor mance computing markets,TIs TMS320C6672/74/78 (C667x) DSP family offers the industrys
first 10-GHz DSP. Based on TIs KeyStone multicore architecture, and integrated with the new and
innovative C66x DSP core, C6672/74/78 devices come with two, four or eight cores, respectively.
C6000 Multicore Roadmap
C64x & C66x multicore DSPs provide the highest performance solutions for various
market segments.
TMS320C66x DSP Generation, Fixed- and Floating-Point
High Performance Multicore DSPs
Get samples, data sheets, tools and app reports at: www.ti.com/NVMUJDPSF
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Key Applications
Industrial/medical applications
||du|||a| au|cra||c| a|d :c|||c|
Sa|e|] P|c|arrao|e |c|: Cc|||c||e|
(PLCs)
PcWe| e|e|a||c| a|d d||||ou||c|
Tu|o||e a|d W||dr|||
Ve||||a|c| a|d de||o||||a|c|
|||u|c| a|d ||u||| purp
Transportation applications
B|a||| ]|er (ABS a|d ESC,
E|e:|||: pcWe| |ee||| (EPS,
HEV/EV ||.e||e| ]|er
Ae|cpa:e
Ra||Wa] :c|||c|, :crru||:a||c|
and signaling
0||-|cad .e||:|e
Au|crc||.e ||||a||u:|u|e
Ccrre|:|a| .e||:|e
0||-|cad .e||:|e
A||oa, e|e:|||: pa|| o|a|e, a|e
communication, parking assist
Key Features
RM4x Safety MCUs
AR| Cc||e/-R4| :c|e W||| ||ca|||-pc|||
support
Up |c 220 |H/
|c:||ep a|e|] |ea|u|e ou|||-|| |rp|||]
SIL-3 applications
Up |c 8-|B ||a|/2oO-|B RA| W||| ECC
|erc|] p|c|e:||c| u||| || CPU a|d O|A
|u|||p|e |e|Wc|| pe||p|e|a|.
Ethernet, USB, CAN
Dual Timer Co-processors with up
to 44 pins
Dual12-bit analog/Digital Converters
External memory interface
TMS570LS Safety MCUs
AR| Cc||e/-R4| :c|e ||ca|||-pc||| uppc||
Up |c 180 |H/
|c:||ep a|e|] |ea|u|e ou|||-|| |rp|||]
SIL-3/ASIL D applications
Up |c 8-|B ||a|/2oO-|B RA| W||| ECC
|erc|] p|c|e:||c| u||| || CPU a|d O|A
|u|||p|e :crru||:a||c| pe||p|e|a|.
- E||e||e|, ||e/Ra], CA\, ||\, SP|
Dual Timer Co-processors with up
to 44 pins
12-bit analog/Digital Converters
External memory interface
TMS470M Safety MCUs
80-|H/ Cc||e/-|8 CPU
Up |c O40-|B ||a| / O4-|B RA| W|||
ECC protection and EEPROM emulation
S|||e 8.8-V upp|] (V|e c|-:||p,
|u|||p|e :crru||:a||c| |||e||a:e
2 CAN, 2 MibSPIs, 2 LIN/UART
- ||e/|o|e ||re| rcdu|e (1O :|,
10-bit analog/digital converter (16 ch)
Safety features (ECC, BISTs, CRC)
Pin and software compatible family
Embedded debug module
Hercules
Safety Microcontrollers
Make the world safer with the new Hercules safety MCU platform
Get samples, data sheets, tools and app guides at: www.ti.com/IFSDVMFT
Hercules RM4x and TMS570 Integrated Safety Features
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Specifications
Up |c 1.8oH/ Cc||e/-A8
1H/ CO/4/ OSP
S/o80 8O |ap||: e|||e de||.e|
up to 30 MTriangles/s
Up |c |||ee p|c|arrao|e |||-de||||||c|
video image coprocessing engines for
1080p/60
P|c|arrao|e :c|e |c |edu:e :crp|e/||]
of system software
Video encode/decode/transcode/transrate,
video security, video conferencing, video
infrastructure, media server, IP phone, thin
client and digital signage.
DM36x
Key Features
H||-pe||c|ra|:e d|||a| red|a
System-on-Chip (DMSoC)
Up |c 800-|H/ AR|9
TWc .|dec |rae :c-p|c:ec|
(HDVICP, MJCP) engines
V|dec p|c:e|| uo]|er |ea|u|||
enhanced MPEG/JPEG coprocessor
Key Peripherals
10/100| E||e||e| |AC
USB pc|| W||| |||e|a|ed 2.0
H||-Speed PH\
TWc UART (c|e |a| UART W||| RTS
and CTS flow control)
||.e Se||a| Pc|| |||e||a:e (SP|, ea:|
with two chip-selects
DM8148
Key Features
1/ 1080p80
Up |c 1|/ Cc||e/-A8
CO/4/ OSP
S/o80 8O |ap||: e|||e de||.e|||
18MTriangles/sec
1-e||e||e| W||:|
PC|e, |POOR/ OOR2/OOR8
DM8168
Key Features
Up |c 8/ 1080pO0
Up |c 1.8oH/ Cc||e/-A8
CO/4/ OSP
S/o80 8O |ap||: e|||e de||.e|||
18MTriangles/sec
PC|e, OOR2/OOR8
2/ 1-e||e||e|
Up |c 8/ d|p|a]
DaVinci Roadmap
TMS320DM816x SoC Block Diagram
The high-performance DM8168 DaVinci video processor offers 3x the video streaming capability
over competing solutions enabling customers to build video-centric systems that
capture, encode, decode and analyze multiple video streams simultaneously on up to three
independent displays.
Fixed/Floating
point DSP
C674x
DSP Core
Switched Central Resource (SCR)
Peripherals
ARM
microprossor
ARM
Cortex A8
HD video
coprocessor
(x3)
Display
3D graphics
engine
Video I/O
On-screen
display
Resizer
SD DAC
(x3)
PCIe
2 lanes
McASP x3
SPDIF
McBSP
I
2
C x2 UART x3
Memory interfaces
DDR3 x2 SDIO/IO
Async
EMIF/NAND
SATA2
x2
SPI
USB 2.0
x2
GPIO
GMII
EMAC x2
HD DAC
(x3)
HDMI PHY
HD video
I/O (x2)
30 graph|cs
Face recogo|t|oo
Vo|ce recogo|t|oo
F0|| body track|og
S|og|e- or m0|t|-0ser
30 depth (0p to V6A++)
20 868 (720p to I0|| h0)
haod track|og
30 depth (0p to 00V6A)
20 868 (720p to I0|| h0)
haod track|og
Face detect|oo
haod track|og
Face detect|oo
Face recogo|t|oo
1080p h.264 30Ips
haod track|og
Face detect|oo
1080p h.264 30Ips
haod track|og
0pper body track|og
8ackgro0od s0bst|t0t|oo
Face detect|oo
F0|| body track|og
30 graph|cs
ohaoced speed
Face recogo|t|oo
Vo|ce recogo|t|oo
1080p h.264 30Ips
N0|t|p|e I0|| body track|og
8ackgro0od s0bst|t0t|oo
A0gmeoted rea||ty
0|g|ta| s|goage
Face detect|oo
Face recogo|t|oo
Vo|ce recogo|t|oo
V|deo cooIereoc|og
Stereoscop|c 30 (S30) 720p
0NAP 4l0N8148 Ieat0res, p|0s:
1080p h.264 60Ips
Stereoscop|c 30 (S30) 1080p 30Ips
w|re|ess d|sp|ay (0p to 1080p 60Ips)
8ea|-t|me Iacelvo|ce detect|oolrecogo|t|oo
V6A++ 30 seosor |oterIace (0S|3)
N0|t|p|e I0|| body track|og
30 graph|c a0gmeoted rea||ty
20l30 |mage recoostr0ct|oo
0epth recogo|t|oo aod aoa|ys|s
S30 v|deo cooIereoce
0N3730
Processor
0NAP 4
Processor
0NAP 5
Processor
0NAP 3
Processors
AN335x
NP0s
AN37x
NP0s
0N368
Processor
0N385
Processor
0N8148
Processor
Value line
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DaVinci
Video Processors: Optimized for Digital Video

Best-in-class video solution
Get samples, data sheets, tools and app reports at: www.ti.com/EBWJODJ
www.eecataIog.com/dsp DeveIopment TooIs 35
CONTACT INFORMATION
Kentec Display
Kentec Display
(852)95121814 Telephone
t.liang@kentecdisplay.com
http://www.kentecdisplay.com
2, Interface,
two interface options available for customer selection

3 LCD driver code examples
ht t p: / / www. kent ecdi spl ay. com/ Downl oads/ Ken-
tec320x240x16_ssd2119_8bit.c
LM4F232/LM4F120 LCD
Interface Expansion Board
(Stellaris Boosterpack)
1 EB-LM4F232/LM4F120-LCD Overview
The EB-LM4F232/LM4F120-LCD is an extension board
for the EK-LM4F232 Development Board and Stellaris
LaunchPad (see Figure 1).
Figure 1. LCD expansion board for EK-LM4F232 and
Stellaris LaunchPad
The expansion board has build in LED backlight driver
circuit and 60pin FPC connector for the following Kentec
TFT LCD modules
- 3.2 QVGA TFT module: K320QVG-V1-F;
- 3.5 QVGA TFT module: K350QVG-V2-F;
- 4.3 480*272dots TFT module: K430WQC-V3-FF;
- 5.0 WVGA TFT module: K50DWN2-V1-FF;
- 7.0 WVGA TFT module: K70DWN2-V1-FF;
- 9.0 WVGA TFT module: K90DWN2-V1-FF.
The above TFT modules are also compatible to TI Cortex
M3 development kits
- DK-LM3S9D96
- RDK-IDM-L35
- RDK-IDM-SBC
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P1 Pin Symbol EK-LM4F232 Descript ion
1 LCD_D17 PJ7 Data bit 17 for LCD
2 GND GND Ground (0V)
3 LCD_CS PL5 Chip select signal for LCD
4 LCD_RST PL4 Reset input for LCD
5 LCD_RS PL3 Register/Data select
signal for LCD
6 LCD_RD PL2 Read control signal for LCD
7 LCD_WR PL1 Writecontrol signal for LCD
8 NC PL0 Noconnection
10 TOUCH_YN PK7
11 TOUCH_XN PK6
4-wire resistor touch screen
terminal
12 NC PK5 Noconnection
13 NC PK4 Noconnection
14 3.3V 3.3V Power supply(3.3V)
2-9 NC PF0 - PF7 Noconnection
11 LCD_BL PG3 LCD backlight control signal
12-13 NC PG6 - PG7 Noconnection
15-18 NC PH0 - PH3 Noconnection
20 TOUCH_XP PK3
21 TOUCH_YP PK2
terminal
22-23 NC PK1 - PK0 Noconnection
25-26 NC PA6 PA7 Noconnection
27 3.3V 3.3V Power supply(3.3V)
J1 Pin Symbol LaunchPad Descript ion
1 3V3 +3.3V Power supply
2 LCD_D5 PB5 Data bit 5for LCD
5 TOUCH_XP PE4
6 TOUCH_YP PE5
terminal
8 LCD_WR PA5 Writecontrol signal for LCD
9 LCD_RS PA6 Register/Data select for LCD
10 LCD_CS PA7 Chipselect for LCD
1 GND GND Ground
3 NC PE0 Noconnection
4 NC PF0 Noconnection
5 RESET RST
Reset signal for LCD/MCU
8 LCD_RD PA4 Readcontrol signal for LCD
9 TOUCH_XN PA3
10 TOUCH_YN PA2
terminal
1 5V0 VBUS Power supply
2 GND GND Ground
3 NC PD0 Noconnection
1 LCD_BL PF2 LCD backlight ON/OFF
control
3 LCD_D3 PB3
Data bit 3for LCD
4 NC PC4 Noconnection
Interface Option 1.
For EK-LM4F232
Interface Option 2. For
Stellaris LaunchPad
CONTACT INFORMATION
36 DeveIopment TooIs Embedded Processing & DSP Resource Guide 2013
Link Research
Link Research
131 Fairview Street
Providence, RI 02908
USA
401-270-5221 Fax
sales@link-research.com
www.link-research.com
TECHNICAL SPECS
Analog Input Range: 10 volts.
A/D Channels: Three versions having 4, 8, or 16,
14-bit converters with simultaneous sampling.
D/A Channels: Two versions having 8 or 16, 14-bit
converters with simultaneous updating.
Sampling Rate: 350 kbps using one channel, 100
kbps per channel using all channels.
RS-232 Interface: Operates up to 921.6 kbps
AVAILABILITY
In production since 2006
APPLICATION AREAS
Power Supply Design, Power Factor Correction, Three
Phase Power Inverters, Motor Control, Uninterruptible
Power Supply.
Multi-channel Data Acquisition
daughtercard for the F2812/
F28335 eZdsp Development Kit
Supported TI Processors: F28x Delfno foating-point MCUs,
F28x Fixed-point Series
The Link Research models LR-F2812DAQ and LR-
F28335DAQ daughtercards plug directly into the F2812
and F28335 eZdsp development kits respectively.
The daughtercards feature up to 16 channels of 14-bit,
simultaneous sampling A/Ds, and up to 16 channels of
simultaneous updating D/As. All analog I/O channels fea-
ture a full 10 volt I/O range. A/D sampling rates of up to
350kHz on a single channel, or 100 kHz with all channels
operating are possible.
The standard version of the daughtercard includes an
RS-232 interface with a maximum data rate of 921.6 kbps,
eight digital I/Os, two user LEDs and a Hitachi 44780
compatible LCD display interface (F2812 version only).
Also available as optional interfaces are a fber optic
serial communications interface allowing true galvanic
isolation between the daughtercard and the PC, and an
802.3 compatible Ethernet interface.
The daughtercard ships with everything needed to get
up and running fast, including a 15 volt analog power
pack, a 6 foot RS-232 cable, an extra set of connectors to
be soldered into the eZdsp development kit, and frame-
work software and documentation on CD.
FEATURES & BENEFITS
Adds high precision, multi-channel data conversion
capability to the F2812 or F28335 eZdsp development kit
Includes complete CCS projects demonstrating both
DSP/BIOS software kernel foundation as well as
non-BIOS applications
Optional Ethernet interface includes software dem-
onstrating a web browser JAVA applet model for
accessing development system data.
Achieve a maximum of 16 A/D and 16 D/A channels
by stacking a second daughtercard (model LR-
F2812DAQ8X8/LR-F28335DAQ8X8)
These daughtercards are also available bundled with
a Spectrum Digital eZdsp development system
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CONTACT INFORMATION
Xilinx
FEATURES & BENEFITS
Xilinx Spartan-6 LX150T board
Cables, Power Supply and Compact Flash
Xilinx ISE Design Suite System Edition Software
(device locked to Spartan-6 LX150T)
Includes EDK and System Generator for DSP
The MathWorks Simulink evaluation tools
DSP reference design tutorials
Kit documentation
Avnet Spartan-6 FPGA DSP Kit
Xilinx FPGAs exceed the computing power of DSPs with
their inherent parallelism and offer co-processing methods
of performance acceleration for signal processing. The
Xilinx Spartan-6 FPGA DSP Kit integrates hardware, IP,
software development tools and methodologies together
into solutions that accelerate development for experienced
users and simplify the adoption of FPGAs for new users.
With the addition of targeted reference designs, these
DSP platforms enable users to focus on creating their
own unique differentiation from the very beginning of the
product development process.
This kit includes the Xilinx Spartan-6 LX150T board and
allows users to quickly learn the different tool fows and
design techniques involved in creating DSP centric designs
with the Spartan-6 FPGA family. Traditional RTL design
methodologies are also supported through a design imple-
mentation that uses ISE Design Suite: Logic Edition and
LogicCore DSP IP.
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CONTACT INFORMATION
Xilinx
2100 Logic Drive
San Jose, CA 95124
more_info@xilinx.com
http://www.xilinx.com/products/
boards_kits/dsp.htm
Xilinx
2100 Logic Drive
San Jose, CA 95124
boards_kits/dsp.htm
Xilinx
FEATURES & BENEFITS
Avnet Spartan-6 Development Board including
Spartan-6 LX45T FPGA
Cables, power supply and compact fash
ISE Design Suite: System Edition (Device-locked to
the Spartan-6 LX45T FPGA)
Texas Instruments Code Composer Studio inte-
grated development environment
MathWorks MATLAB evaluation version
Kit documentation
Avnet TI OMAP Processor /
Spartan-6 FPGA Co-Processing Kit
FPGAs can be used to accelerate traditional processor/
DSP systems up to 15X. Conventional system design
methods, however, are insuffcient to meet the require-
ments of todays ultra-high performance applications.
The inherent parallel nature and optimized DSP blocks in
an FPGA enable intelligent co-processing execution of
massive signal processing computations that accelerate
your system to optimally meet your most demanding
performance requirements.
The TI OMAP processor/Spartan-6 FPGA Co-Processing
Development Kit is a sophisticated platform that delivers
breakthrough system performance by integrating and
optimizing the key strengths of high performance FPGAs,
system control processing, and digital signal processing,
all within one single environment. While an ARM9 CPU
provides run control and executes Real Time Operating
Systems like embedded Linux, and a C674X DSP can be
dedicated to specifc signal processing algorithms, a fex-
ible Spartan-6 FPGA can be focused on the performance
bottlenecks to accelerate data path applications.
CONTACT INFORMATION
Marktstr. 10
Kerken, 47647
Germany
+49 2833 570977 Telephone
+49 2833 3328 Fax
info@dsignt.de
www.dsignt.de
D.Module2.C6747: foating-point DSP, 1800 MFLOPS
peak. Interfaces: PWM, Capture/Compare, Quadrature
Encoder, Memory Card, Real-Time Clock, USB Host.
Applications: Industrial Control and Automation.
D.Module2.C6657: ultra-high performance 2-core DSP,
1.25GHz. UPP Interface for high-speed ADC/DACs.
PCIe, SRIO, Gigabit-Ethernet. Applications: Material
Inspection, Machine Vision, Medical Imaging.
D.Module2.ADDA500K16: six analog inputs, two
analog outputs, 16 bit resolution, 500KHz sampling,
calibration. ADC8556 and DAC8822 converters.
D.Module2.6SLX45T: Xilinx Spartan-6 FPGA daughter card
for high-speed data acquisition and preprocessing. I/O
compatible with FMC standard, FMC base board available.
AVAILABILITY
D.Module2.C6657: end 2012, all others in full production.
APPLICATION AREAS
Audio, Broadband, Communi-
cations & Telecom, Industrial,
Medical, Security, Video, Wireless
D.Module2 High-Performance
DSP Processor and I/O Boards
Supported TI Processors: DM64x, C674x Low Power DSP, C67x
DSP, C66x DSPs, C665x Multicore DSPs
The D.Module2 family of DSP and I/O boards make up
a highly integrated and scalable stand-alone signal
processing platform. With a small form factor, modular
design, and stacking capability, these boards are ideally
suited as the heart of your industrial control, material
inspection, imaging, or test & measurement application.
Versatile communication and expansion interfaces ease
system integration. Built-in tools for in-feld updates of pro-
grams, parameters, and reconfguration address the needs
of maintenance-friendly installations. The D.Module2.BIOS
is a system-resident set of functions which encapsulates
hardware dependencies, handles initialization and confgu-
ration, and provides a consistent programming interface
throughout the entire board family. This concept assures
long-term availability and compatibility.
The D.Module2 family features various DSP boards
(DM642, C6747, and - coming soon - C6657). Common to
all DSP boards are processor, power supply, DRAM and
non-volatile memories, USB, Ethernet, RS232/485, GPIO,
synchronous serial ports, and a parallel external bus
interface. Processor and board-specifc peripherals are
brought out on a separate expansion connector. These
DSP boards are accompanied by data acquisition periph-
erals, an FPGA board (Xilinx Spartan 6), and base boards
for prototyping and evaluation.
FEATURES & BENEFITS
Stackable small-sized boards (87x59mm), industry-
standard IEEE1386 high density connectors, 3.3V
single supply, 3.3V IO
On-board memory expansion: DRAM and non-volatile
Flash Memory
Communication Interfaces: USB, Ethernet, UART
(RS232/RS485), SPI, I2C, GPIO
External Parallel Bus Interface and Synchronous Serial
Ports to connect data acquisition peripherals and/or
FPGAs
D.Module2.BIOS system-resident programming support
functions, Utilities for in-feld updates via USB and UART
TECHNICAL SPECS
D.Module2.DM642: high performance fxed-point DSP
board, 5760 MIPS peak. Three Video Capture/Display
Ports with FIFOs. Applications: Ultrasonics, Surveillance,
Video, Biometrics, Machine Vision.
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www.eecatalog.com/dsp DevelopmentTools39
ContaCt InformatIon
114 Sheldon Road
Ithaca, NY 14850
USA
607.266.6000 Telephone
607.266.8221 Fax
sales@traquair.com
www.traquair.com
TECHNICAL SPECS
C6412Compact
720-MHzTITMS320C6412-basedintegerDSPboard
1-MGateor4-MGateSpartan-3FPGA
Upto128-MBSDRAM;upto32-MBbootprogram
ROM
TwoindependentIEEE1394aFireWireinterfaces
forstreamingdatain/outsimultaneously
10/100BaseTxEthernet,USB2.0andRS-232inter-
faces;16-/32-bithostportinterface
AVAILABILITY
Inproductionsince2006
APPLICATION AREAS
Audio, Automotive, Broadband, Communications &
Telecom, Industrial, Medical, Military, Security, Video
andImaging,Wireless
micro-line TMS320C641x-based
Integer DSP/FPGA Boards
Supported TI Processors: C6410/12/13/18
The micro-line series of embedded DSP/FPGA boards
provides embedded systems developers with a tightly
integrated suite of programmable DSP, FPGA and I/O
resourcesinsmall,stand-alone-capableboardformats.
micro-lineC6412CompactandC641xCPUDSP/FPGAboards
target high-performance integer DSP applications using
TexasInstrumentsTMS320C6410/6412/6413/6418DSPs.
The C6412Compact combines Texas Instruments
powerful 720-MHz TMS320C6412 DSP, up to 128-MB
SDRAM, 8- or 32-MB boot program ROM and a high-
density1-MGateor4-MGateXilinxSpartan-3FPGA.
The optionally programmable FPGA greatly expands
processing and interfacing options. Two independent
400-Mbps 1394a FireWire interfaces are included,
enabling simultaneous high-bandwidth video-in/out
for completely integrated video processing. A 64-bit
bus connects the DSP, FPGA, SDRAM and FireWire
resources.On-boardUSB2.0and10/100BaseTxEthernet
interfacesroundofftheimpressivearrayoffeatures.
The C641xCPU family of boards features a smaller
(98-mmx67-mmfootprint)andleanerconfiguration,
withupto64-MBSDRAM,8-MBbootprogramROM,
andahigh-density500-KGate,1-MGate,or1.6-MGate
Spartan-3EFPGA.
Analog I/O daughtercards can also be combined with
theseboards:
ORS-112(16-bitA/D/A)
4-chA/D2.5MSPS;4-chD/A625KSPS
2-chA/D65MSPS;2-chD/A125MSPS
12-chA/D250KSPS;12-chD/A100KSPS
FEATURES & BENEFITS
Smallformfactor,embeddableDSP/FPGAboardsfor
OEMapplications
Suitableforproductdevelopmentandvolumeproduction
User-programmableDSP,optionallyprogrammableFPGA
ExtensiveconnectivityoptionsviaDSP,FPGA,
FireWire,USB,Ethernet,RS-232
OptionalA/D/A
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ContaCt InformatIon
40 Development Tools Embedded Processing & DSP Resource Guide 2013
114 Sheldon Road
Ithaca, NY 14850
USA
607.266.8221 Fax
sales@traquair.com
www.traquair.com
TECHNICAL SPECS
C6713Compact
300-MHzfoating-pointTMS320C6713DSP
Spartan-6(LX45,LX75,LX100,orLX150)orVirtex-
II(250-kGate,500kGate,or1MGate)FPGA;upto
160confgurabledigitalI/Opins
On-board400-MbpsIEEE1394aFireWireinterface;
RS-232interfacealsoincluded
ExternalaccesstoTMS320C6713DSPI/Ointerfaces:
32-bitEMIF,XF0/1pins,timerinput/outputpins,
McASPandMcBSPports,IC,andHostPortInterface
67-mmx120-mmfootprint;ISO9001:2000accred-
itedproductionandCEcertifcation
AVAILABILITY
C6713CompactwithSpartan-6LXFPGA:2012;othersin
productionsince2003
APPLICATION AREAS
Telecom, Industrial, Medical, Military, Security, Video
andImaging,Wireless
micro-line TMS320C6713 DSP-based
Floating-Point DSP/FPGA Boards
Supported TI Processors: C67xDSPs
The micro-line series of embedded DSP/FPGA boards
provides embedded systems developers with a tightly
integrated suite of programmable DSP, FPGA and I/O
resourcesinsmall,stand-alonecapableboardformats.
micro-line C6713Compact and C6713CPU DSP/FPGA
boards target high-performance foating-point DSP
applications using the powerful Texas Instruments
TMS320C6713DSP.
TheC6713Compactincorporatesupto128-MBSDRAM,
8-MBbootprogramROMandanon-board,high-density
XilinxSpartan-6LXorVirtex-IIFPGA(optionallypro-
grammable).TheFPGAgreatlyexpandsprocessingand
hardware interfacing options. An on-board 400-Mbps
IEEE 1394a FireWire interface allows for communica-
tions with other embedded DSP resources, cameras,
sensors and PCs. Software APIs are available to utilize
theFireWireinterfaceforgeneralpurposes,videoframe
capture from cameras, and data storage to hard drives
andCompactFlashmemory.
The C6713CPU offers a smaller (98-mm x 67-mm foot-
print)andleanerconfguration,withupto64-MBSDRAM,
2-MBbootprogramROMandahigh-density400-kGateor
1-MGateXilinxSpartan-3FPGA.
Analog I/O daughtercards can also be combined with
theseboards:
4-chA/D2.5MSPS;4-chD/A625KSPS
2-chA/D65MSPS;2-chD/A125MSPS
12-chA/D250KSPS;12-chD/A100KSPS
FEATURES & BENEFITS
Smallformfactor,embeddableDSP/FPGAboardsfor
OEMapplications
Suitableforproductdevelopmentandvolumeproduction
User-programmableDSP,optionallyprogrammableFPGA
ExtensiveconnectivityoptionsviaDSP,FPGA,
FireWire,RS-232
OptionalA/D/A
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ContaCt InformatIon
Xilinx
Xilinx
2100 Logic Drive
San Jose, CA 95124
boards_kits/dsp.htm
AVAILABILITY
Available now at www.xilinx.com/products/boards-and-kits
Avnet Kintex-7 FPGA DSP Kit
with High-Speed Analog
The Kintex-7 FPGA DSP Kit with high-speed analog
brings digital and analog hardware, development
tools, high-level design methodologies, IP, and veri-
fied reference designs together into a development
platform that accelerates development of DSP appli-
cations for experienced users and simplifies the
adoption of FPGAs for DSP for new users. By com-
bining all the elements of a total solution, users can
focus on the unique value of a design at the beginning
of the design process.
Standard with every kit, the Kintex-7 FPGA DSP Tar-
geted Reference Design includes a DSP datapath
connected to a high-speed analog interface in a loop
back configuration. Xilinx DSP IP is used to create
digital filters used for digital up / down conversion to
the interface. The design is tuned for maximum per-
formance from the Kintex-7 FPGA programmable logic
and the analog interface. Key features of the Kintex-7
FPGA DSP Targeted Reference Design include:
XilinxFIRCompiler
Muxisolationofboththeanaloganddigital
logic for debug
Selectablesinewaveorimpulsepatterngeneration
Dynamicupdatestothedataconvertercon-
figuration registers from the FPGA using
ChipScopeVIOAXI4Streaminginterface
FEATURES & BENEFITS
KC705XC7K325T-2FFG900CEvaluationBoard
4DSPFMC150Dual14-bit250MspsA/D,Dual16-bit
800MspsD/A
FullseatISEDesignSuite:SystemEdition
DevicelockedtotheKintex-7XC7K325TFPGA
ReferenceDesigns,ExampleDesigns,andDemos
Board Design Files
Documentation including Step-by-Step Getting
Started Guide
Cables & Power Supply
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ContaCt InformatIon
42 Development Tools Embedded Processing & DSP Resource Guide 2013
Signum Systems
IAR SYSTEMS INC.
1065 E. Hillsdale Blvd., #420
Foster City, CA 94404
650-287-4250
info@iar.com
www.signum.com
fexibility protects your investment in embedded tools
and simplifes the debugging process. And YES, you can
use almost any ARM C/C++ compiler with JTAGjet: Code
Composer Studio integrated development environ-
ment (IDE), IAR Embedded Workbench for ARM, ARM
RealView, MetroWerks, GDB, Eclipse, Keil, Mentor
Graphics and others. JTAGjet is fully compatible with
TI Code Composer Studio IDE (ARM & DSP) and IAR
Systems C-SPY (ARM) debuggers and most models
come with Chameleon Debugger for ARM capable of
embedded Linux debugging.
Signum Systems Emulators for TI DSPs,
OMAP and DaVinci Processors
Signum Systems JTAGjet line of In-Circuit Debuggers
(emulators) cover the entire line of TI DSP, OMAP,
Sitara and DaVinci processors as well as other ARM
platform-based devices. We offer many preconfgured
models or you can create your own, custom emulator. If
you need more options later, no problem most can be
emailed to you whenever they are needed. This unusual
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CONTACT INFORMATION
CONTACT INFORMATION
Sundance Digital Signal Processing Inc
Sundance Digital Signal
Processing Inc
4790 Cauhghlin pkwy #233
Reno, NV 89519
USA
+1 775 8273103 Tel, West Coast
+1 514 684 0130 Tel, East Coast
salesforce@sundancedsp.com
www.sundancedsp.com
arithmetic on the C67x and simulation for TMS320C6000
DSPs. It can processes real & complex data vectors and matrices.
TECHNICAL SPECS
All libraries are algorithmically optimized and some are
even hand-coded
Functions within GDD libraries are interruptible and give
additional control to time-critical
applications
GDD Libraries help reduce
application time to market
Hand-coded, Optimized DSP/Vector,
LINPACK, EISPACK, and CBLAS Libraries
Supported TI Processors: DaVinci DM64x, DaVinci DM81x, DaVinci
DM64x, DaVinci DM37x, DaVinci DM3x, DM81x Video SoC, DM64x Video
SoC, DM646x, DM644x, DM643x, DM64x, DM37x, DM3x, DM814x,
DM816x, OMAP35x, OMAP3525/30 SoC, TMS320DM37x SoC, TMS-
320DM3x Video SoC, OMAPL1x, C67x DSP, C66x, C64x, C62x DSP, C647x
Multicore, C645x Multicore, C667x Multicore, C665x Multicore, AM35x/
AM37x ARM
Cortex-A8, AM18x ARM9, AM17x ARM9

GDD0300 library functions perform operations like FFT, Fast
Hartley Transform, Discrete Cosine Transform, FIR/IIR flters,
vector operations, complex-number arithmetic, and more.
GDD7000 LINPACK library solves systems of simultaneous
equations for many applications like radar and Telecom. It
can handle a wide variety of matrices including triangular,
band, Hermitian and Toeplitz.
GDD8000 ECC EISPACK library functions solve linear alge-
braic eigen systems with various matrices, real or complex,
general, band, symmetric or Hermitian. Several types of
matrix decompositions like SVD or QR are performed.
The GDD9000 CBLAS 123 functions perform operations on
IEEE-754 SP and DP foating-point numbers. It uses native FP
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Explore...
White Papers
Exclusive Videos
Valuable Articles

CONTACT INFORMATION
Blackhawk
123 Gaither Drive
USA
856-866-1100 Fax
Blackhawk
Bi-Color Wireless SIaIus LED (red/greeh)
EIerhal Power Supply Ior sIahdalohe WiFi use
Pih CohverIers (2) Ior T 14-pih ahd APM 20-pih
USB2000 Features
Super Low-CosI XDS510 emulaIor-class CohIroller
SupporIs T C2000 MCUs
F283 F281 F280
F280
LF240
Code Composer SIudio DE v3.3 SP2 or laIer
AVAILABILITY
All Blackhawk Emulators are available for immediate
delivery from a world wide network of industry resellers
and distributors. Please visit www.blackhawk-dsp.com
for a complete list.
APPLICATION AREAS
Audio, Automotive, Communications, Military, Telecom,
Telecom Infrastructure, Telephony,
Video Conferencing, Video Secu-
rity, Video and Imaging, Wireless.
Advanced JTAG XDS510 Emulators
Blackhawk is a recognized leader in providing advanced
JTAG Emulators for Texas Instruments DSPs and the
frst company to develop a USB JTAG Emulator for TI
TMS320 DSPs. Our XDS510-class emulators & con-
trollers provide a full range of features and benefts with
support for a wide-range of TI DSPs. Blackhawk XDS510-
class JTAG Emulators & Controllers are also compatible
with Code Composer Studio Flash-burner utility.
Feature Set of All Emulators
Bus-powered via USB cable
Bi-Color SIaIus LED (red/greeh)
Full Code Composer SIudio DE compaIibiliIy
Wihdows Plug h' Play hsIallaIioh
Drivers are provided Ior Lihu ahd Wihdows
including 64-bit support
All driver updaIes are available Ior dowhload Iree-
of-charge from our website
CompaIibiliIy wiIh Ihe Code Composer SIudio DE
Flashburn plugin and Blackhawk FlashBurn Utility
add-on
Free Iechhical supporI ahd web dowhloads
Ohe Year WarrahIy
AuIo-sehsihg low /O volIage supporI -
1.8v/3.3v/5.0v
Fully assembled ahd IesIed ih Ihe US
PoHS CompliahI
T 14-pih TargeI CohhecIioh (cT 20-pih Ior
USB510W)
OpIiohal solaIioh AdapIer Available
Code Composer SIudio DE v3.3, v4., v5. ahd laIer
USB510L Features
AIIordable XDS510 emulaIor-class CohIroller
SupporIs T TMS320' DigiIal Sighal Processors:
High-perIormahce 32-biI C2000' cohIrollers MCUs
C5000' ulIra-low power processors
C6000' (IoaIihg-poihI DSPs)
C6000' processors (high-perIormahce DSPs)
C6000' processors (high-perIormahce mulIi-
core DSPs)
DaVihci' video Processors
TMS470 (APM processors)
TMS570LS APM CorIe'-P4-based MCUs
32-biI SIellaris APM CorIe-M3-based MCUs
SiIara' Iamily oI APM CorIe A8 & APM9'
OMAP' processors
hIegra' DSP+APM processors
USB510W Features
All Ihe IeaIures oI Ihe USB510L
hIegraIed EEE 802.11 Trahsceiver
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CONTACT INFORMATION
Blackhawk
Blackhawk Emulator Product Matrix
Blackhawk offers a complete line of JTAG Emulator for
TI Embedded Processors including features not found
on other similar products. Contact Blackhawk for any
feature or emulator model not listed.
Model Highlight Indicates a
Blackhawk Unique Feature.
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System Trace
Yes Yes Yes - - - - - - - - - -
c-JTAG (IEEE 1149.7)
Yes Yes Yes - - - - - - - - - -
BHFlashburn
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes - -
Boundary Scan
Yes Yes Yes Yes Yes Yes Yes - - - - - -
USB (bus-powered)
Yes Yes Yes - Yes - - Yes Yes Yes Yes Yes Yes
Host Interface
USB
Yes Yes Yes Yes Yes Yes - Yes Yes Yes Yes Yes Yes
Ethernet-Wired
- Yes Yes - - Yes - - - - - - -
Ethernet-Wireless
- - - - - - - Yes - - - - -
PCI
- - - - - - Yes - - - - - -
Code Composer Studio
(CCS) IDE Support
CCS v5.x
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
CCS v4.x
CCS v3.3/v3.2/v3.1
- - - Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
CCS v3.0/v2.2
- - - Yes Yes Yes Yes - Yes - - - -
Device Support
TMS320C24xx
- - - Yes Yes Yes Yes Yes Yes Yes Yes - -
TMS320C28xx
TMS320C54xx
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes - Yes Yes
TMS320C55xx
TMS320C6xxx
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes - C674x C674x
TMS320C64xx
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes - - -
TMS320C64+
TMS320C66xx
TMS470 ARM7/9/11
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes - ARM9 ARM9
Stellaris ARM Cortex
MCUs
OMAP processors
Integra DSP+ARM/Sitara
ARM processors
DaVinci processors
OS Support
Windows 2000/XP/XP64
Windows Vista/7 (32/64bit)
Linux (32/64 bit)
Yes Yes Yes Yes Yes Yes - Yes Yes Yes Yes Yes Yes
I/O Voltage Support
1.8v/3.3v
5.0v
- - - Yes Yes Yes Yes Yes Yes Yes Yes - -
Target Connections
MIPI 60
Yes Yes Yes - - - - - - - - - -
TI 60 (trace)
option Yes Yes Yes Yes Yes Yes option option option option option -
TI 14
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes -
cTI 20
Yes Yes Yes Yes Yes Yes Yes Yes option option option Yes -
ARM 20
Yes Yes Yes Yes Yes Yes Yes Yes - - - option Yes
ARM 10
- - - - - - - - - - - - Yes
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Blackhawk
123 Gaither Drive
USA
856-866-1100 Fax
CONTACT INFORMATION
Blackhawk
123 Gaither Drive
USA
856-866-1100 Fax
Blackhawk
PCI560 Features
UlIra compacI halI-heighI ahd halI-lehgIh Iorm IacIor
Fleible 5 IooI high-speed micro coa JTAG
cable with 20-pin cTI (Compact TI) header
hcludes boIh a halI-heighI (ihsIalled) ahd sIahdard
height bracket
hcludes (3) pih cohverIers Ior T 14-pih,
20-pin(ARM-based platform) and TI 60-pin (Trace)
target headers
USB560 BP Features
USB Bus-powered, heeds ho power supply
LighIweighI (5 ouhce) pod
Bi-color SIaIus ahd AcIiviIy LED
High-speed USB 2.0 (480 MbiIs/sec) porI
hcludes a pih cohverIers Ior T 14-pih IargeI headers
System Trace (STM) Support
All Blackhawk XDS560-class Emulators are capable
of collecting System Trace (STM) data from TI CTools-
enabled devices. For more information, please visit
www.blackhawk-dsp.com/STM.
AVAILABILITY
APPLICATION AREAS
Telecom Infrastructure, Telephony,
High Performance JTAG Emulators
The Blackhawk XDS560-class emulators are the standard
of high-performance debugging of TI embedded proces-
sors and each includes support for the Code Composer
Studio integrated development environment (IDE) v3.3
and later plus the ability to collect system trace data (read
below). These emulator models are a great value with new
reduced pricing and continue to offer up-to-date features.
Feature Set of All Blackhawk 560 Emulators
SupporI Ior Corelis Scah Epress Programmer ahd
Scan Express Jet Boundary Scan tools
SupporI Ior TMS320', TMS470' (APM proces-
sors) and OMAP processor families including the
DaVinci platform
High-speed PTDX' Iechhology wiIh daIa raIes oI
over 2 MB/sec
hcludes XDS560 Pevisioh D cable elecIrohics ahd Iea-
tures with 20-pin cTI JTAG Header (SYSRESET signal)
hcludes 20-pih cT Io 14-pih adapIer Ior boards
using standard 2x7 target header
AuIo-sehsihg low /O volIage supporI dowh Io 0.5v
Peal-Iime, hoh-ihIrusive Advahced EvehI Triggerihg
(AET) capability
Code Composer SIudio DE compaIibiliIy Ior v2.2
and later
Wihdows Plug h' Play hsIallaIioh
Wihdows XP/VisIa/7 SupporI (32 ahd 64-biI ediIiohs).
LNUX supporI uhder CCSIudio v5 (32 ahd 64-biI
editions) *PCI560 excluded
All driver updaIes are available Ior dowhload Iree-
of-charge from our website
CompaIibiliIy wiIh Ihe Code Composer SIudio DE
Flash-burner utility
Up Io 100 Iimes IasIer Ihah XDS510' emulaIors
USB560M Features
CompacI pod wiIh power ahd USB sIaIus ihdicaIor
LEDs
High-speed USB 2.0 (480 MbiIs/sec) porI
Fleible 12 ihch high-speed micro coa JTAG cable
with 20-pin cTI (Compact TI) header
hcludes (3) pih cohverIers Ior T 14-pih,
20-pin(ARM-based platforms) and TI 60-pin
(Trace) target headers
LAN560 Features
The LAN560 includes all the features of the USB560m, plus
10/100 Mbps EIherheI LAN hIerIace
NeIwork AcIiviIy LED
HosI ihIerIace via USB or EIherheI (PJ45)
TCP/P cohIguraIioh seIIihgs Ior P, mask ahd
gateway address
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CONTACT INFORMATION
Blackhawk
123 Gaither Drive
USA
856-866-1100 Fax
Blackhawk
NaIive 10-pih APM IargeI ribboh cable
NaIive 20-pih APM IargeI ribboh cable
AVAILABILITY
APPLICATION AREAS
Audio, Automotive, Motor Control, Communications, Mili-
tary, Telecom, Telecom Infrastructure, Industrial, Telephony,
USB100v2 JTAG Controllers
The Blackhawk USB100v2 JTAG Controllers are very
low-cost controllers for basic debugging of Texas Instru-
ments DSPs. Requiring no external power source, they
can support most of the basic features of higher priced
controllers and require no additional drivers when
installed using the Code Composer Studio integrated
development environment (IDE) v4 or later.
Both models are TI XDS100v2-compatible controllers
fully supported under Code Composer Studio IDE v4/
v5 and future Texas Instruments roadmap software
development environments. Faster code downloads and
assembly code stepping are provided by the use a high-
speed USB2.0 (480 Mb/s) port instead of slower USB1.x
(12 Mb/s) implementations.
Both models are identical in hardware and software sup-
port, but offer different, native target connection options
- check your target boards JTAG connector.
USB100v2 Common Features
High-Speed USB 2.0 (480Mb/s) HosI hIerIace.
Power SIaIus LED.
Wihdows ahd Lihu SupporI (32 ahd 64-biI ediIiohs)
SupporIed Devices:
TMS320C28 High PerIormahce 32-biI cohIrollers
TMS320C54 Power-EIIciehI DSPs
TMS320C55 Fied-poihI DSPs
TMS320C674 Low Power DSPs
TMS320C645 DSPs
TMS320C64+ High PerIormahce DSPs
APM CorIe' M3-based MCUs
APM CorIe P4 processors
APM CorIe A8 & APM9' MPUs
hIegra' DSP+APM processor
DaVihci' video processors (hoI ihcludihg DM64)
1.8/3.3 volI device /O supporI.
Ohlihe SupporI Irom T.
USB100v2 Unique Features
SupporI Ior Code Composer SIudio DE v3.3
(XDS100v1 backwards compatibility)
Ohly supporIs TMS320C28 ahd TMS320C674
devices
USB100v2D Features
NaIive 20-pih cT IargeI ribboh cable
hcluded T 14-pih cohverIer
OpIiohal APM 20-pih cohverIer available
USB100v2-ARM Features
Desigh Ior TargeI boards wiIh APM JTAG cohhecIiohs
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CONTACT INFORMATION
Blackhawk
123 Gaither Drive
USA
856-866-1100 Fax
Blackhawk
AVAILABILITY
APPLICATION AREAS
Telecom Infrastructure, Telephony, Video Conferencing,
Video Security, Video and Imaging, Wireless.
XDS560v2 System Trace (STM)
The Blackhawk XDS560v2 System Trace Emulator models
are is based on the Texas Instruments XDS560v2 JTAG
emulator reference design (XDS560v2). The XDS560v2
design is the next-generation of the high-performance
XDS560-class technology frst made available by Black-
hawk with the USB560/LAN560 and XDS560 Trace. The
XDS560v2 design adds support for IEEE 1149.7 and
System Trace (STM), an interface on the TI SOC multi-
core (ARM + DSP) devices.
The Blackhawk XDS560v2 models meet all the TI
XDS560v2 reference design features and requirements
- no short-cuts. All models support System Trace data
collection. Here is an overview of features.
See www.blackhawk-dsp.com for a complete list of fea-
tures and device support.
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Model Highlight Indicates a
Blackhawk Unique Feature.
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IEEE 1149.7 (cJTAG) Support Yes Yes Yes
MIPI System Trace (STM) Support Yes Yes Yes
RoHS Compliant - Pb free Yes Yes Yes
LEDs for Status / Mode / Acti vity Yes Yes Yes
Target IO Voltage Range +1.2v - +4.1v Yes Yes Yes
Code Composer Studio IDE v4.2 and
later
Yes Yes Yes
DSS Java Scripting Support Yes Yes Yes
Variable/Programmable TCK up to 50
MHz
Yes Yes Yes
100 MHz STM Export Clock Yes Yes Yes
High-Speed STM Capable JTAG Cable Yes Yes Yes
USB bus-powered Yes Yes Yes
PoE Switch Capable - Yes Yes
External Power Suppl y option - Yes Yes
High-Speed USB 2.0 Host Interface Yes Yes Yes
Ethernet (10-100 Mb) Host Interface Yes Yes Yes
Linux 32 and 64-bit Support Yes Yes Yes
Windows 32 and 64-bit Support Yes Yes Yes
Configuration and Test GUI Program Yes Yes Yes
MIPI 60 Target Connection Yes Yes Yes
TI 14 Target Connection Yes Yes Yes
cTI 20 Target Connection Yes Yes Yes
ARM 20 Target Connection Yes Yes Yes
TI 60 (XDS560 Trace) Connection option Yes Yes
Price $999 $1500 $1600
CONTACT INFORMATION
CONTACT INFORMATION
Kane Computing Ltd
Kane Computing Ltd
Suite I, Ascot Court,
71-73 Middlewich Road
Northwich, Cheshire CW9 7BP
UK
01606 351006 Telephone
01606 351007 Fax
sales@kanecomputing.com
www.kanecomputing.co.uk
TI-trained engineers with the widest range of DSP
development tools in the UK.
UK Distributor/Agent for a wide range of TI 3rd party
products.
Application Areas: Audio, Automotive, Broadband
Solutions, Communications, Imaging, Industrial, Military,
Motor Control, Optical Net-
working, Telecom, Telephony,
Broadcast, Video, Video
Infrastructure, Wireless.
Kane Computing Company Profle
Supported TI Processors: DM64x, OMAP35x, DM81xx, C6A816x,
C5xxx, C67xx, C64xx, MSP430 MCU, C2xxx and DM3xx.
Kane Computing supply cost effective and reliable DSP solu-
tions to match the users needs. We have the widest range
of DSP development tools, hardware and software, in the
UK and we have an intimate knowledge of these products.
Kane Computing also have vast experience in video and
audio processing, particularly for compression, streaming
and storage. Kane Computing also works with a number of
members of TIs Third Party Network who provide hardware
platforms, software libraries and technical resources, to
allow Kane Computing to offer complete packages not avail-
able from any other single source.
TECHNICAL SPECS
Consultants and providers of DSP Development Tools,
hardware and software, for the complete range of TI
DSPs.
Many years of industrial experience of DSPs and
signal/video processing.
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CONTACT INFORMATION
Signum Systems
IAR SYSTEMS INC.
1065 E. Hillsdale Blvd., #420
Foster City, CA 94404
650-287-4250
info@iar.com
www.signum.com
Coverage Analysis (ARM and Cortex cores only
requires ETM)
TECHNICAL SPECS
Supports ARM7, ARM9, ARM11 and Cortex-M/R/A
devices from all manufacturers
Supports C2000, C5000, C6000, TMS470,
TMS570, Stellaris, OMAP, OMAP3, DM, DaVinci and
Sitara devices
High-speed USB 2.0 port (480Mbps) allows super
fast RAM downloads and Flash programming
ETM trace clock of up to 200MHz allows debugging
devices running at speeds > 1GHz
AVAILABILITY
Now
APPLICATION AREAS
Telecom, Computers & Peripherals, Consumer Electronics,
Industrial, Medical, Military, Security, Video and Imaging,
Wireless
JTAGjet In-Circuit Debuggers for DSP,
OMAP and DaVinci Processors
Supported TI Processors: DM646x, DM644x, DM643x, DM64x,
DM355, OMAP35x, F283x, F282x, F281x, F280x, LF240x, C55x, C54x,
C672x, C67x, C645x, C6414T/15T/16T, C642x, C6410/12/13/18, C62x,
TMS470, TMS570, Stellaris, Cortex-M3, Sitara AM37x, AM35x,
AM18x, AM17x
JTAGjet is a USB 2.0 based In-Circuit Debugger
designed to support all ARM7/9/11, Cortex-M/R/A
as well as all TI DSP, OMAP, DaVinci and Sitara
devices. JTAGjet comes with a multi-core Chameleon
Debugger for ARM and it can also be used with a variety
of 3rd party debuggers, like IAR Embedded Work-
bench for ARM, Texas Instruments Code Composer
Studio integrated development environment (IDE),
Eclipse, GNU and others. When used with Chameleon
Debugger, JTAGjet features ETM & ETB real-time
trace, Serial Wire Debugging (SWD), integrated Flash
programming, code profling, timing analysis and com-
plex triggering events making the debugging process
faster and easier.
One of the unique JTAGjet features is that it may
be used concurrently with two different debuggers
offering a complete multi-core debug environment for
systems that use different RTOSes on different cores
FEATURES & BENEFITS
Supports all ARM, Cortex, TI DSP, OMAP, DaVinci
and Sitara devices
Available with ETM and/or ETB real-time trace
for quicker, more effcient debugging with timing
analysis
Multi-core support on single and multiple JTAG
chains
Compatible with major ARM and DSP compilers and
debuggers
Integrated GUI and batch mode Flash programming
Real-time trace history of program execution and
variables along with CPU cycle-accurate timing
helps to locate even the most elusive bugs
Embedded Linux support speeds-up debugging
of uBoot, Linux kernel, kernel modules, peripheral
drivers and applications.
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www.eecataIog.com/dsp Embedded Software 51
CONTACT INFORMATION
525 Plymouth Road
Suite 316
Plymouth Meeting, PA 19462
USA
1-800-340-2066 Toll Free
610-825-0182 x120 Telephone
sales@adaptivedigital.com
www.adaptivedigital.com
FEATURES
Superb speech quality
User Confgurable
Cancels multiple independent echo tails
G.168 echo canceller AT&T certifed as Carrier Grade
Capable of packet echo cancellation: Handles round-trip
delays of up to 512 milliseconds
BENEFITS
Field-hardened, deployed in 49 countries
ITU G.168 compliant beyond requirements
Available as a chip solution
Included in VoIP Engine
AVAILABILITY
All products are available now.
APPLICATION AREAS
Broadband, Communications & Telecom, Consumer
Electronics, Medical, Military,
Security, Wireless
Adaptive Digital Echo
Cancellation Library: Acoustic,
Packet, Network, & Line
Supported TI Processors: DaVinci DM64x, DaVinci DM81x,
DaVinci DM64x, DM646x, DM644x, DM643x, DM64x, DM814x,
DM816x, OMAP35x, OMAP3525/30 SoC, C55x, C55x Dual MAC
DSPs, C54x DSPs, C674x Low Power DSP, C67x DSP, C66x DSPs,
C64x DSP, C62x DSP, C647x Multicore DSP, C645x Multicore DSP,
C667x Multicore DSPs, C665x Multicore DSPs, AM37/AM35x
ARM Cortex-A8, AM18x ARM9 , AM17x ARM9, Stellaris
ARM Cortex-M based
With a strong focus on providing optimum voice quality,
Adaptive Digital developed an echo canceller unparal-
leled in quality and effciency. The carrier-grade echo
canceller carries with it the robustness that comes from
the combination of careful design, relentless testing, and
widespread deployment.
The G.168 Plus packet EC has the distinctive ability to
handle round-trip delays of up to 512 msec. This ability cou-
pled with a built-in awareness and handling of packet-loss
makes G.168 Plus uniquely suitable for VoIP applications.
Adaptive Digitals G.168 EC features, enhanced beyond
ITU recommendation include tandem free operation,
dynamic NLP, rapid convergence, convergence monitor,
stationary signal detector, split pre and post processing,
and the ability to cancels multiple refectors.
G.168 EC Highlights
Superior Voice OualiIy
Papid, deep cohvergehce
Low MPS
No divergehce due Io doubleIalk
MaIched ComIorI Noise GeheraIor
Tohe Disabler
ACOUSTIC ECHO CANCELLATION
Adaptive Digitals acoustic echo canceller (AEC) enables
true full-duplex hands-free telephony in mobile phones,
speakerphones, and hands-free intercoms.
AEC Highlights
AEC G4 Designed for high-end speakerphones and con-
ferencing endpoints. Supports HD Voice, integrated noise
reduction and AGC, supports tail length up to 256 msec,
superior double-talk performance. C6000, ARM, and
x86 platforms
AEC G2 - Designed for traditional speakerphones, with
enhancements specifcally designed for mobile handsets.
C6000, C5000, ARM, and x86 platforms
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52 Embedded Software Embedded Processing & DSP Resource Guide 2013
CONTACT INFORMATION
525 Plymouth Road
Suite 316
USA
1-800-340-2066 Toll Free
610-825-0182 x120 Telephone
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FEATURES & BENEFITS
Certifed carrier class G.168 Echo Canceller achieves
excellent voice quality while leading the industry in
CPU and memory utilization effciency.
HD Full-Duplex Acoustic Echo Cancellation for appli-
cations ranging from high-end conference endpoints
to desktop phones and mobile handsets.
Customers have the fexibility to choose a turnkey
solution (G.PAK), a highly integrated framework (VoIP
Engine), or a set of algorithm libraries.
Evaluation software is available for testing in your
design. Contact sales or login to our extranet to
download demos.
Adaptive Digital provides support throughout all
project phases; customers have access to our techni-
cal team directly over the phone or via email.
Developers of voice-centric applications fnd both our
algorithms and solutions easy to integrate and well
optimized for their requirements.
Adaptive Digitals solutions support a low-cost prod-
uct development model with short time-to-market.
Using its proprietary Echo Analysis test system,
Adaptive Digital can analyze customers recorded data
and isolate circuitry and acoustic problems, as well as
assist in echo canceller and voice quality tuning.
AVAILABILITY
All products are available now.
APPLICATION AREAS
Audio, Communications & Telecom,
Medical, Military, Security, Wireless
Voice Algorithms and Solutions on
the Texas Instruments TMS320
Family of DSPs, OMAP, DM-Series,
Multi-Core, and ARM processors
DM64x, DM81x Video SoC, DM64x Video SoC, DM646x, DM644x,
DM643x, DM64x, OMAP35x, OMAP3525/30 SoC, C55x, C55x Dual
MAC DSPs, C54x DSPs, C674x Low Power DSP, C66x DSPs, C64x DSP,
C62x DSP, C647x Multicore DSP, C645x Multicore DSP, C667x Multi-
core DSPs, C665x Multicore DSPs, AM35x/AM37x ARM Cortex-A8,
AM18x ARM9, AM17x ARM9, Stellaris ARM Cortex -M based
Adaptive Digital is a developer of voice algorithms, soft-
chip solutions, and VoIP Engine software for VoIP and
traditional telecommunications systems and applica-
tions. Our expertise is in the development of solutions
that maximize voice quality as well as channel density.
VoIP Engine is at the core of our ARM-based VoIP applica-
tions, it is a software engine package that handles all the
voice processing from PCM to Packet and back. Its intended
use is in VoIP enabled handsets or desktop phones.
G.PAK, the core technology behind our turnkey solu-
tions, is a VoIP application that runs on a TI DSP or SOC
that handles the complete data fow between the TDM
and Packet interfaces.
Adaptive Digitals Algorithm Library Includes:
Voice Quality Algorithms: Echo Cancellation G.168
Line, Network, & Packet, G.168Plus Packet EC, Acoustic
Echo Cancellation (AEC), AEC G2 (mobile devices) & HD
AEC G4 (NB/WB), Noise Reduction, Noise Suppression,
and Comfort Noise Generation.
All of the ITU G.XXX vocoders and many of the ETSI and
3GPP compression algorithms.
HD Audio/Voice algorithms: HD AEC, HD Conferencing,
G.722, G.722.1, G.722.2 (AMR-WB), Speex
Telephony algorithms: Tone Detect and Suppress, DTMF,
AGC, Arbitrary Tone Detect, R1/R2 Detect, Voice Activity
Detection, Tone Relay, and High Density Conferencing
(NB/WB)
Military and Defense codecs: MELP/MELPe, CVSD, LPC,
G.729D
Encryption algorithms: AES, SRTP
Modem software: Caller ID, T.38 Fax Relay, V.xx (21, 27,
29, 22Bis, & 32Bis), Modem Relay, and G.165 detect
CONTACT INFORMATION
4 Slavi
Penza, 440600
Russian Federation
7 963 105 32 18 Telephone
request@dspini.com
www.dspini.com
www.twelp.pro
Any platforms (DSP, RISC or general-purposes) are
available for porting.
Integrated Circuit (Chip). TWELP 2400/3600 bps
vocoder is available also as specialized chip (IC) from
CML Microcircuits.
One license. No third-party IP holders.
Related software: Linear and Acoustic Echo Cancel-
lers (LEC and AEC), Multi-Channel Noise Cancellers,
modems for radio and wire channels for any bit rates.
AVAILABILITY
Varies. Check www.twelp.pro website and contact to
fnd out current availability.
APPLICATION AREAS
Communications & Telecom, Military, Security, Wireless
New TWELP Vocoder
(6009600 bps)
DSPINIs high-quality vocoder provides the best speech
quality among competitors today. It has a wide range of
bit rates from 600 bps up to 9600 bps and is intended for
Digital Radio (HF, UHF, DMR, dPMR, etc.), wire communi-
cation, VoIP and other markets.
The vocoder is based on the newest speech coding tech-
nology, called Tri-Wave Excited Linear Prediction
(TWELP), developed by experts of DSPINI.
TWELP is:
Advahce reliable meIhod oI PiIch esIimaIioh
PiIch syhchrohous ahalysis
Advahce Iri-wave model oI eciIaIioh
NewesI quahIizaIioh schemes
PiIch syhchrohous syhIhesis
Although the technology is based on well-known
LPC-method, where output speech is gotten by the syn-
thesizing LPC-flter, it is not a variety or combination of
well-known speech coding methods, patented compre-
hensively during last 20-30 years.
TWELP is a unique three-component representation
of pitch-synchronous LPC residual that is quantized by
unique speech-driven quantizers in conjunction with
LPC-parameters.
FEATURES & BENEFITS
Superiority in speech quality. ITU-T P.50 multi-
language speech base and ITU-T P.862 utility were
used for objective estimation and pair comparisons
by listening were used for subjective estimation.
Superiority in non-speech signals (sirens, etc.)
High robustness to acoustic noise.
High robustness to channel errors, thanks to FEC,
integrated using joint source-channel coding
approach. Soft Decisions and Hard Decisions
from a modem can be used.
Automatic Gain Control (AGC), Noise Cancellation for
Speech Enhancement (NCSE), Voice Activity Detector
(VAD), Tone Relay (transparence) for any single and
dual tones.
Guarantee of quality thanks to accurate testing and
methods of quality control. Reliable support.
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CONTACT INFORMATION
525 Plymouth Road
Suite 316
USA
1-800-340-2066 Toll Free
610-825-0182 x120 Telephone
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VOICE PROCESSING FUNTIONS INCLUDE: Digital
Gain Control, Noise Reduction, Vad/CNG, RTP & Jitter
Buffer, AGC, G.711 u-Law, G.711 A-Law, and G.729AB.
The combination of TIs ARM and DSP processors
and Adaptive Digitals superior algorithms and G.PAK
framework, provide a solid foundation for the devel-
opment of differentiated next-gen telecom products.
Adaptive Digitals VoIP Intercom ISS enables equip-
ment manufacturers to develop products quickly and
cost-effectively.
Our engineering team has over thirty years experi-
ence in practical and theoretical aspects of DSP
Software, and Communications.
Should modifcations be necessary for your project,
customization is available.
APPLICATION AREAS
Broadband, Communications & Telecom, Medical,
Military, Security, Wireless
IP phone/intercom/ATA for
OMAP3530, OMAP3730, DM814X,
DM816X, and Stellaris devices.
Supported TI Processors: DaVinci DM81x processor, DM81x
Video SoC, DM814x, DM816x, OMAP35x, OMAP3525/30 SoC,
Stellaris ARM Cortex-M based MCUs: 3000 Series
Adaptive Digital simplifes software design of an IP
Phone, IP Intercom or ATA. We provide the software that
runs on the DSP consisting of a fully functioning and
complete SIP solution with RTP, UDP/IP, G711, G.729AB,
tone handling, and echo cancellation. Additionally we
offer what we call ISS (Intercom Server System), which
is a software component that runs on the ARM under
Linux. The ISS deals with the DSP interface and control,
and RTP streaming over UDP/IP. The ISS also provides an
interface to your ARM-based application.
Adaptive Digitals ISS software subsystem simplifes
software design of an IP intercom or IP phone that runs
on TIs OMAP3530 and DM814x/DM816x devices. ISS
implements complete VoIP capability all the way from
PCM to Packet and back. This includes a process running
on the ARM under Linux as well as the necessary voice-
processing running on the DSP core.
Adaptive Digitals ATA solution is a software and
hardware reference design that provides equipment
manufacturers a fast path to market for a low-cost ATA.
The application runs completely within the Stellaris
MCUs internal fash memory and RAM. A Silicon Labs
ProSLIC provides the FXS line interface and a Codec as
well as POTS protection circuitry that typically requires
additional circuitry. Stellaris MCU-based ATA and IP
Phone software solutions share a similar base set of pro-
tocols and algorithms while separately addressing the
features that are unique to these two solutions.
FEATURES
Stellaris MCU-based IP Phone, IP Intercom, and ATA
ATA - Highly integrated, low chip count. Supports
single or dual port, call control and management.
ATA Software includes: Line EC, G.711 with PLC,
G.729AB, SIP, RTP Packetization, Caller ID, Tone Det/
Gen, and Confgurable Jitter Buffer.
OMAP processor, DM814x, and DM816x based-IP
Phone, and IP Intercom
The VoIP software includes Adaptive Digitals Gen-4
Acoustic Echo cancellation, which incorporates a
noise reduction feature, as well as anti-howling,
nonlinear processing, and double-talk detection.
CONTACT INFORMATION
260 Bear Hill Rd
Suite 101
Waltham, MA 02451
USA
781-890-2055 Fax
info@delcomsys.com
www.delcomsys.com
Packet-switched traffc modes include GPRS CS-1
through 4 and EDGE/EGPRS MCS-1 through 9.
Automatic system information message scheduling
and transmission.
A5/1, A5/2, and A5/3 ciphering support.
Includes support for detection of neighboring cells
for femtocell and custom applications.
AVAILABILITY
Available now.
APPLICATION AREAS
Broadband, Communications & Telecom, Consumer
Electronics, Industrial, Military, Security, Wireless
GSM/EGPRS/EDGE LayerONE
Physical Layer Software
DM64x, DaVinci DM37x, DaVinci DM3x, DM81x Video SoC, DM64x
Video SoC, DM646x, DM644x, DM643x, DM64x, DM37x, DM3x,
DM814x, DM816x, OMAP35x, OMAP3525/30 SoC, TMS320DM37x SoC,
TMS320DM3x Video SoC, OMAPL1x, C6A816x, C6A814x, C55x, C55x
Dual MAC DSPs, C54x DSPs, C674x Low Power DSP, C67x DSP, C66x
DSPs, C64x DSP, C62x DSP, C647x Multicore DSP, C645x Multicore
DSP, C66x Multicore DSPs, C647x Multicore DSP, C645x Multicore DSP,
C667x Multicore DSPs, C665x Multicore DSPs, AM389x/AM35x/AM37x
ARM
Cortex-A8, AM18x ARM9, AM17x ARM9

DelComs GSM LayerONE is a turnkey 2.75G physical layer
solution based on software-defned radio (SDR). Designed
with ease of integration in mind, the software framework
allows for rapid product development without the need for
expertise in the intricacies of modulation, channel coding,
interleaving, and physical channel multiplexing. Clean and
concise Layer 2, Layer 3, and base-band interfaces and exten-
sive logging capabilities make integration a snap. Available
for a variety of processors including some of TIs OMAP
processors, DaVinci video processors, TCI, Faraday, and
TMS320C6000, and TMS320C5000 DSPs. DelComs Lay-
erONE physical layer framework offers the scalability and
fexibility only a software solution can provide.
FEATURES & BENEFITS
Portable to almost any commercially available DSP,
general-purpose processor, or proprietary core with
customizable interfaces to drop into your existing
design or network stack.
Perfect for femtocell and picocell applications as well
as standard BTS designs.
Ideal for use in specialty applications such as point-
of-sale devices, test and measurement equipment,
proprietary modems, network load monitors, IMSI/
IMEI catchers, and lawful call interceptors (SIGINT).
Extensive built-in test functionality and L3, L2, and
base-band logging capabilities simplify integration
and hardware qualifcation.
Flexible terms including full source code licenses
are available to qualifed customers. All core library
modules for both MS and BTS devices including the
GMSK and 8PSK (EDGE) equalizers are also available
for license individually.
TECHNICAL SPECS
Circuit-switched traffc modes include TCH/FS, TCH/
EFS, TCH/AFS, TCH/WFS, TCH/HS, TCH/AHS, TCH/
F14.4, TCH/F9.6, TCH/F4.8, and TCH/F2.4.
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CONTACT INFORMATION
Marktstr. 10
Kerken, 47647
Germany
+49 2833 570977 Telephone
+49 2833 3328 Fax
info@dsignt.de
www.dsignt.de
TECHNICAL SPECS
TMS320F2812/28335 typical resource requirements:
code: 27.4K bytes,
data: 5.6K bytes + 604 bytes per socket
TMS320C55x typical resource requirements:
code: 35K bytes,
data: 8K bytes + 640 bytes per socket
TMS320C6000 DSP typical resource requirements:
code: 72K bytes,
data: 7.2K bytes + 604 bytes per socket
AVAILABILITY
now
APPLICATION AREAS
Industrial, Security, Video,
Wireless
D.SignT TCP/IP Stack for TI C2000
MCUs, C5000, and C6000 DSPs
Supported TI Processors: DM64x, C55x, C67x DSP, C64x DSP,
F28x Delfno MCU foating-point series, F28x fxed-point series
TCP/IP communications on an embedded DSP system
greatly differs from Personal Computer requirements. A
DSP is not required to handle hundreds of simultaneous
connections as does a PC based server. On the other
hand, latencies and resource consumption are much
more critical to avoid compromising signal processing
performance.
The D.SignT TCP/IP stack has been carefully tailored
to the requirements of DSP systems. Code and data
memory size are minimized, and no additional resources
like DSP interrupts or timers are required. The TCP/IP
protocol stack does not require an underlying real-time
operating system and can be used in a linear C program.
In addition the stack can run as a task in a RTOS, e.g.
DSP/BIOS. The user has full control to balance the pro-
cessor time for communications and signal processing.
No large memory buffers are required because the
zero-copy stack feature transfers data directly out of
or into the application data buffers, thereby minimizing
memory requirements, latencies and processor time. An
overview of memory requirements for a typical confgu-
ration (including ARP, IP, ICMP, UDP, TCP, DHCP and DNS)
is given below in the Technical Specs.
To evaluate and test the D.SignT TCP/IP stack, DSK Eth-
ernet Daughter Cards for C2000 MCUs and, C5000,
C6000 processors EVMs, and DSKs are available. The
Quantity and OEM licenses include design-in support
to integrate Ethernet communications into your custom
hardware. Various Ethernet network controllers are sup-
ported.
FEATURES & BENEFITS
does not require a real-time operating system
zero-copy stack minimizes data memory resource
consumption
application has full control to balance communica-
tions and signal processing resources
Evaluation Hardware Platform (DSK Daughter Cards)
available for C2000 MCUs, C5000 and C6000
processors
Licensing Models: Test and Development License,
Small Quantity (10) License, Medium Quantity (100)
license, OEM license. License includes hardware
design-in support.
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CONTACT INFORMATION
525 Plymouth Road
Suite 316
USA
1-800-340-2066 Toll Free
610-825-0182 x120 Telephone
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G.PAK enables developers to implement high-density,
multi-channel, voice-over-packet applications in the
shortest possible time with maximum processing
performance.
G.PAK is a built to order, voice over packet software
solution. Spend your engineering resources on
features that differentiate your product.
Adaptive Digitals G.PAK is also interoperable with TIs
Telogy Software on the TNETV VoIP system-on-
chip (SOC) series.
A video demonstration of the G.PAK build process can
be found on Adaptive Digitals web site at http://www.
adaptivedigital.com/video_training/GPAK/GPAK.htm.
AVAILABILITY
This product is available now.
APPLICATION AREAS
Communications & Telecom,
Wireless
G.PAK bridges the gap between
infexible fxed-function chips and
custom programmed solutions
Supported TI Processors: DaVinci DM64x, DM646x, DM644x,
DM643x, DM64x, DM814x, DM816x, OMAP35x, C54x DSPs, C66x
DSPs, C64x DSP, C647x Multicore DSP, C645x Multicore DSP
G.PAK integrates the building blocks that are required
voice-over-IP and voice-over-LTE systems into a turnkey
solution. G.PAK is a scalable, build time confgurable voice-
over-packet DSP software application that runs on the TIs
TMS320C5000 and TMS320C6000 families of DSPs.
G.PAK provides all of the DSP components necessary in
a voice-over-packet system and provides an application
interface to allow easy integration into a users applica-
tion. It includes one or more algorithms like conferencing,
vocoders, echo cancellation, tone detection, etc. G.PAK
runs the entire DSP and interfaces with peripherals such
as the serial port.
G.PAK is run time confgurable allowing channels to be setup
for individualized processing. Channel setup (identifcation
of input and output ports, vocoders, and voice algorithms),
conference setup, and teardown operations are performed
at run time. G.PAK DSPs interface to a host control processor.
Adaptive Digitals G.PAK DSP software solutions address
the need for high-density, VoIP, and traditional telecommu-
nications applications. Adaptive Digital provides pre-built
G.PAK software images for telephony applications such as
VoIP gateway, conferencing, and transcoding. These solu-
tions include host API software to simplify the process of
integrating a host processor with the DSP applications.
G.PAK can easily be customized to include only the neces-
sary algorithms, channel confgurations, and interfaces of
a particular applications requirements. If G.PAKs built-in
fexibility is not enough, source code can be licensed.
FEATURES & BENEFITS
G.PAK supports several channel types: TDM to Packet,
PCM to TDM, Packet to Packet, TDM to Conference,
Packet to Conference, and Conference Composite.
For those who want to customize the G.PAK software
beyond the capabilities of the automated confgura-
tion utility, application source code is available,
encouraged, and supported.
The combination of TIs High Density DSPs with
Adaptive Digitals feld-tested algorithms and G.PAK
framework provide a solid foundation for the develop-
ment of high-quality, differentiated telecom products.
CONTACT INFORMATION
HCC Embedded
HCC Embedded
444 East 82nd Street
New York, NY 10028
USA
+1 212 734 1345 Telephone
info@hcc-embedded.com
www.hcc-embedded.com
TECHNICAL SPECS
Flash Management: truly fail-safe Flash Translation
Layer provides a high-performance solution to interface
with any Flash-based media. SafeFTL presents a simple
logical sector interface and manages the underlying
complexity effciently and safely.
Fail-safe File Systems: fve highly optimized fle sys-
tems which can be used even on the smallest MCUs.
Support for any target media with incredibly high
performance and support for all NAND/NOR fash.
USB Device, Host & OTG: support for all speeds and all
end-point types. Advanced class drivers which can sup-
port multi-media network and fle system integration.
MISRA Compliant TCP/IP: advanced, high speed,
embedded networking software built to fully
verifable standards. Support for IPv4 & IPv6 and
extensive range of protocols.
Boot-loaders: customizable boot-loaders supporting
fle, USB or serial interfaces. Fully fail-safe recovery
from interrupted programming. AES encryption
module for secure data transfer.
AVAILABILITY
Immediately
APPLICATION AREAS
Telecom, Computers & Peripherals, Consumer Elec-
tronics, Industrial, Medical, Military, Security, Video,
Wireless
Advanced Embedded Middleware
Supported TI Processors: DaVinci DM37x, DaVinci DM3x,
OMAP35x, TMS320DM37x SoC, C54x DSPs, C66x DSPs, C64x DSP,
C62x DSP, AM37x ARM Cortex-A8 , AM35x ARM Cortex-A8,
AM18x ARM9 , AM17x ARM9, F28M35x Concerto Series, F28x Del-
fno MCU foating-point series, F28x Piccolo MCU series, F28x
fxed-point series, MSP430L092 Series Low Voltage, MSP430F1xx
Series Up to 8 MHz, MSP430G2xx Value Series Up to 16 MHz,
MSP430F2xx Series Up to 16 MHz, MSP430AFE2xx Series Up
to 12 MHz, MSP430F4xx Series Up to 8 or 16 MHz, MSP430F5xx/
F6xx Series Up to 25 MHz, MSP430FR57xx FRAM Series Up to 8
or 24 MHz, 1000 Series, 2000 Series, 3000 Series, 5000 Series, 6000
Series, 8000 Series, 9000 Series
Advanced Embedded Framework: all software compo-
nents from HCC can be integrated easily with almost any
common RTOS, development environment, peripheral
or fash device. The ability to achieve this effciently is a
central part of the companys technology strategy. It also
provides an important beneft for those companies who
do not want to rely on proprietary operating systems in
their design. HCC developed its Advanced Embedded
Framework to enable consistent abstractions and inter-
faces to any embedded environment. This means that
engineers can easily integrate HCC middleware whether
they have proprietary or commercial software platforms.
The framework not only provides a consistent set of
interfaces, but it also creates the environment for HCC to
apply its rigorous coding standard in the development of
MISRA compliant and verifable software components.
FEATURES & BENEFITS
Verifable Middleware Components: using a strong
development methodology, HCC supplies a coopera-
tive scheduler and TCP/IP stack which are developed
to the highest verifable standards.
Seamless RTOS Integration: all HCC middleware is
developed with no dependence on the hardware or
software environment. Software is supplied with
effcient abstractions to nearly all popular commer-
cial RTOS (and none).
High Performance: with a focus only on storage and
communications software, HCC has attained memory
utilisation and speed of execution which is unrivalled.
Extensive Tool Support: projects can be supplied for
almost any popular IDE or compiler with no need for
engineers to perform integration or complex periph-
eral confguration to get a project started.
Royalty Free Licensing: straightforward licensing
with no run-time fees and support and maintenance
included in the price.
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CONTACT INFORMATION
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Anaren
Anaren
6635 Kirkville Road
East Syracuse, NY 13057
USA
800-411-6596 Toll Free
air@anaren.com
www.anaren.com
60 End-Equipment SoIutions Embedded Processing & DSP Resource Guide 2013
CONTACT INFORMATION
Critical Link
Robust OS support, including Real-Time Embedded
Linux, QNX and Windows Embedded Compact 7
Small form factor: 68mm x 38mm; std. SODIMM-204
connector; ind. temp -40C to +85C available
Industrial communications: CAN Bus, EtherCAT, PRO-
FIBUS, Profnet, Powerlink, Secos-IIII and Ethernet/IP
Applications: medical, industrial automation, instru-
mentation; scientifc instrumentation; custom kiosks;
scales; security; building
automation; rich UIs
MityARM System on Modules
based on TI AM335x processors
Supported TI Processors: AM335x ARM Cortex-A8
MityARM-335x is a family of highly-confgurable, small
form-factor AM335x based modules optimized for
numerous commercial and industrial communications
protocols and high performance user interfaces. With
multiple versions, the MityARM-335x family meets a broad
range of processing requirements and product needs.
MityARM-335x is based on the ARM Cortex-A8 32-bit
RISC processor includes optional graphics acceleration. It
provides a complete and fexible CPU infrastructure for
highly integrated embedded systems.
The MityARM-335x is optimized to speed your development
of a robust, high quality product at a price point to ft within
your cost targets. Critical Link provides superior product
support and a life-cycle that ensures long-term availability.
TECHNICAL SPECS
ARM Cortex-A8 up to 720Mhz; integrated SGX530
3D graphics accelerator; onboard NOR, NAND, and
DDR3; integrated power management
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Critical Link
6712 Brooklawn Parkway
Syracuse, NY 13211
US
315.425.4048 Fax
Info@CriticalLink.com
www.mitydsp.com
Xilinx Spartan-6 FPGA available in multiple sizes
OS supported: Real-Time Embedded Linux, QNX,
DSP/BIOS, StarterWare, VxWorks, ThreadX, Win-
dows Embedded CE 6.0
SOMs include 128MB DDR2, 8 MB NOR fash, 256MB
NAND fash; multiple I/O, additional memory options
Applications: industrial automation; scientifc, medi-
cal, industrial instrumentation; network enabled data
acquisition; test & measure-
ment; machine vision
MityDSP and MityARM System
on Modules with FPGA
Supported TI Processors: OMAP-L138, C6748, AM1808
MityDSP and MityARM SOMs support a wide range of appli-
cation requirements. In addition to modules built around TIs
C6711 and C645x DSPs, Critical Link SOMs supports some
of TIs OMAP and Sitara ARM processors the OMAP-
L138, AM1808, and C6748 DSP-based devices built for apps
requiring minimal power consumption. The MityDSP-L138F
combines DSP, ARM processor, and Xilinx Spartan-6
FPGA processing power. The MityARM-1808F combines an
ARM processor with a Spartan-6 FPGA; the MityDSP-6748F
pairs a foating point DSP with a Spartan-6 FPGA. FPGA can
be used for I/O expansion, signal processing, and high speed
data acquisition. CPU-only versions are also offered. All mod-
ules are interchangeable, allowing for a single solution that
takes advantage of a highly scalable CPU/FPGA subsystem.
TECHNICAL SPECS
OMAP-L138 (ARM + foating point DSP), AM1808
(ARM only), or TMS320C6748 processor (foating
point DSP only) in multiple speeds up to 456MHz
Critical Link
www.eecataIog.com/dsp End-Equipment SoIutions 61
CONTACT INFORMATION
Z3 Technology, LLC
Z3 Technology, LLC
100 N. 8th Street
STE 250
Lincoln, NE 68508
USA
+1.402.323.0702 Telephone
+1.801.697.6829 Fax
sales@z3technology.com
www.z3technology.com
TECHNICAL SPECS
Compact Size: 82mm x 43mm
Supports H.264 HP QCIF to 1080p60
Supports TMS320DM8107 processors running at
720MHz ARM Cortex-A8 microprocessors
1GB DDR3, 256MB Flash
Parallel and serial CMOS sensor ports
AVAILABILITY
Available Today. Contact sales@z3technology.com for more
details or visit us on the web at www.z3technology.com
APPLICATION AREAS
Telecom, Consumer Electronics, Industrial, Medical,
Military, Security, Video
Compact Low-Power Software-
Enabled HD Multimedia Module
DaVinciVideo Processors: DM8107 DaVinci video SoC
Z3 Technologys Z3-DM8107-MOD low-power, high
defnition multimedia encoder/decoder module is
based on the Texas Instruments TMS320DM8107
DaVinci video processor. It measures only 82mm x
43mm, less area than a typical business card.
Z3 offers customized, fully integrated video encoding
and decoding modules based on open-source Linux. The
TMS320DM8107-based module allows for user expan-
sion with additional audio, video and image codecs,
as well as customer-specifc application software. It is
capable of H.264 encoding or decoding up to 1080p60.
The Z3-DM8107-MOD module supports pre-com-
piled, pre-loaded, ready-to-run software executables.
The combination of Z3s Z3-DM8107-MOD and pre-
compiled executables enable ODM/OEMs to rapidly
develop video products in application areas such
as digital video recorders, network video recorders,
industrial video interface displays and medical
imaging.
FEATURES & BENEFITS
OEM-ready HD multimedia module based on the low-
power multimedia TMS320DM8107 DaVinci video
processor technology.
The H.264 encoder supports full parameter control
via API and leverages hardware acceleration of the
TMS320DM8107 to support a full H.264 1080p60.
Ready-to-run software multimedia executables for
encode and stream, decode from stream, encode to
storage and decode from storage.
Z3-DM8107-MOD can support up to 4 inputs, 4 output
digital video ports.
Module supports open-source Linux 2.6.3x.
Complete Linux OS, multimedia software and SDK
available for application development and system
integration.
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62 Engineering Services Embedded Processing & DSP Resource Guide 2013
CONTACT INFORMATION
CONTACT INFORMATION
Advantech Co., Ltd.
Advantech Co., Ltd.
DSP@advantech.com.tw
www.advantech.com
1 GB DDR-1333 on board memory per DSP
Support XDS560v2 evaluation module via JTAG for
Code Composer Studio IDE connection
Support both Linux and Windows drivers
DSPC-8681 Half-length PCI Express
Multimedia Processing Card
Supported TI Processors: C667x multicore DSPs
DSPC-8681 includes Serial RapidIO and SGMII daisy-chains
for connecting DSP devices. Each DSP device is connected
by 2 separate PCIe lanes (PCIe x2) via PEX8624 enabling up
to 10Gbps non-blocking throughput. The card supports 120
channels in a H.264 mobile video application (CIF, 30fps)
and 60 channels in a content delivery network (SD, 30fps).
For HD Broadcast applica tions, DSPC-8681 supports 4
channels of AVCIntra-50, 10-bit, 4:2.0 at 60fps. The 32 DSP
cores make it ideal for power effcient solutions and it is
perfect for applications such as digital media, communica-
tions, video-surveillance, medical imaging, bioinformatics,
radar, sonar and instrumentation, high performance com-
puting as well as test and measurement.
TECHNICAL SPECS
4 TI TMS320C6678 DSPs on single half-length PCI
Express Card with PCIe Gen 2 x8 interface to the
edge connector
8 TMS320C66x DSP Core Subsystems (C66x Core-
Pacs) @ 1.0 GHz per DSP
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White Papers
Exclusive Videos
Valuable Articles

www.eecataIog.com/dsp Engineering Services 63
CONTACT INFORMATION
(507) 535-4274 Telephone
wally.thomson@bench.com
www.bench.com
Cameras:
Omnivision - 5MPI Rear Facing OV5640 Auto Focus
OV7739 VGA FF Front Facing
Audio:
TI TWL6040A
WiFi / BT:
Bluetooth and WLAN 802.11 b/g/n
LSR TiWi-R2
Other interfaces:
HDMI, USB OTG, RS-232 (Debug)
Non-Volatile Memory:
Up to 32GB SD 8GB on board eMMC
Power Management:
TI (TWL6030 Power Management Companion IC)
Cellular Interface:
Socketed Wireless modules support for UMTS/
HSDPA and CDMA
Battery:
25Wh Battery Dual Cell Polymer Li-Ion
World Wide Electronics Design
and Manufacturing Services
Project Description
Low power, low cosI, IableI plaIIorm uIilizihg T
OMAP 4 processors
CusIomized Ior CusIomer requiremehIs
Target Markets
Medical, MiliIary/Aerospace, hdusIrial
Puggedized soluIiohs
Design Services
hdusIrial Desigh
Mechahical Desigh
ElecIrical Desigh
SoIIware Desigh
Process ahd TesI DevelopmehI
Volume Manufacturing
New producI ihIroducIioh services
Low / medium volume
TECHNICAL SPECS
Software:
Android 2.3 Gingerbread
4.0 Ice Cream Sandwich; QNX
Processor:
TI OMAP 4 family of processors
Memory:
Micron 8Gb POP LPDDR2
Display / User Interface:
10.1 Projected Capacitive Multi-Touch interface
WSVGA 1024 x 600 LCD with LED Backlight - 262K
(RGB 6-bits).
Accelerometer / Gyro:
STMicro LSM303DLHC 3-axis MEMS accelerometer
3 axis magnetometer
STMicro L3G4200D 3-axis MEMS gyroscope
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64 Engineering Services Embedded Processing & DSP Resource Guide 2013
CONTACT INFORMATION
Micross Components
Micross Components
7725 N. Orange Blossom Trail
Orlando, Florida 32810
USA
1-855-4COMPONENTS Toll Free
407-290-0164 Fax
sales.americas@micross.com
www.micross.com
FEATURES & BENEFITS
Board real estate savings of up to 60%
Extended environment for industrial and military
applications
Simplifed I/O down routing
Reduced trace lengths for improved parasitic perfor-
mance at frst and second level and superior signal
integrity
Reduced component count and wider pitch ball
placements
AVAILABILITY
Die and packaging solutions from Micross Components
are available now. For more information please visit our
website at www.micross.com
APPLICATION AREAS
Audio, Automotive, Communications & Telecom, High
Performance Compute, Industrial, Medical, Military,
Security, Video, Wireless
DSP & Microcontroller Die
and Alternative Packaging
The Micross family of COTS DDR and DDR2 SDRAM is
designed to provide PCB engineers with high density
memory solutions that support the wide data widths
and extended environments demanded by embedded
applications.
Micross high performance memory is available in BGA
packages as small as 1 in2 with either 1.27mm or 1.0mm
pitch. Our memory also features data transfer rates of
up to DDR2-667 and adjustable data with output drive
strength and 4-bit pre-fetch architecture.
With densities of 256MB, 512MB, and 1GB in x72
and x64 configurations, our SDRAM memory pro-
vides significant benefits for designers. By typically
providing greater than 50% space savings over con-
ventional TSOP or FBGA designs, PCB layout takes
advantage of lower component counts. Simplified
memory-down routing can reduce routing time for
board designers and save up to 4 layers in the PCB.
This enables Class 3 PCB rule compliance since .5mm
and .65mm pitch memory parts can be avoided. Accu-
rate placement of wider pitch parts on larger capture
pads are advantages accrued by the assembly side of
the business. Simplified routing opens up board real
estate for additional product features for the user.
The result is an opportunity to capture more sales
with a richer feature set.
Micross memory products also improve parasitic per-
formance at both the first and second level. Use of
Micross iPEM provides reduced bus capacitance and
increased signal integrity.
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SPECTRUM DIGITAL
SOLUTION
SPECTRUM DIGITAL
SOLUTION
One Source For High
Performance TI DSP
Development Tools
One Source For High
Performance TI DSP
Development Tools
Stafford, Texas 77477
T: 281.494.4500 F: 281.494.5310
www.spectrumdigital.com
8/15/12
|me|ctets:
XDS560v2, XDS560v2 STM Traveler,
XDS560v2 LC Traveler, XDS510 USB,
XDS510USB PLUS, XDS100v2/v3,
XDS100v3, XDS510USB Galvanic,
XDS510PP PLUS, C2000 XDS510LC,
SPI530 MPSD, JTAG Pin Adapters
0e|eggets:
TI Code Composer Studio
TM
IDE
|vc|ect|ea Ne6e|es:
VC5502/VC5505/C5515/C6455/
DM355/DM357/DM365/DM368/
DM642/DM6446/DM6467/
AM1807/AM1808/AM1810
eI6s
TM
, 0SKs, 0SKs ca6 eI1I0
DSKs for F2407/VC5416/VC5509A/
VC5510/C6713/C6416T/C6455,
eI6s Iet ||2101kJ||210IkJC33J
F2808/F2812/R2812/F28335/
C5505JC5515JC5502, eI1I0
and OSKs for OMAP-L137
SeItwcte Iee|s:
'C' tem||ets, cssem||ets, ||akets
FLASH Programming Utilities
k||tct|ea SeItwcte
eCkh Stctk, |aet Stctk, k|get|t|m
Wizard,CodeBox
TM
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TM
0SP SeItwcte
Beea6cty Stca Iest SeItwcte:
Iemeate 0|cIem 0e|egget Iet I| 0SPs
N|ste||caeees:
Digital Motor Controllers,
Ptetetye Ne6e|es,
Pewet Se||es, IIk6 |xca6et
ARGENTINA/CHILE/ECUADOR/URUGUAY. S7&.Zl.IZ.J.J /USTRALI/. I.J.7lZJ.SJ++ K|NELUl. JI.J+S.S+S.SJS KRAZIL. SS.II.J+ZZ.+ZJJ KULGARIA: 359.2.953.0078
COLUKI/. SI.JZSl.++I |RANC|. JJ.SI.JJ.7.JJ GERMANY. +7.Z&JJ.SlJ7ll INDI/. 7I.&J.Z.&I&J INDI/. 7I.JII.SIJJ &ISS ISRAEL: 972.3.9002727
ITALY. J7.JlS&.Z7&S.JI !/|/N: 81.53.762.3681, !/|/N. &I.J.S&ZJ.JI7I KOR|/. &Z.Z.&SS.+JSl KOR|/. &Z.J.ZJZS.JJ&& |lICO: 52.33.3825.0667
|R OF CHIN/. &.IJ.&ZJS.lSl7, JZI.I7.IJ&&, JIJ.ZJ.&J&&, &.lSS.&JJS.+&&&, &.Z&.&S.SJIJ, &SZ.ZZ&.7&&& |/KISTAN. 7Z.ZI.JZlZIlJ |OLAND: 48.22.724.30.39
RUSSI/. l.+7S.l&I.+7+S 'C/NDINAVI/. +.+J.lJ.IlIJ 'ING/|OR|. S.l++.7l&7 'WITZERLAN9. +I.JI7lZJISZ 'OUTH AFRICA: 27.11.882.6836
'|/IN. J+.7J+.I&.SJ+l I/IW/N. &.Z.Z&&.IIl7I IURK|Y. 7J.ZIZ.+S.lI77 lI+Z UNII|9 KINGDO. ++.IJ.JSIJJ \IETNAM: 84.4.785.3060
/RROW |LECTRONIC'. &JJ.&JJ.JSSl /\N|I. &JJ.JJZ.&J& 9IGI-K|Y. &JJ.J++.+SJ7 |N/KLE ENGINEERING: 800.686.6428
OUSER ELECTRONIC'. &JJ.J+.&lJ N|W/RK. &JJ.+J.7ZlS
INTERNATIONAL RESELLERS
NORTH AMERICAN RESELLERS

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Embedded Processing & DSP

Advanced emulator controller

2012 Extension Media

Cortex-A8 and ARM9 Processors ..........................................................................................................30

Cortex-M MCUs ........................................................................................................................... 31

Processors Married Once Again

and complementary analog products, offering

video processor solutions are tailored

DSP platform offers the industrys

DSP platform provides a broad

32-Bit Micro controller for

microcontroller family combines

MCUs, the powerful

floating-point MCUs and the connectivity

-A8 and ARM9

32-Bit ARM Cortex-M MCUs

Software, Stellaris gives developers

-based microcontroller families

DSPs are supported by eXpressDSP

high performance fixed/

ultra-low power fixed-point

MCU core with

Microcontrollers, Fixed-Point and Floating-Point

(176 256 pins)

(38 100 pins)

controller platform provides an optimized combination of DSP performance

-M3 core with C2000s C28x core in

16-bit RISC CPU

MCUs orthogonal architec-

-A8 and ARM9

family block diagram

Video Processors: Optimized for Digital Video

Cortex-A8, AM18x ARM9, AM17x ARM9

Annual Industry Guide

Cortex-A8, AM18x ARM9, AM17x ARM9

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