Barrel

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity barrel is
PORT(datain:in std_logic_vector(7 downto 0);
opcode:in std_logic_vector(2 downto 0);
count:in std_logic_vector(2 downto 0);
dataout:out std_logic_vector(7 downto 0)
);
end barrel;
architecture Behavioral of barrel is

begin
process(opcode,count)
begin
--takin count as case statement
case count is
--this case indicates there is no shift and rotate
when"000"=>
if opcode="000"then
dataout<=datain;
elsif opcode="001"then
dataout<=datain;
dataout<=datain;
dataout<=datain;
dataout<=datain;
dataout<=datain;
end if;
--this case indicates input data in shifted by 1 bit
when "001"=>
if opcode="000"then --shift right logical
dataout<="0"&datain( 7 downto 1);
elsif opcode="001"then --shift right arithmetic
dataout<=datain(7)& datain(7 downto 1);
elsif opcode="010"then --rotate right
dataout<=datain(0) & datain(7 downto 1);
elsif opcode="100"then --shift left logical
dataout<=datain(6 downto 0) &"0";
elsif opcode="101"then --shift left arithmetic
dataout<=datain(7)&datain(5 downto 0) &"0";
elsif opcode="110"then--rotate left
dataout<=datain(6 downto 0) & datain(7);
end if;
--this case indicate that input data is shifted by 2 bits

when "010"=>
if opcode="000"then
dataout<="00" & datain(7 downto 2);
dataout<=datain(7)&datain(7)&datain(7 downto 2);
dataout<=datain(1 downto 0)&datain(7 downto 2);
dataout<=datain(7)&datain(4 downto 0)&"00";
dataout<=datain(5 downto 0)&datain( 7 downto 6);
end if;
--this case indicates that data is shifted by 3 bits
when "011"=>
if opcode="000"then
dataout<="000" &datain( 7 downto 3);
dataout<=datain(7)&datain(7)&datain(7)&datain(7 downto 3);
dataout<=datain(2 downto 0) &datain( 7 downto 3);
dataout<=datain(7)&datain(3 downto 0)&"000";
dataout<=datain(4 downto 0 )&datain( 7 downto 5);
end if;
--this case indicates that input data is shifted by 4 bits
when "100"=>
if opcode="000"then
dataout<="0000" & datain(7 downto 4);
dataout<=datain(7)&datain(7)&datain(7)&datain(7)&datain(7 downto 4);
dataout<=datain(7)&datain(2 downto 0) & "0000";
dataout<=datain(3 downto 0)&datain( 7 downto 4);
end if;
when "101"=>
if opcode="000"then
dataout<="00000" &datain( 7 downto 5);
dataout<=datain(7)&datain(7)&datain(7)&datain(7)&datain(7)&datain(7 downto 5);
dataout<=datain(4 downto 0) & datain(7 downto 5);

dataout<=datain(7)&datain(1 downto 0 )& "00000";
dataout<=datain(2 downto 0) & datain(7 downto 3);
end if;
when "110"=>
if opcode="000"then
dataout<="000000"&datain( 7 downto 6);
dataout<=datain(7)&datain(7)&datain(7)&datain(7)&datain(7)&datain(7)&datain(7 downto 6);
dataout<=datain(7)&datain( 0) &"000000";
end if;
--this case indicates that the input data is shifted by 7 bits
when others=>
if opcode="000"then
dataout<="0000000" &datain(7);
dataout<=datain(7)&datain(7)&datain(7)&datain(7)&datain(7)&datain(7)&datain(7)&datain(7);
dataout<=datain(6 downto 0)&datain(7);
dataout<=datain(0) &"0000000";
dataout<=datain(7)&"0000000";
dataout<=datain(0)&datain( 7 downto 1);
end if;
end case;
end process;
end Behavioral;
8BIT LOGICAL RIGHT SHIFTER
library IEEE;

--library UNISIM;
ENTITY LOGICRIGHT IS
PORT(I:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
COUNT:in STD_LOGIC_VECTOR(2 DOWNTO 0);
Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END LOGICRIGHT;
architecture STRUCT OF LOGICRIGHT IS
SIGNAL X,W:STD_LOGIC_VECTOR(7 DOWNTO 0);
COMPONENT MUX2_1 IS
port(A,B:IN STD_LOGIC;
SEL:IN STD_LOGIC;
MOUT:OUT STD_LOGIC
);
END COMPONENT;
BEGIN
--RIGHT SHIFT BY 4 BIT
MO:MUX2_1 PORT MAP ('0',I(7),COUNT(2),X(7));
M1:MUX2_1 PORT MAP ('0',I(6),COUNT(2),X(6));
M4:MUX2_1 PORT MAP (I(7),I(3),COUNT(2),X(3));
--RIGHT SHIFT BY 2 BITS
M8:MUX2_1 PORT MAP ('0',X(7),COUNT(1),W(7));
M9:MUX2_1 PORT MAP ('0',X(6),COUNT(1),W(6));
M10:MUX2_1 PORT MAP (X(7),X(5),COUNT(1),W(5));

M16:MUX2_1 PORT MAP ('0',W(7),COUNT(0),Y(7));
M17:MUX2_1 PORT MAP (W(7),W(6),COUNT(0),Y(6));
end STRUCT;
8 BIT RIGHT ROTATE

library IEEE;

--library UNISIM;
ENTITY ROTATERIGHT IS
);
END ROTATERIGHT;
architecture STRUCT OF ROTATERIGHT IS
COMPONENT MUX2_1 IS
SEL:IN STD_LOGIC;
MOUT:OUT STD_LOGIC
);
END COMPONENT;
BEGIN
MO:MUX2_1 PORT MAP (I(3),I(7),COUNT(2),X(7));

end STRUCT;
8 BIT ARITHMETIC RIGHT SHIFT

library IEEE;

--library UNISIM;
ENTITY ARITHMETICRIGHT IS
);
END ARITHMETICRIGHT;
architecture STRUCT OF ARITHMETICRIGHT IS
COMPONENT MUX2_1 IS
SEL:IN STD_LOGIC;
MOUT:OUT STD_LOGIC
);
END COMPONENT;
BEGIN
MO:MUX2_1 PORT MAP (I(7),I(7),COUNT(2),X(7));

end STRUCT;
8 BIT RIGHT SHIFT/ROTATE(ARITHMETIC AND LOGICAL)

library IEEE;

--library UNISIM;
ENTITY RIGHTROTSHT IS
PORT(I
:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
COUNT :IN STD_LOGIC_VECTOR(2 DOWNTO 0);

SAL :IN STD_LOGIC;
SRS :IN STD_LOGIC;
Y
:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
--COUNT->AMOUNT TO BE SHIFTED OR ROTATED
END RIGHTROTSHT;
architecture STRUCT OF RIGHTROTSHT IS

SIGNAL S:STD_LOGIC;
SIGNAL P:STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL X:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL D:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL Z:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL W:STD_LOGIC;
COMPONENT MUX2_1 IS
SEL:IN STD_LOGIC;
MOUT:OUT STD_LOGIC
);
END COMPONENT;
BEGIN
--TO decide whether to use logical or arithmetic
--sal->0 logical sal->1 arithmetic
M_D:MUX2_1 PORT MAP ('0',I(7),SAL,S);
--TO DECIDE WETHER TO ROTATE OR SHIFT BY 4 BITS

--SRS->0 SHIFT..SRS->1 ROTATE
MA:MUX2_1 PORT MAP (S,I(3),SRS,P(3));
MB:MUX2_1 PORT MAP (S,I(2),SRS,P(2));
MC:MUX2_1 PORT MAP (S,I(1),SRS,P(1));
MD:MUX2_1 PORT MAP (S,I(0),SRS,P(0));
--RIGHT ROTATE/SHIFT BY 4 BIT

MO:MUX2_1 PORT MAP (I(7),P(3),COUNT(2),X(7));
M1:MUX2_1 PORT MAP (I(6),P(2),COUNT(2),X(6));
ME:MUX2_1 PORT MAP (S,X(1),SRS,D(1));

MF:MUX2_1 PORT MAP (S,X(0),SRS,D(0));
--RIGHT ROTATE/SHIFT BY 2 BITS

M8:MUX2_1 PORT MAP (X(7),D(1),COUNT(1),Z(7));
M9:MUX2_1 PORT MAP (X(6),D(0),COUNT(1),Z(6));
M10:MUX2_1 PORT MAP (X(5),X(7),COUNT(1),Z(5));

MG:MUX2_1 PORT MAP (S,Z(0),SRS,W);
--RIGHT ROTATE/SHIFT BY 1 BIT
M16:MUX2_1 PORT MAP (Z(7),W,COUNT(0),Y(7));

M17:MUX2_1 PORT MAP (Z(6),Z(7),COUNT(0),Y(6));
end STRUCT;

Barrel

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library IEEE;

---- Uncomment the following library declaration if instantiating

architecture Behavioral of barrel is

--this case indicate that input data is shifted by 2 bits

dataout<=datain(2 downto 0) &"00000";

8BIT LOGICAL RIGHT SHIFTER

---- Uncomment the following library declaration if instantiating

architecture STRUCT OF LOGICRIGHT IS

SIGNAL X,W:STD_LOGIC_VECTOR(7 DOWNTO 0);

M12:MUX2_1 PORT MAP (X(5),X(3),COUNT(1),W(3));

8 BIT RIGHT ROTATE

---- Uncomment the following library declaration if instantiating

architecture STRUCT OF ROTATERIGHT IS

SIGNAL X,W:STD_LOGIC_VECTOR(7 DOWNTO 0);

M13:MUX2_1 PORT MAP (X(4),X(2),COUNT(1),W(2));

8 BIT ARITHMETIC RIGHT SHIFT

---- Uncomment the following library declaration if instantiating

architecture STRUCT OF ARITHMETICRIGHT IS

SIGNAL X,W:STD_LOGIC_VECTOR(7 DOWNTO 0);

M13:MUX2_1 PORT MAP (X(4),X(2),COUNT(1),W(2));

8 BIT RIGHT SHIFT/ROTATE(ARITHMETIC AND LOGICAL)

---- Uncomment the following library declaration if instantiating

:IN STD_LOGIC_VECTOR(7 DOWNTO 0);

COUNT :IN STD_LOGIC_VECTOR(2 DOWNTO 0);

:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

architecture STRUCT OF RIGHTROTSHT IS

SIGNAL P:STD_LOGIC_VECTOR(3 DOWNTO 0);

--TO DECIDE WETHER TO ROTATE OR SHIFT BY 4 BITS

MD:MUX2_1 PORT MAP (S,I(0),SRS,P(0));

--RIGHT ROTATE/SHIFT BY 4 BIT

--TO DECIDE WETHER TO ROTATE OR SHIFT BY 2 BITS

ME:MUX2_1 PORT MAP (S,X(1),SRS,D(1));

--RIGHT ROTATE/SHIFT BY 2 BITS

M13:MUX2_1 PORT MAP (X(2),X(4),COUNT(1),Z(2));

--TO DECIDE WETHER TO ROTATE OR SHIFT BY 2 BITS

MG:MUX2_1 PORT MAP (S,Z(0),SRS,W);

--RIGHT ROTATE/SHIFT BY 1 BIT

M16:MUX2_1 PORT MAP (Z(7),W,COUNT(0),Y(7));

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