A

Cover Sheet

888Z3 LA-1044 REV2.0 SCHEMATIC DOCUMENT

Intel (Tualatin) with VIA(VT8606-TwisterT + VT8231)
3

BOM

LN_ SKU W/SS

L@ SKU WO/SS
1394@ SKU W/1394
TV@ SKU W/TVOUT
DJ@ SKU W/AUDIO DJ
DJN_ SKU WO/AUDIO DJ
EQ@ SKU W/EQ
EQN_ SKU WO/EQ
F@ SKU W/FPR
FN_ SKU WO/FPR
SPR@ SKU W/DOCKING CONN.

JOPEN1
JOPEN8
JOPEN9
JOPEN10

PCB Layer
Structure:
TOP
GND1
IN1
GND2
VCC
IN2
GND3
BOT

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

of

44

Block Diagram

Compal confidential
Model Name : 888Z3/LA-1044 (Intel Tualatin)

Intel
Tualatin Micro-FCPGA
page 3,4,5

page 6

VID
SELECT
page 7

Y1
14.318MHZ

CRT Connector

14M_3V

VIA North Bridge

Twister-T

page 14

Power On/Off
Reset Circuit

Clock Generator
CY28317-2

DCLKWR

page 8,9,10

TV Encoder
CH7005

TV/Out
Connector

page 33

AD(0..31)

DC/DC Interface
RTC Battery

MD(0..63)

page 15

page 14

page 14

page 11 +3VSUS

PCLK_PCM

+3VRUN

DCLKO

TFT/HPA Panel
Interface

page 32

14M_5V
PCLK_DOCK

CLK_SDRAM0,1
CLK_SDRAM1,2

SO-DIMM 0
(Bank 0,1)

SO-DIMM 1
(Bank 2,3)
page 13

page 12

USB
Port 3
FingerPR

PCLK_PIIX4

SpeedStep
Logic

MA(0..13)

PCI BUS

page 36

AC Link

Mini PCI
Socket

PCMCIA

VIA VT6306

ENE CB1410

1394 Controller

page 36

page 16

page 18

AC97
Codec
page 24

VIA South Bridge

VT8231

USB
HUB

CLK_48MHZ

page 37

14M_3V

page 19,20,21

Slot 0

* HSP Modem Card

* Combo for HSP Modem and
802.11b
* Controllerless Modem
* Combo for Controllerless
Modem and 802.11b

page 17

Speaker

page 26

page 30

AMP
Jack

page 25

page 26

page 28

USB
Port 2

page 37

LAN
RTL8100

NS87591

page 29

PIO

IDE Damping
Resistor

KeyBoard

Docking Connector

page 28

* DC-IN
* 2 USB Port
* TV Out (S Video)
* VGA Out
* 2 PS/2
* LAN
* Parallel Port
* Serial Port
* Line Out
* Headphone
* Microphone

page 22

page 31

FIR

page 27

Touch Pad
page 33

Power Circuit
DC/DC

KBD

page 32

HDD
Connector
page 22

CD Player
OZ163
page 23

I/O Buffer
page 32

page 37,38,39,40

page 35

CD-ROM
Connector

BIOS

page 32
4

USB
Port 3
Bluetooth

page 27

LPC BUS
14M_5V

RJ45/RJ11
Jack

USB
Port 0,1

Audio
EQ

page 22

PCB1

LA-1044 PCB
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

of

44

Tualatin/Celeron-T CPU

+CPU_CORE

A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35

R1
L3
T1
U1
L1
T4
AA3

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
RP#
ADS#

W2
AB3
P3
C14
AF23
AF4

AERR#
AP#0
AP#1
BERR#
BINIT#
IERR#

8 H_BPRI#
8 H_BNR#
8 H_LOCK#

A7
C4
C22
AD23
R2
L2
V3

BREQ0#
NC
NC
NC
BPRI#
BNR#
LOCK#

8 H_HIT#
8 H_HITM#
8 H_DEFER#

AA2
U2
T3

HIT#
HITM#
DEFER#

8 H_REQ#[0..4]

H_REQ#[0..4]
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

8 H_ADS#

+1.5VS
3

8 H_BREQ0#

PIR(37)

R229
1

1.5K_0402
2

1
R249
1
R250

2
@0_0402
2
10_0402

TUALATIN

VCC

Address
Lines

Mobile
Tualatin

Data
Signals

Request
Signals

Error
Interface

Arbitration
Signals
Snoop
Signals

VSS

VCC

VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74
VCC_73

K1
J1
G2
K3
J2
H3
G1
A3
J3
H1
D3
F3
G3
C2
B5
B11
C6
B9
B7
C8
A8
A10
B3
A13
A9
C3
C12
C10
A6
A15
A14
B13
A12

H_D#[0..63]

D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

A16
B17
A17
D23
B19
C20
C16
A20
A22
A19
A23
A24
C18
D24
B24
A18
E23
B21
B23
E26
C24
F24
D25
E24
B25
G24
H24
F26
L24
H25
C26
K24
G26
K25
J24
K26
F25
N26
J26
M24
U26
P25
L26
R24
R26
M25
V25
T24
M26
P24
AA26
T26
U24
Y25
W26
V26
AB25
T25
Y24
W24
Y26
AB24
AA24
V24

H_D#[0..63] 8

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

P6
M6
AC5
AA5
AB6
W5
Y6
U5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72

U8A

H_A#[3..31]

E16 VSS_0
R4 VSS_1
E25 VSS_2
G25 VSS_3
J25 VSS_4
L25 VSS_5
N25 VSS_6
R25 VSS_7
U25 VSS_8
W25 VSS_9
AA25 VSS_10
AC25VSS_11
AF25 VSS_12
AE26 VSS_13
C23 VSS_14
F23 VSS_15
H23 VSS_16
K23 VSS_17
M23 VSS_18
P23 VSS_19
T23 VSS_20
V23 VSS_21
Y23 VSS_22
AB23 VSS_23
AE23 VSS_24
B22 VSS_25
D21 VSS_26
F21 VSS_27
E22 VSS_28
H21 VSS_29
G22 VSS_30
K21 VSS_31
J22 VSS_32
M21 VSS_33
L22 VSS_34
P21 VSS_35
N22 VSS_36
T21 VSS_37
R22 VSS_38
V21 VSS_39
U22 VSS_40
Y21 VSS_41
W22 VSS_42
AB21 VSS_43
AA22 VSS_44
AC22VSS_45
AE21 VSS_46
B20 VSS_47
D19 VSS_48
AB19 VSS_49
AA20 VSS_50
AC20VSS_51
AE19 VSS_52
B18 VSS_53
D17 VSS_54
F17 VSS_55
E18 VSS_56
AB17 VSS_57

8 H_A#[3..31]

D22
F22
E21
H22
G21
K22
J21
M22
L21
P22
N21
T22
R21
V22
U21
Y22
W21
AB22
AA21
AC21
D20
F20
E19
AB20
AA19
AC19
D18
F18
E17
AB18
AA17
AC17
D16
F16
E15
AB16
AA15
AC15
D14
F14
E13
AB14
AA13
AC13
D12
F12
E11
AB12
AA11
AC11
D10
F10
E9
AB10
AA9
AC9
D8
F8
E7
AB8
AA7
AC7
D6
F6
E5
H6
G5
K6
J5
N5
T6
V6

+CPU_CORE
4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044

Size

Document Number

Custom

401196

Date:

, 17, 2002

Rev
2A
Sheet
E

of

44

+1.5VS

VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129

U8B

AA18
AC18
AE17
B16
D15
F15
AB15
AA16
AC16
AE15
B14
D13
F13
E14
AB13
AA14
AC14
AE13
B12
D11
F11
E12
AB11
AA12
AC12
AE11
B10
D9
F9
E10
AB9
AA10
AC10
AE9
B8
D7
F7
E8
AB7
AA8
AC8
AE7
B6
F5
H5
G6
K5
J6
N6
L6
T5
R6
V5
U6
Y5
W6
AB5
AA6
AC6
AE5
B4
D4
F4
H4
K4
M3
U4
W4
B2
D2
F2
H2

Tualatin/Celeron-T CPU
+VCPU_IO

6 GT_IGNNE#
6 GT_SMI#
6 H_PWRGD
6 GT_STPCLK#
20,40 H_DPSLP#
6 GT_INTR
6 GT_NMI
6 GT_CPUINIT#
C598
+1.5VS

GT_INTR
GT_NMI

AC3
AF6
AF5
AD9
AD3
AB4
AE4
AF8
AD15
AE14
AE6
B15
W3
Y1

8 H_DBSY#
8 H_DRDY#

L@1UF_0603

VTT Ref

DBSY#
DRDY#

Analog

11 BSEL1
THERMDA
THERMDC

Mobile
Tualatin

AE12 SELFSB0
AF10 SELFSB1
2 AF16
110_1%_0402 EDGECTRLP

Y4
R5
N3
N2
P1
P5
E1
F1

CLK0
CLK0#
TESTLO

AC1
AD1
M1

2
56.2_1%_0402

L5

6 CPU_LO/HI#

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7

( ITP )

VCCT

VID

VTTPWRGOOD

GHI#

+VCPU_IO

+3VS

Test
Access
PORT

CMOSREF_1
CMOSREF_0
RTTIMPDEP

But pull high too weak

MAINP

+V_AGTLREF
+CPU_CORE
+VCPU_IO

TESTLO1
L46
1
2
LQG21N4R7K10_4.7UH

VCPU_PLL1
VCPU_PLL2

C370

33UF_16V_D2

CLK_HCLK
CLK_HCLK#
TESTLO2

AF18
AD16
AF11
AE8
N24
AE10
E2

NCHCTRLP
TESTHI1

1
2
R209 14_1%_0402

TESTHI2
CLK_HCLK

NC
TCK
TDI
TDO
TMS
TRST#
PREQ#
PRDY#

Note :
GHI# Pull-Up internally

TESTLO1
TESTLO2
TESTHI2
TESTHI1

8P4R_1K_0804

NC

P4

CLK_HCLK#

AD4
A5
D1
AD13
B1
P26
A11

R262

R258

@33_0402

@33_0402

C369

C367

@10PF_0402

@10PF_0402

VTT_PWRGD

E3
D26

+VCPU_IO

VSS_142
VSS_141
VSS_140
VSS_139
VSS_138
VSS_137
VSS_136
VSS_135
VSS_134
VSS_133
VSS_132
VSS_131
VSS_130

1
R212

AF12
AD5
AE16

Debug
Break
Point

F19
E20
C25
A25
AE1
AD2
AB2
Y2
V2
T2
P2
M2
K2

+VS_CMOSREF

AD10
AD7
AD11
AF7
AF15
AF19
AE22

RP2#
RP3#
BPM0#
BPM1#

NC
NCHCTRLP
TESTHI
NC
NC
NC
TESTHI

C1 NC
AF17 NC
N4 NC

ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_PREQ#
ITP_PRDY#

APIC

B26 VSS
M4 VSS
AF26 VSS

2
@33_0402 AF22
AE20
AD22
AD21

PICD0
PICD1
PICCLK

A26 VCCT_1
G23 VCCT_2
J23 VCCT_3
L23 VCCT_4
N23 VCCT_5
R23 VCCT_6
U23 VCCT_7
W23 VCCT_8
AA23 VCCT_9
C21 VCCT_10
C19 VCCT_11
AD20VCCT_12
C17 VCCT_13
AD18VCCT_14
C15 VCCT_15
C13 VCCT_16
AD14VCCT_17
C11 VCCT_18
AD12VCCT_19
C9 VCCT_20
C7 VCCT_21
AD8 VCCT_22
C5 VCCT_23
AD6 VCCT_24
AC23VCCT_25
AA4 VCCT_26
E4 VCCT_27
G4 VCCT_28
J4 VCCT_29
L4 VCCT_30
AC4 VCCT_31
V4 VCCT_32
AE3 VCCT_33
AF2 VCCT_34
AF1 VCCT_35
AE18 VCCT_36
D5 VCCT_37
E6 VCCT_38

1
R196
R199
@10PF_0402
@137_1%_0402

PIR(19)

AD19
AD17
AF20

PIC_CLK
C278

8
7
6
5

+VCPU_IO

VID0
VID1
VID2
VID3
VID4

1
R60

AB1
AC2
AE2
AF3
R3

AF13
AF14

150_0402

1
2
R194
0_0402
*26.7_1%_0402

11 CLK_CPU_APIC

R218 1K_0402
1
2
1
2
R220 @1K_0402

R200

150_0402

TESTLO
VCC
PLL1
PLL2
NC
NC
NC
NC

+VCPU_IO

H_THERMDA
H_THERMDC

AF21
AB26
H26
A21
AF9
A4
N1
AA1

Data
Signals

A20M#
FERR#
FLUSH#
IGNNE#
SMI#
PWRGOOD
STPCLK#
DPSLP# Compatibility
INTR/LINT0
NMI/LINT1
INIT#
RESET#

+3VS

+1.5VS

PIR(37)

R202

VREF_1
VREF_2
VREF_3
VREF_4
VREF_5
VREF_6
VREF_7
VREF_8

GND

1
2
3
4

GT_A20M#
H_FERR#
H_FLUSH#
GT_IGNNE#

6 GT_A20M#

8,20 CPURST#

Request
Signals

AE24
AD25
AE25
AC24
AF24
AD26
AC26
AD24

8 H_TRDY#

RP28
DEP#0
DEP#1
DEP#2
DEP#3
DEP#4
DEP#5
DEP#6
DEP#7

PIR(37)

3K_0402 1.5K_0402
2

1.5K_0402

R226

RS#0
RS#1
RS#2
RSP#
TRDY#

R225

R228

Y3
V1
U3
M5
W1

8 H_RS#0
8 H_RS#1
8 H_RS#2

Place CPURST# R208

R208<0.1" from
1K_0402
U6

+1.5VS

+1.5VS

R267
2K_0402

TUALATIN
2

W=40mil
1

VTT_PWRGD

200_0402
C89

+1.5VS

31 THERMDA_591
31 THERMDC_591

From 87591

+VCPU_IO

+1.5VS

2
56.2_1%_0402

R187 @0_0402
1
2
1
2
R188 @0_0402
A

+3VS

CLK_BCLK

11 CLK_BCLK

R492
FERR# 20

ITP_PREQ#

2
200_0402

1K_0402
2

R214 1K_0402
1
2

Q12
3 FDV301N

R266
475_1%_0402

RP8

R44
H_FERR#
ITP_TMS

@10K_0402

10
9
8
7
6

1
2
3
4
5

ITP_TRST#
ITP_TDO
ITP_TCK
ITP_TDI

11 CLK_BCLK#

10P8R-1.5K
Title

+3VS

Address:1001_110X

R259 1
R264 1

PIR(1)

R45
1

C371
@2.2UF_10V_0805

ITP_PRDY#

4.7K_0402

R191
R62

EC_SMC2 23,31,35
EC_SMD2 23,31,35

GND
GND

14
12
11

R201
1.5K_0402

2200PF_0402
H_THERMDC

DXN

VCC

STBY#

15

@0_0402
2

@0_0402

C87

SMBC
SMBD
ALERT#

ADD0
ADD1

R58

@0_0402
2
CRTIT0
CRTIT1
H_THERMDA

Thermal Sensor
MAX1617

U25

8
7

R46
1

MAX1617
16 NC
13 NC
9 OS#
5 CRIT0
1 CRIT1
3 DXP

10
6

@0_0402

@0_0402

R59

R57

R54

+3VS

.1UF_0402

10K_0402 R52 10K_0402

Q31
2

2N7002

VTT_PWRGD#

7
7
7
7
7

11,31,42 VTT_PWRGD#
CPU_VR_VID4
CPU_VR_VID3
CPU_VR_VID2
CPU_VR_VID1
CPU_VR_VID0

R51

+3VS

+3VS

R55

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
C

R261 1
CLK_BCLK# R260 1

CLK_HCLK
2 33_0402
2 60.4_1%_0402

Place all these Block's

Components near CPU (U6)
4

2 60.4_1%_0402
CLK_HCLK#
2 33_0402

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044

Size
Custom

Date:

Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

of

44

CPU Decoupling CAP.

Layout note :
Place close to CPU, Use 2~3 vias per PAD.
Place 0.22uF caps underneath balls on solder side.
Place 10uF caps on the peripheral near balls.
Use 2~3 vias per PAD.

Layout note :

.22UF

.22UF

.22UF

.22UF

.22UF

1
C339

C285
.22UF
2

C284

1
C288
.22UF
2

C287
2

C321
.22UF
2

C272

C271
.22UF

C92
470UF_4V_D4
ESR=18m ohm

.22UF

C270
2

C283
.22UF
2

C275
2

C274
.22UF

+VCPU_IO

+CPU_CORE

Place close to CPU,

Use 2 vias per PAD.

C368
220UF_2.5V_D2
ESR=25m ohm

C=690uF

ESR=10.465m
ESR=10.465m ohm .
(CPU)

+CPU_CORE

1
C316
1UF_10V

C334
1UF_10V

C340
1UF_10V
2

C301
1UF_10V

1
C289
1UF_10V
2

C273
1UF_10V
2

C322
1UF_10V

1
C304
1UF_10V

C286
1UF_10V

C269
1UF_10V

.22UF

C318

2
.22UF

C317
.22UF
2

.22UF

C335

.22UF

C320
.22UF
2

C319

.22UF

C303
.22UF
2

C302

C300
.22UF

.22UF

C299
2

C337
.22UF
2

C338
2

C336
.22UF

+VCPU_IO

C67
10UF_6.3V_P
2

C68
10UF_6.3V_P
2

C69
10UF_6.3V_P
2

C70
10UF_6.3V_P
2

C71
10UF_6.3V_P

+CPU_CORE

C232
10UF_6.3V_P

Tualatin

C233
10UF_6.3V_P
2

C234
10UF_6.3V_P
2

C235
10UF_6.3V_P
2

C236
10UF_6.3V_P

+CPU_CORE

D4 D3 D2 D1 D0

QS( MP)

1
C104
470UF_4V_D4
ESR=18m ohm

0 0 1 1 1

1.40V

0 1 1 0 0

1.15V

------------------------------------------------------C102
470UF_4V_D4
ESR=18m ohm

300 MHz & 0.95V : 4.11A

500 MHz & 1.05V : 6.38A
533 MHz & 1.05V : 6.61A
700 MHz & 1.10V : 8.40A
733 MHz & 1.15V : 9.39A
800 MHz & 1.15V : 9.84A
1000 MHz & 1.40V : 16.83A
1066 MHz & 1.40V : 17.46A
1133 MHz & 1.40V : 18.11A

C62
470UF_4V_D4
ESR=18m ohm

+
2

C76
470UF_4V_D4
ESR=18m ohm

CPU_Core(V)

-------------------------------------------------------

+CPU_CORE

EMTS updated by the note released on April 27 , 2001.

C230
220UF_2.5V_D2
ESR=25m ohm

C231
+
220UF_2.5V_D2
ESR=25m ohm

+CPU_CORE

Ctotal=2320uF
ESR=3.309m
ohm

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044

Size

Document Number

Custom

401196

Date:

, 17, 2002

Rev
2A
Sheet
E

of

44

Geyserville Logic
without Geyserville,
GHI#(CPU_LO/HI#) can
OPEN

U32
LN_AMI11686-001

1
2
3
4

+1.5VS
20
16
22
24
21
17

HSMI#

3
11
47

RESERVED

46

GHI#

10

CPUPWRGD
VRPWRGD

9
32

H_PWRGD
G_VR_POK

12
33
34

VRCHGNG#
VR_HI/LO#

35
39
40

23
19
13

STPCLK#
SUSSTAT1#
CPU_STP#

GT_LO/HI#

14

G_LO/HI#

VGATE

15
29
43

VR_ON
VGATE
IGN_VGATE#

28
44

VR100/50#
PLL30/60#

41

CRESET#

VRCHGNG#
VR_HI/LO#
LP_TRANS#

26
25
45

CLK_IN
CLK_OUT
CLKEN#L

RESERVED
RESERVED
RESERVED

38
37
36

STB#
DIN
DOUT

Y6
1

8P4R_1.5K_0804

+3V

1
R135

VR_HI/LO#
2
10K_0402

+3VS

1
R357

G_VR_POK
2
LN_10K_0402

+3VS

1
R333

GT_CPU_STP#
2
4.7K_0402

+3VS

1
R345

+VCPU_IO

H_PWRGD 4
G_VR_POK 33
VRCHGNG# 20
VR_HI/LO# 7,40
CPU_LO/HI#
R136

CPU_LO/HI# 4

2 2
G
LN_10K_0402
S

Q18
LN_SI2302DS
+3VS

1
2
3
4

+3VS

R499

C423

HCPUINIT#
HNMI
HINTR
HSMI#

LN_8P4R_4.7K_0804

LN_.1UF_0402
2

LN_.01UF_0402

8
7
6
5

L@_1.5K_0402

C466

22

+3V

GT_SUSTAT1#
2
10K_0402
RP22

C481
LN_15PF_0402

C484
LN_15PF_0402

GT_CPUINIT#
2
1K_0402
GT_STPCLK#
2
680_0402
GT_SMI#
2
330_0402
CPU_LO/HI#
2
L@1.5K_0402

GT_STPCLK# 4
GT_SUSTAT1# 9
GT_CPU_STP# 7,11

LN_14.318MHZ

GT_NMI
GT_INTR
GT_IGNNE#
GT_A20M#

8
7
6
5

1
R129
1
R138
1
R322
1
R128

GT_SMI# 4

CRESET#

RP39

GT_SMI#

VCC3
VCC3

R346 1
LN_1K_0402

9 CRESET#

G_STPCLK#
G_SUSSTAT1#
G_CPU_STP#

GT_STPCLK#
GT_SUSTAT1#
GT_CPU_STP#

GT_NMI 4
GT_INTR 4
GT_CPUINIT# 4

7
30

20 GT_LO/HI#
31,34,40 VR_ON
40 VGATE

GT_NMI
GT_INTR
GT_CPUINIT#

HSTPCLK#
SUS_STAT#
CPUSTP#

GND
GND
GND
GND
GND

20 HSTPCLK#
20,29 SUS_STAT#
11,20,33 CPUSTP#

1
4
8
48
2
5

G_NMI
G_INTR
G_INIT#
G_A20M#
G_IGNNE#
G_SMI#

6
18
31
42
27

20 HSMI#

NMI
INTR
INIT#
A20M#
IGNNE#
SMI#

HNMI
HINTR
HCPUINIT#

20 HNMI
20 HINTR
20 HCPUINIT#

H_PWRGD

1
R137
1
R323

HSTPCLK#
2
LN_4.7K_0402
VRCHGNG#
2
10K_0402

1
R349
1
R341
1
R347
1
R328
1
R334

CRESET#
2
LN_1K_0402
GT_LO/HI#
2
10K_0402
SUS_STAT#
2
LN_10K_0402
HA20M#
2
@10K_0402
HIGNNE#
2
@10K_0402

SPWROFF# 19,20,31,33

Q63
L@_FDV301N

PIR(16)

+3V

+5VS
1

+3VS
20 HA20M#
R494
100K_0402

HA20M#

2 R327
1
0_0402

GT_A20M#

HIGNNE#

2 R331
1
0_0402

GT_IGNNE#

20 HIGNNE#
D

CPUSTP#
HINTR
HSMI#
HCPUINIT#

HNMI
2

+3VS
GT_IGNNE# 4
+3VS

RP43

Q60
2N7002

2
G

CRESET#

+3VS

GT_A20M# 4

HNMI

22K
B

SUS_STAT#
E

9
10
11
12
13
14
15
16

22K
Q61
DTC124EK
VGATE

GT_CPU_STP#
GT_INTR
GT_SMI#
GT_CPUINIT#

8
7
6
5
4
3
2
1

GT_NMI
GT_SUSTAT1#

L@16P8R_0
G_VR_POK
1
2
R361
L@0_0402
GT_STPCLK#
1
2
R134
L@0_0402

PIR(6)
3

HSTPCLK#

for without Geyserville

Fiducial Mark
FD4

1
1

HA9
HOLEA

HA8
HOLEA

1
1

HA7
HOLEA

HA4
HOLEA

HA2
HOLEA

HA5
HOLEA

HA3
HOLEA

HA1
HOLEA

1
HA6
HOLEA

FD5

FIDUCIAL MARK

FIDUCIAL MARK

FIDUCIAL MARK

CF8

CF17

CF2
FIDUCIAL MARK

CF16

CF4

CF19
1

FIDUCIAL MARK

CF13

FIDUCIAL MARK

CF7

FIDUCIAL MARK

FIDUCIAL MARK

CF10
1

FIDUCIAL MARK

CF11
1

FIDUCIAL MARK

FD2
1

FIDUCIAL MARK

FIDUCIAL MARK

FIDUCIAL MARK

FIDUCIAL MARK

FD1
1

FIDUCIAL MARK

CF18

HD1
HD2
HOLED HOLED

HC1
HOLEC

1
1

1
1

1
1

1
1

HB3
HOLEB

CF14

FD3
1

FIDUCIAL MARK
CF6
1

FIDUCIAL MARK
HB2
HOLEB

FIDUCIAL MARK
CF5
1

CF15

HB4
HOLEB

FD6

FIDUCIAL MARK
CF12
1

HB1
HOLEB

PIR(28)

CF3

FIDUCIAL MARK

FIDUCIAL MARK

FIDUCIAL MARK

CF1

FIDUCIAL MARK

FIDUCIAL MARK

HE1
HOLEE

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

of

44

CPU Voltege ID
+3VS

5
1

11,20 PCISTP#

5
2

R493

L@8P4R-0
2

DPRSLPVR 40

+3VS

DPRSLPVR

4
1

@0_0402

@7SH32

@1UF_10V

1
CPU_VR_VID4

C116
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3

8
7
6
5

1
2
3
4

2
3
1

2
@1.2K_0402

RP14
CPU_VR_VID0
CPU_VR_VID1
CPU_VR_VID2
CPU_VR_VID3

+3VS
4

1
R79

10,19,20,31,33 PM_SLP_S1#

U11

U10
@7SH00

R501
0_0402

CPU_VID4
1
R78

6,11 GT_CPU_STP#

5
1

2
@56_0402

R263
L@0_0402

U9
4

2
3

20 DPSLP#
C118

@7SH32
2

@.1UF_0402

PIR(28,30)
+3V

R268
4
4
4
4
4

CPU_VR_VID4

1K_0402

15
14
13
12
11

9
10

Level
GND

ADDRESS: ASEL = LOW => 6E/6F

R53

VID0
VID1
VID2
VID3
VID4

2K_1%_0402

LN_FM3560

CPU_VR_VID0
CPU_VR_VID1
CPU_VR_VID2
CPU_VR_VID3
CPU_VR_VID4

+V_AGTLREF
C255
.1UF_0402

C256
.1UF_0402

Y-0
Y-1
Y-2
Y-3
Y-4

R275 LN_0_0402
1
2

C351
.1UF_0402

C350
.1UF_0402

17
16

Non_Mux_Out
Mux_Sel

I-0
I-1
I-2
I-3
I-4

1. Place R48 and R53 between the TwisterT and CPU.

2. Place decoupling caps near CPU.(Within 500mils)

2
LN_0_0402

8P4R_1K_0804
1
2

4
5
6
7
8

CPU_VR_VID0
CPU_VR_VID1
CPU_VR_VID2
CPU_VR_VID3

8
7
6
5

Layout note :

1K_1%_0402

19
18

R48

ASEL
WP

R272
2

20

RP27
1
2
3
4

LN_.1UF_0402
VCC3

SCL
SDA
Override#

R274 LN_10K_0402
1
2
+3V
D

1
2
3

GTL Reference Voltage

+3V

U28

31,32,41 EC_SMD1
12,20 SMB_SB_DA

+VCPU_IO
C374

R271 @0_0402
1
2
1
2
R273
LN_0_0402
1 R270
2
@0_0402 1
2
R269 LN_0_0402

31,32,41 EC_SMC1
12,20 SMB_SB_CK

Q32

2
G

6,40 VR_HI/LO#

S
3

LN_SI2302DS
+1.5VS

CMOS Reference Voltage

PIR(22)
RP79

R230
510_0402

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3

Layout note :
1. Place R230 and R235 between the TwisterT and CPU.
2. Place decoupling caps near CPU.

+VS_CMOSREF
C308
.1UF_0402

C352
.1UF_0402

+3V

R235
1K_0402

R502
LN_0_0402

CPU_VID4

VID4

LN_8P4R_0
1
2

8
7
6
5

1
2
3
4

VID0
VID1
VID2
VID3

1
2
3
4

U12

R72

RP21
@8P4R_10K_0804

STRAP_VID0
STRAP_VID1
STRAP_VID2
STRAP_VID3
STRAP_VID4

8
7
6
5

@10K_0402

Default for Resistors Should

be +VCC_CPU = 0.85V, for
Deeper Sleep Only.
VID[4:0]->10101

2
6
10
16
20

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4

4
8
14
18
22

B0
B1
B2
B3
B4

D0
D1
D2
D3
D4

5
9
15
19
23

+5V

BE#

VCC

24

BX

GND

12

1
1
1
1

DPRSLPVR

R71

13

@SN74CBT3383

@0_0402
2

@0_0402

R76
@0_0402

C0
C1
C2
C3
C4

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4

40
40
40
40
40

C117
@.01UF_0402

R75

A0
A1
A2
A3
A4

1
1

@0_0402

R74
@0_0402

3
7
11
17
21

2
2
2
2

R73

VID0
VID1
VID2
VID3
VID4

PIR(30)
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044

Size

Document Number

Custom

401196

Date:

, 17, 2002

Rev
2A
Sheet
E

of

44

TwisterT(VIA_VT8606)-A

H_REQ#[0..4]
H_RS#[0..2]
H_D#[0..63]
H_A#[3..31]

3 H_REQ#[0..4]
4 H_RS#[0..2]
3 H_D#[0..63]
3 H_A#[3..31]

2.5V +- 5%

+2.5VS

.1UF_0402

C282

C246
47UF_6.3V_B

C280
47UF_6.3V_B

.1UF_0402
2

.1UF_0402

C309

.1UF_0402

C281

C323
.1UF_0402

.1UF_0402

C268

.1UF_0402

C310

PIR(37) 4,20 CPURST#

3 H_ADS#
3 H_BNR#
3 H_BPRI#

A25
D24
B25
B26
E23
C26
C24
A23
C25
D22
B24
D25
F22
C23
D21
A20
C22
A21
B23
A22
B21
E20
B22
B19
C20
A24
B20
D20
C21

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

A19
J24
D26
E26

CPURST#
ADS#
BNR#
BPRI#

H26
F26
J23
G24
G26
G23
G25
J25

DBSY#
DEFER#
DRDY#
HIT#
HITM#
HLOCK#
HTRDY#
BREQ0#

H_RS#0
H_RS#1
H_RS#2

H23
K23
H25

RS0#
RS1#
RS2#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

E24
F23
F24
F25
E25

HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#

HCLK_NB

G22

HCLK

E12
E21

GTLVREF
GTLVREF1

R232
2
0_0402

4 H_DBSY#
3 H_DEFER#
4 H_DRDY#
3 H_HIT#
3 H_HITM#
3 H_LOCK#
4 H_TRDY#
3 H_BREQ0#

+GTL_VREF
3

11 HCLK_NB
+VCPU_IO

R213
2
75_1%_0402

2/3 +VCPU_IO +- 2%
W=40mils

C305
1000PF_0402

1000PF_0402
2

C357

C358

1UF_10V

VIA_VT8606

1
2

@27PF_0402

C312

1UF_10V
2

150_1%_0402

R215

@10_0402

C366

HOST INTERFACE

R242

VT8606
TwisterT

B2 GND
N3 GND
N6 GND
L11 GND
N11 GND
P11 GND
T11 GND
M12 GND
N12 GND
P12 GND
R12 GND
A18 GND
AF18 GND
C19 GND
AD19GND
F21 GND
N21 GND
P21 GND
AA21GND
D23 GND
AC23GND
H24 GND
W24 GND
A26 GND
J26 GND
V26 GND
AF26 GND

.1UF_0402

C330

.01UF_0402

.01UF_0402

C354

.01UF_0402

C324

C266

+2.5VS

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25
VDD25

.1UF_0402

C342

.1UF_0402

C279

.1UF_0402

C327

C292

.1UF_0402

C326

.01UF_0402

.01UF_0402

.01UF_0402

C307

C291

U7A
C295

L9
M9
R9
T9
V10
J11
J12
J15
V15
J16
L18
M18
T18
U18
J9
K9
U9
V9
J10
V11
V12
V16
J17
V17
J18
K18
R18
V18

+2.5VS

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

E19
B18
B16
A16
C18
C17
D18
D15
D17
C16
B17
D16
A17
A15
E16
D19
A14
E18
E17
B14
C15
E14
B11
D14
B15
D13
C13
E9
C12
D12
E15
A13
B12
B13
A12
E13
D11
D10
A11
E10
E8
C9
D9
C11
B10
A10
E7
D8
B8
C10
B6
B9
F8
D6
D7
C7
E5
A7
E6
B7
C6
D5
A6
A8

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

** Place as close to
TwisterT as possible.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

of

44

TwisterT(VIA_VT8606)-B

+3VS +- 5%

C347

.01UF_0402

.1UF_0402

.1UF_0402

1000PF_0402

C355
2

C325

C290

C333

.01UF_0402

.1UF_0402

.1UF_0402

1000PF_0402

C265
2

C328
2

.01UF_0402

1000PF_0402

C306
2

C315

+3VS

SWEC#/CKE0
SCASC#/CKE1
SWEB#/CKE2
SCASB#/CKE3
SRASC#/CKE4
SRASB#/CKE5

V23
W23
AF24
AE23
W26
W25
AD23
AF23

1
1

+
C593

1000PF_0402

.1UF_0402

1
1
1
1

2
2
2
2

22_0402
22_0402
22_0402
22_0402

RAS#0
RAS#1
RAS#2
RAS#3

12
12
13
13

MMA[0..14]

J22

DCLKI

K22

MMA[0..14] 13
RCAS#[0..7] 12,13

PIR(26)
RP30 8P4R_22_0804
4
5
3
6
2
7
1
8
4
5
3
6
2
7
1
8

RRCAS#0
RRCAS#1
RRCAS#2
RRCAS#3
RRCAS#4
RRCAS#5
RRCAS#6
RRCAS#7

RCAS#0
RCAS#1
RCAS#2
RCAS#3
RCAS#4
RCAS#5
RCAS#6
RCAS#7

CKE0_1
CKE1_1
CKE2_1
CKE3_1

R257
R245
R251
R253

1
1
1
1

2
2
2
2

12,13
12,13
12,13
12,13
12,13
12,13
12,13
12,13

+3VS

SRASA# 12,13
SCASA# 12,13
RMWEA# 12,13

33_0402
33_0402
33_0402
33_0402

CKE0
CKE1
CKE2
CKE3

12
12
13
13

MMA4

R65
1

@10K_0402
2

MMA3

R255
1

@10K_0402
2

MMA2

R254
1

@10K_0402
2

MMA6

R66
1

10K_0402
2

MMA8

R67
1

10K_0402
2

MMA12

R64
1

@10K_0402
2

PIR(26)
R241

DCLKO

DCLKO_R
W=5mils

18_0402

2 W=5mils

DCLKO 11
W=5mils

C365
N/C
N/C
N/C

V22
W22
AB22

VSUS25

AA22

DCLKRW 11

R234

@22PF_0402

NC PINs
VSUS25

10_0402

place
closely to
VT8606

C345

AC22
K24
E22 CRESET#
AD14
AE15

H ENSABLE INTA# CLAIM

MA3 L DISABLE I/O ACCESS
H ENABLE I/O ACCESS

GT_SUSTAT1# 6
2 R265
1
4.7K_0402
CRESET# 6
PWROK 33
PCIRST# 14,16,18,19,22,23,29,31,36

MA2 L ADDRESS MAPPING 1

H ADDRESS MAPPING 0
MA12 MA8

+3V

D14

VSUS25

MA4 L DISABLE INTA# CLAIM

15PF_0402

PIR(14,35)
SUSST#
PLLTEST
CRSTD#
PWROK
PCIRST#

C341
47UF_6.3V_B

C592
2

2
R256
R252
R240
R239

RP35 8P4R_22_0804
AA24 S_RASA# R246 1
2 10_0402
S_CASA# R238 1
U22
2 10_0402
RM_WEA# R247 1
U24
2 10_0402
U26
V24
U25
V25
AA26
AA25

E11
F7
F9
F10
F12
F17
F18
F19
F20
G21
J21
K21
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3

DRAM INTERFACE

RRAS0#
RRAS1#
RRAS2#
RRAS3#

C298
47UF_6.3V_B

PIR(17)

VIA_VT8606

SRASA#
SCASA#
SWEA#

Y26
Y25
Y24
Y23
Y22
W21

1
C314
2

.01UF_0402

1000PF_0402

C332
2

C311

+3VS

DQM0/CAS0#
DQM1/CAS1#
DQM2/CAS2#
DQM3/CAS3#
DQM4/CAS4#
DQM5/CAS5#
DQM6/CAS6#
DQM7/CAS7#

MMA0
MMA1
MMA2
MMA3
MMA4
MMA5
MMA6
MMA7
MMA8
MMA9
MMA10
MMA11
MMA12
MMA13
MMA14

11

.1UF_0402

VT8606
TwisterT

+VCPU_IO

C356

.1UF_0402

C349

.01UF_0402

RAS0#/CS0#
RAS1#/CS1#
RAS2#/CS2#
RAS3#/CS3#
RAS4#/CS4#
RAS5#/CS5#

AA23
AB23
AB26
AB25
AB24
AC26
AC25
AC24
AD26
AD25
AE26
AD24
AE24
AE25
AF25

1
C294
2

C329
.01UF_0402

1
C293

1000PF_0402

MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14

.1UF_0402

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63

C348

.1UF_0402

C331

.01UF_0402

M23
K25
L26
L25
M26
M24
N26
N24
P23
P25
R23
R25
P22
T23
T25
T22
AD22
AF22
AB21
AE21
AB20
AD20
AE20
AC19
AF19
AC18
AE18
AD17
AF17
AB17
AE16
AC16
K26
L23
M22
L24
M25
N23
N25
N22
P26
P24
R26
R24
R22
T26
T24
U23
AE22
AC21
AD21
AF21
AC20
AF20
AB19
AE19
AB18
AD18
AA19
AE17
AC17
AD16
AF16
AB16

+VCPU_IO

1
C296
2

C297
.01UF_0402

+3VS

1
C277

** Place as close to
VT8606 as
possible.

+3VS

1000PF_0402

U7B
MMD0
MMD1
MMD2
MMD3
MMD4
MMD5
MMD6
MMD7
MMD8
MMD9
MMD10
MMD11
MMD12
MMD13
MMD14
MMD15
MMD16
MMD17
MMD18
MMD19
MMD20
MMD21
MMD22
MMD23
MMD24
MMD25
MMD26
MMD27
MMD28
MMD29
MMD30
MMD31
MMD32
MMD33
MMD34
MMD35
MMD36
MMD37
MMD38
MMD39
MMD40
MMD41
MMD42
MMD43
MMD44
MMD45
MMD46
MMD47
MMD48
MMD49
MMD50
MMD51
MMD52
MMD53
MMD54
MMD55
MMD56
MMD57
MMD58
MMD59
MMD60
MMD61
MMD62
MMD63

+VCPU_IO

P1 GND
AF1 GND
D4 GND
AC4 GND
F6 GND
P6 GND
AA6 GND
C8 GND
AD8 GND
A9 GND
N9 GND
P9 GND
AF9 GND
M11 GND
R11 GND
L12 GND
T12 GND
F13 GND
J13 GND
V13 GND
L13 GND
M13 GND
N13 GND
P13 GND
R13 GND
T13 GND
AA13GND
AD13GND
C14 GND
J14 GND
V14 GND
L15 GND
T15 GND
M16 GND
R16 GND
N18 GND
P18 GND
M21 GND
T21 GND

MMD[0..63]

13 MMD[0..63]

+3VS

+VCPU_IO
G6
H6
J6
L4
R21
T4
U21
V6
V21
W6
Y6
Y21
AA7
AA9
AA10
AA17
AA18
AA20

+3VS

00
01
11
10

R237
1N4148

=
=
=
=

CPU FSB FREQ.

66
MHZ
AUTO
133 MHZ
100 MHZ

MA6 GTL INTRNAL PULLUPS

0 ENABLE
1 DISABLE

R248

@.1UF_0402

@500
4

C353

@100_0402

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

of

44

19 PREQ#
19 PGNT#
16,18,19,29,36 FRAME#
19 PLOCK#
16,18,19,29,36 PAR
16,19,29,36 SERR#
16,18,19,29,36 TRDY#
16,18,19,29,36 IRDY#
16,18,19,29,36 STOP#
16,18,19,29,36 DEVSEL#
11 PCLK_NB
16,19,31,36 CLKRUN#

PCLK_NB

R221
3

10_0402
2
1
2

C313
15PF_0402

PCLK_NB

AD1
AE1
AA4
AB4
AC3
AD3
AC2
AD2
AB1
AC1
Y5
AA5
W4
Y4
AA3
AB3

LVDS2_C+
LVDS2_CLVDS2_2+
LVDS2_2LVDS2_1+
LVDS2_1LVDS2_0+
LVDS2_0LVDS1_C+
LVDS1_CLVDS1_2+
LVDS1_2LVDS1_1+
LVDS1_1LVDS1_0+
LVDS1_0-

+VCCA
+3VS

H22
H21

ZCP
ZCM
Z2P
Z2M
Z1P
Z1M
Z0P
Z0M
YCP
YCM
Y2P
Y2M
Y1P
Y1M
Y0P
Y0M

VCCA
VCCA

@33K_0402

+DACVDD

+3VS

L40
+2.5VS

OSCGUI 11

HB-1M2012-601JT
C245

PIRQA# 16,19

SUSPEND
STANDBY

C244

+ C240

1000PF_0402 1UF_10V

10UF_10V_1206

DDCCLK 14
DDCDATA 14

PANELDET
ENVEE
ENVDD
PANELCLK
PANELDEN
PANELVS
PANELHS
PD0/TVD11
PD1/TVD10
PD2
PD3
PD4
PD5
PD6
PD7
PD8/TVD9
PD9/TVD8
PD10
PD11
PD12
PD13
PD14
PD15
PD16/TVCLKR
PD17/TVBLANK
PD18
PD19
PD20
PD21
PD22
PD23
PD24/TVD6
PD25/TVD4
PD26/TVD5
PD27/TVD7
PD28/TVD0
PD29/TVD1
PD30/TVD3
PD31/TVVS
PD32/TVCLK
PD33/TVD2
PD34/TVHS
PD35

R6
T2
T1
R5
R2
R4
R1
R3
P5
P2
P3
P4
N5
N2
N1
N4
T3
U1
U3
AA16
H5
F1
G4
H3
G3
G5
G2
H2
H1
J2
J1
H4
K6
J4
J3
L5
K2
J5
K1
K3
L6
L2
K5
L1
L3
M6
K4
M4
M5
M1
T6
T5
U4
U2
V1
V2
V3
W3
V4
U5
V5
C5

R33
10_0402
PLLVDD2
R197

L37
+2.5VS

C79

LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15
HREF
VS
LCLK

FBM_L11-201209-601LMT
10K_0402

C267

15PF_0402

C263

+ C262
2

1000PF_0402 1UF_10V

10UF_10V_1206

R224 33K_0402
PANELDET

PLLVDD1
ENVEE 15,31
ENVDD 15

L38
+2.5VS
FBM_L11-201209-601LMT
C260

TVD11
TVD10

C261

+ C249

1000PF_0402 1UF_10V

10UF_10V_1206

TVD[0..11]

TVD[0..11] 14

TVD9
TVD8

HB-1M2012-601JT
3

+2.5VS
R195

22_0402

L41

TVCLKR 14
LAVDD

C264
15PF_0402

+ C251
C254

C253

.1UF_0402

.1UF_0402

C252

10UF_10V_1206

TVD6
TVD4
TVD5
TVD7
TVD0
TVD1
TVD3

.1UF_0402

LVDD

TVVS 14
TVCLK 14

TVD2

L39
+3VS

TVHS 14

HB-1M2012-601JT
R198
10_0402

C257
.1UF_0402

C276

U23
15PF_0402
2

AA11 WSC#
BISTIN
F15
DFTIN
F11

AB2

Y2

A5

B3

B4
C4

.1UF_0402

12

VIA_VT8606

IRSET

2
10K_0402
2
1K_0402
2
1K_0402 PIR(3)
2
147_1%
2
@0_0402
2
@0_0402

FRAME#
PLOCK#
PAR
SERR#
TRDY#
IRDY#
STOP#
DEVSEL#
PCLK
CLKRUN#

DFTIN

RED 14,35
GREEN 14,35
BLUE 14,35
HSYNC 14
VSYNC 14
SPDAT1 14
SPCLK1 14
+2.5VS

GOP0

BISTIN

AE9
AE5
AB10
AF10
AD10
AC10
AE10
AB9
AB15
AF15

2.5V +- 0.25V

PREQ#
PGNT#

3.3V +- 0.3V

VDDD

AC15
AD15

AGP_BUSY
STP_AGP

PREQ#
PGNT#

WSC
BISTIN
DFTIN

GNT0#
GNT1#
GNT2#
GNT3#
GNTX#

VDDD

AB5
AF4
AF3
AE3
AE2

PLLVCCA

GNT#0
GNT#1
GNT#2
GNT#3
GNT#4

VCCPLL2

REQ0#
REQ1#
REQ2#
REQ3#
REQX#

LVDS

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

AC5
AD5
AE4
AD4
AF2

3.3V +- 0.3V -> 2.5V +- 0.25V

VCCLVDS

1
R216
1
R222
1
R217
1
R182
1
R223
1
R219

GNT#0
GNT#1
GNT#2
GNT#3
GNT#4

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4

VCCLPLL

IRSET
R190

+3VS
WSC#

36
36
29
16
18,21

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4

CBE0#
CBE1#
CBE2#
CBE3#

2.5V +- 0.25V

36
36
29
16
18,21

AF12
AB11
AD9
AD7

C359

2.5V +- 0.25V

VCCPLL2

TwisterT(VIA_VT8606)-C

10P8R_10K

CBE#0
CBE#1
CBE#2
CBE#3

C3
G1
AA12
A2
A3
W5
F5
F4
U6
M2
M3

VCCPLL1

+3VS

REQ#0
REQ#1
REQ#2
REQ#3

C2
D3
D2
E2
E1
F2
F3
E4
E3

2.5V +- 0.25V

+3VS

10
9
8
7
6

RED
GREEN
BLUE
HSYNC
VSYNC
SPD1
SPCLK1
COMP
RSET

2.5V +- 0.25V

VCCDAC

1
2
3
4
5

+3VS

VCCA

PGNT#
PREQ#
REQ#4

PCI INTERFACE

RP6

2
4.7K_0402
2
4.7K_0402

2.5V +- 0.25V

@10P8R_10K

VT8606
TwisterT
DISPLAY INTERFACE

+3VS

GNT#0
GNT#1
GNT#2
GNT#3

Y3 PLLGND
AA1 LVDS1GND
Y1 LVDSGND

+3VS

10
9
8
7
6

AA2 VSSD

1
2
3
4
5

GNDRGB
GNDDAC

GNT#4

GNDPLL2

RP7

1
R193
1
R189

GOP0
FPGPIO
STRW/GPOUT
XTLI
XTLO
INTA
SUSPEND
STANDBY
N/C
SPCLK2
SPD2

A1
B1

10UF_10V_1206

GNDPLL1

+ C360

1UF_10V

B5

C364

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

A4

C362
1000PF_0402

AF14
AE14
AE13
AF13
AC14
AB14
AC13
AB13
AE12
AD12
AB12
AC12
AF11
AE11
AD11
AC11
AA8
AC9
AF8
AE8
AE7
AB8
AF7
AC8
AC7
AB7
AF6
AE6
AD6
AC6
AB6
AF5

LAVDD

LVDD
LAVDD

F14 GND
L14 GND
M14 GND
N14 GND
P14 GND
R14 GND
T14 GND
AA14GND
M15 GND
N15 GND
P15 GND
R15 GND
AA15GND
F16 GND
L16 GND
N16 GND
P16 GND
T16 GND

+2.5VS

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

L22 GNDA
L21 GNDA

L43
HB-1M2012-601JT

VCCDAC
VCCRGB

VCCPLL1

C1
D1

U7C
+VCCA

PLLVDD2

PLLVDD1

W1
W2

+DACVDD
CBE#[0..3]
AD[0..31]

16,18,19,29,36 CBE#[0..3]
16,18,19,29,36 AD[0..31]

VCCRGB

LVDSVCCA
LVDS1VCCA

7,19,20,31,33 PM_SLP_S1#

SUSPEND
4

NC7S04
3

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

10

of

44

Clock Generator

+VCLK_CPU
L23
1
2
HB-1M2012-121JT

Width=40 mils
1

+2.5V_CLK

C135

C131
4.7UF_10V_0805

+3VS_CPUCLK

Width=40 mils

C140
.1UF_0402

C167
1000PF_0402

C160

1000PF_0402
.01UF_0402
2

C161

C162

1000PF_0402
.01UF_0402

C139

U13
46
45
5
9
29
35
28

VDDCPU_2.5
VDDCPU_3.3
VDDREF
VDDPCI
VDDSDRAM
VDDSDRAM
AVDD48

2 10K_0402 PWR_DWN# 21
GT_CPU_STP# 19
20

*PD#
*CPU_STOP#
*PCI_STOP#

+3VS_SDR

C138

C142

1000PF_0402
.01UF_0402
2

C141
1000PF_0402
R1071

+3VSCLK
6,7 GT_CPU_STP#
7,20 PCISTP#

12
12
4
19

SDACLK
SCKCLK
BSEL1
USBCLK

R101 1
1
R92

2 100_0402
2
22_0402

FS1
FS0

4,31,42 VTT_PWRGD#
R86 1

2 220_1%_0402

+3VSCLK

1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2

33_0402
33_0402
33_0402
22_0402
22_0402
22_0402
22_0402
22_0402
22_0402
22_0402
22_0402

R99
R100
R89
R90

1
1
1
1

2
2
2
2

22_0402
@22_0402
0_0402
0_0402

14.318M_TV 14
OSCGUI 10
OSCSB 21
CLK_CPU_APIC 4
PCLK_SB 19
PCLK_LAN 29
PCLK_LPC 31
PCLK_NB 10
PCLK_PCM 16
PCLK_MINI 36
PCLK_1394 18

*FS4/PCICLK_F
*FS3/PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5

10
11
13
14
15
16
17

CPUCLK1
CPUCLK0
CPUCLKT
CPUCLKC

47
48
44
43

SDRAM_IN

18

SDRAM0
SDRAM1

37
36

SDRAM2
SDRAM3

34
33

R97
R98

1
1

2 10_0402
2 10_0402

CLK_SDRAM0 12
CLK_SDRAM1 12

SDRAM4
SDRAM5

31
30

R94
R95

1
1

2 10_0402
2 10_0402

CLK_SDRAM2 13
CLK_SDRAM3 13

SDRAM6

39

R96

2 22_0402

DCLKRW 9

24
25
26
27

SDATA
SCLK
24_48MHz/FS1*
48MHz/FS0*

4
22
40
41

Vtt_PWRGD#
MULTSEL
IREF
RESET#

1
6
12
23
32
38
42

GND
GND
GND
GND
GND
GND
GND

10K_0402

X1

X2

CY28317-2

HOST_CPU
HOST_CPU#

CLK_BCLK
CLK_BCLK
CLK_BCLK#

HCLK_NB 8
CLK_BCLK 4
CLK_BCLK# 4
DCLKO 9

R121

PIR(20)
Y1

2
GT_CPU_STP#

1
1

2
@0_0402

1
R109

FS4
FS3

R105
R106
R110
R87
R116
R127
R117
R118
R119
R120
R123

R112

R108
@10K_0402

6,20,33 CPUSTP#

FS2

.01UF_0402
2

C132

C130
4.7UF_10V_0805

Width=40 mils

3
2

C137

@10_0402

14.318MHZ
C163

C164

12

L22
1
2
HB-1M2012-121JT

+3VS

REF0
*FS2/REF1

.01UF_0402
2

C159

C158
4.7UF_10V_0805

Width=40 mils
1

+3VS

L21
1
2
HB-1M2012-121JT

+3VS

1000PF_0402

+3VSCLK
L25
1
2
HB-1M2012-121JT

C136

.01UF_0402

C166
@15PF_0402
2

15PF_0402

15PF_0402

@33PF_0402

C134
15PF_0402

PIR(14)

1
R122

R93

R91

10K_0402

10K_0402

10K_0402

10K_0402

+3VSCLK

R124

10K_0402

+3VSCLK

+3VSCLK

R88

+3VSCLK

+3VSCLK

FS4 FS3 FS2 FS1 FS0

FS0
FS1

CPUCLK/PCICLK

133.30/33.30 (0 ~ -0.5% down spread)

133.60/33.40 (+/-0.25% center spread)

FS2
FS3

FS4

R125

R111

133.90/33.47 (+/-0.25% center spread)

100.00/33.30 (0 ~ -0.5% down spread)

@10K_0402
2

@10K_0402

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Date:
G

Sheet

11
H

of

44

SO-DIMM0 (Bank 0,1)

C143

.01UF_0402

.01UF_0402

C421
10UF_10V_1206
9,13 RCAS#[0..7]

MA[0..14]

13 MA[0..14]
13 MD[0..63]

+3V

RCAS#[0..7]

1/20 ADD MMA14 LINK

MD[0..63]

.01UF_0402
JP28

.01UF_0402

RCAS#0
RCAS#1

C149
1UF_25V_0805

MA0
MA1
MA2

MD8
MD9
MD10
MD11
INHIB

1
R365

2
10K_0402

SM BUS
+3V

MD12
MD13
MD14
MD15

PIR(14)
C427
2
1

+3V

+3V

2
1
R325 @10_0402

@15PF_0402
+3V

C444

8
7
6
5

RP42
8P4R_10K_0804

9,13 SRASA#
9,13 RMWEA#
9 RAS#0
9 RAS#1

RP44
8P4R_10K_0804

.1UF_0402
1
2
3
4

R336
10K_0402

21 ENDIM0
21 ENDIM1

7,20 SMB_SB_CK
3

U36

16
6
10
9

13

7,20 SMB_SB_DA

INH
A
B

X0
X1
X2
X3

1
5
2
4

SCKDIMM0

Y0
Y1
Y2
Y3

12
14
15
11

SDADIMM0

X
Y

GND
GND

INHIB
ENDIM0
ENDIM1

VCC

R367
10K_0402
CHANGE FROM
4.7K_0402 07/05

RMWEA#
RAS#0
RAS#1

1
2
3
4

8
7
6
5

11 CLK_SDRAM0

MD16
MD17
MD18
MD19

SCKDIMM1 13
SCKCLK 11

MD20
MD21
MD22
MD23

SDADIMM1 13
SDACLK 11

MA6
MA8

7
8

74HC4052

MA9
MA10
RCAS#2
RCAS#3

INHIB

ENDIM1

ENDIM0

SO-DIMM0

SO-DIMM1

Clock Generator

Channel

MD24
MD25
MD26
MD27

ON

MD28
MD29
MD30
MD31
SDADIMM0

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

RFU/CLK0
VCC
RFU
WE#
RE0#
RE1#
OE#/RESVD
VSS
RESVD/DQ66
RESVD/DQ67
VCC
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
A6
A8
VSS
A9
A10
VCC
CE2#/RESVD
CE3#/RESVD
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VCC

RFU/CKE0
VCC
RFU
RFU/CKE1
RFU
RFU
RFU/CLK1
VSS
RESVD/DQ70
RESVD/DQ71
VCC
DQ48
DQ49
DQ50
DQ51
VSS
DQ52
DQ53
DQ54
DQ55
VCC
A7
A11/BA0
VSS
A12/BA1
A13/A11
VCC
CE6#/RESVD
CE7#/RESVD
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VCC

62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
RCAS#4
RCAS#5
MA3
MA4
MA5
2

MD40
MD41
MD42
MD43

+3V

MD44
MD45
MD46
MD47

+3V

C156

VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
VSS
CE4#
CE5#
VCC
A3
A4
A5
VSS
DQ40
DQ41
DQ42
DQ43
VCC
DQ44
DQ45
DQ46
DQ47
VSS
RESVD/DQ68
RESVD/DQ69

R103
@10K_0402

R102
@10K_0402
2

.01UF_0402

C165

4.7UF_25V_1206

C422

1000PF_0402

C147

1000PF_0402

C151

VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
CE0#
CE1#
VCC
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
VSS
RESVD/DQ64
RESVD/DQ65

MD4
MD5
MD6
MD7

+3V

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

MD0
MD1
MD2
MD3

CKE0 9
SCASA# 9,13
CKE1 9

MA14
CLK_SDRAM1 11
1

.01UF_0402

+3V

C418

R104
@10_0402

MD48
MD49
MD50
MD51

12

.01UF_0402

C157

1UF_25V_0805

C152

C155

1000PF_0402

1000PF_0402

C154

C153

+3V

MD52
MD53
MD54
MD55

C150
@15PF_0402
3

C146

.1UF_0402

C145

.1UF_0402

C144

1UF_25V_0805

C420

1000PF_0402

C148

+3V

PIR(14)
MA7
MA11
MA12
MA13
RCAS#6
RCAS#7
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
SCKDIMM0

SO-DIMM144

NONE

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Date:
G

Sheet

12
H

of

44

SO-DIMM1 (Bank 2,3)

RCAS#[0..7]

9,12 RCAS#[0..7]

MA[0..14]

12 MA[0..14]

+3V
MD[0..63]

C125

C124

C123

C128

C122

12 MD[0..63]
C126

C107
+3V

+3V

10UF_10V_1206
2

.01UF_0402
2

.01UF_0402

.1UF_0402

.1UF_0402

1UF_25V_0805

1000PF_0402

JP17

.01UF_0402

C111
.01UF_0402

PIR(14)
C105
2
1

R68
2

@15PF_0402

9 MMA[0..14]
9 MMD[0..63]

1
2
3
4

MMD4
MMD5
MMD6
MMD7

RP33
4
3
2
1

9,12
9,12
9
9

MMD[0..63]

8P4R_22_0804
MD4
5
MD5
6
MD6
7
MD7
8

1
@10_0402

11 CLK_SDRAM2

MMA[0..14]

RP20 8P4R_22_0804
MD0
8
MD1
7
MD2
6
MD3
5

MMD0
MMD1
MMD2
MMD3

MMD32
MMD33
MMD34
MMD35

RP34
4
3
2
1

8P4R_22_0804
MD32
5
MD33
6
MD34
7
MD35
8

MMD36
MMD37
MMD38
MMD39

RP19
1
2
3
4

8P4R_22_0804
MD36
8
MD37
7
MD38
6
MD39
5

SRASA#
RMWEA#
RAS#2
RAS#3

RMWEA#
RAS#2
RAS#3

MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23

MD12
MD13
MD14
MD15

MA6
MA8
MMD8
MMD9
MMD10
MMD11

RP32
4
3
2
1

8P4R_22_0804
MD8
5
MD9
6
MD10
7
MD11
8

MMD40
MMD41
MMD42
MMD43

RP18
1
2
3
4

8P4R_22_0804
MD40
8
MD41
7
MD42
6
MD43
5

MMD12
MMD13
MMD14
MMD15

RP36
4
3
2
1

8P4R_22_0804
MD12
5
MD13
6
MD14
7
MD15
8

MMD44
MMD45
MMD46
MMD47

RP17
1
2
3
4

8P4R_22_0804
MD44
8
MD45
7
MD46
6
MD47
5

MMD16
MMD17
MMD18
MMD19

RP26
4
3
2
1

8P4R_22_0804
MD16
5
MD17
6
MD18
7
MD19
8

MMD48
MMD49
MMD50
MMD51

RP13
4
3
2
1

8P4R_22_0804
MD48
5
MD49
6
MD50
7
MD51
8

MMD20
MMD21
MMD22
MMD23

RP12
4
3
2
1

8P4R_22_0804
MD20
5
MD21
6
MD22
7
MD23
8

MMD52
MMD53
MMD54
MMD55

RP11
4
3
2
1

8P4R_22_0804
MD52
5
MD53
6
MD54
7
MD55
8

MMD24
MMD25
MMD26
MMD27

RP10
4
3
2
1

8P4R_22_0804
MD24
5
MD25
6
MD26
7
MD27
8

MMD56
MMD57
MMD58
MMD59

RP9
4
3
2
1

8P4R_22_0804
MD56
5
MD57
6
MD58
7
MD59
8

MMD28
MMD29
MMD30
MMD31

RP24
4
3
2
1

8P4R_22_0804
MD28
5
MD29
6
MD30
7
MD31
8

MMD60
MMD61
MMD62
MMD63

RP25
4
3
2
1

8P4R_22_0804
MD60
5
MD61
6
MD62
7
MD63
8

PIR(26)

MA9
MA10
RCAS#2
RCAS#3
MMA0
MMA1
MMA2
MMA3

RP31
4
3
2
1

8P4R_10_0804
MA0
5
MA1
6
MA2
7
MA3
8

MMA4
MMA5
MMA6
MMA7

RP16
4
3
2
1

8P4R_10_0804
MA4
5
MA5
6
MA6
7
MA7
8

MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
12 SDADIMM1

61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

RFU/CLK0
VCC
RFU
WE#
RE0#
RE1#
OE#/RESVD
VSS
RESVD/DQ66
RESVD/DQ67
VCC
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
A6
A8
VSS
A9
A10
VCC
CE2#/RESVD
CE3#/RESVD
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VCC

RFU/CKE0
VCC
RFU
RFU/CKE1
RFU
RFU
RFU/CLK1
VSS
RESVD/DQ70
RESVD/DQ71
VCC
DQ48
DQ49
DQ50
DQ51
VSS
DQ52
DQ53
DQ54
DQ55
VCC
A7
A11/BA0
VSS
A12/BA1
A13/A11
VCC
CE6#/RESVD
CE7#/RESVD
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VCC

62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

RCAS#4
RCAS#5
MA3
MA4
MA5
MD40
MD41
MD42
MD43

+3V
2

R82
@10K_0402

R81
@10K_0402

CKE2 9
SCASA# 9,12
CKE3 9

MA14
CLK_SDRAM3 11

MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55

R80
@10_0402

C129
@15PF_0402

PIR(14)
3

MA7
MA11
MA12
MA13
RCAS#6
RCAS#7
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
SCKDIMM1 12

SO-DIMM144_H5.6
MMA8
MMA9
MMA10
MMA11

RP29
4
3
2
1

8P4R_10_0804
MA8
5
MA9
6
MA10
7
MA11
8

MMA12
MMA13
MMA14

RP15
4
3
2
1

8P4R_10_0804
MA12
5
MA13
6
MA14
7
8

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:

+3V

MD44
MD45
MD46
MD47

.01UF_0402

C110

1UF_25V_0805

C115

C109

1000PF_0402

1000PF_0402

C112

C113

MD36
MD37
MD38
MD39

MD8
MD9
MD10
MD11

+3V

MD32
MD33
MD34
MD35

MA0
MA1
MA2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

RCAS#0
RCAS#1

1UF_25V_0805

VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
VSS
CE4#
CE5#
VCC
A3
A4
A5
VSS
DQ40
DQ41
DQ42
DQ43
VCC
DQ44
DQ45
DQ46
DQ47
VSS
RESVD/DQ68
RESVD/DQ69

.01UF_0402

MD4
MD5
MD6
MD7

C127

VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
CE0#
CE1#
VCC
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
VSS
RESVD/DQ64
RESVD/DQ65

12

.01UF_0402

C114

C121

4.7UF_25V_1206

C106

1000PF_0402

1000PF_0402

C120

C119

+3V

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

MD0
MD1
MD2
MD3

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

13

of

44

CRT Conn./TV Encoder

+5VS
F1

D2
DAN217

D3
DAN217
1

D4

CRTVDD

W=40mils

CRTVDD
1

RB411D
C39

D1
DAN217

CRT Connector

POLYSWITCH_0.5A

R24
2.2K_0402

R11
2.2K_0402

L1
1
2
FCM2012C-800_0805
L2
1
2
FCM2012C-800_0805
L3
1
2
FCM2012C-800_0805

10,35 RED
10,35 GREEN

C6

C3

18PF_0402

18PF_0402

18PF_0402

DDC_MD2

@22PF_0402

C4

@22PF_0402

C12

C10

@22PF_0402

C13

R9
75_1%

R6
75_1%

R8
75_1%

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

31,35 MSEN#

10,35 BLUE

JP3
CRT-15P

.1UF_0402

L4
1

DDCDATA 10

Q1
2N7002

DDCCLK 10
2

C9

220PF_0402
2

220PF_0402
2

C5

C7

68PF_0402

100PF_0402
1
R10

+12VS

CRTVDD

C40

68PF_0402

3
2

C8

R22
@10K_0402

R3
@10K_0402

1
2
FBM-11-160808-121
1

Q6
2N7002

L16

10 VSYNC
2

Q5
2N7002

1
2
FBM-11-160808-121

Q3
2N7002

10 HSYNC

1
R25

2
100K_0402
DOCK_VSYNC 35

2
100K_0402

+12VS

DOCK_DDCD 35

+5VS

DOCK_DDCC 35
DOCK_HSYNC 35

C241

L36
1
2
TV@FBM_L10-201209-201LMT

TV-Out Connector
C238

2
TV@47PF_0402
L6
1
2
TV@FBM-11-160808-121
1
2
C29
TV@47PF_0402
L5
1
2
TV@FBM-11-160808-121
C30

L18

TV@.1UF_0402

L19
1
2
TV@FBM_L10-201209-201LMT

2
1

TV@10UF_10V_1206

C223

C75

LUMA

+3VS

TV@10UF_10V_1206
CRMA

C81

S-Video
JP5
1
2
3
4
5
6
7

TV@.1UF_0402
2

TV@10UF_10V_1206

TV@FBM_L10-201209-201LMT

TV@.1UF_0402

C222

COMPS
3

29

RESETB

RSET

24

TVD8
TVD9
TVD10
TVD11

C26
TV@270PF_0402

C27
TV@270PF_0402

TVCLK 10

C84
TV@15PF_0402
Y3
14M_TV2

2 14M_TV1

TV@14.318MHZ
C248
TV@10PF_0402

1
R185

2
@0_0402

14.318M_TV 11

C247
TV@10PF_0402

1
DGND
DGND
DGND
DGND

TV@CH7005

C86
TV@15PF_0402

Notes :

If Rx mount, remove Yx/Cx, and

Cx change to 0_0603 resister.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

TV@150PF_0402

R179
TV@360

8
18
36
28

AGND
GND
GND

34
23
19

TV@10_0402
TVD[0..11]

C227

7
9
10
11
12
13
14
15

TV@150PF_0402

D8
D9
D10
D11
D12
D13
D14
D15

R49

10 TVD[0..11]

1
33
32

C34

9,16,18,19,22,23,29,31,36 PCIRST#

CH7005

XO/FIN
XI

TP1
1
1
2
R43
TV@0_0402
14M_TV1
14M_TV2

TV@150PF_0402

D7
D6
D5
D4
D3
D2
D1
D0

17
35
37

C33

6
4
3
2
1
44
43
42

TVD7
TVD6
TVD5
TVD4
TVD3
TVD2
TVD1
TVD0

CSYNC
BCO
P-OUT

TV@75_1%

H
V

R178

TV@75_1%
2

40
41

R175

TV@75_1%
2

10 TVHS
10 TVVS

COMPS 35
LUMA 35
CRMA 35

XCLK

COMPS
LUMA
CRMA

39

20
22
21

10 TVCLKR

R173
CVBS/B
Y/R
C/G

SD
SC

26
27

10 SPDAT1
10 SPCLK1

DVDD
DVDD
DVDD
DVDD

PIR(8)

U22

2 4.7K_0402
2 4.7K_0402

31
25

1
1

AVDD
VDD

R35
R37

30
5
16
38

TV@S CONN._FOXCONN
+3VS

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

14

of

44

W/LVDS LCD CONN.

PID[0..3]

PID[0..3] 20,21

+3VS
L35
INV_B+
8P4R_10K_0804
PID0
8
PID1
7
PID2
6
PID3
5

INV_B+

B+

+5VALW

C224

C225
.1UF_0402

1000PF_0402

JOPEN4
2

FBM-L11-201209-221

C228
4.7UF_25V_1206

L34

@FBM-L11-201209-221

RP5
1
2
3
4

JOPEN2
2

+5VS

JP12

10 LVDS1_C+
10 LVDS1_C10 LVDS2_1+
10 LVDS2_110 LVDS2_0+
10 LVDS2_010 LVDS2_C+
10 LVDS2_C-

LVDS1_0+
LVDS1_0LVDS1_C+
LVDS1_CLVDS2_1+
LVDS2_1LVDS2_0+
LVDS2_0LVDS2_C+
LVDS2_C-

LCDVDD_1

+3VS
1

CHANGE INVERTER POWER SOURCE TO +5VS

R172
1K_0402

INV_B+
LCDVDD_1
D9
10,31 ENVEE

LCDVDD
INVT_PWM 31

PID0
PID1
PID2
PID3

C57
1000PF_0402

ENVEE

RB751V
D10
2

C58
10 ENVDD

ENVDD

DISPOFF#

FBM-L11-201209-221
.01UF_0402

L33

DAC_BRIG 31

DISPOFF#

10 LVDS1_0+
10 LVDS1_0-

LVDS2_2+
LVDS2_2-

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

RB751V

LVDS1_1+
LVDS1_1-

The cap.'s colsely to LCD CONN.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

10 LVDS1_1+
10 LVDS1_110 LVDS2_2+
10 LVDS2_2-

LVDS1_2+
LVDS1_2-

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

10 LVDS1_2+
10 LVDS1_2-

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

D11
31

ENBKL

2
RB751V

LVDS 50 PIN CONN.

+12VS
Q10
LCDVDD
SI2302DS
3
1

R29
100K_0402

+3VS

LCDVDD
1

+12VS
R27

C55
+ C56
C52
.047UF_0402 .1UF_0402
4.7UF_10V_0805

R28

1K_0402

R26
100K_0402

150K_0402
Q8

1
2
3

2
3

Q9
2N7002
1

2N7002

ENVDD

22K

Q7
DTC124EK

22K

SI2301DS: P CHANNEL
VGS: -4.5V, RDS: 130 mOHM
VGS: -2.5V, RDS: 190mOHM
Id(MAX): 2.3A
VGS(MAX): +-8V

SI2302DS: N CHANNEL
VGS: 4.5V, RDS: 85 mOHM
VGS: 2.5V, RDS: 115mOHM
Id(MAX): 2.8A
VGS(MAX): +-8V

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

15

of

44

PCMCIA Controller
S1_VCC

C85

C229

C205

C204

C258

.1UF_0402

C243
.1UF_0402

.1UF_0402
2

.1UF_0402
2

.1UF_0402
2

.1UF_0402

.1UF_0402

.1UF_0402
.1UF_0402

C203

C239
2

3V_CB
C259

C237
S1_A23
2
22K_0402
S1_WP
2
@22K_0402

C202
1
R38
1
R41

.1UF_0402
3V_CB

4.7UF_10V_0805
2

1
R47
1
R192

S1_VCC
2
@0_1206
2
0_1206

+3VS
+3V

Stuff R38 for OZ6912.

Stuff R41 for TI/ENE CB1410.

+3V
VPPD0
VPPD1
VCCD0#
VCCD1#

12

R174
10_0402

C226

22PF_0402

PCM_RI#
2
22K_0402

1
R20

+3V

1
R21

+3V

10,18,19,29,36
10,18,19,29,36
10,18,19,29,36
10,18,19,29,36

9,14,18,19,22,23,29,31,36 PCIRST#
10,18,19,29,36 FRAME#
10,18,19,29,36 IRDY#
10,18,19,29,36 TRDY#
10,18,19,29,36 DEVSEL#
10,18,19,29,36 STOP#
18,19,29,36 PERR#
10,19,29,36 SERR#
10,18,19,29,36 PAR
10 REQ#3
2
10 GNT#3
10K_0402
11 PCLK_PCM
D8

31 PCM_SUSP#
1
R19

PCLK_PCM

PCM_PMER#

1
R164

2
AD15

RB751V
+3VALW

CBE#3
CBE#2
CBE#1
CBE#0

2
10K_0402

1
R31

2
0_0402
2
100_0402

10,19 PIRQA#
21,31 SERIRQ
19 PCM_RI#

PCM_RI#

10,19,31,36 CLKRUN#
1
R165

2
0_0402
1

17,31 G_RST#

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

12
27
37
48

C/BE3#
C/BE2#
C/BE1#
C/BE0#

20
28
29
31
32
33
34
35
36
1
2
21

PCIRST#
PCIFRAME#
PCIIRDY#
PCITRDY#
PCIDEVSEL#
PCISTOP#
PCIPERR#
PCISERR#
PCIPAR
PCIREQ#
PCIGNT#
PCIPCLK

59
70

RI_OUT#/PME#
SUSPEND#

13

63
VCCI

138
122
102
86
50
30
14
VCC
VCC
VCC
VCC
VCCP
VCCP
VCC

126
90
VCCCB
VCCCB

44
18
VCCP
VCCP

2
.1UF_0402

U21

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17

CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD15/IOWR#
CAD14/A9
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3

144
142
141
140
139
129
128
127
124
121
120
118
116
115
113
98
96
97
93
95
92
91
89
87
85
82
83
80
81
77
79
76

CCBE3#/REG#
CCBE2#/A12
CCBE1#/A8
CCBE0#/CE1#

125
112
99
88

CRST#/RESET
CFRAME#/A23
CIRDY#/A15
CTRDY#/A22
CDEVSEL#/A21
CSTOP#/A20
CPERR#/A14
CSERR#/WAIT#
CPAR/A13
CREQ#/INPACK#
CGNT#/WE#
CCCLK/A16

119
111
110
109
107
105
104
133
101
123
106
108

CSTSCHNG/BVD1
CCLKRUN#/WP

135
136

S1_WP

IDSEL

CBLOCK#/A19

103

S1_A19

60
61
64
65
67
68
69

MF0
MF1
MF2
MF3
MF4
MF5
MF6

CINT#/READY

132

S1_RDY# 17

SPKROUT
CAUDIO#/BVD2

62
134

PCM_SPK# 24
S1_BVD2 17

66

G_RST#

CCD2#/CD2#
CCD1#/CD1#
CVS2/VS2#
CVS1/VS1#

137
75
117
131

S1_CD2# 17
S1_CD1# 17
S1_VS2 17
S1_VS1 17

C207
CB1410

PQFP 144
22.2 X
22.2 X
1.60

84 RSVD/D14
100 RSVD/A18
143 RSVD/D2

VPPD1
VPPD0

VCCD1#
VCCD0#
1

PCLK_PCM

3
4
5
7
8
9
10
11
15
16
17
19
23
24
25
26
38
39
40
41
43
45
46
47
49
51
52
53
54
55
56
57

GND
GND
GND
GND
GND
GND
GND
GND

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

6
22
42
58
78
94
114
130

AD[0..31]

10,18,19,29,36 AD[0..31]

72
71

1
C206

74
73

17
17
17
17

S1_A[0..25]

S1_A[0..25] 17

S1_D[0..15]

S1_D[0..15] 17

S1_IOWR# 17

S1_A9

S1_IORD# 17

S1_A11
S1_OE#

S1_OE#

S1_OE# 17
S1_CE2# 17

S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

PIR(24)

R500
47K_0402

S1_VCC

S1_REG# 17

S1_A12
S1_A8

S1_CE1# 17
S1_RST 17

S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A14

S1_WAIT# 17

S1_A13

1
R181

2
33_0402

S1_INPACK# 17
S1_WE# 17
S1_A16
S1_BVD1 17
S1_WP 17

1UF_25V_0805
2

S1_D2
S1_A18
S1_D14

2
G

+5V

18,29,31 WAKEUP#

PCM_PMER#

1
D

Q23
2N7002

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

16

of

44

PCMCIA Socket

+12VALW

S1_A[0..25]

S1_VCC

C38
.1UF_0402
9

12V

5
6

5V
5V

VCC
VCC
VCC

13
12
11

VPP

10

C61
4.7UF_10V_0805

16 S1_CD2#
16 S1_WP

S1_VPP

+5VALW

C60
.1UF_0402
+3VALW

1
2
15
14

VCCD0# 16
VCCD1# 16
VPPD0 16
VPPD1 16

16 S1_BVD1
16 S1_BVD2
16 S1_REG#

GND
7

.1UF_0402

SHDN

16 S1_INPACK#
3.3V
3.3V

OC

8
16 S1_WAIT#

PIR(18)

16 S1_RST

16

C59

C49
.1UF_0402

VCCD0
VCCD1
VPPD0
VPPD1
3
4

16 S1_VS2
G_RST# 16,31

S1_CD2#
S1_WP
S1_D10
S1_D2
S1_D9
S1_D1
S1_D8
S1_D0
S1_BVD1
S1_A0
S1_BVD2
S1_A1
S1_REG#
S1_A2
S1_INPACK#
S1_A3
S1_WAIT#
S1_A4
S1_RST
S1_A5
S1_VS2
S1_A6
S1_A25
S1_A7
S1_A24
S1_A12
S1_A23
S1_A15
S1_A22

S1_A16
S1_VPP
S1_VCC

16 S1_RDY#
16 S1_WE#
S1_VPP

S1_VCC

C101

S1_A[0..25] 16

JP16
S1_D[0..15]

U4
TPS2211

10UF_10V_1206

C99

C103

C108

.1UF_0402

4.7UF_25V_1206

.01UF_0402

16 S1_IOWR#
16 S1_IORD#
16 S1_VS1
16 S1_OE#
16 S1_CE2#

16 S1_CE1#

S1_A17
S1_A8
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_VS1
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_CE1#
S1_D14
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_CD1#
S1_D3

a68
a34
a67
a33
GND
a66
a32
a65
a31
a64
a30
a63
GND
a29
a62
a28
a61
a27
a60
a26
GND
a59
a25
a58
a24
a57
a23
a56
GND
a22
a55
a21
a54
a20
a53
GND
a19
a52
a18
a51
a17
a50
a16
a49
a15
a48
a14
a47
a13
GND
a46
a12
a45
a11
a44
GND
a10
a43
a9
a42
a8
GND
a41
a7
a40
a6
a39
a5
GND
a38
a4
a37
a3
a36
a2
a35
a1

b68
b34
b67
b33
GND
b66
b32
b65
b31
b64
b30
b63
GND
b29
b62
b28
b61
b27
b60
b26
GND
b59
b25
b58
b24
b57
b23
b56
GND
b22
b55
b21
b54
b20
b53
GND
b19
b52
b18
b51
b17
b50
b16
b49
b15
b48
b14
b47
b13
GND
b46
b12
b45
b11
b44
GND
b10
b43
b9
b42
b8
GND
b41
b7
b40
b6
b39
b5
GND
b38
b4
b37
b3
b36
b2
b35
b1

B77
B76
B75
B74
B73
B72
B71
B70
B69
B68
B67
B66
B65
B64
B63
B62
B61
B60
B59
B58
B57
B56
B55
B54
B53
B52
B51
B50
B49
B48
B47
B46
B45
B44
B43
B42
B41
B40
B39
B38
B37
B36
B35
B34
B33
B32
B31
B30
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1

S1_D[0..15] 16

C98
1

S1_CD1#

1000PF_0402

C133
2

S1_CD2#

1000PF_0402

JP16AS1

CARDBUS HOUSING

78
79
80
81

78
79
80
81

16 S1_CD1#

S1_A21
S1_RDY#
S1_A20
S1_WE#
S1_A19
S1_A14
S1_A18
S1_A13

A77
A76
A75
A74
A73
A72
A71
A70
A69
A68
A67
A66
A65
A64
A63
A62
A61
A60
A59
A58
A57
A56
A55
A54
A53
A52
A51
A50
A49
A48
A47
A46
A45
A44
A43
A42
A41
A40
A39
A38
A37
A36
A35
A34
A33
A32
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1

PCMC154PIN

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

17

of

44

IEEE1394 Controller/PHY

Enable I2C EEPROM

1394@10PF_0402

R184
1394@1K_0402

C54

C90

C91
1394@.1UF_0402

1394@.1UF_0402
2

C82

1394@.1UF_0402

C88

C53

1394@.1UF_0402

C64

C51

C250

+3VS

R176

1394@.1UF_0402

1394@.1UF_0402

1394@.1UF_0402

1394@.1UF_0402

1394@2K_0402

AD[0..31]

10,16,19,29,36 AD[0..31]

C50

1394@.1UF_0402
2

R183
1394@1M_0402

C242
1394@10PF_0402

C80
1394@.1UF_0402

+3VS

X1
1394@24.576MHz

+3VS

+3VS

R180
1394@1K_0402

+3VS
C77

C96
1394@.1UF_0402

C93

C95

1394@.1UF_0402

1394@.1UF_0402

C94
1394@.1UF_0402

1394@.1UF_0402

12

R56
33_0402

C97

AD31
AD30
AD29
AD28
AD27

AD0
AD1

A0
A1
A2
GND

8
7
6 EECK_LAN
5 EEDI_LAN

VCC
WC#
SCL
SDA

U20
1
2
3
4

R177
1394@510

1394@24C02-27
2

AD2
AD3
AD4
AD5
AD6
AD7
CBE#0 10,16,19,29,36

R32

AD13
AD14
AD15

1394@56.2_1%

1394@56.2_1%

AD8
AD9
AD10
AD11
AD12

C72
3

R36
1394@1UF_25V_0805

CBE#1 10,16,19,29,36
PAR 10,16,19,29,36
PERR# 16,19,29,36

XTPBIAS0
XTPA0+
XTPA0XTPB0+
XTPB0-

1394@VT6306

103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

22PF_0402

10,21 GNT#4
10,21 REQ#4

+3VS

EECK_LAN
EEDI_LAN

WAKEUP# 16,29,31

PCLK_1394

PCLK_1394

38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

1
2
3
4

R39

JP13

L20

4
3
2
1

8
7
6
5

1394@IEEE1394-COILS 1394@1394_CONN 4PIN

19 PIRQC#
9,14,16,19,22,23,29,31,36 PCIRST#
11 PCLK_1394

LPS/CMC
PME#
VSSC2
VDDC2
VSS9
VDD6
SCL/EECK
SDA/EEDI
EEDO
EECS
AD0
AD1
VSS8
RAMVSS
RAMVDD
AD2
AD3
AD4
VDD5
AD5
AD6
AD7
VSS7
CBE0#
AD8
AD9
AD10
AD11
AD12
VSS6
VDD4
AD13
AD14
AD15
CBE1#
PAR
PERR#
VSS5

C63
1394@.1UF_0402

VDDARX0
XREXT
NC
GNDARX1
GNDATX1
XTPB0M
XTPB0P
XTPA0M
XTPA0P
XTPBIAS0
VDDARX1
VDDATX1
XTPB1M
XTPB1P
XTPA1M
XTPA1P
XTPBIAS1
GNDARX2
GNDATX2
XTPB2M
XTPB2P
XTPA2M
XTPA2P
XTPBIAS2
VDDARX2
VDDATX2
INTA#
PCIRST#
PCICLK
VSS1
GNT#
REQ#
AD31
AD30
AD29
AD28
AD27
VDD1

XTPB0XTPB0+
XTPA0XTPA0+
XTPBIAS0

65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102

C73
1394@.1UF_0402
C66
1394@47PF_0402

GNDARX0
XCPS
VDDATX0
XO
XI
GNDATX0
PHYRESET
LINKON/TSIJMP
LREQ/TSOJMP
CTL1/PC1JMP
CTL0/PC0JMP
D7/PC2JMP
D6/CMCJMP
D5
PGND2
PVDD2
D4
D3
D2
D1
D0
MODE0
MODE1
PGND1
SCLK
PVDD1

R30
1394@6.34K 1%

VSS2
AD26
AD25
AD24
CBE3#
IDSEL
AD23
AD22
VSS3
AD21
VDD2
VDDC1
VSSC1
AD20
AD19
AD18
AD17
AD16
VSS4
CBE2#
FRAME#
IRDY#
VDD3
TRDY#
DEVSEL#
STOP#

U6

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39

C78
1394@.1UF_0402

R50
1394@56.2_1%

C83

1394@56.2_1%

R42
1394@5.11K

1394@220PF_0402
2

AD16
AD17
AD18
AD19
AD20

AD21

AD22
AD23

AD24
AD25
AD26

STOP# 10,16,19,29,36
DEVSEL# 10,16,19,29,36
TRDY# 10,16,19,29,36
IRDY# 10,16,19,29,36
FRAME# 10,16,19,29,36
CBE#2 10,16,19,29,36

10,16,19,29,36 CBE#3
AD25
4

1
R40

2
1394@100_0402

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

18

of

44

VT8231-A

1UF_10V

C505

C506

1UF_10V

C432
1UF_10V

1UF_10V

C457

1UF_10V

C451

1UF_10V

C426

1UF_10V

C404

1UF_10V

C401

1UF_10V

C407

1UF_10V

C405

1UF_10V

C471

1UF_10V

C408

1UF_10V

C400

1UF_10V

C417

1UF_10V

C456

1UF_10V

C496

+3VS

+3VS

G6
H6
J6
L6
M6
N6
F7
G8
G9
G10
G12
F9
F12
F13
F15
J15
K15
M15
P15

+3VS

10 PREQ#
10 PGNT#
10,16
29,36
18
36

PCIRST#_SB

R296 2
R297 2

10K_0402
1
1

F6
A7
C7
B7
D7
E7
C8

FRAME
DEVSEL
IRDY
TRDY
STOP
SERR
PAR

D2
D1

REQL
GNTL

B2
B1
C3
C2

PINTA
PINTB
PINTC
PINTD

E4
M17
R5

CLKRUN#

31 GATEA20
31 KBRST#

PCIRST
PCICLK
CLKRUN

M4
N1
N2
N4

KBCK/KA20G
*
KBDT/KBRC
*
MSCK/IRQ1
*
MSDT/IRQ12

U8
R8
T8

IRRX
IRTX
IRRX2/GPI

Internal
Keyboard
* Controller

10K_0402
2
R395

1
0_0402
1

27 IRRX
27 IRTXOUT
27 IRMODE

Ground

1
28
28
28
28

U*
U*
U*
U*

USBP2+
USBP2USBP3+
USBP3-

B20
A20
C17
B17

USBP2+
USBP2USBP3+
USBP3-

28
28
28
28

OC0
OC1

A17
D16

OVCUR#0
OVCUR#1

PRD0
PRD1
PRD2
PRD3
PRD4
PRD5
PRD6
PRD7

D11
C12
A12
E12
C13
B13
A13
C14

LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7

ACK
BUSY
PE
SLCT
ERROR
PINIT
AUTOFD
SLCTIN
STROBE

B14
A14
D13
E13
F11
B12
E11
D12
A11

TXD
DTR
RTS
CTS
DSR
DCD
RI
RXD

B15
A16
A15
B16
D14
D15
C16
E14

DRVDEN0
DRVDEN1
INDEX
MTR0
DS1
DS0
MTR1
DIR
STEP
WDATA
WGATE
TRAK00
WRTPRT
RDATA
HDSEL
DSKCHG

L17
K17
L20
K18
K19
J17
J16
K20
J18
J19
J20
H16
H17
H20
H19
H18

USBCLK 11

R370
100K_0402

10 PLOCK#
+3VS

1
2
3
4
5

10
9
8
7
6
10P8R_4.7K

PIRQA#
PIRQB#
PIRQC#
PIRQD#

+3VS

31 RING#

PAR

8
7
6
5

+3VS

8P4R_4.7K_0804
2
1
+3VS
R171
@4.7K_0402

RI1# 35

RXD1 35

Power-On Configuration Strapping Pins

INDEX#

+3VS

TRAK0#
WP#
RDATA#

LO:Disable LPC ROM

21 SA16

2
R394

1
4.7K_0402

7,10,20,31,33 PM_SLP_S1#

2
R283

1
10K_0402

+3VS

Hi:INIT polarity ( slot A )

2
R376
2
R371

1
10K_0402
1
@10K_0402

+3VS

H:Disable CPU strapping

20 MCCS#

2
R338
2
R337

1
10K_0402
1
@10K_0402

+3VS

2
R508
2
R290

1
4.7K_0402
1
@1K_0402

+3VS

DSKCHG#

L:Enable CPU strapping

+5VS
2
R421 2
R420

1
1 1K_0402
330_0402

1
2
3
4

21 SA17

8
7
6
5
+3VS

RTS1#
RXD1

2
R363 2
R366

1
1 10K_0402
10K_0402

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
C

H:Disable auto reboot

L:Enable auto reboot

PIR(38)

Date:
A

RIA0 35

R388
100K_0402

CLKRUN#

1
2
3
4

2
G
S

R364
10K_0402

8P4R_1K_0804

IRDY#
TRDY#
DEVSEL#
FRAME#

1
TXD1 35
DTR1# 35
RTS1# 35
CTS1# 35
DSR1# 35
DCD1# 35

2
STOP#
SERR#

TXD1
DTR1#
RTS1#
CTS1#
DSR1#
DCD1#
RI1#
RXD1

PCI Pullups
RP41

LPTACK# 28,35
LPTBUSY 28,35
LPTPE 28,35
LPTSLCT 28,35
LPTERR# 28,35
LPTINIT# 28,35
LPTAFD# 28,35
LPTSLCTIN# 28,35
+3VS
LPTSTB# 28,35

WP#
TRAK0#

16,18,29,36 PERR#

D19
36 MODEM_RI#

Q40
2N7002

DSKCHG#

RP38

RB751V

RP64

RB751V
R360
10_0402

OVCUR#0 28,35
OVCUR#1 28
LPD[0..7] 28,35

D18
16 PCM_RI#

USBCLK

C463
15PF_0402

C507
15PF_0402

+3V

USBP0+
USBP0USBP1+
USBP1-

INDEX#
RDATA#

2
1

B18
A18
B19
A19

P14
J8
J9
J10
J11
J12
J13
K8
K9
K10
K11
K12
K13
L8
L9
L10
L11
L12
L13
P10

R416
10_0402 VT8231

C15

USBP0+
USBP0USBP1+
USBP1-

Floppy
Disk

PIR(40)
11 PCLK_SB
10,16,31,36 CLKRUN#
+3V

PIRQA#
PIRQB#
PIRQC#
PIRQD#

PIRQA#
PIRQB#
PIRQC#
PIRQD#

C_BE0
C_BE1
C_BE2
C_BE3

USBCLK

Serial
Port

FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
SERR#
PAR

10,16,18,29,36 FRAME#
10,16,18,29,36 DEVSEL#
10,16,18,29,36 IRDY#
10,16,18,29,36 TRDY#
10,16,18,29,36 STOP#
10,16,29,36 SERR#
10,16,18,29,36 PAR

F10
A8
D6
C5

C460
.1UF_0402

CBE#0
CBE#1
CBE#2
CBE#3

USBCLK

U*
U*
U*
U*

Parallel
Port

10,16,18,29,36
10,16,18,29,36
10,16,18,29,36
10,16,18,29,36

PC99 Compliant,
Integrated Super-I/O
(FDC,LPT,COM,FIR),
Integrated Fast Ethernet,
LPC, ISA/LPC BIOS
ROM, Integrated
SoundBlaster
Pro/MultiChannel,
DirectSound AC97 Audio
and MC97 Modem
Interface,
UltraDMA-33/66/100
Master Mode EIDE
Controller, 4 Port USB
Controller, Keyboard
Controller, RTC, Serial
IRQ, SMBus, Plug and
Play, ACPI, Enhanced
Power Managerment,
Temperature, Voltage,
and Fan-Speed
Monitoring

C458
10UF_10V_1206

PIR(40)

F14

7SH08FU

USBGND

+3VS
L51
1
2
FBM-L11-160808-601LMP

USB_VCC

SPWROFF# 6,20,31,33

E15

VIA VT8231
South Bridge

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

USBVDD

C462
.1UF_0402

PCI Bus
Interface

@15PF_0402

PCIRST#_SB

1
9,14,16,18,22,23,29,31,36 PCIRST#

C599
2

U*

Power

FIR

R298 @15_0402
1
2 1

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

USB
Interface

+3VS

U66

C11
B11
D10
E10
B10
A10
C10
D9
E9
A9
B9
F8
C9
E8
D8
B8
A6
E6
B6
C6
D5
A5
E5
B5
A4
B4
A3
C4
B3
D4
A1
A2

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

U34A
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

10,16,18,29,36 AD[0..31]

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
D

19

of

44

+1.5VS

+1.5VS
1

+3VS

VT8231-B

+3VS
R69

R70

22 PDCS1#
22 PDCS3#

L18
L19

22 PDDREQ#
22 PDDACK#
22 PDIOR#
22 PDIOW#
22 PDIORDY

P19
N20
N18
P20
N19

22 PDA0
22 PDA1
22 PDA2

M19
M18
M20

22 SDCS1#
22 SDCS3#

U18
U19

22 SDDREQ#
22 SDDACK#
22 SDIOR#
22 SDIOW#
22 SDIORDY

U17
W20
W19
Y19
Y20
V19
V18
V20

22 SDA0
22 SDA1
22 SDA2
+3V
1

P5
P6

VH* DTD+

L2

VRCHGNG#

VFER

K1

FLASH#

DTD-

L3

VH* VDD78

M5

Secondary
IDE

SDA0
SDA1
SDA2

VT8231

R15
R14
P13
R13
P12
P11
R10
P9
R9
P8
R7
FAN1
VH* FAN2/GPI18/GPO18
VH*

C409
.1UF_0402

SDDREQ
SDDACK
SDIOR
SDIOW
SHDRDY

K2
K3

VCCSUS
VCCSUS

1.5K_0402
H_DPSLP# 4,40

VH*

*
*

F4
Y2
J5
Y1
W3
Y6
W6
G5
P4
T4
T9
U9

EXTSMI#

DPSLP#

+3V

EXTSMI# 31
SPWROFF# 6,19,31,33

PBTN#

PME_SB#

1
R303

RSMRST# 33
SWI# 31
MUTE# 32
SCI# 31

SWI#
PME_SB#
LID#
BATLOW#
SUS_STAT#R
SUS_CLK

2
10K_0402

D16
PBTN#

PBTN_OUT# 31
2

RB751V
PM_SLP_S1# 7,10,19,31,33
PM_SLP_S3# 31
PM_SLP_S5# 31
1
R289
SMB_SB_CK 7,12
SMB_SB_DA 7,12
PID2 15
VRCHGNG# 6
FLASH# 32
PID3 15

VRCHGNG#
FLASH#
PCS0#
MCCS#

1
R292

+3V
D17
LID#

2
10K_0402 +3V

SPKR

LID_OUT# 31

PM_BATLOW# 31

RB751V
2
10K_0402

D26
BATLOW#

2
RB751V

MCCS# 19
GT_LO/HI# 6
CPUSTP# 6,11,33
PCISTP# 7,11

CPUSTP#
PCISTP#

D15
SUS_STAT#R

SUS_STAT#

SUS_STAT# 6,29

RB751V

SPKR 24

M1
M3
M2
L4
L1

Ground
GND78

DPSLP#

Q13
3 3904

HA20M# 6
CPURST# 4,8
FERR# 4
HIGNNE# 6
HCPUINIT# 6
HINTR 6
HNMI 6
DPSLP# 7
HSMI# 6
HSTPCLK# 6

2
@0_0402

+3VS

1
R306
1
R293

2
@10K_0402
2
10K_0402

1
R354
1
R279
1
R310
1
R311
1
R382
1
R348
1
R288
1
R351

2
@10K_0402
2
@10K_0402
2
10K_0402
2
@10K_0402
2
@10K_0402
2
@10K_0402
2
10K_0402
2
10K_0402

1
R368
1
R391

2
@10K_0402
2
4.7K_0402

+3V

+3VS +3V

+3VS
HW_VCC

2
1

T16
R16
U20
T19
P16
N17
R20
R18
P18
R19
N16
P17
T20
T18
R17
T17

W1
E2
U2
F2
U3
R4
V3
U1
V2
T3
N5
W2
P1
P2
N3
T2
R3
T1

1
R314

C396
.1UF_0402

L5

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

BITCLK
A20M
CPURST
SDIN0
FERR
SDIN1
Power
IGNNE
SYNC
INIT
SDOUT
INTR
ACRST
NMI
JBY
CPU
SLP
JBX
AC97
JAY
Interface SMI
STPCLK
JAX
Audio/Modem
JAB2
Game Port
JAB1
JBB2
* EXTSMI/GPI2
PWRGD
JBB1
R*
PWRBTN
MSO/SPDIF
*
RSMRST
MSI/I2S
R* RING/GPI3
*
PDD0
GPO0
*
Power
PDD1
GPI1
*
PDD2
Management* PME/GPI6
LID/GPI4
PDD3
* BATLOW/GPI5
and
PDD4
*
PDD5
External * SUSST1/GPO3
PDD6
* SUSCLK/GPO4
State
SUSA/GPO1
PDD7
* SUSB/GPO2
PDD8
Monitoring
*
SUSC
PDD9
*SMBALT/GPI7
PDD10
*
SMBCLK
PDD11
* SMBDATA
Primary
PDD12
*
IDE
PDD13
GPI0
PDD14
R* GPIOA/GPI24/GPO24
PDD15
GPIOC/GPI25/GPO25
PDCS1
GPIOD/GPI30/GPO30
PDCS3
GPIOE/GPI31/GPO31
GPIO
PCS0/GPO16
MCCS/GPO17
PDDREQ
PCS1/SDIN2/GPI19/GPO19
PDDACK
CPUSTP/GPO5
PDIOR
PDIOW
PCISTP/GPO6
PHDRDY
ROMCS/KBCS
SPEAK
PDA0
PDA1
PDA2
VH* UIC1
VH* UIC2
UIC3
Hardware VH* UIC4
SDCS1
VH* UIC5
SDCS3
Monitoring

22 PDD[0..15]

1.5K_0402

1
W5
U4
U5
T6
V5
R6
T5
U6
Y5
V6

1
1 22_0402
1 22_0402
22_0402

U34B
J3
H1
H2
G1
H3
G2
J2
K5
K4
J1
H5
G3
H4
F1
J4
G4

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

10_0402

Power

2
R300 2
R299 2
R307

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

15PF_0402

R291
2

SUS_CLK

1
L49
FBM-L11-160808-601LMP

SUS_STAT#

C402
10UF_10V_1206

PBTN#
CPUSTP#

M8
M9
M10
M11
M12
M13
G7
G11
G14
H15
L15
N15
P7
K6

24,36 AC97_BCLK
24 AC97_SDIN0
36 AC97_SDIN1
24,36 AC97_SYNC
24,36 AC97_SDOUT
24,36 AC97_RST#

4.7K_0402
C395
2

R77

PCISTP#
EXTSMI#
BATLOW#
LID#

PCS0#
SPKR

PIR(38)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
D

20

of

44

VT8231-C

22 SDD[0..15]

19 SA16
19 SA17

Y18
W17
V16
Y16
W15
V14
U16
U15
T15
W14
Y15
V15
W16
Y17
V17
W18

SA0/SDD0
SA1/SDD1
SA2/SDD2
SA3/SDD3
SA4/SDD4
SA5/SDD5
SA6/SDD6
SA7/SDD7
SA8/SDD8
SA9/SDD9
SA10/SDD10
SA11/SDD11
SA12/SDD12
SA13/SDD13
SA14/SDD14
SA15/SDD15

SA16
SA17

Y14
T13
U13
V13
W13
Y13

SA16
SA17
SA18
SA19
LA20/GPO20
LA21/GPO21

OVCUR#2

27 OVCUR#2

22 IRQ14
22 IRQ15
16,31 SERIRQ

MEMR
MEMW
IOR/OC2/GPO22
IOW/OC3/GPO23

IRQ14
IRQ15
SERIRQ

T14
U14
V9

IRQ14
IRQ15
SERIRQ

C397

REQH
GNTH

C1
D3

PCI Bus

14.31818MHz

L*
LAN
Controller L*
L*

R* RTC Battery

L*
L*
L*

MTXE
MTXD0
MTXD1
MTXD2
MTXD3
MTXC

F19
F20
G18
G19
G20
F17

L*
L*
L*
L*
L*
L*
L*

MRXER
MRXC
MRXDV
MRXD0
MRXD1
MRXD2
MRXD3

F18
C19
E20
E19
E18
D20
D19

L*
L*

MDC
MDIO

C20
D18

Serial
SEEDO
EEPROM SEEDI

SEECS

SEECLK

C18
D17
E17
E16

VDDRAM
GNDRAM

G15
G13

VDDM

F16
K16

2
1
2
31 THRM#

SYSVOL_UP#
SYSVOL_DW#
THRM#
CPUMISS
INTRUDER#

R2
R1
P3
V1
F3

SMBDT2/GPI26/GPO26
SMBCK2/GPI27/GPO27
AOLGPI/GPI17
*
CPUMISS/GPI16
*
INTRUDER/GPI8

* I2C and
*

Monitoring

R*

L16

PLLVDD

C500

R02 VALUE CHANGE

.1UF_0402
2

M16

ENDIM1 12

SD12

+RTCVCC

PIDERST# 22

SD14

INTRUDER#
1
R308

SIDERST# 22
LFRAME#
LDRQ#
LAD0
LAD1
LAD2
LAD3

LFRAME# 31
LDRQ# 31
LAD0 31
LAD1 31
LAD2 31
LAD3 31

2
10K_0402

+3VS
RP37
SD8
SD10
SD12
SD14

REQ#4 10,18
GNT#4 10,18

1
2
3
4

8
7
6
5

8P4R_4.7K_0804

PLLGND

Power and
RTC
Clock
Ground for
Internal
R*
R*
PLL

VT8231

LAN
Power L*

L* VDDM

+3VS
RP74
LAD0
LAD1
LAD2
LAD3

1
2
3
4

8
7
6
5

8P4R_4.7K_0804
RP70
1
2
3
4
5

1
2
3
4

10
9
8
7
6

LDRQ#

2
R319
2
R318
2
R317
2
R315

LFRAME#
IOR#

10P8R_10K
RP63
8
7
6
5

IOW#

1
4.7K_0402
1
4.7K_0402
1
4.7K_0402
1
4.7K_0402

RP46
MEMR#
MEMW#
SERIRQ

8P4R_10K_0804

1
2
3
4

8
7
6
5

8P4R_4.7K_0804
+3VS
3

+5VS

RTCX2

PLLVDD

2
10K_0402

ENDIM0 12

SD10

RP48

F5

L55
1
2
FBM-L11-160808-601LMP

+3VS

APIC

RTCX1

15 PID0

APICREQ/WSC/GPI14
APICCS/PICD0/GPI28/GPO28
APICACK/PICD1/GPI29/GPO29
APICCLK/GPI9

E3

V4
W4
Y4
Y3

15 PID1

SD8

1
R309

G16
G17

.1UF_0402

C465
15PF_0402

+3V
CPUMISS

ISA Bus

CRS
COL

OSC
VBAT

W8
Y8
V8
Y7
W7
V7

L*
L*

E1

+RTCVCC

R356
10_0402

R12
V12
W12
Y12
U12
U11
R11
T11
Y11
W11
V11
T10
U10
Y10
W10
V10

LFRAME
LREQ/SDIN3/GPI15
LAD0
LAD1
LAD2
LAD3

LPC
Interface

W9
Y9
U7
T7

T12

SD0
SD1
SD2
SD3
LPC
SD4
SD5
Interface
SD6
SD7
SD8/HREQ1/GPI10
SD9/HGNT1/GPO8
SD10/HREQ2/GPI11
SD11/HGNT2/GPO9
SD12/LREQ1/GPI12
SD13/LGNT1/GPO10
SD14/LREQ2/GPI13
SD15/LGNT2/GPO11

Secondary
IDE

MEMR#
MEMW#
IOR#
IOW#

OSCSB

11 OSCSB

U34C
SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

1
2
3
4

IRQ14
IRQ15
Y5

8
7
6
5

8P4R_4.7K_0804
C399

32.768KHZ

+3V

10PF_0402
2

10PF_0402

C413

SYSVOL_UP#
SYSVOL_DW#

2
R285
2
R284

1
4.7K_0402
1
4.7K_0402

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

21

of

44

HDD/CD-ROM Module
+5VS

C177

C561

RP68

.1UF_0402

Place component's closely IDE CONN.

+3VS
C595
2

PCIRST#

1
R150

U64

P_IDERST# 2
3

7SH08FU

PIR(36)

27,32 HDDACT_LED#
+5VS
1
R475

PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

1
2
3
4
5
6
7
8

JP21
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

P_DDREQ#
P_DIOW#
P_DIOR#
P_DIORDY
P_DDACK#
P_IRQ14
P_DA1
P_DA0
P_DCS#1

+5VS

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10
9

P_DD0
P_DD1
P_DD2
P_DD3
P_DD4
P_DD5
P_DD6
P_DD7

16P8R_33

2
10K_0402

PDD_IDERST#
P_DD7
P_DD6
P_DD5
P_DD4
P_DD3
P_DD2
P_DD1
P_DD0

2
10K_0402

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

RP67
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

+5VS

P_DD8
P_DD9
P_DD10
P_DD11
P_DD12
P_DD13
P_DD14
P_DD15

9,14,16,18,19,23,29,31,36 PCIRST#

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7

R398
100K_0402

16
15
14
13
12
11
10
9

P_DD8
P_DD9
P_DD10
P_DD11
P_DD12
P_DD13
P_DD14
P_DD15

16P8R_33

.1UF_0402

PDD[0..15]

C563

1UF_25V_0805
2

10UF_10V_1206
2

1000PF_0402

20 PDD[0..15]
C562

RP65
PCSEL

1
R466

PDCS3#
PDCS1#
PDA2
PDA0

1
2
3
4

20 PDA1
21 IRQ14
20 PDIORDY
21 PIDERST#

1
2
3
4

20
20
20
20

2
470_0402

8
7
6
5

P_DCS#3
P_DCS#1
P_DA2
P_DA0

8P4R_33_0804

P_DA2
P_DCS#3

RP62
+5VS

HDD CONN

PIDERST#

8
7
6
5

8P4R_22_0804

P_DA1
P_IRQ14
P_DIORDY
P_IDERST#
2

1
R415

2
1K_0402

+5VS

RP66
1
2
3
4

20 PDIOW#
20 PDIOR#
20 PDDREQ#
20 PDDACK#

8
7
6
5

8P4R_22_0804

+5VCD_1
L53
1
2
FBM-L11-322513-151
1

C485

1UF_25V_0805

C478

23 S_DD[0..15]

CD_DD[0..15]

1
R426

10UF_10V_1206
2
1
R407
10K_0402
23 INT_CD_L
23 CD_IDERST#

CD_DD7
CD_DD6
CD_DD5
CD_DD4
CD_DD3
CD_DD2
CD_DD1
CD_DD0

23 CD_DIOW#
23 CD_DIORDY
23 CD_IRQ15
23 CD_DA1
23 CD_DA0
23 CD_DCS1#
27,32 CDACT_LED#
+5VCD

2
R396

+5VCD_1
+5VCD_1

1
10K_0402
2

SEC_CSEL
R358
470_0402

1
R433

16
15
14
13
12
11
10
9

1
2
3
4
5
6
7
8

S_DD0
S_DD1
S_DD2
S_DD3
S_DD4
S_DD5
S_DD6
S_DD7

16P8R_33

2
@0_0402

RP52
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

CD_AGND 23,24
JP23
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

INT_CD_R 23
CD_DD8
CD_DD9
CD_DD10
CD_DD11
CD_DD12
CD_DD13
CD_DD14
CD_DD15

R411
1

W=80mils

2
C480
1
R353

16
15
14
13
12
11
10
9

S_DD8
S_DD9
S_DD10
S_DD11
S_DD12
S_DD13
S_DD14
S_DD15

RP71
20
20
20
20

CD_DDREQ# 23
CD_DIOR# 23

PDIAG#

1
2
3
4
5
6
7
8

16P8R_33

CD_DACK# 23
100K_0402
2
CD_DA2 23
CD_DCS3# 23
+5VCD_1
+5VCD_1
+5VCD_1

1
.1UF_0402

1
2
3
4

SDCS3#
SDCS1#
SDA2
SDA0

8
7
6
5

RP58
20 SDA1
21 IRQ15
20 SDIORDY
21 SIDERST#

SIDERST#

1
2
3
4

8
7
6
5

S_DA1 23
S_IRQ15 23
S_DIORDY 23
S_IDERST# 23
1
R409

2
1K_0402

+5VS

RP61

+5VCD
20 SDIOW#
20 SDIOR#
20 SDDREQ#
20 SDDACK#

CD-ROM CONN.

S_DCS3# 23
S_DCS1# 23
S_DA2 23
S_DA0 23

8P4R_33_0804
+5VCD

8P4R_22_0804

2
100K_0402

1
2
3
4

8
7
6
5

8P4R_22_0804

2
@0_0402

S_DD[0..15]
RP40

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7

C513
3

1
5.6K_0402

.1UF_0402

Place component's closely IDE CONN.

23 CD_DD[0..15]

2
R422

SDD[0..15]

10UF_10V_1206
2

1000PF_0402

C470

C473

21 SDD[0..15]
1

+5VCD

P_DIOW#
P_DIOR#
P_DDREQ#
P_DDACK#

S_DIOW# 23
S_DIOR# 23
S_DDREQ# 23
S_DACK# 23
2
R412

1
5.6K_0402

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

22

of

44

+5VALW

Audio DJ OZ163

U14
VCC

GND

EC_SMD1_CD
+5VCD_2

U15
VCC

S_DD[0..15] 22

S_DD0
S_DD1
S_DD2
S_DD3
S_DD4
S_DD5
S_DD6
S_DD7
S_DD8
S_DD9
S_DD10
S_DD11
S_DD12
S_DD13
S_DD14
S_DD15

X3
OSC2
DJ@8MHZ

DJ@1M_0402

C492

DJ@10PF_0402

DJ@10PF_0402

C482

VDD

DJ@74HCT1G66

R379

C461

DJ@.1UF_0402

DJ@.1UF_0402

DJ@.1UF_0402

+5VCD

U41
DJ@OZ163

58

GND

OSC1

C454

DM_ON

2
44

S_DD[0..15]

CD_DD0
CD_DD1
CD_DD2
CD_DD3
CD_DD4
CD_DD5
CD_DD6
CD_DD7
CD_DD8
CD_DD9
CD_DD10
CD_DD11
CD_DD12
CD_DD13
CD_DD14
CD_DD15

HDA0
HDA1
HDA2

CDA0
CDA1
CDA2

69
71
67

CD_DA0
CD_DA1
CD_DA2

63
61

HCS0
HCS1

CCS0
CCS1

64
62

CD_DCS1#
CD_DCS3#

S_DIORDY

99
6
72
93

HDIOR#
HDIOW#
HIOCS16#
HIORDY

CDIOR#
CDIOW#
CIOCS16#
CIORDY

100
5
73
94

CD_DIOR#
CD_DIOW#
CIOCS16#
CD_DIORDY

S_IRQ15
S_DDREQ#
S_DACK#

74
12
88

HINTRQ
HDMARQ
HDMACK#

CHINTRQ
CDMARQ
CHDMACK#

75
13
89

CD_IRQ15
CD_DDREQ#
CD_DACK#

CRESET#
CDASPN

23
60

CD_IDERST#
CDASPN

SSYNC
SBIT_CLK
SDATA_OUT
SDATA_IN
SACRSTN

47
52
54
49
45

PWR_CTL

51

S_DA0
S_DA1
S_DA2

68
70
66

S_DCS1#
S_DCS3#

INT_CD_L1
2
1
R126
20K_0402
2
1
R130
33K_0402

22 INT_CD_L
77
79
82
84
87
91
96
98
1
3
7
10
14
17
19
21

HDD0
HDD1
HDD2
HDD3
HDD4
HDD5
HDD6
HDD7
HDD8
HDD9
HDD10
HDD11
HDD12
HDD13
HDD14
HDD15

C459
1

C168
1
2

INT_CD_L2

1UF_10V

PLAYBTN#
REVBTN#
FRDBTN#
STOPBTN#

1
2
3
4

8
7
6
5

22 S_DCS1#
22 S_DCS3#

U31B
C170
2

INT_CD_R1 1

2
1
R131
20K_0402

22 INT_CD_R

INT_CD_R2

1UF_10V

22 S_DIORDY

.1UF_0402
PCIRST#

9,14,16,18,19,22,29,31,36 PCIRST#

C596
1
2

22 S_IRQ15
22 S_DDREQ#
22 S_DACK#

U65

S_IDERST# 2

22 S_IDERST#

SDD_IDERST#

R147
1
2
DJ@33_0402

7SH08FU
3

R381
1
2
DJ@10K_0402

+5VCD

PIR(36)

D5
DM_ON

DJ@RB751V

R148
DJ@22K_0402

1
D6

2
DJ@1N4148

INTN

1
2
R142 DJ@100K_0402

+5VCD
3

PLAYBTN#
FRDBTN#
REVBTN#
STOPBTN#

R144
DJ@22K_0402
2

DJ@1UF_10V
1

+3VCD

C173
2

EC_SMD1_CD
EC_SMC1_CD

24
59

HRESET#
HDASPN

48
53
55
50
46

HSYNC
HBIT_CLK
HDATA_OUT
HDATA_IN
HACRSTN

28
36
35
34
37

PAV_EN
PLAY/PAUSE
FFORWARD
REWIND
STOP/EJECT

29
25
30

PCSYSTEM_OFF
INTN
RESET#

26

SDATA

27
OSC1
OSC2

31
32

OSCI
OSCO

CD_DA0 22
CD_DA1 22
CD_DA2 22

14
4
7

CD_DD[0..15]

CDROM_L 24

74HCT4066

DM_ON#

CD_DD[0..15] 22

Input to
CODEC

CD_DCS1# 22
CD_DCS3# 22

U31D
INT_CD_R2

CD_DIOR# 22
CD_DIOW# 22

14
8
7

CD_DIORDY 22

CDROM_R 24

74HCT4066

DM_ON#

CD_IRQ15 22
CD_DDREQ# 22
CD_DACK# 22

RP23
RP51
ISCDROM
CD_IRQ15
CDASPN
INTN

CD_IDERST# 22
+5VCD

1
2
3
4
5

10
9
8
7
6

MODE0
MODE1
GPIO_0
GPIO_1

+5VCD

DJ@10P8R_10K

S_DCS3#
S_DCS1#
S_DA2
S_DA0
S_DA1
S_DIOW#
S_DIOR#
S_DACK#

1
2
3
4
5
6
7
8

S_DD0
S_DD1
S_DD2
S_DD3
S_DD4
S_DD5
S_DD6
S_DD7

1
2
3
4
5
6
7
8

CD_DCS3#
CD_DCS1#
CD_DA2
CD_DA0
CD_DA1
CD_DIOW#
CD_DIOR#
CD_DACK#

16
15
14
13
12
11
10
9
DJN_16P8R_0

1
R332

2
+5VCD
DJ@10K_0402

ISCDROM

80

ISCDROM

GPIO[1]/VOL_UP
GPIO[0]/VOL_DN

39
40

GPIO_1
GPIO_0

MODE0
MODE1

56
57

MODE0
MODE1

PAVMODE

38

CSN
INCN
UDN

41
42
43

1
R145

2
DJ@47K_0402

+5VCD

10
9
8
7
6

+5VCD

RP49

RP55
CD_DD0
CD_DD1
CD_DD2
CD_DD3

1
2
3
4
5

+5VCD

CD_DD7
CD_DD6
CD_DD5
CD_DD4

CD_DD0
CD_DD1
CD_DD2
CD_DD3
CD_DD4
CD_DD5
CD_DD6
CD_DD7

16
15
14
13
12
11
10
9
DJN_16P8R_0

DJ@10P8R_4.7K
3

RP56
1
R141

S_DD8
S_DD9
S_DD10
S_DD11
S_DD12
S_DD13
S_DD14
S_DD15

RP72

2
DJ@10K_0402

CD_DD8
CD_DD9
CD_DD10
CD_DD11
+5VCD

1
2
3
4
5

10
9
8
7
6

CD_DD15
CD_DD14
CD_DD13
CD_DD12

+5VCD

DJ@10P8R_4.7K

16
15
14
13
12
11
10
9

CD_DD8
CD_DD9
CD_DD10
CD_DD11
CD_DD12
CD_DD13
CD_DD14
CD_DD15

1
2
3
4
5
6
7
8
DJN_16P8R_0

16
33
65
85
92

EC_SMD1_CD 25
EC_SMC1_CD 25

RIGHT_EQ 24,25

74HCT4066

U31C
INT_CD_L2

CIOCS16#

SCLK

10

+3VS

14
11
7
DM_ON

GND
GND
GND
GND
GND

S_DIOR#
S_DIOW#

22 S_DIOR#
22 S_DIOW#

LEFT_EQ 24,25

Input
to EQ

1
33K_0402

DJ@8P4R_10K_0804
2

22 S_DA0
22 S_DA1
22 S_DA2

14
1
7

DM_ON
2
R133

+5VCD
RP54

U31A
74HCT4066

.1UF_0402

CDD0
CDD1
CDD2
CDD3
CDD4
CDD5
CDD6
CDD7
CDD8
CDD9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15

76
78
81
83
86
90
95
97
2
4
8
11
15
18
20
22

3
Q17
@2N7002

2
DJ@HB-1M2012-601JT

EC_SMC1_CD

VDD

VDD

4
4,31,35 EC_SMC2

1
L52
C488

22,24 CD_AGND

+5VCD

DJ@74HCT1G66

13

4,31,35 EC_SMD2

12

CD_PLAY

+5VCD

C430

+5VALW

+5VCD

+12VALW

C434

SI4800
C431

1
R342

2
DM_ON

S_DDREQ#

1
R139

U35D

Q19
2N7002

2
3

14
8

CD_PLAY_ON#

CD_PLAY

SDD_IDERST# 1
R146

2
1
R149
1K_0402
CD_DIORDY
2
DJN_0_0402

+5VCD

CD_IRQ15
2
DJN_0_0402
1
2
R140
5.6K_0402
CD_DDREQ#
2
DJN_0_0402
CD_IDERST#
2
DJN_0_0402

+5VALW POWER

CD_PLAY 32
4

Q35
2N7002
+5VALW POWER

12

32 CD_PLAY_ON#

74HCT14
2 EN_CDPLAY#

33_0402

1UF_25V_0805

+5VALW

2
C425

R132
.1UF_0402

4.7UF_10V_0805

2
3

S_IRQ15
DM_ON#

R324
100K_0402

1
2
3
4

U35C
74HCT14

S
S
S
G

D
D
D
D

8
7
6
5

14

EN_CDPLAY# 25,26

1
U33
+5VALW
+5VCD

1
R378

1UF_25V_0805
2

4.7UF_10V_0805

C429

S_DIORDY
R143
10K_0402

+5VALW

Q37
2N7002
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

23

of

44

AC97 Codec

+3VALW

31 BEEP#

+3VALW

AVDD

14

U42D
74LVC14
+3VALW POWER

C503
.22UF

2
1
1
C520
R441
1UF_10V

R330
10K_0402

2
560_0402

+5VALW

+3VALW

2
C452

+5VS

1
1UF_10V

1
10

2
1
1
C519
R439
1UF_10V

U42E
74LVC14
+3VALW POWER

2
560_0402

Q36

R340

2SC2411EK

2.4K_0402

C375
4.7UF_10V_0805

C376
.1UF_0402

11

16 PCM_SPK#

MONO_IN
2
1UF_25V_0805

1
C441

14

R276
10K_0402
U29
3 VIN
1

R335
10K_0402

VOUT

BP

GND

AVDD

SHDN#

C372

.01UF_0402
MAX8868_EUK50

C373
4.7UF_10V_0805

+3VALW POWER
1

R390
10K_1%

U48B
74LVC125
5

R389
100K_1%

PIR(5)
+3VALW

14
2
560_0402
1

VDDC

AVDD_AC97
1
R302

2
0_0805

L50

+3VS

1
2
HB-1M2012-121JT

AVDD

C398

C394
10UF_10V_1206
2

.1UF_0402

C424

D30
RB751V

R444
10K_0402

2
1
1
C518
R438
1UF_10V

12
U42F
74LVC14
+3VALW POWER

13

20 SPKR

C428

1M_0402
R305

C419
.1UF_0402

C433
10UF_10V_1206

MDSPK
2
1UF_10V

1
C403

1
1K_0402
1
10K_0402

2
R312
2
R304

36 MD_SPK

10UF_10V_1206
2

AVDD_AC97

.1UF_0402

C411
R282
33K_0402

.1UF_0402

C437

27
28

AFILT1
AFILT2

29
30

VRAD
VRDA
CAP1
NC
JD/SDIN1
TEST1
ID0#
ID1#
EAPD
SPDIFO
HP-OUT-L
NC
HP-OUT-R

31
32
33
34
43
44
45
46
47
48
39
40
41

C445 1

AUD_VREF
C447 1000PF_0402
C439

C438

2 4.7UF_10V_0805

C443
1UF_10V

1000PF_0402

@1000PF_0402

C446 1

2 4.7UF_10V_0805
1
C442
1
C435

2
1UF_25V_0805
2
1000PF_0402

C449

C450

1UF_10V

1UF_10V

1UF_10V

SPDIFO 35

R114
@10K_0402

R115
@10K_0402

2
R320

CD_GNA

1
6.8K_0402

1
L24

2
0_0805

1
L58

2
0_0805

2
2
22,23 CD_AGND

LEFT_EQ 23,25
RIGHT_EQ 23,25
MD_MIC 36

C440
.1UF_0402

C448

R113 33_0402
1
2

ALC201

VREF
VREFOUT

LINEL
LINER
MDMIC

35
36
37

1000PF_0402

MOD_AUDIO_MONR

1
20K_0402

LINE-OUTL
LINE-OUTR
MONO-OUT

26 MICIN

PC-BEEP
PHONE
AUX-L
AUX-R
VIDEO-L
VIDEO-R
CD-L
CD-R
MIC1
MIC2
LINE-L
LINE-R
VSS
VSS

2
R278

MDSPK

12
13
14
15
16
17
18
20
21
22
23
24

36 MOD_AUDIO_MON

MONO_IN
2
.1UF_0402

1
C410

2
1UF_10V
2
1UF_10V

2
22_0402

RESET#
BIT-CLK
SYNC
SDATA-OUT
SDATA-IN

4
7

23 CDROM_R

1
C412
1
C416

1
R295

11
6
10
5
8

23 CDROM_L

2
22_0402

1000PF_0402

AVSS
AVSS

MOD_AUDIO_MONR

1
R294

CD-GND

20,36 AC97_RST#
20,36 AC97_BCLK
20,36 AC97_SYNC
20,36 AC97_SDOUT
20 AC97_SDIN0

XTL-IN
XTL-OUT

26
42

1
15PF_0402

C436
U30

AVDD
AVDD

1
9

22PF_0402
2
3

2
C392

VDD
VDD

C393

24.576MHz

19

C406
22PF_0402

25
38

Y4

C414 .1UF_0402
4

R321

6.8K_0402

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Date:
G

Sheet

24
H

of

44

DIGITAL EQ

UPDATED EQ SCHEMATICS
+3VCD

+12VALW
1

R435
LEFT_BYPASS 26

U37

2
EQ@20K_0402

R359
100K_0402

1
2
3
4

S
S
S
G

C468
.1UF_0402
2

D
D
D
D
SI4800

1
R432

23,24 LEFT_EQ

8
7
6
5

+3VALW

EQN_0_0402

R362
33_0402

R431

C526

12

@4.22K

@220PF_0402

EN_CDPLAY# 23,26

Q38
2N7002

2
Q39
2N7002

R451
1

RIGHT_BYPASS 26

EQN_0_0402
2
EQ@20K_0402
2

1
R450

23,24 RIGHT_EQ
C542

R448
@4.22K
1

U43

+3VCD

LRCLK/O
SCLK/O
MCLK_OUT

13
14

XTLIN1/MCLK
XTLIN2

48

RINA

40

RINB

41

ANLP

47

ANLM

46

ANRP

42

ANRM

43

EQ@1UF_10V
2

C529
2
C536

EQ@1UF_10V

EQ_SCL
EQ_SDA

X2

15
16

SCL
SDA

5
6
7
8
9
11
21

INPA_ACT
RST#
CS1
PWRDWN
TEST
CLK_SEL
IFM/S

EQ@24.576MHz
CS1

+3VCD
C498

C464

C469

EQ@.1UF_0402

EQ@15PF_0402

EQ@15PF_0402

AOUTR

37

VCOM

38

AOUTL

39

NC

34

NC1

36

R385
D20

EQ@RB751V
3

R384

+3VCD

ALLPASS
IO0
IO1
IO2
IO3
IO4
IO5

@10K_0402

IO0
IO1
IO2
IO3
IO4
IO5

27
28
29
30
31
32
33

R447

EQ@1200PF
RIGHT

EQ@24.9K

RIGHT 26
EQOUT_VREF 26

LEFT

LEFT 26

C533

VRFILT

VREFP

44

VREFM

45

CAP_PLL

10

AVDD

35

C497

EQ@10UF_10V_1206

17

DVDD

AVSSREF

18

DVSS

AVSS

1
C479

.1UF_0402

C504
3

EQ@.1UF_0402

C530

EQ@.1UF_0402

C531

+3VCD_A

1
C477

+3VCD

10UF_10V_1206

26 HPS

EQ@10K_0402

EQ@24.9K

C534

R401
EQ@10K_0402

R449

EQ@1200PF

R387
@10K_0402

19
20
12

LINB

EC_SMD1_CD 23

C527
1
2

CS1

SDOUT1
SDOUT2
SDOUT_ADC

EC_SMC1_CD 23

2 EQ@0_0402

EQ@TAS3002CPFB

R380
EQ@10K_0402

26
24
25

LINA

2 EQ@0_0402

R377 1

C539
EQ@1UF_10V

C541
EQ@.1UF_0402

SDIN1
SDIN2

R369 1

EQ_SDA

+3VCD
R393
EQ@10K_0402

22
23

EQ_SCL

+3VCD

@220PF_0402

EQ@10UF_10V_1206

EQ@.1UF_0402

L56

+3VCD_A

C499

1
2
EQ@FBM-11-160808-121

+3VCD

R383
C515
EQ@27.4

+
EQ@.1UF_0402

IO0
IO1
IO2
IO3

C483

EQ@1500PF

C476
EQ@.068UF

4
3
2
1

5
6
7
8

RP69

EQ@10UF_10V_1206

EQ@8P4R_10K_0804
RP73
5
6
7
8

4
3
2
1

IO4
IO5

EQ@8P4R_10K_0804

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

25

of

44

14

+5VALW

AMP & Audio Jack

U26A
JP10

SPKR+
SPKR-

3
2
74AHCT32

1
2

+5VAMPP

1
2

R-SPK CONN.
JP11

2
C545

SPKL+
SPKL-

C546

1
2

SPKR-

19

LOUT+

LOUT-

HPOUT_L

1
2
C558
100UF_10V_D2

SPKL-

LINEOUTL
C23

1
1

2 LINEOUT_R
4.7UF_10V_0805
2 LINEOUT_L
4.7UF_10V_0805

MODE

L_UP/DOWN#

2
R468

1
0_0402

14

SVR

16

30dB/20dB#

2
L10
HB1M1608-601JT

1
100K_0402

C552

TDA8552TS

C22
330PF_0402

+5VALW

2
D34

1
RB751V

MIC
JP1

HPS

JOPEN1
@3MM

C550

INT_MIC
EXT_MIC

L14
HB1M1608-601JT
1
2
1
2
L8
HB1M1608-601JT
1

3
6
2
1

+5VALW

C15
330PF_0402
2

R203 +5VALW
10K_0402
14

U35B

+5VALW

+5VAMP

2.2UF_16V_0805

.1UF_0402

FOXCONN JA6033L-101
C16
330PF_0402

U26C

HPS1

MIC_PWR

10

C24
330PF_0402

74HCT14

1
10
11
20

2
R474

ADJVOL_UP/DW# 32

14

GAINSEL

U57
7SZ125
+5VALW POWER

1
R473
100K_0402

HP_OUT_PLUG

3
6
2
1

GND1
GND2
GND3
GND4

@100K_0402

27 HP_OUT_PLUG

R_UP/DOWN#

2
JOPEN3
@3MM

L7
HB1M1608-601JT
1
2

HPS

25 HPS

+5VAMP

C25

RB751V

R469

LINEOUTR

5
2

LINE_OUT_PLUG

+5VALW

74AHCT32

HPOUT_L 27

DIS_ADJVOL 32

D33
HPS

1
LINE_OUT
JP2

PIR(12)

U26B

HPOUT_R 27

7
8

LLINEIN

R472
100K_0402

220PF_0402
220PF_0402
HPOUT_R

1
2
C557
100UF_10V_D2

14
HPS1

C46

15

PIR(12)
+5VALW

C47

SPKL+

+5VAMP

EC_MUTE_LINE#

SPKR+
12

ROUT+
RLINEIN
ROUT-

U62D
74HCT4066
LEFT_SW
9

14
2
8
2.2UF_16V_0805 7

1
C553

17

25 LEFT_BYPASS
25 LEFT

RIGHT_SW

EC_MUTE_LINE#

LEFT

VDD1
VDD2
VDD3
VDD4

14
2
11
2.2UF_16V_0805 7

1
C528

12

RIGHT

25 RIGHT

C43

1
2

L-SPK CONN
220PF_0402

U51
U62B
74HCT4066
10

C44
220PF_0402

3
8
13
18

25 RIGHT_BYPASS

100UF_10V_D2

.1UF_0402

.1UF_0402

+ C554

7
8

0_0805

+5VAMP

L57

PIR(15)
74AHCT32

+5VALW

13

0_0805

Q11
SI2304DS
3
1

EXT_MIC

C343

DOCK_MIC

JP8

DOCK_MIC 35

1
2

PIR(7)

74AHCT32

4.7UF_10V_0805
2
1

INT_MIC

2
10M

MIC_IN

23,25 EN_CDPLAY#

C363
.01UF_0402

1
2

Q30

14
1
7

8
5
2
6
56K_0402

EC_MUTE_L# 32

24 MICIN

MICIN

2
1

C589
2

1UF

EQN_24K_1%
25 EQOUT_VREF

R497

2 1

C590
2

2
0_0402

LOUT_VREF

EQN_75K_1%
MIC_IN

.22UF

1
C591

2
12K_1%
2
15PF_NPO_0402

PIR(15,39)

LINEOUTL 35
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

EC_MUTE_LINE#

PIR(12)

Date:
A

1
R430

R458

10K_1%

1
R498

U62C
74HCT4066
LINEOUTL
3

14
4
7

R456

EC_MUTE_L#
2
0_0603

C583
.1UF_0402
1
2

1
2
1
C547
R445
2.2UF_16V_0805

1
R481

LEFT

C588
.1UF_0402

+5VAMP

U53B
TDA1308

MIC_PWR

AVDD
U63B
TDA1308

PIR(27)

+5VAMP

+3VCD

R496
2
100_0402

2
22PF_0402
2
82K_0402

LOUT_VREF

.1UF_0402

LINEOUTR 35

EC_MUTE_LINE#
1
C535
1
R443

1
1

U63A
TDA1308
1

3
2
2
56K_0402

1UF

U62A
74HCT4066
LINEOUTR
2

C587

13

LOUT_VREF

C586

+5VAMP

AUD_VREF

2N7002

U53A
TDA1308

DOCK_MIC

C208

AVDD

100K_0402
R243

2
22PF_0402
2
82K_0402

.1UF_0402
1
2

PIR(15)
R170

1
2
1
C559
R470
2.2UF_16V_0805

2.2K_0402

0_0402
+12VALW

100K_0402

RIGHT

R168

4.7UF_10V_0805

+12VS

R207

1
C555
1
R471

C192

R-SPK CONN.
1
R34

35 INTMICOFF#

1
2

35 DOCK_HP_OUT_PLUG

+5VAMP

SI2306DS
Q27

L42

+5VALW
11

U26D

12

LINE_OUT_PLUG

10K_0402

14

R204

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

26

of

44

Dot Matrix LCD/FIR

+ C575

C574

470K_0402

100UF_10V_D2

150PF_0402

MODE
PLAY
FRD

.1UF_0402

1UF_25V_0805

R490

OVCUR#2 21
R488

1000PF_0402

KSI1
KSI3

560K_0402

C415

31 DOT_EN
32 DOT_DB4
31 KSO17
31 KSI1
31 KSI3
31 KSI5
31,32 VOL_DW#
32 MUTELED
31 DJ_ON/OFF#
32 MP3_LED#
32 PWR1_LED#
22,32 HDDACT_LED#
32 BATT2_LED#

19 IRTXOUT
19 IRMODE
32 DOT_DB6

LEDVCC
LEDVCC
DOT_R/W# 32
DOT_RS 31
DOT_PRES# 32
KSI0 31
KSI2 31
KSI4 31
VOL_UP# 31,32
EC_MUTE# 32
EC_ACT# 31
51ON# 33,41
CDPLAY_LED# 32
PWR2_LED# 32
BATT1_LED# 32
BACKLIGHT# 32
IRRX 19

KSI0
KSI2
KSI4

C174
.01UF_0402
1

.01UF_0402

LEDVCC

MP3
REV
STOP
C486

1000PF_0402

C487
.01UF_0402

+5VALW
DOT_DB5 32
DOT_DB7 32
1

CD_PLAYER_50PIN_ACES

C489

C490
.01UF_0402

1000PF_0402

C494

1000PF_0402

C576

1
2
FBM-11-451616-800T
1

W=40mils

C493

+5VALW
+5VS

USB_C
L62

+5VS
+5VALW

+5VS

W=40mils

RT9701-CBL
C566

VOUT2

VIN2

VOUT1

VIN1
GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

JP22

+5VS

PIR(41)

U58

USB_CS
+5VS

+3VS

LEDVCC

R485
330_0402
2

+5VS
LEDVCC
+5VS

JP7

BTN2
BTN4

KSI1
KSI3

JP24
BT_ON/OFF# 32

1
3
5
7
9
11

BTN1
BTN3
BTN5

1000PF_0402

C18

C17

.01UF_0402

C28
4.7UF_25V_1206

F_BTN_16PIN

HPOUT_L 26
HPOUT_R 26
HP_OUT_PLUG 26

1
2

HP/USB_12PIN

2
4
6
8
10
12

C580
220PF_0402

L63
FBM-11-160808-121
1
2
1
2
L61
FBM-11-160808-121

28 USB2_D+
28 USB2_D-

PLED# 32
ON/OFFBTN# 33

KSI0
KSI2
KSI4

.01UF_0402

31 CAPSLED#
31 NUMLED#
22,32 CDACT_LED#
31 KSO16

LEDVCC

USB_C

C19

2
4
6
8
10
12
14
16

BT_ON# 32,37

1
3
5
7
9
11
13
15

NDS352P
2

Q56

C582
C581
220PF_0402 220PF_0402

+12VALW
1

Q20
NDS352P

R413
100K_0402

+5VALW

D24
3

2 1
BYS10-45

31 LID_SW#

2
BYS10-45

2
G
2N7002

+5VALW

ACIN 31,42

Q44
NDS351

Q45

D22

SW2

LEDVCC

LID Switch

3
LID SW

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

27

of

44

Printer Port/USB
USB A
USB_AS

USB Port

USB B

USB_A

USB_B

C37

L32
2
1
FBM-11-451616-800T
1

+ C210

C42
.1UF_0402

L13
FBM-11-451616-800T

100UF_10V_D2

.1UF_0402

.1UF_0402

L30
FBM-11-160808-121
USB1_D2
USB1_D+
2
L29
FBM-11-160808-121

USBGND

USB CONN.
C35

1
1

1
L12
FBM-11-451616-800T

.1UF_0402

5
6
7
8

C45

1
2
3
4

1
+

C209
100UF_10V_D2

JP6

L31
FBM-11-160808-121
USB0_D1
2
USB0_D+
1
2
L28
USBGND
FBM-11-160808-121

L17
1
2
FBM-11-451616-800T
1

USB_BS

USB_AS

+3VS

+5VS

USB_BS

R17

R18

10K_0402

10K_0402

8
7
6
5

OC1#
OUT1
OUT2
OC2#

OVCUR#0 19,35

OVCUR#1 19
C36

TPS2042

4.7UF_10V_0805

GND
IN
EN1#
EN2#

C65

1
2
3
4

U5

C74
1UF_10V

1UF_10V

The component's
component' s most place cloely
VT8231.

+5V_PRN
+5V_PRN

Parallel Port

1
R7

2
33_0402

19,35 LPTERR#
+5V_PRN
RP3
1
2
3
4
5

+5V_PRN

10
9
8
7
6

FD7
FD6
FD5
FD4

FD0
LPTERR#
FD1
INIT#
FD2
SLCTIN#
FD3
FD4
FD5

10P8R_2.7K

FD6
RP1
+5V_PRN

RP2
SLCTIN#
INIT#
LPTERR#
AFD/3M#

1
2
3
4
5

+5V_PRN

10
9
8
7
6
10P8R_2.7K

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

LPD3
LPD2
LPD1
LPD0
LPD7
LPD6
LPD5
LPD4

9
10
11
12
13
14
15
16

8
7
6
5
4
3
2
1

FD3
FD2
FD1
FD0
FD7
FD6
FD5
FD4

FD7
19,35 LPTACK#
19,35 LPTBUSY

LPTACK#
LPTBUSY
LPTPE

19,35 LPTPE
LPTSLCT
19,35 LPTSLCT

16P8R_68

1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13

CP1
AFD/3M#
LPTERR#
INIT#
SLCTIN#

1
2
3
4

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

1
2
3
4

RP50
8P4R_15K_0804
3

5
6
7
8

CP11
8P4C_33PF
JP4
LPTCN-25-SUYIN

27
27
37
37

4
3
2
1

1
2

8
7
6
5

8P4R_33_0804

USB2_D+
USB2_DUSB3_D+
USB3_D-

8
7
6
5

8P4C_220PF
CP6
8
7
6
5
8P4C_220PF

RP60
19
19
19
19

1
2
3
4

USBP0+
USBP0USBP1+
USBP1-

USB0_D+
USB0_DUSB1_D+
USB1_D-

8
7
6
5

8P4R_33_0804

USB0_D+
USB0_DUSB1_D+
USB1_D-

35
35
35
35

4
3
2
1

19,35 LPTAFD#

2
33_0402
AFD/3M#

USB2_D+
USB2_DUSB3_D+
USB3_D-

8
7
6
5

CP3
FD0
FD1
FD2
FD3

1
2
3
4

CP10
8P4C_33PF

8
7
6
5

RP59
8P4R_15K_0804
5
6
7
8

19,35 LPTSTB#

1
R4

1
2
3
4

USBP2+
USBP2USBP3+
USBP3-

1
2
3
4

1
R5

SLCTIN#
2
33_0402

LPTSTB#

.1UF_0402

19
19
19
19

8
7
6
5

INIT#
2
33_0402

C190

1
2
3
4

1
R14

2
w=10mils

19,35 LPTSLCTIN#

FD0
FD1
FD2
FD3

4.7UF_10V_0805
R13
1K_0402

19,35 LPTINIT#
3

RB420D

C11

LPD[0..7]

19,35 LPD[0..7]

1w=10mils

RP53
D7
2

+5VS

8P4C_220PF
CP2
FD4
FD5
FD6
FD7

1
2
3
4

8
7
6
5

8P4C_220PF
4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

28

of

44

LAN Realtek RTL8100

L15
LANVDD
FBM_L11-201209-601LMT
LANVDD

R507

6,20 SUS_STAT#

C2

@0_0402

PIR(34)

C14

C31

R159 1K_0402

.1UF_0402

.1UF_0402

.1UF_0402

(ISOLATEB)

+3VS

C188

+
C186
10UF_10V_1206

R158
C187

15K_0402

.1UF_0402
GND

GND

.1UF_0402
L9
LANVDD_AVDD

30 LAN_LED1

C191

LANVDD

HB-1M2012-601JT

.1UF_0402

WAKEUP# 16,18,31
R15
1.8K

LANIO

LANIO
C216

LANVDD

GND

GND
CLKOUT
XTALFB

LAN_RX+
LAN_RXGND

C217
ISOB
GND
LAN_TX+
LAN_TX-

LAN_LED0
LAN_LED1

30 LAN_LED0

C212

.1UF_0402
10UF_10V_1206

.1UF_0402

PIR(29)

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

GND

PCLK_LAN
AD31
AD30
GND
AD29
AD28
AD27
AD26
AD25
AD24
LANVDD

AD24

10,16,18,19,36 CBE#3
AD23

INTAB
RSTB
CLK
GNTB
REQB
AD31
AD30
GND
AD29
VDD
AD28
AD27
AD26
AD25
AD24
VDD25
VDD
CBE3B
IDSEL
AD23

R23

AUX
EECS
EESK
EEDI
EEDO
AD0
AD1
GND
AD2
AD3
VDD25
VDD
AD4
AD5
AD6
VDD25
VDD
AD7
CBE0B
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

R157 100_0402

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

LED0
LED1
NC
LED2
AVDD25
AVDD
ISOLATEB
GND
TXD+
TXDAVDD
AVDD25
RXIN+
RXINGND
RTSET
RTT2
RTT3
GND
X1
X2
AVDD
AVDD25
PMEB
GND
VCTRL
NC
NC
NC
VDD25

19,36 PIRQB#
9,14,16,18,19,22,23,31,36 PCIRST#
11 PCLK_LAN
10 GNT#2
10 REQ#2

U19

AD22
GND
AD21
AD20
AD19
VDD
VDD25
AD18
AD17
AD16
CBE2B
FRAMEB
IRDYB
TRDYB
DEVSELB
GND
STOPB
PERRB
SERRB
PAR
CBE1B
VDD
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8

GND

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

5.6K_0402
U3

LANIO

EECS
EESK
EEDI
EEDO
AD0
AD1
GND
AD2
AD3
LANVDD

1
2
3
4

CS
SK
DI
DO

8
7
6
5

VCC
NC
NC
GND

LANIO
C32
GND
.1UF_0402

93C46-3GR

AD4
AD5
AD6
LANVDD
AD7
CBE#0 10,16,18,19,36

GND

LAN_TX+
CLKOUT

LAN_TX+ 30

LAN_TX-

LAN_TX- 30

RTL8100
LAN_RX+

LAN_RX+ 30

Y2 25MHz

10,16,18,19,36 CBE#2
10,16,18,19,36 FRAME#
10,16,18,19,36 IRDY#
10,16,18,19,36 TRDY#
10,16,18,19,36 DEVSEL#

LAN_RX-

LAN_RX- 30

CRYSTAL

AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8

GND

AD22
GND
AD21
AD20
AD19

AD[0..31]

LANVDD
AD18
AD17
AD16

XTALFB
10,16,18,19,36 AD[0..31]

C193

C211

27PF_0402

27PF_0402
3

CBE#1 10,16,18,19,36
PAR 10,16,18,19,36
SERR# 10,16,19,36
PERR# 16,18,19,36
STOP# 10,16,18,19,36

+12VALW
Q2
NDS351

LANIO
LANVDD

R12

0_0805

R16
100K_0402

R156

PCLK_LAN

+3VALW

2
C185

Q4
1

12

10_0402

22PF_0402

2
G
2N7002

EN_WOL# 31

S
4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

29

of

44

LAN CONN.

C196
.1UF_0402
1

RJ45_TXX- 35

50_1%

RJ45_TXX+ 35
RJ45_RXX- 35

1:1

RJ45_RXX+ 35

R161

50_1%
2

R160

U2
TXTX+
CT
NC
NC
CT
RXRX+

RJ45_TXXRJ45_TXX+

9
10
11
12
13
14
15
16

RJ45_RXXRJ45_RXX+

R162

29 LAN_RX29 LAN_RX+

TDTD+
CT
NC
NC
CT
RDRD+

LANIO

8
7
6
5
4
3
2
1

29 LAN_TX29 LAN_TX+

75_1%

H0013
C200

.1UF_0402

.1UF_0402
1

C215

C198

50_1%

50_1%

R163

75_1%

R167

C48

R166

1000PF_2KV_1206

.1UF_0402
1

CHASSIS GND

C189

JP9
RJ45_TXX+

TX+

RJ45_TXX-

TX-

RJ45_RXX+

C195

N/C1

N/C2

RX-

N/C3

N/C4

RX+

13

CATHODE1

16

ANODE1

15

.1UF_0402
LAN_LED1 29

GREEN
2

R155 330_0402
R169
CATHODE2

ACT_CR

17

1
330_0402

LANIO

C197

@10PF_0402 @10PF_0402 @10PF_0402

2

@10PF_0402

C201

C199

RJ45_RXX-

GND1

N/C5

10

RING

11

TIP

12

N/C6

LANIO

YELLOW

18

GND2

14

LAN_LED0 29

C194

PIR(2)
220PF_3KV_1808

RJ-45 & RJ-11

220PF_3KV_1808

1000PF_0402

1000PF_0402

JOPEN5

JP26
MOD_TIP
MOD_RING

C214
2

C213

C219

MOD_TIP

ANODE2

VH1
DSSA-P3100SB

MOD_RING

1
2

MODEM CONN.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

30

of

44

L59

+RTCVCC

KSO0

KSI3

KSO1

11
13

13

KSO7

15

15

KSO6

17

17

KSO12

19

19

KSO10

KSI7

KSO9

21

CP12
KSO9
KSO0
KSO1
KSO5

KSI5

KSI2

10

KSO5

12

12

KSI0

14

14

KSO4

16

16

KSO8

18

18

KSO3

20

20

KSO13

22

22

KSO11

24

24

KSO15

21

23

8P4C_100PF

10
11

KSO2

KSO14

23

1
2
3
4

8
7
6
5

8P4C_100PF
+3VALW
CP8
KSI4
KSI2
KSI3
KSI0

1
2
3
4

8
7
6
5

CP7
KSO2
KSO4
KSO7
KSO8

1
2
3
4

8
7
6
5

8P4C_100PF

TP3

TP4
TP5
TP6
TP7
TP8

1
1
1
1
1

35 KBD_CLK
35 KBD_DATA
35 PS2_CLK
35 PS2_DATA
33 TP_CLK
33 TP_DATA
27 LID_SW#
27 DJ_ON/OFF#

CP4
1
2
3
4

TP2

8P4C_100PF

INT_KB_CONN.

KSO6
KSO3
KSO12
KSO13

8
7
6
5

8P4C_100PF

8
7
6
5

1
R465

8P4C_100PF

C538

PIR(11)

CRY2

2
20M
1

1
2
3
4

49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68

IOPC0
IOPC1/SCL2
IOPC2/SDA2
IOPC3/TA1
IOPC4/TB1/EXWINT22
IOPC5/TA2
IOPC6/TB2/EXWINT23
IOPC7/CLKOUT

168
169
170
171
172
175
176
1

IOPD0/RI1/EXWINT20
IOPD1/RI2/EXWINT21
IOPD2/EXWINT24

26
29
30

ACIN 27,42
RING# 19
PM_SLP_S3# 20

IOPE4/SWIN
IOPE5/EXWINT40
IOPE6/LPCPD/EXWIN45
IOPE7/CLKRUN/EXWINT46

2
44
24
25

LPC_PD#

ON/OFF 33
PM_SLP_S5# 20

IOPH0/A0/ENV0
IOPH1/A1/ENV1
IOPH2/A2/BADDR0
IOPH3/A3/BADDR1
IOPH4/A4/TRIS
IOPH5/A5/SHBM
IOPH6/A6
IOPH7/A7

124
125
126
127
128
131
132
133

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7

IOPI0/D0
IOPI1/D1
IOPI2/D2
IOPI3/D3
IOPI4/D4
IOPI5/D5
IOPI6/D6
IOPI7/D7

138
139
140
141
144
145
146
147

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

IOPJ0/RD
IOPJ1/WR0

150
151

FRD#
FWR#

SELIO

152

IOPD4
IOPD5
IOPD6
IOPD7

41
42
54
55

MINI_PME#

IOPK0/A8
IOPK1/A9
IOPK2/A10
IOPK3/A11
IOPK4/A12
IOPK5/A13/BE0
IOPK6/A14/BE1
IOPK7/A15/CBRD

143
142
135
134
130
129
121
120

KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15

IOPL0/A16
IOPL1/A17
IOPL2/A18
IOPL3/A19
IOPL4/WR1

113
112
104
103
48

KBA16
KBA17
KBA18
KBA19

PORTB

KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15

PORTC

PORTD-1

105
106
107
108
109

TINT
TCK
TDO
TDI
TMS

JTAG debug port

110
111
114
115
116
117
118
119

PSCLK1/IOPF0
PSDAT1/IOPF1
PSCLK2/IOPF2
PSDAT2/IOPF3
PSCLK3/IOPF4
PSDAT3/IOPF5
PSCLK4/IOPF6
PSDAT4/IOPF7

PS2 interface

PORTE

PORTH

32.768KHZ
Y7

1
121K_0402

32KX1/32KCLKOUT

160

32KX2

PORTI

PORTJ-1

12PF_0402
2

12PF_0402

2
R457
C549

158

+3V

THRM# 21

+3V
1
10K_0402
2

R425

IOPM0/D8
IOPM1/D9
IOPM2/D10
IOPM3/D11
IOPM4/D12
IOPM5/D13
IOPM6/D14
IOPM7/D15

173
174
47

SEL0
SEL1
CLK

+3VALW +5VALW

+3VS

RB751V

SCI# 20

148
149
155
156
3
4
27
28

R505

PORTK
PORTM

PORTL

PCB FOOTPRINT:PC87570
GND1
GND2
GND3
GND4
GND5
GND6
GND7

FSEL#

32 FSEL#

D25

EQ_ON/OFF#

27,32 VOL_UP#
27,32 VOL_DW#
10,15 ENVEE
15 ENBKL

R402

591SCI#

SYSON
34,35,38,41 SUSP#
6,34,40 VR_ON

2
RB751V

PORTD-2
PORTJ-2

PC87591VPC
False

R506

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10

THRMOUT# 1

DOT_EN_591#

7,10,19,20,33 PM_SLP_S1#

IOPJ2/BST0
IOPJ3/BST1
IOPJ4/BST2
IOPJ5/PFS
IOPJ6/PLI
IOPJ7/BRKL_RSTO

AGND

D28

62
63
69
70
75
76

17
35
46
122
159
167
137

10K_0402

FANSPEED
WAKEUP#
THRMOUT#
EC_ACT#
PC7

(BADDR0)

KBA2

(BADDR1)

KBA3

(TRIS)

KBA4

(SHBM)

KBA5

KSO16 27
KSO17 27
EN_WOL# 29
EC_SMC1 7,32,41
EC_SMD1 7,32,41
PCIRST# 9,14,16,18,19,22,23,29,36
PBTN_OUT# 20
EC_SMC2 4,23,35
EC_SMD2 4,23,35
FANSPEED 33
WAKEUP# 16,18,29

10K_0402

10K_0402

RB751V
D21
2

KBRST#_RC

2
G20
DOT_EN_591#

Q65
2N7002

RB751V

PIR(31,44)

DOT_RS_591

PIR(31)

+3VS
U44

1 LPC_PD#
@0_0402

2
R419

5
2

SPWROFF# 6,19,20,33

LPC_PD# 4

R434
10K_0402

PCIRST#

1
5
2

7SH08
C521

For REV:A Only.

.1UF_0402

CLKRUN# 10,16,19,36
+5VALW

SYSON

11

10

+5VALW

SYSON# 34

U35E
74HCT14
+5VALW POWER

R343

EQ_ON/OFF#
FRD# 32
FWR# 32

ECSMI# 9

8 EXTSMI#

+3V

EXTSMI# 20

U48C
74LVC125
+3VALW POWER
R477
EQN_10K_0402

SELIO# 32
EN_WOLR# 36
NUMLED# 27
CAPSLED# 27
MINI_PME# 36

8.2K_0402

R476
EQ@10K_0402

PIR(33)

+3VALW

+3VALW

+3VALW

+3VALW

R313
10K_0402

WAKEUP#

R436
10K_0402

LAN_PME#

R437
10K_0402

MINI_PME#

+3VS

R478
10K_0402

MSEN#

R63
10K_0402

FANSPEED

+3VALW

FSTCHG 39

RP75
EC_SMC1
EC_SMD1
EC_SMC2
EC_SMD2

1
2
3
4

8
7
6
5

WAKEUP#

8P4R_4.7K_0804

D37
2

RB751V
MINI_PME#
1

D38
2

RB751V
LAN_PME#
1

D40
2

@RB751V
CONA#
1

CONA# 32,35

2
FBM-L11-160808-601LMP
L60

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
C

7SH08

EC_ACT# 27

Date:
A

Q64
3 FDV301N

PIR(10,23,43)
DOT_EN 27

19 KBRST#

DOT_RS 27
1

+3V

10K_0402
1

D23
19 GATEA20

100K_0402

R400
10K_0402

R504

1.5K_0402

+3V

U45

11
12
20
21
85
86
91
92
97
98

36 LAN_PME#
16,17 G_RST#
20 SWI#

R417

96

ECSMI#
LAN_PME#

EC_SMC1
EC_SMD1
PCIRST#

VBAT

153
154
162
163
164
165

CRY1

CP5
KSO14
KSO11
KSO10
KSO15

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

IOPB0/URXD
IOPB1/UTXD
IOPB2/USCLK
IOPB3/SCL1
IOPB4/SDA1
IOPB7/RING/PFAIL

Key matrix scan

KBA1

1
@10K_0402
1
10K_0402
1
@10K_0402
1
10K_0402
1
@10K_0402
1
10K_0402

KSI4

INVT_PWM 15
BEEP# 24
VTT_ON 42
ACOFF 39
PM_BATLOW# 20
EC_ON 33
LID_OUT# 20
PCM_SUSP# 16

(ENV1)

2
R453
2
R463
2
R462
2
R461
2
R460
2
R480

PWM
or
PORTA

VTT_ON

KBA0

8
7
6
5

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

32
33
36
37
38
39
40
43

(ENV0)

KSI6

1
2
3
4

71
72
73
74
77
78
79
80

IOPA0/PWM0
IOPA1/PWM1
IOPA2/PWM2
IOPA3/PWM3
IOPA4/PWM4
IOPA5/PWM5
IOPA6/PWM6
IOPA7/PWM7

DOT_RS_591

R503

DAC_BRIG 15
EN_FAN 33
IREF 39

JP19
KSI1

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

CP13
KSI1
KSI7
KSI6
KSI5

GA20/IOPB5
KBRST/IOPB6

99
100
101
102

+3VALW +5VALW
+3VALW

THERMDC_591 4

INT_KBD CONN.

5
6

THERMDA_591 4
C565
2200PF_0402

G20
KBRST#_RC

For REV:A Only.

ALI/MH# 39,41
MSEN# 14,35

MSEN#

161

95

DA0
DA1
DA2
DA3

DA output

AVBATT 39

I/O Address
Index
Data
2E
2F
4E
4F
(HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1
Reserved

IOPD3/ECSCI

BADDR1-0
0 0
0 1
1 0
1 1

ABATT_TEMP 41

31

EC_SMD1

591SCI#

Q46
2N7002

SMBus2

PC7
1
470K_0402

EC_SMC1

10

2
R429

+3VALW

AD Input

14

1
470K_0402

Host interface

81
82
83
84
87
88
89
90
93
94

2
R427

+3VALW

AD0
AD1
AD2
AD3
IOPE0AD4
IOPE1/AD5
IOPE2/AD6
IOPE3/AD7
DP/AD8
DN/AD9

33 EC_RST#

SERIRQ
LDRQ
LFRAME
LAD0
LAD1
LAD2
LAD3
LCLK
LREST
SMI
PWUREQ

21 LFRAME#
21 LAD0
21 LAD1
21 LAD2
21 LAD3
11 PCLK_LPC

7
8
9
15
14
13
10
18
19
22
23

16,21 SERIRQ

1
@0_0402

GND
NC

SMBus1

@LTC1694-1
VTT_PWRGD# 4,11,42

2
R326

21 LDRQ#

2
3

KSI[0..7] 27

C516
1UF_25V_0805

15PF_0402
1

PC87591

Vcc

KBA[0..19] 32
ADB[0..7] 32

KSI[0..7]

1
2

VDD

.1UF_0402
1

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6

R428
2
10_0402

AVCC

U47

34
45
123
136
157
166

C522

.1UF_0402

KBA[0..19]
ADB[0..7]

.1UF_0402
C564

1000PF_0402 C508
.1UF_0402
2
1

+3VALW

C568

16

C540

C517

C514
.1UF_0402

2
1
FBM-L11-160808-601LMP

EC_AVCC
+3VS

2
1
@0_0402

+3VALW

U17

2
0_0402

+3VALW

+3VALW

R423
2

R418

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

31

of

44

BIOS & I/O Port

Output Port

ADB[0..7]

31 ADB[0..7]

Input Port

KBA[0..19]

31 KBA[0..19]

+5VALW
+3VALW

1
19

KBA1
31 SELIO#

+3VALW

KBA2

SELIO#

U52A
3

11
1

CLK
CLR

VCC

AA
LARST#

2
5
6
9
12
15
16
19

GATE_RST 33
BT_RST# 37
BT_DET 37
BT_ON# 27,37
DOT_R/W# 27
EC_MUTE_L# 26
CD_PLAY 23
CD_PLAY_ON# 23

74HCT273

+5VALW

1
R486

2
20K_0402

C567
1
2
1UF_25V_0805

5
74LVC32

20

+5VALW

22,27 CDACT_LED#

+3VALW

DRIVER_ACT#

14

RB717F
KBA4
SELIO#

8
10

27,31 VOL_UP#
27,31 VOL_DW#

11
1

CLK
CLR

RP76
1
2
3
4

BB
LARST#

74LVC32

+3VALW
CONA#
EE
VOL_UP#
VOL_DW#

U52C

D0
D1
D2
D3
D4
D5
D6
D7

U59

VCC

3
4
7
8
13
14
17
18

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

2
5
6
9
12
15
16
19

TPAD_LED# 33
BACKLIGHT# 27
DIS_ADJVOL 26
ADJVOL_UP/DW# 26
DOT_DB4 27
DOT_DB5 27
DOT_DB6 27
DOT_DB7 27

74HCT273

10

22,27 HDDACT_LED#

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

GND

D27
2

U61
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

74LVC244

CC

D0
D1
D2
D3
D4
D5
D6
D7

74LVC32

U52B

SELIO#

1G
2G

10

14

+3VALW

18
16
14
12
9
7
5
3

3
4
7
8
13
14
17
18

GND

TP_ON/OFF#
BT_ON/OFF#

33 TP_ON/OFF#
27 BT_ON/OFF#
37 BT_WAKE_UP

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

10

2 RB751V

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

14

27 EC_MUTE#

2
4
6
8
11
13
15
17

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

2 @RB751V

D32 1

31,35 CONA#
37 BT_PRE#

U56

GND

D31 1

DOT_PRES#
DRIVER_ACT#
CONA#
BT_PRE#

27 DOT_PRES#

2
20 MUTE#

20

R479
10K_0402

VCC

20

+3VALW

8
7
6
5

8P4R_100K_0804

+5VALW

+3VALW
RP78

20

8
7
6
5

8P4R_100K_0804
+3VALW
RP77
1
2
3
4

8
7
6
5

14
KBA6

8P4R_100K_0804

SELIO#

U52D

12
11
13

3
4
7
8
13
14
17
18

D0
D1
D2
D3
D4
D5
D6
D7

EE
LARST#

11
1

CLK
CLR

10

74LVC32

FWE#
KBA17
KBA14
KBA13
KBA8
KBA9
KBA11
FRD#
KBA10
FSEL#
ADB7
ADB6
ADB5
ADB4
ADB3

5
1

4
2
3

+3VALW
1

2
G

+3VALW

+12VS

R408
100K_0402

FWR# 31

U39
8
7
6
5

7,31,41 EC_SMC1
7,31,41 EC_SMD1
FRD# 31

VCC
WC
SCL
SDA
NM24C16-27

A0
A1
A2
GND

1
2
3
4

8
7
6
5
4
3
2
1
32
31
30
29
28
27
26
25

1
100K_0402

R399
100K_0402

FSEL# 31

R375
100K_0402
4

VCC
WE*
A17
A14
A13
A8
A9
A11
OE*
A10
CE*
DQ7
DQ6
DQ5
DQ4
DQ3

74HCT273

Q49 2N7002
3
FLASH# 20

A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS

2
R442

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
KBA0
ADB0
ADB1
ADB2

1
R454
100K_0402

U49
7SH32

U54

PWR1_LED# 27
PWR2_LED# 27
BATT1_LED# 27
BATT2_LED# 27
PLED# 27
MP3_LED# 27
MUTELED 27
CDPLAY_LED# 27

+3VALW
+3VALW

1
.1UF_0402

2
5
6
9
12
15
16
19

2
C560

+3VALW

2
1
C556
4.7UF_10V_0805

U60
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

DOT_PRES#
BT_PRE#
BT_ON/OFF#
DRIVER_ACT#

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

VCC

1
2
3
4

GND

AA
CC
BB
TP_ON/OFF#

39F040_TSOP

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

32

of

44

Reset & PS2 & FAN CKT

+3VALW

+3VALW

+3V

+5VS
U42B
74LVC14

R405

330K_0402

1
1

14

U42C
74LVC14
6

14

+3VALW POWER

+5VS

JP20
RSMRST#

1
2
3
4
5
6
7
8

RSMRST# 20

C491

TP_ON/OFF#
TPAD_LED#

32 TP_ON/OFF#
32 TPAD_LED#

+3VALW POWER

.1UF_0402

TP_DATA
TP_CLK
1

31 TP_DATA
31 TP_CLK

R406
47K_0402

C171

1
2
3
4
5
6
7
8

A1
A2
A3
A4
A5
A6
A7
A8

A1
A2
A3
A4
A5
A6
A7
A8

TP_ON/OFF#
TPAD_LED#
TP_DATA
TP_CLK

C172
HEADER 8

@22PF_0402

+3VALW

C525

+5V
1
1

@22PF_0402

PWR ON CKT
2

+3V

.1UF_0402
R404
47K_0402
SPWROFF#

R403

14
1

330K_0402

5
2

6,11,20 CPUSTP#

U42A
74LVC14
+3VALW POWER
+3VALW

C495
.1UF_0402

7,10,19,20,31 PM_SLP_S1#

1
R205
1
R206

2
@0_0402
2
@0_0402

1
+3VS

1
R211

PWROK

2
0_0402

C543
2

.1UF_0402
+3VS

PWROK 9

U24
@7SH08

SPWROFF#

2 PWROK
@0_0402

4 1
R210

2
1
C548 .1UF_0402

+3VALW

MR#

VCC

14

PFI

RST#

C544

GND

PFO#

U48A
74LVC125
+3VALW POWER

MAX6342

R482
100K_0402

SPWROFF# 6,19,20,31
D35

R440
100K_0402

.1UF_0402

1
3

27 ON/OFFBTN#

ON/OFF

ON/OFF 31

51ON#

51ON# 27,41

.01UF_0402

SPWROFF#

DAN202U
1

R459

C570

R491
100K_0402

+3VALW

2.2M_0402

2
2 2

0_0402

22K
B

31 EC_ON

E
22K
Q58
DTC124EK

+12VS

D36
RLZ20A

FAN Connector

1000PF_0402
R487

C551

R467
100K_0402

6 G_VR_POK

U50

R464
113K_1%

+5VS
WHEN R=0,Vbe=1.35V
WHEN R=33K,Vbe=0.8V

R244
0

R227

D13
1N4148

32 GATE_RST

1 2SA1036K

1
2
3

1
C1

R1
10K_0402

1
2

U27
VEE LMV321_SOT23-5

+3VALW

SW1

3
2

+3VALW
JP14

2
.1UF_0402

U1
7SH32

FAN_CON_3P

4
2

EC_RST# 31

2
13K_1%

C344

3 Q29
4

1
R236

1SS355

5 VCC
1

EN_FAN

M/E OFF Button

D12

2.2UF_16V_0805

C346
31 EN_FAN

.1UF_0402
1
2

.1UF_0402

+5VS

C361

FMMT619
2

PIR(4) Q28

3.48K_1%

2
7.32K_1%

31 FANSPEED

RESET BTN

PIR(9)
4

1
R231

R2
10K_0402

35 ME_OFF#

Second FAN connector

PIR(13,32)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

33

of

44

DC/DC Interface & RTC

+5VALW

Q21
2N7002

Q41
2N7002

SYSON#

Q15
2N7002

SUSP

12

2
G

R84
1K_0402

D
Q14
2N7002

2
G

SUSP

D
1

Q16
2N7002

2
G

2
G

SUSP

12

2
G

R83
1K_0402

SYSON#

31 SYSON#

+2.5VS

Q22
2N7002

R85
470_0402

2
G

R397
@10K_0402

+3VS

SUSP

12

Q42
2N7002
S

R386
1K_0402

12

SUSP# 2
G

31,35,38,41 SUSP#

R151
470_0402

R153
1K_0402

SUSP

+3V

+5VS

+5V

+12VS
1

R392
10K_0402

+5V

+3VALW

+3V

C474

C176
4.7UF_25V_1206

1UF_25V_0805

Q43
SI3865

@.1UF_0402
R410
1
2

100K_0402

4.7UF_10V_0805

8936

C472

1
2
3
4

S1
G1
S2
G2

4.7UF_10V_0805

D1
D1
D2
D2

1UF_25V_0805

C502

+12VALW

+2.5V_CLK

1M_0402

R373

C475

R484
@1M_0402

C175
4.7UF_25V_1206

1
1

.01UF_0402
2

R414

C571
@.01UF_0402

6,31,40 VR_ON

ON_GATE

1
2
R483
100K_0402
Q59
D
2N7002
SYSON#
2
G
S

C579

4.7UF_10V_0805

8936

C184

8
7
6
5

+2.5VS
C501

4.7UF_10V_0805

1
2
3
4

S1
G1
S2
G2

C179

U40

D1
D1
D2
D2

U18
8
7
6
5

+2.5VS

+5VALW

+2.5VS To +2.5VCLK Transfer

+3VALW To +3V Transfer

+5VALW To +5V Transfer

0_0402
2

+5VALW To +5VS Transfer

+5VALW

+3VALW To +3VS Transfer

+5VS

+3VALW

C512

C511

10UF_10V_1206

10UF_10V_1206
2

10UF_10V_1206

C509

.1UF_0402

C510
10UF_10V_1206

4.7UF_10V_0805

R154
C537

.01UF_0402

D
R446

+5VS_GATE

+5VS_GATE

@330K_0402

1M_0402
2

S
3

@.1UF_0402

1
R452

2
100K_0402

+12VALW

2 SUSP
G
Q47
2N7002

C180

C523

8936
C532

4.7UF_10V_0805

1
2
3
4

C578
10UF_10V_0805

S1
G1
S2
G2

D1
D1
D2
D2

10UF_10V_0805

C572

C577
10UF_10V_0805

8
7
6
5

.1UF_0402

C178

C182
10UF_10V_0805

1
2
3
4

8936
C183

+3VS
U46

S1
G1
S2
G2

D1
D1
D2
D2

8
7
6
5

U16

+12VALW To +12VS Transfer

+12VALW

+12VS

ML1220

SUSP# 5

PIR(21)

R233
330_0402

D29
HSM126S
+RTCVCC

JOPEN7

0_0402

R152

2
100_0402

2
1

1
3

1UF_25V_0805
W=15mils 1
R424

1
R61
330_0402

CHGRTC

R186
330_0402

C181

W=15mils

+CPU_CORE

+VCPU_IO

100K_0402

+2.5V_CLK
BATT1.1

BATT1
D

1UF_25V_0805

RTC BATT

1
C569

1
2
Q57
@.1UF_25V_0805
SI3861
R489
1
2
4

C573

+12VALW

Q26
2N7002

2
3

Q25
2N7002

2
3

SYSON#

Q24
2N7002

W=15mils

C524

.1UF_0402

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

34

of

44

SPR CONN.

LPD[0..7]

19,28 LPD[0..7]

+5VS
VIN_1

10,14 BLUE
10,14 GREEN
10,14 RED
14 CRMA
14 LUMA
14 COMPS
26 DOCK_HP_OUT_PLUG
26 INTMICOFF#
26 LINEOUTR
26 LINEOUTL
26 DOCK_MIC
24 SPDIFO
30 RJ45_TXX+
30 RJ45_TXX30 RJ45_RXX+
30 RJ45_RXX28 USB1_D28 USB1_D+
19,28 OVCUR#0
31,32 CONA#

CONA#

ME_OFF# 33

PIR(42)

DOCK_DDCC 14
DOCK_VSYNC 14
DOCK_HSYNC 14
DOCK_DDCD 14
MSEN# 14,31
DCD1# 19
DSR1# 19
TXD1 19
RXD1 19
DTR1# 19
CTS1# 19
RTS1# 19
RI1# 19
RIA0 19

+5VS

+5VS

PS2_CLK
PS2_DATA
KBD_CLK
KBD_DATA

+5VALW

SPR@.01UF_0402
C220

C221

+5VALW
PS2_CLK 31
PS2_DATA 31
KBD_CLK 31
KBD_DATA 31

C41
SPR@22UF_16V_1206

C218
SPR@.01UF_0402

SPR@1000PF_0402

USB0_D- 28
USB0_D+ 28

101
102
103
104

EC_SMD2 4,23,31
EC_SMC2 4,23,31
SUSP# 31,34,38,41

8P4R_10K_0804

LPTSLCT 19,28
LPTPE 19,28
LPTBUSY 19,28
LPTACK# 19,28

LPD0

19,28 LPTAFD#
19,28 LPTSTB#

5
6
7
8

19,28 LPTERR#

LPD7
LPD6
LPD5

4
3
2
1

LPD1

RP4
PS2_CLK
PS2_DATA
KBD_DATA
KBD_CLK

LPD2

19,28 LPTINIT#

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100

19,28 LPTSLCTIN#

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100

LPD4
LPD3

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

SPR@100PF_0402
2

SPR@1000PF_0402

C20

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
102
103
104

C21

JP25

L11
1
2
SPR@FBM-L11-322513-151
1

VIN

SPR@DOCKING 100

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

35

of

44

Mini-PCI Slot

AD[0..31]

.1UF_0402

C382

C381

.1UF_0402

C378
1

10UF_10V_1206

1000PF_0402

C377

C390
10UF_10V_1206

.1UF_0402

C388

.1UF_0402

+3.3VAUX

C383

C389

10UF_10V_1206

1000PF_0402

C386

C380
10UF_10V_1206

.1UF_0402

C384

.1UF_0402

C385

1000PF_0402

C379

+3VS_MINIPCI

+5VS_MINIPCI

AD[0..31] 10,16,18,19,29

JP27

AD31
AD29

IDSEL :

R316
100_0402
2
AD31 AD31 1
10,16,18,19,29 CBE#3

AD27
AD25
LAN_IDSEL
AD23
AD21
AD19
AD17

10,16,18,19,29 CBE#2
10,16,18,19,29 IRDY#
CLKRUN#

10,16,19,31 CLKRUN#
10,16,19,29 SERR#

PCLK_MINI

16,18,19,29 PERR#
10,16,18,19,29 CBE#1

R287
10_0402

AD14

12

AD12
AD10
C391
AD8
AD7

15PF_0402
3

AD5
AD3
W=30mils

+5VS_MINIPCI

2 .1UF_0402

PIR(25)

24 MD_MIC
19 MODEM_RI#

+5VS

2 W=30mils

L47
FBM-11-160808-121

127

+5VS_MINIPCI

127

129

129

GNT#1

+5VS_MINIPCI
PIRQB# 19,29
+3VS_MINIPCI
GNT#0 10
+3.3VAUX
L48
PCIRST# 9,14,16,18,19,22,23,29,31
W=40mils
1
2
FBM-11-160808-121
GNT#1 10
MINI_PME# 31
LAN_PME# 31

R286 2
1
AD30 0_0402
AD28
AD26
AD24
MINI_IDSEL

1
R301

+3VS

AD27
2
100_0402

IDSEL : AD27

AD22
AD20
PAR 10,16,18,19,29

AD18
AD16

FRAME# 10,16,18,19,29
TRDY# 10,16,18,19,29
STOP# 10,16,18,19,29

2MM
PJP2

20mil

DEVSEL# 10,16,18,19,29

+12VALWP

+12VALW

(0.5A)

+5VALW

(2A)

+3VALW

(3A)

+2.5VS

(2A)

+VCPU_IO

(2.5A)

+1.5VS

3MM
PJP3

AD15
AD13
AD11

100mil

+5VALWP

AD9
3MM
PJP4

CBE#0 10,16,18,19,29
AD6
AD4
AD2
AD0

+3.3VAUX

+3VALWP

2
3MM
PJP5

100mil

R277
100K_0402

+2.5VP

2
3MM
PJP6

AC97_RST# 20,24

100mil

Q34

+VTTP

D
MD_SPK 24
the channel width 50 mils
W=40mils

+12VALW

NDS351
3
AC97_SDOUT 20,24

120mil

+3VALW
Q33

C594 1

1
1 22_0402
22_0402

PIRQB#
W=40mils
PCIRST#

1
15PF_0402
24 MOD_AUDIO_MON

2
R281 2
R280
+3.3VAUX

RING

2
C387

20,24 AC97_SYNC
20 AC97_SDIN1
20,24 AC97_BCLK

AD1

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

REQ#1

10 REQ#1

PCLK_MINI

11 PCLK_MINI

2
KEY
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

PIRQD#
W=40mils

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123

1
KEY
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123

2
G
2N7002

2MM
PJP9

EN_WOLR# 31
+1.5VP

19 PIRQD#
+3VS_MINIPCI
10 REQ#0

TIP

+3.3VAUX

Mini-PCI SLOT
DIGITAL GND

MINI_GNDA

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

36

of

44

USB HUB/BT/FPR

R372
R355
R350
R352

1
1
1
1

2
2
2
2

@0_0402
@0_0402
FN_0_0402
FN_0_0402

+HUBVCC
L54
2
1
F@HB-1M2012-121JT+5VS
C467
1
2

VERG
R374

F@.1UF_0402

+5VS

F6MHZ

10

SP/BP#

17

RESET#

15

XTAL1

16

1
32

DP4
DM4

9
8

DP5
DM5

21
20

FP_USB1_D+
FP_USB1_DBT_USB2_D+
BT_USB2_D-

1
2
3
4

F@8P4R_33_0804

Bluetooth Connector

CP9

RP45

F@8P4C_47PF

F@8P4R_15K_0804

JP15
32 BT_DET
32 BT_WAKE_UP
BT_USB2_D+
BT_USB2_D-

L44
L45

1
1

RP57
XTAL2
VREG(3.3)
INDV/SDA
OPTION/SCL

3
4
5
6
7

OC1#
OC2#
OC3#
OC4#
OC5#/GOC#

29

1
2
3
4
5

VERG

GND

19
18

PSW1#/GL1#
PSW2#/GL2#
PSW3#/GL3#
PSW4#/GL4#
PSW5#/GL5#/GPSW#

31

+5VS

RP47

4
3
2
1

DP3
DM3

1
2
3
4

DP2
DM2

27
26

8
7
6
5

28
30
12
13
14

10
9
8
7
6

1
3
5
7
9
11
13
15
17
19

2 BT@FBM-11-160808-121
2 BT@FBM-11-160808-121
32 BT_RST#

VERG
+3VALW
1

2
F@10K_0402

HUBGL#

23
22

2
4
6
8
10
12
14
16
18
20

BT_ON# 27,32
BT_PRE# 32

+5VALW

BT@AXK5F20535P
C100

F@10P8R_100K
BT@.1UF_0402
2

11

DP1
DM1

5
6
7
8

DP0
DM0

8
7
6
5

R339

VCC

25
24

28 USB3_D+
28 USB3_D-

F@1.5K_0402
U38

F@ISP1122BD

Finger Printer Connector

3

+3VS

2
C169

1
F@.1UF_0402
JP18

+5VS
L26
L27

1
1

2 F@FBM-11-160808-121
2 F@FBM-11-160808-121

FP_USB1_D+
FP_USB1_DR329

OSC1

C453

VDD
ST

F@FINGER_4PIN

R344
OUT

GND

F6MHZ
F@33_0402
1

F@10K_0402

1
2
3
4

F@OSC_6MHZ

C455

F@22PF_0402
2

F@.1UF_0402

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

37

of

44

5V/3V/12V
+5VALWP
PC100
2.2UF_0805_16V

B1+

B1+
PR125
11.5K_1%

PC126
0.1UF_0805_25V

B1+

0.1UF_0805_25V

FBM-L11-322513-201LMAT
DAP202U
PD27

VL
8
7
6
5

OUT1_D

26

OUTGND1

23

24
VCC

TRIP1

TRIP2

LL2

18

OUT2_D

19

OUTGND2

20

PR124

3VDH

G
S
S
S
4
3
2
1

INV2

FB2

PQ30
SI4810

PC115
@1000PF

15

PGOD

SOFT2

14

13

12

STBY2

STBY1

SCP
11

10

GND

5V_STBY

REF
8

SKIP/PWM #

CT
5

SOFT1

3VDL

57.6K_1%

PR113
330

PR118
330

PC121
47UF_D_6.3V_SP

PZD8
RLZ6.2C

PC106
47P

VL

PC88
150UF_D_6.3V_FP

PC110
2200P

PC107
0.1UF_16V

PR114
11.5K_1%
0.85VREF

PC108
10P

+3VALWP
1

PC113
4700P

PD29
EP10QY03

+3VALWP

PC109
0.01UF

PZD9
RLZ4.3B

PC104
2200P

PR121
220

PC103
3300P

PD26
EP10QY03

PR111
430

MAINP

+3VALWP
+

0.85VREF

+5VALWP

1
SPC-100M

SCP

PC89
@47UF_D_6.3V_SP

PR120
33.2K_1%

+5VALWP

PR103
75_1%
PC86
4.7UF_1206_16V

17

PR110

Vout

JOPEN9
2

INV1
1

3
2

25

4
3
2
1
LL1

27

FB1

1
2
3
4

S
S
S
G

5VDL

PU7
AMS2906-SOT-89

Vin
1

OUT2_U
PU8

28

PR123

TPS5120
PQ28
SI4810

ADJ

21

OUT1_U

PL13
3VSW

16

LH2

PC97
@1000PF

JOPEN8

PC117
@4.7UF_1210_25V

5
6
7
8

29
PR108

D
D
D
D
PT1
10UH-SDT-1205P

PC95
2.2UF_1206_25V

PQ29
SI4800

D
D
D
D

8
7
6
5

LH1

5VDH
2

REG5V_IN

22
30

VREF5

5VSW

PR107
PD24
EC11FS2

PC114

G
S
S
S

S
S
S
G
1
2
3
4

PC96
0.1UF_0805_25V

PC102
0.1UF_0805_25V

PC99
4.7UF_1206_16V

0.1UF_0805_25V

SNB1

PR106
22_1206

15K_1%

PQ27
SI4800
PC92
4.7UF_1210_25V

PC118
2200P

D
D
D
D

D
D
D
D

PR126

PC94
470PF_0805_100V

+12VALWP

PC116
4.7UF_1210_25V

PC101

5
6
7
8

PC93
4.7UF_1210_25V

B+

PC91
0.1UF_0805_25V

PL12

PC120
150UF_D_6.3V_FP

PR112
100K

PR117
11.5K_1%

PR122
@100K

MAINP
PR104
PR210
@0
PC105

+5V : 6.81A ~ 9.03A

1
2

31,34,35,41 SUSP#

PC112

100K

PC111
0.01UF

+3.3V : 9.22A ~ 12.13A

PQ31
DTC115EUA
3

CPU thermal protection at 85 degree C

.047U_16V

PR115
150K

PR154
100K

100K

0.01UF

VS

649_1%

VL
1

PC73
0.1UF_16V
39,42 PACIN
1

VL

PACIN2
G

VL

PQ33
2N7002

VIN

S
PC136
0.1UF_0805_25V
3

SCP

PR75
47K_1%

PR72

PQ38
TP0610T

MAINP

1
MAINP

PR153
330
VL

PU9A
LM393M

RTCVREF

100K_1%

PR157
100K

PR76

VL
PQ39
2N7002

2
G
S
1

1000P

PC75
0.22UF_0805_16V

PH1
10K_1%_0805

PR156
@100K
PC74

VL
PR152
10K

PR74
16.9K_1%

PR77
100K_1%
PQ40
2N7002

2
G
S
3

PR73
47K_1%

2.15K_1%

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

38

of

44

Charger

Iadp=0~2.60A
Air-line:50W
B++
P3

PQ11
FDS4435

2
1

PC37
2200P

PC35
4.7UF_1210_25V

8
7
6
5

PC34
4.7UF_1210_25V

1
2
3

8
7
6
5
4

PR20
10K

1
2
3

PL3
FBM-L11-453215-900LMAT

PR24
0.02_2512_1%

1
2
3

8
7
6
5

GND

23

3
2
1

OUTC2

+INC2

VIN

PR135

24

ACOFF#

-INC2

PR34
0

PU3
MB3878
1

PC36
@0.1UF_0805_25V

PR38
47K

PR21
200K

PQ9
SI4835DY

VIN

B+

P2

PQ8
SI4835DY

1
PR25
100K

+INE2

CS

22

-INE2 VCC(o)

21

FB2

OUT

20

VREF

FB1

-INE1

VH

19

VCC

18

RT

17

PC39
0.1UF_0805_25V
PC40
0.1UF_16V
1
2

PR27
1K

1
1

+INE1

-INE3

16

10

OUTC1

FB3

15

11

OUTD

CTL

14

PC41
0.1UF_0805_25V
2

31 FSTCHG

PL14
SPC-220M

PR35
68K

1
PR28
10K

PC45
4.7UF_1210_25V
2

VMB

PR36
330K

PD12
EA60QC04

PC42
1500P

PC135
0.01uF
2

PC43
68UF_EC_25V

+
2

PR33
768K_1%

PR39
0.02_2512_1%
1
2

1M_1%

PC32
2200P

31 IREF

PR32
1

PD33
1SS355

PR30
@24.9K_1%

LXCHRG

ACOFF 31

2
PR26
10K

2
PQ13
DTC115EUA

100K

PC31
4700P

ACOFF#

100K

PC33
0.1UF_16V

PQ12
FDS4435

PR31
10K_1%

2
G

PC38
2200P

PQ10
2N7002

PR29
28K_1%

PACIN 1

38,42 PACIN

PR207
47K

PC134
0.1UF_16V

5
6
7
8

PR22
150K

1
12

IREF=1.151*Icharge
IREF=0~3.3V
Set charge current 2.86A for LI-ION
Set charge current 2A for NI-MH (SPEC. ---> 2.5h)

-INC1

+INC1

PR37
10K

13

PC44
4.7UF_1210_25V

PC133
56PF
+INC1
-INC1

BATT+
1

+3VALWP

PR149

+3VALWP

2
1

PC125
22PF

300K_0.5%
+

Charge voltage :
1

PR147

LI-3S : 13.2V

VL

PR43
100K

LI-4S ( NI ) : 17.4V

PC138
0.1UF_16V
PQ15
DTC115EUA

PC132
0.01UF

100K_0.5%

4
2

PC131
2.2UF_0805_16V

1
PR41
316K_0.1%

31 AVBATT

PR42
316K_0.1%

PU9B
LM393M

10K

3
PQ14
2N7002

PR146

RB751V

PD32
PR144

PR40
147K_0.1%

324K_0.5%

PR148

100K

36.5K_1%
2

ALI/MH# 31,41

LI-3S/LI-4S(NI)# 31,41

100K

2
G
PQ34
2N7002

LI-3S/LI-4S(NI)#

LI-3S:0.1794*BATT+ = AVBATT
LI-4S(NI):0.1381*BATT+ = AVBATT
4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

39

of

44

CPU_CORE
+3VALWP

PR158
100K

PR159
100K

PR160
100K

PR161
100K

PR162
100K

COREB+

B+
4.7UF_1210_25V

4.7UF_1210_25V

2200P
1

COREB+
PC152

PC153

PC154

PC155

PC156

PC157

4.7UF_1210_25V

PR171
180K_1%

2VREF
PC147
1U_0603_10V

PR172
249K_1%

V+
VCC

VGATE

TIME

SDN/SKIP

17
6

FB

VDD

3
2
1

PL18
0.9UH_25A_LPI

+CPU_CORE

1
PR182
3mR

PD37
EP10QY03

PD35
EC31QS04

+5VALWP

PC149
0.1UF_0805_25V

POS

13

NEG

ZMODE

19

OVP

SUS

18

11

REF

S1

12

ILIM

S0

GND

TON

15

PQ45
SI4362DY

20

CC

PC150
4.7UF_0805_10V

PC175
1U_0603_10V

2
PR188
100

PC151
@2200P

PR186
0

PC161
1000PF

PU12
2

PR183
510_1%

D0

14

PC148
0.1UF_0805_25V
COREDL
4

2
PR178

25

16

26

DL

PQ44
SI4362DY
5
6
7
8

BST

D1

PQ43
SI4362DY

4.7UF_0805_10V
PC146
470PF_0603

D2

0
2

5
6
7
8

24

PR177

+ 3

- 4

DPRSLPVR 7
PR187
1K_1%

FB
1

ZMODE

1
PR185
1K_1%

PC145

28

PR181
3mR

3
2
1

PR170
150K_1%

1
51K

LX
DH

5
6
7
8

23

CORELX

27

PU10

3
2
1

1
D3

1
PR169

6,31,34 VR_ON
PC176
0.047UF_16V

D4

22

2
2

MAX1718
21

PR168
10K

PD34
RB751V

3
2
1

PR163
0

+3VALWP

PR164
0

7 CPU_VID0

PR175
20

PR166
0

PR165
0

+CPU_CORE
PL17
@ESPI-1206-1R0M

7 CPU_VID1

PR176
0

PR167
0

7 CPU_VID2

COREDH 4

7 CPU_VID3

PQ42
SI4892DY

7 CPU_VID4

5
6
7
8

PQ41
SI4892DY

PC143
PC144
@4700PF @4700PF

3
2
1

PC142
@4700PF

@0.1UF_0805_25V

5
6
7
8

+5VALWP

VGATE 6

2
1

4.7UF_1210_25V

4.7UF_1210_25V
PC141
@4700PF

PR202
10K

PL15
FBM-L11-322513-201LMAT

PC158

PC140
@4700PF

PR184
604_1%

MAX4322

NEG

10

POS
PR179
@0

+3VALWP

2
PR174
0

PU13

PR180
0

10

NO2

V+

NO3

COM

NO1

NO0

INH

ADDA

GND

ADDB

PR173
274K_1%

2VREF

PC162
1U_0603_10V
1

VR_HI/LO# 6,7
OUTPUT

VOLTS

1
2

MAX4524

PR189
10K

D3

D2

D1

D0

D4 = 1

D4 = 0

10K

PR194
@604K_1%

PR191
61.9K_1%

H_DPSLP# 4,20

0.975

1.75

0.950

1.70

10K

PR192
19.6K_1%

PQ47
DTC114EUA

PR193
16.2K_1%

MODE
DEEPER SLEEP
BATTEY SLEEP
PERFORMANCE SLEEP
BATTERY MODE
PERFORMANCE MODE

OFFSET
0mV
-56mV
-51mV
-16mV

RBOTTOM
X
16.2K
19.6K
61.9K

Vout(0A)
0.850
1.083
1.332
1.131
1.400

ADDA
X
1
1
0
0

ADDB
X
0
1
0
1

0.925

1.65

0.900

1.60

0.875

1.55

0.850

1.50

0.825

1.45

0.800

1.40

0.775

1.35

0.750

1.30

0.725

1.25

0.700

1.20

0.675

1.15

0.650

1.10

0.625

1.05

0.600

1.00

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Date:
G

Sheet

40
H

of

44

Connector/2.5V/1.5V
VIN
+3VALWP
2

PR136
10_1206

ADPGND

PC72
1000P

VMB

PF1
7A SLOW

PCN2

BATT

31,39 LI-3S/LI-4S(NI)#

B/I
+3VALWP

TS

PZD2
RLZ24B

PL9
@FBM-L11-453215-900LMAT

SLD
SLC

PR83 25.5K_1%

3
3

JOPEN6

PL10
FBM-L11-453215-900LMAT

15K
PR82
1K

PC71
100P

SINGATRON 2DC-S026B301

2
1

BATT+

PR81

1000P

ADPIN

PL8
FBM-L11-453215-900LMAT

PC70
1000P

3MM-NEW
PD20
@BAS40-04

PR93
1K

2
2

PC80
0.01UF

PD21
@BAS40-04

1
2
3
4
5
6
7

BATT CONN.

PR84

PC81

PC69
100P

PD17
BYS10-45

PCN1

1K

31 ABATT_TEMP
+3VALWP
3

RLS4148

7,31,32 EC_SMD1

VS

+3VALWP
1

PQ21
TP0610T
3
1

100

PD22
@BAS40-04

PD19

CHGRTCP 2

PR85

2
2

VMB

VIN

PD18
RB751V

3
1

100

PD23
@BAS40-04

PC77
0.1UF_0805_25V

PR78
100K

27,33 51ON#

PR86

PZD3
RLZ4.3B

7,31,32 EC_SMC1

2
PR79
22K

PC76
0.22UF_1206_25V

CHGRTCP
RTCVREF

2
1

PQ35
TP0610T
3
1

PC78
4.7UF_1206_16V

Sense

+3VALWP
PZD4
RLZ16B
1

+5VALWP

+2.5VP

Output

Control

Adjust

PC84
10UF_1210_16V

PC82
10UF_1210_16V

Vpower

PR94
200

PU6
AMS1503

RTCVREF

CHGRTC

200_0805

PR80

PU5
S-81233SGUP

PU11
Vin Vout
GND Adj
EN
PG

6
5
4

+1.5VP

PC122
0.1UF_0805_25V

1
2
3

+3VALWP

PR150
68

PR151
100K

PR198
10K_1%

AME8804AEEY

100K

31,34,35,38 SUSP#

PQ36
DTC115EUA

100K
3

PC166
2.2UF_0805_16V
PR197
42.2K_1%

PC165
4.7UF_0805_10V

PC79
1UF_0805_25V

31,34,35,38 SUSP#
PR201
0

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

41

of

44

VTT
PQ7
SI3445DV

+VTTP

1
1

PR139

VL

4
1
0.85VREF

VTT_PWRGD# 4,11,31

PC130
1000P

PR138
5.6M

PR200
47K

PC29
4700P
VL

0.85VREF

2
+

PR199
10K

PR141
10K_1%

PU2A
LM393M

10K

PU2B
LM393M

PR18
11.8K_1%

PC163
0.1UF_16V

2
PC28
4700P

PC128
0.1UF_16V

1
PR16
10K

1
3

3
PQ5
2SA1036K 1

PC30
220UF_D_4V_FP

PQ6
PR15 HMBT2222A
1K
1
2
2

+3VS
+

PC164
470P

PD7
RB751V

PC27
10UF_1210_16V

PR17
5.62K_1%

PR195
2M

PD8
RB051L-40

+1.25V +-5%

PL2
5uH-SPC-06704
1
2

LX125

6
5
2
1

+3VALWP

PR142
19.6K_1%

1
PD36
1SS355

PR196
100K

PR143
100K_1%

PC129
0.22U_0603

+VTTP

100K

100K

PQ48
DTC115EUA

VTTP=1.021V------>VTT_PWRGD:"L"

100K

VTT_ON 31

VTTP=1.014V------>VTT_PWRGD:"H"

PQ49
DTC115EUA

VIN detector
16.90
17.55
16.46
17.08

100K

18.22
17.72

Detector
PR208
1M_1%
1

VIN
2

VS

VIN

2
1

PR129

PR209
82.5K_1%

PU14A
LM393A

ACIN 27,31

10K

10k

PACIN

1
1

2
1

PC178
0.1UF_16V

PACIN 38,39

1
1

2
2

1
PR204
10K

PZD5
RLZ3.6B

PR128
10k

PR205
20K_1%

1 ACIN

PR127

2
8

PR206
22K
1

PC179
1000PF

PC177
0.01UF

PU14B
LM393A

RTCVREF

3.3V
7

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date:
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044
Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

42

of

44

For C1-test
1.Solving can't boot-up issue.
Pull-high(R492;200 ohm) ITP_PREQ# to +VCPU_IO.

Voltage Rails
Power Plane

Description

S1

S3

S5

2.For solving high voltage test fail issue.

Change C219,C213 from 1000P_2KV_1206 to 220P_3KV_1808.

VIN

Adapter power supply (19V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

+CPU_IO

1.25V switched power rail for CPU AGTL Bus

ON

OFF

OFF

+1.5VS

1.5V switched power rail

ON

OFF

OFF

+2.5VS

2.5V switched power rail for TwisterT(VT8606) core power.

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+3V

3.3V power rail

ON

ON

OFF

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5V

5V power rail

ON

ON

OFF

+5VS

5V switched power rail

ON

OFF

OFF

+12VALW

12V always on power rail

ON

ON

ON*

+12VS

12V switched power rail

ON

OFF

OFF

RTCVCC

RTC power

ON

ON

ON

3.To avoid the chipset enter an unpredictable state.(VIA's recommend by AN198)

Add two 1K ohm pull-high resistor at R217,R222.

4.Change Q28 from 2SC2411EK(P=0.2W) to FMMT619(P=0.625W) for increasing

system reliability.
5.For solving Microphone noise issue.
Change C372 from 0.1uF to 0.01uF.

6.For solving 1.06GHz QS CPU speed detect incorrect issue.

Add Q60 2N7002
Add Q61 DTC124EK
Add R494 100K_0402

7.Exchange Q11.1 and Q11.3 for solving external MIC. can't be disable on docking
side.

8.Cahnge R35,R37 from TV@4.7K_0402 to 4.7K_0402 for solving B3C082.

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

9.For solving ESD fail issue.

Exchange SW1.1,SW1.3 with SW1.2,SW1.4

10.For solving EC can't resume from idle mode issue.

External PCI Devices

Device

IDSEL#

Mini-PCI

AD27

REQ#/GNT#
0

PIRQB#

Mini-PCI(LAN)

AD31

PIRQD#

LAN(RTL8100)

AD24

PIRQB#

CardBus(CB1410)

AD15

PIRQA#

IEEE-1394 Controller

AD25

PIRQC#

Add D37 and D38.(RB751V)

Interrupts

11.For EMI requirement.

Add CP4,CP5 8P4C_100PF.

12.For solving audio sound can't be muted issue.

Del Q48,Q50,Q51,Q52,Q53,Q54,Q55,R455.
Add U62(74HCT4066),C583(0.1UF).

13.Reserve for second FAN.

EC SM Bus1 address
Device

Add JP29,C584(0.1UF),D39(1N4148),Q62(NDS351),R495(0_0402).

EC SM Bus2 address

14.For solving SDRAM clock timing can't meet PC133 specification issue.
Del R234,R121,R325,R104,R68,R80
Del C345,C166,C427,C150,C105,C129

Device

CPU voltage Mux

0110 1110 b

MAX1617MEE

1001 110X b

Smart Battery

0001 011X b

OZ163

0011 0100 b

EEPROM

1010 000X b

Docking

0011 011X b

15.For solving the record sound is much weaker issue.

Add U63(TDA1308)
Add R496(100_0402)
Add R497(10K_0603_1%)
Add R498(22K_0603_1%)
Add C588(0.1UF_0402)
Add C590(0.22UF_0603)
Add C591(15PF_NPO_0603)
Add C586(1UF_0603)
Add C587(0.1UF_0402)
Add C589(1UF_0603)

P.S:Default Resistor & Capacitor's package are 0603.

Default 8P4R package is 0402.
4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
A

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044

Size
Custom

Date:

Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

43

of

44

16.For solving Celeron-T CPU can't power on issue.(Celeron-T SKU only)

Del JP29,C584,Q62,D39,R495.

33.For solving wake up from Ring failure issue.(To divide On-board LAN and
MINI-PCI card's AUX. power plan for saving power consumption.(2001/10/11)
34.Reserve R507(@0_0402) for BIOS team request.(2001/10/17)
35.SDRAM skew didn't met specification.(2001/10/17)

17.VIA recommend.It can increasing +VCPU_IO power plan noise immunity.

Add C592(1000PF_0402)
Add C593(.1UF_0402)

Add R234(10_0402),C345(15PF_0402).

18.To change CardBus power switcher from CP2211(ENE) to TPS2211(TI).

Add U64,U65(7SH08FU).
Add C595,C596(.1UF_0402).

Del R196(137_1%_0402)
Change R194 from 26.7_1%_0402 to 0_0402.

37.For solving Celeron-T 933MHz CPU reboot fail issue.(2001/10/24)

20.To change clock generator from ICS950602 to CY28317 for solving system up
issue.
21.Change RTC battery from VL1220(Panasonic) to ML1220(Maxell) for purchase
policy.
22.Intel recommend that change +VS_CMOSREF voltage divider from 1K/2K to
510/1K.

Add R250(10_0402),R232(0_0402)
Add C598(1UF_0603) for Celeron-T SKU only.
Del R249,R314
Change R208 from 56.2_1%_0402 to 1K_0402.

38.To correct pull-up resistor error.(2001/10/24)

Del R290(1K_0402)
Add R508(4.7K_0402),R391(4.7K_0402)

39.For solving internal microphone echo issue.(2001/10/24)

Change R230 from 1K ohm to 510 ohm.

Change R235 from 2K ohm to 1K ohm.

Change R498 from 22K_1% to 12K_1%.

23.EC team change their SPEC. for support dock-on to wake up EC(591).

40.For solving PCIRST# from VT8231 has glitch issue.It causes system cold
boot from LAN failure.(2001/10/24)

Add D40.

24.Add a pull high resistor(R500,47K ohm) for solving cardbus card can't be
detected.

Add U66(7SH08FU)
Del R298.

41.Change JP22.1 & JP22.2 's power plan from +3VS to +5VS for increasing IR
transmission distance.

25.For solving audio noise from PHONE channel.

Add C594,0.1UF_0402.

26.For EMI team requirement.

For MP(REV1.0)

1.Change R256,R252,R240,R239 from 0_0402 to 22_0402.

2.Change R246,R238,R247 from 0_0402 to 10_0402.
3.Change R257,R245,R251,R253 from 0_0402 to 33_0402.
4.Change RP9~RP13,RP17~RP20,RP24~RP26,RP32~RP34,RP36.

42.For solving system auto re-start while system hot dock to SPR.
Disconnection JP25.38 and JP25.42

43.EC team request.

27.For solving c-test unit can't power-on issue.(2001/9/20)

Delete D40.

Change net "EC_MUTE#" to "EC_MUTE_L".

Change R481 from 10M ohm to 0_0603.

36.For solving IDE bus reset incorrect issue.(2001/10/18)

19.To change 133MHz from +-0.25% center spread to -0.5% down spread.

32.Delete second FAN circuit unnecessarily in all of SKU.(2001/10/11)

Add Q63(FDV301N)
Add R499(1.5K_0402)

For MP(REV2.0)

28.For Intel PMU SPEC. and SKU change.(2001/9/25)

44.For solving CD-Play board abnormal issue.

1.)For all SKU.

Del R79(1.2K_0402)
Del C116(1UF_10V)
Del U11(7SH32)
2.)For Tualatin SKU only.
Stuff R78,C118,U9,R493,U10,R349
3.)For Celeron-T SKU only.
Stuff R501

Change R505 from 1.5K_0402 to 10K_0402.

Change R506 from 1K_0402 to 10K_0402.
Change Q65 from FDV301N to 2N7002.

29.Increasing LANVDD power plan noise immunity.(2001/9/25)

Add C187,C191,C217(.1UF_0402)

For C2-test
4

30.BIOS can't support C4 and deepper sleep mode,so delete unnecessary components
for all of the Tualatin CPU SKU.(2001/10/11)

Del U9,U10,R493,U12,C117,R74,R76,R72,RP21,R78,C118.
Add R501(0_0402),R502(0_0402),RP79(8P4R_0).

31.Build two sets level shifter for solving CD-player board unstable issue.(2001/10/11)
Add Q64,Q65(FDV301N).
Add R503,R505(1.5K_0402).
Add R504(100K_0402).
Add R506(1K_0402).
A

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
B

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1044

Size
Custom

Date:

Document Number

Rev
2A

401196
, 17, 2002

Sheet
E

44

of

44