entity mux is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; s : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC); end mux; architecture

Muxes of mux is begin y<= a when s="00" else b when s="01" else c when s="10" else d; end Muxes; ++++++++++++++++++++++++++++++++++++++++++++++++++++ entity mux is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; s : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC); end mux; architecture Muxes of mux is begin multiplexor: process(a,b,c,d,s) begin if s = "00" then y <= a; elsif s="01"then y <= b; elsif s="10"then y <= c; else y<=d; end if; end process; end Muxes;

entity mux is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; s : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC); end mux; architecture Muxes of mux is begin multiplexor: process(a,b,c,d,s) begin case s is when "00" => y <= b; when "01" => y <= a; when "10" => y <= c; when others => y<=d; end case; end process; end Muxes;

CREACIN DE VARIABLES

entity XNOR2 is port (A, B: in std_logic; Z: out std_logic); end XNOR2; architecture behavioral_xnor of XNOR2 is -- signal declaration (of internal signals X, Y) signal X, Y: std_logic; begin X <= A and B; Y <= (not A) and (not B); Z <= X or Y; End behavioral_xnor;

REGISTRO DE 8 BITS ESTRUCTURAL entity Registro is Port ( A : in bit; B : out bit; reset : in bit; clock : in STD_LOGIC); end Registro; architecture Behavioral of Registro is begin process(reset,clock) begin if reset='1' then b <= '0'; elsif clock'event and clock='1' then b <= a; end if; _______________ LA ARQUITECTURA DEFINICIN CON Y SIN FOR
entity regstruct is Port ( entrada : in bit_VECTOR (3 downto 0); salida : out bit_VECTOR (3 downto 0); reset : in bit; clock : in STD_LOGIC); end regstruct; architecture Behavioral of regstruct is component registro Port ( A : in bit; B : out bit; reset : in bit; clock : in STD_LOGIC); end component; -- signal cables1: std_logic; begin -U0: REGISTRO port map (entrada(3),salida(3),reset,clock); -U1: REGISTRO port map (entrada(2),salida(2),reset,clock); -U2: REGISTRO port map (entrada(1),salida(1),reset,clock); -U3: REGISTRO port map (entrada(0),salida(0),reset,clock); laso: for i in 0 to 3 generate u: registro port map(entrada(i),salida(i),reset,clock); end generate laso; B <= F;

--

end Behavioral; end Behavioral;

MEMORI

entity MEMORIA is Port ( direccion : in STD_LOGIC_VECTOR (1 downto 0); indata : in STD_LOGIC_VECTOR (3 downto 0); clk : in STD_LOGIC; rdwr: in STD_LOGIC; outdata : out STD_LOGIC_VECTOR (3 downto 0)); end MEMORIA; architecture Behavioral of MEMORIA is subtype RegSize_type is integer range 0 to 3; subtype datatyp is std_logic_vector (3 downto 0); type reg_typ is array (RegSize_type) of DataTyp; signal mireg: reg_typ; begin process begin wait until clk'event and clk='1' ; if rdwr='0' then mireg(CONV_INTEGER(direccion))<= indata; end if; end process; outdata<= mireg(CONV_INTEGER(direccion)); end Behavioral;

entity contload is generic(lim_max:integer:=2500000); Port ( --load : in STD_LOGIC; clock : in STD_LOGIC; -- datos : buffer STD_LOGIC_VECTOR (3 downto 0); salidas : out STD_LOGIC_VECTOR (3 downto 0)); end contload; architecture Behavioral of contload is signal clock_hz: std_logic; --signal mi_dato: std_logic_vector (3 downto 0):=x"0"; begin uno: process(clock) variable contador: integer range 0 to 2500000; begin if clock'event and clock='1' then contador:=contador+1; if contador = lim_max then contador:=0; clock_hz<= not clock_hz; end if; end if; end process uno; process(clock_hz) variable mi_dato: std_logic_vector (3 downto 0); begin if clock_hz'event and clock_hz='1' then mi_dato:=mi_dato+1; if mi_dato="1111" then mi_dato:="0000"; end if; end if; salidas<=mi_dato; end process; end Behavioral;