MR.

IRFANKHORAKIWALA

NITESHKUMARSINGH PRABHANSHUSHARMA SHUBHAMSAH TRIVENDRAJOSHI

1

Multilevelinvertersareoperatingwithlowfrequencyand presenthighefficiencythanPWMinverters,becauseoflow switchinglosses. HBridgeinverterhassignificantadvantageoverothermulti levelinvertertopologies. Thisprojectworkinvolvesthehardwareimplementationof twolevelcascadedinverterwiththeeliminationof3rd and 5th harmonicsusingmicrocontroller(P89V51RD2).

May12,2013

Todevelopasystemwhichismoreefficientandcost effectiveever. Projectparticularthroughustoapractical understandingofthedevicesandcomponentswe havestudiedearlier. Andachancetoenhanceandputourknowledge& experiencestouse.

May12,2013

Initiallythecircuithasbeensimulatedin MULTISIM(NI NationalInstrumentation) software. Afterthesuccessfulsimulationthehardware implementationisdone. Fourieranalysishasbeenmadetoeliminatethe3rd and5th harmonics. Theswitchingsequencesarecalculatedsoasto equallyutilizealltheMOSFETsanddcsources.

May12,2013

 MOSFET(IRF630FP)isusedaspowerswitching device. Eliminationof3rd and5th harmonicsusingmicro controller(P89V51RD2). Optocoupler(4pinDIP817B)isusedtoovercome thecommongroundproblemandalsotogivethe sufficientgatedrivingvoltage.

May12,2013

 BasicschematicoftwolevelHBridgeInverterusingMOSFETswitch

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+2V +V 0 -V -2V

Thepreviouscircuitcanproducefivedifferentlevelsofoutputvoltage. Bymodulatingtheswitchescorrectlywecanproduceasteppedsine waveformasshownintheabovefigure. Theoutputvoltagecontains+V,+2V,0,V&2Vvoltagelevels.

May12,2013 7

+2V +V 0 -V -2V Va +V

AftertheFourierseriesanalysisand harmonicseliminationtheoutput waveformofthesystemisshownin figure,i.e.voltageoutputVb. outputwaveofamultilevelinverter canviewedasthesummationof squarewaveshavingdifferent conductingangles. Theconductinganglesa1anda2 can bechosensuchthatthetotal harmonicdistortionoftheoutput voltageisminimized.
8

-V Vb

+V

-V
May12,2013

 PowerMOSFETIRF630FP

o o o o

ManufacturedbySTMicroelectronics. AnNChannel,200V,9AMOSFET. ONstateresistanceof0.35Wonly. ItsturnON timeisonly34nsanditsturnOFF timeis70ns.

9

May12,2013

10

 817Boptocouplerina4pindualinlinepackage. Pindescriptionisshownrightaboveatright. ThemaximumVce0 thatcanbeappliedis70V. Itcansustainacontinuouscollectorcurrentof50mA. Themaxrisetimeandfalltimeare18ms atloadresistanceof100W.

May12,2013

11

May12,2013

12

Step1st :Switchingtimingcontrol. Inputdesiredvoltageandconnectionsisfedtothemicrocontroller80C51. Port0ofthemicrocontrollerissoprogrammedtoswitchtherequired MOSFETSindesirableconductionanglesandtiming. Step2nd :AC.Generation&HarmonicsElimination. Twodifferentalternatedswitchedoutputsarecascadedtoproducefivelevel ofvoltageoutput. FivelevelACoutputisbeingproducedbyswitchingofMOSFETSand undesirablelowlevelharmonicshasbeenremoved. Step3rd :Result/Observation. TheoutputobservedatoutputofthesecondstepisthenfedtotheCROand theoutputisthenobserved. Theobservedoutputwaveformcanbeseenthatthelowerorderharmonics hasbeensuccessfullyeliminated.

May12,2013

13

 CanbeusedtoproduceACforhomeorindustrial
uses,(wherepureSINEWAVEisnothardlyrequired). Furtheradvancementsanddevelopmentscanbe done. Canbeusedinlaboratoriesforresearchpurpose.

May12,2013

14

May12,2013

15

A PROJET REPORT ON

IMPLEMENTATION OF TWO LEVEL CASCADED INVERTER ADVANTAGES & APPLICATIONS

submitted for the partial fulfilment of the award of Degree of Bachelor of Technology In Electronics & Communication Engineering From Uttarakhand Technical University, Dehradun

Submitted by: Shubham Sah Nitesh Kumar Singh Prabhanshu Sharma Trivendra Joshi 0009070102122 0600701021051 0600701021053 0600701021054

Under the Guidance of: Mr. Irfan Khorakiwala (Lecturer)

Department of Electronics & Communication Engineering Dehradun Institute of Technology Dehradun, (May 2013)

IMPLEMENTATION OF TWO LEVEL CASCADED INVERTER ADVANTAGES & APPLICATIONS

Dehradun Institute of Technology Mussoorie diversion road Village, Makkawala Dehradun, 248009

Department of Electronics & Communication Engineering

CERTIFICATE
This is to certify that the project work entitled Implementation of two level cascaded Inverter, Advantages & Applications have carried out by Shubham Sah, Prabhanshu Sharma, Nitesh Kumar Singh and Trivendra Joshi in partial fulfilment for the award of Bachelor of Technology final year in Electronics & Communication Engineering from Uttarakhand Technical University, Dehradun, under the supervision of Mr Irfan Khorakiwala during the year 2012-13. It is also certified that all corrections/suggestions mentioned in internal assessment have been incorporated in this Report submitted. The project report has been approved as it satisfies the academic requirements in respect of Project work prescribed for the said Degree.

Mr. Irfan Khorakiwala Lecturer Project Guide

Mr. P.S. Sharma Professor Project Co-ordinator

Mr. Sandeep Vijay H.O.D. Head of Department

ii

ACKNOWLEDGEMENT

Firstly we would like to thank Mr. Irfan Khorakiwala for his great support, knowledge sharing and his persistent motivation throughout the project making process which helped us in executing the work smoothly. Further we would like to thank Mr. Sandeep Vijay (H.O.D, ECE Dept., DIT Dehradun) and our project coordinator Mr. P.S. Sharma for their continuous support and guidance throughout our project. We also owe our sincere gratitude to our friends and acquaintances who helped us in different steps and modules in our project.

Date:

Shubham Sah 0009070102122 B.Tech(ECE, 4th year)

Prabhanshu Sharma 060070102153 B.Tech(ECE, 4th year)

Nitesh Kumar Singh 060070102151 B.Tech (ECE, 4th year)

Trivendra Joshi 060070102154 B.Tech(ECE, 4th year)

iii

ABSTRACT

Multi-level inverters are operating with low frequency and present high efficiency than PWM inverters, because of low switching losses. H-Bridge inverter has significant advantage over other multi-level inverter topologies. It requires least number of components; optimized circuit layout and packaging are possible. This project work involves the hardware implementation of two-level cascaded inverter with the elimination of 3rd and 5th harmonics using micro-controller (P89V51RD2). Initially the circuit has been simulated in MULTISIM software. After the successful simulation the hardware implementation is done. MOSFET (IRF630FP) is used as power switching device. Fourier analysis has been made to eliminate the 3rd and 5th harmonics. Opto-coupler (4 pin DIP 817B) is used to overcome the common ground problem and also to give the sufficient gate driving voltage. The switching sequences are calculated so as to equally utilize all the MOSFETs and dc sources.

iv

TABLE OF CONTENTS

CHAPTER NO.

TITLE LIST OF TABLES LIST OF FIGURES LIST OF SYMBOLS

PAGE NO. ix x xii 1 2 3 3 5 5 6 6

INTRODUCTION

1.1 Harmonics 1.2 Inverter 1.3 Conventional Two-Level & Three-Level Voltage Source Inverter 1.4 PWM Techniques 1.5 Multi-Level Voltage Source Inverter 1.6 Cascaded Multi-Level Inverter 1.6.1 Features of cascaded inverter

CONFIGURATION AND OPERATIONAL PRINCIPLE OF PROPOSED INVERTER

7 8 9 9

2.1 Circuit Configuration 2.2 Block Diagram 2.3 Operation

FOURIER ANALYSIS AND HARMONICS ELIMINATION

11 12 13 14 14

3.1 Fourier Series for Periodic Function 3.2 Harmonics Elimination 3.2.1 Conduction angles calculation

3.3 C++ program for iteration

COMPONENT DESCRIPTION

16 16 17 17 18 18 19 19
v

4.1 POWER MOSFET 4.1.1 4.1.1.1 4.1.1.2 4.1.1.3 4.1.1.4 4.1.2

Introduction Basic structure and operation Switching characteristics ON state resistance Internal body diode Power MOSFET IRF630 FP

4.2 MICRO-CONTROLLER 4.2.1 4.2.2 4.2.3 4.2.4 4.2.4.1 4.2.4.2 4.2.4.3 4.2.4.3.1 4.2.4.3.2 4.2.4.3.3 4.2.5 4.2.5.1 4.2.5.2 4.2.5.3 4.2.5.4 4.2.5.5 General Description and Features Block Diagram of P89V51RD2 Pin Configuration Functional Description Memory organization Timers 0 and 1 Modes of operation Mode 0 Mode 1 Mode 0

22 22 22 23 23 23 24 26 26 26 26 26 26 26 27 28 28

Programming Switching sequence selection Delay time calculation Calculation of values for timer register Port 0 output values Program

4.3 OPTO-COUPLER 4.3.1 4.3.2 4.3.2.1 4.3.2.2 4.3.2.3 4.3.2.4 Introduction Importance of Opto-Coupler Common ground problem Gate driving voltage Opto-Coupler 817B Characteristics

33 33 33 33 34 34 35 36 36 36 38 39 40

4.4 TRANSFORMER (STEP-UP) 4.4.1 4.4.2 5 Introduction Induction Law

SIMULATION IN MULTISIM SOFTWARE

5.1 Introduction 5.2 Fourier Analysis Result

HARDWARE IMPLEMENTATION

42 43 47
vi

6.1 PCB Designing 6.2 PCB Designing using NI- ULTIboard

6.2.1

NI-ULTIboard

47 50 50 51 51 52

6.3 The Whole Setup 6.4 Micro-Controller 6.5 Circuit Setup 6.6 Output Waveform 6.7 Cost Estimation

CONCLUSION AND FUTURE ASPECTS

53 54 54

7.1 Conclusion 7.2 Future aspect

REFERENCES AND BIBLIOGRAPHY

vii

LIST OF TABLES TABLE No 2.1 4.1 4.2 4.3 4.4 4.5 4.6 5.1 6.7 TITLE Switching techniques for various voltage levels TMOD Timer/counter control register bit allocation TMOD Timer/counter control register bit description TMOD Timer/counter control register M1/M0 operating mode TCON Timer/counter control register bit allocation TCON Timer/counter control register bit description Port 0 output values Magnitude of each harmonic component Cost Estimation PAGE No 10 24 24 25 25 25 28 41 52

viii

LIST OF FIGURES

FIGURE No.

TITLE

PAGE No.

1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.1 2.2 2.3 3.1 3.2 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16

Fourier series representation of a distorted waveform Half-Bridge configuration Full-Bridge configuration Output waveform of half-bridge configuration Output waveform of full-bridge configuration A sinusoidal PWM waveform Schematic of multi-level inverter by a switch Typical output voltage of a three-level multilevel inverter Single-phase multilevel cascaded H-bridge inverter Typical two-level inverter Block diagram of H-Bridge cascaded inverter Output waveform Waveform of 2-level inverter Output of the program n-channel enhancement type MOSFET Transfer characteristics of n-channel enhancement MOSFET Switching waveforms and times MOSFET internal body diode MOSFET IRF630 FP Internal Schematic diagram Output characteristics Transfer characteristics Static Drain-Source ON resistance characteristics Block diagram of P89V51RD2 Pin configuration of P89V51RD2 Switching sequence Output waveform of port 0, pins 0-7, from top to down ON and OFF pulses to the opto-coupler Opto-coupler Common ground
ix

2 3 4 4 4 5 5 5 6 8 9 9 13 14 17 17 18 19 19 18 20 20 21 22 23 27 31 32 33 33

4.17 4.18 4.19 4.20 4.21 4.22 4.23 5.1(a) 5.1(b) 5.2 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11

Signal coupling using opto-coupler 817B opto-coupler in a 4-pin dual in-line package Pin description Forward voltage vs. forward current Collector current vs. collector emitter voltage Primary and secondary winding turn ratio.. Schematic of primary and secondary windings and core.. NI-MULTISIM Circuit Simulation in MULTISIM Fourier analysis Magnitude of each component PCB dipped in FeCl3 Solution Impression developed after some time PCB drilling NI-ULTIboard circuit PCB layout Optocoupler Unit circuit PCB layout Design Mirrored Impression for etching process 3-D View of Optocoupler Unit The whole setup of the project Micro-controller Circuit setup Output waveform

34 34 34 35 35 36 37 39 40 40 45 45 46 47 48 49 49 50 50 51 51

LIST OF SYMBOLS

PWM MOSFET dc ac THD rms SDCS VGS td(on) tr td(off) tf VT RDS(on) VDS ID kB TTL CMOS EMI ALE RAM LED IEEE IEC

Pulse Width Modulation Metal Oxide Semiconductor Field Effect Transistor Direct current Alternating current Total Harmonic Distortion root mean square Separate DC Source Gate to Source voltage Turn-on delay time rise time Turn-off delay time rise time Threshold voltage ON state resistance Drain to Source voltage Drain current kilo byte Transistor-Transistor Logic Complementary MOSFET Electromagnetic Interference Address Latch Enable Random Access Memory Light Emitting Diode Institute of Electrical and Electronics Engineers International Electrotechnical Commission

xi

CHAPTER 1

INTRODUCTION

CHAPTER 1

INTRODUCTION
1.1 HARMONICS
Presence of harmonics in power system causes various problems; especially the low frequency harmonics reduce the overall efficiency of the system to a greater extent. Fourier transformation is applied in harmonic analysis. Any periodic waveform can be shown to be the super position of a fundamental and a set of harmonic components. By applying Fourier transformation, magnitude of these components can be known. The frequency of each harmonic component is an integral multiple of its fundamental.

50 Hz (h = 1) 150 Hz (h = 3) 250 Hz (h = 5) 350 Hz (h = 7) 450 Hz (h = 9) 550 Hz (h = 11) 650 Hz (h = 13)

Fig 1.1 Fourier series representation of a distorted waveform Normally to eliminate the harmonics, filters are used. When the order of harmonics decreases, size of the filter increases. When size of the filter increases, it occupies more space and sometimes it needs cooling system and also it becomes costly. So it is important to eliminate the low frequency harmonics. There are several methods to indicate the quantity of harmonics content. The most widely used measure is the total harmonic distortion (THD), which is defined in terms of the amplitudes of the harmonics; Mh. THD is a measure of the effective value of the harmonic components of a distorted waveform. That is, it is the potential heating value of the harmonics relative to the fundamental.

(1.1) 2

where Mh is the rms value of harmonic component h of the quantity M.

1.2 INVERTER
Dc-to-ac converters are known as inverters. The function of an inverter is to change a dc input voltage to a symmetric output voltage of desired magnitude and frequency. The output voltage waveforms of ideal inverters should be sinusoidal. However the waveforms of practical inverters are non-sinusoidal and contain certain harmonics. Generally the inverters can be classified into two types, 1) Voltage source inverters 2) Current source inverters. Multi-level inverter falls under the category of voltage source inverter.

1.3 CONVENTIONAL TWO-LEVEL AND THREE-LEVEL VOLTAGE SOURCE INVERTER

A half-bridge is the simplest topology, which is used to produce a two-level square wave output waveform. A center-tapped voltage source supply is needed in such a topology. It may be possible to use a simple supply with two-well matched capacitors in series to provide the center tap. The full-bridge topology is used to synthesize a three level square-wave output waveform. The half-bridge and full-bridge configurations of the single-phase voltage-source inverter are shown in Fig. 1.2 and 1.3 respectively. In a single-phase half-bridge inverter, only two switches are needed. To avoid short-through fault, both switches are never turned on at the same time. S+ is turned on and S- is turned off to give a load voltage, vo in Fig. 1.2 of +vi/2. To complete one cycle, S+ is turned off and S- is turned on to give a load voltage of vi/2.

Fig 1.2 Half-Bridge configuration In full-bridge configuration, turning on S1+ and S2- and turning off S2+ and S1- give a voltage of vi between point A and B (vo), in Fig. 1.3, while turning off S1+ and S2- and turning on S2+ and S1- give a voltage of -vi. To generate zero level in a full bridge inverter, the combination can be S1+ and S2+ ON while 3

S1- and S2- OFF or vice verse. Note that S1+ and S1-should not be closed at the same time, nor should S2+ and S2-. Otherwise, a short circuit would exist across the source.

Fig 1.3 Full-Bridge configuration The output waveforms of half-bridge and full-bridge of single-phase voltage source inverter are shown in fig 1.4 and 1.5 respectively.

Fig 1.4 Output waveform of half-bridge configuration

Fig 1.5 Output waveform of full-bridge configuration

1.4 PWM TECHNIQUES

To obtain a quality output voltage or a current waveform with a minimum amount of ripple content, they require high-switching frequency along with various pulse-width modulation (PWM) strategies. PWM techniques have some limitations in operating under high frequencies mainly due to switching losses and constraints of device ratings.

Fig 1.6 A sinusoidal PWM waveform

1.5 MULTI-LEVEL VOLTAGE SOURCE INVERTER

Fig 1.7 Schematic of multi-level inverter by a switch The general structure of the multi-level inverter is to synthesize a near sinusoidal waveform from several levels of dc voltages. As the number of levels increases, the synthesized output waveform has more steps, which produces a staircase wave that approaches a desired waveform. Also, as more steps are added to the waveform, the harmonic distortion of the output waveform decreases.

Fig 1.8 Typical output voltage of a three-level multilevel inverter

1.6 CASCADED MULTI-LEVEL INVERTER

A cascaded multilevel inverter consists of a series of H-Bridge (single-phase, full-bridge) inverter units. The general function of this multilevel inverter is to synthesize a desired voltage from several separate dc sources (SDCSs), which may be obtained from batteries, fuel cells, or solar cells. Fig 1.8 shows the basic structure of a single-phase cascaded inverter with SDCSs. Each SDCS is connected to an H-Bridge inverter. The ac terminal voltages of different level inverters are connected as series.

Fig 1.9 Single-phase multilevel cascaded H-bridge inverter

1.6.1 Features of Cascaded Inverter

The main features are as follows: The cascaded inverters need separate dc sources. The structure of separate dc sources is well suited for various renewable energy sources such as fuel cell, photovoltaic and biomass. It requires least number of components relatively. Optimized circuit layout and packaging are possible because each level has the same structure.

CHAPTER 2

CONFIGURATION AND OPERATIONAL PRINCIPLE OF PROPOSED INVERTER

CHAPTER 2

CONFIGURATION AND OPERATIONAL PRINCIPLE OF PROPOSED INVERTER

2.1 CIRCUIT

CONFIGURATION

Fig 2.1 Typical two-level inverter A typical two-level H-Bridge cascaded inverter is shown in the above fig 2.1. It has two separate voltage sources V1 & V2 and eight power electronic switches. The desired output waveform as shown in the fig 2.2 can be produced by correctly switching on and off the appropriate switches at correct instants.

2.2 BLOCK DIAGRAM

Fig 2.2 Block diagram of H-Bridge Cascaded Inverter Circuitry

2.3 OPERATION
This circuit can produce five different levels of output voltage. By modulating the switches correctly we can produce a stepped sine waveform as shown in the fig 2.2. The output voltage contains +V, +2V, 0, -V & -2V voltage levels. To produce +V, we can either use V1 as voltage source or V2 as voltage source. If V1 is used, switches S1S4S5S6 or S1S4S7S8 should be closed. If V2 is used as voltage source, switches S1S2S5S8 or S3S4S5S8 should be closed.

+2V +V 0 -V -2V

Fig 2.3 Output waveform To produce +2V, both the voltage sources should be connected in series. So switches S1S4S5S8 are closed. To produce 0V, the load should be short-circuited. We have four switching options to short the load. Closing of S1S2S5S6 or S1S2S7S8 or S3S4S5S6 or S3S4S7S8 switches short circuit the load. 9

To produce -V, we can either use V1 as voltage source or V2 as voltage source. If V1 is used, switches S2S3S5S6 or S2S3S7S8 should be closed. If V2 is used as voltage source, switches S1S2S6S7 or S3S4S6S7 should be closed. To produce -2V, both the voltage sources should be connected in series. So switches S2S3S6S7 are closed. The switching sequences must be selected in such a way that both the sources are equally utilized and also all the eight devices are equally used. Table 2.1 Switching techniques for various voltage levels Voltage level S1 1 +V (V1) 1 1 +V (V2) +2V 0 1 1 1 0V 0 0 0 -V (V1) -V (V2) 0 -2V 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 1 S2 0 0 1 0 0 1 1 0 0 1 1 1 S3 0 0 0 1 0 0 0 1 1 1 1 0 S4 1 1 0 1 1 0 0 1 1 0 0 0 S5 1 0 1 1 1 1 0 1 0 1 0 0 S6 1 0 0 0 0 1 0 1 0 1 0 1 S7 0 1 0 0 0 0 1 0 1 0 1 1 S8 0 1 1 1 1 0 1 0 1 0 1 0

10

CHAPTER 3

FOURIER ANALYSIS AND HARMONICS ELIMINATION

11

CHAPTER 3

FOURIER ANALYSIS AND HARMONICS ELIMINATION

3.1 FOURIER SERIES FOR PERIODIC FUNCTION
Under steady-state condition, the output voltage of power converters is, generally, a periodic function of time defined by vo(t) = vo (t + T) =2 and Eq.(3.1) can be rewritten as vo ( t) = vo ( t +2 ) (3.3) The Fourier theorem states that a periodic function vo(t) can be described by a constant term plus an infinite series of sine and cosine terms of frequency n vo(t)= a0 where n is an integer. Therefore, vo(t) can be expressed as ancos n t + bnsin n t n varies from 1 to infinity where a0/2 is the average value of the output voltage . The constants a0, an and bn can be determined from the following expressions: /T = 2 f (3.1) (3.2) where T is the periodic time. If f is the frequency of the output voltage in hertz, the angular frequency is

1 a0 =

(3.5)

1 an =

(3.6)

1 bn =

(3.7)

If the output voltage has a half-wave symmetry, the number of integrations within the entire period can be reduced significantly. A waveform has the half-wave symmetry if the waveform satisfies the following condition: vo ( t) = -vo ( t + ) (3.8) In a waveform with a half-wave symmetry, the negative half-wave is a mirror image of the positive half-wave, but phase shifted by T/2 s (or rad) from the positive half-wave. A waveform with a halfwave symmetry does not have the even harmonics (i.e., n = 2,4,6, ) and possess only the odd harmonics (i.e., n = 1,3,5, . ). Due to the half-wave symmetry, the average value is zero (i.e., a0 = 0). Moreover if the wave is symmetric about y-axis, it contains only cosine terms (i.e., bn = 0) and if the wave is anti-symmetric, it contains only sine terms (i.e., an = 0).

12

3.2 HARMONICS ELIMINATION

+2V +V 0 -V -2V Va +V

-V Vb

+V

-V

Fig 3.1 Waveform of 2-level inverter As shown in the fig 3.1, the output wave of a multilevel inverter can viewed as the summation of square waves having different conducting angles. vo(t) = va(t) + vb(t) zero. We get bn as (3.9) Due to the quarter-wave symmetry along the x-axis, both Fourier coefficients a0 and an are

(3.10)

(3.11) which gives the instantaneous voltage von( t) of nth component as (3.12) The conducting angles a1 and a2 can be chosen such that the total harmonic distortion of the output voltage is minimized. These angles are normally chosen so as to cancel some predominant lower frequency harmonics. Here the conducting angles should be chosen so as to eliminate the 3rd and 5th harmonics. So we must solve the following equations. cos 3 cos 5
1 1

+ cos 3 + cos 5

2= 2=

0 0

(3.13) (3.14)

13

3.2.1 Conduction angles calculation Rearrange the equations 3.13 & 3.14; we can get the following equations,
2=cos 1=cos -1 -1

(-cos(3* (-cos(5*

1)))/3; 2)))/5;

(3.15) (3.16)

Initially the simple gauss-siedel iteration method is used to solve the above equations. But iteration starts oscillating between two values. So a slight change is introduced in the normal iteration procedure. A simple C++ program is developed to solve the above equations. 3.2.1.1 C++ Program for iteration #include<conio.h> #include<iostream.h> #include<math.h> void main() { float a1,a2,a11,a22; clrscr(); cout<<"\n\tGIVE THE INITIAL GUESS\n\t"; cin>>a1; cout<<"\n\t a1"<<"\t\t"<<" a2\n\n"; while((a1!=a11)&&(a2!=a22)) { a11=a1; a22=a2; a2=(acos(-cos(3*a1)))/3; a1=(acos(-cos(5*a2)))/5; cout<<"\t"<<a1<<" \t"<<a2<<"\n"; a1=(a11+a1)/2; } getch(); } Output:

14

Fig 3.2 Output of the program

1 2

= 0.20944 rad = 120 = .837758 rad = 480

(3.17) (3.18)

Thus the conducting angles are successfully found.

15

CHAPTER 4

COMPONENT DESCRIPTION

16

CHAPTER 4

COMPONENT DESCRIPTION
4.1 POWER MOSFET
4.1.1 INTRODUCTION
A power MOSFET is a voltage-controlled device and requires only a small input current. The switching speed is very high and the switching times are of the order of nanoseconds. Power MOSFETs find increasing applications in low-power high-frequency converters. MOSFETs do not have problem of second breakdown phenomena as do BJTs. However, MOSFETs have the problems of electrostatic discharge and require special care in handling.

4.1.1.1 Basic structure and Operation

Fig 4.1 n-channel enhancement type MOSFET The two types of MOSFETs are 1) depletion MOSFETs and 2) enhancement MOSFETs. The gate is isolated from the channel by a thin oxide layer. The three terminals are called gate, drain, and source. An n-channel enhancement-type MOSFET has no physical channel, as shown in fig 4.1. If VGS is positive, an induced voltage attracts the electrons in the p-layer and accumulates them at the surface beneath the oxide layer. If VGS is greater than or equal to a value known as threshold voltage VT, a sufficient number of electrons are accumulated to form a virtual n-channel and the current flows from the drain to source. The polarities of VDS, IDS, and VGS are reversed for a p-channel enhancement type MOSFET.

Fig 4.2 Transfer characteristics of n-channel enhancement-type MOSFET

17

4.1.1.2 SWITCHING CHARACTERISTICS

Without any gate signal, an enhancement-type MOSFET may be considered as two diodes connected back to back or as an NPN-transistor. The gate structure has parasitic capacitances to the source, Cgs, and to the drain, Cgd. The npn-transistor has a reverse-bias junction from the drain to the source and offers a capacitance, Cds.

Fig 4.3 Switching waveforms and times The typical switching waveforms and times are shown in fig. 4.3. the turn-on delay time td(on) is the time that is required to charge the input capacitance to threshold voltage level. The rise time tr is the gate-charging time from the threshold level to the full gate voltage Vg, which is required to drive the MOSFET into the saturated region. The turn off time delay td(off) is the time required for the input capacitance to discharge from the overdrive gate voltage to the pinch-off region. VGS must decrease significantly before VDS begins to rise. The fall time tf is the time that is required for the input capacitance to discharge from the pinch-off region to threshold voltage. If VGS<VT, the transistor turns off.

4.1.1.3 ON state resistance

When the MOSFET is in the on-state, the channel of the device behaves like a constant resistance RDS(on) that is linearly proportional to the change between vDS and iD as given by the following relation:

(4.1) The total conduction (on-state) power loss for a given MOSFET with forward current ID and on-resistance RDS(on) is given by (4.2) 18

The value of RDS(on) can be significant and varies between tens of milliohms and a few ohms for low-voltage and high-voltage MOSFETS, respectively. The on-state resistance is an important data sheet parameter, because it determines the forward voltage drop across the device and its total power losses.

4.1.1.4 Internal body diode

The modern power MOSFET has an internal diode called a body diode connected between the source and the drain as shown in Fig. 4.4. This diode provides a reverse direction for the drain current, allowing a bidirectional switch implementation.

Fig 4.4 MOSFET internal body diode

4.1.2 MOSFET IRF630 FP

1. Gate 2. Drain 3. Source

Fig 4.5 MOSFET IRF630 FP The MOSFET, which we are using now, is IRF630FP. It is manufactured by STMicroelectronics. It is an N-Channel, 200V, 9A MOSFET. It has an ON-state resistance of 0.35 only It has good switching characteristics. Its turn-ON time is only 34ns and its turn-OFF time is 70ns.

Fig 4.6 Internal Schematic diagram

19

Fig 4.7 Output characteristics

Fig 4.8 Transfer characteristics

20

Fig 4.9 Static Drain-Source ON resistance characteristics The maximum VGS allowed is 20V. To turn ON the device, 9V is applied as gate to source voltage using a battery.

21

4.2 MICRO-CONTROLLER
4.2.1 GENERAL DESCRIPTION AND FEATURES
The micro-controller is used here to create accurate on, off pulses for all the eight MOSFETs. Using a micro-controller for generating the switching sequence is very advantageous in many aspects. It is very compact, occupies very less space, allows reprogramming of time-delays, and is very reliable. The P89V51RD2 is an 80C51 microcontroller with 64 kB Flash and 1024 bytes of data RAM. Some features of P89V51RD2: 5 V Operating voltage from 0 to 40 MHz Three 16-bit timers/counters TTL- and CMOS-compatible logic levels Low EMI mode (ALE inhibit) Four 8-bit I/O ports

It is plastic dual in-line package. It has 40 pins.

4.2.2 BLOCK DIAGRAM OF P89V51RD2

The block diagram gives the architecture of micro-controller. The diagram is self-explanatory.

Fig 4.10 Block diagram of P89V51RD2

22

4.2.3 PIN CONFIGURATION

Fig 4.11 Pin configuration of P89V51RD2

4.2.4 FUNCTIONAL DESCRIPTION

4.2.4.1 Memory organization 23

The device has separate address spaces for program and data memory. There are two internal flash memory blocks in the device. We use only the Block 0. It has 64 kB and contains the users code. The data RAM has 1024 bytes of internal memory. The device can also address up to 64 kB for external data memory. 4.2.4.2 Timers 0 and 1 The two 16-bit Timer/Counter registers: Timer 0 and Timer 1 can be configured to operate either as timers or event counters. In the Timer function, the register is incremented every machine cycle. A machine cycle consists of six oscillator periods. Timer 0 and Timer 1 have four operating modes from which to select. Control bits C/T in the Special Function Register TMOD select the Timer or Counter function. These two Timer/Counters have four operating modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different. The four operating modes are described in the table 5.1 and 5.2. Table 4.1 TMOD Timer/counter control register bit allocation

Table 4.2 TMOD Timer/counter control register bit description

Table 4.3 TMOD Timer/counter control register M1/M0 operating mode

24

Table 4.4 TCON Timer/counter control register bit allocation

Table 4.5 TCON Timer/counter control register bit description

25

4.2.4.3 Modes of operation 4.2.4.3.1 Mode 0 In the mode 0 timer register is configured as a 13-bit register. The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not clear the registers. Mode 0 operation is the same for Timer 0 and Timer 1. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3). 4.2.4.3.2 Mode 1 Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn) are used. 4.2.4.3.3 Mode 2 Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload; Mode 2 operation is the same for Timer 0 and Timer 1.

4.2.5 PROGRAMMING
4.2.5.1 Switching sequence selection Switching sequence should be selected so as to equally utilize both the voltage sources and to equally use all the eight MOSFETs. The switching sequence is shown in fig. The MOSFETs are equally used, that is, four times per cycle.

V1

V1 +V V2 V2
0 V1 V1

+2V

V2

V2

-V

-2V

MOSFETs switched ON: 1, 4, 5, 6 - V1 1, 4, 5, 8 - V1 + V2 1, 2, 5, 8 - V2 1, 2, 5, 6 - 0V 2, 3, 7, 8 - (-V1) 2, 3, 6, 7 - (-V1) + (-V2) 3, 4, 6, 7 - (-V2) 3, 4, 7, 8 - 0V

Fig 4.12 Switching sequence 4.2.5.2 Delay time calculation 1. Time gap for +V output: t1=(( 2- 1)/360)*20 ms =((48-12)/360)*20 ms =2 ms 26

2. Time gap for +2V output: t2=(((180-36- 1)- 2)/360)*20 ms =(((180-36-12)-48)/360)*20 ms =4.6667 ms 3. Time gap for 0V output: t3=(2 1/360)*20 ms =(24/360)*20 ms =1.3333 ms Since the waveform is half-wave symmetry and also quarter-wave with respect to x-axis, time gap for other voltage levels can be easily calculated. 4. Time gap for -V output: t -1 = t1 = 2 ms 5. Time gap for -2V output: t -2 = t2 = 4.6667 ms 5.5.3 Calculation of values for timer register Timer 0 is used in 16-bit mode. The clock frequency used in micro-controller is 11.0592 MHz. The micro-controller is used with 12-clock rate, i.e., 12 clocks per machine cycle. Therefore, to execute a one-machine cycle instruction, it takes, (1/11.0592)*12 = 1.085 in the timer register can be calculated as follows, c1 = (2/1.085)*1000 = 1843 cycles = 733H cycles T1 = FFFFH-733H = F8CC H c2 = (4.6667/1.085)*1000 = 4301 cycles = 10CDH cycles T2 = FFFFH-10CDH = EF32 H c3 = (1.3333/1.085)*1000 = 1288 cycles = 508H cycles T3 = FFFFH-508H = FAF7 H s The decrementing operation in timer needs one machine cycle. Therefore the value to be stored

27

For all the above values, last 30 to 90 cycles, of the output of port 0 is maintained at zero to avoid short-through problem, because of switching delay in opto-coupler and MOSFET. 4.2.5.4 Port 0 output values Since all the outputs are taken from port 0, it is unable to drive the opto-coupler. To avoid this problem, anode is connected to the source voltage of micro-controller and cathode is connected to the ports. So, to drive an opto-coupler LED, the port pin should be at 0-level not at 1-level. The port 0 output values are calculated based on the above idea.

Table 4.6 Port 0 output values S8 1 0 0 1 0 1 1 0 S7 1 1 1 1 0 0 0 0 S6 0 1 1 0 1 0 0 1 S5 0 0 0 0 1 1 1 1 S4 0 0 1 1 1 1 0 0 S3 1 1 1 1 0 0 0 0 S2 1 1 0 0 0 0 1 1 S1 0 0 0 0 1 1 1 1 Port 0 output value C6H 66H 6CH CCH 39H 99H 93H 33H

4.2.5.5 Program Device: P89V51RD2 ORG 0H; MOV TMOD,#01; CLR TF0; HERE: MOV A,#0C6H; MOV P0,A; MOV TL0,#0FCH; MOV TH0,#0F8H; ACALL DELAY; MOV A,#0FFH; MOV P0,A; MOV TL0,#0E1H; 28

MOV TH0,#0FFH; ACALL DELAY; MOV A,#66H; MOV P0,A; MOV TL0,#8FH; MOV TH0,#0EFH; ACALL DELAY; MOV A,#0FFH; MOV P0,A; MOV TL0,#0E1H; MOV TH0,#0FFH; ACALL DELAY; MOV A,#6CH; MOV P0,A; MOV TL0,#0FCH; MOV TH0,#0F8H; ACALL DELAY; MOV A,#0FFH; MOV P0,A; MOV TL0,#0EBH; MOV TH0,#0FFH; ACALL DELAY; MOV A,#0CCH; MOV P0,A; MOV TL0,#23H; MOV TH0,#0FBH; ACALL DELAY; MOV A,#0FFH; MOV P0,A; MOV TL0,#0EBH; MOV TH0,#0FFH; ACALL DELAY; MOV A,#39H; MOV P0,A; MOV TL0,#0FCH; MOV TH0,#0F8H; ACALL DELAY; 29

MOV A,#0FFH; MOV P0,A; MOV TL0,#0E1H; MOV TH0,#0FFH; ACALL DELAY; MOV A,#99H; MOV P0,A; MOV TL0,#6AH; MOV TH0,#0EFH; ACALL DELAY; MOV A,#0FFH; MOV P0,A; MOV TL0,#0E1H; MOV TH0,#0FFH; ACALL DELAY; MOV A,#93H; MOV P0,A; MOV TL0,#0FCH; MOV TH0,#0F8H; ACALL DELAY; MOV A,#0FFH; MOV P0,A; MOV TL0,#0EBH; MOV TH0,#0FFH; ACALL DELAY; MOV A,#33H; MOV P0,A; MOV TL0,#25H; MOV TH0,#0FBH; ACALL DELAY; MOV A,#0FFH; MOV P0,A; MOV TL0,#0EBH; MOV TH0,#0FFH; ACALL DELAY; LJMP HERE;

30

DELAY: SETB TR0; AGAIN: JNB TF0,AGAIN; CLR TR0; CLR TF0; RET; END The above program is simulated in keil u-vision software. The output waveform for each pin of port 0 is shown in fig 5.6

Fig 4.13 Output waveform of port 0, pins 0-7, from top to down

The fig 4.13 shows the actual ON and OFF time pulses to the opto-coupler.

31

Fig 4.14 ON and OFF pulses to the opto-coupler

32

4.3 OPTO-COUPLER
4.3.1 INTRODUCTION
Opto-coupler is nothing but a combination of LED and a phototransistor. It provides optical coupling between input and output. The input side has a LED. It emits photons, when it is forward biased. The output side has a phototransistor. When the emitted photons hit the phototransistor, it induces the base current to flow. The transistor is switched on. When the LED is not forward biased, the transistor remains in off state.

Fig 4.15 Opto-coupler 4.3.2 IMPORTANCE OF OPTO-COUPLER Opto-coupler is used to solve two main problems. One is common ground problem, which arises because of MOSFETs, which need individual signal grounds. Second problem is the gate driving voltage of MOSFET. 4.3.2.1 Common ground problem When the signal is directly given from micro-controller, the source of all MOSFETs should be commonly grounded to the micro-controller ground. It makes some MOSFETs permanently shorted as shown in fig 6.2. To avoid this problem opto couplers are used. Each phototransistor is driven by individual dc supply.

Fig 4.16 Common ground The common ground problem eliminated circuit is shown in fig 6.3

33

1 2

U1 PS2501

V1 4 9Vdc R1 10k Q3 IRF630/TO

3 1 2 3 U1 PS2501 V1 4 9Vdc R1 10k

Q4 IRF630/TO

Fig4.17 Signal coupling using opto-coupler 4.3.2.2 Gate driving voltage The driving voltage from micro-controller is only 5V. It is not sufficient to drive a power MOSFET IRF630. The usage of opto-coupler paves the way to increase the gate driving voltage. A 9V dc source is used to drive the gate of the MOSFET. It is shown in fig 6.3.

4.3.3 OPTO-COUPLER 817B

Fig 4.18 817B opto-coupler in a 4-pin dual in-line package

Fig 4.19 Pin description

34

It consists of a gallium arsenide infrared emitting diode driving a silicon phototransistor. It is in dual in-line package as shown in fig 6.4 and pin description is shown in fig 6.5. 4.3.3.1 Characteristics The maximum Vce0 that can be applied is 70V. It can sustain a continuous collector current of 50mA. The maximum rise time and fall time are 18 s at the load resistance of 100

Fig 4.20 Forward voltage vs. forward current

Fig4.21 Collector current vs. collector emitter voltage

35

4.4 TRANSFORMER
4.4.1 Introduction
A transformer is a static electrical device that transfers energy by inductive coupling between its winding circuits. A varying current in the primary winding creates a varying magnetic flux in the transformer's core and thus a varying magnetic flux through the secondary winding. This varying magnetic flux induces a varying electromotive force (emf) or voltage in the secondary winding. Transformers range in size from thumbnail-sized used in microphones to units weighing hundreds of tons interconnecting the power grid. A wide range of transformer designs are used in electronic and electric power applications. Transformers are essential for the transmission, distribution, and utilization of electrical energy.

Fig 4.22 Primary and secondary winding turn ration and voltage formula

4.4.2 Induction law

The transformer is based on two principles: first, that an electric current can produce a magnetic field and second that a changing magnetic field within a coil of wire induces a voltage across the ends of the coil (electromagnetic induction). Changing the current in the primary coil changes the magnetic flux that is developed. The changing magnetic flux induces a voltage in the secondary coil. Referring to the two figures here, current passing through the primary coil creates a magnetic field. The primary and secondary coils are wrapped around a core of very high magnetic permeability, usually iron, so that most of the magnetic flux passes through both the primary and secondary coils. Any secondary winding connected load causes current and voltage induction from primary to secondary circuits in indicated directions.

36

Fig 4.23: Schematic of primary and secondary windings and core with flux density Ideal transformer and induction law. The voltage induced across the secondary coil may be calculated from Faraday's law of induction, which states that:

where Vs = Es is the instantaneous voltage, Ns is the number of turns in the secondary coil, and d/dt is the derivative[d] of the magnetic flux through one turn of the coil. If the turns of the coil are oriented perpendicularly to the magnetic field lines, the flux is the product of the magnetic flux density B and the area A through which it cuts. The area is constant, being equal to the cross-sectional area of the transformer core, whereas the magnetic field varies with time according to the excitation of the primary. Since the same magnetic flux passes through both the primary and secondary coils in an ideal transformer,[6] the instantaneous voltage across the primary winding equals

Taking the ratio of the above two equations gives the same voltage ratio and turns ratio relationship shown above, that is,

. The changing magnetic field induces an emf across each winding. [8] The primary emf, acting as it does in opposition to the primary voltage, is sometimes termed the counter emf.[9] This is in accordance with Lenz's law, which states that induction of emf always opposes development of any such change in magnetic field. As still lossless and perfectly-coupled, the transformer still behaves as described above in the ideal transformer. 37

CHAPTER 5

SIMULATION IN MULTISIM SOFTWARE

38

CHAPTER 5

SIMULATION IN MULTISIM SOFTWARE

5.1 INTRODUCTION
MULTISIM is user-friendly simulation software. The entire circuit is simulated in MULTISIM. But the exact components are unavailable in MULTISIM. So the components are chosen such that their characteristics are almost similar to the originally used components.

Fig 5.1(a) NI-MULTISIM (National Instrumentation Multisimulator 11.0) Simulation Circuitry.

39

R12 500

V3
1 10 U3 45

35 R4 10k 7 2 Q2 IRF530

R13 500

V5 30 1
2

U2

4 8

9V
3

R2 10k 14

XSC1
Ext Trig + _

9V
2 3

PS2561-1

PS2561-1

Q3 IRF530

A + _ +

B _

33 VCC U1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P1B0T2 P1B1T2EX P1B2 P1B3 P1B4 P1B5MOSI P1B6MISO P1B7SCK RST P3B0RXD P3B1TXD P3B2INT0 P3B3INT1 P3B4T0 P3B5T1 P3B6WR P3B7RD XTAL2 XTAL1 GND VCC P0B0AD0 P0B1AD1 P0B2AD2 P0B3AD3 P0B4AD4 P0B5AD5 P0B6AD6 P0B7AD7 EAVPP ALEPROG PSEN P2B7A15 P2B6A14 P2B5A13 P2B4A12 P2B3A11 P2B2A10 P2B1A9 P2B0A8 40 38 39 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

6 V1 12 V Q4 IRF530 37 R1 100 4 R3 10k 19 Q5 IRF530 24

5V VCC 36

R14 500 38

V7
1 11

R15

V6
1 12

U5

4 20

U4

4 15

9V
2 3

500 R5 10k 2 22 39 PS2561-1

9V
3

PS2561-1

8051 R16 500

2 3

R17 V8
1 13

V9
1 16

17 9 R6 10k 25 V2 12 V Q1 IRF530 0

U7

4 26

U6

4 23

9V PS2561-1

500 Q6 2 3 PS2561-1 IRF530

9V

R7 10k 28

40 Q7 IRF530 R18 V10

1 21

41

Q8 IRF530 R19 V11 27 1

2

U8

4 29

U9

4 32

18 R9 10k 34

500 0 2 PS2561-1

9V
3

R8 10k 31

500
3

9V PS2561-1

Fig 5.1(b) Circuit simulated in MULTISIM

5.2 FOURIER ANLAYSIS RESULT

The Fourier analysis has been done in the output (stepped) waveform using MULTISIM software.

Fig 5.2 Fourier analysis Magnitude of each component

40

Table 5.1 Magnitude of each harmonic component

From the above table 6.1 the harmonics dominating are 7, 11, 13, 17, 19, etc.

41

CHAPTER 6

HARDWARE IMPLEMENTATION

42

CHAPTER 6

HARDWARE IMPLEMENTATION
6.1 PCB Designing PCB Designing Steps
A printed circuit board, or PCB, is used to mechanically support and electrically connect electronic components using conductive pathways, tracks or signal traces etched from copper sheets laminated onto a non-conductive substrate. It is also referred to as printed wiring board (PWB) or etched wiring board. This unit introduces the process of developing a Printed Circuit Board (PCB).

Objectives
Expose the photoresist of a PCB using a circuit mask and Ultraviolet Light Develop the exposed PCB with photoresist developer Etch a developed PCB Prepare the PCB for use and drill the PCB Solder electronic components onto a PCB

Materials List
Unexposed printed circuit board (positive photoresist PCB) Approximately 50 grams of developing solution Approximately 100 grams of dry concentrated etchant (Ferric Chloride) Circuit transparency mask

Tools List
UV exposer setup Drill with appropriate drill bit Soldering iron and solder A medium strength scrub pad Plastic (preferred) or glass container large enough to immerse the PCB Glass stirrer

Safety Precautions
ALWAYS wear rubber gloves, a disposable apron and eye goggles when developing and etching the board. Follow all instructions on the chemical packages.

The Job
The unexposed PCB should be kept in its packet until it is ready to be exposed. Make sure all your equipment is clean before starting the UV expose positive photoresist PCB. 1) Prepare the UV exposer for use; make sure there is as little light as possible in the room. 43

2) When you are ready to expose the unexposed PCB. 3) Set the unexposed PCB down on the UV exposer, taking care not to touch the copper side of the board, and place the circuit trace on top of the PCB. Make sure the circuit trace is oriented correctly and not upside down. 4) Close the UV exposer and turn the UV light on. 5) At exactly 10 minutes, turn off the UV light and open the UV exposer.

Develop an exposed PCB with PCB Developer

1) Put on your rubber gloves, disposable apron and eye goggles. 2) Pour 1,000 ml. of warm water (25 - 30oC) into the plastic container. 3) Pour the developing solution into the plastic container and stir it with the glass stirrer until there are no more solids left in the container. 4) Remove the exposed PCB from its package, taking care not to touch the surface of the PCB, and slowly place the PCB (copper side up) in the plastic container. 5) Gently rock the plastic container from side to side, taking care not to splash the developing solution. 6) Rock the container until the blue smoke film stops floating from the PCB. This procedure should last between 0.5 to 2.0 minutes. Exceeding 2.0 minutes might cause the photoresist film to be over exposed thus making the board unusable. 7) When this is done, remove the PCB from the container and wash the PCB under cold running water. If possible, use gentle flowing water to wash off any remaining developer from the PCB; this stops the developing process from continuing. 8) Gently dab the PCB dry with a dry paper towel and put it aside. 9) Store the remaining developing solution in a plastic container for later use. Clean the plastic container, with water, thoroughly. You are now ready to etch the PCB.

Etch a developed PCB

1) Dip the PCB in etching tank and set the temperature about 40-600C. 2) The process of etching the PCB can take anywhere from a few minutes to 2 hours; the key idea is to etch the unprotected copper from the PCB. 3) When the unprotected copper on the PCB seems to be all gone, remove the PCB from the container and verify that this is the intended circuit. 4) Clean the PCB under flowing water, ensuring that all the etching solution is removed from the board. Dry the board with clean paper towels and set the board aside.

44

Fig 6.1 PCB dipped in FECl3 solution

Fig 6.2 Impressing made after some time 45

Prepare the PCB for use and drill the PCB

5) Using the appropriate drill bit, drill the white holes on the PCB. Place the drill bit up to the PCB (copper side up) and start the drill, firmly push the drill bit through the PCB continue doing so for all the holes. 6) Once all the holes are drilled, wash the PCB under running water and dry it well. If the PCB is not fully dried, soldering will not work well on the PCB. The PCB is now ready to be soldered.

Fig 6.3 PCB Drilling

Solder onto a PCB

1) Place the component to be soldered into the holes drilled in the board. 2) Refer to the enclosed sheet on how to solder. 3) Once you are done soldering, check the solder joints under a magnifying glass to ensure proper solder joints. 4)Once you are done soldering all the components, check to make sure there are no short circuits on the traces; i.e. no solder has flowed between two pins.

46

6.2 PCB Designing using NI-ULTIBOARD

6.2.1 NI-ULTIBOARD NI Ultiboard or formerly ULTIboard is an electronic Printed Circuit Board Layout program which is part of a suite of circuit design programs, along with NI Multisim. One of its major features is the Real Time Design Rule Check, a feature that was only offered on expensive work stations in the days when it was introduced. ULTIboard was originally created by a company named Ultimate Technology, which is now a subsidiary of National Instruments. Ultiboard includes a 3D PCB viewing mode, as well as integrated import and export features to the Schematic Capture and Simulation software in the suite, Multisim.

47

Fig 6.4 National Instrumentation NI-Ultiboard Circuit PCB layout.

Fig 6.5 Optocoupler Unit Circuit PCB layout Design.

48

Fig: 6.6: Mirrored Impressions for Etching process.

Fig: 6.7: 3D view of optocoupler unit, NI (National Instrumentation) Ultiboard (Circuit designing Solutions).

49

6.3 THE WHOLE SETUP

Fig 6.8: Whole setup of the project

6.4 MICRO-CONTROLLER
The wires shown in fig 8.2 are output wires taken from port 0 of micro-controller.

Fig 6.9 Micro-controller

50

6.5 CIRCUIT SETUP

Chips, which are in left-hand side in the fig 8.3, are opto-couplers. The output of the opto coupler is given as VGS to the MOSFET.

Fig 6.10 Circuit setup

6.6 OUTPUT WAVEFORM

The output of the inverter is connected to a resistive load. The waveform is seen using a CRO.

Fig 6.11 Output waveform

51

6.7 COST ESTIMATION:

PARTS
Microcontroller (P89V51RD2)

QUANTITY
1 8 8 11 1 17

COST
250 200 160 1250 200 50

Power MOSFETS (IRF630-FP) OPTO-Coupler (817B) Power Supplies (9V, 12V & 5V) PCB Resistances (500, 10k , 10 )

Burning Module and Programming 1 kit Other expenditures -

2000 350

Total= 4450 approx.

52

CHAPTER 7

CONCLUSION & FUTURE ASPECTS

53

CHAPTER 7

CONCLUSION & FUTURE ASPECTS

The 3rd and 5th order harmonics eliminated, two-level cascaded inverter is successfully implemented in hardware. It is giving the expected output. It is well suited for dc-ac conversion from batteries, fuel cells and solar cells. Compared to other multilevel inverter topologies, it requires least no of components. Since the circuit for all the levels are same, optimized circuit layout and packaging are possible. This two-level inverter has only 8 transitions in each cycle, but a PWM inverter of same type needs 10 transitions. Moreover in each transition only half of the voltage is applied across the MOSFET so switching loss is halved. Thus switching loss is substantially reduced compared to PWM inverters.

54

REFERENCES AND BIBLIOGRAPHY

[1] Muhammad H.Rashid (2004) Power electronics Circuits, Devices and Applications, Third Edition, Prentice Hall, India. [2] Muhammad H.Rashid (2001) Power electronics Handbook, Academic press. [3] Roger C.Dugon, Mark F.McGranaghan, Surya santoso, H.Wayne Beaty (2004) Electrical Power Systems Quality, Second Edition, McGraw-Hill. [4] Muhammad Ali Mazidi, Janice Gillispe Mazidi, Rolin D.Mckinlay (2006) The 8051 Microcontroller and Embedded Systems Using Assembly and C, Second Edition, Prentice Hall, India. [5] David A.Bell (2006), Electronic Devices and Circuits, Fourth Edition, Prentice Hall, India. [6] Alberto Lega (2007) Multilevel Converters: Dual Two-Level Inverter Scheme, Ph.D., thesis, Department of Electrical Engineering, University of Bologna [7] Zainal Salam (2003) Design and development of a Stand-alone Multilevel Inverter For Photovoltaic Application, Research Report, Faculty of Electrical Engineering, UTM. [8] Data sheets of MOSFET IRF630, OPTO-COUPLER 817B, P89V51RD2 from www.datasheetcatalog.com

55