Basic Sequential Design Steps

Derive circuit state diagram from design specs Create state table Choose flip-flops Create circuit excitation table Construct K-maps for:
flip-flop inputs primary outputs

Obtain minimized SOP equations Draw logic diagram Simulate to verify design & debug as needed Perform circuit analysis & logic optimization
Sequential Logic Design (11/03) 1

C. E. Stroud

Sequential Design Example

Design a 3-bit gray code counter with active low synchronous reset (R) Inputs Current state Next state State Diagram
0 R=0 R=1 0 1

000

001
0 0

State order: XYZ

1

100
1 0 0 1 0

011
1

101

010
1

111

110

R 0 1 1 1 1 1 1 1 1

(X Y Z) XXX 000 001 010 011 100 101 110 111

(X Y Z) 000 001 011 110 010 000 100 111 101

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State Table
Sequential Logic Design (11/03)

C. E. Stroud

3-bit Gray Code Counter

Choose flipflops:
Let X be a JK Let Y be a D Let Z be a SR
Inputs Current state Next state QX R (X Y Z) (X Y Z) Jx Kx 0 XXX 01 000 1 000 0X 001 1 001 0X 011 1 010 1X 110 1 011 0X 010 1 100 X1 000 1 101 X0 100 1 110 X0 111 1 111 X0 101 QY Dy 0 0 1 1 1 0 0 1 0 QZ Sz Rz 01 10 X0 0X 01 0X 01 10 X0

Create circuit excitation table

C. E. Stroud

Sequential Logic Design (11/03)

3-bit Gray Code Counter (cont)

Generate K-Maps & obtain minimized SOPs
YZ RX 00 01 11 10 00 01 11 X X X X 10 1 Jx = RYZ 01 11 10 1 1 1 1 0 1 0 1 0 YZ YZ RX 00 01 11 10 RX 00 01 11 10 00 00 01 01 11 11 1 X 1 10 10 1 X 1 1 1 Sz = RXY + RXY Dy = RYZ + RXZ YZ RX 00 01 11 10 00 1 1 1 1 Further reductions: 01 1 1 1 1 Rz = R + XY 11 X 1 Sz = R(XY) 10 = (R + XY) 1 X

YZ RX 00 00 1 01 1 11 1 10 X
C. E. Stroud

X X X Kx = R + YZ

= Rz

Rz = R + XY + XY
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Sequential Logic Design (11/03)

3-bit Gray Code Counter (cont)

Logic diagram Next would come design verification via logic simulation
Y Z Y Z X Z
Jx Kx Clk Dy Clk Sz Rz Clk X X Y Y Z Z

Debug as necessary to obtain working R circuit Update logic diagram, logic X equations, etc. Y to reflect fixes
C. E. Stroud

Sequential Logic Design (11/03)

Sequential Logic Models

Huffman model consists of two types:
Mealy model (aka Mealy machine)
Outputs are function inputs and current state
9 Outputs can change when inputs change or when current state changes Primary Inputs Comb Logic Primary Outputs Next State only for Mealy Output Logic Next State Logic Current FlipState Flips Next State
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Current FlipState Flips

Primary Inputs

Moore model (aka Moore machine)

Outputs are function of current state only
9 Outputs can change only when current state changes
C. E. Stroud

Primary Outputs

Sequential Logic Design (11/03)

Mealy & Moore State Diagrams

Mealy model
Outputs associated with state transition Output values shown with inputs
Input / Output

1/1 0/1

00
0/1 0/0 1/0

State order XY

1/1

10

01
States / Output

Moore model
Outputs associated with states only Output values shown with states
C. E. Stroud

1 0

00/1
0 0 1

10/0

01/0
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Sequential Logic Design (11/03)

Mealy & Moore State Tables

1/1 0/1

00
0/1 0/0 1/0

In X Y X+ Y+ DX DY OMealy OMoore
1/1

0 0 0 1 1

0 0 0 1 1 0 0 0 0 1 1 0 1 1

0 1 0 1 0 0 X

1 0 0 0 0 1 X

0 1 0 1 0 0 X

1 0 0 0 0 1 X

1 0 1 1 1 0 X

1 0 0 1 0 0 X

10

01

1 0

00/1
0 0 1

1 0

10/0

01/0

Note: next state (next state logic) is same for both Mealy & Moore only output is different
Sequential Logic Design (11/03) 8

C. E. Stroud

Mealy & Moore Design Examples

XY In 00 01 0 1 0 1 1 0 11 X X 10 0 0 XY In 00 01 0 1 1 1 0 1 11 X X 10 1 0

DX = InY + InXY
XY In 00 01 0 1 0 1 0 0 11 X X 10 0 1

OMealy = InY + InX

XY In 00 01 0 1 0 1 1 0 11 X X 10 0 0

DY = InX + InXY
C. E. Stroud

OMoore = XY
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Sequential Logic Design (11/03)

Mealy & Moore Design Examples

OMealy = InY + InX
In Y X Y X X Y Y X Clk

DX = InY + InXY DY = InX + InXY

In X X Y Y Y X Y X X Y X Y

OMoore = XY
X X Y Clk Y

OMealy

OMoore

Note: OMealy is a function of In but OMoore is not a function of In

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