Code: 12D68101 M.

Tech I Semester Regular Examinations, April/May 2013 ANALOG & DIGITAL IC DESIGN (Common to VLSIES, ESVLSI & VLSIESD) Time: 3 hours Max. Marks: 60 Answer any FIVE questions. All questions carry equal marks. ***** Draw the high frequency equivalent circuit of MOS transfer and explain its operation under three operating regions. (a) (b) Draw and explain simple CMOS current mirror. In the cascade current mirror, where Iin=100 A and each transistor has w/L= 90 /(1.4 ). Given that n cox = 92 2 , = 0.8 v and = [8000 ()] () . Find rout for the current mirror. Iout I
in

Q3

Q1

Q4 rout Q2

3 (a) (b) 4 (a) (b) 5 (a) (b)

Write a short note on: High output impedence current mirror. Bipolar gain stages. Explain: Digital decimation filter. Continuous time filters. Explain dynamic characteristics of CMOS inverter. Consider a CMOS inverter circuit with the following parameters VDD = 3.3 V, VTo,n = 0.6 V, VTo,p = -0.7 v, Kn = 200 2 , Kp = = 800 2 . Calculate the noise margin of the circuit. Explain the following CMOS based design rules: 2 double metal, double poly CMOS rules. 1.2 double metal, single poly CMOS rules.

6 (a) (b) 7 (a) (b)

Draw the mask layout for an 8 1 nMOS inverter circuit. Both the input and output points should be on the polysilicon area. Derive expression for: (i) Sheet resistance. (ii) Area capacitance of layers. Explain any two of the following: Pipeline multiplier array. Modified Booths algorithm. Carry look ahead adders. *****

8 (a) (b) (C)