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Topics

Verilog styles for sequential machines. Flip-flops and latches.

FPGA-Based System Design: Chapter 5

Copyright 2004 Prentice Hall PTR

Verilog always statement

Use always to wait for clock edge:


always @(posedge clock) // start execution at the clock edge begin // insert combinational logic here end

FPGA-Based System Design: Chapter 5

Copyright 2004 Prentice Hall PTR

Verilog state machine


always @(posedge clock) // start execution at the clock edge begin if (rst == 1) begin // reset code end else begin // state machine case (state) state0: begin o1 = 0; state = state1; end state1: begin if (i1) o1 = 1; else o1 = 0; state = state0; endcase end // state machine end
FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR

Traffic light controller

Intersection of two roads:


highway (busy); farm (not busy).

Want to give green light to highway as much as possible. Want to give green to farm when needed. Must always have at least one red light.

FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR

Traffic light system


traffic light highway farm road

sensor

FPGA-Based System Design: Chapter 5

Copyright 2004 Prentice Hall PTR

System operation
Sensor on farm road indicates when cars on farm road are waiting for green light. Must obey required lengths for green, yellow lights.

FPGA-Based System Design: Chapter 5

Copyright 2004 Prentice Hall PTR

Traffic light machine

Build controller out of two machines:


sequencer which sets colors of lights, etc. timer which is used to control durations of lights.

Separate counter isolates logical design from clock period. Separate counter greatly reduces number of states in sequencer.

FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR

Sequencer state transition graph


(cars & long) / 0 green red hwygreen cars & long / 1 green red

short/ 1 red yellow

short / 0 red yellow

farmyellow

hwyyellow

short / 0 yellow red

short / 1 yellow red cars & long / 1 red green farmgreen cars & long / 0 red green
FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR

Verilog model of controller


module sequencer(rst,clk,cars,long,short,hg,hy,hr,fg,fy,fr,count_reset); input rst, clk; /* reset and clock */ input cars; // high when a car is present at the farm road input long, short; /* long and short timers */ output hg, hy, hr; // highway light: green, yellow, red output fg, fy, fr; /* farm light: green, yellow, red */ reg hg, hy, hr, fg, fy, fr; // remember these outputs output count_reset; /* reset the counter */ reg count_reset; // register this value for simplicity // define the state codes define HWY_GREEN 0 define HWY_YX 1 define HWY_YELLOW 2 define HWY_YY 3 define FARM_GREEN 4 define FARM_YX 5 define FARM_YELLOW 6 define FARM_YY 7 reg [2:0] state; // state of the sequencer always @(posedge clk) begin if (rst == 1) begin state = HWY_GREEN; // default state count_reset = 1; end FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR

Verilog model of controller, contd.


else begin // state machine count_reset = 0; case (state) HWY_GREEN: begin if (~(cars & long)) state = HWY_GREEN; else begin state = HWY_YX; count_reset = 1; end hg = 1; hy = 0; hr = 0; fg = 0; fy = 0; fr = 1; end HWY_YX: begin state = HWY_YELLOW; hg = 0; hy = 1; hr = 0; fg = 0; fy = 0; fr = 1; end HWY_YELLOW: begin if (~short) state = HWY_YELLOW; else begin state = FARM_YY; end hg = 0; hy = 1; hr = 0; fg = 0; fy = 0; fr = 1; end FARM_YY: begin state = FARM_GREEN; hg = 0; hy = 0; hr = 1; fg = 1; fy = 0; fr = 0; FPGA-Based System Design: Chapter 5end Copyright 2004 Prentice Hall PTR

Verilog model of timer


module timer(rst,clk,long,short); input rst, clk; // reset and clock output long, short; // long and short timer outputs reg [3:0] tval; // current state of the timer always @(posedge clk) // update the timer and outputs if (rst == 1) begin tval = 4b0000; short = 0; long = 0; end // reset else begin {long,tval} = tval + 1; // raise long at rollover if (tval == 4b0100) short = 1b1; // raise short after 2^2 end // state machine endmodule

FPGA-Based System Design: Chapter 5

Copyright 2004 Prentice Hall PTR

Verilog model of system


module tlc(rst,clk,cars,hg,hy,hr,fg,fy,fr); input rst, clk; // reset and clock input cars; // high when a car is present at the farm road output hg, hy, hr; // highway light: green, yellow, red output fg, fy, fr; // farm light: green, yellow, red wire long, short, count_reset; // long and short // timers + counter reset sequencer s1(rst,clk,cars,long,short, hg,hy,hr,fg,fy,fr,count_reset); timer t1(count_reset,clk,long,short); endmodule
FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR

FARM_GREEN: begin if (cars & ~long) state = FARM_GREEN; else begin state = FARM_YX; count_reset = 1; end hg = 0; hy = 0; hr = 1; fg = 1; fy = 0; fr = 0; end FARM_YX: begin state = FARM_YELLOW; hg = 0; hy = 0; hr = 1; fg = 1; fy = 0; fr = 0; end FARM_YELLOW: begin if (~short) state = FARM_YELLOW; else begin state = HWY_GREEN; end hg = 0; hy = 0; hr = 1; fg = 0; fy = 1; fr = 0; end HWY_YY: begin state = HWY_GREEN; hg = 1; hy = 0; hr = 0; fg = 0; fy = 0; fr = 1; end endcase end // state machine end // always endmodule

FPGA-Based System Design: Chapter 5

Copyright 2004 Prentice Hall PTR

The synchronous philosophy

All operation is controlled by the clock.


All timing is relative to clock. Separates functional, performance optimizations.

Put a lot of work into designing the clock network so you dont have to worry about it throughout the combinational logic.
Copyright 2004 Prentice Hall PTR

FPGA-Based System Design: Chapter 5

Register characteristics
Form of clock signal used to trigger the register. How the behavior of data around the clock trigger affects the stored value. When the stored value is presented at the output. Whether there is ever a combinational path from input to output.

FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR

Types of registers
Latch: transparent when internal memory is being set. Flip-flop: not transparent, reading and changing output are separate.

FPGA-Based System Design: Chapter 5

Copyright 2004 Prentice Hall PTR

Types of registers
D-type (data). Q output is determined by the D input at the clocking event. T-type (toggle). Toggles its state at input event. SR-type (set/reset). Set or reset by inputs (S=R=1 not allowed). JK-type. Allows both J and K to be 1, otherwise similar to SR.

FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR

Clock event

Change in clock signal that controls register behavior.


0-1 transition or 1-0 transition.

Data must generally be held constant around the clock event.

FPGA-Based System Design: Chapter 5

Copyright 2004 Prentice Hall PTR

Setup and hold times


setup clock event hold

changing

stable

time
FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR

Duty cycle

Percentage of time that clock is active.

50%

FPGA-Based System Design: Chapter 5

Copyright 2004 Prentice Hall PTR

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