Code: 9D06106c M.

Tech - I Semester Regular & Supplementary Examinations, April/May 2013 LOW POWER VLSI DESIGN
(Common to DSCE and DECS)

Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 (a) (b) 2 (a) (b) 3 (a) (b) 4 (a) (b) 5

Max Marks: 60

What are the low-voltage, low-power design considerations? Explain. What are the advantages and limitations of silicon-on-insulator technology? What are the BICMOS manufacturing and integration considerations? Explain. How graded drain structure can be produced? Mention the advantages. Give the device structure and describe the fabrication process of low-voltage/lowpower lateral BJT on SOI. With schematic diagrams explain about deep submicron processes. What are the features of HSPICE level 50 (Phillip MOS 69) model? Explain. Discuss in detail about limitations of MOSFET models. Draw the circuit for conventional BICMOS two-input NAND gate and describe its characteristics. Give the comparative evaluation of all the BICMOS circuits employing lateral parasitic PnP BJTs. What are the quality measures for latches and flip-flops? Explain. Explain about power reduction in clock networks. Explain in detail about low power techniques for SRAM. Write short note on the following: Sub-half micron MOS devices. Design perspectives of latches and flip-flops.

6 (a) (b) 7 (a) (b) 8 (a) (b)

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