Chapter 7 -- Modular Sequential Logic

Shift Registers Counters Modulo-N Counters Midterm II: Nov. 1 (Friday) Review: Oct. 30 (Weds) HW 5 due: Oct. 28 (Monday)
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Serial-in, Serial-out Shift Register

Cell n Serial in xn Cell i xi Cell i-1 xi-1 Cell 1 x1 Serial out M S M S M S M S

Shift control pulse

(a)

Serial in

Serial out S CK R Q R Q S CK Q R Q S CK Q Q

Shift (b)

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Shift Register Serial/parallel-in, Serial/parallel-out

Cell n Serial in Parallel out xn Cell i xi Cell i-1 xi-1 Cell 1 Parallel out x1 Serial out M S M S M S M S

Shift control pulse

Parallel in Clock

Parallel in

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Generic Shift Register

Parallel in (Y) Parallel out (X)

Preset: set flip-flop to logic 1 Clear: reset flip-flop to logic 0

Serial in

n-Bit shift register

Serial out

Preset control Shift pulse Clear control (a) Parallel in (Y) Parallel out (X)

n-Bit shift register

Serial out

Serial in

n-Bit shift register

Preset control Shift pulse Clear control Shift pulse Clear control (c)

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(b)

SN74164 Serial-in, Serial-out Shift Register

(9) Clear (8) Clock Serial A inputs B (1) (2)
S Clear R QA CK
QA

Clear R QB CK S
QB

Clear R QC CK S
QC

Clear R QD CK S
QD

Clear R QE CK S
QE

Clear R QF CK S
QF

Clear R QG CK S
QG

Clear R QH CK S
QH

(3) Output QA

(4) Output QB

(5) Output QC (a)

(6) Output QD

(10) Output QE

(11) Output QF

(12) Output QG

(13) Output QH (Serial output)

Clear Serial A inputs B Clock QA QB QC QD QE QF QG Clear (b) Clear

Outputs

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Serial Data Loading Using Shift Register

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Serial Data Loading Using Shift Register

CLK: serial clock input, used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. DATA: serial data input. The serial data is loaded MSB first with the two LSBs being the control bits. LE: load enable. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits.

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Serial Data Loading Using Shift Register Timing Characteristics

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Serial Adder Using Shift Register

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Accumulator Using Shift Register

In

Out

Z-1

xn

x2

x1

...
FA FA HA

Parallel Accumulator

CK CLR

... ...

CK CLR

CK CLR Clear Accumulate

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zn+1 zn

z2 (b)

z1

Synchronous Binary Counter (Fast)

Xn X3 X2 X1

...
Overflow Q CK Q CLR K Q CLR J Q CK K Q CLR J Q CK K Q CLR Clear Count Inhibit J Q CK K J 1

... ...
Xn 0 0 0 0 0 1 1 0 0 0 X3 0 0 0 0 1 1 1 0 0 0 (b) (a)

X2 0 0 1 1 0 1 1 0 0 1

X1 0 1 0 1 0 0 1 0 1 0

X1, toggle every cycle X2, toggle every 2 cycles

Recycles

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Asynchronous Ripple Up Counter (Slow)

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Ripple Up Counter Timing Diagram

Ripple effect causes intermediate states limits the counter speed

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Asynchronous Down Counter (Slow)

Xn 1 0 0 0 0 0 ... ... ... ... ... ... ... X3 1 0 0 0 0 X2 1 0 0 1 1 X1 1 0 1 0 1 0 Xn 0 1 1 1 1 1 ... ... ... ... ... ... ... X3 0 1 1 1 1 X2 0 1 1 0 0 X1 0 1 0 1 0 1

1 0 Up count mode

0 1 Down count mode

(a)

Xn

X2

X1

Down counter
...
Count

Q CK Q CLR

J CK

Q CK

...
K Q

K CLR

Q CLR

K Clock

...
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(b)

Clear

Synchronous Up/Down Counter

Xn X2 X1

... ...
Q Up overflow Q CLR CK K Q CLR J Q CK K Q CLR J Q CK K J 1

Up/down

... ...
Down overflow

... ...

Clock Clear

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Modulo-N Counters
Count from state 0 through state N-1 Cycle back to state 0 after state N-1
Modulo-5 Counter: 5=0101 X2X0=1 clear Modulo-8 Counter: 8=1000 X3=1 clear Modulo-10 Counter: 10=1010 X3X1=1 clear

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Asynchronous BCD Counter

Modulo-10 Counter 10=1010 X3X1=1
Ripple effect causes intermediate states:

N X3 X2 X1 X0 X0 toggle 0 0 0 0 0 then X1 toggle 1 0 0 0 1 Toggle order: 2 0 0 1 0 X0 X1 X2 3 0 0 1 1 4 0 1 0 0 34: 011010000100 5 0 1 0 1

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Digital Timer Block Diagram

60 Hz or crystal oscillator
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Modulo-N Asynchronous Counter

Xn- 1 X1 X0

Count control S Q J CK Q R K Q R Q S J CK K Q R Q CK K S J Count pulse

State detection logic

Clear control

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A modulo-A up counter circuit

Modulus Control

Modulo-A Up Counter

...
A0 A1 T-FF
T Q CLK RST

A2 T-FF
T Q CLK RST

An-1

VDD
T-FF
T Q CLK RST

... ...

T-FF
T Q CLK RST

Reset
Hold Clock

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