1

MN HC
#ng d&ng Vi (i)u khi,n
(Microcontroller Applications)
By Trn V#n Hng
Mechatronics Dept
http://www.ntu.edu.vn/
Email: tvh42th@gmail.com
Ti li.u tham kh/o
1. Microprofessors and microcpmputers hardware and softwware, Ronaid J.Tocci, Frank J.Ambrosio,
Prentice Hall, 2003
2. Interfacing Sensors To The Pc, Willis J.Tompkin, Jonh G.webster, Prentice Hall, 1998
3. Vi x% l, V#n Th( Minh, NXB Gio D+c.
4. H. vi 0i1u khi2n 8051, T4ng V#n On.
5. K5 thu8t Vi 0i1u khi2n AVR, T4ng V#n On.
2
N2i dung ch45ng trnh
n Ch01: Cc h9 0(m v m ho
n Ch02: H9 th4ng vi x% l
n Ch03: B: nh;
n Ch04: H. vi 0i1u khi2n AVR
n Ch05: Ngn ng> l8p trnh CodevisionAVR
n Ch06: Input/Output
Cc bi ton
1. Thi(t k( m?ch 0i1u khi2n nh sng theo ch&<ng trnh 0@nh tr&;c
2. Thi(t k( m?ch trang tr bBng 0n LED
3. Thi(t k( m?ch nh8n d?ng 0i2mph+c v+ (thm t nht 2IC)
4. Thi(t k( m?ch 0o l&Cng m&a
5. Thi(t k( m?ch 0i1u khi2n nhi9t 0: khng kh
6. Thi(t k( m?ch 0i1u khi2n nhi9t 0: dung d@ch
7. Thi(t k( m?ch 0Dng hD 0i9n t%
8. Thi(t k( m?ch tnh thEi gian cho cc mn 0i1n kinh
9. Thi(t k( bGng quang bo
10. Thi(t k( m?ch kho 0i9n t%
11. Thi(t k( m?ch 0i1u khi2n thi(t b@ bBng remote
12. K(t n4i bn phm my tnh v;i VXL, hi2n th@ k tH ln LCD
13. Thi(t k( m?ch 0i1u khi2n Robot ch?y theo qIy 0?o (sd motor b&;c)
14. Thi(t k( m?ch 0i1u khi2n t4c 0: 0:ng c< DC
15. Thi(t k( m?ch 0i1u khi2n gc quay cJa mt<, Kn t4c cho motor.
1
Ch&<ng 1: Cc h9 0(m v m ho
n Cc h9 0(m dng trong my tnh
n Cc php ton s4 h.c 04i v;i h9 hai
n M ASCII
1.1 Cc h9 0(m dng trong my tnh
1.1.1 H9 m&Ei v h9 hai
n Con ng&Ei th quen dng h9 c< s4 m&Ei (h9 m&Ei)
1234,56 = 1.10
3
+ 2.10
2
+ 3.10
1
+ 4.10
0
+ 5.10
-1
+ 6.10
-2
n My tnh th chL lm vi9c v;i h9 c< s4 hai (h9 hai)
1011,01 = 1.2
3
+ 0.2
2
+ 1.2
1
+ 1.2
0
+ 0.2
-1
+ 1.2
-2
n Nibble gDm 4 bit
n Byte gDm 8 bit
n Word gDm 16 bit
0 3
7 0
15 0
MSB LSB
2
1.1.1 Chuy2n 0Ki gi>a h9 m&Ei v h9 hai
n NKi h9 hai sang h9 m&Ei
1011,01
2
= 1.2
3
+ 0.2
2
+ 1.2
1
+ 1.2
0
+ 0.2
-1
+ 1.2
-2
= 11,25
10
n NKi h9 m&Ei sang h9 hai
46
10
= 101110
2
Hnh 1. M:t cch 0Ki h9 m&Ei sang h9 hai
0
1
46 2
23 2
11 2
5 2
2 2
1 2
0
1
1
0
1
1.1.1 Chuy2n 0Ki gi>a h9 m&Ei v h9 hai (ti$p)
n NKi s4 th8p phn h9 m&Ei sang h9 hai
0,125
10
= 0,001
2
n S4 BCD (s4 h9 m&Ei m ho bBng h9 hai)
S4 BCD thch hCp cho cc thi( b@ 0o c hi2n th@ s4 O 0u ra.
1234
10
= 0001 0002 0003 0004
BCD
n H9 m&Ei su
1234
10
= 0100 1101 0010
2
= 4D2
16
0,125 x 2 =
0,250 x 2 =
0,500 x 2 =
,250
,500
,000
0
0
1
3
1.2 Cc php ton s4 h.c 04i v;i h9 hai
1.2.1 Php c:ng
a
n
a
(n-1)
... a
2
a
1
a
0
+ b
m
b
(m-1)
... b
2
b
1
b
0
= c
k
c
(k-1)
... c
2
c
1
c
0
(h9 c< s4 x)
c
i =
(a
i
+ b
i
+ (a
i-1
+ b
i-1
)%x )/x
V d+ c:ng h9 hai
1.2.2 Php trP v s4 b hai
a. Php trP
a
n
a
(n-1)
... a
2
a
1
a
0
- b
m
b
(m-1)
... b
2
b
1
b
0
= c
k
c
(k-1)
... c
2
c
1
c
0
(h9 c< s4 x)
c
i =
(a
i
B
i-1
) b
i
(n(u (a
i
B
i-1
) >= b
i
v B
i
= 0)
c
i =
(a
i
B
i-1
+ x) b
i
(n(u (a
i
B
i-1
) < b
i
v B
i
= 1)
V d+ trP h9 hai
1101 1001
0001 1011
1111 0100
+
1101 1001
0001 1011
1011 1110
-
1.2.2 Php trP v s4 b hai (ti$p)
b. S4 b hai
Ta c th2 thay php trP bBng php c:ng: c:ng s4 b@ trP v;i 04i s4 cJa s4 trP.
N2 tm s4 b hai cJa m:t s4 A ta lm theo cc b&;c sau:
+ Bi2u diQn s4 A s4 h9 hai cJa n.
+ Tm s4 b m:t (b logic) cJa s4 0 (&'o bt).
+ C:ng m:t vo s4 b m:t O trn 02 nh8n 0&Cc s4 b hai cJa A.
1.2.3 Php nhn
V d+ nhn 2 s4 h9 hai c 0: di 4 bt
BGng 1. Quy tSc php nhn
a.b b a
1
0
0
0
1 1
0 1
1 0
0 0
1 0 1 1
0 0 0 0
1 1
0
0
0
1
1
1
1
0
1
0
1
0
0
0
0
0
1
1
1
1
1
4
1.2.2 Php chia
b. Chia trHc ti(p
V d+: 35/5 = 7
b. Chia gin ti(p
LTy s4 b@ chia trP 0i s4 chia, k(t quG sU l s4 b@ chia cJa php ton
ti(p theo, lVp l?i 0(n khi s4 b@ chia nhW h<n s4 chia hoVc bBng 0.
0
1 0 1
1
0
1
1
1
1 0 1
1 1 1
1
0
0
0
0
0
1
0
0
1
1 1
0
1 0 1
1
0 1
0 0
1
Ch&<ng 2: H9 th4ng vi x% l
n Xu v nh&Cc 0i2m h9 nhng
n Vi x% l, vi 0i1u khi2n
n Cc h. vi 0i1u khi2n
n NgSt v x% l ngSt
2.1 T?i sao l?i s% d+ng h9 nhng?
2.1.1 Xu 0i2m
n KhG n#ng thch nghi cao
n Tnh linh 0:ng
n KhG n#ng thay 0Ki dQ dng
n KhG n#ng ti s% d+ng ti nguyn (th& vi9n,)
n Gi thnh rY
n . . .
2.1.2 Nh&Cc 0i2m
n T4c 0: phGn Zng ch8m
n N: Kn 0@nh thTp
n Khng x% l 0&Cc ga tr@ lin t+c
n . . .
2
2.2 Vi 0i1u khi2n, vi x% l
CPU
General-
Purpose
Micro-
processor
RAM ROM
I/O
PORT
Timer,
Wdg,
ADC,
DAC,

USB,
UARST,
I
2
C,
!"! $%&
'(()*&& $%&
TERMINOLOGY
n Microcontroller vs. Microprocessor vs. Microcomputer
n A microprocessor is a central processing unit on a
single chip.
n A microprocessor combined with support circuitry ,
peripheral I/O components and memory (RAM & ROM)
used to be called a microcomputer.
n A microprocessor where all the components mentioned
above are combined on the same single chip that the
microprocessor is on, is called a microcontroller.
3
2.3 Ki(n trc vi 0i1u khi2n
n N<n v@ s% l s4 h.c (ALU)
n B: nh;
n Input
n Output
n N<n v@ 0i1u khi2n
2.3.1 N<n v@ x% l s4 h.c (ALU)
n ThHc hi9n php ton v php logic trn d> li9u
n D> li9u c th2 lTy trn b: nh; hoVc I/O
n K(t quG c th2 0&Cc 0&a ra ngoi hoVc vo b: nh;
(k(t quG 0&Cc l&u l?i)
General
Purpose
Registrers
ALU
4
2.3.2 B: nh;
n L&u tr> l9nh hay d> li9u
n C th2 02 l&u tr> d> li9u t?m thEi
n C th2 ghi/0.c 0&Cc bOi b: 0i1u khi2n
Program Flash
(4K x 16)
Program Memory
$000
$FFF
32 Gen. Purpose
Working Resisters
64 I/O Resisters
Internal SRAM
(512 x 8)
$025F
$005F
$0060
$001F
$0020
$0000
Data Memory
EEPROM
(512 x 8)
Data Memory
$000
$1FF
2.3.3 Input
n Thi(t b@ cho php thng tin v d> li9u vo bn trong
b: vi 0i1u khi2n
n V d+: ADC, I
2
C, UART,
2.3.4 Output
n Thi(t b@ chuy2n 0Ki thng tin v d> li9u tP b: nh; ra
thi(t b@ ngo?i vi.
n Thi(t b@ ngo?i vi: LED, LCD, my in,
5
2.3.5 N<n v@ 0i1u khi2n
n Cung cTp xung nh@p v 0i1u khi2n tn hi9u
n Tm n?p l9nh v d> li9u
n Chuy2n d> li9u t;i/tP I/O
n GiGi m l9nh
n ThHc hi9n php tnh s4 h.c/logic
n Np Zng tn hi9u ngoi (Reset/NgSt)
2.3.6 M:t s4 h. vi 0i1u khi2n
n Vi 0i1u khi2n 8051
n 8051, 89Cxx, 89Sxx, 89Dxx,
n Vi 0i1u khi2n AVR
n AVR 8 bt, AVR 16 bt,
n Vi 0i1u khi2n PIC
n PIC 8 bt, PIC 16 bt,
n Vi 0i1u khi2n MCUs cJa Philips
n P8xCxx,
n
6
2.3.6 Cc h. vi 0i1u khi2n (ti$p so snh)
n T4c 0: x% l (clock, clock cycle execution)
n KhG n#ng tch hCp (ADC, DAC, UART, I
2
C,)
n DGi 0i9n p ho?t 0:ng (Operating Voltages)
n Cng suTt 0u ra (DC current per I/O pin)
n KhG n#ng ch4ng nhiQu (Noise Reduction)
n T8p l9nh (Instruction)
n Cng suTt IC (Power consumption)
n . . .
2.4 NgSt v x% l ngSt (Interrupt)
2.4.1 Khi ni9m
n NgSt l sH dPng thHc hi9n ch&<ng trnh chnh (CTC) 02
thHc hi9n ch&<ng trnh con ph+ v+ ngSt(ctc)
n: IRQ
i
n + 1:
m: IRQ
j
m + 1:
Main Prog
ISR
i
ISR
j
iret
iret
7
2.4.2 CTu trc ngSt
n XuTt hi9n khng 0&Cc bo tr&;c
n Ph+c v+ gn gi4ng ch&<ng trnh con
n Tch hCp nhi1u lo?i ngSt
n C &u tin ngSt
2.4.3 X% l ngSt
n XuTt hi9n v cho php ngSt
n Hon thnh l9nh hi9n t?i
n L&u tr> 0@a chL l9nh ti(p theo vo ng#n x(p
n N?p 0@a chL ISR vo PC
n ThHc hi9n ISR
n K(t thc ISR l l9nh RETI
n Khi ph+c 0@a chL l9nh ti(p theo trong ng#n x(p,
ch&<ng trnh ti(p t+c thHc hi9n
8
2.4.4 Phn lo?i ngSt
n NgSt m1m (software interrupt)
L vi9c g.i 1 ctc (Subroutine) 0&Cc xy dHng ring m ctc
ny cn c th2 0&Cc g.i bOi thi(t b@ ngo?i vi
n NgSt cZng (hardware interrupt)
Do port pht tn hi9u 0(n CPU
n NgSt trong (internal interrupt)
Trong m:t s4 CPU 02 b[y/x% l cc sH ki9n trong khi thHc
hi9n
n Ngo?i l9 (exceptions)
L vTn 01 hay 0i1u ki9n 02 CPU dPng cng vi9c 0ang thHc
hi9n, tm 0@a chL v thHc hi9n 1 ctc, 0&Cc thi(t k( 02 x% l sH
ki9n ny.
1
Ch&<ng Ch&<ng 3: B 3: B: : nh nh; ;
n n B B: : nh nh; ; b b n d n d[ [n n
n n Gi GiG Gi m 0 i m 0@ @a ch a chL L cho b cho b: : nh nh; ;
n n Ph Ph4 4i gh i gh p b p b: : nh nh; ;
n n M MO O r r: :ng b ng b: : nh nh; ;
3.1 B 3.1 B2 2 nh nh6 6 b b n d n d7 7n n
n n C C c nh c nh m t m t n hi n hi9 9u u
n n ROM ( ROM (read only memory read only memory) )
n n RAM ( RAM (random access memory random access memory) )
ROM
Read
Only
Memory
RAM
Radom
Access
Memory
PROM
EPROM
EEPROM
Programmable ROM
Erasable PROM
Electrically EPROM
SRAM
Static RAM
DRAM
Dynamic RAM
CACHE
L
1
, L
2
, L
3
Memory
2
3.1.1 C 3.1.1 C c nh c nh m t m t n hi n hi. .u u
A
0
A
1
A
2
A
n
.
.
.
D
0
D
1
D
2
D
m
.
.
.
CS
WE
OE
RD
WR
Select IC
Address
Data
Hnh 3. S< 0D kh4i cJa b: nh;
a. Nh a. Nh m t m t n hi n hi. .u ( u (9 9a ch a ch; ;
n n C C t t c d c d+ +ng ch ng ch. .n ra m n ra m: :t nh t nh; ; c c+ + th th2 2
n n S S4 4 0& 0&E Eng 0 ng 0@ @a ch a chL L s sU U quy quy( (t 0 t 0@ @nh c nh c t t4 4i 0a bao nhiu i 0a bao nhiu
nh nh; ;. V . V d d+ + c c m 0& m 0&E Eng 0 ng 0@ @a ch a chL L v v8 8y th y th t t4 4i 0a i 0a 2 2
m m
nh nh; ;. .
b. Nh b. Nh m t m t n hi n hi. .u d u d= = li li. .u u
n n Th& Th&E Eng l ng l 0 0 u ra c u ra cJ Ja ROM v a ROM v l l v v o/ra o/ra 0 04 4i v i v; ;i RAM i RAM
n n C C c m c m? ?ch nh ch nh; ; th& th&E Eng c ng c 0 0 u v u v o/ra l o/ra l 3 tr 3 tr? ?ng th ng th i. i.
n n S S4 4 0& 0&E Eng dy d ng dy d> > li li9 9u quy u quy( (t 0 t 0@ @nh 0 nh 0: : d d i t i tP P nh nh; ; c cJ Ja a
m m\ \i nh i nh; ;. .
3
c. Nh c. Nh m t m t n hi n hi. .u ch u ch? ?n vi m n vi m@ @ch ch
n n Ch Ch. .n vi m n vi m? ?ch s ch sU U trao 0 trao 0K Ki d i d> > li li9 9u. u.
n n C C c t c t n hi n hi9 9u n u n y th& y th&E Eng 0& ng 0&C Cc n c n4 4i v i v; ;i 0 i 0 u ra c u ra cJ Ja b a b: :
gi giG Gi m 0 i m 0@ @a ch a chL L. .
n n Vi m Vi m? ?ch khng 0& ch khng 0&C Cc ch c ch. .n th n th bus d bus d> > li li9 9u c u cJ Ja n a n b b@ @
treo ( treo (O O tr tr? ?ng th ng th i tr i trO O kh kh ng cao). ng cao).
d. Nh d. Nh m t m t n hi n hi. .u (i u (i) )u khi u khi, ,n n
n n Cho ph Cho ph p d p d> > li li9 9u ra bus. u ra bus.
n n Bus d Bus d> > li li9 9u b u b@ @ treo n treo n( (u khng c u khng c t t n hi n hi9 9u 0i u 0i1 1u khi u khi2 2n. n.
n n M M? ?ch th& ch th&E Eng ch ng chL L c c m m: :t t t t n hi n hi9 9u 0i u 0i1 1u khi u khi2 2n 0 n 0. .c/ghi. c/ghi.
3.1.2 ROM 3.1.2 ROM
n n B B: : nh nh; ; c c n n: :i dung 0 ghi s i dung 0 ghi s] ]n ch n chL L 0 02 2 0 0. .c ra c ra
n n Ch ChL L n n? ?p v p v o m o m: :t l t l n duy nh n duy nhT Tt t
n n Khng b Khng b@ @ m mT Tt thng tin khi m t thng tin khi mT Tt 0i t 0i9 9n n
A
0
A
1
A
2
A
n
.
.
.
D
0
D
1
D
2
D
m
.
.
.
CS
WE
OE
RD
WR
Select IC
Address
Data
Hnh 3. B: nh; ROM
4
3.1.3 ROM c 3.1.3 ROM c th th, , l lA Ap tr p tr nh (4 nh (4B Bc c
a. PROM ( a. PROM (Programmable ROM Programmable ROM) )
n n Th ThE Ei gian truy c i gian truy c8 8p nhanh 120 p nhanh 120- -250ns 250ns
n n Ch ChL L n n? ?p m p m: :t l t l n duy nh n duy nhT Tt b t bB Bng c ng c c 0 c 04 4t ch t ch y c y c c c c c u ch u ch
n n Ni Ni9 9n n p khi l p khi l8 8p tr p tr nh kho nh khoG Gng 10 ng 10- -13V 13V
A0
D0
Address
decoder
Address
Bus
A1
A2
VCC
D2 D1
b. EPROM ( b. EPROM (erasable PROM erasable PROM) )
n n Th ThE Ei gian truy c i gian truy c8 8p kho p khoG Gng 120 ng 120 450 450 ns ns
n n Ni Ni9 9n n p l p l8 8p tr p tr nh kho nh khoG Gng 10 ng 10- -25V 25V
n n N N c c th th2 2 0& 0&C Cc xo c xo to to n b n b: : b bB Bng tia c ng tia cH Hc t c t m. m.
n n Th ThE Ei gian l i gian l8 8p tr p tr nh cho m nh cho m: :t nh t nh; ; lu (kho lu (khoG Gng 50ms) ng 50ms)
5
c. EEPROM ( c. EEPROM (electrically EPROM electrically EPROM) )
n n Xo Xo t tP Png 0<n v ng 0<n v@ @ nh nh; ; b bB Bng 0i ng 0i9 9n, khng c n, khng c n tia c n tia cH Hc t c t m. m.
n n Th ThE Ei gian l i gian l8 8p tr p tr nh cho m nh cho m: :t nh t nh; ; kho khoG Gng 5ms. ng 5ms.
d. Flash memory d. Flash memory
n ThEi gian truy c8p nhanh (khoGng 120ns).
n ThEi gian ghi nhanh 10s
n Xa tPng kh4i nh;
6
3.1.4 RAM 3.1.4 RAM
n B@ mTt d> li9u khi mTt 0i9n.
n ThEi gian truy c8p nhanh (c lo?i 15ns).
Register 62 Register 62
Register 63 Register 63
. .
. .
. .
Register 2 Register 2
Register 1 Register 1
Register 0 Register 0
Decoder
6 line to 64 line
A
d
d
r
e
s
s

i
n
p
u
t
R/W
Input buffers
Output buffers
CS
Hnh 3. CTu t?o bn trong cJa 64 x 4 RAM
3.1.4 RAM ( 3.1.4 RAM (ti ti$ $p p) )
n SRAM (static RAM)
n Ch( t?o 0<n giGn
n DQ dng bGo tr
n Th&Eng 0&Cc s% d+ng trong h9 th4ng c b: nh; nhW
n DRAM(dynamic RAM)
n Gi thnh thTp
n Ni hWi m?ch ph+ trC
n PhGi lm t&<i (refresh) th&Eng xuyn
n Th&Eng 0&Cc s% d+ng trong h9 th4ng c b: nh; l;n
7
3.2 Gi 3.2 Gi/ /i m ( i m (9 9a ch a ch; ; cho b cho b2 2 nh nh6 6
n n Phn 0 Phn 0@ @nh khng gian t nh khng gian tK Kng th ng th2 2 th th nh c nh c c v c v ng nh ng nh; ; kh kh c nhau c nhau
n n N NG Gm b m bG Go t o t nh 0<n tr nh 0<n tr@ @ c cJ Ja xung ch a xung ch. .n n
n n Khi thi Khi thi( (t k t k( ( th& th&E Eng c ng c d dH H phng ( phng (spare spare) ) 0 02 2 c c th th2 2 m mO O r r: :ng ng
m m khng ph khng phG Gi thi i thi( (t k t k( ( l l? ?i m i m? ?ch. ch.
M?ch giGi
m 0@a chL
Tn hi9u 0@a chL
Tn hi9u 0i1u khi2n
Cc tn hi9u chon chip
Hnh 3. M?ch giGi m 0@a chL
3.2.1 Gi 3.2.1 Gi/ /i m b i m bC Cng c ng c c m c m@ @ch NAND ch NAND
n n M M? ?ch gi ch giG Gi m 0 i m 0@ @a ch a chL L 0<n gi 0<n giG Gn v n v; ;i 0 i 0 u ra h u ra h? ?n ch n ch( (
Memory
A
0
A
10
D
0
- D
7
A
11
A
19
IO/M
CE OE
RD
Hnh 3. M?ch giGi m 0<n giGn dng NAND
8
3.2.2 Gi 3.2.2 Gi/ /i m b i m bC Cng c ng c c m c m@ @ch 74138 ch 74138
n n L L m m? ?ch gi ch giG Gi m 3 i m 3 0 0 u v u v o, o, 8 8 0 0 u ra u ra
Memory
A
0
A
12
D
0
D
7
A
13
A
15
IO/M
CE OE
RD
74LS138
A
B
C
G1
6
G2A
4
G2B
5
Y0
15
Y1
14
Y2
13
Y3
12
Y4
11
Y5
10
Y6
9
Y7
7
A
19
A
16
A
18
Hnh 3. S< 0D giGi m dng 74LS138
3.2.2 Gi 3.2.2 Gi/ /i m b i m bC Cng c ng c c m c m@ @ch 74138 ch 74138 ( (ti ti$ $p p) )
n n M MZ Zc t c t ch c ch cH Hc l c l m mZ Zc 0 c 0
n n Ch ChL L duy nh duy nhT Tt m t m: :t 0 t 0 u ra u ra O O m mZ Zc t c t ch c ch cH Hc c
9
3.2.3 Gi 3.2.3 Gi/ /i m d i m d ng ROM ng ROM
n n C C ng m ng m: :t ch t chZ Zc n#ng nh& c n#ng nh& 74138 74138
n n Gi GiG Gm thi m thi2 2u s u s4 4 m m? ?ch ph ch ph+ + tr trC C
Memory
A
0
A
12
D
0
D
7
A
13
A
19
IO/M
CE OE
RD
G1
Y0
15
Y1
14
Y2
13
Y3
12
Y4
11
Y5
10
Y6
9
Y7
7
A0
A1
A2
A3
A4
A5
A6
A7
Hnh 3. S< 0D giGi m dng PROM
3.2.3 Gi 3.2.3 Gi/ /i m d i m d ng ROM ( ng ROM (ti ti p p) )
n n Ch ChL L s s% % d d+ +ng 8 ng 8 byte 0 byte 0 u tin, c u tin, c c byte kh c byte kh c 0 c 01 1u ch u chZ Za c a c ng ng
m m: :t gi t gi tr tr@ @ FFh FFh
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C c 0 c 0@ @a ch a chL L kh kh c c 0 0
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0
1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0
1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0
1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
O O
0 0
O O
1 1
O O
2 2
O O
3 3
O O
4 4
O O
5 5
O O
6 6
O O
7 7
A A
0 0
A A
1 1
A A
2 2
A A
3 3
A A
4 4
A A
5 5
A A
6 6
A A
7 7
G G
C C c 0 c 0 u ra u ra C C c 0 c 0 u v u v o o
10
RD
IO/M
Memory
A
0
A
11
A
12
A
14
74LS138
A
B
C
G1
6
G2A
4
G2B
5
Y0
15
Y1
14
Y2
13
Y3
12
Y4
11
Y5
10
Y6
9
Y7
7
+Vcc
A
15
A
19
D
0
D
7
FF000-FFFFF
F8000-F8FFF
Hnh 3. Ph4i ghp b: nh;
B t$o xung tr&
Ready
CS
3.3 Gh 3.3 Gh p n p nE Ei b i b2 2 nh nh6 6
n n N N@ @nh 0 nh 0@ @a ch a chL L c c c nh c nh; ;. .
n n Dung l& Dung l&C Cng b ng b: : nh nh; ;. .
n n T T4 4c 0 c 0: : b b: : nh nh; ; ko 0 ko 0 p p Z Zng 0&<c t ng 0&<c t4 4c 0 c 0: : VNK th VNK th ta ph ta phG Gi c i c
m m? ?ch t#ng thm chu k ch t#ng thm chu k^ ^ 0 0C Ci i
CE OE
3.3 Gh 3.3 Gh p n p nE Ei b i b2 2 nh nh6 6 ( (ti ti$ $p p) )
n n S S% % d d+ +ng b ng b: : d dD Dn knh 0 n knh 02 2 gi giG Gm s m s4 4 chn chn, , t#ng dung l& t#ng dung l&C Cng b ng b: :
nh nh; ; ln ln
128 x 128
Cell array
R/W
Data in
Data out
Column address decoder
7 bit
Column address register
Row
address
decoder
7 bit
Row
address
register
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9 A
10
A
11
A
12
A
13
-----------
|
|
|
|
|
|
|
|
A
0
/ A
7
A
6
/A
13
A
0
/A
7
-------
A
6
/A
13
RAS
CAS
Hnh 3. Ki(n trc cJa b: nh; 4116
11
3.4 M 3.4 MG G r r2 2ng b ng b2 2 nh nh6 6
3.4.1 M 3.4.1 MG G r r2 2ng k ng k ch th4 ch th46 6c nh c nh6 6
Hnh 3. K(t hCp hai b: nh; 16 x 4 thnh 16 x 8
Address bus (AB
0
AB
3
)
Data bus (DB
0
DB
7
)
RAM-0
16 x 4
R/W
CS
I/0
3
I/0
2
I/0
1
I/0
0
A
3
A
2
A
1
A
0
RAM-1
16 x 4
R/W
CS
I/0
3
I/0
2
I/0
1
I/0
0
A
3
A
2
A
1
A
0
R/W
CS
3.4.1 M 3.4.1 MG G r r2 2ng k ng k ch th4 ch th46 6c nh c nh6 6 ( (ti ti$ $p p) )
Hnh 3. K(t hCp b4n b: nh; 2K x 8 thnh 2K x 32
Address bus (AB
0
AB
10
)
Data bus (DB
0
DB
31
)
RAM-0
2K x 8
I/0
0
- I/0
7
R/W
CS
RAM-1
2K x 8
I/0
8
- I/0
15
R/W
CS
RAM-2
2K x 8
I/0
16
- I/0
23
R/W
CS
RAM-3
2K x 8
I/0
24
- I/0
31
R/W
CS
12
3.4.2 M 3.4.2 MG G r r2 2ng dung l4 ng dung l4B Bng nh ng nh6 6
Hnh 3. K(t hCp hai b: nh; 16 x 4 thnh 32 x 4
Address bus (AB
0
AB
3
)
Data bus (DB
0
DB
3
)
RAM-0
16 x 4
R/W
CS
I/0
3
I/0
2
I/0
1
I/0
0
A
3
A
2
A
1
A
0
RAM-1
16 x 4
R/W
CS
I/0
3
I/0
2
I/0
1
I/0
0
A
3
A
2
A
1
A
0
R/W
AB
4
1
Ch&<ng 4: H. vi 0i1u khi2n AVR
n Gi;i thi9u chung
n Cc chZc n#ng 0i1u khi2n
n T8p l9nh v ngn ng> l8p trnh
4.1 Gi;i thi9u chung
n AVR - Ki(n trc RISC
n KhoGng h<n 100 l9nh, hu h(t thHc hi9n m:t chu k^ my
n 32 thanh ghi 0a n#ng 8 bit
n C th2 ln t;i 16 MIPS t?i tn s4 16MHz
n B: nh; :
n 8..256K Flash Mem cho ch&<ng trnh, ghi/xo 0&Cc 10.000
ln
n 512..4K Byte EEPROM, ghi/xo 100.000
n 5128K Byte SRAM
2
4.1 Gi;i thi9u chung (ti$p)
n Cc modul vo ra (I/O moduls)
n ADC 10bit v tP 8..16 knh Analog
n 1 0(n 2 Programmable UART
n Master/Slave ISP Serial Interface
n 3..4 Timer/Counter: 1 x 16 bit, 2 x 8 bit
n WatchDog Timer
n Analog Comparator
n PWM
n Cng suTt (Power Management):
- 3 ch$ &) ngh, (Sleep Mode):
n Idle : 1.9 mA
n Power-Down: <1A
n PowerSave
n (ch( 0: ch?y bnh th&Eng: 6mA)
4.1 Gi;i thi9u chung (ti$p)
.i0n p lm vi0c :
n Vcc 4.0-6.0V v;i AT90S8535
n Vcc 2.7-6.0V v;i AT90LS8535
T1n s2 CLOCK
n 0-8MHz v;i AT90S8535
n 0-4MHz v;i AT90LS8535
n 0-16MHz v;i Atmegaxx
3
4.1 Gi;i thi9u chung (ti$p)
4.1.1 Cc b: nh;
Program Flash
(4K x 16)
Program Memory
$000
$FFF
32 Gen. Purpose
Working Resisters
64 I/O Resisters
Internal SRAM
(512 x 8)
$025F
$005F
$0060
$001F
$0020
$0000
Data Memory
EEPROM
(512 x 8)
Data Memory
$000
$1FF
4
4.1.1 Cc b: nh; (ti$p)
Data Address Space
$001F
$001E

$0001
$0000
$005F
$005E

$0021
$0020
Internal SRAM
$085F
$085E

$0061
$0060
Register File
R31
R30

R2
R1
I/O Register
$3F
$3E

$01
$00
ZL
ZH
SRAM Organization
4.1.2 Cc thanh ghi 0a n#ng
a. Cc thanh ghi 0a n#ng
n Bao gDm 32 thanh ghi 8 bit
n N&Cc thHc hi9n trHc ti(p tP ALU
n Cc cVp thanh ghi R
26
,
27
; R
28
,
29
; R
30
,
31
t?o thnh cc thanh
ghi 16 bit
5
b. Cc thanh ghi ng#n x(p
n N2 l&u tr> d> li9u tam thEi, v@ tr bi(n v 0@a chL trO
v1 sau khi ph+c v+ ch&<ng trnh con ngSt v ch&<ng
trnh con
n Lun trW vo 0Lnh cJa ng#n x(p
n Ng#n x(p lun bSt 0u tP v@ tr cao cJa b: nh;
c. Cc thanh ghi tr?ng thi
n ChZa thng tin hi9n t?i cJa CPU
n C 8 bit chZa thng tin
n Thng tin c th2 b@ thay 0Ki khi c ch&<ng trnh con
ph+c v+ ngSt
6
d. Thanh ghi che ngSt v cE ngSt
n Cho php hay khng cho php m:t ngSt bTt k^
n Thng bo khi c ngSt, n(u ngSt 0 0 0&Cc php
n Thanh ghi che ngSt 0&Cc thi(t l8p bBng phn m1m
e. Thanh ghi 0i1u khi2n
n Cho php 0i1u khi2n ton b: vi 0i1u khi2n
n ChZc n#ng ny gDm:
n Truy c8p b: nh; SRAM
n Ch( 0: ngJ
n Ch( 0: ngSt ngoi
7
f. M:t s4 thanh ghi khc
n Thanh ghi tr?ng thi b: x% l
n Cc thanh ghi 0i1u khi2n timer/counter0
n Cc thanh ghi 0i1u khi2n timer/counter1
n Thanh ghi 0i1u khi2n Watchdog
n Cc thanh ghi 0i1u khi2n vo ra EEPROM
n Cc thanh ghi 0i1u khi2n SPI
n Cc thanh ghi 0i1u khi2n UART
n Cc thanh ghi 0i1u khi2n b: ADC
4.1.3 NgSt v x% l ngSt
Store Program Memory Ready SPM_RDY $028 21
Two-wire Serial Interface TWI $026 20
Analog Comparator ANA_COMP $024 19
EEPROM Ready EE_RDY $022 18
ADC Conversion Complete ADC $020 17
USART, Tx Complete USART, TXC $01E 16
USART Data Register Empty USART, UDRE $01C 15
USART, Rx Complete USART, RXC $01A 14
Serial Transfer Complete SPI, STC $018 13
Timer/Counter0 Overflow TIMER0 OVF $016 12
Timer/Counter0 Compare Match TIMER0 COMP $014 11
Timer/Counter1 Overflow TIMER1 OVF $012 10
Timer/Counter1 Capture Match B TIMER1 COMPB $010 9
Timer/Counter1 Capture Match A TIMER1 COMPA $00E 8
Timer/Counter1 Capture Event TIMER1 CAPT $00C 7
Timer/Counter2 Overflow TIMER2 OVF $00A 6
Timer/Counter2 Compare Match TIMER2 COMP $008 5
External Interrupt Request 2 INT2 $006 4
External Interrupt Request 1 INT1 $004 3
External Interrupt Request 0 INT0 $002 2
External Pin, Power-on Reset, Brown-out Reset,
Watchdog Reset and JTAG AVR Reset
Reset $000 1
Interrupt Difinition Source ProgramAddress Vector No.
8
4.1.3 NgSt v x% l ngSt (ti$p)
n 16 vect< ngSt (2 Byte)
n TP 0@a chL $000 trong b: nh; ch&<ng trnh
n NgSt c chL s4 thTp, 0: &u tin cng cao
n M\i ngSt c m:t bt cho php ngSt ring
n N2 s% d+ng m:t ngSt th bit ny phGi thi(t l8p cng
v;i cE I (Global Interrupt Enable) trong thanh ghi
SREG 0&Cc thi(t l8p
n MTt 4 chu k^ 0Dng hD 02 vo (hoVc ra khWi) ch&<ng
trnh con phHc v+ ngSt
4.1.3 NgSt v x% l ngSt (ti$p)
n I Global Interrupt Enable
n T Bit Copy Storage
n H Haft Carry Flag
n S Sign Bit S = N_V
n V Overflow Flag
n N Negative Flag
n Z Zero Flag
n C Carry Flag
0 0 0 0 0 0 0 0 Initial Value
R/W R/W R/W R/W R/W R/W R/W R/W Read/Write
SREG C Z N V S H T I $3F ($5F)
0 1 2 3 4 5 6 7 Bit
9
4.2 Cc chZc n#ng 0i1u khi2n
n Timer/Counter
n WatchDog Timer
n Cc cKng vo ra
n ADC
n UART
n EEPROM
4.2.1 Timer/Counter
C 3 b: 0(m/0@nh thEi gian
n T/C0 :
n 8 bit
n NguDn 0Dng hD tP m?ch chia thEi gian hoVc tP chn T0
(theo s&En ln/xu4ng)
n NgSt trn
n T/C1:
n 16 bit
n NguDn 0Dng hD tP m?ch chia thEi gian hoVc tP chn T1
(theo s&En ln/xu4ng)
n C ngSt trn, ngSt thch Zng so snh v ngSt cho php bSt
tn hi9u tP chn ICP
10
4.2.1 Timer/Counter (ti$p)
n T/C2:
n 8 bit
n NguDn 0Dng hD tP m?ch chia thEi gian hoVc tP dao 0:ng
bn ngoi (chn TOSC1 v TOSC2 n4i v;i t+ th?ch
anh 32768Hz)
n C ngSt trn v ngSt thch Zng so snh
n Cho php 0&a tn hi9u ra chn OC2 khi c tn hi9u thch
Zng so snh
4.2.2 WatchDog Timer
Processor
Watchdog Timer
Clock
Restart
Reset
11
4.2.2 WatchDog Timer (ti$p)
n Ho?t 0:ng tP b: dao 0:ng 0:c l8p trn chip
n L9nh WDR 02 Reset l?i WatchDog Timer
n Sau khoGng thEi gian > time_out ch&<ng trnh sU b@
Reset l?i
n Thanh ghi 0i1u khi2n: WDTCR
0 0 0 0 0 0 0 0 Initial Value
R/W R/W R/W R/W R/W R R R Read/Write
WDTCR WDP0 WDP1 WDP2 WDE WDTOE ` ` ` $21 ($41)
0 1 2 3 4 5 6 7 Bit
4.2.2 WatchDog Timer (ti$p)
n WDP2, WDP1, WDP0 : xc 0@nh thEi gian time_out
2.1s 2.2s 2M 1 1 1
1.0s 1.1s 1M 0 1 1
0.52s 0.55s 512K 1 0 1
0.26s 0.27s 256K 0 0 1
0.13s 0.14s 128K 1 1 0
65ms 68.5 64K 0 1 0
32.5ms 34.3ms 32K 1 0 0
16.3ms 17.1ms 16K 0 0 0
Typical Time_out
at V
cc
= 5.0V
Typical Time_out
at V
cc
= 3.0V
Number of WDT
Oscillator Cycles
WDP0 WDP1 WDP2
12
4.2.2 Cc cKng vo ra
4.2.2 Cc cKng vo ra (ti$p)
n C 4 cKng vo ra 8 bit PA, PB, PC, PD
n M\i cKng 01u c 3 thanh ghi (8 bit), v d+ cKng A :
n Thanh ghi d> li9u : PORTA
n Thanh ghi 0i1u khi2n h&;ng d> li9u : DDRA
n Thanh ghi 0@a chL cc chn vo : PINA
n Cho php thao tc vo ra trn tPng bt (m:t cKng c
th2 vPa c bit vo vPa c bit ra)
n bit DDRAi=1, chn PAi l chn ra ( = PORTAi)
n bit DDRAi=0, chn PAi l chn vo (= PINAi)
13
4.2.2 Cc cKng vo ra (ti$p)
n PhGi 0@nh nghaa cKng tr&;c khi s% d+ng
n KhG n#ng ch@u tGi cao (I
sink
khoGng 20mA/Pin)
n Vo ra ba tr?ng thi
n C khG n#ng vo t&<ng tH
n Pull_up, I = 33A160A
4.2.3 ADC
n NVc 0i2m:
n N: phn giGi t4i 0a 10 bit, xTp xL lin ti(p
n N: chnh xc tuy9t 04i 0(n 2 LSB
n ThEi gian chuy2n 0Ki: 65-260 s, 13 chu k^ cho m:t ln
chuy2n 0Ki
n 2 ch( 0: ho?t 0:ng: chuy2n 0Ki 0<n v chuy2n 0Ki tH do
n Cc thanh ghi
n Thanh ghi d> li9u: ADCL, ADCH
14
4.2.3 ADC (ti$p)
n Thanh ghi ch.n knh : ADMUX
n Thanh ghi 0i1u khi2n tr?ng thi: ADCSRA
0 0 0 0 0 0 0 0 Initial Value
R/W R/W R/W R/W R/W R/W R/W R/W Read/Write
ADMUX MUX0 MUX1 MUX2 MUX3 MUX4 ADLAR REFS0 REFS1 $21 ($41)
0 1 2 3 4 5 6 7 Bit
0 0 0 0 0 0 0 0
Initial
Value
R/W R/W R/W R/W R/W R/W R/W R/W Read/Write
ADCSRA ADPS0 ADPS1 ADPS2 ADIE ADIF ADATE ADSC ADEN $21 ($41)
0 1 2 3 4 5 6 7 Bit
4.2.4 USART
n NVc 0i2m:
n Truy1n song cng
n Truy1n 0Dng b: hoVc khng 0Dng b:
n Master hoVc Slave cTp xung nh@p
n Khun d?ng d> li9u 0a d?ng (5=>9 bit d> li9u, 1 hoVc 2
bt dPng)
n Ki2m tra bit ch]n lY bBng phn cZng
n TH pht hi9n l\i trn d> li9u, khung d> li9u l\i
n KhG n#ng l.c nhiQu
n 3 ngSt truy1n, nh8n v truy1n h(t
n Nhi1u ch( 0: k(t n4i
n KhG n#ng nhn 0i t4c 0: truy1n thng
15
4.2.4 USART (ti$p)
n Cc thanh ghi
n Thanh ghi t4c 0: Baud : UBRR
n VD: fck = 4MHz,cn t4c 0: 14400bps
n UBRR =16 (16.3), t4c 0: thHc t( l 14705bps, l\i 2.1%
n Khng nn s% d+ng t4c 0: c l\i > 1%
16 * (UBRR + 1)
F
clk
BaudRate =
4.2.4 USART (ti$p)
n Thanh ghi d> li9u: UDR (gDm hai thanh ghi 0:c l8p c cng
0@a chL vo ra): chZa d> li9u nh8n v truy1n
n Thanh ghi 0i1u khi2n v tr?ng thi: UCSR
(Control and Status Register)
0
R/W
MPCM
0
UCSRA
0 0 0 0 1 0 0 Initial Value
R/W R R R R R/W R Read/Write
U2X PE DOR FE UDRE TXC RXC $0B ($2B)
1 2 3 4 5 6 7 Bit
0
R/W
TXB8
0
UCSRB
0 0 0 0 0 0 0 Initial Value
R R/W R/W R/W R/W R/W R/W Read/Write
RXB8 UCSZ2 TXEN RXEN UDRUE TSCIE RXCIE $0A ($2A)
1 2 3 4 5 6 7 Bit
16
4.2.4 USART (ti$p)
Ho?t 0:ng:
n Thi(t l8p t4c 0: truy1n, 8/9 bit d> li9u, truy1n/nh8n
hoVc cG hai, c s% d+ng ngSt hay khng?
n Truy1n d> li9u:
n N&a byte d> li9u cn truy1n vo UDR
n NCi 0(n khi UDRE = 1 (hoVc s% d+ng ngSt) th truy1n t(p
byte ti(p theo
4.2.4 USART (ti$p)
n Nh8n d> li9u:
n NCi 0(n khi cE RXC=1 (hoVc s% d+ng ngSt) bo hi9u nh8n
0&Cc byte d> li9u
n Ki2m tra cE FE v OR
n N.c byte d> li9u tP UDR
St (St/IDLE) Sp1 [Sp2] [P] [8] [7] [6] [5] 4 3 2 1 0 (IDLE)
17
4.2.5 EEPROM
n EERIE (EEPROM Ready Intr En)
n EEMWE (EEPROM Master Write En) : cho php ghi. Bit ny
sU tH 0:ng b@ xo sau 4 chu k^ 0Dng hD
n EEWE (EEPROM Write En) : khi bit ny 0&Cc thi(t l8p v
EEMWE=1 th thao tc ghi m;i 0&Cc thHc hi9n
n EERE (EEPROM Read En): cho php 0.c
n EEPROM. Khi 0.c xong, bit ny sU tH 0:ng b@ xo v CPU sU
dPng 4 chu k^ 0Dng hD tr&;c khi l9nh ti(p theo 0&Cc thHc hi9n
4.2.5 EEPROM (ti$p)
n Quy trnh ghi:
n NCi 0(n khi EEWE=0
n Ghi 0@a chL m;i vo EEARL v EEARH
n Ghi d> li9u m;i vo EEDR
n Ghi mZc logic 1 vo bit EEMWE v mZc logic 0 vo
EEWE 0Dng thEi
n Trong vng 4 chu k^ 0Dng hD sau ghi gi tr@ logic 1 vo
EEWE
18
4.2.6 SPI (Serial Peripheral Interface)
4.2.6 SPI (Serial Peripheral Interface ti$p)
n Truy1n song cng
n Ch.n ch( 0: chJ hoVc t;
n Bit cao hoVc bit thTp truy1n tr&;c
n BGy bt thi(t l8p t4c 0: truy1n
n CE ngSt truy1n h(t
n CE bGo v9 xung 0:t ghi
n Nnh thc tP ch( 0: nghL
n Ch( 0: nhn 0i t4c 0:
19
4.2.7 So snh tn hi9u t&<ng tH (Analog Comparator)
n M?ch so snh tn hi9u t&<ng tH: so snh tn hi9u
analog gi>a hai chn AIN1 v AIN2
S1
Reset
+5V
Reset
MOSI
C4 22p
+5V
+5V
CON8
R1
10K
+5V
SCK
J5
Program
1
2
3
4
5
6
MISO
U1
ATMEGA32
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PB0/XCK/T0
PB1/T1
PB2/INT2/AIN0
PB3/OC0/AIN1
PB4/SS
PB5/MOSI
PB6/MISO
PB7/SCK
RESET
VCC
GND XTAL2
XTAL1
PD0/RXD
PD1/TXD
PD2/INT0
PD3/INT1
PD4/OC1B
PD5/OC1A
PD6/ICP
PD7/OC2
PC0/SCL
PC1/SDA
PC2/TCK
PC3/TMS
PC4/TDO
PC5/TDI
PC6/TOSC1
PC7/TOSC2
AVCC
AGND
AREF
PA7/ADC7
PA6/ADC6
PA5/ADC5
PA4/ADC4
PA3/ADC3
PA2/ADC2
PA1/ADC1
PA0/ADC0
Y1
8MHz
Reset
C5
22p
MISO
+ C3
4.7u
MOSI
SCK
4.1 Gi6i thi.u chung (tip)
20
4.3 T8p l9nh v ngn ng> l8p trnh
4.3.1 T8p l9nh
n 109 l9nh
n Ton h.c v logic (22)
n L9nh rU nhnh (34)
n L9nh chuy2n 0Ki d> li9u (31)
n L9nh bt v ki2m tra bt (31)
4.3.1 T8p l9nh (ti$p)
Cc ch( 0: 0@nh 0@a chL
n N@a chL trHc ti(p (Direct Addressing)
n N@a chL qua chL s4 (Indexed Addressing)
n N@a chL tZc thEi (Immediate Addressing)
n N@a chL t&<ng 04i (Relative Addressing)
n .
21
4.3.2 M:t s4 ngn ng> l8p trnh
n AVR Assembler
n AVR Edit 3.5 (l3p trnh C)
n CodeVisionAVR (l3p trnh C)
1
Ch&<ng Ch&<ng 5: CodevisionAVR 5: CodevisionAVR
n n IDE ( IDE (Integrated Development Environment Integrated Development Environment) )
n n Tr Tr nh d nh d@ @ch ( ch (Compiler Compiler) )
n n H H m th& vi m th& vi9 9n ( n (Library Functions) Library Functions)
n n T TH H 0 0: :ng sinh m ( ng sinh m (Automatic Program Generator Automatic Program Generator) )
Hnh 5. Giao di9n chnh cJa CodevisionAVR
2
5.1 IDE 5.1 IDE
5.1.1 File 5.1.1 File
n n T T? ?o file o file
n n M MO O file file
n n Ch ChL Lnh s nh s% %a a
n n L&u L&u
5.1.2 Project 5.1.2 Project
n n T T? ?o m o m: :t project t project
n n M MO O Project Project
n n Thm ch Thm ch th th ch/di ch/diQ Qn gi n giG Gi i
n n C CT Tu h u h nh cho Project nh cho Project
n n Quan s Quan s t ch&<ng trr t ch&<ng trr nh d nh d@ @ch ch
3
5.1.3 Cng c 5.1.3 Cng c+ +
n n G Gb b r r4 4i ( i (debugger debugger) )
n n L L8 8p tr p tr nh ( nh (programmer programmer) )
n n Terminal Terminal
n n C CT Tu h u h nh ( nh (Configuring Configuring) )
5.1.4 Thi 5.1.4 Thi( (t l t l8 8p mi tr& p mi tr&E Eng ng
n n T TK Kng quan ng quan
n n So So? ?n th n thG Go o
n n Hi Hi9 9n l n l\ \i i
n n N& N&E Eng d ng d[ [n tr n tr nh g nh gb b l l\ \i i
n n C CT Tu h u h nh n nh n? ?p p
4
5.2 Tr 5.2 Tr nh d nh d@ @ch ch
n Ti1n x% l
n Ch thch
n TP kho
n D> li9u chucn, d> li9u tH 0@nh nghaa
n HBng, bi(n
n Chuy2n ki2u
n Php ton
n Hm
n Con trW
n Thanh ghi I/O
n Truy c8p EEPROM
n NgSt
n Assembly
5.3 H 5.3 H m chu m chuc cn n
n n H H m IO chu m IO chuc cn n
n n char char getchar getchar(void) (void)
Returns a character received by the UART, using polling. Returns a character received by the UART, using polling.
n n void void putchar putchar(char c) (char c)
Transmits the character c using the UART, using polling. Transmits the character c using the UART, using polling.
n n
n n H H m to m to n h n h. .c c
n n unsigned char unsigned char cabs cabs(signed char x) (signed char x)
returns the absolute value of the byte x. returns the absolute value of the byte x.
n n unsigned int unsigned int abs abs(int x) (int x)
returns the absolute value of the integer x. returns the absolute value of the integer x.
n n
5
n n LCD LCD
n n void void lcd_write_byte lcd_write_byte (unsigned char addr, unsigned char data) (unsigned char addr, unsigned char data)
write a byte to the LCD character generator or display RAM write a byte to the LCD character generator or display RAM
n n unsigned char unsigned char lcd_read_byte lcd_read_byte(unsigned char addr); (unsigned char addr);
read a byte from the LCD character generator or display RAM read a byte from the LCD character generator or display RAM
n n void void lcd_gotoxy lcd_gotoxy(unsigned char x, unsigned char y); (unsigned char x, unsigned char y);
set the LCD display position x=0..39 y=0..3 set the LCD display position x=0..39 y=0..3
n n . . . . . .
n n I I
2 2
C C
n n void void i2c_init i2c_init(void) (void)
this function initializes the I2C bus. this function initializes the I2C bus.
n n unsigned char unsigned char i2c_start i2c_start (void) (void)
issues a START condition. Returns 1 if bus is free or 0 if the I issues a START condition. Returns 1 if bus is free or 0 if the I2C bus is 2C bus is
busy. busy.
n n void void i2c_stop i2c_stop (void) (void)
issues a STOP condition. issues a STOP condition.
n n . . . . . .
5.4 T 5.4 TH H 0 0: :ng sinh m ng sinh m
n n C C i 0 i 0V Vt c t c c thng s c thng s4 4
n n Thi Thi( (t l t l8 8p RAM ngo p RAM ngo i i
n n Thi Thi( (t l t l8 8p c p cK Kng v ng v o ra o ra
n n Thi Thi( (t l t l8 8p ng p ngS St t
n n Thi Thi( (t l t l8 8p b p b: : 0 0( (m m/ /0 0@ @nh th nh thE Ei i
n n Thi Thi( (t l t l8 8p UART/USART p UART/USART
n n Thi Thi( (t l t l8 8p b p b: : so s so s nh t&<ng t nh t&<ng tH H
n n Thi Thi( (t l t l8 8p ADC p ADC
n n Thi Thi( (t l t l8 8p SPI p SPI
n n Thi Thi( (t l t l8 8p USI p USI
n n Thi Thi( (t l t l8 8p I p I
2 2
C C
n n Thi Thi( (t l t l8 8p LCD p LCD
n n . . . . . .
1
Ch&<ng Ch&<ng 6: Input/Output 6: Input/Output
n n T TK Kng ng quan quan
n n M M: :t t s s4 4 v v d d+ + v v o/ra o/ra
n n L L8 8p p tr tr nh nh 0i 0i1 1u u khi khi2 2n n thi thi( (t t b b@ @
n n Thi Thi( (t t b b@ @ v v o o ra ra chu chuc cn n
T TH Hng ng quan quan
n n V V o o ra ra s s4 4
V V o o n n4 4i i ti ti( (p p
V V o o ra ra song song song song
n n V V o o ra ra t&<ng t&<ng t tH H
ADC ADC
DAC DAC
2
V V o o ra ra c cI Ia a 8051 8051
V V o o ra ra c cI Ia a AVR AVR
3
B B n n ph ph m m 4x4 4x4
S932
K3
S921
K5
S934
S922 S924
S902
S913
S933
S901
K2
S911
S903
S914
K6
K7
S904
K0
K4
S912
S931
K1
S923
B B n n ph ph m m 4x4 4x4
n n N N. .c c b b n n ph ph m m
n n Ch Ch4 4ng ng rung rung
4
Key Board Key Board
Key Board Key Board
n n AT keyboard AT keyboard go go m m mo mo t t ma ma tra tra n n lo lo n n ca ca c c ph ph m m, , ta ta t t ca ca
du duo o c c gia gia m m sa sa t t bo bo i i mo mo t t bo bo x xu u ly ly on on- -board. board. Bo Bo x xu u ly ly
kha kha c c bie bie t t nhau nhau t tu u ba ba n n ph ph m m na na y y d de e n n ba ba n n ph ph m m
kha kha c c( chip ( chip thong thong du du ng ng go go m m 8048, 8049, 6868 8048, 8049, 6868 va va
6805) 6805) nh nhu ung ng ta ta t t chu chu ng ng co co ba ba n n la la m m gio gio ng ng mo mo t t vie vie c c : :
Gia Gia m m sa sa t t nh nhu ung ng ph ph m m du duo o c c nha nha n n / / tha tha va va go go i i d du u
lie lie u u t tu uong ong x xu u ng ng to to i i ma ma y y chu chu . . Bo Bo x xu u ly ly na na y y cham cham
so so c c ta ta t t ca ca d du u lie lie u u ra ra va va d de e m m ba ba t t c cu u d du u lie lie u u na na o o va va o o
bo bo d de e m m 16 16- -byte byte cu cu a a no no ne ne u u ca ca n n. . Ta Ta t t ca ca vie vie c c giao giao
tie tie p p gi giu ua a ma ma y y chu chu va va ba ba n n ph ph m m du du ng ng PS/2 protocol. PS/2 protocol.