FEBRUARY 2007

VOLUME 15

NUMBER 2

ITCOB4

(ISSN 1063-8210)

REGULAR PAPERS

Design Methodology
Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper ....... ......... ........ ......... ......... ..
.. ........ ......... ......... ........ ......... ......... ........ . A. Amirabadi, A. Afzali-Kusha, Y. Mortazavi, and M. Nourani
Design Methodology for Global Resonant -Tree Clock Distribution Networks ..... ... J. Rosenfeld and E. G. Friedman
Physical Design
Integrated Placement and Skew Optimization for Rotary Clocking ...... ........ ..... G. Venkataraman, J. Hu, and F. Liu
Interconnect Lifetime Prediction for Reliability-Aware Systems ......... ........ ......... ......... ........ ......... ......... ..
.. ........ ......... ......... ........ ......... ......... ........ ......... . Z. Lu, W. Huang, M. R. Stan, K. Skadron, and J. Lach

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SRAM Design
A New Single-Ended SRAM Cell With Write-Assist .... ......... ......... ........ ......... ......... ........ ..... R. F. Hobson
Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs ..... ......... .. J. Meyer and F. Kocan
Segmented Virtual Ground Architecture for Low-Power Embedded SRAM .... .... ...... M. Sharifkhani and M. Sachdev

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Statistical Timing Analysis

A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations . ......... ..
.. ........ ......... ......... ........ ......... ......... ........ ......... ......... ........ ........ V. Khandelwal and A. Srivastava

206

Fault Tolerance
Online Fault Tolerance for FPGA Logic Blocks .. ........ ......... ........ J. M. Emmert, C. E. Stroud, and M. Abramovici

216

TRANSACTION BRIEFS

A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks ........ ........ ......... ......... ..
.. ........ ......... .... H.-M. Seo, Y. Moon, Y.-K. Park, D. Kim, D.-S. Kim, Y.-S. Lee, K.-H. Won, S.-D. Kim, and P. Choi
Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses ...... ......... ......... ........ ......... ......... ..
.. ........ ......... ......... ........ ......... ...... L. Zhang, J. M. Wilson, R. Bashirullah, L. Luo, J. Xu, and P. D. Franzon
Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs . ........ ......... ......... ..
.. ........ ......... ......... ........ ......... ......... ........ ......... ......... ........ ....... J.-T. Lai, A.-Y. Wu, and C.-H. Lee
Customization of Arbitration Policies and Buffer Space Distribution Using Continuous-Time Markov Decision
Processes ....... ......... ........ ......... ......... ........ ......... ......... ........ ......... ... S. S. Kallakuri and A. Doboli

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CALLS FOR PAPERS

IEEE ISCAS 2007Call for Participation ........ ........ ......... ......... ........ ......... ......... ........ ......... ......... .

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