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CERTIFICATE
This is to certify that <name> of class XII has satisfactorily completed the project on LOGIC GATES nder the ! idance of <teachers name>d rin! the session "#$%&"#$'(

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VALUED BY

TEACHER EXTERNAL EXAMINER

PRINCIPAL

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DATE:

AC)*O+LE,G-E *T
I.d li/e to e0press my !reatest !ratit de to the people 1ho ha2e helped 3 s pported me thro !ho t my project( I4 m !ratef l to o r school4s 567SICS fac lty I than/ <teachers name> for her contin o s s pport for the project8 from initial ad2ice 3 enco ra!ement to this day( Special than/s of mine !oes to my collea! es 1ho helped me in completin! the project 9y !i2in! necessary information on the apparat s sed in this e0periment8 made this project easy and acc rate(

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I 1ish to than/ my parents for their ndi2ided s pport 3 interest 1ho inspired me 3 enco ra!ed me to !o my o1n 1ay 1itho t 1hich I 1o ld 9e na9le to complete my project( At last 9 t not the least I 1ant to than/s my friends 1ho appreciated me for my 1or/ 3 moti2ated

me(

CO*TE*T
:Introd ction

: E0periment
1. Aim

$#

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2. Apparat s 3. Theory 4. 5roced re 5. Circ its 5repared 6. O9ser2ations 7. <es lt

$# $$
$; "" "' ";

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=i9lio!raphy

">

I*T<O,?CTIO*

Logic Gates:
A !ate is a di!ital circ it that follo1s c rtain lo!ical relationship 9et1een the inp t and o tp t 2olta!es( Therefore8 they are !enerally /no1n as lo!ic !ates @ !ates 9eca se they control the flo1 of information( The fi2e common lo!ic !ates sed are *OT8 A*,8 O<8 *A*,8 *O<( Each lo!ic !ate is indicated 9y a sym9ol and its f nction is defined 9y a tr th ta9le that sho1s all the possi9le inp t lo!ic le2el com9inations 1ith their respecti2e o tp t lo!ic le2els( Tr th ta9les help nderstand the 9eha2ior of lo!ic !ates(

AiB

*OT !ate AIn2erterB

This is the most 9asic !ate8 1ith one inp t and one o tp t( 5rod ces a C$4 o tp t if the inp t is C#4 and 2ice&2ersa( That is8 it prod ces an in2erted 2ersion of the inp t at its o tp t(

A
0

Y=A
1

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AiiB O< Gate

An O< !ate has t1o or more inp ts 1ith one o tp t( The o tp t 7 is $ 1hen either inp t A or inp t = or 9oth are $s8 that is8 if any of the inp t is hi!h8 the o tp t is hi!h(

A
0 0 1 1

B
0 1 0 1

Y=A OR B(A+B)
0 1 1 1

AiiiB A*, Gate

An A*, !ate has t1o or more inp ts and one o tp t( The o tp t 7 of A*, !ate is $ 8only 1hen inp t A and inp t = are 9oth $( It /ind of loo/s for the minim m of the t1o si!nals(

A
0 0

B
0 1

Y=A AND B(A.B)

0 0

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1 1

0 1

0 1

So ! B"#$% Lo&$% '"(!# ")* T+!$, T,-(+ T"./!#

Circ it dia!rams

AND 'ATE

OR 'ATE

NOT 'ATE

Experiment

AIM
To design and simulate basic logic gates and to design an appropriate logic gate combination for a given truth table.

APPARATUS

A project 9oard T1o *'##> diodes T1o LE, A D2 9attery 1ith a connector

T1o =5E&=CF'> transistors T1o $##8 three F;# resistors Connectin! 1ires

T6EO<7

The three 9asic lo!ic !ates and their com9inations are the 9 ildin! 9loc/ of the di!ital circ it( 1. OR gate
A
G =

The O< !ate is an electronic circ it that !i2es a hi!h o tp t A$B if one or more of its inp ts are hi!h( A pl s AGB is sed to sho1 the O< operation(
CIRCUIT DIA'RAM:

2. AND Gate
A =
The A*, !ate is an electronic circ it that !i2es hi!h o tp t only if all inp ts are hi!h

A(=

CIRCUIT DIA'RAM :

3. NOT Gate

The *OT !ate is an electronic circ it that prod ces an in2erted 2ersion of the inp t at its o tp t( It is also /no1n as an in2erter(

A
CIRCUIT DIA'RAM:

# $

PROCEDURE

Design of basic logic gates(

DESI'N OF AND 'ATE

COMPONENTS: T1o p&n j nction diode8 A LE,8 A

$## resistors
CONSTRUCTION: An A*, !ate can 9e realiHed

9y connectin! the diodes as sho1n in the fi! re( A resistance of $## is connected in series 1ith the LE, to pre2ent its malf nction(
PRO0ECT BOARD CIRCUIT: GROUND

HIGH

DESI'N OF OR 'ATE

COMPONENTS: T1o p&n j nction diode8 A LE,8 A

$## resistors
CONSTRUCTION: An O< !ate can 9e realiHed 9y connectin! the diodes as sho1n in the fi! re( 6ere also there is a need for a $## resistor in series 1ith LE,

PRO0ECT BOARD CIRCUIT:

DESI'N OF NOT 'ATE

COMPONENTS: A transistor8 t1o LE,s8 three F;#

resistors(
CONSTRUCTION: not !ate circ it can 9e realiHed 9y connectin! an *5* transistor as sho1n in the fi! re( The 9ase of the transistor is connected to the inp t thro !h resistance of F;# and emitter is connected to the ne!ati2e

terminal( The collector is connected to the positi2e terminal and the o tp t 2olta!e at collector is 1ith respect to ne!ati2e. PRO0ECT BOARD CIRCUIT:
1 2 3 Ground High line 1=2=3=600

Logic gate combination for gi en tr!t" table

$( +rite prod ct term for each inp t AmintermB8 Com9ination 1here =oolean f nction has o tp t "( +hile 1ritin! minterms8 complement the 2aria9le 1hose 2al e is # other1ise 1rite it in the direct form A1itho t complementB( %( Add all the minterms to o9tain the =oolean f nction( %( ,ra1 the circ it sin! 9asic LOGIC Gates(

So 1!2 %+oo#! (+! &$3!) T,-(+ T"./!. A

0 0 1 1

B
0 1 0 1

Y=A.B
0 0 0 1

Y
1 1 1 0

The =oolean I nction IA08yB is o9tained asJ F !"#$% &'.(')&.(')&'( % (')&'( % &')('$ ()('$ % &')(' % &($' <,istri9 ti2e la1> <,istri9 ti2e la1> <la1 of complements> <,e-or!an4s theorem>

So8 o r e0pression red ces to that of a *A*, Gate lo!ic A*ot of A*,B(

LOGIC CI<C?IT ISJ

F=(x.y)

CIRCUIT DIAGRAM
High line Ground

C$,%-$(# P,!4",!*:5

AND ga e

OR ga e

 NOT ga e

NAND ga e

OBSERVATION S

1.

Stim lation of A*, !ate

The follo1in! concl sions can 9e easily dra1n from the 1or/in! of electrical circ itJ

aB If 9oth s1itches are open AAK#8 =K#B then LE, 1ill not !lo18 hence 7K#( 9B If S1itch one s1itch is open and the other is closed AAK$8 =K# or AK#8 =K$B then LE, 1ill not !lo18 hence 7K#( cB If s1itch A 3 = 9oth closed AAK$8 =K$B then LE, 1i ll !lo18 6ence 7K$(

2.

Stim lation of O< !ate

The follo1in! concl sions can 9e easily dra1n from the 1or/in! of electrical circ itJ aB If 9oth s1itches are open AAK#8 =K#B then LE, 1ill not !lo18 hence 7K#( 9B If S1itch one s1itch is open and the other is closed AAK$8 =K# or AK#8 =K$B then LE, 1ill !lo18 hence 7K#( cB If s1itch A 3 = 9oth closed AAK$8 =K$B then LE, 1i ll !lo18 6ence 7K$(

3.

Stim lation of *OT !ate

a) If switch A is open (i.e. A=0), the LED will glow, hence Y=1.

b) If Switch A is closed (i.e. A=1), the LED will not glow, hence Y=0.

4.

Stim lation of *A*, !ate

a) If Switch A ! open (A=0, !=0) then LED will glow, hence Y=1. b) If Switch A open ! closed then (A=0, !=1) LED will glow, hence Y=1. c) If switch A closed ! open then (A=1, !=0) LED will glow, hence Y=1. d) If switch A ! a"e closed then (A=1, !=1) LED will not glow, hence Y=0

R! #-/ (:

B"#$% /o&$% &"(!# 1!,! *!#$&)!* ")* #$ -/"(!* ")* /o&$% %$,%-$( 1"# 4,!4",!* 6o, (+! &$3!) (,-(+ ("./!

BIBLIO'RAPHY:5

+i/ipedia

Electronic de2ices and circ its 9y E = G pta

Concept al physics 9y G C A!ar1al Encarta