Describe another possible implementation of a multiplier circuit.

Implementation of multiplier using partial products: Consider computing the product of two 4-bit integer numbers given by A3,A2,A1,A0,(multiplicand) and B3,B2,B1,B0 (multiplier). The product of these two numbers can be formed as shown below:

Each of the ANDed terms is referred to as a partial product. The final product (the result) is formed by accumulating (summing) down each column of partial products. Any carries must be propagated from the right to the left across the columns. The partial products reduce to simple AND operations between the corresponding bits in the multiplier and multiplicand. The sums down each column can be implemented using one or more 1-bit binary adders. If a carry needs to be added from the right we use a full adder, otherwise we use a half adder. The figure below shows the implementation:

The partial-sum adders can also be rearranged in a tree like fashion, reducing both the critical path and the number of adder cells needed. The presented structure is called the Wallace tree multiplier and its implementation is shown in figure below

The tree multiplier realizes substantial hardware savings for larger multipliers. The propagation delay is reduced as well. These are the other implementations of a multiplier.

Compare the method used in this lab with the design discussed from the earlier question. The design used in this lab is based on reading log values from a lookuptable and finding the antilog, after performing addition, from another lookup table. This method does not involve the use of partial products etc. It is just reading precomputed values stored in memory. Hence it is much faster than finding partial products and adding them and cheaper in terms of cost. However, such an implementation requires more memory as the size of the input number increases. The tree multiplier realizes substantial hardware savings for larger multipliers. The propagation delay is reduced as well. While substantially faster than the carry-save structure for large multiplier word lengths, the Wallace multiplier has the disadvantage of being vary irregular, which complicates the task of an efficient layout design.