ANMOL SHAHANI CSU ID: 829905938

Literature Review: Reliable Network on Chip Design

With technology scaling, as the geometries of the transistors reach the physical limits of operation, an important design challenge of SoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The interconnects will be susceptible to various noise sources such as cross-talk, coupling noise, soft errors, process variations, etc. Designing systems under such uncertain conditions becomes a challenge. In this literature survey, I am reviewing the state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design, such as 1. 2. 3. 4. 5. topology synthesis core mapping achieving timing error-tolerance crossbar sizing Fault tolerant route generation Timing error tolerance mechanism

With technology scaling, the device characteristics fluctuate to a large extent due to process variations and can cause significant variations in wire delay. Wire delay is also affected by other forms of interference such as supply bounce, transmission line effects, etc. As such delay variations can affect multiple bits simultaneously; special mechanisms are needed to handle timing errors. The best mechanism is to use T-error, a timing-error tolerant mechanism to make the interconnect resilientagainst timing errors arising due to such delay variations on wires.This is achieved by using double data sampling techniques by using a main flip flop and a delayed flipflop and comparing the output of the two to get error. By using this technique we can operate NoC at higher frequency typically in the over clocked frequency of operation mode. This is a method to achieve timing error tolerance. Over the remaining part of the semester I plan to review the other problems encountered during NoC design as mentioned above and study about methods to solve them. I have finished reviewing about the t-error method to achieve timing error tolerance. I will now dive deeper into other problems that affect the reliability of NoC design, as mentioned above, and their solutions which make network on chip design more reliable.