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NEOSCHIP TECHNOLOGIES

B.Tech VLSI 2013 MAIN LIVE PROJECTS


S.No. PROJECT TITLE

COMMUNICATIONS BASED PROJECTS


VLSI 01 VLSI 02 Implementation of a Multi-Channel UART Controller based on FIFO Technique and FPGA UART Asynchronous Transmitter/Receiver using FPGA with Verilog/VHDL code Design and Implement of FFT Processor for OFDMA System Using FPGA

VLSI 03 RS-232 Transmitter/Receiver using FPGA with Verilog/VHDL code VLSI 04

VLSI 05 Improved Method to Increase AES System Speed by using VERILOG VLSI 06 Implementation of UART with Status Register VLSI 07 VLSI 08 VLSI 09 VLSI 10 VLSI 11 VLSI 12 Design and Synthesis of Wishbone Bus Dataflow Interface Architecture for SoC Integration Design & Implementation of Noise / Echo canceler using FPGA with Verilog/VHDL Efficient WCDMA Digital Down Converter Design using System Generator Sinusoidal Pulse Width Modulation (SPWM) Design and Implementation by Focusing on Reducing Harmonic Content Efficient Hardware Co-Simulation of Down Converter for wireless Communication systems Design and simulation of UART serial communication module based on VHDL

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NEOSCHIP TECHNOLOGIES
PROTOCOL BASED PROJECTS
VLSI 13 VLSI 14 High speed USB 2.0/Super speed USB 3.0 Transmitter and Receiver using FPGA with Verilog/VHDL FPGA Implementation of mpeg-4 Advanced-Audio-Coding (AAC) decoder FPGA based flexray bus protocol analyzer design using verilog or vhdl. Universal Serial Bus USB Device Controller using FPGA with Verilog/VHDL code

VLSI 15 Design master and slave using AXI protocol VLSI 16 VLSI 17

VLSI 18 Implementation of IEEE 802.11a WLAN Baseband Processor VLSI 19 FPGA based flexray bus guardian system design using verilog/vhdl. VLSI 20 FPGA based LIN bus protocol analyzer design using verilog or vhdl. VLSI 21 FPGA based can bus protocol analyzer design using verilog or vhdl. VLSI 22 Design of On-Chip Bus with OCP Interface VLSI 23 VLSI 24 VLSI 25 Implementation of a Self-Motivated Arbitration Scheme for the Multilayer AHB Bus Matrix Optimized software implementation of a full-rate IEEE 802.11A compliant digital baseband transmitter on a digital signal processor Design and Implementation of A Lottery-based Bandwidth Guaranteed and Low Latency Arbiter for On-Chip Bus AMBA AHB Bus Protocol Checker with Efficient Debugging VLSI 26 Mechanism

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LOW POWER BASED PROJECTS
VLSI 27 VLSI 28 VLSI 29 Novel Low Power, High Speed Hardware Implementation of 1D DCT/IDCT Using Xilinx FPGA Low Power Test Pattern Generator Using a Variable-Length Ring Counter Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

VLSI 30 Design a low power design of Wallance tree multiplier VLSI 31 VLSI 32 VLSI 33 High performance VLSI architecture design for H.264 Context Adaptive Variable Length (CAVLC) decoder Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing Ultra Low Power Clocking Scheme Using Energy Recovery and Clock Gating

VLSI 34 Design of low-power and high performance radix-4 multiplier

DIGITAL SIGNAL PROCESSING


VLSI 35 Design and Implementation of FIR filters VLSI 36 Design of the 16-order FIR digital filter based of FPGA VLSI 37 VLSI 38 VLSI 39 An FPGA implementation of FFT algorithms for DSP & Real time applications The Design of FIR Filter Base on Improved DA Algorithm and its FPGA Implementation Low-Power Digital Signal Processor Architecture for Wireless Sensor
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NEOSCHIP TECHNOLOGIES
VLSI 40 Improvisation of GABOR filter design using VERILOG HDL VLSI 41 VLSI 42 Programmable 16-Tap Low-power FIR Filter using FPGA with Verilog/VHDL code. Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs

VLSI 43 16 Bit fixed point DSP Processor using FPGA with Verilog/VHDL . VLSI 44 Asynchronous Serial controller using FPGA with Verilog/VHDL code VLSI 45 VLSI 46 VLSI 47 VLSI 48 design and simulation of 32-point FFT using radix-2 algorithm for FPGA implementation 16 Point Fast Fourier Transform Algorithm using FPGA with Verilog/VHDL 8 Point Fast Fourier Transform Algorithm using FPGA with Verilog/VHDL New approach to Look-Up-Table Design and Memory-based Realization of FIR Digital Filter An Efficient Architecture for 2-D Lifting-based Discrete Wavelet Transform Flexible hardware-friendly digital architecture for 2-D separable convolution-based scaling VLSI implementation of canonical Huffman encoder/decoder algorithm using FPGA with Verilog/VHDL code Superscalar Power Efficient Fast Fourier Transform FFT
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VLSI 49 SOBEL edge detector by using VERILOG VLSI 50

VLSI 51 An Efficient Architecture for 3-D Discrete Wavelet Transform VLSI 52 VLSI 53 VLSI 54

Architecture.
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NEOSCHIP TECHNOLOGIES
VLSI 55 VLSI 56 VLSI 57 Development of a FPGA-based High Speed FFT Processor for Wideband Direction of Arrival Applications A Spurious Power Suppression Technique for Multimedia/DSP Applications An Efficient Hardware Architecture for Multimedia Encryption and Authentication using Discrete Wavelet Transform FPGA Implementation of Wavelet Transform Based on Lifting Scheme VLSI implementation of Discrete Mellin Transform for Real Time Scale Analysis of Images FPGA Implementation of Pipelined 2D-DCT and Quantization Architecture for JPEG Image Compression Memory-efficient high-speed convolution-based generic structure for multilevel 2-d dwt Design and implementation of low power digital fir filter based on low power multipliers and adders on XILINX FPGA

VLSI 58 VLSI Progressive Coding for Wavelet-based Image Compression. VLSI 59 VLSI 60 VLSI 61 VLSI 62 VLSI 63

MEMORY BASED PROJECTS


VLSI 64 An enhanced canary-based system with BIST for SRAM standby power reduction VLSI 65 A Low-Cost Built-In Redundancy-Analysis Scheme for WordOriented RAMs with 2-D Redundancy VLSI 66 Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory VLSI 67 Cyclic Redundancy Check ECRC/LCRC Error Check using FPGA with Verilog/VHDL code VLSI 68 512K X 8 BIT LOW POWER CMOS SRAM
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NEOSCHIP TECHNOLOGIES
VLSI 69 VLSI 70 VLSI 71 A Built-In Repair Analyzer With Optimal Repair Rate for WordOriented Memories VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory Exploring the Use of Emerging Nonvolatile Memory Technologies in Future FPGAs

VLSI 72 Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes VLSI 73 Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUTBased FPGAs for Area and Speed VLSI 74 Cooperating Virtual Memory and Write Buffer Management for Flash-Based Storage Systems VLSI 75 Efficient Built-in Self-Repair Strategy for Embedded SRAM with Selectable Redundancy VLSI 76 A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs VLSI 77 High Speed VLSI Architecture for General Linear Feedback Shift Register (LFSR) Structures VLSI 78 Design of Testable Reversible Sequential Circuits VLSI 79 Deviation-Based LFSR Reseeding for Test-Data Compression. VLSI 80 Techniques for Compensating Memory Errors in JPEG2000 VLSI 81 Smart Card / Proximity Based Membership Management System VLSI 82 Fault Secure Encoder and Decoder for Nano-memory Applications VLSI 83 VLSI Design and Implementation of Electronic Voting Machine VLSI 84 VLSI 85 Fast enhancement of validation Test Sets for improving the stuck-at fault coverage of RTL circuits Effective and Efficient Approach for Power Reduction by Using MultiPage

Bit Flip-Flops
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NEOSCHIP TECHNOLOGIES
VLSI 86 VLSI 87 On the use of signed digit Arithmetic for new 6-inputs LUT based FPGAs Power optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST

VLSI 88 A Dual-Purpose Real/Complex Logarithmic Number System ALU. VLSI 89 Design of Low Power TPG Using LP-LFSR

MISCELLANEOUS BASED PROJECTS


VLSI 90 VLSI 91 VLSI 92 VLSI 93 VLSI 94 VLSI 95 VLSI 96 VLSI 97 VLSI 98 All-Digital Fast-Locking Pulsewidth-Control Circuit With Programmable Duty Cycle Split-SAR ADCs: Improved Linearity With Power and Speed Optimization MAEPER: Matching Access and Error Patterns With Error-Free Resource for Low Vcc L1 Cache Reduced-Complexity LCC ReedSolomon Decoder Based on Unified Syndrome Computation Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction Architecture for Real-Time Nonparametric Probability Density Function Estimation Statistical Functional Yield Estimation and Enhancement of CNFETBased VLSI Circuits Design of Hardware Function Evaluators Using Low-Overhead Non uniform Segmentation With Address Remapping VLSI Implementation of Booths Algorithm using FPGA with
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Verilog/VHDL
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NEOSCHIP TECHNOLOGIES
VLSI 99 VLSI Design and Implementation of Fuzzy Controller Design VLSI 100 CORDIC Designs for Fixed Angle of Rotation VLSI 101 VLSI 102 Novel MIMO Detection Algorithm for High-Order Constellations in the Complex Domain Current-Comparison-Based Domino: New Low-Leakage High-Speed Domino Circuit for Wide Fan-In Gates Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design Reduced Power Transition Fault Test Sets for Circuits With Independent Scan Chain Modes Minimizing Energy of Integer Unit by Higher Voltage FlipFlop: -Aware Dual Supply Voltage Technique 135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits

VLSI 103 Architecture and Design Flow for a Highly Efficient Structured ASIC VLSI 104 VLSI 105

VLSI 106 Fault Demotion Using Reconfigurable Slack (FaDReS) VLSI 107 VLSI 108 VLSI 109

VLSI 110 A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction VLSI 111 Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes VLSI 112 Glitch-Free NAND-Based Digitally Controlled Delay-Lines VLSI 113 High speed ASIC design of complex multiplier using vedic mathematics FPGA-based Custom Floating-Point Unit Generation for Embedded VLSI 114 Systems.
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NEOSCHIP TECHNOLOGIES
VLSI 115 Hardware implementation of Variable Precision Multiplication on FPGA.

VLSI 116 PCI Express Interface Controller using FPGA with Verilog/VHDL code VLSI 117 VGA/LCD Controller using FPGA with Verilog/VHDL code. VLSI 118 High-Speed Booth Algorithm Encoded Parallel Multiplier Design VLSI 119 VLSI 120 VLSI 121 VLSI 122 VLSI 123 VLSI 124 VLSI Design & Implementation of Viterbi AlgorithmEncoder/Decoder using FPGA with Verilog/VHDL code Dynamic/Deficit Round Robin Algorithm using FPGA with Verilog/VHDL code. Design of FPGA based PID-like Fuzzy Controller for Industrial Applications. VLSI Implementation of AHDB (Adaptive Huffman Dynamic Block) Algorithm. VLSI implementation of Steganography using FPGA with Verilog/VHDL code Design of a Multi-Mode Receive Digital-Front-End for Cellular Terminal RFIC

VLSI 125 High-Speed Architecture for Reed-Solomon Decoder/Encoder. VLSI 126 FPGA Based Power Efficient Channelizer for Software Defined Radio. VLSI 127 An Area-Efficient Universal Cryptography Processor for Smart Cards. VLSI 128 Sub threshold Dual Mode Logic VLSI 129 10-bit 30-MS/s SAR ADC Using a Switchback Switching Method VLSI 130 Constant Delay Logic Style A Research on ASIP processing element architecture suitable for
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VLSI 131

FPGA implementation

NEOSCHIP TECHNOLOGIES
VLSI 132 On the higher efficiency of parallel Reed-Solomon turbo-decoding. VLSI 133 Construction of Near-Optimum Burst Erasure Correcting LowDensity Parity-Check Codes VLSI 134 A Shuffled message-passing decoding method for memory-based LDPC decoders VLSI 135 MULTIPLICATION ACCELERATION THROUGH TWIN PRECISION VLSI 136 A Real time Approach Towards Object Tracking VLSI 137 The Power Stability of FPGA Based Micro Controller Design and Measurement VLSI 138 CORDIC and SVD Implementation in Digital Hardware VLSI 139 Real Time Simulation of a FPGA Based Space Vector PWM Controller VLSI 140 VLSI 141 VLSI 142 FPGA-Based Smart Sensor Implementation with Precise Frequency to Digital converter for Flow Measurement FPGA Implementation of Chaotic Cellular Automation with Binary Synchronization Property Flexible Hardware Architecture of Hierarchical K-Means Clustering for Large Cluster Number

VLSI 143 Common Architecture for Decoding Turbo and LDPC Codes VLSI 144 A Harmonic Signal Generator Based on DDS and SOPC VLSI 145 Design Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation Multiplexed Redundant Execution: A technique for efficient fault tolerance in chip multiprocessors VHDL code generation for FPGA implementation of Digital Control with Co-Simulation Step
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VLSI 146 Asynchronous Data-Driven Circuit Synthesis VLSI 147 VLSI 148

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NEOSCHIP TECHNOLOGIES
VLSI 149 VLSI 150 VLSI 151 Product Reed-Solomon Codes for Implementing NAND Flash Controller on FPGA chip Improved Area-Efficient Weighted Modulo 2n + 1 Adder Design with Simple Correction Schemes A VLSI Efficient Programmable Power-of-Two Scalar for RNS An efficient FPGA implementation of the Advanced Encryption Standard algorithm Implementation of FPGA Control for Multilevel Boost Converter used for PV Applications A very fast and low power carry select adder circuit by using VERILOG

VLSI 152 Multi-operand Redundant Adders on FPGAs VLSI 153

VLSI 154 Tiny Tate Bilinear Pairing Core Specification by using VERILOG VLSI 155 VLSI 156

VLSI 157 Embedded Zero tree Wavelet (EZW) by using VERILOG VLSI 158 Quantization noise suppression in fractional-n PLLS utilizing glitchfree phase switching multi-modulus frequency divider VLSI 159 Ternary Adder by using VERILOG VLSI 160 Trigonometric functions (degrees) in double FPU VLSI 161 Design a VENDING MACHINE by using VERILOG VLSI 162 Design a Traffic light controller by using VERILOG VLSI 163 Design a 4 BIT PROCESSOR by using VERILOG VLSI 164 Design High-speed, Loadable 16-bit Binary Counter by using VERILOG Implementation of reliable and cost effective anti collision technique VLSI 165 for RFID tag.
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NEOSCHIP TECHNOLOGIES
VLSI 166 Hardware Implementation of Watchdog Timer for Application in ATM Machine Using VERILOG A High Speed Wallace Tree Multiplier Using Modified Booth Algorithm for Fast Arithmetic Circuits

VLSI 167 A New Design for Double Edge Triggered Flip-flops by using VERILOG VLSI 168

VLSI 169 Priority Encoder Based Single Cycle Access Structure for Logic Test VLSI 170 Design of Pipelined Quadratic Function Implementation VLSI 171 VLSI Architecture of Arithmetic Coder Used in SPIHT VLSI 172 Double procession floating in VERILOG VLSI 173 Coordinate rotation digital computer (CORDIC) core specification VLSI 174 An Efficient Implementation of Floating Point Multiplier VLSI 175 Design and Implementation of Incremental Encoder based Position and Velocity Measurement Chip

VLSI 176 Design and implantation of sequence Detector VLSI 177 A Low-Complexity Viterbi Decoder for Space-Time Trellis Codes VLSI 178 VLSI Architecture of Parallel Multiplier Accumulator Based on Radix-2 Modified Booth Algorithm VHDL Simulation of Peak Detector, 64 Bit BCD Counter and Reset Automatic Block for PD Detection system using FPGA

VLSI 179 Improving FPGA Performance for Carry Save Arithmetic VLSI 180

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