Physical Layer Prototyping using WARPLab

Patrick Murphy & Melissa Duarte Rice University WARP Workshop March 29, 2010

warp.rice.edu

WARPLab Overview
MATLAB WARP Link Interact with WARP nodes directly from the
MATLAB workspace

Very rapid prototyping of PHY algorithms Real-time Tx-Rx and ofine processing

WARPLab Overview

Ethernet links

WARPLab Overview

Up to 16 WARP Nodes

WARPLab Overview
One PC controls many
WARP nodes processing processing

MATLAB for signal Non-real-time WARP for wireless interfaces Real-time channel use

RADIO 1

FPGA

RADIO 4

RADIO 2

RADIO 3

WARPLab Architecture
Radio Board
Receiver RF Amplier Downconversion Receiver Base-Band Ampliers ADC I To Ethernet Rx Q Buffer ADC Q RSSI Buffer To Ethernet TxI Buffer DAC I From Ethernet TxQ Buffer DAC Q Transmitter RF Amplier Upconversion Transmitter Base-Band Ampliers

FPGA WARPLab Sysgen Core

Rx I Buffer

Antenna Switch

PLL

RSSI

ADC RSSI

WARPLab Architecture
Radio Board
Receiver RF Amplier Downconversion Receiver Base-Band Ampliers ADC I To Ethernet Rx Q Buffer ADC Q RSSI Buffer To Ethernet TxI Buffer DAC I From Ethernet TxQ Buffer DAC Q Transmitter RF Amplier Upconversion Transmitter Base-Band Ampliers

FPGA WARPLab Sysgen Core

Rx I Buffer

TX

Antenna Switch

PLL

RSSI

ADC RSSI

TX Path

WARPLab Architecture
Radio Board
Receiver RF Amplier Downconversion Receiver Base-Band Ampliers ADC I To Ethernet Rx Q Buffer ADC Q RSSI Buffer To Ethernet TxI Buffer DAC I From Ethernet TxQ Buffer DAC Q Transmitter RF Amplier Upconversion Transmitter Base-Band Ampliers

FPGA WARPLab Sysgen Core

Rx I Buffer

RX

Antenna Switch

PLL

RSSI

ADC RSSI

RX Path

WARPLab Architecture
Radio Board
Receiver RF Amplier Downconversion Receiver Base-Band Ampliers ADC I To Ethernet Rx Q Buffer ADC Q RSSI Buffer To Ethernet TxI Buffer DAC I From Ethernet TxQ Buffer DAC Q Transmitter RF Amplier Upconversion Transmitter Base-Band Ampliers

FPGA WARPLab Sysgen Core

Rx I Buffer

TX

Antenna Switch

PLL

RSSI

ADC RSSI

TX I/Q buffers 16384 (214) samples each

WARPLab Architecture
Radio Board
Receiver RF Amplier Downconversion Receiver Base-Band Ampliers ADC I To Ethernet Rx Q Buffer ADC Q RSSI Buffer To Ethernet TxI Buffer DAC I From Ethernet TxQ Buffer DAC Q Transmitter RF Amplier Upconversion Transmitter Base-Band Ampliers

FPGA WARPLab Sysgen Core

Rx I Buffer

RX

Antenna Switch

PLL

RSSI

ADC RSSI

RX I/Q buffers 16384 (214) samples each

WARPLab Architecture
Radio Board
Receiver RF Amplier Downconversion Receiver Base-Band Ampliers ADC I To Ethernet Rx Q Buffer ADC Q RSSI Buffer To Ethernet TxI Buffer DAC I From Ethernet TxQ Buffer DAC Q Transmitter RF Amplier Upconversion Transmitter Base-Band Ampliers

FPGA WARPLab Sysgen Core

Rx I Buffer

RX

Antenna Switch

PLL

RSSI

ADC RSSI

RSSI buffer 12 4096 (2 ) samples

WARPLab Architecture
Radio Board
Receiver RF Amplier Downconversion Receiver Base-Band Ampliers ADC I To Ethernet Rx Q Buffer ADC Q RSSI Buffer To Ethernet TxI Buffer DAC I From Ethernet TxQ Buffer DAC Q Transmitter RF Amplier Upconversion Transmitter Base-Band Ampliers

FPGA WARPLab Sysgen Core

Rx I Buffer

Antenna Switch

PLL

RSSI

ADC RSSI

Variable upconversion/downconversion carrier frequency Value input from MATLAB

WARPLab Architecture
Radio Board
Receiver RF Amplier Downconversion Receiver Base-Band Ampliers ADC I To Ethernet Rx Q Buffer ADC Q RSSI Buffer To Ethernet TxI Buffer DAC I From Ethernet TxQ Buffer DAC Q Transmitter RF Amplier Upconversion Transmitter Base-Band Ampliers

FPGA WARPLab Sysgen Core

Rx I Buffer

Antenna Switch

PLL

RSSI

ADC RSSI

Variable gain Tx BB and RF ampliers Gain value input from MATLAB

WARPLab Architecture
Radio Board
Receiver RF Amplier Downconversion Receiver Base-Band Ampliers ADC I To Ethernet Rx Q Buffer ADC Q RSSI Buffer To Ethernet TxI Buffer DAC I From Ethernet TxQ Buffer DAC Q Transmitter RF Amplier Upconversion Transmitter Base-Band Ampliers

FPGA WARPLab Sysgen Core

Rx I Buffer

Antenna Switch

PLL

RSSI

ADC RSSI

Variable gain Rx BB and RF ampliers Gain value input from MATLAB

WARPLab Architecture
Radio Board
Receiver RF Amplier Downconversion Receiver Base-Band Ampliers ADC I To Ethernet Rx Q Buffer ADC Q RSSI Buffer To Ethernet TxI Buffer DAC I From Ethernet TxQ Buffer DAC Q Transmitter RF Amplier Upconversion Transmitter Base-Band Ampliers

FPGA WARPLab Sysgen Core

Rx I Buffer

Antenna Switch

PLL

RSSI

ADC RSSI

Fixed Point 16_15 I/Q DACs Always clocked at 40 MHz

WARPLab Architecture
Radio Board
Receiver RF Amplier Downconversion Receiver Base-Band Ampliers ADC I To Ethernet Rx Q Buffer ADC Q RSSI Buffer To Ethernet TxI Buffer DAC I From Ethernet TxQ Buffer DAC Q Transmitter RF Amplier Upconversion Transmitter Base-Band Ampliers

FPGA WARPLab Sysgen Core

Rx I Buffer

Antenna Switch

PLL

RSSI

ADC RSSI

Fixed Point 14_13 I/Q ADCs Always clocked at 40 MHz

WARPLab Architecture
Radio Board
Receiver RF Amplier Downconversion Receiver Base-Band Ampliers ADC I To Ethernet Rx Q Buffer ADC Q RSSI Buffer To Ethernet TxI Buffer DAC I From Ethernet TxQ Buffer DAC Q Transmitter RF Amplier Upconversion Transmitter Base-Band Ampliers

FPGA WARPLab Sysgen Core

Rx I Buffer

Antenna Switch

PLL

RSSI

ADC RSSI

RSSI ADC always clocked at 10 MHz 10 bit number

RADIO 1

FPGA

RADIO 4

RADIO 2

RADIO 3

WARPLab Architecture
Radio 1
Receiver RF Amplier Downconversion Receiver Base-Band Ampliers ADC I To Ethernet Rx Q Buffer ADC Q RSSI Buffer To Ethernet TxI Buffer DAC I From Ethernet TxQ Buffer DAC Q Transmitter RF Amplier Upconversion Transmitter Base-Band Ampliers Receiver Base-Band Ampliers ADC I To Ethernet Rx Q Buffer ADC Q RSSI Buffer To Ethernet TxI Buffer DAC I From Ethernet TxQ Buffer DAC Q Transmitter RF Amplier Upconversion Transmitter Base-Band Ampliers From Ethernet TxQ Buffer DAC Q Upconversion Transmitter Base-Band Ampliers Transmitter RF Amplier RSSI Buffer To Ethernet TxI Buffer DAC I To Ethernet Rx Q Buffer ADC Q From Ethernet TxQ Buffer DAC Q Upconversion Transmitter Base-Band Ampliers Receiver Base-Band Ampliers Downconversion ADC I Transmitter RF Amplier RSSI Buffer To Ethernet TxI Buffer DAC I To Ethernet Rx Q Buffer ADC Q Rx I Buffer

FPGA WARPLab Sysgen Core

Rx I Buffer ADC I

Radio 4
Receiver Base-Band Ampliers Downconversion Receiver RF Amplier

Antenna Switch

PLL

RSSI

ADC RSSI

ADC RSSI

RSSI

PLL

Antenna Switch

Receiver RF Amplier

Downconversion

Rx I Buffer

Rx I Buffer

Receiver RF Amplier

Antenna Switch

PLL

RSSI

ADC RSSI

ADC RSSI

RSSI

PLL

Antenna Switch

Radio 2

Radio 3

WARPLab Architecture

WARPLab Architecture
WARP node Daughter Cards
Radio 1 Radio 2 Radio 3 Radio 4 Radio Bridges FPGA I/O

Logic
WARPLab Reference Sysgen Radio Controller AGC

FPGA

PowerPC
WARPLab Reference C Code Radio Driver Ethernet MAC Driver Misc. Drivers

Host PC
WARPLab User M-Code Ethernet WARPLab Reference M-Code WARPLab M-Code Examples

PLB Ethernet MAC

WARPLab Architecture
WARP node Daughter Cards
Radio 1 Radio 2 Radio 3 Radio 4 Radio Bridges FPGA I/O

Logic
WARPLab Reference Sysgen Radio Controller AGC

FPGA

PowerPC
WARPLab Reference C Code Radio Driver Ethernet MAC Driver Misc. Drivers

Host PC
WARPLab User M-Code Ethernet WARPLab Reference M-Code WARPLab M-Code Examples

PLB Ethernet MAC

The WARPLab framework provides the following

Reference design Reference M-Code M-Code Examples

WARPLab Architecture
WARP node Daughter Cards
Radio 1 Radio 2 Radio 3 Radio 4 Radio Bridges FPGA I/O

Logic
WARPLab Reference Sysgen Radio Controller AGC

FPGA

PowerPC
WARPLab Reference C Code Radio Driver Ethernet MAC Driver Misc. Drivers

Host PC
WARPLab User M-Code Ethernet WARPLab Reference M-Code WARPLab M-Code Examples

PLB Ethernet MAC

The WARPLab framework provides the following

Reference design Reference M-Code M-Code Examples

WARPLab Architecture
WARP node Daughter Cards
Radio 1 Radio 2 Radio 3 Radio 4 Radio Bridges FPGA I/O

Logic
WARPLab Reference Sysgen Radio Controller AGC

FPGA

PowerPC
WARPLab Reference C Code Radio Driver Ethernet MAC Driver Misc. Drivers

Host PC
WARPLab User M-Code Ethernet WARPLab Reference M-Code WARPLab M-Code Examples

PLB Ethernet MAC

Reference design

XPS project that contains all the FPGA code required to program the WARP nodes

WARPLab Architecture
WARP node Daughter Cards
Radio 1 Radio 2 Radio 3 Radio 4 Radio Bridges FPGA I/O

Logic
WARPLab Reference Sysgen Radio Controller AGC

FPGA

PowerPC
WARPLab Reference C Code Radio Driver Ethernet MAC Driver Misc. Drivers

Host PC
WARPLab User M-Code Ethernet WARPLab Reference M-Code WARPLab M-Code Examples

PLB Ethernet MAC

Reference design

XPS project that contains all the FPGA code required to program the WARP nodes WARPLab Reference Sysgen - Ex: Buffers

WARPLab Architecture
WARP node Daughter Cards
Radio 1 Radio 2 Radio 3 Radio 4 Radio Bridges FPGA I/O

Logic
WARPLab Reference Sysgen Radio Controller AGC

FPGA

PowerPC
WARPLab Reference C Code Radio Driver Ethernet MAC Driver Misc. Drivers

Host PC
WARPLab User M-Code Ethernet WARPLab Reference M-Code WARPLab M-Code Examples

PLB Ethernet MAC

Reference design

XPS project that contains all the FPGA code required to program the WARP nodes WARPLab Reference Sysgen - Ex: Buffers WARPLab Reference C Code - Ex: Ethernet

WARPLab Architecture

Reference design

Bitsream (.bit) le to program the WARP nodes is provided Same bitstream for all nodes.

Any node can be Tx or Rx

All open source All code required to generate bitstream is available online

WARPLab Architecture
WARP node Daughter Cards
Radio 1 Radio 2 Radio 3 Radio 4 Radio Bridges FPGA I/O

Logic
WARPLab Reference Sysgen Radio Controller AGC

FPGA

PowerPC
WARPLab Reference C Code Radio Driver Ethernet MAC Driver Misc. Drivers

Host PC
WARPLab User M-Code Ethernet WARPLab Reference M-Code WARPLab M-Code Examples

PLB Ethernet MAC

The WARPLab framework provides the following

Reference design Reference M-Code M-Code Examples

WARPLab Architecture
WARP node Daughter Cards
Radio 1 Radio 2 Radio 3 Radio 4 Radio Bridges FPGA I/O

Logic
WARPLab Reference Sysgen Radio Controller AGC

FPGA

PowerPC
WARPLab Reference C Code Radio Driver Ethernet MAC Driver Misc. Drivers

Host PC
WARPLab User M-Code Ethernet WARPLab Reference M-Code WARPLab M-Code Examples

PLB Ethernet MAC

Reference M-Code

MATLAB Code (M-Code) functions that allow interaction with WARP nodes Ex:

warplab_writeSMWO(Node_ID,Buffer_ID,M_Vector)

WARPLab Architecture
WARP node Daughter Cards
Radio 1 Radio 2 Radio 3 Radio 4 Radio Bridges FPGA I/O

Logic
WARPLab Reference Sysgen Radio Controller AGC

FPGA

PowerPC
WARPLab Reference C Code Radio Driver Ethernet MAC Driver Misc. Drivers

Host PC
WARPLab User M-Code Ethernet WARPLab Reference M-Code WARPLab M-Code Examples

PLB Ethernet MAC

The WARPLab framework provides the following

Reference design Reference M-Code M-Code Examples

WARPLab Architecture
WARP node Daughter Cards
Radio 1 Radio 2 Radio 3 Radio 4 Radio Bridges FPGA I/O

Logic
WARPLab Reference Sysgen Radio Controller AGC

FPGA

PowerPC
WARPLab Reference C Code Radio Driver Ethernet MAC Driver Misc. Drivers

Host PC
WARPLab User M-Code Ethernet WARPLab Reference M-Code WARPLab M-Code Examples

PLB Ethernet MAC

M-Code Examples

Illustrate how to use the functions in the WARPLab Reference M-Code Todays Lab 1

WARPLab Architecture
WARP node Daughter Cards
Radio 1 Radio 2 Radio 3 Radio 4 Radio Bridges FPGA I/O

Logic
WARPLab Reference Sysgen Radio Controller AGC

FPGA

PowerPC
WARPLab Reference C Code Radio Driver Ethernet MAC Driver Misc. Drivers

Host PC
WARPLab User M-Code Ethernet WARPLab Reference M-Code WARPLab M-Code Examples

PLB Ethernet MAC

The WARPLab framework provides the following

Reference design Reference M-Code M-Code Examples

All open source

WARPLab Flow
I Buffer To DAC From Ethernet To DAC

Tx
Q Buffer
I Buffer

From ADC

Rx
To Ethernet

From ADC

Q Buffer

WARPLab Flow
I Buffer To DAC From Ethernet To DAC

Tx
Q Buffer
I Buffer

From ADC

Rx
To Ethernet

1. Initialize nodes & radio settings 2. Download Tx vectors

From ADC

Q Buffer

WARPLab Flow
I Buffer To DAC From Ethernet To DAC

Tx
Q Buffer
I Buffer

From ADC

Rx
To Ethernet

3. Enable Tx/Rx paths 4. Prime Tx/Rx state machines

From ADC

Q Buffer

WARPLab Flow
I Buffer

SYNC
From Ethernet

To DAC

To DAC

Tx
Q Buffer
I Buffer

From ADC

Rx
To Ethernet

5. Trigger the transmission and capture 6. Retrieve Rx vectors

From ADC

Q Buffer

Tx BB Signal Requirements
Amplitude of real part in [-1,1] Amplitude of imaginary part in [-1,1] Highest frequency 9.5 MHz (19 MHz BW) Lowest frequency 30 KHz 40 MHz sampling Note: Buffers persist between triggers

Tx to Rx path
Radio Board
Receiver RF Amplier Downconversion Receiver Base-Band Ampliers ADC I To Ethernet Rx Q Buffer ADC Q RSSI Buffer To Ethernet TxI Buffer DAC I TxQ Buffer DAC Q Transmitter RF Amplier Upconversion Transmitter Base-Band Ampliers

FPGA WARPLab Sysgen Core

Rx I Buffer

Tx

Antenna Switch

PLL

RSSI

ADC RSSI

From Ethernet

|Y| = |H| GRXBB GRXRF GTXPA GTXRF GTXBB |X| |H| : Wireless channel magnitude
Radio Board
Receiver RF Amplier Downconversion Receiver Base-Band Ampliers ADC I Rx Q Buffer ADC Q

FPGA WARPLab Sysgen Core

Rx I Buffer

Rx

To Ethernet

Antenna Switch

PLL

RSSI

ADC RSSI TxI Buffer DAC I

RSSI Buffer To Ethernet

From Ethernet TxQ Buffer DAC Q Transmitter RF Amplier Upconversion Transmitter Base-Band Ampliers

WARPLab Examples

Hardware characterization Channel measurement Sphere detection Cooperative communications Beamforming

Lab 1: WARPLab

WARPLab graphical interface SISO communication Measuring the wireless channel Building a real bits-to-RF transmitter Continuous transmitter mode Two-way communication 2x2 MIMO communication

WARPLab Overview

WARPLab Overview

WARPLab Overview

(2,3) (4,5) (7,8) (9,10)

WARPLab Overview
No Ack !

No Ack !
(2,3) (4,5) (7,8) (9,10)

WARPLab Overview

(2,3) (4,5) (7,8) (9,10)