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The TTL / MSI SN54 / 74LS170 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation. Open-collector outputs make it possible to connect up to 128 outputs in a wired-AND configuration to increase the word capacity up to 512 words. Any number of these devices can be operated in parallel to generate an n-bit length. The SN54 / 74LS670 provides a similar function to this device but it features 3-state outputs.
Simultaneous Read / Write Operation Expandable to 512 Words of n-Bits Typical Access Time of 20 ns Low Leakage Open-Collector Outputs for Expansion Typical Power Dissipation of 125 mW
16 1
1 D2
2 D3
3 D4
4 RB
5 RA
6 Q4
7 Q3
8 GND
ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC
PIN NAMES
LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.5 U.L. 0.25 U.L. 0.5 U.L. 5 (2.5) U.L.
LOGIC SYMBOL
12 14 13 5 4 WA EW WB RA RB ER 11 15 1 2 3 D1 D2 D3 D4 Q1 Q2 Q3 Q4 10 9 7 6
D1 D4 WA, WB EW RA, RB ER Q1 Q4
Data Inputs Write Address Inputs Write Enable (Active LOW) Input Read Address Inputs Read Enable (Active LOW) Input Outputs (Note b)
0.5 U.L. 0.5 U.L. 1.0 U.L. 0.5 U.L. 1.0 U.L. Open-Collector
NOTES: a. 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. The Output HIGH drive must be supplied by an external resistor to VCC.
SN54/74LS170
LOGIC DIAGRAM
D4
12 3
D3
2
D2
1
D1
15
EW
13
WB WA
14
G Q
G Q
G Q
G Q
WORD 0
G Q
G Q
G Q
G Q
WORD 1
G Q
G Q
G Q
G Q
WORD 2
G Q RB
4
G Q
G Q
G Q
WORD 3
11
ER RA
5
10
Q4
Q3
Q2
Q1
SN54/74LS170
WRITE FUNCTION TABLE (SEE NOTES A, B, AND C)
WRITE INPUTS WB L L H H X WA L H L H X EW L L L L H 0 Q=D Q0 Q0 Q0 Q0 1 Q0 Q=D Q0 Q0 Q0 WORD 2 Q0 Q0 Q=D Q0 Q0 3 Q0 Q0 Q0 Q=D Q0
NOTES: A. H = HIGH Level. L = LOW Level, X = Irrelevant. NOTES: B. (Q = D) = The four selected internal flip-flop outputs will assume the states applied to the four external data inputs. NOTES: C. Q0 = the level of Q before the indicated input conditions were established. NOTES: D. W0B1 = The first bit of word 0, etc.
IIH
mA
mA mA
SN54/74LS170
AC CHARACTERISTICS (TA = 25C)
Limits S b l Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL P Parameter Propagation Delay, NegativeGoing ER to Q Outputs Propagation Delay, RA or RB to Q Outputs Propagation Delay, NegativeGoing EW to Q Outputs Propagation Delay, Data Inputs to Q Outputs Min Typ 20 20 25 24 30 26 30 22 Max 30 30 40 40 45 40 45 35 U i Unit ns ns ns ns Figure 1 Figure 2 Figure 1 Figure 1 T Test C Conditions di i
VOLTAGE WAVEFORMS
3V 0V 3V 0V 3V 0V 3V Vref tW Vref tPHL Vref Vref tPLH Vref tPLH 0V 3V 0V VOH VOL
3V Vref 0V 3V Vref tPLH tPHL Vref VOL 3V Vref 0V 3V Vref tPHL tPLH Vref 0V 0V 3V 0V VOH
Vref
Vref
tPHL
Vref
Figure 1
Figure 2