TITLE:

Date: Page No: Roll No:12H61A0511 _____________________________________________________________________________ AIM:To write the program to implement operation of Half Adder and observe wave forms SOFTWARE REQUIRED:Xilinx software THEORY:

HALF ADDER

ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,

CSE DEPT.

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Date: Page No: Roll No:12H61A0511 _____________________________________________________________________________

VHDL CODE FOR HA1 GATE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity HA1 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; SUM : out STD_LOGIC; CARRY : out STD_LOGIC); end HA1; architecture df of HA1 is begin SUM <= A xor B; CARRY <= A and B; end df; OUTPUT WAVEFORM FOR HA1 GATE:

HALF ADDER

RTL SCHEMATIC FOR HA1 GATE: TOPVIEW

INTERNAL HARDWARE CIRCUIT DIAGRAM

ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,

CSE DEPT.

TITLE:

Date: Page No: Roll No:12H61A0511 _____________________________________________________________________________

VHDL CODE FOR HA-BEHAVIORAL GATE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity HA_Behavioral is Port ( A : in STD_LOGIC; B : in STD_LOGIC; SUM : out STD_LOGIC; CARRY : out STD_LOGIC); end HA_Behavioral; architecture Behavioral of HA_Behavioral is begin process (A,B) begin if (A = '0' and B = '0') then SUM <= '0'; CARRY <= '0'; elsif (A = '0' and B = '1') then SUM <= '1'; CARRY <= '0'; elsif (A = '1' and B = '0') then SUM <= '1'; CARRY <= '0'; else SUM <= '0'; CARRY <= '1'; end if; end process; end Behavioral; OUTPUT WAVEFORM FOR HA-BEHAVIORAL GATE:

HALF ADDER

ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,

CSE DEPT.

TITLE:

Date: Page No: Roll No:12H61A0511 _____________________________________________________________________________

RTL SCHEMATIC FOR HA-BEHAVIORAL GATE: TOPVIEW

HALF ADDER

INTERNAL HARDWARE CIRCUIT DIAGRAM

ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,

CSE DEPT.

TITLE:

Date: Page No: Roll No:12H61A0511 _____________________________________________________________________________

VHDL CODE FOR HA-STRUCTURAL GATE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity HA_STRUCTURAL is Port ( A : in STD_LOGIC; B : in STD_LOGIC; SUM : out STD_LOGIC; CARRY : out STD_LOGIC); end HA_STRUCTURAL; architecture STRUCTURAL of HA_STRUCTURAL is component EXOR_GATE is Port ( P : in STD_LOGIC; Q : in STD_LOGIC; Y_EXOR : out STD_LOGIC); end component; component AND_GATE is Port ( L : in STD_LOGIC; M : in STD_LOGIC; Y_AND : out STD_LOGIC); end component; begin X1: EXOR_GATE port map (A,B,SUM); A1: AND_GATE port map(A,B,CARRY); end STRUCTURAL; OUTPUT WAVEFORM FOR HA-STRUCTURAL GATE:

HALF ADDER

ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,

CSE DEPT.

TITLE:

Date: Page No: Roll No:12H61A0511 _____________________________________________________________________________

RTL SCHEMATIC FOR HA-STRUCTURAL GATE: TOPVIEW

HALF ADDER

INTERNAL HARDWARE CIRCUIT DIAGRAM

ANURAG GROUP OF INSTITUTIONS, Venktapur (V), Ghatkesar (M), Ranga Reddy (Dist.), A.P, INDIA,

CSE DEPT.