Bao Cao Thuc Tap VXL Nguyen Duy Tuong 688

TRNG AI HOC S PHAM KY THUAT TP.
HCM
KHOA IEN IEN T
2010

VI IEU KHIEN PIC
BAO CAO TT VI X LY
GVHD: NGUYEN VAN HIEP
SVTH: NGUYEN DUY TNG
NGUYEN MINH TA I
A I H O C S P H A M K Y T H U A T
Muc Luc

CHNG 1.TONG QUAT VE VI IEU KHIEN PIC .............................................
1.AC TNH CHUNG .......................................................................................... 3
2.KIEN TRU C CUA PIC ...................................................................................... 5
3.RISC-CISC ........................................................................................................ 5
4.PIPELING .......................................................................................................... 6
5.CAC DONG PIC VA CACH LA CHON PIC ................................................. 7
6.NGON NG LAP TRNH CHO PIC ................................................................. 8
7.MACH NAP PIC ............................................................................................... 8

CHNG 2.KHAO SAT VK PIC16F877A. ............................................................
I.CAU TRUC VK PIC16F877A ......................................................................... 9
1.S O CHAN VK ...................................................................................... 9
2.S O KHOI VK ...................................................................................... 11
3.MOT SO THONG TIN ................................................................................. 12
II.TO CHC BO NH ......................................................................................... 13
1.BO NH CHNG TRNH ......................................................................... 13
2.BO NH D LIE U ....................................................................................... 13
3.CAC CONG XUA T NHAP CUA PIC .......................................................... 21
4.TIMER0 ........................................................................................................ 27
5.TIMER1 ........................................................................................................ 29
6.TIMER2 ........................................................................................................ 31
7.ADC .............................................................................................................. 32
8.COMPARATOR ........................................................................................... 34
9.BO NH IEN A P SO SANH ..................................................................... 36
10.CCP ............................................................................................................. 37
11.GIAO TIEP NOI TIEP ................................................................................ 42
12.GIAO TIEP SONG SONG .......................................................................... 68
13.TONG QUAN VE MO T SO AC TNH CUA CPU .................................. 70

CHNG 3.CHNG TRNH BIEN DCH VA MACH NAP VK ....................
I.CHNG TRNH BIEN DCH CHO VK PIC16F877A ............................... 76
1.PHAN MEM BIEN DCH MPLAB ........................................................... 76
2.PHAN MEM BIEN DCH CCS ................................................................. 87
II.CHNG TRNH MACH NAP VK PIC16F877A ...................................... 92
1.CHNG TRNH NAP WINPIC800 ........................................................ 92
2.CHNG TRNH NAP IC-PRO ............................................................... 93

CHNG 4.TAP LENH CHO VI IEU KHIEN PIC16F877A ..............................
1.NGON NG LAP TRNH ASM CUA MPLAB .............................................. 97
2.NGON NG LAP TRNH C CUA CCS C .................................................... 105

CHNG 5.MOT SO CHNG TRNH NG DUNG ...................................... 109
1.IEU KHIEN I/O .......................................................................................... 109
2.CHNG TRNH DELAY ........................................................................... 111
3.MOT SO CHNG TRNH VE AC TNH I/O CA C PORT K ............... 116
4.MOT SO BAI TAP MAU THAM KHAO CAC CH NANG CU A PIC ...... 130

PHU LUC 2 THANH GHI SFR (SPECIAL FUNCTION REGISTER) ........... 196
TAI LIEU THAM KHAO ....................................................................................... 221

Chng 1
Tong quan ve vi ieu khien Pic

1. AC TNH CHUNG.
Pic la mo t ho Vi ieu khien RISC c san xuat bi cong ty Microchip Technology.
Dong Pic a u tie n la PIC1650 c phat trien bi Microelectronics Dicision thuoc
General Instrument
PIC la viet ta t cua Programable Intelligent Computer, co the ta m dch la ma y
tnh thong minh kha trnh do hang Genenral Instrument at ten cho vi ieu khien a u
tien cua ho: PIC1650 c thie t ke e dung lam ca c thiet b ngoa i vi cho vi ieu khien
CP1600. Vi ieu khie n nay sau o c nghien c u pha t trien them va t o hnh thanh
nen dong vi ieu khie n PIC nga y nay.
Hien nay co kha nhie u dong vi ieu khie n Pic kha c nhau nh chung cung co
chung 1 a c ie m nh sau:
+ S dung cong nghe tch hp cao RISC CPU
+ Ngi s dung co the la p trnh vi 35 ca u lenh n gian
+ Tat ca ca c cau le nh thc hie n trong mot chu k lenh ngoa i tr moi so cau lenh re
nhanh thc hien trong 2 chu k le nh.
+ Toc o hoa t ong la : - Xung ong bo va o la DC-20MHz
- Chu ky lenh thc hien trong 200ns
+ Bo nh chng trnh Flash 8K*14 Words
+ Bo nh Ram 368*8 bytes
+ Bo nh EFPRom 256*8 bytes
Kha nang cua bo vi x ly nay:
+ Kha nang nga t len ti 14 nguon nga t trong va nga t ngoai
+ Ngan nh Stack c pha n chia lam 8 mc
+ Truy cap bo nh bang a ch trc tiep hoa c gian tiep,
+ Nguon khoi ong la i (POR)
+ Bo tao xung thi gian (PWRT) va bo ta o dao ong (OST)
+ Bo em xung thi gian (WDT) vi nguon dao ong tren chp (nguon dao ong
RC) hoat ong ang tin cay
+ Co ma chng trnh bao ve
+ Phng thc ca t gi SLEEP
BAO CAO TT VI X LY trang 4
+ Co ba ng la chong dao ong
+ Cong nhe CMOS FLASH/EEPROM nguong m c thap, toc o cao.
+ Thie t ke hoan toan tnh
+ Mach chng trnh noi tiep co 2 chan
+ Vi x ly o c/ghi bo nh chng trnh
+ Dai ien the hoat do ng ro ng : 2.0 v en 5.5v
+ Nguon s dung hien tai 25mA
+ Day nhie t o cong nghiep va thuan l i.
+ Cong suat tieu thu thap:
< 0.6 mA vi 5V.4MHz
20uA vi nguon ,32KHs
<1uA nguon d phong
Cac a c tnh noi bat cua thie t b ngoai vi tre n chp
+ Timer 0: 8bit cua bo nh thi, bo em vi he so ty le trc
+ Timer 1: 16bit cua bo nh thi, bo e m vi he so t le, co kha nang tang trong
khi che o Sleep qua xung ong ho c cung cap ben ngoa i.
+ Timer 2: 8 bit cua bo nh th i, bo e m vi 8bit cua he so t le trc va he so t le
sau
+ Co 2 che o ba t gi, so sanh, ie u che o rong xung (PWM).
+ Che o ba t gi vi 16 bt vi toc o 12.5ns, che o so sanh vi 16bit, toc o gia i
quyet c c a i la 200ns, che o rong xung vi 10bit.
+ Bo chuyen oi tn hieu so sang tng t v i 10bit.
+ Cong truyen thong noi tiep SSP vi SPI phng thc chu (chu/t )
+ Bo truyen nhan thong tin ong bo, d bo (USART/SCL) co kha nang phat hien
9bit a ch.
+ Cong phu song song (PSP) v i 8bit m ro ng, vi RD, WR va CS ie u khie n.

2. KIEN TRUC CUA PIC
Cau truc pha n cng cu a mo t vi ieu khien c thie t ke theo hai da ng kien truc:
kie n truc Von Neuman va kien truc Havard.

Hnh 1.1: kieu kien tru c Harvard va Von-Neumann
To chc pha n cng cua PIC c thie t ke theo kien tru c Havard. ie m kha c bie t
gia kien truc Havard va kien truc Von-Neuman la cau truc bo nh d lieu va bo nh
chng trnh.oi vi kie n truc Von-Neuman, bo nh d lie u va bo nh chng trnh
nam chung trong mot bo nh, do o ta co the to chc, can oi mot cach linh hoa t bo
nh chng trnh va bo nh dlieu. Tuy nhien ieu nay ch co y ngha khi to c o x l
cua CPU phai ra t cao, v vi cau truc o, trong cung mot thi iem CPU ch co the
tng tac v i bo nh d lieu hoac bo nh chng trnh. Nh vay co the noi kien truc
Von-Neuman khong thch hp vi cau tru c cua mo t vi ie u khien.o i vi kien truc
Havard, bo nh d lie u va bo nh chng trnh ta ch ra thanh hai bo nh rieng biet. Do
o trong cu ng mot thi ie m CPU co the tng ta c vi ca hai bo nh, nh vay to c o x
l cua vi ieu khie n c cai thien ang ke. Mo t ie m ca n chu y na la tap lenh trong
kie n truc Havard co the c to i u tuy theo yeu cau kien truc cua vi ieu khien ma
khong phu thuoc vao cau truc d lieu. V du, oi v i vi ieu khien dong 16F, o da i
lenh luon la 14 bit (trong khi d lieu c to chc thanh tng byte), con oi vi kien
truc Von-Neuman, o dai le nh luon la boi so cua 1 byte (do d lie uc to chc tha nh
tng byte). ac iem nay c minh hoa cu the trong hnh 1.1.

3. RISC va CISC
Nh a trnh bay tren, kien truc Havard la khai niem m i hn so vi kien truc
Von-Neuman. Kha i niem nay c hnh tha nh nha m ca i tien to c o thc thi cua mot vi
ie u khien.Qua viec tach ri bo nh chng trnh va bo nh d lieu, bus chng trnh
va bus d lie u,CPU co the cu ng mo t luc truy xuat ca bo nh chng trnh va bo nh d
lieu, giup tang to c o x l cua vi ie u khien len gap oi. o ng thi cau truc le nh
khong con phu thuo c vao cau truc d lieu na ma co the linh ong ieu chnh tu y theo
kha nang va toc o cu a tng vi ie u khien. Va e tie p tu c cai tien to c o thc thi lenh,
tap lenh cua ho vi ie u khie n PIC c thiet ke sao cho chieu dai ma le nh luon co nh
(v du o i vi ho 16Fxxxx chieu dai ma lenh luon la 14 bit) va cho phep th c thi le nh
trong mo t chu k cua xung clock ( ngoai tr mo t so trng hp ac biet nh le nh nhay,
lenh goi chng trnh con ca n hai chu k xung ong ho).ie u na y co ngha tap lenh
cua vi ieu khien thuoc cau truc Havard se t lenh hn, ngan hn, n gian hn e a p
ng yeu ca u ma hoa lenh ba ng mot so lng bit nhat nh.Vi ie u khien c to chc
theo kien truc Havard con c goi la vi ie u khie n RISC(Reduced Instruction Set
Computer) hay vi ieu khie n co tap lenh rut gon. Vi ie u khien c thiet ke theo kien
truc Von-Neuman co n c goi la vi ie u khie n CISC (Complex Instruction Set
Computer) hay vi ieu khien co tap lenh phc tap v ma lenh cua no khong phai la mo t
so co nh ma luon la boi so cua 8 bit (1 byte).

4. PIPELINING
ay chnh la c che x l lenh cua ca c vi ieu khien PIC. Mo t chu k le nh cua vi
ie u khien se bao gom 4 xung clock. V du ta s dung oscillator co ta n so 4 MHZ, th
xung lenh se co tan so 1 MHz (chu k lenh se la 1 us). Gia s ta co mo t oan chng
trnh nh sau:
1. MOVLW 55h
2. MOVWF PORTB
3. CALL SUB_1
4. BSF PORTA,BIT3
5. instruction @address SUB_1
ay ta ch ba n en qui trnh vi ie u khie n x l oan chng trnh tren thong
qua tng chu k le nh. Qua trnh tren se c thc thi nh sau
Hnh 1.2 : c che Pipelining
TCY0: oc lenh 1
TCY1: thc thi lenh 1, oc lenh 2
TCY2: thc thi lenh 2, oc lenh 3
TCY3: thc thi lenh 3, oc lenh 4.
TCY4: v lenh 4 khong pha i la lenh se c thc thi theo qui trnh thc thi
cua chng trnh (lenh tiep theo c thc thi pha i la lenh au tie n ta i
label SUB_1)nen chu k th c thi lenh na y ch c dung e oc lenh a u
tien tai label SUB_1. Nh vay co the xem lenh 3can 2 chu k xung clock
e thc thi.
TCY5: thc thi lenh au tien cua SUB_1 va oc lenh tiep theo cua SUB_1.
Qua trnh nay c thc hie n tng t cho ca c lenh tiep theo cua chng
trnh.Thong thng, e thc thi mot le nh, ta can mo t chu k le nh e goi le nh o, va mo t
chu k xung clock na e gia i ma va thc thi lenh. Vi c che pipelining c trnh bay
tren, moi lenh xem nh ch c thc thi trong mo t chu k lenh. oi vi ca c lenh ma
qua trnh thc thi no la m thay oi gia tr thanh ghi PC (Program Counter) can hai chu k
lenh e thc thi v phai th c hien vie c goi lenh a ch thanh ghi PC ch ti. Sau khi
a xa c nh ung v tr lenh trong thanh ghi PC, moi lenh ch ca n mot chu k lenh e
thc thi xong

5. CAC DONG PIC VA CACH LA CHON VI IEU KHIEN PIC
Cac k hie u cua vi ie u khien PIC:
PIC12xxxx: o dai lenh 12 bit
C: PIC co bo nh EPROM (ch co 16C84 la EEPROM)
F: PIC co bo nh flash
LF: PIC co bo nh flash hoa t ong ien ap thap
LV: tng t nh LF, ay la k hieu cu
Ben canh o mot so vi ieu khien co k hie u xxFxxx la EEPROM, neu co them
ch A cuoi la flash (v du PIC16F877 la EEPROM, con PIC16F877A la flash). Ngoai
ra con co the m mo t dong vi ieu khien PIC m i la dsPIC.
Vie t Nam pho bien nhat la cac ho vi ieu khien PIC do hang Microchip san
xuat.Cach la chon mot vi ie u khie n PIC phu hp:
Trc he t ca n chu y en so chan cua vi ie u khien can thie t cho ng du ng. Co
nhieu vi ieu khien PIC vi so lng chan khac nhau, tham ch co vi ieu khien ch co
8 cha n,ngoai ra con co cac vi ieu khien 28, 40, 44, chan.Can chon vi ieu khien PIC
co bo nh flash e co the nap xoa chng trnh c nhie u lan hn.Tiep theo can chu y
en cac khoi chc nang c tch hp san trong vi ie u khien, cac chuan giao tie p ben
trong.Sau cung can chu y en bo nh chng trnh ma vi ieu khien cho phep.Ngoa i ra
mo i thong tin ve cach la chon vi ieu khien PIC co the c tm thay trong cuon sa ch
Select PIC guide do nha san xuat Microchip cung cap.

6. NGON NG LAP TRNH CHO PIC
Ngon ng la p trnh cho PIC rat a da ng. Ngon ng lap trnh cap thap co MPLAB
( c cung cap mie n ph bi nha san xuat Microchip), ca c ngon ng lap trnh cap cao
hn bao gom C,Basic, Pascal, Ngoai ra co n co mot so ngon ng la p trnh c pha t
trien danh rieng cho PIC nh PICBasic, MikroBasic,

7. MACH NAP PIC
ay cung la mo t dong san pha m rat a dang danh cho vi ieu khie n PIC. Co the
s dung cac mach nap c cung cap bi nha san xuat la hang Microchip nh:
PICSTART plus, MPLAB ICD 2, MPLAB PM 3, PRO MATE II. Co the dung cac san
pham na y e nap cho vi ieu khien khac thong qua chng trnh MPLAB. Dong san
pham chnh thong na y co u the la nap c cho ta t ca cac vi ieu khien PIC, tuy nhien
gia tha nh rat cao va thng gap rat nhieu kho khan trong qua trnh mua san
pham.Ngoa i ra do tnh nang cho phep nhie u che o nap khac nhau, con co ra t nhieu
mach nap c thiet ke danh cho vi ie u khien PIC. Co the s lc mot so mach nap
cho PIC nh sau:
JDM programmer: ma ch nap nay dung chng trnh nap Icprog cho phep na p ca c vi
ie u khien PIC co ho tr tnh nang na p chng trnh ien ap thap ICSP (In Circuit
Serial Programming). Hau het ca c mach nap eu ho tr tnh na ng nap chng trnh
nay.
WARP-13A va MCP-USB: hai ma ch nap nay gio ng vi ma ch nap PICSTART PLUS
do nha san xuat Microchip cung cap, tng thch vi trnh bien dch MPLAB, ngha la
ta co the tr c tie p dung chng trnh MPLAB e nap cho vi ieu khien PIC ma khong
can s dung mo t chng trnh nap kha c, cha ng han nh ICprog.
P16PRO40: ma ch nap nay do Nigel thie t ke va cung kha no i tieng. Ong con thie t ke
ca chng trnh nap, tuy nhien ta cung co the s dung chng trnh nap Icprog.

Chng 2
Khao sat vi ieu khien Pic16f877A

I. CAU TRUC VI IEU KHIEN PIC16F877A
1. S o chan vi ieu khien Pic16f877A


Hnh 2.1 Vi ieu khie n PIC16F877A/PIC16F874A va cac da ng s o chan
2. s o khoi cua vi ieu khien Pic 16f877A

Hnh 2.2 S o khoi vi ie u khien PIC16F877A.

3. Mot vai thong tin ve PIC16f877A
ay la vi ieu khien thuoc ho PIC16Fxxx vi tap lenh gom 35 le nh co o da i 14
bit.Mo i lenh eu c thc thi trong mot chu k xung clock. To c o hoat ong toi a
cho phep la 20 MHz vi mo t chu k lenh la 200ns. Bo nh chng trnh 8Kx14 bit, bo
nh d lieu 368x8 byte RAM va bo nh d lieu EEPROM vi dung lng 256x8 byte.
So PORT I/O la 5 vi 33 pin I/O.
Cac a c tnh ngoai vi bao go mcac khoi chc nang sau:
Timer0: bo em 8 bit vi bo chia ta n so 8 bit.
Timer1: bo em 16 bit vi bo chia tan so, co the thc hie n chc na ng em
da vao.xung clock ngoai vi ngay khi vi ieu khie n hoa t ong che o
sleep.
Timer2: bo em 8 bit vi bo chia ta n so, bo postcaler.
Hai bo Capture/so sanh/ieu che o rong xung.
Cac chuan giao tiep noi tiep SSP (Synchronous Serial Port), SPI va I2C.
Chuan giao tiep noi tiep USART vi 9 bit a ch.
Cong giao tiep song song PSP (Parallel Slave Port) vi ca c chan ieu
khien RD, WR,CS ben ngoai.
Cac a c tnh Analog:8 kenh chuyen oi ADC 10 bit.Hai bo so sanh.Ben ca nh o
la mot va i a c tnh khac cua vi ieu khien nh:
Bo nh flash vi kha nang ghi xoa c 100.000 lan.
Bo nh EEPROM vi kha nang ghi xoa c 1.000.000 lan.
D lieu bo nh EEPROM co the lu tr tren 40 na m.
Kha nang t nap chng trnh vi s ieu khien cua phan mem.
Nap c chng trnh ngay tren ma ch ien ICSP (In Circuit Serial
Programming) thong qua 2 chan.
Watchdog Timer vi bo dao ong trong.
Chc nang bao ma t ma chng trnh.
Che o Sleep.
Co the hoa t ong vi nhie u dang Oscillator khac nhau.

II. TO CHC BO NH
Cau truc bo nh cua vi ieu khien PIC16F877A bao gom bo nh chng trnh
(Program memory) va bo nh d lieu (Data Memory).

1. BO NH CHNG TRNH
Bo nh chng trnh cua vi ieu khie n
PIC16F877A la bo nh flash, dung lng
bonh 8K word (1 word = 14 bit) va c
phan thanh nhieu trang (t page 0 en page
3). Nh vay bo nh chng trnh co kha
nang cha c 8*1024 = 8192 le nh (v mot
lenh sau khi ma hoa se co dung lng 1
word (14bit). e ma hoa c a ch cua
8K word bo nh chng trnh, bo e m
chng trnh co dung lng 13 bit
(PC<12:0>). Khi vi ieu khien c reset,
bo emchng trnh se ch en a ch 0000h
(Reset vector). Khi co nga t xay ra, bo e m
chng trnh se ch en a ch 0004h
(Interrupt vector).
Bo nh chng trnh khong bao gom
bo nh stack va khong c a ch hoa bi
bo em chng trnh. Bo nh stack se c
e cap cu the trong phan sau.
Hnh 2.3 Bo nh chng trnh PIC16F877A
2. BO NH D LIEU
Bo nh d lieu cua PIC la bo nh EEPROM c chia ra lam nhie u bank. oi v i
PIC16F877A bo nh d lie u c chia ra la m 4 bank. Mo i bank co dung lng 128
byte, bao gom ca c thanh ghi co ch c nang ac bie t SFG (Special Function Register)
nam cac vung a ch thap va cac thanh ghi mu c ch chung GPR (General Purpose
Register) na m vung a ch con lai trong bank. Ca c thanh ghi SFR thng xuyen c
s dung (v du nh thanh ghi STATUS) se c a t tat ca cac bank cua bo nh d
lieu giup thuan tie n trong qua trnh truy xua t va lam gia m bt lenh cua chng trnh. S
o cu the cua bo nh d lie u PIC16F877A nh sau:

Hnh 2.4 S o bo nh d lie u PIC16F877A

2.1 Thanh ghi cha nang ac biet cua SFR
ay la ca c thanh ghi c s dung b i CPU hoac c dung e thie t lap va ieu
khien cac khoi chc nang c tch hp ben trong vi ieu khien. Co the phan thanh ghi
SFR la m hai loai: thanh ghi SFR lien quan en ca c chc nang ben trong (CPU) va
thanh ghi SRF dung e thie t la p va ieu khien ca c khoi chc nang be n ngoai (v du nh
ADC, PWM, ). Phan nay se e cap en cac thanh ghi lie n quan en ca c chc nang
ben trong. Ca c thanh ghi dung e thiet lap va ieu khien ca c kho i chc nang se c
nhac en khi ta e cap en cac khoi chc na ng o.
Thanh ghi STATUS (03h, 83h, 103h, 183h):thanh ghi cha ket qua thc hie n
phep toa n cua khoi ALU, trang tha i reset va ca c bit chon bank can truy xuat trong bo
nh d lieu.

Bit 7: IRP bit chon bank bo nh d lieu can truy xua t (dung cho a ch gian
tiep).
IRP = 0: bank 2,3 (t 100h en 1FFh)
IRP = 1: bank 0,1 (t 00h en FFh)
Bit 6,5:RP1:RP0 hai bit chon bank bo nh d lieu can truy xua t (dung cho a ch
trc tiep)

RP1:RP2 BANCK
00 0
01 1
10 2
11 3

Bit 4: bit ch th trang tha i cua WDT(Watch Dog Timer)
=1 khi vi ieu khien va c cap nguon, hoac sau khi le nh
CLRWDT hay SLEEP c thc thi.
=0 khi WDT b tran
Bit 3: bit ch th trang tha i nguon
= 1 khi vi ieu khien c ca p nguon hoa c sau lenh CLRWDT
= 0 sau khi lenh SLEEP c thc thi
Bit 2: Z bit Zero
Z =1 khi ket qua cua phep toan hay logic bang 0
Z = 0 khi ket qua cua phep toa n hay logic khac 0
Bit 1:DC Digit carry/Borrow
DC = 1 khi ket qua phep toan tac ong len 4 bit tha p co nh.
DC = 0 khi ket qua phep toan tac ong len 4 bit tha p khong co nh.
Bit 0: C Carry/borrow
C =1 khi ket qua phep toan ta c ong len bit MSB co nh.
C=0 khi ket qua phep toan ta c ong len bit MSB khong co nh.
Thanh ghi OPTION_REG (81h, 181h): thanh ghi nay cho phep oc va ghi, cho
phep ie u khien chc nang pull-up cua ca c chan trong PORTB, xa c lap cac tham so ve
xung tac ong, canh ta c ong cua ngat ngoa i vi va bo em Timer0.

Bit 7: PORTB pull-up enable bit
= 1 khong cho phep chc nang pull-up cua PORTB
= 0 cho phep chc na ng pull-up cua PORTB
Bit 6: INTEDG Interrupt Edge Select bit
INTEDG = 1 nga t xa y ra khi canh dng cha n RB0/INT xua t hien.
INTEDG = 0 nga t xa y ra khi canh am cha n BR0/INT xuat hien.
Bit 5 TOCS Timer0 Clock Source select bit
TOSC = 1 clock lay t chan RA4/TOCK1.
TOSC = 0 dung xung clock ben trong (xung clock nay ba ng vi
xung clock dung e thc thi lenh).
Bit 4 TOSE Timer0 Source Edge Select bit
TOSE = 1 ta c ong ca nh len.
TOSE = 0 ta c ong ca nh xuong.
Bit 3 PSA Prescaler Assignment Select bit
PSA = 1 bo chia tan so (prescaler) c dung cho WDT
PSA = 0 bo chia ta n so c dung cho Timer0
Bit 2:0 PS2:PS0 Prescaler Rate Select bit
Cac bit nay cho phep thie t lap t so chia tan so cua Prescaler

Bit value TMR0 Rate WDT Rate
000 1:2 1:1
001 1:4 1:2
010 1:8 1:3
011 1:16 1:8
100 1:32 1:16
101 1:64 1:32
110 1:128 1:64
111 1:256 1:128

Thanh ghi INTCON (0Bh, 8Bh,10Bh, 18Bh):thanh ghi cho phep oc va ghi,cha
cac bit ieu khien va cac bit c hie u khi timer0 b tran, nga t ngoai vi RB0/INT va nga t
interrput-on-change ta i ca c chan cua PORTB.

Bit 7 GIE Global Interrupt Enable bit
GIE = 1 cho phep ta t ca cac nga t.
GIE = 0 khong cho phep tat ca cac nga t.
Bit 6 PEIE Pheripheral Interrupt Enable bit
PEIE = 1 cho phep ta t ca ca c ngat ngoa i vi
PEIE = 0 khong cho phep tat ca ca c nga t ngoai vi
Bit 5 TMR0IE Timer0 Overflow Interrupt Enable bit
TMR0IE = 1 cho phep ngat Timer0
TMR0IE = 0 khong cho phep nga t Timer0
Bit 4 RBIE RB0/INT External Interrupt Enable bit
RBIE = 1 cho phep ngat ngoai vi RB0/INT
RBIE = 0 khong cho phep ngat ngoa i vi RB0/INT
Bit 3 RBIE RB Port change Interrupt Enable bit
RBIE = 1 cho phep ngat RB Port change
RBIE = 0 khong cho phep ngat RB Port change
Bit 2 TMR0IF Timer0 Interrupt Flag bit
TMR0IF = 1 thanh ghi TMR0 b tran (pha i xoa bang chngtrnh) .
TMR0IF = 0 thanh ghi TMR0 cha b tran.
Bit 1 INTF BR0/INT External Interrupt Flag bit
INTF = 1 nga t RB0/INT xay ra (phai xoa c hieu bang
chngtrnh).
INTF = 0 ngat RB0/INT cha xay ra.
Bit 0 RBIF RB Port Change Interrupt Flag bit
RBIF = 1 t nha t co mot cha n RB7:RB4 co s thay oi trangthai.Bit
nay phai c xoa bang chng trnh sau khi a kie m tra laica c gia
tr cua ca c chan tai PORTB.
RBIF = 0 khong co s thay oi tra ng tha i ca c chan RB7:RB4.
Thanh ghi PIE1 (8Ch): cha cac bit ie u khien chi tie t ca c ngat cu a cackhoi chc
nang ngoai vi.
Bit
7 PSPIE Parallel Slave Port Read/Write Interrupt Enable bit
PSPIE = 1 cho phep ngat PSP read/write.
PSPIE = 0 khong cho phep nga PSP read/write.
Bit 6 ADIE ADC (A/D converter) Interrupt Enable bit
ADIE = 1 cho phep ngat ADC.
ADIE = 0 khong cho phep ngat ADC.
Bit 5 RCIE USART Receive Interrupt Enable bit
RCIE = 1 cho phep ngat nha n USART
RCIE = 0 khong cho phepn gat nhan USART
Bit 4 TXIE USART Transmit Interrupt Enable bit
TXIE = 1 cho phep ngat truyen USART
TXIE = 0 khong cho phep ngat truyen USART
Bit 3 SSPIE Synchronous Serial Port Interrupt Enable bit
SSPIE = 1 cho phep ngat SSP
SSPIE = 0 khong cho phep nga t SSP
Bit 2 CCP1IE CCP1 Interrupt Enable bit
CCP1IE = 1 cho phep ngat CCP1
CCP1IE = 0 khong cho phep nga t CCP1
Bit 1 TMR2IE TMR2 to PR2 Match Interrupt Enable bit
TMR2IE = 1 cho phep ngat.
TMR2IE = 0 khong cho phep nga t.
Bit 0 TMR1IE TMR1 Overflow Interrupt Enable bit

Thanh ghi PIR1 (0Ch) cha c ngat cua cac khoi ch c nang ngoai vi, cac nga t
nay c cho phep bi cac bit ieu khien ch a trong thanh ghi PIE1.

Bit 7 PSPIF Parallel Slave Port Read/Write Interrupt Flag bit
PSPIF = 1 va hoan ta t thao ta c oc hoa c ghi PSP (phai xoa bang
chng trnh).
PSPIF = 0 kho ng co thao tac oc ghi PSP na o dien ra.
Bit 6 ADIF ADC Interrupt Flag bit
ADIF = 1 hoan ta t chuyen oi ADC.
ADIF = 0 cha hoa n tat chuyen oi ADC.
Bit 5 RCIF USART Receive Interrupt Flag bit
RCIF = 1 buffer nha n qua chuan giao tiep USART a ay.
RCIF = 0 buffer nha n qua chuan giao tiep USART rong.
Bit 4 TXIF USART Transmit Interrupt Flag bit
TXIF = 1 buffer truye n qua chuan giao tiep USART rong.
TXIF = 0 buffer truye n qua chuan giao tiep USART ay.
Bit 3 SSPIF Synchronous Serial Port (SSP) Interrupt Flag bit
SSPIF = 1 nga t truyen nhan SSP xay ra.
SSPIF = 0 nga t truyen nhan SSP cha xay ra.
Bit 2 CCP1IF CCP1 Interrupt Flag bit
Khi CCP1 che o Capture
CCP1IF=1 a ca p nha t gia tr trong thanh ghi TMR1.
CCP1IF=0 cha cap nhat gia tr trong thanh ghi TMR1.
Khi CCP1 che o Compare
CCP1IF=1 gia tr ca n so sanh ba ng vi gia tr cha trong
TMR1
CCP1IF=0 gia tr ca n so sanh khong bang vi gia tr trong
TMR1
Bit 0 TMR1IF TMR1 Overflow Interrupt Flag bit
TMR1IF = 1 thanh ghi TMR1 b tran (pha i xoa bang chng
trnh).

Thanh ghi PIE2 (8Dh): cha cac bit ie u khien cac ngat cua ca c khoi chc nang
CCP2, SSP bus, nga t cua bo so sanh va nga t ghi vao bo nh EEPROM

Bit 7, 5, 2, 1 Khong ca n quan tam va mac nh mang gia tr 0.
Bit 6 CMIE Comparator Interrupt Enable bit
CMIE = 1 Cho phep ngat cua bo so sa nh.
CMIE = 0 Khong cho phep nga t.
Bit 4 EEIE EEPROM Write Operation Interrupt Enable bit
EEIE = 1 Cho phep ngat khi ghi d lieu len bo nh EEPROM.
EEIE = 0 Khong cho phep nga t khi ghi d lieu len bo nh
EEPROM.
Bit 3 BCLIE Bus Collision Interrupt Enable bit
BCLIE = 1 Cho phep ngat.
BCLIE = 0 Khong cho phep nga t.
CCP2IE = 1 Cho phep ngat.
CCP2IE = 0 Khong cho phep nga t.
Thanh ghi PIR2 (0Dh): cha cac c nga t cua ca c khoi chc na ng ngoai vi, ca c
ngat nay c cho phe p bi ca c bit ieu khie n cha trong thanh ghi PIE2.

Bit 7, 5, 2, 1: khong quan ta m va ma c nh mang gia tr 0.
Bit 6 CMIF Comparator Interrupt Flag bit
CMIF = 1 tn hieu ngo vao bo so sanh thay oi.
CMIF = 0 tn hieu ngo vao bo so sanh khong thay oi.
Bit 4 EEIF EEPROM Write Operation Interrupt Flag bit
EEIF = 1 qua trnh ghi d lieu len EEPROM hoan tat.
EEIF = 0 qua trnh ghi d lieu le n EEPROM cha hoan ta t hoac cha bat
au.
Bit 3 BCLIF Bus Collision Interrupt Flag bit
BCLIF = 1 Bus truyen nhan ang ban khi (ang co d lieu truyen i trong
bus) khi SSP ha t ong che o I2C Master mode.
BCLIF = 0 Bus truyen nhan cha b tra n (khong co d lie u truyen i trong
bus).
Bit 0 CCP2IFCCP2 Interrupt Flag bit
che o Capture
CCP2IF = 1 a ca p nhat gia tr trong thanh ghi TMR1.
CCP2IF = 0 cha cap nhat gia tr trong thanh ghi TMR1.
che o Compare
CCP2IF = 1 gia tr can so sanh bang vi gia tr cha trong
TMR1.
CCP2IF = 0 gia tr can so sa nh cha bang vi gia tr cha
trong TMR1.
Thanh ghi PCON (8Eh): cha ca c c hie u cho biet trang tha i ca c che o reset
cua vi ie u khien.

Bit 7, 6, 5, 4, 3, 2 Kho ng ca n quan ta m va mac nh mang gia tr 0.
Bit 1 Power-on Reset Status bit
= 1 khong co s tac ong cua Power-on Reset.
= 0 co s tac ong cua Power-on reset.
Bit 0 Brown-out Reset Status bit
= 1 khong co s tac ong cua Brown-out reset.
= 0 co s tac ong cua Brown-out reset.

2.2 Thanh ghi muc ch GPR
Cac thanh ghi nay co the c truy xua t tr c tie p hoa c gian tiep thong qua thanh
ghi FSG (File Select Register). ay la cac thanh ghi d lie u tho ng thng, ngi s
dung co the tuy theo mu c ch chng trnh ma co the dung cac thanh ghi nay e cha
cac bien so , hang so, ket qua hoac cac tham so phuc vu cho chng trnh.

2.3 STACK
Stack khong na m trong bo nh chng trnh hay bo nh d lieu ma la mo t vung
nh a c biet khong cho phep oc hay ghi. Khi lenh CALL c thc hien hay khi mo t
ngat xay ra lam chng trnh b re nhanh, gia tr cua bo em chng trnh PC t ong
c vi ieu khien ca t vao trong stack. Khi mo t trong cac lenh RETURN, RETLW hat
RETFIE c thc thi, gia tr PC se t ong c la y ra t trong stack, vi ieu khien se
thc hien tiep chng trnh theo ung qui trnh nh trc. Bo nh Stack trong vi ieu
khien PIC ho 16F87xA co kha nang cha c 8 a ch va hoat ong theo c che xoay
vong. Ngha la gia tr cat vao bo nh Stack lan th 9 se ghi e len gia tr ca t vao Stack
lan au tien va gia tr cat vao bo nh Stack lan th 10 se ghi e len gia tr ca t vao Stack
lan th 2.
Can chu y la khong co c hieu nao cho biet trang tha i stack, do o ta khong bie t
c khi nao stack tra n. Ben canh o tap le nh cua vi ieu khien dong PIC cu ng khong
co lenh POP hay PUSH, ca c thao tac vi bo nh stack se hoa n toan c ieu khien bi
CPU.
3. CAC CONG XUAT NHAP CUA PIC16F877A
Cong xuat nha p (I/O port) chnh la phng tien ma vi ie u khien dung e tng
tac vi the gii ben ngoai. S tng ta c na y rat a dang va thong qua qua trnh tng
tac o, chc nang cu a vi ieu khien c the hie n mot cach ro rang.Mot cong xua t
nhap cua vi ie u khie n bao gom nhieu chan (I/O pin), tu y theo cach bo tr va ch c na ng
cua vi ieu khien ma so lng co ng xuat nhap va so lng chan trong moi cong co the
khac nhau. Ben canh o, do vi ieu khie n c tch hp san ben trong ca c ac tnh giao
tiep ngoa i vi nen ben canh ch c nang la cong xua t nha p thong thng, mot so chan
xuat nhap con co them cac chc nang kha c e the hien s ta c ong cua ca c ac tnh
ngoai vi neu tren o i vi the gi i ben ngoai. Chc na ng cua tng chan xua t nhap trong
mo i co ng hoan toan co the c xac la p va ieu khie n c thong qua ca c thanh ghi
SFR lie n quan en chan xuat nhap o.Vi ieu khien PIC16F877A co 5 cong xuat nhap,
bao gom PORTA, PORTB, PORTC,PORTD va PORTE. Cau truc va chc na ng cua
tng cong xua t nha p se c e cap cu the trong phan sau.

3.1 PORTA : a ch 05h.


PORTA (RPA) bao go m 6 I/O pin. ay la ca c chan hai chieu (bidirectional
pin), ngha la co the xuat va nhap c. Chc nang I/O nay c ieu khie n bi thanh
ghi TRISA (a ch 85h). Muon xa c lap chc nang cua mo t chan trong PORTA la input,
ta set bit ie u khie n tng ng vi cha n o trong thanh ghi TRISA va ngc la i,
muo n xa c la p chc na ng cua mot cha n trong PORTA la output, ta clear bit ieu
khien tng ng vi chan o trong thanh ghi TRISA. Thao ta c nay hoan toan tng t
oi vi cac PORT va cac thanh ghi ieu khie n tng ng TRIS (oi vi PORTA la
TRISA, oi vi PORTB la TRISB, oi vi PORTC la TRISC, oi vi PORTD la
TRISD va oi vi PORTE la TRISE). Ben ca nh o PORTA co n la ngo ra cua bo ADC,
bo so sanh, ngo vao analog ngo vao xung clock cua Timer0 va ngo vao cua bo giao
tiep MSSP (Master Synchronous Serial Port). ac tnh nay se c trnh ba y cu the
trong pha n sau.
Cac thanh ghi SFR lie n quan en PORTA bao gom:
PORTA (a ch 05h) : cha gia tr ca c pin trong PORTA
TRISA (a ch 85h) : ieu khien xua t nha p
CMCON (a ch 9Ch) : thanh ghi ie u khie n bo so sanh.
CVRCON (a ch 9Dh) : thanh ghi ie u khie n bo so sanh ien ap
ADCON1 (a ch 9Fh) : thanh ghi ieu khien bo ADC.
Chi tiet ve ca c thanh ghi se c trnh ba y cu the trong phu lu c 2.

3.2 PORTB: a ch 06h, 106h.

PORTB (RPB) gom 8 pin I/O. Thanh ghi ieu khien xuat nha p tng ng la
TRISB. Ben ca nh o mo t so cha n cua PORTB con c s dung trong qua trnh nap
chng trnh cho vi ieu khien vi ca c che o na p kha c nhau. PORTB con lien quan
en nga t ngoa i vi va bo Timer0. PORTB con c tch hp chc na ng ie n tr keo le n
c ieu khien bi chng trnh.
Cac thanh ghi SFR lie n quan en PORTB bao gom:
PORTB (a ch 06h,106h) : cha gia tr ca c pin trong PORTB
TRISB (a ch 86h,186h) : ieu khien xua t nhap
OPTION_REG (a ch 81h,181h):ieu khien ngat ngoa i vi va bo Timer0.

3.3 PORTC: a ch 07h

PORTC (RPC) go m 8 pin I/O. Thanh ghi ieu khien xua t nha p tng ng la
TRISC. Ben ca nh o PORTC co n cha cac chan chc nang cua bo so sanh, bo Timer1,
bo PWM va cac chua n giao tiep noi tiep I2C, SPI, SSP, USART.
Cac thanh ghi ieu khien lien quan en PORTC:
PORTC (a ch 07h) : cha gia tr ca c pin trong PORTC
TRISC (a ch 87h) : ieu khien xua t nha p.

3.4 PORTD : a ch 08h

PORTD (RPD) gom 8 chan I/O, thanh ghi ie u khien xuat nhap tng ng la
TRISD.PORTD con la cong xua t d lieu cua chuan giao tiep PSP (Parallel Slave Port).
Cac thanh ghi lien quan en PORTD bao gom:
PORTD : cha gia tr cac pin trong PORTD.
TRISD : ieu khien xuat nhap.
TRISE : ieu khien xuat nhap PORTE va chuan giao tiep PSP.


3.5 PORTE : a ch 09h

PORTE (RPE) go m 3 chan I/O. Thanh ghi ie u khien xuat nhap tng ng la
TRISE.Ca c chan cua PORTE co ngo vao analog. Ben ca nh o PORTE con la ca c chan
ie u khie ncua chuan giao tie p PSP.
Cac thanh ghi lien quan en PORTE bao go m:
PORTE : cha gia tr ca c chan trong PORTE.
TRISE : ie u khie n xuat nhap va xac lap cac thong so cho chua n giao
tiep PSP.
ADCON1 : thanh ghi ie u khie n khoi ADC.

4. TIMER 0
ay la mo t trong ba bo em hoac bo nh thi cua vi ie u khien PIC16F877A.
Timer0 la bo em 8 bit c ket no i vi bo chia ta n so (prescaler) 8 bit. Cau truc cua
Timer0 cho phep ta la chon xung clock tac ong va canh tch c c cua xung clock.
Ngat Timer0 se xua t hie n khi Timer0 b tran. Bit TMR0IE (INTCON<5>) la bit ie u
khien cua Timer0. TMR0IE=1 cho phep ngat Timer0 tac ong, TMR0IF= 0 khong cho
phep nga t Timer0 ta c ong. S o khoi cua Timer0 nh sau:

Hnh 2.5 S o khoi cua Timer0.
Muon Timer0 hoa t o ng che o Timer ta clear bit TOSC (OPTION_REG<5>),
khi o gia tr thanh ghi TMR0 se tang theo tng chu k xung ong ho (ta n so vao
Timer0 bang ta n so oscillator). Khi gia tr thanh ghi TMR0 t FFh tr ve 00h, ngat
Timer0 se xua t hien. Thanh ghi TMR0 cho phep ghi va xoa c giu p ta an nh thi
ie m ngat Timer0 xua t hien mo t cach linh ong.
Muon Timer0 hoat o ng che o counter ta set bit TOSC (OPTION_REG<5>).
Khi o xung tac ong len bo em c lay t chan RA4/TOCK1. Bit TOSE
(OPTION_REG<4>) cho phep la chon canh tac ong vao bot e m. Canh tac ong se
la canh len neu TOSE=0 va canh tac ong se la canh xuong neu TOSE=1.
Khi thanh ghi TMR0 b tran, bit TMR0IF (INTCON<2>) se c set. a y chnh
la c ngat cua Timer0. C ngat nay phai c xoa ba ng chng trnh trc khi bo e m
bat au thc hien la i qua trnh em. Ngat Timer0 khong the anh thc vi ieu khien
t che o sleep.
Bo chia tan so (prescaler) c chia se gia Timer0 va WDT (Watchdog
Timer). ieu o co ngha la neu prescaler c s dung cho Timer0 th WDT se khong
co c ho tr cua prescaler va ngc lai. Prescaler c ieu khie n bi thanh ghi
OPTION_REG. Bit PSA (OPTION_REG<3>) xa c nh oi tng tac ong cua
prescaler. Cac bit PS2:PS0 (OPTION_REG<2:0>) xa c nh t so chia ta n so cua
prescaler. Xem la i thanh ghi OPTION_REG e xa c nh la i mo t ca ch chi tie t ve cac bit
ie u khien tren. Ca c lenh ta c ong len gia tr thanh ghi TMR0 se xoa che o hoat ong
cua prescaler. Khi oi tng tac ong la Timer0, tac ong len gia tr thanh ghi TMR0
se xoa prescaler nhng khong lam thay oi oi tng ta c ong cu a prescaler. Khi oi
tng tac ong la WDT, lenh CLRWDT se xoa prescaler, ong thi prescaler se ngng
tac vu ho tr cho WDT.
Cac thanh ghi ieu khien lien quan en Timer0 bao gom:
TMR0 (a ch 01h, 101h) : cha gia tr em cua Timer0.
INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho phep nga t hoat ong
(GIE va PEIE).
OPTION_REG (a ch 81h, 181h): ieu khie n prescaler.

5. TIMER1
Timer1 la bo nh th i 16 bit, gia tr cua Timer1 se c lu trong hai thanh ghi
(TMR1H:TMR1L). C nga t cua Timer1 la bit TMR1IF (PIR1<0>). Bit ieu khien cua
Timer1 se la TMR1IE (PIE<0>). Tng t nh Timer0, Timer1 cung co hai che o
hoat ong: che o nh thi (timer) vi xung kch la xung clock cua oscillator (tan so
cua timer bang tan so cua oscillator) va che o em (counter) vi xung kch la xung
phan anh ca c s kien ca n e m lay t ben ngoai thong qua cha n RC0/T1OSO/T1CKI
(canh tac ong la canh len). Vie c la chon xung ta c ong (tng ng vi vie c la chon
che o hoat ong la timer hay counter) c ieu khie n bi bit TMR1CS
(T1CON<1>). Sau a y la s o khoi cua Timer1:

Hnh 2.6 S o khoi cua Timer1.
Ngoa i ra Timer1 con co chc na ng reset input ben trong c ie u khien b i mo t
trong hai khoi CCP (Capture/Compare/PWM). Khi bit T1OSCEN (T1CON<3>) c
set, Timer1 se lay xung clock t hai chan RC1/T1OSI/CCP2 va RC0/T1OSO/T1CKI
lam xung em. Timer1 se bat au em sau canh xuong a u tien cua xung ngo va o. Khi
o PORTC se bo qua s tac ong cua hai bit TRISC<1:0> va PORTC<2:1> c gan
gia tr 0. Khi clear bit T1OSCEN Timer1 se lay xung em t oscillator hoac t chan
RC0/T1OSO/T1CKI. Timer1 co hai che o em la ong bo (Synchronous) va ba t ong
bo (Asynchronous). Che o em c quyet nh bi bit ie u khien
(T1CON:<2>)
Khi =1 xung em lay t ben ngoai se khong c ong bo hoa vi xung
clock ben trong, Timer1 se tiep tuc qua trnh e m khi vi ie u khien ang che o
sleep va nga t do Timer1 ta o ra khi b tran co kha nang anh thc vi ieu khien.
che o em bat ong bo, Timer1 khong the c s dung e la m nguon xung clock cho
khoi CCP(Capture/Compare/Pulse width modulation). Khi =0 xung em vao
Timer1 se c ong bo hoa vi xung clock ben trong. che o nay Timer1 se khong
hoat ong khi vi ieu khien ang che o sleep.
Cac thanh ghi lien quan en Timer1 bao gom:
INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho phep nga t hoat ong
(GIE va PEIE).
PIR1 (a ch 0Ch): cha c nga t Timer1 (TMR1IF).
PIE1( a ch 8Ch): cho phep nga t Timer1 (TMR1IE).
TMR1L (a ch 0Eh): cha gia tr 8 bit thap cua bo em Timer1.
TMR1H (a ch 0Eh): cha gia tr 8 bit cao cua bo em Timer1.
T1CON (a ch 10h): xac lap cac thong so cho Timer1.

6. TIMER2
Timer2 la bo nh thi 8 bit va c ho tr bi hai bo chia ta n so prescaler va
postscaler. Thanh ghi cha gia tr em cua Timer2 la TMR2. Bit cho phep ngat Timer2
tac ong la TMR2ON (T2CON<2>). C ngat cua Timer2 la bit TMR2IF (PIR1<1>).
Xung ngo vao (tan so bang tan so oscillator) c a qua bo chia tan so prescaler 4
bit (vi cac t so chia tan so la 1:1, 1:4 hoac 1:16 va c ieu khien bi ca c bit
T2CKPS1:T2CKPS0 (T2CON<1:0>)).

Hnh 2.7 S o khoi Timer2.

Timer2 con c ho tr bi thanh ghi PR2. Gia tr em trong thanh ghi TMR2
se ta ng t 00h en gia tr cha trong thanh ghi PR2, sau o c reset ve 00h. Kh I
reset thanh ghi PR2 c nhan gia tr ma c nh FFh. Ngo ra cua Timer2 c a qua
bo chia tan so postscaler v i cac mc chia t 1:1 en 1:16. Postscaler c ieu khien
bi 4 bit T2OUTPS3:T2OUTPS0. Ngo ra cu a postscaler ong vai tro quyet nh trong
vie c ie u khie n c nga t. Ngoa i ra ngo ra cua Timer2 con c ket noi v i khoi SSP, do
o Timer2 con ong vai tro tao ra xung clock ong bo cho khoi giao tiep SSP.
Cac thanh ghi lien quan en Timer2 bao gom:
INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho phep toan bo ca c
ngat (GIE va PEIE).
PIR1 (a ch 0Ch): cha c nga t Timer2 (TMR2IF).
PIE1 (a ch 8Ch): cha bit ie u khie n Timer2 (TMR2IE).
TMR2 (a ch 11h): cha gia tr em cua Timer2.
T2CON (a ch 12h): xac lap cac thong so cho Timer2.
PR2 (a ch 92h): thanh ghi ho tr cho Timer2.
Chi tiet ve ca c thanh ghi se c trnh bay cu the trong phu lu c 2.
Ta co mot vai nhan xet ve Timer0, Timer1 va Timer2 nh sau:
Timer0 va Timer2 la bo em 8 bit (gia tr em toi a la FFh), trong khi Timer1
la bo em 16 bit (gia tr em to i a la FFFFh). Timer0, Timer1 va Timer2 eu co hai
che o hoa t ong la timer va counter. Xung clock co tan so bang tan so cua
oscillator. Xung ta c o ng le n Timer0 c ho tr bi prescaler va co the c thie t lap
nhieu che o kha c nhau (tan so ta c ong, canh ta c ong) trong khi ca c thong so cua
xung tac ong len Timer1 la co nh. Timer2 c ho tr bi hai bo chia ta n so
prescaler va postcaler oc lap, tuy nhie n ca nh ta c ong van c co nh la canh len.
Timer1 co quan he vi khoi CCP, trong khi Timer2 c ket noi vi khoi SSP. Mot va i
so sanh se giup ta de dang la chon c Timer thch hp cho ng dung.

7. ADC
ADC (Analog to Digital Converter) la bo chuyen oi tn hieu gia hai da ng
tng t va so. PIC16F877A co 8 ngo va o analog (RA4:RA0 va RE2:RE0). Hieu ien
the chuan VREF co the c la chon la VDD, VSS hay hieu ien the chuan c xac la p
tren hai chan RA2 va RA3. Ke t qua chuyen oi t tn tieu tng t sang tn hie u so la
10 bit so tng ng va c lu trong hai thanh ghi ADRESH:ADRESL. Khi khong s
dung bo chuyen oi ADC, cac thanh ghi nay co the c s du ng nh cac thanh ghi
thong thng khac. Khi qua trnh chuyen oi hoan tat, ket qua se c lu vao hai
thanh ghi ADRESH:ADRESL, bit (ADCON0<2>) c xoa ve 0 va c nga t
ADIF c set.
Qui trnh chuyen oi t tng t sang so bao gom ca c bc sau:
1. Thie t la p ca c thong so cho bo chuyen o i ADC:
Chon ngo vao analog, chon ien ap mau (da tre n ca c thong so cu a thanh
ghi ADCON1)
Chon kenh chuyen o i AD (thanh ghi ADCON0).
Chon xung clock cho kenh chuyen oi AD (thanh ghi ADCON0).
Cho phep bo chuyen oi AD hoat ong (thanh ghi ADCON0).
2. Thiet lap ca c c ngat cho bo AD
Clear bit ADIF.
Set bit ADIE.
Set bit PEIE.
Set bit GIE
3. i cho ti khi qua trnh lay mau hoan tat.
4. Ba t au qua trnh chuyen oi (set bit ).
5. i cho t i khi qua trnh chuyen o i hoa n tat bang ca ch:
Kie m tra bit . Neu =0, qua trnh chuyen oi a hoan tat.
Kie m tra c nga t.
6. o c ket qua chuye n oi va xoa c ngat, set bit (neu can tiep tuc
chuyen o i).
7. Tie p tuc thc hien cac bc 1 va 2 cho qua trnh chuyen oi tie p theo.

Hnh 2.8 S o khoi bo chuye n oi ADC
Can chu y la co hai ca ch lu ket qua chuyen oi AD, viec la chon cach lu
c ieu khien bi bit ADFM va c minh hoa cu the trong hnh sau:

Hnh 2.9 Cac cach lu ket qua chuyen oi AD
Cac thanh ghi lien quan en bo chuyen oi ADC bao go m:
INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho phep ca c nga t (ca c bit
GIE, PEIE).
PIR1 (a ch 0Ch): cha c nga t AD (bit ADIF).
PIE1 (a ch 8Ch): cha bit ie u khie n AD (ADIE).
ADRESH (a ch 1Eh) va ADRESL (a ch 9Eh): cac thanh ghi cha
ket qua chuyen oi AD.
ADCON0 (a ch 1Fh) va ADCON1 (a ch 9Fh): xac la p cac thong
so cho bo chuyen oi AD.
PORTA (a ch 05h) va TRISA (a ch 85h): lie n quan en cac ngo
vao analog PORTA.
PORTE (a ch 09h) va TRISE (a ch 89h): lien quan en ca c ngo
vao analog PORTE.
Chi tiet ve ca c thanh ghi se c trnh bay cu the phu luc 2.

8. COMPARATOR
Bo so sanh bao go m hai bo so so sa nh tn hie u analog va c at PORTA.
Ngo vao bo so sanh la cac chan RA3:RA0, ngo ra la hai cha n RA4 va RA5. Thanh ghi
ie u khien bo so sanh la CMCON. Ca c bit CM2:CM0 trong thanh ghi CMCON ong
vai tro chon la ca c che o hoa t ong cho bo Comparator (hnh 2.10). C che hoat
ong cua bo Comparator nh sau:
Tn hieu analog cha n VIN + se c so sa nh vi ie n ap chuan chan VIN- va
tn hieu ngo ra bo so sanh se thay oi tng ng nh hnh ve. Khi ien ap chan
VIN+ ln hn ien ap chan VIN+ ngo ra se m c 1 va ng c la i.
Da vao hnh ve ta thay ap ng ta i ngo ra khong pha i la t c thi so v i thay
oi ta i ngo vao ma ca n co mo t khoang thi gian nha t nh e ngo ra thay oi tra ng tha i
(to i a la 10 us). Ca n chu y en khoang thi gian ap ng nay khi s dung bo so sa nh.
Cc tnh cua ca c bo so sanh co the thay o i da va o cac gia tr a t vao ca c bit C2INV
va C1INV (CMCON<4:5>).

Hnh 2.10 Nguyen l hoat o ng cua mot bo so sanh n gian.

Hnh 2.11 Cac che o hoat ong cua bo comparator.
Cac bit C2OUT va C1OUT (CMCON<7:6>) ong vai tro ghi nha n s thay oi
tn hie u analog so vi ien ap a t tr c. Cac bit nay can c x l thch hp bang
chng trnh e ghi nhan s thay oi cua tn hie u ngo va o. C ngat cua bo so sanh la bit
CMIF (thanh ghi PIR1). C nga t na y phai c reset ve 0. Bit ieu khien bo so sanh la
bit CMIE (Tranh ghi PIE).
Cac thanh ghi lien quan en bo so sanh bao gom:
CMCON (a ch 9Ch) va CVRCON (a ch 9Dh): xac lap ca c thong so
cho bo so sa nh.
Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cha cac bit cho
phep ca c nga t (GIE va PEIE).
Thanh ghi PIR2 (a ch 0Dh): cha c nga t cua bo so sa nh (CMIF).
Thanh ghi PIE2 (a ch 8Dh): cha bit cho phep bo so sa nh (CNIE).
Thanh ghi PORTA (a ch 05h) va TRISA (a ch 85h): cac thanh ghi
ie u khie n PORTA.

9. BO TAO IEN AP SO SANH
Bo so sa nh na y ch hoat ong khi bo Comparator c nh dang hoa t ong
che o110. Khi o cac pin RA0/AN0 va RA1/AN1 (khi CIS = 0) hoac pin RA3/AN3
va RA2/AN2 (khi CIS = 1) se la ngo vao analog cua ien ap can so sanh a vao ngo
VIN- cua 2 bo so sanh C1 va C2 (xem chi tiet hnh 2.10). Trong khi o ien ap a
vao ngo VIN+ se c lay t mo t bo ta o ien ap so sanh. S o khoi cua bo tao ien ap
so sanh c trnh bay trong hnh ve sau:

Hnh 2.12 S o khoi bo tao ien ap so sanh.
Bo tao ie n ap so sanh nay bao gom mo t thang ien tr 16 m c ong vai tro la
cau pha n ap chia nho ie n ap VDD thanh nhie u mc khac nhau (16 m c). Moi m c co
gia tr ien a p khac nhau tuy thuoc vao bit ieu khien CVRR (CVRCON<5>). Neu
CVRR m c logic 1, ien tr 8R se khong co tac dung nh mo t thanh phan cua cau
phan a p (BJT dan ma nh va dong ien khong i qua ien tr 8R), khi o 1 m c ie n ap
co gia tr VDD/24. Ngc lai khi CVRR m c logic 0, dong ie n se qua ien tr 8R
va1 m c ie n ap co gia tr VDD/32. Cac m c ien ap nay c a qua bo MUX cho
phep ta chon c ie n ap a ra pin RA2/AN2/VREF-/CVREF e a vao ngo VIN+
cua bo so sa nh ba ng cach a ca c gia tr thch hp vao cac bit CVR3:CVR0.
Bo tao ie n ap so sa nh nay co the xem nh mo t bo chuyen oi D/A n gia n.
Gia tr ien ap ca n so sanh ngo vao Analog se c so sanh vi cac mc ien ap do
bo ta o ien ap tao ra cho t i khi hai ien ap nay at c gia tr xa p x bang nhau. Khi
o ket qua chuyen oi xem nh c cha trong ca c bit CVR3:CVR0.
Cac thanh ghi lien quan en bo tao ien a p so sanh na y bao go m:
Thanh ghi CVRCON (a ch 9Dh): thanh ghi trc tiep ieu khie n bo so
sanh ien ap.
Thanh ghi CMCON (a ch 9Ch): thanh ghi ie u khie n bo Comparator.
Chi tiet ve ca c thanh ghi se c trnh ba y cu the phu lu c 2.

10. CCP
CCP (Capture/Compare/PWM) bao gom ca c thao tac tren cac xung em cung
cap bi ca c bo em Timer1 va Timer2. PIC16F877A c tch hp san hai khoi CCP :
CCP1 va CCP2.Mo i CCP co mo t thanh ghi 16 bit (CCPR1H : CCPR1L va CCPR2H :
CCPR2L), pin ieu khie n dung cho khoi CCPx la RC2/CCP1 va RC1/T1OSI/CCP2.
Cac chc na ng cua CCP bao gom:
Capture.
So sanh (Compare).
ieu che o ro ng xung PWM (Pulse Width Modulation).
Ca CCP1 va CCP2 ve nguyen tac hoa t ong eu giong nhau va chc na ng cua
tng khoi la kha oc lap. Tuy nhien trong mo t so trng hp ngoai le CCP1 va CCP2
co kha nang phoi hp vi nhau e e tao ra cac hien tng a c bie t (Special event
trigger) hoa c ca c tac ong le n Timer1 va Timer2. Ca c trng hp nay c liet ke
trong bang sau:

CCPx CCPy Tac ong
Capture Capture Dung chung nguon xung clock t TMR1
Capture Compare Tao ra hien tng a c bie t lam xoa TMR1
Compare Compare Tao ra hien tng a c bie t lam xoa TMR1
PWM PWm Dung chung tan so xung clock va cung chu tac ong cua
ngat TMR2
PWM Capture Hoat ong oc la p
PWM compare Hoat ong oc la p

Khi hoa t ong che o Capture th khi co mot hien tng xay ra tai pin RC2/CCP1
(hoac RC1/T1OSI/CCP2), gia tr cua thanh ghi TMR1 se c a vao thanh ghi
CCPR1 (CCPR2). Ca c hien tng c nh ngha bi ca c bit CCPxM3:CCPxM0
(CCPxCON<3:0>) va co the la mot trong ca c hien tng sau:
Moi khi co canh xuong ta i ca c pin CCP.
Moi khi co canh len.
Moi canh len th 4.
Moi canh len th 16.

Hnh 2.13 S o khoi CCP (Capture mode).
Sau khi gia tr cua thanh ghi TMR1 c a vao thanh ghi CCPRx, c ngat
CCPIF c set va phai c xoa bang chng trnh. Ne u hien tng tie p theo xa y ra
ma gia tr trong thanh ghi CCPRx cha c x l, gia tr tie p theo nha n c se t
ong c ghi e len gia tr cu.
Mot so ie m ca n chu y khi s dung CCP nh sau:
Cac pin dung cho khoi CCP pha i c an nh la input (set ca c bit tng ng
trong thanh ghi TRISC). Khi an nh ca c pin dung cho khoi CCP la output, viec a gia
tr vao PORTC cung co the gay ra cac hien tng ta c ong le n khoi CCP do trang
tha i cua pin thay oi.
Timer1 pha i c hoa t ong che o Timer hoac che o em ong bo.
Tranh s dung nga t CCP bang cach clear bit CCPxIE (thanh ghi PIE1), c nga t
CCPIF nen c xoa bang phan me m moi khi c set e tiep tu c nha n nh c
trang thai hoat ong cua CCP.
CCP co n c tch h p bo chia ta n so prescaler c ieu khie n bi ca c bit
CCPxM3:CCPxM0. Vie c thay oi o i tng tac ong cua prescaler co the tao ra hoa t
ong nga t. Prescaler c xoa khi CCP khong hoa t ong hoac khi reset.
Xem cac thanh ghi ie u khien khoi CCP (phu luc 2 e biet the m chi tiet).
Khi hoa t ong che o Compare, gia tr trong thanh ghi CCPRx se thng
xuyen c so sanh vi gia tr trong thanh ghi TMR1. Khi hai thanh ghi cha gia tr
bang nhau, ca c pin cu a CCP c thay oi trang tha i (c a len m c cao, a xuong
m c tha p hoac gi nguyen trang tha i), ong thi c ngat CCPIF cung se c set. S
thay oi trang thai cua pin co the c ieu khien bi ca c bit CCPxM3:CCPxM0
(CCPxCON <3:0>).


Hnh 2.14 S o khoi CCP (Compare mode).

Tng t nh che o Capture, Timer1 phai c an nh che o hoat ong la
timer hoac em ong bo. Ngoai ra, khi che o Compare, CCP co kha na ng tao ra
hie n tng ac biet (Special Event trigger) lam reset gia tr thanh ghi TMR1 va khi
ong bo chuyen oi ADC. ieu na y cho phe p ta ie u khie n gia tr thanh ghi TMR1 mo t
cach linh ong hn.
Khi hoa t ong che o PWM (Pulse Width Modulation _ khoi ie u che o ro ng
xung), tn hie u sau khi ie u che se c a ra cac pin cua khoi CCP (can a n nh cac
pin nay la output). e s dung chc na ng ieu che nay trc tien ta can tien
hanh cac bc cai at sau:
1. Thiet lap thi gian cua 1 chu k cua xung ie u che cho PWM (period) ba ng
cach a gia tr thch hp va o thanh ghi PR2.
2. Thiet lap o rong xung can ieu che (duty cycle) bang cach a gia tr vao
thanh ghi CCPRxL va ca c bit CCP1CON<5:4>.
3. ieu khien cac pin cua CCP la output bang ca ch clear ca c bit tng ng trong
thanh ghi TRISC.
4. Thiet lap gia tr bo chia tan so prescaler cua Timer2 va cho phe p Timer2
hoat ong bang ca ch a gia tr thch hp va o thanh ghi T2CON.
5. Cho phe p CCP hoa t o ng che o PWM.

Hnh 2.15 S o khoi CCP (PWM mode).

Hnh 2.16 Cac tham so cua PWM
Trong o gia tr 1 chu k (period) cua xung ieu che c tnh bang cong th c:

PWM period = [(PR2)+1]*4*T
OSC
*(gia tr bo chia ta n so cua TMR2).

Bo chia ta n so prescaler cua Timer2 ch co the nha n cac gia tr 1,4 hoa c
16 (xem lai Timer2 e biet them chi tie t). Khi gia tr thanh ghi PR2 bang
vi gia tr thanh ghi TMR2 th qua trnh sau xay ra:
Thanh ghi TMR2 t ong c xoa.
Pin cua khoi CCP c set.
Gia tr thanh ghi CCPR1L (cha gia tr a n nh o rong xung ieu che
duty cycle) c a vao thanh ghi CCPRxH.
o rong cua xung ie u che (duty cycle) c tnh theo cong thc:

PWM duty cycle = (CCPRxL:CCPxCON<5:4>)*TOSC*(gia tr bo chia tan so TMR2)

Nh vay 2 bit CCPxCON<5:4> se cha 2 bit LSB. Thanh ghi CCPRxL cha byte
cao cua gia tr quyet nh o rong xung. Thanh ghi CCPRxH ong vai tro la buffer cho
khoi PWM. Khi gia tr trong thanh ghi CCPRxH bang v i gia tr trong thanh ghi
TMR2 va hai bit CCPxCON<5:4> bang vi gia tr 2 bit cua bo chia ta n so prescaler,
pin cua khoi CCP lai c a ve m c tha p, nh vay ta co c hnh anh cua xung ie u
che ta i ngo ra cua khoi PWM nh hnh 2.14.
Mot so ie m ca n chu y khi s dung khoi PWM:
Timer2 co hai bo chia tan so prescaler va postscaler. Tuy nhien bo
postscaler khong c s dung trong qua trnh ieu che o rong xung cua
khoi PWM.
Neu thi gian duty cycle dai hn th i gian chu k xung period th xung
ngo ra tiep tuc c gi m c cao sau khi gia tr PR2 bang vi gia tr
TMR2.

11. GIAO TIEP NOI TIEP
11.1 USART
USART (Universal Synchronous Asynchronous Receiver Transmitter) la mo t
trong hai chuan giao tiep noi tiep.USART con c goi la giao dien giao tiep noi tiep
noi tiep SCI (Serial Communication Interface). Co the s dung giao dien nay cho cac
giao tiep vi cac thie t b ngoai vi, vi cac vi ie u khien khac hay vi may tnh. Ca c
dang cua giao die n USART ngoai vi bao go m:
Bat ong bo (Asynchronous).
ong bo_ Master mode.
ong bo_ Slave mode.
Hai pin dung cho giao dien na y la RC6/TX/CK va RC7/RX/DT, trong o
RC6/TX/CK dung e truyen xung clock (baud rate) va RC7/RX/DT dung e truyen
data. Trong trng h p nay ta phai set bit TRISC<7:6> va SPEN (RCSTA<7>) e cho
phep giao dien USART.
PIC16F877A c tch hp sa n bo tao to c o baud BRG (Baud Rate Genetator)
8 bit dung cho giao dien USART. BRG thc cha t la mot bo e m co the c s dung
cho ca hai dang ong bo va ba t ong bo va c ie u khie n bi thanh ghi PSBRG.
dang bat ong bo, BRG co n c ieu khien bi bit BRGH ( TXSTA<2>). da ng
ong bo tac ong cua bit BRGH c bo qua. To c o baud do BRG ta o ra c tnh
theo co ng thc sau:

Trong o X la gia tr cua thanh ghi RSBRG ( X la so nguyen va 0<X<255).
Cac thanh ghi lien quan en BRG bao gom:
o TXSTA (a ch 98h): chon che o ong bo hay bat ong bo ( bit SYNC)
va chon m c to c o baud (bit BRGH).
o RCSTA (a ch 18h): cho phep hoa t ong co ng noi tiep (bit SPEN).
o RSBRG (a ch 99h): quyet nh to c o baud.
o Chi tiet ve ca c thanh ghi se c trnh ba t cu the trong phu lu c 2.

11.1.1 USART BAT ONG BO
che o truyen na y USART hoa t ong theo chua n NRZ (None-Return-to-
Zero), ngha la ca c bit truyen i se bao gom 1 bit Start, 8 hay 9 bit d lie u (thong
thng la 8 bit) va 1 bit Stop. Bit LSB se c truyen i trc. Cac khoi truyen va nha n
data oc lap vi nhau se dung chung tan so tng ng vi to c o baud cho qua trnh
dch d lieu (toc o baud gap 16 hay 64 lan to c o dch d lieu tu y theo gia tr cua bit
BRGH), va e a m ba o tnh hieu qua cua d lieu th hai khoi truye n va nhan pha i dung
chung mot nh dang d lie u.

11.1.1.1 TRUYEN D LIEU QUA CHUAN GIAO TIEP USART BAT
ONG BO
Thanh pha n quan tro ng nha t cua kho i truyen d lie u la thanh ghi dch d lieu
TSR (Transmit Shift Register). Thanh ghi TSR se lay d lieu t thanh ghi em dung
cho qua trnh truyen d lieu TXREG. D lie u can truyen pha i c a trc vao thanh
ghi TXREG. Ngay sau khi bit Stop cua d lieu can truyen trc o c truyen xong,
d lie u t thanh ghi TXREG se c a vao thanh ghi TSR, thanh ghi TXREG b
rong, ngat xay ra va c hie u TXIF (PIR1<4>) c set. Nga t nay c ie u khien bi
bit TXIE (PIE1<4>). C hieu TXIF van c set bat chap trang thai cua bit TXIE hay
tac ong cua chng trnh (khong the xoa TXIF bang chng trnh) ma ch reset ve 0
khi co d lieu m i c a vao thanhh ghi TXREG.

Hnh 2.17 S o khoi cua khoi truyen d lieu USART

Trong khi c hieu TXIF ong vai tro ch th trang tha i thanh ghi TXREG th c
hie u TRMT (TXSTA<1>) co nhie m vu the hien tra ng tha i thanh ghi TSR. Khi thanh
ghi TSR rong, bit TRMT se c set. Bit nay ch oc va khong co ngat na o c gan
vi tra ng thai cua no. Mot ie m can chu y na la thanh ghi TSR khong co trong bo nh
d lieu va ch c ie u khien bi CPU.
Khoi truyen d lieu c cho phep hoat ong khi bit TXEN (TXSTA<5>) c
set. Qua trnh truyen d lieu ch thc s bat a u khi a co d lieu trong thanh ghi
TXREG va xung truyen baud c tao ra. Khi khoi truyen d lie u c khi ong la n
au tien, thanh ghi TSR rong. Tai thi ie m o, d lieu a va o thanh ghi TXREG
ngay lap tc c load vao thanh ghi TSR va thanh ghi TXREG b ro ng. Luc nay ta co
the hnh thanh mo t chuoi d lieu lien tuc cho qua trnh truyen d lieu. Trong qua trnh
truyen d lieu neu bit TXEN b reset ve 0, qua trnh truyen ket thuc, khoi truyen d
lieu c reset va pin RC6/TX/CK chuyen en trang tha i high-impedance.
Trong trng hp d lieu can truyen la 9 bit, bit TX9 (TXSTA<6>) c set va
bit d lieu th 9 se c lu trong bit TX9D (TXSTA<0>). Ne n ghi bit d lie u th 9
vao tr c, v khi ghi 8 bit d lie u vao thanh ghi TXREG trc co the xay ra trng hp
noi dung thanh ghi TXREG se c load vao thanh ghi TSG trc, nh vay d lieu
truyen i se b sai kha c so vi yeu cau.
To m la i, e truyen d lie u theo giao dien USART bat ong bo, ta can thc hie n
tuan t ca c bc sau
1. Tao xung truyen baud bang cach a cac gia tr can thiet vao thanh ghi
RSBRG va bit ieu khien mc to c o baud BRGH.
2. Cho phep cong giao dien noi tiep noi tiep ba t ong bo ba ng cach clear bit
SYNC va set bit PSEN.
3. Set bit TXIE neu can s dung nga t truye n.
4. Set bit TX9 neu nh dang d lieu can truyen la 9 bit.
5. Set bit TXEN e cho phep truyen d lieu (lu c na y bit TXIF cung se c set).
6. Neu nh dang d lieu la 9 bit, a bit d lieu th 9 vao bit TX9D.
7. a 8 bit d lieu ca n truyen vao thanh ghi TXREG.
8. Neu s dung nga t truyen, ca n kie m tra lai ca c bit GIE va PEIE (thanh ghi
INTCON).
Cac thanh ghi lien quan en qua trnh truyen d lieu ba ng giao die n USART ba t
ong bo:
Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho phep ta t ca cac
ngat.
Thanh ghi PIR1 (a ch 0Ch): cha c hie u TXIF.
Thanh ghi PIE1 (a ch 8Ch): cha bit cho phep ngat truyen TXIE.
Thanh ghi RCSTA (a ch 18h): cha bit cho phep cong truyen d lieu
(hai pin RC6/TX/CK va RC7/RX/DT).
Thanh ghi TXREG (a ch 19h): thanh ghi cha d lieu ca n truyen.
Thanh ghi TXSTA (a ch 98h): xa c lap cac thong so cho giao die n.
Thanh ghi SPBRG (a ch 99h): quyet nh to c o baud.

11.1.1.2 NHAN D LIEU QUA CHUAN GIAO TIEP USART BAT ONG
BO
D lieu c a vao t chan RC7/RX/DT se kch hoa t khoi phuc hoi d lieu.
Khoi phuc hoi d lieu thc chat la mot bo dch d lie u cto c o cao va co tan so hoat
ong gap 16 lan hoac 64 la n tan so baud. Trong khi o to c o dch cua thanh thanh ghi
nhan d lieu se bang vi tan so baud hoa c ta n so cua oscillator.

Hnh 2.18 S o khoi cua khoi nhan d lie u USART
Bit ieu khien cho phep kho i nha n d lieu la bit RCEN (RCSTA<4>). Thanh
phan quan trong nha t cua khoi nhan d lieu la thsnh ghi nha n d lieu RSR (Receive
Shift Register). Sau khi nhan dien bit Stop cua d lieu truyen t i, d lie u nhan c
trong thanh ghi RSR se c a vao thanh ghi RCGER, sau o c hie u RCIF
(PIR1<5>) se c set va nga t nhan c kch hoat. Nga t na y c ieu khie n bi bit
RCIE (PIE1<5>). Bit c hieu RCIF la bit ch oc va khong the c tac ong bi
chng trnh. RCIF ch reset ve 0 khi d lie u nhan vao thanh ghi RCREG a c
oc va khi o thanh ghi RCREG rong. Thanh ghi RCREG la thanh ghi co bo em kep
(double-buffered register) va hoa t ong theo c che FIFO (First In First Out) cho phep
nhan 2 byte va byte th 3 tiep tu c c a vao thanh ghi RSR. Neu sau khi nhan c
bit Stop cua byte d lieu th 3 ma thanh ghi RCREG van con ay, c hieu bao tra n d
lieu (Overrun Error bit) OERR(RCSTA<1>) se c set, d lieu trong thanh ghi RSR
se b ma t i va qua trnh a d lie u t thanh ghi RSR vao thanh ghi RCREG se b gia n
oan.
Trong trng hp nay can lay het d lie u thanh ghi RSREG vao trc khi tiep
tu c nhan byte d lieu tiep theo. Bit OERR phai c xoa ba ng pha n me m va thc hie n
bang cach clear bit RCEN roi set la i. Bit FERR (RCSTA<2>) se c set khi phat hien
bit Stop dua d lieu c nhan vao. Bit d lieu th 9 se c a vao bit RX9D
(RCSTA<0>). Khi o c d lie u t thanh ghi RCREG, hai bit FERR va RX9D se nhan
cac gia tr mi. Do o can oc d lieu t thanh ghi RCSTA trc khi oc d lieu t
thanh ghi RCREG e tranh b mat d lieu.
To m lai, khi s dung giao die n nha n d lieu USART ba t ong bo can tien ha nh
tuan t ca c bc sau:
1. Thiet la p toc o baud (a gia tr thch hp vao thanh ghi SPBRG va bit
BRGH.
2. Cho phep cong giao tiep USART ba t ong bo (clear bit SYNC va set bit
SPEN).
3. Neu can s dung ngat nhan d lieu, set bit RCIE.
4. Neu d lieu truyen nhan co nh dang la 9 bit, set bit RX9.
5. Cho phe p nha n d lieu bang ca ch set bit CREN.
6. Sau khi d lie u c nhan, bit RCIF se c set va nga t c kch hoat (neu
bit RCIE c set).
7. oc gia tr thanh ghi RCSTA e oc bit d lieu th 9 va kie m tra xem qua
trnh nhan d lieu co b lo i khong.
8. o c 8 bit d lieu t thanh ghi RCREG.
9. Neu qua trnh truye n nhan co loi xay ra, xoa loi bang ca ch xoa bit CREN.
10. Neu s dung ngat nhan can set bit GIE va PEIE (thanh ghi INTCON).
Cac thanh ghi lien quan en qua trnh nhan d lie u bang giao die n USART ba t
ong bo:
phep toa n bo ca c ngat (bit GIER va PEIE).
Thanh ghi PIR1 (a ch 0Ch): cha c hie u RCIE.
Thanh ghi PIE1 (a ch 8Ch): cha bit cho phep ngat RCIE.
Thanh ghi RCSTA (a ch 18h): xa c nh cac trang thai trong qua trnh
nhan d lieu.
Thanh ghi RCREG (a ch 1Ah): cha d lie u nhan c.
Thanh ghi TXSTA (a ch 98h): cha cac bit ieu khien SYNC va
BRGH.
Thanh ghi SPBRG (a ch 99h): ie u khie n to c o baud.

11.1.2 USART ONG BO
Giao dien USART o ng bo c kch hoa t bang ca ch set bit SYNC. Cong giao
tiep noi tiep van la hai chan RC7/RX/DT, RC6/TX/CK va c cho phep bang cach set
bit SPEN. USART cho phep hai che o truyen nhan d lie u la Master mode va Slave
mode. Master mode c kch hoat bang ca ch set bit CSRC (TXSTA<7>), Slave mode
c kch hoat ba ng cach clear bit CSRC. ie m kha c biet duy nha t gia hai che o nay
la Master mode se la y xung clock ong bo t bo tao xung baud BRG co n Slave mode
lay xung clock ong bo t ben ngoa i qua chan RC6/TX/CK. ieu nay cho phep Slave
mode hoa t ong ngay ca khi vi ieu khien ang che o sleep.

11.1.2.1 TRUYEN D LIEU QUA CHUAN GIAO TIEP USART ONG BO
MASTER MODE
Tng t nh giao dien USART ba t ong bo, thanh pha n quan trong nha t cua
hoi truyen d lieu la thanh ghi dch TSR (Transmit Shift Register). Thanh ghi nay ch
c ieu khie n bi CPU. D lieu a va o thanh ghi TSR c cha trong thanh ghi
TXREG. C hieu cua khoi truyen d lieu la bit TXIF (ch th trang tha i thanh ghi
TXREG), c hieu nay c gan vi mot ngat va bit ieu khien ngat nay la TXIE. C
hie u ch th trang thai thanh ghi TSR la bit TRMT. Bit TXEN cho phep hay khong cho
phep truyen d lieu.
Cac bc can tien hanh khi truyen d lieu qua giao die n USART ong bo
Master mode:
1.Tao xung truyen baud bang cach a cac gia tr can thie t vao thanh ghi
RSBRG va bit ieu khien mc to c o baud BRGH.
2. Cho phe p cong giao dien noi tiep no i tiep ong bo bang ca ch set bit SYNC,
PSEN va CSRC.
3. Set bit TXIE neu can s dung nga t truye n.
4. Set bit TX9 neu nh dang d lieu can truyen la 9 bit.
5. Set bit TXEN e cho phep truyen d lieu.
6. Neu nh dang d lieu la 9 bit, a bit d lieu th 9 vao bit TX9D.
7. a 8 bit d lieu ca n truyen vao thanh ghi TXREG.
8. Neu s dung nga t truyen, ca n kie m tra la i cac bit GIE va PEIE (thanh ghi
INTCON).
Cac thanh ghi lien quan en qua trnh truyen d lieu ba ng giao die n USART
ong bo Master mode:
Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho phep ta t ca ca c
ngat.
Thanh ghi RCSTA (a ch 18h): cha bit cho phep cong truyen d lie u

11.1.2.2 NHAN D LIEU QUA CHUAN GIAO TIEP USART ONG BO
MASTER MODE
Cau truc khoi truyen d lieu la khong oi so vi giao die n bat ong bo, ke ca
cac c hieu, nga t nhan va ca c thao ta c tren cac thanh pha n o. ie m khac bie t duy nhat
la giao dien nay cho phep hai che o nhan s lie u, o la ch nha n 1 word d lieu (set
bit SCEN) hay nhan mo t chuoi d lieu (set bit CREN) cho t i khi ta clear bit CREN.
Neu ca hai bit eu c set, bit ie u khie n CREN se c u tie n.
Cac bc can tien hanh khi nhan d lieu bang giao dien USART ong bo Master
mode:
1. Thiet la p toc o baud (a gia tr thch hp vao thanh ghi SPBRG va bit
BRGH).
2. Cho phep co ng giao tie p USART ba t ong bo (set bit SYNC, SPEN va
CSRC).
3. Clear bit CREN va SREN.
6. Neu ch nhan 1 word d lieu, set bit SREN, neu nhan 1 chuoi word d lie u,
set bit CREN.
bit RCIE c set).
trnh nhan d lieu co b loi khong.
10. Neu qua trnh truyen nhan co lo i xay ra, xoa loi bang ca ch xoa bit CREN.
11. Neu s dung nga t nhan can set bit GIE va PEIE (thanh ghi INTCON).
Cac thanh ghi lien quan en qua trnh nhan d lie u ba ng giao dien USART ong
bo Master mode:
phep toa n bo ca c ngat (bit GIER va PEIE).
nhan d lieu.
BRGH.

11.1.2.3 TRUYEN D LIEU QUA CHUAN GIAO TIEP USART ONG BO
SLAVE MODE
Qua trnh nay khong co s kha c biet so vi Master mode khi vi ieu khien hoat
ong che o bnh thng. Tuy nhien khi vi ie u khie n ang trang thai sleep, s
khac bie t c the hien ro rang. Neu co hai word d lieu c a vao thanh ghi
TXREG trc khi lenh sleep c thc thi th qua trnh sau se xay ra:
1. Word d lieu au tien se ngay lap t c c a vao thanh ghi TSR e truyen
i.
2. Word d lieu th hai van nam trong thanh ghi TXREG.
3. C hieu TXIF se khong c set.
4. Sau khi word d lieu au tien a dch ra khoi thanh ghi TSR, thanh ghi
TXREG
tiep tu c truyen word th hai vao thanh ghi TSR va c hie u TXIF c set.
5. Neu nga t truyen c cho phep hoat o ng, ngat nay se a nh thc vi ie u
khien va neu toan bo cac ngat c cho phep hoat ong, bo em chng trnh se ch t i
a ch cha chng trnh nga t (0004h).
Cac bc can tien ha nh khi truyen d lieu bang giao dien USART ong bo
Slave mode:
1. Set bit SYNC, SPEN va clear bit CSRC.
2. Clear bit CREN va SREN.
3. Neu can s dung ngat, set bit TXIE.
4. Neu nh dang d lieu la 9 bit, set bit TX9.
5. Set bit TXEN.
6. a bit d lieu th 9 vao bit TX9D trc (neu nh dang d lieu la 9 bit).
7. a 8 bit d lieu vao thanh ghi TXREG.
8. Neu nga t truyen c s dung, set bit GIE va PEIE (thanh ghi INTCON).
Cac thanh ghi lien quan en qua trnh truyen d lieu bang giao dien USART
ong bo Slave mode:
Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho phep ta t ca cac
ngat.
Thanh ghi RCSTA (a ch 18h): cha bit cho phep cong truyen d lie u

11.1.2.4 NHAN D LIEU QUA CHUAN GIAO TIEP USART ONG BO SLAVE
MODE
S kha c biet cua Slave mode so vi Master mode ch the hien ro ra ng khi vi
ie u khie n hoa t ong che o sleep. Ngoai ra che o Slave mode khong quan ta m t i
bit SREN. Khi bit CREN (cho phep nha n chuoi d lie u) c set trc khi lenh sleep
c thc thi, 1 word d lieu van c tiep tu c nhan, sau khi nha n xong bit thanh ghi
RSR se chuyen d lie u vao thanh ghi RCREG va bit RCIF c set. Neu bit RCIE (cho
phep ngat nhan) a c set trc o, nga t se c thc thi va vi ieu khie n c
anh thc, bo em chng trnh se ch en a ch 0004h va chng trnh nga t se c
thc thi.
Cac bc ca n tie n hanh khi nhan d lieu bang giao dien USART ong bo Slave mode:
1. Cho phe p cong giao tiep USART ba t ong bo (set bit SYNC, SPEN clear bit
CSRC).
4. Set bit CREN e cho phep qua trnh nhan d lieu ba t a u.
bit RCIE c set).
trnh nhan d lieu co b loi khong.
8. Neu qua trnh truye n nhan co loi xay ra, xoa loi bang ca ch xoa bit CREN.
9. Neu s dung nga t nhan ca n set bit GIE va PEIE (thanh ghi INTCON).
Cac thanh ghi lien quan en qua trnh nhan d lie u ba ng giao dien USART ong
bo Slavemode:
phep toa n bo ca c nga t (bit GIER va PEIE).
nhan d lieu.
BRGH.

11.2 MSSP

Hnh 2.19 S o khoi MSSP (giao dien SPI)

MSSP ( Master Synchronous Serial Port) la giao dien ong bo noi tie p dung e
giao tie p vi cac thie t b ngoa i vi (EEPROM, ghi dch, chuyen oi ADC,) hay ca c vi
ie u khie n kha c. MSSP co the hoa t ong di hai da ng giao tiep:
o SPI (Serial Pheripheral Interface).
o I2C (Inter-Intergrated Circuit).
Cac thanh ghi ie u khien giao chuan giao tiep nay bao gom thanh ghi trang tha i
SSPSTAT va hai thanh ghi ieu khien SSPSON va SSPSON2. Tuy theo chua n giao
tiep c s dung (SPI hay I2C) ma chc nang ca c thanh ghi na y c the hien kha c
nhau.

11.2.1 SPI
Chuan giao tie p SPI cho phep truyen nhan ong bo. Ta ca n s dung 4 pin cho
chuan giao tiep nay:
RC5/SDO: ngo ra d lieu dang noi tiep (Serial Data output).
RC4/SDI/SDA: ngo vao d lieu dang no i tiep (Serial Data Input). Hnh
2.19 S o khoi MSSP (giao dien SPI)
RC3/SCK/SCL: xung ong bo noi tie p (Serial Clock).
RA5/AN4/SS/C2OUT: chon o i tng giao tiep (Serial Select) khi giao
tiep che o Slave mode.
Cac thanh ghi lien quan en MSSP khi hoat ong chuan giao tie p SPI bao
gom:
Thanh ghi ieu khien SSPCON, thanh ghi na y cho phep oc va ghi.
Thanh ghi trang thai SSPSTAT, thanh ghi na y ch cho phep oc va ghi 2
bit tren, 6 bit con la i ch cho phep oc.
Thanh ghi ong vai tro la buffer truyen nha n SSPBUF, d lie u truyen i
hoac nha n c se c a vao tranh ghi nay. SSPBUF khong co cau
truc em hai l p (doubled-buffer), do o d lieu ghi vao thanh ghi
SSPBUF se lap t c c ghi vao thanh ghi SSPSR.
Thanh ghi dch d lie u SSPSR dung e dch d lieu vao hoac ra. Khi 1
byte d lieu c nha n hoan chnh, d lie u se t thanh ghi SSPSR chuyen
qua thanh ghi SSPBUF va c hieu c set, ong thi nga t se xay ra.
Khi s dung chua n giao tiep SPI trc tie n ta can thie t lap ca c che o cho giao
die n bang cach a ca c gia tr thch hp vao hai thanh ghi SSPCON va SSPSTAT. Ca c
thong so can thie t lap bao go m:
Master mode hay Slave mode. oi vi Master mode, xung clock ong bo se i
ra t chan RC3/SCK/SCL. o i vi Slave mode, xung clock ong bo se c nha n t
ben ngoa i qua chan RC3/SCK/SCL. Ca c che o cua Slave mode.
Mc logic cua xung clock khi trang tha i ta m ngng qua trnh truyen nhan
(Idle).
Canh tac ong cua xung clock ong bo (canh le n hay canh xuong).
To c o xung clock (khi hoa t ong Master mode).
Thi ie m xac nh mc logic cua d lieu ( gia hay cuoi thi gian 1 bit d
lieu c a vao).
Master mode, Slave mode va cac che o cua Slave mode c ie u khien bi
cac bit SSPM3:SSPM0 (SSPCON<3:0>). Xem chi tie t phu luc 2.
MSSP bao gom mot thanh ghi dch d lieu SSPSR va thanh ghi em d lieu
SSPBUF. Hai thanh ghi nay tao tha nh bo e m d lieu kep (doubled-buffer). D lieu se
c dch vao hoa c ra qua thanh ghi SSPSR, bit MSB c dch trc. ay la mot
trong nhng ie m kha c bie t gi hai giao die n MSSP va USART (USART dch bit LSB
trc). Trong qua trnh nhan d lie u, khi d lieu a vao t cha n RC4/SDI/SDA trong
thanh ghi SSPSR a san sang (a nhan u 8 bit), d lieu se c a vao thanh ghi
SSPBUF, bit ch th trang thai bo em BF (SSPSTAT<0>) se c set e bao hie u bo
em a ay, ong thi c ngat SSPIF (PIR1<3>) cung c set. Bit BF se t ong reset
ve 0 khi d lieu trong thanh ghi SSPBUF c oc vao. Bo em kep cho phep oc tiep
byte tiep theo trc khi byte d lieu trc o c oc vao. Tuy nhien ta nen oc trc
d lieu t thanh ghi SSPBUF tr c khi nhan byte d lieu tiep theo.
Qua trnh truyen d lieu cung hoan toa n tng t nhng ng c la i. D lieu ca n
truyen se c a va o thanh ghi SSPBUF ong th i a va o thanh ghi SSPSR, khi o
c hie u BF c set. D lieu c dch t thanh ghi SSPSR va a ra ngoa i qua chan
RC5/SDO. Ngat se xa y ra khi qua trnh dch d lieu hoan tat. Tuy nhien d lieu trc
khi c a ra ngoai phai c cho phep b i tn hieu t cha n . Chan nay o ng vai tro
chon oi tng giao tiep khi SPI che o Slave mode.
Khi qua trnh truyen nhan d lieu ang dien ra, ta khong c phep ghi d lieu
vao thanh ghi SSPBUF. Thao tac ghi d lieu nay se set bit WCON (SSPCON<7>). Mo t
ie u can chu y na la thanh ghi SSPSR khong cho phep truy xuat trc tiep ma pha i
thong qua thanh ghi SSPBUF.
Cong giao tiep cua giao dien SPI c ieu khie n bi bit SSPEN (SSPSON<5>).
Ben canh o can ieu khien chieu xua t nha p cua PORTC thong qua thanh ghi TRISC
sao cho phu hp vi chie u cua giao dien SPI. Cu the nh sau:
RC4/SDI/SDA se t ong c ieu khien bi khoi giao itep SPI.
RS5/SDO la ngo ra d lie u, do o can clear bit TRISC<5>.
Khi SPI da ng Master mode, can clear bit TRISC<3> e cho phep a xung
clock ong bo ra chan RC3/SCK/SCL.
Khi SPI dang Slave mode, can set bit TRISC<3> e cho phep nhan xung
clock ong bo t be n ngoai qua chan RC3/SCK/SCL.
Set bit TRISC<4> e cho phep chan nhan tn hieu ieu
khien truy xua t d lieu khi SPI che o Slave mode.
S o ket noi cua chua n giao tiep SPI nh sau:

Hnh 2.20 S o ket no i cua chua n giao tie p SPI.
Theo s o ket noi nay, khoi Master se ba t au qua trnh truyen nhan d lieu
bang ca ch gi tn hie u xung ong bo SCK. D lieu se dch t ca hai thanh ghi SSPSR
a ra ngoa i neu co mo t canh cua xung ong bo ta c ong va ngng dch khi co tac
ong cua canh con la i. Ca hai khoi Master va Slave nen c a n nh chung ca c qui ta c
tac ong cua xung clock ong bo e d lieu co the dch chuyen ong thi.

11.2.1.1 SPI MASTER MODE.
che o Master mode, vi ie u khien co quyen an nh thi ie m trao oi d
lieu (va oi tng trao oi d lieu neu can) v no ieu khien xung clock ong bo. D
lieu se c truyen nhan ngay th i ie m d lieu c a vao thanh ghi SSPBUF. Ne u
ch ca n nha n d lieu, ta co the an nh cha n SDO la ngo vao (set bit TRISC<5>). D
lieu se c dch va o thanh ghi SSPSR theo mot toc o c nh san cho xung clock
ong bo. Sau khi nhan c mot byte d lieu hoan chnh, byte d lieu se c a dao
thanh ghi SSPBUF, bit BF c set va nga t xay ra. Khi lenh SLEEP c thc thi trong
qua trnh truyen nha n, trang thai cua qua trnh se c gi nguyen va tiep tuc sau khi
vi ieu khien c a nh thc. Gian o xung cua Master mode va cac tac ong cua ca c
bit ieu khien c trnh bay trong hnh ve sau:

Hnh 2.21 Gian o xung SPI che o Master mode. 2.12.2.1.2 SPI SLAVE MODE

11.2.1.2 SPI SLAVE MODE
che o nay SPI se truyen va nhan d lie u khi co xung ong bo xua t hien
chan SCK. Khi truyen nha n xong bit d lieu cuoi cung, c nga t SSPIF se c set.
Slave mode hoat ong ngay ca khi vi ieu khien ang che o sleep, va ngat truyen
nhan cho phep anh thc vi ieu khie n. Khi ch ca n nhan d lie u, ta co the an nh
RC5/SDO la ngo vao (set bit TRISC<5>). Slave mode cho phep s tac ong cua chan
ie u khie n (SSPCON<3:0> = 0100). Khi cha n
mc thap, cha n RC5/SDO c cho phep xuat d lieu va khi
m c cao, d lieu ra chan RC5/SDO b khoa, ong thi SPI
c reset (bo e m bit d lieu c gan gia tr 0)

Hnh 2.22 Gian o xung chuan giao tiep SPI (Slave mode).
Cac thanh ghi lien quan en chuan giao tiep SPI bao gom:
Thanh ghi INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): ch a bit cho phep
toan bo cac nga t (GIE va PEIE).
Thanh ghi PIR1 (a ch 0Ch): cha ngat SSPIE.
Thanh ghi PIE1 (a ch 8Ch): cha bit cho phep ngat SSPIE.
Thanh ghi TRISC (a ch 87h): ieu khie n xuat nhap PORTC.
Thanh ghi SSPBUF (a ch 13h): thanh ghi em d lieu.
Thanh ghi SSPCON (a ch 14h): ieu khien chua n giao tie p SPI.
Thanh ghi SSPSTAT (a ch 94h): cha ca c bit ch th trang thai chuan
giao tiep SPI.
Thanh ghi TRISA (a ch 85h):ie u khie n xuat nhap chan .

11.2.2 I2C
ay la mo t dang khac cua MSSP. Chuan giao tiep I2C cu ng co hai che o
Master,Slave va cung c ket noi vi nga t. I2C se s dung 2 pin e truyen nhan d
lieu:
RC3/SCK/SCL: chan truyen dan xung clock.
RC4/SDI/SDA: chan truyen dan d lieu.
Cac khoi c ba n trong s o khoi cua I2C khong co nhieu kha c biet so v i
SPI.Tuy nhie n I2C co n co them khoi pha t hien bit Start va bit Stop cua d lieu (Start
and Stop bit detect) va khoi xa c nh a ch (Match detect).
Cac thanh ghi lien quan en I2C bao go m:
Thanh ghi SSPCON va SSPCON2: ieu khien MSSP.
Thanh ghi SSPSTAT: thanh ghi cha ca c tra ng thai hoat ong cua MSSP.
Thanh ghi SSPBUF: buffer truyen nha n noi tiep.
Thanh ghi SSPSR: thanh ghi dch dung e truyen nhan d lieu.
Thanh ghi SSPADD: thanh ghi cha a ch cua giao die n MSSP.
Cac thanh ghi SSPCON, SSPCON2 cho phep oc va ghi. Thanh ghi SSPSTAT
ch cho phep oc va ghi 2 bit au, 6 bit co n la i ch cho phep oc.
Thanh ghi SSPBUF cha d lieu se c truyen i hoac nhan c va ong vai
tro nh mo t thanh ghi em cho thanh ghi dch d lieu SSPSR.
Thanh ghi SSPADD cha a ch cua thiet b ngoai vi can truy xuat d lie u cua
I2C khi hoa t ong Slave mode. Khi hoat ong Master mode, thanh ghi SSPADD
cha gia tr tao ra toc o baud cho xung clock dung e truyen nha n d lieu. Trong qua
trnh nhan d lieu, sau khi nhan c 1 byte d lieu hoan chnh, thanh ghi SSPSR se
chuyen d lieu vao thanh ghi SSPBUF. Thanh ghi SSPSR khong oc va ghi c, qua
trnh truy xua t thanh ghi na y pha i thong qua thanh ghi SSPBUF. Trong qua trnh truyen
d lieu, d lieu ca n truyen khi c a va o thanh ghi SSPBUF cung se ong thi a
vao thanh ghi SSPSR.

Hnh 2.23 S o khoi MSSP (I2Cslave mode).

I2C co nhieu che o hoat ong va c ieu khien bi cac bit SSPCON<3:0>,
bao go m:
I2C Master mode, xung clock = fosc/4*(SSPADD+1).
I2C Slave mode, 7 bit a ch.
I2C Slave mode, 10 bit a ch.
I2C Slvae mode, 7 bit a ch, cho phep ngat khi phat hien bit Start va bit
Stop.
I2C Slave mode, 10 bit a ch, cho phep ngat khi pha t hien bit Start va
bit Stop.
I2C Firmware Control Master mode.
a ch truyen i se bao gom ca c bit a ch va mot bit e xac nh thao
tac (oc hay ghi d lie u) v i oi tng can truy xua t d lieu.
Khi la chon giao dien I2C va khi set bit SSPEN, cac pin SCL va SDA se
trang tha i c c thu h. Do o trong trng h p can thie t ta phai s dung ien tr keo len
ben ngoa i vi ieu khie n, ben canh o ca n an nh cac gia tr phu hp cho ca c bit
TRISC<4:3> (bit ie u khien xuat nhap ca c chan SCL va SDA).

11.2.2.1 I2C SLAVE MODE.
Vie c trc tien la pha i set cac pin SCL va SDA la input (set bit TRISC<4:3>).
I2C cua vi ieu khien se c ieu khie n bi mot vi ieu khien hoa c mo t thiet b ngoa i
vi khac thong qua cac a ch. Khi a ch nay ch en vi ieu khien, th tai thi iem
nay va ta i thi iem d lie u a c truyen nhan xong sau o, vi ie u khie n se ta o ra
xung e bao hieu ket thuc d lieu, gia tr trong thanh ghi SSPSR se c a va o
thanh ghi SSPBUF. Tuy nhie n xung se khong c ta o ra neu mo t trong cac
trng hp sau xay ra:
Bit BF (SSPSTAT<0>) bao hieu buffer ay a c set trc khi qua trnh
truyen nhan xay ra.
Bit SSPOV (SSPCON<6>) c set tr c khi qua trnh truyen nhan xay ra
(SSPOV c set trong trng hp khi mot byte khac c nhan vao trong khi d lieu
trong thanh ghi SSPBUF tr c o va n cha c la y ra).
Trong ca c trng hp tren, thanh ghi SSPSR se khong a gia tr vao thanh ghi
SSPBUF, nhng bit SSPIF (PIR1<3>)se c set. e qua trnh truye n nhan d lieu
c tie p tuc, can oc d lieu t thanh ghi SSPBUF vao trc, khi o bit BF se t
ong c xoa, con bit SSPOV phai c xoa bang chng trnh. Khi MSSP c kch
hoat, no se ch tn hie u e ba t a u hoa t ong. Sau khi nhan c tn hieu bat au hoat
ong (ca nh xuong a u tien cua pin SDA), d lieu 8 bit se c dch vao thanh ghi
SSPSR. Cac bit a va o se c lay mau ta i canh len cua xung clock. Gia tr nha n c
t thanh ghi SSPSR se c so sanh vi gia tr trong thanh ghi SSPADD tai canh xuong
cua xung clock th 8. Neu ket qua so sanh bang nhau, tc la I2C Master ch nh oi
tng giao tiep la vi ieu khien ang che o Slave mode (ta goi hien tng na y la
address match), bit BF va SSPOV se c xoa ve 0 va gay ra cac tac ong sau:
1. Gia tr trong thanh ghi SSPSR c a vao thanh ghi SSPBUF.
2. Bit BF t ong c set.
3. Mo t xung c ta o ra.
4. C nga t SSPIF c set (ngat c kch hoat neu c cho phep trc o) ta i
canh xuong cua xung clock th 9.
Khi MSSP che o I2C Slave mode 10 bit a ch, vi ieu khie n can pha i nhan
vao 10 bit a ch e so sanh. Bit (SSPSTAT<2>) pha i c xo a ve 0 e cho phep
nhan 2 byte a ch. Byte au tie n co nh dang la 11110 A9 A8 0 trong o A9, A8 la
hai bit MSB cua 10 bit a ch. Byte th 2 la 8 bit a ch con la i.
Quatrnh nha n dang a ch cua MSSP che o I2C Slave mode 10 bit a ch
nh sau:
au tien 2 bit MSB cu a 10 bit a ch c nhan trc, bit SSPIF, BF va UA
(SSPSTAT<1>) c set (byte a ch a u tien co nh dang la 11110 A9 A8
0) .
Cap nha t vao 8 bit a ch thap cua thanh ghi SSPADD, bit UA se c xoa bi
vi ieu khien e khi tao xung clock pin SCL sau khi qua trnh cap nhat hoa n
tat.
oc gia tr thanh ghi SSPBUF (bit BF se c xoa ve 0) va xoa c ngat SSPIF.
Nhan 8 bit a ch cao, bit SSPIF, BF va UA c set.
Cap nhat 8 bit a ch a nha n c vao 8 bit a ch cao cua thanh ghi SSPADD,
neu a ch nha n c la ung (address match), xung clock chan SCL c
khi ta o va bit UA c set.
oc gia tr thanh ghi SSPBUF (bit BF se c xoa ve 0) va xoa c ngat SSPIF.
Nhan tn hie u Start.
Nhan byte a ch cao (bit SSPIF va BF c set).
oc gia tr thanh ghi SSPBUF (bit BF c xoa ve 0) va xoa c nga t SSPIF.
Trong o cac bc 7,8,9 xa y ra trong qua trnh truyen d lieu che o Slave
mode. Xem gian o xung cua I2C e co c hnh a nh cu the hn ve cac bc tie n
hanh trong qua trnh nhan dang a ch.
Xet qua trnh nhan d lieu che o Slave mode, ca c bit a ch se c I2C Master
a vao trc. Khi bit trong ca c bit a ch co gia tr bang 0 (bit nay c nhan
dang sau khi cac bit a ch a c nha n xong) va a ch c ch nh ung (address
match), bit cua thanh ghi SSPSTAT c xoa ve 0 va ng d lieu SDI c
a ve mc logic tha p (xung ). Khi bit SEN (SSPCON<0>) c set, sau khi 1
byte d lieu c nhan, xung clock t cha n RC3/SCK/SCL se c a xuong m c
thap, muon kh i tao la i xung clock ta set bit CKP (SSPCON<4>). ieu nay se la m cho
hie n tng tra n d lieu khong xay ra v bit SEN cho phep ta ieu khien c xung
clock dch d lie u tho ng qua bit CKP (tham khao gia n o xung e biet them chi tie t).
Khi hie n tng tran d lie u xa y ra, bit BF hoac bit SSPOV se c set. Nga t se xay ra
khi mot byte d lieu c nha n xong, c nga t SSPIF se c set va pha i c xoa bang
chng trnh.

Hnh 2.24 Gian o xung cua I2C Slave mode 7 bit a ch trong qua trnh nhan d lieu
(bit SEN = 0).

Hnh 2.25 Gian o xung cua I2C Slave mode 10 bit a ch trong qua trnh nha n d lieu
(bit SEN = 0).
(bit SEN = 1).

(bit SEN = 1).

Xet qua trnh truyen d lie u, khi bit trong cac bit d lieu mang gia tr 1 va
a ch c ch nh ung (address match), bit cua thanh ghi SSPSTAT se c
set. Cac bit a ch c nhan trc va a vao thanh ghi SSPBUF. Sau o xung
c tao ra, xung clock chan RC3/SCK/SCL c a xuong m c thap bat chap tra ng
tha i cua bit SEN. Khi o I2C Master se khong c a xung clock vao I2C Slave cho
en khi d lieu thanh ghi SSPSR trang thai wsan sang cho qua trnh truyen d lieu
(d lieu a va o thanh ghi SSPBUF se ong thi c a vao thanh ghi SSPSR). Tiep
theo cho phep xung pin RC3/SCK/SCL ba ng ca ch set bit CKP (SSPCON<4>). Tng
bit cua byte d lieu se c dch ra ngoa i tai mo i ca nh xuong cua xung clock. Nh vay
d lie u se san sa ng ngo ra khi xung clock mc logic cao, giu p cho I2C Master nhan
c d lieu tai mo i canh len cua xung clock. Nh vay trong qua trnh truyen d lie u
bit SEN khong ong vai tro quan trong nh trong qua trnh nhan d lieu.
Tai canh len xung clock th 9, d lieu a c dch hoan toa n va o I2C Master,
xung se c tao ra I2C Master, ong thi pin SDA se c gi m c logic cao.
Trong trng hp xung c chot bi I2C Slave, thanh ghi SSPSTAT se c
reset.I2C Slave se ch tn hieu cua bit Start e tiep tu c truyen byte d lie u tie p theo
(a byte d lieu tiep theo vao thanh ghi SSPBUF va set bit CKP. Ngat MSSP xay ra
khi mo t byte d lieu ket thuc qua trnh truyen, bit SSPIF c set ta i canh xuong cua
xung clock th 9 va phai c xoa bang chng trnh e a m ba o se c set khi byte
d lieu tiep theo truyen xong.

Hnh 2.28 Gian o xung cua I2C Slave mode 7 bit a ch trong qua trnh truyen d lieu.

Hnh 2.29 Gian o xung cua I2C Slave mode 10 bit a ch trong qua trnh truyen d
lie u.
Qua trnh truyen nhan cac bit a ch cho phep I2C Master chon la oi tng
I2C Slave ca n truy xuat d lieu. Ben canh o I2C con cung cap them mo t a ch GCA
(General Call Address) cho phep chon ta t ca cac I2C Slave. a y la mo t trong 8 a ch
ac bie t cua protocol I2C. a ch nay c nh dang la mo t chuo i 0 vi =0 va c
cho phep bang ca ch set bit GCEN (SSPCON2<7>). Khi o a ch nhan va o se c so
sanh vi thanh ghi SSPADD va vi a ch GCA.

Hnh 2.30 Gian o xung cua I2C Slave khi nhan a ch GCA.

Qua trnh nhan da ng a ch GCA cung tng t nh khi nhan da ng cac a ch
khac va khong co s khac biet ro rang khi I2C hoa t ong che o a ch 7 bit hay 10
bit.

11.2.2.2 I2C MASTER MODE
I2C Master mode c xac lap ba ng ca ch a cac gia tr thch h p vao ca c bit
SSPM cua thanh ghi SSPCON va set bit SSPEN. che o Master, cac pin SCK va
SDA se c ie u khien bi phan c ng cua MSSP.

Hnh 2.31 S o khoi MSSP (I2C Master mode).
I2C Master ong vai tro tch c c trong qua trnh giao tiep va ie u khien cac I2C
Slave thong qua vie c chu o ng tao ra xung giao tiep va cac ieu kie n Start, Stop khi
truyen nhan d lieu. Mot byte d lieu co the c ba t au bang ie u kien Start, ket
thu c bang ie u kien Stop hoa c bat a u va ket thu c vi cung mo t ie u kien kh i ong
lap lai (Repeated Start Condition).
Xung giao tiep noi tie p se c tao ra t BRG (Baud Rate Generator), gia tr an
nh tan so xung clock noi tiep c la y t 7 bit tha p cua thanh ghi SSPADD. Khi d
lieu c a vao thanh ghi SSPBUF, bit BF c set va BRG t ong em ngc ve 0
va dng lai, pin SCL c gi nguyen trang thai trc o.Khi d lieu tie p theo c
a vao, BRG se can mo t khoang thi gian TBRG t ong reset lai gia tr e tiep tu c
qua trnh em ngc. Moi vong lenh (co th i gian TCY ) BRG se gia m gia tr 2 lan.

Hnh 2.32 S o khoi BRG (Baud Rate Benerator) cua I2C Master mode.
Cac gia tr cu the cua tan so xung no i tiep do BRG tao ra c lie t ke trong bang sau:

Trong o gia tr BRG la gia tr c la y t 7 bit thap cua thanh ghi SSPADD.
Do I2C che o Master mode, thanh ghi SSPADD se khong c s dung e cha a
ch, thay va o o chc nang cua SSPADD la thanh ghi cha gia tr cua BRG. e tao
c ieu kien Start, trc het can a hai pin SCL va SDA le n m c logic cao va bit
SEN (SSPCON2<0>) phai c set. Khi o BRG se t ong oc gia tr 7 bit thap cua
thanh ghi SSPADD va bat au em. Sau khoang th i gian TBRG, pin SDA c a
xuong m c logic thap. Trang tha i pin SDA m c logic tha p va pin SCL mc logic
cao chnh la ieu kie n Start cua I2C Master mode. Khi o bit S (SSPSTAT<3>) se
c set. Tiep theo BRG tiep tuc lay gia tr t thanh ghi SSPADD e tie p tuc qua trnh
em, bit SEN c t ong xoa va c ngat SSPIF c set. Trong trng hp pin SCL
va SDA trang thai logic thap, hoac la trong qua trnh tao ieu kie n Start, pin SCL
c a ve trang thai logic tha p trc khi pin SDA c a ve trang tha i logic tha p,
ie u kien Start se khong c hnh thanh, c ngat BCLIF se c set va I2C se trang
tha i ta m ngng hoa t ong (Idle).

Hnh 2.33 Gian o xung I2C Master mode trong qua trnh tao ieu kien Start.
Tn hieu Stop se c a ra pin SDA khi ket thc d lieu bang ca ch set bit
PEN (SSPCON2<2>). Sau ca nh xuong cua xung clock th 9 va vi ta c ong cua bit
ie u khien PEN, pin SDA cu ng c a xuong m c thap, BRG lai ba t au qua trnh
em. Sau mo t khoa ng thi gian TBRG, pin SCL c a len m c logic cao va sau
mo t khoa ng thi gian TBRG na pin SDA cung c a len m c cao. Ngay tai thi
ie m o bit P (SSPSTAT<4>) c set, ngha la ie u kie n Stop a c tao ra. Sau mo t
khoang thi gian TBRG na, bit PEN t ong c xoa va c ngat SSPIF c set.

Hnh 2.34 Gian o xung I2C Master mode trong qua trnh tao ieu kien Stop.

e tao c die u kie n Start lap la i lien tuc trong qua trnh truyen d lieu, trc
het can set bit RSEN (SSPCON2<1>). Sau khi set bit RSEN, pin SCL c a xuong
m c logic tha p, pin SDA c a le n m c logic cao, BRG lay gia tr t thanh ghi
SSPADD vao e ba t au qua trnh e m. Sau khoa ng thi gian TBRG, pin SCL cung
c a len m c logic cao trong khoang thi gian TBRG tiep theo. Trong khoang thi
gian TBRG ke tiep, pin SDA la i c a xuong mc logic thap trong khi SCL van
c gi mc logic cao. Ngay thi iem o bit S (SSPSTAT<3>) c set e ba o
hie u ieu kien Start c hnh thanh, bit RSEN t ong c xoa va c ngat SSPIF se
c set sau mot khoang thi gian TBRG na. Lu c na y a ch cua I2C Slave co the
c a vao thanh ghi SSPBUF, sau o ta ch vie c a tiep a ch hoac d lieu tie p
theo vao thanh ghi SSPBUF mo i khi nhan c tn hie u t I2C Slave, I2C Master
se t ong tao tn hieu Start lap la i lie n tuc cho qua trnh truyen d lieu lien tu c.
Can chu y la ba t c mo t trnh t nao sai trong qua trnh ta o ieu kien Start lap
lai se lam cho bit BCLIF c set va I2C c a ve trang thai Idle.

Hnh 2.35 Gian o xung I2C Master mode trong qua trnh tao ieu kien Start lie n tuc.

Xet qua trnh truyen d lieu, xung clock se c a ra t pin SCL va d lieu
c a ra t pin SDA. Byte d lieu au tien phai la byte a ch xac nh I2C Slave
can giao tiep va bit (trong trng hp nay = 0). au tien cac gia tr a ch se c
a vao thanh ghi SSPBUF, bit BF t ong c set le n 1 va bo em ta o xung clock noi
tiep BRG (Baud Rate Generator) ba t au hoat ong. Khi o tng bit d lie u (hoa c a
ch va bit ) se c dch ra ngoai theo t ng canh xuong cua xung clock sau khi canh
xuong au tien cua pin SCL c nhan die n (ie u kien Start), BRG bat au em ngc
ve 0. Khi ta t ca ca c bit cua byte d lie u c a c a ra ngoa i, bo em BRG mang
gia tr 0. Sau o, ta i canh xuong cua xung clock th 8, I2C Master se ngng ta c ong
len pin SDA e ch i tn hieu t I2C Slave (tn hieu xung ). Tai canh xuong cua
xung clock th 9, I2C Master se lay mau tn hie u t pin SDA e kie m tra xem a ch
a c I2C Slave nhan dang cha, trang tha i c a vao bit ACKSTAT
(SSPCON2<6>). Cung ta i thi iem canh xuong cua xung clock th 9, bit BF c t
ong clear, c ngat SSPIF c set va BRG tam ngng hoa t o ng cho t i khi d lie u
hoac a ch tiep theo c a vao thanh ghi SSPBUF, d lieu hoa c a ch se tiep tu c
c truyen i tai canh xuong cua xung clock tiep theo.

Hnh 2.36 Gian o xung I2C Master mode trong qua trnh truyen d lie u.
Xet qua trnh nhan d lieu che o I2C Master mode. Trc tie n ta can set bit
cho phep nhan d lieu RCEN (SSPCON2<3>). Khi o BRG bat au qua trnh em, d
lieu se c dch va o I2C Master qua pin SDA tai canh xuong cu a pin SCL. Ta i ca nh
xuong cua xung clock th 8, bit c hie u cho phep nha n RCEN t ong c xoa, d
lieu trong thanh ghi SSPSR c a va o thanh ghi SSPBUF, c hieu BF c set, c
ngat SSPIF c set, BRG ngng e m va pin SCL c a ve mc logic thap. Khi o
MSSP tra ng tha i ta m ngng hoat ong e ch i lenh tiep theo. Sau khi oc gia tr
thanh ghi SSPBUF, c hieu BF t ong c xoa. Ta con co the gi tn hieu
bang cach set bit ACKEN (SSPCON2<4>).

Hnh 2.37 Gian o xung I2C Master mode trong qua trnh nha n d lieu.

12. CONG GIAO TIEP SONG SONG PSP (PARALLEL SLAVE PORT)
Ngoai ca c cong noi tiep va ca c giao ien noi tie p c trnh bay phan tren, vi
ie u khie n PIC16F877A co n c ho tr mot cong giao tie p song song va chua n giao
tiep song song thong qua PORTD va PORTE. Do co ng song song ch hoa t ong che
o Slave mode nen vi ie u khien khi giao tie p qua giao die n nay se chu s ieu khie n
cua thiet b ben ngoa i thong qua cac pin cua PORTE, trong khi d lie u se c oc
hoac ghi theo dang bat ong bo thong qua 8 pin cua PORTD. Bit ieu khie n PSP la
PSPMODE (TRISE<4>). PSPMODE c set se thiet la p chc nang ca c pin cua
PORTE la ca c pin cho phep o c d lieu , cho phep ghi d lieu
va pin chon vi ie u khie n phu c vu cho vie c
truyen nhan d lie u song song thong qua bus d lie u 8 bit cua PORTD. PORTD lu c nay
ong vai tro la thanh ghi chot d lie u 8 bit, ong thi ta c ong cua thanh ghi TRISD
cung se c bo qua do PORTD lu c nay chu s ieu khien cua ca c thiet b ben ngoa i.
PORTE van chu s ta c ong cua thanh ghi TRISE, do o can xac lap trang thai cac pin
PORTE la input bang cach set cac bit TRISE<2:0>. Ngoa i ra ca n a gia tr thch hp
cac bit PCFG3:PCFG0 (thanh ghi ADCON1<3:0>) e an nh cac pin cua PORTE la
cac pin I/O dang digital (PORTE co n la ca c pin chc na ng cua kho i ADC).
Khi ca c pin va cu ng m c thap, d lieu t ben ngoai se c ghi len
PORTD. Khi mo t trong hai pin tren chuye n len m c logic cao, c hie u bao d lieu
trong buffer a ay BIF (TRISE<7>) c set va c ngat PSPIF (PIR1<7>) c set e
bao hieu ket thuc ghi d lieu. Bit BIF ch c xoa ve 0 khi d lie u va nhan c
PORTD c oc va o. Bit bao hieu d lieu nha n c trong buffer b tran IBOV
(TRISE<5>) se c set khi vi ie u khien nhan tiep d lieu tiep theo trong khi cha
oc vao d lieu a nha n c trc o. Khi cac pin va cung m c logic
thap, bit ba o hieu buffer truyen d lieu a a y BOF (TRISE<6>) se c xoa ngay lap
t c e bao hie u PORTD a san sang cho qua trnh oc d lieu. Khi mo t trong hai pin
tren chuyen sang m c logic cao, c ngat PSPIF se c set e ba o hieu qua trnh oc
d lieu hoan tat. Bit BOF van c gi m c logic 0 cho en khi d lie u tie p theo c
a vao PORTD.

Hnh 2.38 S o khoi cua PORTD va PORTE khi hoat o ng che o PSP Slave mode.
Can chu y la nga t SSPIF c ieu khien bi bit PSPIE (PIE1<7>) va phai c
xoa bang chng trnh.
Cac thanh ghi lien quan en PSP bao gom:
Thanh ghi PORTD (a ch 08h): cha d lie u can oc hoa c ghi.
Thanh ghi PORTE (a ch 09h): cha gia tr cac pin PORTE.
Thanh ghi TRISE (a ch 89h): cha ca c bit ie u khie n PORTE va PSP.
Thanh ghi PIR1 (a ch 0Ch): cha c ngat PSPIF.
Thanh ghi PIE1 (a ch 8Ch): cha bit cho phep nga t PSP.
Thanh ghi ADCON1 (a ch 9Fh): ieu khie n khoi ADC ta i PORTE.

13. TONG QUAN VE MOT SO AC TNH CUA CPU.
13.1 CONFIGURATION BIT
ay la ca c bit dung e la chon cac a c tnh cua CPU. Cac bit nay c cha
trong bo nh chng trnh ta i a ch 2007h va ch co the c truy xuat trong qua trnh
lap trnh cho vi ie u khie n. Chi tiet ve cac bit nay nh sau:

Bit 13 CP: (Code Protection)
1: tat che o bao ve ma chng trnh.
0: ba t che o bao ve ma chng trnh.
Bit 12, 5, 4: khong quan ta m va c mac nh mang gia tr 0.
Bit 11 DEBUG (In-circuit debug mode bit)
1:khong cho phep, RB7 va RB6 c xem nh cac pin xuat nha p bnh
thng.
0:cho phep, RB7 va RB6 la ca c pin c s dung cho qua trnh debug.
Bit 10-9 WRT1:WRT0 Flash Program Memory Write Enable bit
11: Tat chc nang cho ng ghi, EECON se ie u khien qua trnh ghi len toan
bo nh chng trnh.
10: ch chong t a ch 0000h:00FFh.
01: ch chong ghi t a ch 0000h:07FFh.
00: ch chong ghi t a ch 0000h:0FFFh.
Bit 8 CPD Data EEPROM Memory Write Protection bit
1: Tat chc nang bao ve ma cua EEPROM.
0: Ba t chc na ng ba o ve ma.
Bit 7 LVP Low-Voltage (Single supply) In-Circuit Serial Programming Enable
1: Cho phep che o nap ien ap thap, pin RB3/PGM c s dung cho
che o nay.
0: Khong cho phep che o nap ien ap thap, ien ap cao c a vao t
pin , pin RB3 la pin I/O bnh thng.
Bit 6 BODEN Brown-out Reset Enable bit
1: cho phep BOR (Brown-out Reset)
0: khong cho phep BOR.
Bit 3 Power-up Timer Enable bit
1: khong cho phep PWR.
0: cho phep PWR.
Bit 2 WDTEN Watchdog Timer Enable bit
1: cho phep WDT.
0: khong cho phep WDT. Bit 1-0 FOSC1:FOSC0 la chon loa i oscillator
11: s du ng RC oscillator.
10: s du ng HS oscillator.
01: s du ng XT oscillator.
00: s du ng LP oscillator.
Chi tiet ve ca c a c tnh se c e cap cu the trong ca c pha n tie p theo.

13.2 CAC AC TNH CUA OSCILLATOR
PIC16F877A co kha nang s dung mot trong 4 loa i oscillator, o la :
LP: (Low Power Crystal).
XT: Tha ch anh bnh thng.
HS: (High-Speed Crystal).
RC: (Resistor/Capacitor) dao ong do ma ch RC ta o ra.
oi vi cac loai oscillator LP, HS, XT, oscillator c ga n vao vi ieu khien
thong qua ca c pin OSC1/CLKI va OSC2/CLKO. oi vi ca c ng dung khong ca n cac
loa i oscillator toc o cao, ta co the s dung ma ch dao ong RC lam nguon cung cap
xung hoat ong cho vi vi ieu khien. Tan so tao ra phu thuoc vao cac gia tr ie n ap,
gia tr ien tr va tu ie n, ben canh o la s anh hng cua ca c yeu to nh nhiet o,
cha t lng cua ca c linh kien.

Hnh 2.39 RC oscillator.

Cac linh kien s dung cho mach RC oscillator pha i bao am ca c gia tr sau:
3 K < REXT < 100 K
CEXT >20 pF

13.3 CAC CHE ORESET
Co nhie u che o reset vi ieu khien, bao go m: Power-on Reset POR (Reset khi
cap nguon hoa t ong cho vi ieu khien).
reset trong qua trnh hoat ong.
t che o sleep.
WDT reset (reset do khoi WDT ta o ra trong qua trnh hoa t ong).
WDT wake up t che o sleep.
Brown-out reset (BOR).
Ngoai tr reset POR trang thai cac thanh ghi la khong xac nh vaWDT wake
up khong a nh hng en trang tha i cac thanh ghi, ca c che o reset con lai eu a gia
tr cac thanh ghi ve gia tr ban a u c an nh san. Ca c bit va ch th tra ng tha i
hoat ong, trang tha i reset cua vi ie u khie n va c ieu khie n b i CPU.
reset: Khi pin mc logic tha p, vi ieu khien se c reset. Tn hie u
reset c cung cap bi mot mach ngoa i vi vi cac yeu ca u cu the sau: Khong noi pin
trc tiep len nguon VDD. R1 phai nho hn 40 K e a m bao ca c a c tnh ien
cua vi ie u khien. R2 phai l n hn 1 K e ha n dong i vao vi ieu khien.

Hnh 2.40 Mach reset qua pin .
reset con c chong nhie u bi mo t bo lo c e tra nh ca c tn hieu nho ta c
ong le n pin .
Power-on reset (POR): ay la xung reset do vi ieu khien ta o ra khi phat hie n
nguon cung cap VDD. Khi hoat ong che o bnh thng, vi ie u khien can c
am ba o ca c thong so ve dong ie n, ien a p e hoa t ong bnh thng. Nhng neu cac
tham so nay khong c a m bao, xung reset do POR tao ra se a vi ieu khie n ve
trang thai reset va ch tiep tu c hoa t ong khi nao ca c tham so tren c am bao.
Power-up Timer (PWRT): ay la bo nh thi hoat ong da vao mach RC ben
trong vi ieu khien. Khi PWRT c kch hoat, vi ieu khien se c a ve tra ng thai
reset. PWRT se tao ra mo t khoang thi gian delay (khoang 72 ms) e VDD ta ng en
gia tr thch hp.
Oscillator Start-up Timer (OST): OST cung ca p mo t khoa ng thi gian delay
bang 1024 chu k xung cua oscillator sau khi PWRT ngng tac ong (vi ieu khien a
u ieu kien hoat o ng) e a m bao s o n nh cua xung do oscillator pha t ra. Ta c
ong cua OST co n xa y ra oi vi POR reset va khi vi ieu khien c anh thc t che
o sleep. OST ch tac ong oi vi ca c loai oscillator la XT, HS va LP.
Brown-out reset (BOR): Ne u VDD ha xuo ng tha p hn gia tr VBOR (khoang
4V) va keo dai trong khoang thi gian ln hn TBOR (khoang 100 us), BOR c kch
hoat va vi ieu khien c a ve trang tha i BOR reset. Neu ie n ap cung cap cho vi
ie u khien ha xuong thap hn VBOR trong khoang thi gian ngan hn TBOR, vi ieu
khien se khong c reset. Khi ien ap cung cap u cho vi ieu khien hoa t ong,
PWRT c kch hoa t e tao ra mo t khoang thi gian delay (khoang 72ms). Neu trong
khoang thi gian nay ie n ap cung cap cho vi ie u khien lai tie p tuc ha xuong di
m c ien ap VBOR, BOR reset se lai c kch hoat khi vi ieu khien u ien ap hoat
ong. Mo t ie m ca n chu y la khi BOR reset c cho phep, PWRT cung se hoat ong
bat chap tra ng thai cua bit PWRT.
To m la i e vi ieu khie n hoa t ong c t khi cap nguon can tra i qua cac bc
sau: POR tac ong. PWRT (neu c cho phep hoa t ong) tao ra khoang thi gian
delay TPWRT e on nh nguon cung ca p. OST (neu c cho phep) tao ra khoang
thi gian delay bang 1024 chu k xung cua oscillator e on nh tan so cua oscillator.
en thi iem nay vi ie u khien m i ba t a u hoat ong bnh thng. Thanh ghi ieu
khien va ch th trang tha i nguon cung cap cho vi ieu khien la thanh ghi PCON (xem
phu lu c 2 e bie t them chi tie t).

Hnh 2.41 S o cac che o reset cu a PIC16F877A.

13.4 NGAT (INTERRUPT)
PIC16F877A co en 15 nguon tao ra hoa t ong nga t c ie u khien bi thanh
ghi INTCON (bit GIE). Ben canh o moi ngat co n co mo t bit ieu khien va c nga t
rie ng. Cac c nga t va n c set bnh thng khi thoa man ieu kie n ngat xay ra ba t
chap tra ng tha i cua bit GIE, tuy nhien hoa t ong ngat van phu thuoc vao bit GIE va ca c
bit ieu khien khac. Bit ieu khie n ngat RB0/INT va TMR0 nam trong thanh ghi
INTCON, thanh ghi nay con cha bit cho phep ca c nga t ngoa i vi PEIE. Bit ie u khien
cac ngat nam trong thanh ghi PIE1 va PIE2. C nga t cua ca c nga t nam trong thanh ghi
PIR1 va PIR2. Trong mo t thi ie m ch co mo t chng trnh ngat c thc thi, chng
trnh ngat c ket thuc bang lenh RETFIE. Khi chng trnh ngat c thc thi, bit
GIE t ong c xoa, a ch le nh tiep theo cua chng trnh chnh c cat vao trong
bo nh Stack va bo em chng trnh se ch en a ch 0004h. Lenh RETFIE c
dung e thoa t khoi chng trnh nga t va quay tr ve chng trnh chnh, ong thi bit
GIE cu ng se c set e cho phep ca c nga t hoat ong tr la i. Cac c hieu c dung e
kie m tra ngat nao ang xay ra va pha i c xoa bang chng trnh trc khi cho phep
ngat tiep tuc hoat ong tr lai e ta co the phat hie n c thi ie m tie p theo ma ngat
xay ra.
oi vi ca c nga t ngoa i vi nh nga t t cha n INT hay ngat t s thay oi trang tha i
cac pin cua PORTB (PORTB Interrupt on change), vie c xac nh ngat nao xa y ra can 3
hoac 4 chu k lenh tu y thuoc vao thi ie m xay ra nga t.
Can chu y la trong qua trnh th c thi nga t, ch co gia tr cua bo e m chng trnh
c cat va o trong Stack, trong khi mo t so thanh ghi quan trong se khong c ca t va
co the b thay oi gia tr trong qua trnh thc thi chng trnh ngat. ieu nay nen c
x l ba ng chng trnh e tranh hien tng tren xay ra.

Hnh 2.42 S o logic cua tat ca cac ngat trong vi ie u khien PIC16F877A.

13.4.1 NGAT INT
Ngat na y da tren s thay o i trang thai cua pin RB0/INT. Canh ta c ong gay ra
ngat co the la ca nh le n hay ca nh xuong va c ieu khien bi bit INTEDG (thanh ghi
OPTION_ REG <6>). Khi co canh ta c ong thch hp xuat hien ta i pin RB0/INT, c
ngat INTF c set bat chap trang tha i cac bit ie u khien GIE va PEIE. Ngat nay co
kha nang anh thc vi ie u khien t che o sleep neu bit cho phep ngat c set trc
khi lenh SLEEP c thc thi.

13.4.2 NGAT DO S THAY OI TRANG THAI CAC PIN TRONG PORTB
Cac pin PORTB<7:4> c dung cho nga t nay va c ieu khien bi bit RBIE
(thanh ghi INTCON<4>). C nga t cua nga t nay la bit RBIF (INTCON<0>).

13.5 WATCHDOG TIMER (WDT)
Watchdog timer (WDT) la bo em oc lap dung nguon xung e m t bo tao xung
c tch hp san trong vi ieu khie n va kho ng phu thuoc va o bat k nguon xung clock
ngoai vi nao. ieu o co ngha la WDT va n hoat ong ngay ca khi xung clock c lay
t pin OSC1/CLKI va pin OSC2/CLKO cua vi ieu khie n ngng hoat ong (chang ha n
nh do tac ong cua lenh sleep). Bit ieu khie n cua WDT la bit WDTE nam trong bo
nh chng trnh a ch 2007h (Configuration bit). WDT se t ong reset vi ie u
khien (Watchdog Timer Reset) khi bo em cua WDT b tran (neu WDT c cho phep
hoat ong), ong thi bit t ong c xoa. Neu vi ie u khien ang che o sleep th
WDT se anh thc vi ie u khien (Watchdog Timer Wake-up) khi bo em b tran. Nh
vay WDT co tac dung reset vi ieu khie n thi ie m can thie t ma khong can en s
tac ong t ben ngoa i, chang han nh trong qua trnh thc thi lenh, vi ie u khien b
ket mot cho na o o ma khong thoa t ra c, khi o vi ieu khie n se t ong c
reset khi WDT b tra n e chng trnh hoat ong ung tr la i. Tuy nhie n khi s dung
WDT cung co s phie n toai v vi ie u khien se thng xuyen c reset sau mo t thi
gian nha t nh, do oi can tnh toan thi gian thch hp e xoa WDT (dung le nh
CLRWDT). Va e vie c an nh thi gian reset c linh ong, WDT con c ho tr
mo t bo chia tan so prescaler c ieu khie n bi thanh ghi OPTION_REG (prescaler
nay c chia xe v i Timer0).
Mot ie m can chu y na la lenh sleep se xo a bo em WDT va prescaler. Ngoa i
ra lenh xoa CLRWDT ch xoa bo e m ch khong lam thay oi o i tng ta c ong cua
prescaler (WDT hay Timer0).
Xem lai Timer0 va thanh ghi OPTION_REG (phu lu c 2) e biet them chi tiet.

13.6 CHE O SLEEP
ay la che o hoat o ng cua vi ieu khie n khi lenh SLEEP c thc thi. Khi o
neu c cho phep hoat ong, bo em cua WDT se b xoa nhng WDT va n tiep tu c
hoat ong, bit (STATUS<3>) c reset ve 0, bit c set, oscillator ngng ta c ong
va ca c PORT gi nguyen trang thai nh trc khi le nh SLEEP c thc thi. Do khi
che o SLEEP, dong cung cap cho vi ieu khien la rat nho nen ta can th c hien cac
bc sau trc khi vi ieu khien thc thi lenh SLEEP:
a tat ca cac pin ve trang tha i VDD hoac VSS
Can bao a m rang khong co ma ch ngoa i vi nao c ie u khien bi dong ie n
cua vi ie u khien v dong ien nho khong u kha nang cung cap cho cac mach ngoa i vi
hoat ong.
Tam ngng hoat ong cu khoi A/D va khong cho phep ca c xung clock t ben
ngoai ta c ong vao vi ie u khie n.
e y en chc nang keo len ien tr PORTB.
Pin phai m c logic cao.

13.6.1 ANH THC VI IEU KHIEN
Vi ieu khien co the c anh thc di tac ong cua mot trong so ca c hien
tng sau:
1. Ta c ong cua reset ngoai vi thong qua pin .
2. Ta c ong cua WDT khi b tran.
3. Ta c ong t cac ngat ngoa i vi t PORTB (PORTB Interrupt on change hoa c
pin INT).
Cac bit va c dung e the hien tra ng thai cua vi ieu khien va e pha t hien
nguon tac ong la m reset vi ieu khie n. Bit c set khi vi ieu khien c cap nguon
va c reset ve 0 khi vi ieu khie n che o sleep. Bit c reset ve 0 khi WDT tac
ong do bo em b tra n.
Ngoai ra co n co mo t so nguon ta c ong khac t ca c chc nang ngoa i vi bao gom:
oc hay ghi d lieu thong qua PSP (Parallel Slave Port).
Ngat Timer1 khi hoa t ong che o em ba t ong bo.
Ngat CCP khi hoa t o ng che o Capture.
Cac hien tng a c biet lam reset Timer1 khi hoa t ong che o em bat ong
bo dung nguon xung clock ben ngoai).
Ngat SSP khi bit Start/Stop c pha t hie n.
SSP hoat ong che o Slave mode khi truyen hoac nhan d lieu.
Tac ong cua USART t cac pin RX hay TX khi hoat ong che o Slave mode
ong bo.
Khoi chuyen oi A/D khi nguon xung clock hoat ong dang RC.
Hoan ta t qua trnh ghi vao EEPROM.
Ngo ra bo so sanh thay o i trang tha i.
Cac ta c ong ngoai vi kha c khong co tac dung a nh thc vi ie u khien v khi
che o sleep cac xung clock cung cap cho vi ieu khien ngng hoa t ong. Be n canh o
can cho phep ca c nga t hoa t ong tr c khi lenh SLEEP c thc thi e bao am ta c
ong cua cac nga t. Viec anh thc vi ie u khie n t ca c ngat van c th c thi ba t chap
trang thai cua bit GIE. Neu bit GIE mang gia tr 0, vi ieu khien se thc thi lenh tiep
theo sau lenh SLEEP cua chng trnh (v chng trnh ngat khong c cho phep th c
thi). Neu bit GIE c set trc khi lenh SLEEP c thc thi, vi ie u khien se thc thi
lenh tiep theo cua chng trnh va sau o nhay t i a ch ch a chng trnh nga t
(0004h). Trong trng hp le nh tiep theo khong ong vai tro quan trong trong chng
trnh, ta can a t them lenh NOP sau le nh SLEEP e bo qua ta c ong cua lenh nay,
ong thi giup ta de dang hn trong viec kie m soa t hoa t ong cu a chng trnh nga t.
Tuy nhien cung co mot so ie m ca n lu y nh sau: Neu ngat xa y ra trc khi lenh
SLEEP c thc thi, lenh SLEEP se khong c thc thi va thay vao o la lenh NOP,
ong thi cac ta c ong cua le nh SLEEP cu ng se c bo qua. Neu nga t xa y ra trong
khi hay sau khi lenh SLEEP c thc thi, vi ieu khie n lap t c c anh thc t che
o sleep, va lenh SLEEP se c th c thi ngay sau khi vi ieu khien c anh thc.
e kie m tra xem lenh SLEEP a c thc thi hay cha, ta kie m tra bit. Neu bit va n
mang gia tr 1 t c la lenh SLEEP a khong c thc thi va thay vao o la le nh NOP.
Ben ca nh o ta can xoa WDT e chac cha n rang WDT a c xoa trc khi thc thi
lenh SLEEP, qua o cho phep ta xa c nh c thi iem vi ieu khien c anh thc
do ta c ong cua WDT.

Chng 3
Chng trnh bien dch va mach nap
cho vi dieu khien PIC16f877A

I. CHNG TRNH BIEN DCH
Nh a trnh bay phan gi i thieu, hien nay co rat nhieu chng trnh bien dch cho
Pic, nhng 2 phan mem c s dung pho bie n nha t hie n nay la MPLAB cua ha ng
Microchip va CCS c.
1. Phan mem bien dch MPLAB
Chng trnh bien dch MPLAB do hang Microchip cung cap ho tr mie n ph tai
trang website http://www.microchip.com. Chuyen ho tr cho trnh bien dch ngon ng
cap thap ASM
Phan mem MPLAB IDE tng thch vi he ie u hanh:
Windows 98 se
Windows ME
Windows NT 4.0 SP6A Wordstations (not sever)
Windows 2000 SP2
Windows XP Home and professional
Cai a c xong kch va o bie u tng tren ma ng hnh se xuat hien:


Sau o:








Bie n dch chng trnh
2. Phan mem bien dch CCS C
Chng trnh c cung cap ta i a ch http://www.ccsinfo.com/download.shtml
CCS la chng trnh bien dch cho lap trnh ngon ng C cho vi ieu khien PIC cua ha ng
Microchip, chng trnh la tch hp cua 3 trnh bien dch cua 3 dong PIC khac nhau do
la:
PCB cho dong PIC 12bits opcodes
PCM cho dong PIC 14bits opcodes
PCH cho dong PIC 16bit va 18bit
Ca 3 trnh bien dch nay c tch hp trong mo t chng trnh bao gom ca soa n
thao va bien dch CCS.
e s dung sau khi ca i ac xong.
Mang hnh khoi ong:

Hng dan tao mo t project m i trong CCS ta vao Project chon PIC Wizard sau o mot
cua so hien ra ye u ca u nhap ten file can tao nh sau:

Chon save mot cua so tao ra e tao mo t project mi nh sau:

Sau o nhap ok la a tao ra mot project m i va cua so lam viec nh sau:

Nh vay a ta o c mo t project mi tien hanh vie t chng trnh va bien dch.
Khi muon bien dich t file *.c sang file *.hex th vao compile => chon compile hoa c
bam F9. Khi bien dch neu xuat hien mang hnh di th tha nh cong.

Neu chng trnh b lo i th con tro se xuat hien tai v tr loi cua chng trnh.

II. CHNG TRNH NAP CHO PIC
1. Chng trnh nap Winpic800
Hien nay co ra t nhieu chng trnh nap cho PIC nhng co 2 phan mem
Winpic8000 va IC-PRO la c s dung rong rai nha t va at hieu qua nha t hie n gi
Khi cai a c xong thi tren desktop xua t hie n bieu tng Winpic800 , kch vao
bie u tng se xuat hie n cua so cho chng trnh nap

Sau o vao setting => chon Hardware e tie n hanh ca i at phan cng cho ma ch
nap,mang hnh setting xuat hien nh sau:

Chon Hardware la JMD programmer, chon apply edits e chap nha n
Sau o chon Pic va ten Pic muo n na p chng trnh. V du muo n nap cho Pic
16f877a th chon Pic16F ten Pic la 16F877A.
Hng da n nap chng trnh bang Winpic800 : chon File => Open hoac
e chon file *.hex ca n nap. Sau o chon Device => program All (ctrl + P) hoa c
chon e nap chng trnh.
2. Chng trnh nap IC-Pro
Chay file ICpros.exe bo qua tat ca ca c loi e m chng trnh. Sau o chon
setting => clear setting xua t hien mang hnh nh sau:

Sau o nhan yes lien tuc e xuat hien mang hnh HardWare setting nh sau:

Chon cac thong so nh mang hnh.sau o ma ng hnh ban a u se xuat hien la i IC-
prog nh hnh di. Chung ta chon Setting=>Options e tiep tuc cai a c cho IC-Prog

Mang hnh Options se hie n ra nhng ch can quan ta m en phan Misc.cac phan
khac c gi nguyen.

Chon Enable Vcc control for JDM, sau o chon Enable NT/2000/XP Driver. Khi
chon xong, ngay la p t c se co mang hnh Confirm hien ra ben di nhan vao yes e ca i
ac

Mot mang hnh Comfirm m i se hien ra e xac nhan driver cho windown NT/2000/XP
chon yes

Nh vay co ng vie c cai ac a hoa n ta t
Hng dan na p cho PIC16f877A:
Khi ong ma ng hnh sau o chon ten pic ca n nap nh hnh sau:

V du : chon Pic16f877A sau o vao file => chon open hoac chon e chon file can
nap. Sau o chon command => program all (F5) hoac chon e nap chng trnh
cho pic16f877A.

CHNG 4
Tap lenh cua vi ieu khien PIC16F877A

VAI NET S LC VE TAP LENH CUA VI IEU KHIEN PIC
Nh a trnh ba y, PIC la vi ieu khie n co ta p lenh rut gon RISC. Hai ngon ng
c s dung hien nay la ngon ng ASM cua MPLAB va ngon ng la p trnh C cua
CCS.
oi vi CCS C cho phep ban pho i hp ASSEMBLY cung vi C , ieu na y cho
phep chng trnh cua ban se tr nen rat uyen chuyen , ket hp c s c manh cua ca
2 ngon ng , du rang vie c phoi hp se la m cho vie c vie t chng trnh tr nen kho khan
hn .

1. Ngon ng lap trnh ASM cua MPLAB
1.1 s lc tap lenh ngon ng lap trnh ASM
Ngon ng lap trnh ASM th bao gom 35 lenh va co the c phan ra tha nh 3
nhom c ban:
Nhom le nh thao tac tren bit.
Nhom le nh thao tac tren byte.
Nhom le nh ie u khie n.
oi v i dong vi ieu khien PIC16Fxxx, moi le nh c ma hoa thanh 14 bit
word, bao gom ca c bit opcode (dung e xa c nh lenh nao c ma hoa) va ca c bit mo
ta mot hay va i tham so cua lenh. oi vi nhom lenh thao ta c tren byte, ta co 2 tham so
f (xa c nh a ch byte can thao tac) va d (xac nh ni cha ket qua thc thi lenh).
Neu d = 0, ket qua se c a vao thanh ghi W. Ne u d = 1, ket qua c a vao
thanh ghi c mo ta bi tham so f. o i vi nhom le nh thao tac tren bit, ta co hai tham
so b (xac nh bit can thao tac) va f (xa c nh a ch byte d lieu can thao ta c).

K hieu quy c trong MPLAB:
K hieu Chc nang
f nh a ch cho file thanh ghi t 0x00 en 0x7F
W Thanh ghi W Working register (accumulator)
b La a ch na m trong file thanh ghi 8bit
K Hang so hoac nhan
x Khong quan tam la 0 hay 1
d La chon ni nhan d lieu
d=0 lu ket qua va o thanh ghi W
d=1 lu ket qua va o thanh ghi f
Mac nh d=1
PC Bo em chng trnh
TO Bit timer-out
PD Bit power-down
Khuon kho chung cua mo t so le nh

Hnh 3.1 C che ma ho a lenh cua PIC16Fxxx.
oi vi nhom lenh ie u khien ch co mo t tham so duy nha t la k (k co the la 8 bit
trong trng hp cac lenh bnh thng hay 11 bit trong trng hp la lenh CALL va
lenh GOTO) dung e mo ta oi tng tac o ng cua vi ieu khien (mo t label, mot hang
so nao o).
Moi lenh se c vi ieu khien thc thi xong trong vong mo t chu k lenh, ngoai
tr cac lenh la m thay oi gia tr bo em chng trnh PC can 2 chu k lenh. Mot chu k
lenh gom 4 xung clock cua oscillator. V du ta s dung oscillator co tan so 4 MHz th
tan so thc thi lenh se la 4MHz/4 = 1 MHz, nh vay mo t chu k le nh co thi gian 1 uS.
Cac lenh thao tac tren mot thanh ghi ba t k eu thc hie n c che Read-Modify-Write,
t c la thanh ghi se c oc, d lieu c thao ta c va ket qua c a vao thanh ghi
cha ket qua (ni cha ket qua tuy thuoc vao lenh thc thi va tham so d). V du nh
khi thc thi lenh CLRF PORTB, vi ie u khien se oc gia tr thanh ghi PORTB, xoa
tat ca cac bit va ghi ket qua tr lai thanh ghi PORTB.
Sau ay ta se i sau vao cau truc, cu phap va ta c ong cu the cua tng lenh.

1.2 Tap lenh cua vi ieu khien
To m tac tap le nh

1.2.1 Lenh ADDLW
Cu phap: ADDLW k (0 k255)
Tac dung: co ng gia tr k vao thanh ghi W,
ket qua c cha trong thanh ghi W.
Bit tra ng tha i: C, DC, Z

1.2.2 Lenh ADDWF
Cu phap: ADDWF f,d 0f255, d[0,1]).
Tac dung: cong gia tr hai thanh ghi W va thanh ghi f. Ket qua c cha trong
thanh ghi W neu d = 0 hoac thanh ghi f neu d =1.

1.2.3 Lenh ANDLW
Cu phap: ANDLW k (0k255)
Tac dung: thc hien phep toan AND gia thanh ghi va gia tr k, ket qua c
cha trong thanh ghi W.
Bit tra ng tha i: Z

1.2.4 Lenh ANDWF
Cu phap: ANDWF f,d (0f127, d [0,1]).
Tac dung: thc hie n phep toan AND gia ca c gia tr cha trong hai thanh ghi W
va f. Ke t qua c a vao thanh ghi W neu d=0 hoa c thanh ghi f neu d = 1.
Bit tra ng tha i: Z

1.2.5 Lenh BCF
Cu phap: BCF f,b (0f127, 0b7)
Tac dung: xoa bit b trong thanh ghi f ve gia tr 0.
Bit tra ng tha i: khong co.

1.2.6 Lenh BSF
Cu phap: BSF f,b (0f127, 0b7)
Tac dung: set bit b trong trnh ghi f.
Bit tra ng tha i: khong co

1.2.7 Lenh BTFSS
Cu phap: BTFSS f,b (0f127, 0b7)
Tac dung: kie m tra bit b trong thanh ghi f. Neu bit b bang 0, le nh tiep theo c
thc thi. Neu bit b bang 1, lenh tiep theo c bo qua va thay vao o la lenh NOP.

1.2.8 Lenh BTFSC
Cu phap: BTFSC f,b (0f127, 0b7)
Tac dung: kie m tra bit b trong thanh ghi f. Neu bit b bang 1, lenh tiep theo c
thc thi. Neu bit b bang 0, lenh tiep theo c bo qua va thay vao o la lenh NOP.

1.2.9 Lenh CALL
Cu phap: CALL k (0k2047)
Tac dung: goi mo t chng trnh con. Trc het a ch quay tr ve t chng
trnh con (PC+1) c ca t vao trong Stack, gia tr a ch m i c a vao bo em
gom 11 bit cua bien k va 2 bit PCLATH<4:3>.

1.2.10 Lenh CLRF
Cu phap CLRF f (0f127)
Tac dung: xoa thanh ghi f va bit Z c set.
Bit tra ng tha i: Z

1.2.11 Lenh CLRW
Cu phap CLRW
Tac dung: xoa thanh ghi W va bit Z c set.
Bit tra ng tha i: Z

1.2.12 Lenh CLRWDT
Cu phap: CLRWDT
Tac dung: reset Watchdog Timer, ong th i prescaler cung c reset, cac bit
va c set len 1.
Bit tra ng tha i: ,

1.2.13 Lenh COMF
Cu phap: COMF f,d (0f127, d[0,1]).
Tac dung: ao cac bit trong thanh ghi f. Ket qua c a vao thanh ghi W neu
d=0 hoa c thanh ghi f neu d=1.
Bit tra ng tha i: Z

1.2.14 Lenh DECF
Cu phap: DECF f,d (0f127, d[0,1]).
Tac dung: gia tr thanh ghi f c gia m i 1 n v. Ket qua c a vao thanh
ghi W neu d = 0 hoa c thanh ghi f neu d = 1.
Bit tra ng tha i: Z

1.2.15 Lenh DECFSZ
Cu phap: DECFSZ f,d (0f127, d[0,1])
Tac dung: ga tr thanh ghi f c gia m 1 n v. Neu ket qua sau khi gia m khac
0, le nh tie p theo c thc thi, neu ket qua bang 0, lenh tiep theo khong c th c thi
va thay vao o la lenh NOP. Ket qua c a vao thanh ghi W neu d = 0 hoa c thanh
ghi f neu d = 1.

1.2.16 Lenh GOTO
Cu phap: GOTO k (0k2047)
Tac dung: nhay t i mo t label c nh ngha bi tham so k va 2 bit PCLATH
<4:3>.

1.2.17 Lenh INCF
Cu phap: INCF f,d (0f127, d [0,1])
Tac dung: tang gia tr thanh ghi f le n 1 n v. Ke t qua c a vao thanh ghi
W ne u d = 0 hoa c thanh ghi f neu d = 1.
Bit tra ng tha i: Z 3.2.18 Lenh INCFSZ

1.2.18 Lenh INCFSZ
Cu phap: INCFSZ f,d (0f127, d[0,1])
Tac dung: tang gia tr thanh ghi f len 1 n v. Ne u ket qua khac 0, le nh tiep
theo c thc thi, neu ket qua bang 0, lenh tiep theo c thay bang le nh NOP. Ke t
qua se c a vao thanh ghi f neu d=1 hoac thanh ghi W neu d = 0.

1.2.19 Lenh IORLW
Cu phap: IORLW k (0k255)
Tac dung: thc hien phep toan OR gia thanh ghi W va gia tr k. Ket qua c
cha trong thanh ghi W.
Bit tra ng tha i: Z

1.2.20 Lenh IORWF
Cu phap: IORWF f,d (0f127, d[0,1])
Tac dung: thc hien phep toan OR gia hai thanh ghi W va f. Ket qua c a
vao thanh ghi W neu d=0 hoa c thanh ghi f neu d=1.
Bit tra ng tha i: Z
1.2.21 Lenh : MOVLW
Cu phap: MOVLW k (0k127)
Tac dung: copy hay nap d lieu 8bit k vao thanh ghi W
Chu ky th c hien : 1
1.2.22 Lenh MOVF
Cu phap: MOVF f,d (0k127), d[0,1]
Tac dung : noi dung thanh ghi f c copy sang ni en tuy thuoc vao
gia tr cua d
Chu ky lenh: 1
1.2.23 Lenh MOVWF
Cu phap: MOVWF f (0k127), d[0,1]
Tac dung : noi dung thanh ghi W c copy sang ni en tuy thuoc va o
thanh ghi f
Chu ky lenh: 1
1.2.24 Lenh RETFIE
Cu phap: RETFIE
Tac dung : tr ve t chng trnh phuc vu ngat
Chu ky lenh: 2
1.2.25 Lenh RETLW
Cu phap: RETFIE
Tac dung : tr ve chng trnh con phuc vu ngat
Chu ky lenh: 2

1.2.26 Lenh RLF
Cu phap: RLF f,d (0f127, d[0,1])
Tac dung: dch trai ca c bit trong thanh ghi f qua c carry. Ke t qua c lu trong
thanh ghi W neu d=0 hoac thanh ghi f neu d=1.
Bit tra ng tha i: C

1.2.27 Lenh RETURN
Cu phap: RETURN
Tac dung: quay tr ve chng trnh chnh t mo t chng trnh con Bit tra ng
tha i:khong co

1.2.28 Lenh RRF
Cu phap: RRF f,d (0f127, d[0,1])
Tac dung: dch phai cac bit trong thanh ghi f qua c carry. Ke t qua c lu
trong thanh ghi W neu d=0 hoa c thanh ghi f neu d=1.
Bit tra ng tha i: C

1.2.29 Lenh RLF
Cu phap: RLF f,d (0f127, d[0,1])
Tac dung: dch trai ca c bit trong thanh ghi f qua c carry. Ke t qua c lu trong
Bit tra ng tha i: C

1.2.30 Lenh SLEEP
Cu phap: SLEEP
Tac dung: a vi ie u khie n ve che o sleep. Khi o WDT b xoa ve 0, bit
c xo ve 0, bit c set len 1 va oscillator khong c cho phep hoa t ong.
Bit tra ng tha i: , .

1.2.31 Lenh SUBLW
Cu phap: SUBLW k
Tac dung: lay gia tr k tr gia tr trong thanh ghi W. Ke t qua c cha trong
thanh ghi W.

1.2.32 Lenh SUBWF
Cu phap: SUBWF f,d (0f127, d[0,1])
Tac dung: lay gia tr trong thanh ghi f em tr cho thanh ghi W. Ket qua c
lu trong thanh ghiaW neu d=0 hoa c thanh ghi f neu d=1.

1.2.33 Lenh SWAP
Cu phap: SWAP f,d (0f127, d[0,1])
Tac dung: a o 4 bit thap vi 4 bit cao trong thanh ghi f. Ket qua c cha trong

1.2.34 Lenh XORLW
Cu phap: XORLW k (0k255)
Tac dung: thc hie n phep toa n XOR gia gia tr k va gia tr trong thanh ghi W.
Ket qua c lu trong thanh ghi W.
Bit tra ng tha i: Z

1.2.35 Lenh XORWF
Cu phap: XORWF f,d
Tac dung: thc hien phep toan XOR gia hai gia tr cha trong thanh ghi W va
thanh ghi f. Ke t qua c lu vao trong thanh ghi W neu d=0 hoac thanh ghi f neu d=1.
Bit tra ng tha i: Z

2. Ngon ng lap trnh C cua CCS C
2.1 s lc ve ngon ng C cua CCS C
CCS la trnh bien dch dung ngon ng C la p trnh cho VK . a y la ngon ng
lap trnh ay sc manh , giup ban nhanh chong trong vie c vie t chng trnh hn so vi
ngon ng Assembly. Tuy nhien C khong phai la va n na ng , co the thc hien mo i th
nh y muo n . Trong 1 so trng hp , no co the sinh ma cha y sai.Mat khac , no sinh ma
khong theo y muonla m cham toc o thc thi chng trnh neu ban oi hoi chng trnh
x ly vi toc o cao , v du nh ieu che PWM
2.2 Tap lenh cua ngon ng C
Cau truc cua chng trnh trong CCS :
#include < 16F877 .h >
#device PIC6f877 *=16 ADC=10
#use delay(clock=20000000)
. . . .
Int16 a,b;
. . . .
Void xu_ly_ADC ( )
{ . . . 4
. . .
}

#INT_TIMER1
Void xu_ly_ngat_timer ( )
{ . . .
. . .
}

Main ( )
{ . . .
. . .
}
au tien la cac ch th tie n x ly : # . . . co nhiem vu bao cho CCS can s dung
nhng g trong chng trnh C nh dung VXL g , co dung giao tiep PC khong , ADC
khong , DELAY khong , . . .
Cac khai ba o bien .
Cac ha m con .
Cac ha m phuc vu ngat theo sau bi 1 ch th tien x ly cho biet dung ngat
nao.
Chng trnh chnh .
Cau truc cac le nh: gom ca c lenh while... do,case...

while (expr) stmt : xet ie u kien trc roi thc thi bieu thc sau .
do stmt while (expr) : thc thi bieu thc roi m i xet ieu kie n sau .
Return : dung cho ha m co tra ve tr , hoac khong tra ve tr cung c , khi o ch
can dung: return ; ( ngha la thoat khoi ham tai o ) .
Break : nga t ngang ( thoa t khoi ) vong la p while. _Continue : quay tr ve a u
vong lap while .
2.2.1 Lenh #DIFINE
Cu phap: #DEFINE <text1> <text2>
Tac dung: thay the mot chuoi k t na y bang mo t chuo i k t kha c, co ngha la
mo i khi chuoi k t text1 xua t hien trong chng trnh, trnh bie n dch se t ong thay
the chuo i k t o bang chuoi k t <text2>.
2.2.2 Lenh INCLUDE
Cu phap: #INCLUDE <filename> hoa c #INCLUDE filename
Tac dung: nh kem mo t file kha c vao chng trnh, tng t nh viec ta copy
file o vao v tr xuat hie n le nh INCLUDE. Neu dung cu pha p <filename> th file nh
kem la file he thong (stem file), neu dung cu phap filename th file nh ke m la file
cua ngi s dung. Thong thng chng trnh c nh ke m theo mo t header file
cha cac thong tin nh ngha cac bien (thanh ghi W, thanh ghi F,..) va ca c a ch ca u
cac thanh ghi ch c nang a c biet trong bo nh d lieu. Neu khong co header file,
chng trnh se kho oc va kho hieu hn.

2.2.3 Lenh CONSTANT
Cu phap: CONSTANT <name>=<value>
Tac dung: khai bao mo t hang so, co ngha la khi phat hien chuoi k t name
trong chng trnh, trnh bien dch se t ong thay bang chuoi k t bang gia tr value
a c nh ngha trc o.

2.2.4 Lenh VARIABLE
Cu phap: VARIABLE <name>=<value>
Tac dung: tng t nh lenh CONSTANT, ch co ie m kha c bie t duy nhat la gia
tr value khi dung lenh VARIABLE co the thay oi c trong qua trnh thc thi
chng trnh con le nh CONSTANT th khong.

2.2.5 Lenh SET
Cu phap: <name variable> SET <value>
Tac dung: ga n gia tr cho mo t ten bien. Ten cua bien co the thay oi c trong
qua trnh thc thi chng trnh.

2.2.6 Lenh EQU
Cu phap: <name constant> EQU <value>
Tac dung: gan gia tr cho ten cua ten cua hang so. Ten cua hang so khong thay
oi trong qua trnh thc thi chng trnh.

2.2.7 Lenh ORG
Cu phap: ORG <value>
Tac dung: nh ngha mo t a ch cha chng trnh trong bo nh chng trnh
cua vi ie u khien.

2.2.8 Lenh END
Cu phap: END
Tac dung: anh dau ket thuc chng trnh.

2.2.9 Lenh __CONFIG
Cu phap:
Tac dung: thiet lap ca c bit ieu khien cac khoi chc na ng cua vi ieu khie n c
cha trong bo nh chng trnh (Configuration bit).

2.2.10 Lenh PROCESSOR
Cu phap: PROCESSOR <processor type>
Tac dung: nh ngha vi ieu khien nao s dung chng trnh.
o la nhng lenh c ban,ngoai ra con nhie u le nh c trnh ba y trang web
info.CCS.com ca c ban t tm hie u the m

CHNG 5
Mot so ng dung cu the cua vi ieu khien pic16f877A

Trong chng nay ta se i sau va o mo t so ng dung cu the cua vi ieu khien
PIC16F877A. Ca c ng dung nay c xa y dng da tren ca c chc nang ngoa i vi c
tch hp san ben trong vi ie u khien, qua o giup ta nam ro hn va ieu khien c
cac khoi chc nang o. Tuy nhien trc tie n se la mo t so ng du ng n gian giu p ta
bc au la m quen vi tap lenh va ca ch vie t chng trnh cho vi ieu khie n PIC.

1. IEU KHIEN CAC PORT I/O.
ay la mo t trong nh ng ng dung n gian nhat giup ta lam quen vi vi ieu
khien. Trong ng dung nay ta se xua t mo t gia tr nao o ra mo t PORT cua vi ieu
khien, chang han nh PORTB. Gia tr nay se c kiem tra ba ng cach ga n vao ca c pin
cua PORTB cac LED. Khi o pin mang gia tr m c logic 1 se la m cho LED sang va pin
mang gia tr mc logic 0 se lam cho LED ta t.
Sau ay la mot vai ie m ca n chu y cho ng dung nay:
e LED sang bnh thng th ien a p a t len LED vao khoang 1.8 en 2.2
Volt tu y theo mau sa c cua LED, trong khi ien ap tai ngo ra cua 1 pin trong PORTB
neu mc logic 1 thng la 5 volt. Do o ta can co them ien tr mac no i tie p vi
LED e ha n dong (co the dung ien tr 0.33 K).
e xua t c gia tr ra PORTB, trc het ta can khi tao cac pin cua PORTB
la output. ieu na y c th c hie n bang cach clear cac bit trong thanh ghi TRISB. Tuy
nhien hai thanh ghi PORTB va TRISB na m hai bank kha c nhau trong bo nh d
lieu.Do o trc khi muo n truy xua t gia tr trong mo t thanh ghi nao o ca n chon bank
d lieu cha thanh ghi o bang ca ch a ca c gia tr thch hp vao 2 bit RP1:RP0 cua
thanh ghi STATUS (xem phu lu c 2 va s o bo nh d lieu).
Do trong tap lenh cua vi ie u khie n PIC khong co lenh nao cho phep a mo t
byte vao mo t thanh ghi cho trc, do o ca n s dung mo t thanh ghi trung gian (thanh
ghi W) va dung hai le nh MOVLW (a byte vao thanh ghi W) va lenh MOVWF (a
gia tr trong thanh ghi W vao thanh ghi f nao o ma ta muon).
Ngoai ra can dung lenh ORG e ch ra a ch ba t a u chng trnh khi vi ieu
khien c reset. Tho ng thng a ch ba t au chng trnh se la a ch 0000h.
Trong trng hp ca n dung en che o reset cua pin MCLR, ta co the thie t ke
them mot ma ch reset ngoai vi (vi ie u khie n se c reset khi pin MCLR chuyen t
m c logic 1 xuong m c logic 0).

Hnh 5.1 Mach nguyen l cu a ng du ng ie u khien cac PORT cua vi ie u khien.

Mot ie m can chu y la vi ie u khie n PIC16F877A co en 2 pin VDD va 2 pin
GND. Trong trng hp nay ta pha i cap nguon va o ta t ca ca c pin tren, khi o vi ie u
khien m i co u ien ap e hoa t ong.
Chng trnh viet cho ng dung tren nh sau:
;chng trnh 4.1.1
;PORTBTEST.ASM
processor 16f877a ; khai bao vi ieu khien
include <p16f877a.inc> ; header file nh kem
__CONFIG _CP_OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON &
_XT_OSC & _WRT_OFF & _LVP_OFF & _CPD_OFF
; khai bao ca c Configuration bits
ORG 0x000 ; a ch bat au chng trnh
GOTO start
Star ; chng trnh chnh bat au tai ay
BCF STATUS,RP1
BCF STATUS,RP0 ; chon BANK0
CLRF PORTB ; xoa PORTB
BSF STATUS,RP0 ; chon BANK1

MOVLW 0x00
MOVWF TRISB ; PORTB <- outputs
MOVLW 0x8F ; gia tr ca n a ra PORTB
MOVWF PORTB ; PORTB <- 8Fh
loop GOTO loop ; vong lap vo ha n
END ; ket thuc chng trnh

Cac bc tiep theo e hoan ta t ng dung tren la bien dch chng trnh tren bang
mo t trnh bien dch Assembly da nh cho vi ie u khien PIC (trnh bien dch MPLAB
chang han), sau o du ng ma ch nap e na p chng trnh vao vi ie u khien PIC va kiem
tra ket qua. Neu khong co loi na o xay ra, LED gan vao ca c pin RB7, RB3, RB2, RB1,
RB0 se sa ng, LED gan vao cac pin con lai se ta t (do gia tr ta a ra PORTB la
8Fh).Hoan toan tng t ta co the vie t chng trnh a mot gia tr ba t k va o cac
PORT cua vi ieu khien PIC16F877A. Tuy nhien co mo t ieu can chu y la oi vi
PORTA, do pin

2. CHNG TRNH DELAY
Chng trnh tren giu p ta a gia tr ra ca c PORT cua vi ieu khien va cac LED
se sang hay ta t tu y theo mc logic a ra cac PORT. Bay gi ta lai muon ca c LED se
chp ta t sau mo t khoa ng th i gian nh trc. Muon vay ta dung them mo t oan chng
trnh DELAY. Thc chat cua chng trnh DELAY la cho vi ie u khien lam mo t cong
vie c vo ngha nao o trong mo t khoang thi gian nh trc. Khoang thi gian nay
c tnh toan da tre n qua trnh thc thi le nh, hay cu the hn la da vao thi gian cua
mo t chu k lenh. Co the vie t chng trnh DELAY da tren oan chng trnh sau:

MOVLW 0X20 ; gia tr 20h
MOVWL delay-reg ; a vao thanh ghi delay
loop DECFSZ delay-reg ; gia m gia tr thanh ghi delay-reg 1 n v
GOTO loop ; nhay t i label loop neu thanh ghi delay-reg
;sau khi giam 1 n v cha gia tr kha c 0.
; lenh nay c thc thi khi delay-reg ba ng 0
Neu dung oan chng trnh nay th thi gian delay c tnh ga n ung nh sau:
td = 3(1+tv)ti
Trong o td la thi gian delay, tv la gia tr a vao thanh ghi delay-reg va ti la
thi gian cua mo t chu k lenh va c tnh theo cong thc:
ti = 4/f0
Vi f0 la tan so cua oscillator. S d co cong thc nay la v mo t chu k le nh bao
gom 4 xung clock. Co ng thc nay ch gan ung v ta a bo qua thi gian thc thi cac
lenh trc label loop va mo t chu k le nh phat sinh khi thanh ghi delay-reg mang gia
tr 0 (trng hp nay can hai chu k le nh e thc thi lenh DECFSZ).
Do thanh ghi delay-reg ch mang gia tr ln nhat la FFh nen thi gian delay ch
gi i han mot khoang thi gian nhat nh tu y thuoc va o xung clock s dung e cap cho
vi ieu khien. Muon tang thi gian delay ta co the goi chng trnh delay nhieu la n
hoac tang so lng vo ng la p cua chng trnh delay nh sau:
MOVLW 0Xff
MOVWF delay-reg1
loop DECFSZ delay-reg1
GOTO loop1 ; thc thi dng lenh nay neu delay-reg kha c 0
GOTO exit ; thc thi dng le nh na y neu delay-reg ba ng 0
Loop1 MOVLW 0Xff
MOVWF delay-reg2
DECFSZ delay-reg2
MOVWF loop1 ; thc thi dng lenh nay neu delay-reg khac 0
GOTO loop ; thc thi dng le nh na y neu delay-reg ba ng 0
Exit ; le nh tiep theo sau thi gian delay
Vi oan chng trnh tren thi gian delay ch ket thu c khi ca hai thanh ghi
delay-reg1 va delay-reg2 eu mang gia tr 0. Sau ay la mo t v du cu the. Yeu cau a t
ra la cho ca c LED trong chng trnh 4.1 chp tat sau mo i 100 miligiay. Gia s ta ang
s dung oscillator 4MHz. Khi o thi gian cua mot chu k le nh la:
ti = 4/4 MHz = 1 uS.
Vi thi gian can delay la td bang 1s th gia tr can a vao thanh ghi delay-reg
la:
tv = (td/3ti) 1 = 33332.
Nh va y ta a vao thanh ghi delay-reg2 gia tr 255 (FFh) va thanh ghi delay-
reg1 gia T
r 33332/255 = 131 (83h).
Chng trnh c viet nh sau:
;chng trnh 4.1.2
;PORTBTESTANDDELAY.ASM
;Version 1.1

_XT_OSC &
_WRT_OFF & _LVP_OFF & _CPD_OFF

delay_reg1 EQU 0x20 ; khai bao a ch cac o nh cha ca c thanh ghi
delay_reg2 EQU 0x21 ; delay-reg1 va delay-reg2

GOTO start
start ; chng trnh chnh ba t a u ta i ay
BCF STATUS,RP1
MOVLW 0x00 MOVWF TRISB ; PORTB <- outputs

loop MOVLW 0x8F ; gia tr ca n a ra PORTB
MOVLW 0x83
MOVWF delay_reg1
MOVLW 0xFF
MOVWF delay_reg2
loop1 DECFSZ delay_reg1
GOTO loop2
GOTO exit1
GOTO loop2
GOTO loop1 ; delay 100 ms
exit1 CLRF PORTB ; xoa PORTB
MOVLW 0x83
MOVWF delay_reg1
MOVLW 0xFF
MOVWF delay_reg2
GOTO loop4
GOTO exit2
GOTO loop4
exit2
GOTO loop ; vong lap vo han


Vi chng trnh nay cac pin cua PORTB se thay oi tra ng tha i sau moi khoang
thi gian delay la 100 ms. ieu na y cho phep ta nhan thay bang mat thng v trong
mo t gia y cac pin cua PORTB se thay oi trang tha i 10 la n. Tuy nhien ta de da ng nha n
thay mot nhc iem cua chng trnh tren la can ti hai oan chng trnh delay vi
cau truc chng trnh, thua t toan va chc nang hoan toan giong nhau. ieu nay la m cho
chng trnh tr nen phc tap va ton nhieu dung lng bo nh cua vi ieu khien. ieu
nay can c chu tro ng v dung lng bo nh chng trnh cua mot vi ieu khie n
thng nho (oi vi PIC16F877A dung lng bo nh chng trnh la 8K word vi mot
word la 14 bit). Mo t phng pha p e khac phuc nhc ie m na y la s dung chng
trnh con va dung lenh CALL e goi chng trnh con o. Chng trnh con co the
c a t tai bat c v tr nao trong chng trnh chnh. Chng trnh 4.2 khi o c
vie t lai nh sau:

;chng trnh 4.1.3
;PORTBTESTANDDELAY.ASM
;Version 1.2

delay_reg1 EQU 0x20 ; khai bao a ch cac o nh cha ca c thanh ghi
delay_reg2 EQU 0x21 ; delay-reg1 va delay-reg2

GOTO start
BCF STATUS,RP1
MOVLW 0x00
loop MOVLW 0x8F ; gia tr ba t k ca n a ra PORTB
CALL delay100ms ; goi chng trnh con delay100ms
CALL delay100ms

Delay100ms
MOVLW 0x83
MOVWF delay_reg1
MOVLW 0xFF
MOVWF delay_reg2

GOTO loop2
GOTO exit
GOTO loop2
Exit
RETURN ; tr ve chng trnh chnh


Vi cach vie t chng trnh s dung chng trnh con, ca u truc chng trnh se
tr nen gon gang de hieu hn, linh hoa t hn va tiet kie m c nhie u dung lng bo nh
chng trnh.
Bay gi ta se ban en mot thua t toan khac e vie t chng trnh delay. Ve
nguyen ta c th thua t toan m i nay khong co nhieu kha c biet so vi thua t toan cu, tuy
nhien le nh s dung trong chng trnh va ca ch tnh toa n thi gian delay th kha c nhau.
Chng trnh con delay100ms vi oscillator 4 MHz co the c vie t la i nh sau:
delay100ms
MOVLW d100
MOVWF count1
d1 MOVLW 0xC7
MOVWF counta
MOVLW 0x01
MOVWF countb
delay_0
DECFSZ counta,1
GOTO $+2 DECFSZ countb,1
GOTO delay_0
DECFSZ count1,1
GOTO d1
RETLW 0x00
END

Trc tien ta xet oa n chng trnh ke t label delay_0. Le nh DECFSZ mat
mo t chu k lenh (tr trng hp thanh ghi counta mang gia tr 0 th can 2 chu k lenh),
lenh GOTO $+2 ma t hai chu k lenh. Le nh nay co ta c dung co ng vao bo em chng
trnh gia tr 2, khi o chng trnh se nha y t i lenh co a ch (PC+2), t c la lenh
GOTO delay_0, lenh nay cu ng ton hai chu k lenh. Nh va y ta ca n tong co ng 5 chu k
lenh e gia m gia tr trong thanh ghi counta 1 n v. Thanh ghi counta mang gia tr 199
(C7h), do o oan chng trnh nay se tao ra mo t khoang thi gian delay:

td = 5(counta+1)*ti = 5(199+1)*1 uS = 1 mS

Muon tao ra thi gian delay 100 mS, ta ch vie c a gia tr 100 vao thanh ghi
count1. V i gia i thua t nay thi gian delay tao ra se dai hn so v i giai thua t ma ta s
dung chng trnh 4.2. Ben canh o ta co the vie t mo t chng trnh con co tac dung
delay mot khoang thi gian ba t k la bo i so cua 1 mS mot cach de dang.Trong chng
trnh tren ta con s dung them mot lenh kha la la lenh RETLW. Lenh nay co ta c dung
tr ve v tr ma chng trnh con c goi va thanh ghi W khi o mang gia tr la tham
so cua lenh RETLW (00h). Trong trng hp nay thanh ghi W khong can mang mot
gia tr cu the khi quay tr ve chng trnh chnh nen lenh RETLW ch co ta c dung nh
lenh RETURN.

3. MOT SO NG DUNG VE AC TNH I/O CUA CAC PORT IEU
KHIEN
Da vao chng trnh delay va thao ta c a d l ie u ra ca c PORT, ta phat trie n
them mot so chng trnh nho vi muc ch lam quen vi cach viet chng trnh cho vi
ie u khie n PIC16F877A.

ng dung 5.1:
Da va o mach nguye n l hnh 4.1 viet chng trnh ieu khie n LED chay. Cu
the la sau thi gian delay 250 ms, LED tie p theo se sang mo t cach tuan t t tren
xuong di. Chng trnh nay c vie t da vao chng trnh 4.3 vi mot vai thay o i
nho. Thay v a mot gia tr bat k ra PORT, ta a ra PORB gia tr 80h, sau o dch
phai gia tr 80h sau moi khoang thi gian delay (dung lenh RRF).

; Chng trnh 5.1.1
; Chng trnh ieu khien LED chay

_XT_OSC &
_WRT_OFF & _LVP_OFF & _CPD_OFF
;-------------------------------------------------------------------------------------------------------
;Khai bao bie n
;--------------------------------------------------------------------------------------------------------
count1 EQU 0x20 ; dung cho chng trnh delay
counta EQU 0x21 ; dung cho chng trnh delay
countb EQU 0x22 ; dung cho chng trnh delay

GOTO start
BCF STATUS,RP1
MOVLW 0x00
MOVLW 0x8F ; gia tr ba t k ca n a ra PORTB
loop CALL delay100ms ; goi chng trnh con delay100ms
RRF PORTB,1 ; dch phai PORTB

delay100ms
MOVLW d100
MOVWF count1
d1 MOVLW 0xC7
MOVWF counta
MOVLW 0x01 MOVWF countb
delay_0
DECFSZ counta,1
GOTO $+2
DECFSZ countb,1
GOTO delay_0
DECFSZ count1,1
GOTO d1 ; delay 100ms
RETLW 0x00 ; tr ve chng trnh chnh

Nh va y da tren mot so chng trnh c ba n, ta ch can thay oi mo t so chi tiet
la co the tao ra mo t ng dung m i. Mo t phng phap khac e viet chng trnh tren la
dung bang d lie u. Phng phap bang d lie u c a ra ay khong mang tnh chat
to i u hoa giai thua t chng trnh ma ch mang tnh chat la m quen vi mot gia i thuat
m i, qua o tao ieu kien thuan l i hn trong vie c viet cac chng trnh ng dung phc
tap hn sau na y. Ta co the vie t lai chng trnh tren theo phng phap bang d lieu
nh sau:
; Chng trnh 5.1.2
; Chng trnh ieu khien LED chay dung ba ng d lieu

count EQU 0x23 ; dung e tra bang d lieu

GOTO start
BCF STATUS,RP1
MOVLW 0x00
MOVWF TRISB ; PORTB <- outputs BCF STATUS,RP0 ; cho n BANK0
Loop1
CLRF count ; reset thanh ghi cha gia tr em
Loop2
MOVF count, 0 ; a gia tr em vao thanh ghi W
CALL Table ; goi chng trnh con Table
MOVWF PORTB ; xuat gia tr cha trong thanh ghi W ra PORTB
INCF count, 0 ; tang gia tr than ghi count va cha ket qua trong
; thanh ghi W
XORLW d8 ; so sanh thanh ghi W vi gia tr 8
BTFSC STATUS,Z ; kie m tra bit Z (Zero)
GOTO Loop1 ; nhay ve label Loop1 neu W = 0
INCF count, 1 ; thc thi lenh nay neu W kha c 0
GOTO Loop2

Table
ADDWF PCL,1 ; cong g tr thanh ghi W vao thanh ghi PCL, ket
; qua cha trong thanh ghi PCL
RETLW b10000000
RETLW b01000000
RETLW b00100000
RETLW b00010000
RETLW b00001000
RETLW b00000100
RETLW b00000010
RETLW b00000001
delay100ms
MOVLW d100
MOVWF count1
d1 MOVLW 0xC7
MOVWF counta
MOVLW 0x01
MOVWF countb
delay_0
DECFSZ counta,1
GOTO $+2
DECFSZ countb,1
GOTO delay_0
DECFSZ count1,1
GOTO d1 ; delay 100ms RETURN ; tr ve chng trnh chnh

pha n trc ta a t ng e cap en lenh RETLW nhng khi o lenh nay ch co
tac dung nh lenh RETURN. Tuy nhien trong trng hp nay lenh RETLW co mot vai
tro cu the hn la mang d lieu t bang d lieu tr ve chng trnh chnh va xuat ra
PORTB d lieu va mang ve o. Sau moi lan mang d lieu ve bien count se tang gia
tr em len. Gia tr e m c a vao thanh ghi W e co ng va o thanh ghi PCL. Thanh
ghi PCL la thanh ghi cha gia tr bo e m chng trnh, gia tr t bie n count c cong
vao thanh ghi PCL tho ng qua thanh ghi W se ieu khien chng trnh nhay ti ung a
ch can lay d lieu t bang d lie u vao thanh ghi W va thanh ghi W mang d lie u o
tr ve chng trnh chnh trong qua lenh RETLW.
e e phong trng hp gia tr bie n count cong vao thanh ghi PCL se ieu
khien chng trnh en v tr vt qua v tr cua bang d lieu (tr ng hp nay xay ra khi
bie n count mang gia tr ln hn 8, khi o v tr lenh ca n thc thi do bo em chng trnh
ch en khong con ung na), ta so sa nh bien count vi gia tr 8. Neu bien count mang
gia tr 8 th phep toa n XOR gia bien cao va gia tr se co ket qua bang 0 va c Z trong
thanh ghi STATUS se c set. Luc nay ta can reset lai bien count bang ca ch nhay ve
label Loop1.
Vie c dung ba ng d lie u trong trng hp na y la m cho chng trnh tr nen da i
hn, qua trnh thc thi chng trnh la u hn v bo e m chng trnh lien tuc b thay oi
gia tr, tuy nhien ta cung thay c mot u ie m cua viec dung bang d lieu la cho
phep ta sa p xep bo tr d lieu mot ca ch linh hoa t. Dieu nay the hien qua vie c ch ca n
thay o i d lieu trong bang d lieu, ta se co c nhieu cach ieu khien cac LED sang
hay tat theo nhieu qui luat khac nhau ch khong ch n thuan la dch LED sang sang
tra i hoa c sang pha i. ng dung sau ay cho ta thay ro hn hie u qua cua bang d lieu.

ng dung 5.2: Tng t nh ng dung 1, nhng lan nay ta cho LED chay t v tr
gia sang hai pha sau mo i khoang thi gian delay 100 ms.
Chng trnh cho ng dung na y hoa n toan tng t nh trong ng dung, ta ch
can thay oi bang d lieu mo t ca ch thch hp.

; Chng trnh 5.1.3
; Chng trnh ieu khien hien th LED
processor 16f877a ; khai ba o vi ieu khien
_XT_OSC & _WRT_OFF & _LVP_OFF & _CPD_OFF ; khai bao cac
Configuration bits
;-----------------------------------------------------------------------------------------------
;Khai bao bie n
;-----------------------------------------------------------------------------------------------
count EQU 0x23 ; dung e tra bang d lieu

GOTO start
Start ; chng trnh chnh ba t a u ta i ay
BCF STATUS,RP1
MOVLW 0x00
Loop1
CLRF count ; reset thanh ghi cha gia tr em
Loop2
MOVF count, 0 ; a gia tr em vao thanh ghi W
CALL Table ; goi chng trnh con Table
MOVWF PORTB ; xuat gia tr cha trong thanh ghi W ra PORTB
INCF count, 0 ; tang gia tr than ghi count va cha ket qua trong
; thanh ghi W
XORLW d8 ; so sanh thanh ghi W vi gia tr 8
BTFSC STATUS,Z ; kie m tra bit Z (Zero)
GOTO Loop1 ; nhay ve label Loop1 neu W = 0
INCF count, 1 ; thc thi lenh nay neu W kha c 0
GOTO Loop2
Table
ADDWF PCL,1 ; cong g tr thanh ghi W vao thanh ghi PCL, ket
; qua cha trong thanh ghi PCL
RETLW b00011000
RETLW b00100100
RETLW b01000010

RETLW b10000001
RETLW b01000010
RETLW b00100100
RETLW b00011000
RETLW b00100100

delay100ms
MOVLW d100
MOVWF count1
d1 MOVLW 0xC7
MOVWF counta
MOVLW 0x01
MOVWF countb
delay_0
DECFSZ counta,1
GOTO $+2
DECFSZ countb,1
GOTO delay_0
DECFSZ count1,1
GOTO d1 ; delay 100ms
RETURN ; tr ve chng trnh chnh


ng dung 5.3: Test chc nang Input/Output cua cac pin cua vi ie u khien.
cac ng dung trc ta ch lam mo t viec la xuat tn hie u ieu khie n ra cac
PORT theo mot so qui tac nh sa n nao o. Trong ng dung nay ta se phat trien them
mo t chc nang na cu a cac PORT la kha na ng nhan tn hieu ie u khien t ben ngoai.
Vi ieu khien se oc tn hie u 0 (ien ap 0 V) va 1 (ien a p 5 V) c tao ra bang ca ch
s dung ca c cong ta c an t ca c pin RB0:RB3 cua PORTB , sau o kiem tra xem cong
tac nao c an va ba t LED tng ng vi cong ta c o (cac LED nay c bo tr ca c
pin RB7:RB4) sang le n. e kie m tra c ng dung nay ta can xa y dng s o mach
nh sau:
Hnh 5.2 Mach test chc nang I/O cho ng dung 3.

Chng trnh vie t cho ng dung na y nh sau:

;Chng trnh 5.1.4
processor 16f877a
include <p16f877a.inc>

;--------------------------------------------------------------------------------------------------------
;Khai bao ha ng
;--------------------------------------------------------------------------------------------------------
SW1 EQU 0
SW2 EQU 1
SW3 EQU 2
SW4 EQU 3
LED1 EQU 4
LED2 EQU 5 LED3 EQU 6
LED4 EQU 7

ORG 0x000
GOTO start
start
BCF STATUS,RP1
BCF STATUS,RP0
CLRF PORTB
BSF STATUS,RP0
MOVLW b'00001111' ; thiet lap chc nang I/O cho tng pin trong PORTB
MOVWF TRISB
BCF STATUS,RP0
loop
BTFSS PORTB,SW1 ; kie m tra cong ta c 1
CALL switch1 ; thc thi lenh nay neu cong tac 1 c an
BTFSS PORTB,SW2 ; neu cong ta c ; 1 khong c a n, kie m tra cong tac 2
CALL switch2 ; tiep tu c qua trnh oi vi cac cong ta c con la i
BTFSS PORTB,SW3
CALL switch3
BTFSS PORTB,SW4
CALL switch4
GOTO loop
switch1
CLRF PORTB
BSF PORTB,LED1
RETURN
switch2
CLRF PORTB
BSF PORTB,LED2
RETURN

switch3
CLRF PORTB
BSF PORTB,LED3
RETURN

switch4
CLRF PORTB BSF PORTB,LED4
RETURN
END
Trong chng trnh tren ta ng dung thuat toan hoi vong thong qua vong lap
loop trong pha n chng trnh chnh. Khi co ng tac khong c nhan, m c logic ta i cac
pin noi vi cong ta c la mc 1. Khi cong tac c a n, cac pin tren sem nh noi a t va
mang mc logic 0. Ta ch viec kie m tra lien tuc trang thai logic cua cac pin o va ba t
LED tng ng vi co ng tac thong qua ca c chng trnh con switch1, switch2, switch3
va swtich4 khi pha t hien mo t cong tac nao o c an. Tuy nhie n can chu y la pha i
thiet lap trang thai I/O thch hp cho tng pin trong PORTB (thie t lap RB3:RB0 la
input, RB7:RB4 la output).
Mot ie m quan trong can lu y la cac cong tac an thng b doi, tc la khi an
xuong hoa c tha ra, ie n ap tai ca c cong ta c se pha i tra i qua mo t giai oa n qua o, ien
ap se dao ong khong on nh trong mot khoang thi gian nao o, ngoai ra tra ng tha i
logic cua pin cung se thay oi do mo t ta c ong t c thi t mo t trng ben ngoai ma
khong pha i do ta an cong tac. Cac yeu to tren se la m anh hng t i hoa t ong cua vi
ie u khie n. e kha c phuc nhc iem tren ta co hai phng phap:
Phng pha p chong doi bang pha n cng: ta them ca c tu ie n vao cac cong
tac e loc bt cac tn hieu nho ga y nhieu va cac tn hieu khong on nh trong thi gian
qua o. Phng phap nay cu ng hieu qua nhng gay to n kem ve linh kie n va ma ch
nguyen l tr nen phc tap.
Phng phap chong doi bang pha n me m: ta cho vi ieu khien delay trong mot
thi gian ngan va kie m tra xem cong ta c co n c an khong, neu cong ta c th c s con
c an th m i tien hanh ca c thao tac tng ng v i cong ta c o.
Chng trnh ca i tien e khac phuc nhc iem tren co the c viet nh sau:
;Chng trnh 5.1.5
processor 16f877a
;--------------------------------------------------------------------------------------------------------
;Khai bao ha ng
;--------------------------------------------------------------------------------------------------------
SW1 EQU 0
SW2 EQU 1
SW3 EQU 2
SW4 EQU 3 LED1 EQU 4
LED2 EQU 5
LED3 EQU 6
LED4 EQU 7
;--------------------------------------------------------------------------------------------------------
;Khai bao bie n
;--------------------------------------------------------------------------------------------------------
count1 EQU 0x20
counta EQU 0x21
countb EQU 0x22
;--------------------------------------------------------------------------------------------------------
;Cac khai bao kha c
;--------------------------------------------------------------------------------------------------------
SWdel SET del150 ; ga n SWdel vi label del150
;--------------------------------------------------------------------------------------------------------
;Chng trnh
;--------------------------------------------------------------------------------------------------------
ORG 0x000
GOTO start
start ; v tr bat au chng trnh chnh
BCF STATUS,RP1
CLRF PORTB
MOVLW b'00001111'
MOVWF TRISB
loop ; vong la p kie m tra cong ta c na o c an
BTFSS PORTB,SW1 ; kie m tra SW1
CALL switch1 ; nha y t i chng trnh con switch1 neu SW1 c a n
BTFSS PORTB,SW2 ; neu SW1 khong c an tiep tuc kie m tra SW2
CALL switch2 ; thao ta c tng t nh SW1
BTFSS PORTB,SW3
CALL switch3
BTFSS PORTB,SW4
CALL switch4
GOTO loop
switch1 CLRF PORTB ; xoa PORTB
CALL SWdel ; goi chng trnh delay del150
BTFSC PORTB,SW1 ; kie m tra cong tac 1 con nhan hay khong
RETURN ; neu khong co n nha n th tr ve chng trnh chnh led1_ON
BSF PORTB,LED1 ; ba t LED1 sa ng
BTFSC PORTB,SW1 ; xa c nha n la i trang thai cong ta c 1
RETURN ; tr ve chng trnh chnh neu cong ta c khong con an
GOTO led1_ON ; tiep tuc gi LED1 sa ng neu cong ta c con c an
switch2 ; thao tac tng t vi ca c cong tac con lai
CLRF PORTB
CALL SWdel
BTFSC PORTB,SW2
RETURN
led2_ON
BSF PORTB,LED2
BTFSC PORTB,SW2
RETURN
GOTO led2_ON

switch3
CLRF PORTB
CALL SWdel
BTFSC PORTB,SW3
RETURN
led3_ON
BSF PORTB,LED3
BTFSC PORTB,SW3
RETURN
GOTO led3_ON

switch4
CLRF PORTB
CALL SWdel
BTFSC PORTB,SW4
RETURN
led4_ON
BSF PORTB,LED4 BTFSC PORTB,SW4
RETURN
GOTO led4_ON
;--------------------------------------------------------------------------------------------------------
;Chng trnh delay ca i tie n cho phep nhieu khoang thi gian delay kha c nhau
;--------------------------------------------------------------------------------------------------------
del0
RETURN
del1
MOVLW d'1'
GOTO delay
del5
MOVLW d'5'
GOTO delay
del10
MOVLW d'10'
GOTO delay
del20
MOVLW d'20'
GOTO delay
del50
MOVLW d'50'
GOTO delay
del100
MOVLW d'100'
GOTO delay
del150
MOVLW d'150'
GOTO delay
del200
MOVLW d'200'
GOTO delay
delay
MOVWF count1
d1 ; ta o thi gian delay 1 mS
MOVLW 0xC7
MOVWF counta
MOVLW 0x01
MOVWF countb
delay_0
DECFSZ counta,1 GOTO $+2
DECFSZ countb,1
GOTO delay_0
DECFSZ count1,1
GOTO d1
RETURN
END

Vi chng trnh tren, thi gian an cong ta c pha i lau hn thi gian delay c
ch nh b i hang so SWdel do cong tac se c kie m tra la i tra ng tha i sau thi gian
delay . Neu thi gian an cong tac khong a t yeu cau, thao ta c ba t LED tng ng vi
cong ta c o sa ng len se khong c thc hien va vi ieu khie n se tiep tu c qua trnh
kie m tra trang thai ca c cong ta c con la i. Thi gian delay ca n c kie m nh ba ng thc
nghiem va c a n nh mot cach thch hp e chong do i mo t cach hieu qua, ong
thi cung khong c lau qua, nh vay se gay s kho chu trong vie c s dung cong tac
do pha i an co ng tac trong mot khoa ng thi gian u lau.
Vie c thay oi thi gian delay trong chng trnh co the c thc hie n n gia n
bang ca ch thay oi label cua chng trnh delay gan cho tham so SWdel. Thc ra ta co
the trc tiep a tham so thi gian delay trc tiep vao thanh ghi count1 ma khong can
thong qua tham so SWdel, ie u o lam cho chng trnh tr nen dai va phc tap hn.
Tuy nhie n chng trnh tren cu ng a cho ta tha y c mo t ie m kha c biet gia lenh
EQU va lenh SET, giup ta hie u ro hn va s dung mot ca ch thch hp cac lenh
tren trong ca c ng dung kha c.

4. MOT SO BAI TAP THAM KHAO S DUNG PIC16F877A,TRONG
TNG NG DUNG CU THE

Bai 1A : Dung pic 16F877A ieu khien 6 led 7
oan em giay, phut, gi, dung ngon ng
assembly

;Ten chuong trinh: dong ho so dung VDK Pic
16F877A
;*****************************************
TITLE " dong ho so dung PIC 16F877A"
PROCESSOR P16F877A
INCLUDE <P16F877A.inc>
__CONFIG _CP_OFF & _PWRTE_ON &
_WDT_OFF & _HS_OSC & _LVP_OFF
;*****************************************
;chuong trinh
;---------------------------------------------
;--------------- khai bao bien----------------
CBLOCK 0x020
COUNT1
COUNT2
COUNT3
GIAY_DV
GIAY_CHUC
PHUT_DV
PHUT_CHUC
GIO_DV
GIO_CHUC
BIEN_GIAY_DV
BIEN_GIAY_CHUC
BIEN_PHUT_DV
BIEN_PHUT_CHUC
BIEN_GIO_DV
BIEN_GIO_CHUC
ENDC
;***********************************
ORG 0x000
CLRF STATUS
MOVLW 0x00
MOVWF PCLATH
GOTO START
;*************************************
;---------------------------------------------------------
; KHOI TAO
*****************************************
;KHOI TAO PORT B DIEU KHIEN 6 TRANSISTOR QUET
HANG
;KHOI TAO PORT D KET NOI VOI 8 CHAN CUA LED 7
DOAN

START ORG 0x006
BCF STATUS,RP1
BSF STATUS,RP0 ; LUA CHON BANK
1
CLRF TRISB ; PORT B XUAT
DATA
CLRF TRISD ; PORT D XUAT
DATA
BCF STATUS,RP0 ; TRO VE BANK 0

;****************************************
;chuongtrinhchinh
;***************************************
;====KHOI TAO GIA TRI BAN DAU========
X7 MOVLW 0x00
MOVWF GIO_CHUC ;CHO GIO PHUT
GIAY = 0
X6 MOVLW 0x00
MOVWF GIO_DV
X5 MOVLW 0x00
MOVWF PHUT_CHUC
X4 MOVLW 0x00
MOVWF PHUT_DV
X3 MOVLW 0x00
MOVWF GIAY_CHUC
X2 MOVLW 0x00
MOVWF GIAY_DV

;=================================

X1 CALL BCD_7DOAN
CALL DELAY_HIEN_THI
;=================================

INCF GIAY_DV ;TANG GIAY_DV
MOVF GIAY_DV,0 ;NAP GIAY_DV VAO T G
W
XORLW D'10'
BTFSS STATUS,Z ;kiem tra bit Z va nhay
neu Z=1(bo qua lenh GOTO) co nghia la
giay don vi=10
GOTO X1

INCF GIAY_CHUC ;TANG GIAY_CHUC
MOVF GIAY_CHUC,0 ;NAP GIAY_CHUC VAO
TG W
XORLW D'6' ;SO SANH GIAY_CHUC VOI
6,Z=1 NEU GIAY_CHUC=6,NGUOC LAI Z=0
BTFSS STATUS,Z ;KIEM TRA Z,NHAY KHI Z=1
GOTO X2 ;VE X2 NEU Z=0

INCF PHUT_DV ;TANG PHUT_DV
MOVF PHUT_DV,0 ;NAP PHUT_DV VAO
TG W
XORLW D'10' ;SO SANH PHUT_DV VOI
10,Z=1 NEU GIAY_CHUC=10,NGUOC LAI Z=0
BTFSS STATUS,Z ;KIEM TRA Z,NHAY
KHI Z=1

INCF PHUT_CHUC ;TANG PHUT_CHUC
MOVF PHUT_CHUC,0 ;NAP PHUT_CHUC VAO
TG W
XORLW D'6' ;SO SANH PHUT_CHUC
VOI 6,Z=1 NEU GIAY_CHUC=6,NGUOC LAI Z=0
BTFSS STATUS,Z ;KIEM TRA Z,NHAY KHI
Z=1
;====================================
MOVF GIO_CHUC,0
XORLW D'2'
BTFSS STATUS,Z
GOTO X10
GOTO X11
X10 INCF GIO_DV
MOVF GIO_DV,0
XORLW D'10'
BTFSS STATUS,Z
GOTO X5
INCF GIO_CHUC
GOTO X6
X11 INCF GIO_DV
MOVF GIO_DV,0
XORLW D'4'
BTFSS STATUS,Z
GOTO X5
GOTO X7
;====================================
BCD_7DOAN
MOVF GIAY_DV,0 ;MOV (GIAY_DV)
VAO W
CALL TABLE
MOVWF BIEN_GIAY_DV ;MOV
(GIAY_DV) VAO BIEN_GIAY_DV

MOVF GIAY_CHUC,0 ;MOV
(GIAY_CHUC) VAO W
CALL TABLE
MOVWF BIEN_GIAY_CHUC ;MOV
(GIAY_CHUC) VAO BIEN_GIAY_CHUC

MOVF PHUT_DV,0 ;MOV (PHUT_DV) VAO
W
CALL TABLE
MOVWF BIEN_PHUT_DV ;MOV (PHUT_DV)VAO
BIEN PHUT_DV

MOVF PHUT_CHUC,0 ;MOV
(PHUT_CHUC) VAO W
CALL TABLE
MOVWF BIEN_PHUT_CHUC ;MOV
(PHUT_CHUC) VAO BIEN_PHUT_CHUC

MOVF GIO_DV,0 ;MOV (GIO_DV) VAO W
CALL TABLE
MOVWF BIEN_GIO_DV ;MOV (GIO_DV) VAO
BIEN_GIO_DV

MOVF GIO_CHUC,0 ;MOV (GIO_CHUC)
VAO W
CALL TABLE
MOVWF BIEN_GIO_CHUC ;MOV (GIO_CHUC)
VAO BIEN_GIO_CHUC

RETURN

;====================================
DELAY_HIEN_THI
MOVLW 0x2 ;NAP 01 VAO W
MOVWF COUNT1 ;MOV 01 VA0 COUNT1
DEL1
MOVLW 0x18 ;NAP 1 VAO W
MOVWF COUNT2 ;MOV 1 VAO COUNT2
DEL2
CALL HIENTHI
DECFSZ COUNT2 ;GIAM COUNT2,KHI
BANG 0 THI NHAY XUONG GIAM COUNT1
GOTO DEL2
DECFSZ COUNT1 ;GIAM COUNT1,KHI
BANG 0 THI BO QUA LENH KE
GOTO DEL1
RETURN

;====================================
=
HIENTHI
MOVF BIEN_GIAY_DV,0 ;HIEN THI GIAY-
DONVI
MOVWF PORTD
MOVLW 0x1
MOVWF PORTB
CALL DELAY
;===================================
MOVLW 0X00 ;CHONG LEM
MOVWF PORTB
MOVLW 0xff
MOVWF PORTD
;====================================
MOVF BIEN_GIAY_CHUC,0 ;HIEN THI
GIAY_CHUC
MOVWF PORTD
MOVLW 0x2
MOVWF PORTB
CALL DELAY

MOVLW 0X00
MOVWF PORTB
MOVLW 0xff
MOVWF PORTD

MOVF BIEN_PHUT_DV,0 ;HIEN THI PHUT-
DON VI
MOVWF PORTD
MOVLW 0x4
MOVWF PORTB
CALL DELAY

MOVLW 0X00
MOVWF PORTB
MOVLW 0XFF
MOVWF PORTD

MOVF BIEN_PHUT_CHUC,0 ;HIN THI
PHUT_CHUC
MOVWF PORTD
MOVLW 0x8
MOVWF PORTB
CALL DELAY

MOVLW 0X00
MOVWF PORTB
MOVLW 0XFF
MOVWF PORTD

MOVF BIEN_GIO_DV,0 ;HIEN THI
GIO_DONVI
MOVWF PORTD
MOVLW 0x10
MOVWF PORTB
CALL DELAY

MOVLW 0X00
MOVWF PORTB
MOVLW 0XFF
MOVWF PORTD

MOVF BIEN_GIO_CHUC,0 ;HIEN THI
GIO_CHUC
MOVWF PORTD
MOVLW 0x20
MOVWF PORTB
CALL DELAY

MOVLW 0X00
MOVWF PORTB
MOVLW 0XFF
MOVWF PORTD

RETURN
;====================================
DELAY
MOVLW 0xFF
MOVWF COUNT3
DELAY1
DECFSZ COUNT3
GOTO DELAY1
RETURN
;====================================
TABLE
ADDWF PCL,1
DT 0xC0, 0xF9, 0xA4, 0xB0, 0x99, 0x92, 0x82,
0xF8, 0x80, 0x90
END

Bai 1.C: Dung pic 16F877A ieu khien 6 led
7 oan em giay, phut, gi, dung ngon ng C.

chng trnh chnh


Chng trnh ngt

Ngt timer 0

CHNG TRNH
#include <16F877A.h>
#include<khaibaotghi_16f877a.h>
#fuses
NOWDT,PUT,XT,NOPROTECT,HS,NOLVP
#use fast_io(b)
#use fast_io(d)
#use fast_io(c)
#bit start=portb.1
#bit tphuc=portb.2
#bit gphuc=portb.3
#bit tgio=portb.4
#bit ggio=portb.5
int16 count;
int8
giay,phuc,gio,dvgiay,chgiay,dvphuc,chphuc,dvgio,
chgio,i;
const unsigned char
dig[]={0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,
0x80,0x90}
//ma 7 doan
void hex_bcd()
{chgiay=giay/10;
dvgiay=giay%10;
chphuc=phuc/10;
dvphuc=phuc%10;
chgio=gio/10;
dvgio=gio%10;}

void nhienthi()
{ i=0;
while(i<5)
{ output_high(pin_d0);
portc=dig[dvgiay];
delay_ms(1);
output_low(pin_d0);
output_high(pin_d1);
portc=dig[chgiay];
delay_ms(1);
output_low(pin_d1);

portc=dig[dvphuc];
delay_ms(1);
output_low(pin_d2);

portc=dig[chphuc];
delay_ms(1);
output_low(pin_d3);

portc=dig[dvgio];
delay_ms(1);
output_low(pin_d4);

portc=dig[chgio];
delay_ms(1);
output_low(pin_d5);
i=i+1; }}
#int_ext
void ngat_ngoai()
{ while (true)
{if (tphuc==0)
{phuc=phuc+1;
goto loop;
}
if (gphuc==0)
{phuc=phuc-1;
goto loop;
}
if (tgio==0)
{gio=gio+1;
goto loop;
}
if (ggio==0)
{ gio=gio-1;
goto loop; }
goto lap1;

loop:
if (phuc==60)
{phuc=0; }
if (phuc==-1)
{ phuc=59;}
if (gio==24)
{ gio=0; }
if (gio==-1)
{ gio=23;}
lap: nhienthi();
if (tphuc==0||gphuc==0||tgio==0||ggio==0)
{goto lap;}
lap1:
if (start==0)
{ break; }
hex_bcd();
nhienthi(); }}
//Chuong trinh ngat TMR0
#int_timer0
void interrupt_timer0()
{ set_timer0(6);
++count;
if(count ==500)
{count=0;
giay=giay+1; }}

void hienthi()
{ i=0;
while(i<5)
{output_high(pin_d0);
portc=dig[dvgiay];
delay_ms(1);
output_low(pin_d0);
portc=dig[chgiay];
delay_ms(1);
output_low(pin_d1);
portc=dig[dvphuc];
delay_ms(1);
output_low(pin_d2);
portc=dig[chphuc];
delay_ms(1);
output_low(pin_d3);
portc=dig[dvgio];
delay_ms(1);
output_low(pin_d4);
portc=dig[chgio];
delay_ms(1);
output_low(pin_d5);
i=i+1; }}
//Chuong trinh chinh
void main(void)
{ trisb=1;
trisd=0;
trisc=0;
intcon=0xb0;//ngat ngoai va ngat t0
enable_interrupts(int_timer0);//chopheptmr0

setup_timer_0(RTCC_INTERNAL|RTCC_DIV_2)
;
enable_interrupts(global);
giay =0;
phuc=0;
gio=0;
while(true){
if(giay==60)
{ giay=0;
phuc=phuc+1; }
if (phuc==60)
{phuc=0;
gio=gio+1;}
if (gio==24)
{ gio=0;}
hex_bcd();
hienthi();}}

Bai 2.A: ung pIc 16I877A dIou khIon 3
Iod 7 doan Iam ma ch dom san pham,
dung ngon ngu assombIy dung fImor0

LU

Chng trnh
title "dem san pham"
processor p16f877a
include <P16f877a.inc>
__CONFIG _WDT_OFF
;=================================
;Chuong trinh chinh
;=================================
;----------khai bao bien--------
dvi equ 0x20
chuc equ 0x21
tram equ 0x22
tam equ 0x23
bien1 equ 0x24
bien2 equ 0x25
bien3 equ 0x26
dem equ 0x27
;-------------------------------
org 0x000
goto start
;-------------------------------
;khoi tao Port va Timer0
;-------------------------------
start org 0x005
banksel TRISB
clrf TRISB
clrf TRISC
movlw b00101000
movwf OPTION_REG
banksel PORTB
;xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
clrf TMR0
movlw 0x00
movwf tam
lb4 movlw 0x00
movwf tram
lb3 movlw 0x00
movwf chuc
lb2 movlw 0x00
movwf dvi
lb1 call giaimahienthi
movf TMR0,0
xorwf tam,0
btfsc STATUS,Z
goto lb1
movf TMR0,0
movwf tam
incf dvi
movf dvi,0
xorlw d'10'
btfss STATUS,Z
goto lb1
incf chuc
movf chuc,0
xorlw d'10'
btfss STATUS,Z
goto lb2
incf tram
movf tram,0
xorlw d'10'
btfss STATUS,Z
goto lb3
goto lb4
;-------------------------------------------
;chuong trinh con giai ma hien thi
;-------------------------------------------
giaimahienthi
movf dvi,0
call table
movwf PORTB
movlw b'00000100'
movwf PORTC
call delay
clrf PORTC
call delay
movf chuc,0
call table
movwf PORTB
movlw b'00000010'
movwf PORTC
call delay
clrf PORTC
call delay
movf tram,0
call table
movwf PORTB
movlw b'00000001'
movwf PORTC
call delay
clrf PORTC
call delay
return
;---------------------------------------------
;chuong trinh con delay
;---------------------------------------------
delay
movlw 0xff
movwf dem
d1 decfsz dem
goto d1
return
;-------------------------------------------
;table
;-------------------------------------------
table addwf PCL,1
DT
0x40,0x79,0x24,0x30,0x19,0x12,0x02,0x78,0x
00,0x10
end
;$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
$$$$$$$$$$$$$$$$$$$$$$$$$$$$$

Bai 2.C:Dung pic 16F877A ieu khien 3 led
7 oan lam mach em san pham, dung ngon
ng C dung timer1.

LU

Chng trnh
#include <KhaiBaoTGhi_16F877A.h>
#fuses
NOWDT,PUT,HS,NOPROTECT,NOLVP
#use fast_io(b)
#use fast_io(d)
#byte dem=TMR1L
int8 tram,chuc=0,dv=0,ht=0;
const unsigned char
dig[]={0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0
xf8,0x80,0x90};
//xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
void khoitao()
{
trisb=0x0; //khoi tao portb & portd la ngo ra
trisd=0x0; //
T1CON=0X06; //chon bo chia 1:1,bo dao dong bat dong
bo
dem=0;tram=0;
}
void hienthi()
{
switc(ht)
{
case 0: portb=dig[dv];
portd=0x01;
delay_us(20);
portb=0xff;
break;
case 1: portb=dig[chuc];
portd=0x02;
delay_us(20);
portb=0xff;
break;
case 2: portb=dig[tram];
portd=0x04;
delay_us(20);
portb=0xff;
}
ht++;
if (ht==3) ht=0;
}

void main()
{
khoitao();
bit_set(T1CON,0);
while(1)
{
if (dem==100)
{
bit_clear(T1CON,0); //xoa bit TMR1ON de thay doi gia
tri TMR1L
dem=0;
tram=tram+1;
if (tram==10)
tram=0;
bit_set(T1CON,0);
}
chuc=dem/10;
dv=dem%10;
hienthi();
}
}

Bai 3.A:Dung pic 16F877A ieu khien 4 led
7 oan, 6 Led n lam mach ieu khien en
giao thong. Thi gian cho en xanh la 20
giay, vang 5 giay, o 25 giay, dung ngon ng
assembly dung timer1 lam bo nh thi.

I. Lu o
a. Chng trnh ngt

b. Chng trnh chnh

CHNG TRNH
processor P16f877a
_CONFIG _CP_OFF & _WDT_OFF &
_BODEN_OFF & _PWRTE_ON & _RC_OSC &
_WRT_OFF & _LVP_ON & _CPD_OFF
;================================
; KHAI BAO HANG VA BIEN
;================================
;Dinh nghia cac gia tri su dung hien thi trang thai
;den giao thong tren hai cot
DENGT EQU PORTB
XANH_1 EQU 0
VANG_1 EQU 1
DO_1 EQU 2
XANH_2 EQU 3
VANG_2 EQU 4
DO_2 EQU 5
;Khai bao cac hang su dung dieu khien thoi gian
hien thi
DATA_LED EQU PORTC
CONTROL_LED EQU PORTD
LED_DV_1 EQU 0x01
LED_CHUC_1 EQU 0x02
LED_DV_2 EQU 0x04
LED_CHUC_2 EQU 0x08
;Hang so kiem tra du 1 giay
DIV_1S EQU 0

;-----KHAI BAO BIEN------------
cblock 0x20
STATUS_TEMP
W_TEMP
TGCOT_1 ;Gia tri thoi gian dua ra 2
cot den
TGCOT_2
DV_COT1 ;Gia tri BCD cua so giay
CHUC_COT1
DV_COT2
CHUC_COT2
temp_1 ;Bien tam su dung trong
chuong
temp_2 ;trinh chuyen doi HEX sang BCD
MA_CHUC_1 ;Bien luu tru ma 7 doan cua
cac led
MA_DV_1
MA_CHUC_2
MA_DV_2

btam1 ;Bien tam su dung trong
btam2 ;chuong trinh phuc vu ngat
counter
THANHGHI_TAM;Thanh ghi de kiem tra
ngat lan 2
dem ;Bien dung cho chuong trinh delay
endc
;----------------------------------
;Tao MACRO luu va phuc hoi cac
;thanh ghi quan trong
PUSH MACRO
MOVWF W_TEMP
SWAPF STATUS,W
MOVWF STATUS_TEMP
ENDM

POP MACRO
SWAPF STATUS_TEMP,W
MOVWF STATUS
SWAPF W_TEMP,F
SWAPF W_TEMP,W
ENDM
;Ket thuc MACRO
;================================
; CHUONG TRINH NGAT
;================================
NGAT org 0x04
PUSH
BANKSEL PIR1

BTFSS PIR1, TMR1IF ;Kiem tra co ngat
GOTO exit_int ;Neu khong
phai ngat do timer1 thi thoat
BCF PIR1, TMR1IF ;Xoa co
ngat
BANKSEL TMR1H ;Khoi tao lai gia
tri timer
MOVLW high d'3036'
MOVWF TMR1H
MOVLW low d'3036'
MOVWF TMR1L

BTFSS THANHGHI_TAM, DIV_1S
GOTO notfull_1s
;Chuong trinh phuc vu ngat thuc
;hien cac trang thai cua den giao thong
;va gia tri thoi gian de dua ra hien thi
BCF THANHGHI_TAM,
DIV_1S
BANKSEL DENGT
CLRF DENGT

DECF counter, 1
MOVLW 0x00
XORWF counter, W
BTFSS STATUS, Z
GOTO X1_D2
;-------------------------
MOVLW d'50'
MOVWF counter
BSF DENGT, XANH_1
BSF DENGT, DO_2
MOVLW d'30'
MOVWF btam1
MOVLW d'25'
MOVWF btam2
CALL laythoigian
GOTO exit_int
;-------------------------
X1_D2
MOVLW d'30'
SUBWF counter, 0
BTFSS STATUS, C
GOTO V1_D2
BANKSEL DENGT
BSF DENGT, XANH_1
BSF DENGT, DO_2
MOVLW d'30'
MOVWF btam1
MOVLW d'25'
MOVWF btam2
CALL laythoigian
GOTO exit_int
;-------------------------
V1_D2
MOVLW d'25'
SUBWF counter, W
BTFSS STATUS, C
GOTO D1_X2
BANKSEL DENGT
BSF DENGT, VANG_1
BSF DENGT, DO_2
MOVLW d'25'
MOVWF btam1
MOVLW d'25'
MOVWF btam2
CALL laythoigian
GOTO exit_int
;-------------------------
D1_X2
MOVLW d'5'
SUBWF counter, W
BTFSS STATUS, C
GOTO D1_V2
BANKSEL DENGT
BSF DENGT, DO_1
BSF DENGT, XANH_2
MOVLW d'0'
MOVWF btam1
MOVLW d'5'
MOVWF btam2
CALL laythoigian
GOTO exit_int
;-------------------------
D1_V2
BANKSEL DENGT
BSF DENGT, DO_1
BSF DENGT, VANG_2
MOVLW d'0'
MOVWF btam1
MOVLW d'0'
MOVWF btam2
CALL laythoigian

notfull_1s
BSF THANHGHI_TAM, DIV_1S
exit_int
POP
RETFIE
;==KET THUC CHUONG TRINH NGAT===

;----------------------------------
; CHUONG TRINH LAY THOI GIAN
;----------------------------------
laythoigian
MOVF btam1, W
SUBWF counter, W
MOVWF TGCOT_1
MOVF btam2, W
SUBWF counter, W
MOVWF TGCOT_2
RETURN
;================================
; CHUONG TRINH CHINH
;================================
org 0x000
goto main

;CHUONG TRINH BAT DAU O DAY
Chuongtrinhchinh
org 0x090
main
BANKSEL TRISC
CLRF TRISB
CLRF TRISC
CLRF TRISD
BCF STATUS, RP0 ;chon
bank 0
BCF STATUS, RP1
MOVLW d'50'
MOVWF counter
CALL khoitaotimer1
loop
CALL hex_bcd_1 ;Giai ma TGCOT_1
sang BCD
CALL hex_bcd_2 ;Giai ma TGCOT_2
sang BCD
CALL bcd_7doan
CALL hienthi
GOTO loop
;====================================
; KHOI TAO TIMER 1
;====================================
khoitaotimer1
CLRF T1CON
CLRF INTCON
CLRF TMR1H
CLRF TMR1L
BSF STATUS, RP0 ;chon bank 1
CLRF PIE1
BSF PIE1,TMR1IE ;cho phep ngat
timer 1
BCF STATUS, RP0 ;chon bank 0
CLRF PIR1 ;xoa cac co ngat
MOVLW 0xC0;cho phep ngat toan cuc va
MOVWF INTCON;ngat ngoai vi
MOVLW 0x30
MOVWF T1CON ;0011 0000:
Timer1 su dung Fosc/4,;PSA 1:8
BANKSEL TMR1H
MOVLW high d'3036'
MOVWF TMR1H
MOVLW low d'3036'
MOVWF TMR1L
BSF T1CON, TMR1ON
RETURN
;====KET THUC KHOI TAO TIMER 1====
;CTRINH CHUYEN DOI HEX SANG BCD
;================================
;CHUYEN DOI O COT 1
hex_bcd_1
BCF STATUS, RP0
CLRF DV_COT1
CLRF CHUC_COT1
MOVF TGCOT_1, W
MOVWF temp_1
BCD1
MOVLW .10
SUBWF temp_1, W
BTFSS STATUS, C
GOTO BCD2
INCF CHUC_COT1
MOVLW .10
SUBWF temp_1, F
;temp_1 = temp_1 - 10
GOTO BCD1
BCD2
MOVF temp_1, W
MOVWF DV_COT1
RETURN
;CHUYEN DOI O COT 2
hex_bcd_2
BCF STATUS, RP0
CLRF DV_COT2
CLRF CHUC_COT2
MOVF TGCOT_2, W
MOVWF temp_2
BCD3
MOVLW .10
SUBWF temp_2, W
BTFSS STATUS, C
GOTO BCD4
INCF CHUC_COT2
MOVLW .10
SUBWF temp_2, F
;temp_2 = temp_2 - 10
GOTO BCD3
BCD4
MOVF temp_2, W
MOVWF DV_COT2
RETURN
;===KET THUC HEX SANG BCD=======
;=================================
;C TR CHUYEN DOI BCD SANG LED 7 DOAN
;====================================
bcd_7doan
;Lay ma 7 doan cho led hien thi hang chuc cot 1
MOVF CHUC_COT1, 0
CALL table
MOVWF MA_CHUC_1
;Lay ma 7 doan cho led hien thi hang don vi cot 1
MOVF DV_COT1, 0
CALL table
MOVWF MA_DV_1
;Lay ma 7 doan cho led hien thi hang chuc cot 2
MOVF CHUC_COT2, 0
CALL table
MOVWF MA_CHUC_2
;Lay ma 7 doan cho led hien thi hang don vi cot 2
MOVF DV_COT2, 0
CALL table
MOVWF MA_DV_2
RETURN
;-------------------------------------
;BANG LAY MA LED 7 DOAN
;-------------------------------------
table ADDWF PCL, F
RETLW 0XC0 ;0
RETLW 0XF9 ;1
RETLW 0XA4 ;2
RETLW 0XB0 ;3
RETLW 0X99 ;4
RETLW 0X92 ;5
RETLW 0X82 ;6
RETLW 0XF8 ;7
RETLW 0X80 ;8
RETLW 0X90 ;9
;-------------------------------------
;==KET THUC BCD SANG 7 DOAN===
;====================================
;CT QUET LED 7 DOAN HIEN THI
;====================================
hienthi
MOVF MA_DV_1, 0
MOVWF DATA_LED
MOVLW LED_DV_1
MOVWF CONTROL_LED
CALL delay
CLRF CONTROL_LED
CALL delay

MOVF MA_CHUC_1, 0
MOVWF DATA_LED
MOVLW LED_CHUC_1
MOVWF CONTROL_LED
CALL delay
CLRF CONTROL_LED
CALL delay

MOVF MA_DV_2, 0
MOVWF DATA_LED
MOVLW LED_DV_2
MOVWF CONTROL_LED
CALL delay
CLRF CONTROL_LED
CALL delay

MOVF MA_CHUC_2, 0
MOVWF DATA_LED
MOVLW LED_CHUC_2
MOVWF CONTROL_LED
CALL delay
CLRF CONTROL_LED
CALL delay
RETURN
;===KET THUC HIEN THI=======
;---------------------------------
; CHUONG TRINH DELAY
;---------------------------------
delay
MOVLW 0xFF
MOVWF dem
del DECFSZ dem
GOTO del
RETURN

END
;=====KET THUC CHUONG TRINH=====

Bai 3.C: Dung pic 16F877A ieu khien 4 led
7 oan, 6 Led n lam mach ieu khien en
giao thong. Thi gian cho en xanh la 20
giay, vang 5 giay, o 25 giay, timer1, dung
ngon ng C.
THEO PHNG PHAP QUET LED

CHNG TRNH CHNH


CHNG TRNH NGT:

CHNG TRNH:
#include <16f877a.h>
#fuses nowdt, put, hs, noprotect, nolvp
#use delay (clock=20000000)
#use fast_io(b)
#use fast_io(d)
int8 j,k,chuc1,chuc2,dvi1,dvi2;
int16 t_do,a,t_xanh,b;
const unsigned char
dig[]={0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,
0x80,0x90};
#INT_TIMER1
VOID NGAT() // bat dau chuong trinh ngat
{ J++;
IF(J==10) // khi j=10 thi thoi gian dung 1s
{ k=k+1; // bien k dung de xac dinh thoi gian
cho cot 1
if((k<26)&&(k>0))
{ a=t_do;
t_do=t_do-1;
b=t_xanh;
t_xanh=t_xanh-1;
if(a<5) // thoi gian hien thi cho led vang
{ portc=0x22; // Den v2 va d1 sang
b=a;
}
else
portc=0x21; // den x2 va den d1 sang
}
if((k<26)&&(k>24)) // khi du 25s thi chuyen
sang cot 2
{ t_do=24;
t_xanh=19;
}
if(k>25) // bat dau hien thi cho cot 2
{ b=t_do;
t_do=t_do-1;
a=t_xanh;
t_xanh=t_xanh-1;
if (b<5) // khi den xanh du 20s thi den
vang bat dau sang
{ portc=0x14; // den do 2 va den vang 1
sang
a=b;
}
else
portc=0x0c; // den do 2 va den xanh 1
sang
}
chuc1=a/10;
dvi1=a%10;
chuc2=b/10;
dvi2=b%10;

if(k>49)// khi cot 2xong 25s thi chuyen ve cot 1
{ k=0; // khoi tao lai gia tri dem ban dau
t_do=24;
t_xanh=19;
}
SET_TIMER1(3035); // cai lai thoi gian cho
timer1
j=0;
}
SET_TIMER1(3035); // cai lai thoi gian cho
timer1
}

void main() // bat dau chuong trinh
chinh
{ set_tris_b(0x00); // khoi tao cho port b,c,d
la ngo ra
set_tris_d(0x00);
set_tris_c(0x00);
j=0; // khoi tao cho bien dem timer1
k=0; // khoi tao cho bien dem cua
tung cot
t_do=24; // gan gia tri ban dau cho den do
va xanh
t_xanh=19;
SET_TIMER1(3035); //dat so dem cho
timer1
T1CON=0x35; //khoi tao gia tri cho
timer
enable_interrupts(INT_TIMER1); //tran thi
ngat
enable_interrupts(global); //cho phep ngat
timer1
WHILE(TRUE)
{ portb=dig[chuc1]; //dua gia tri chuc1 ra
portb
portd=0xf8; //chi led o vi tri chuc1 la sang
delay_ms(8); //dung de nhin thay duoc led
sang
portd=0xf0; //chong lem

portb=dig[dvi1]; //dua gia tri dvi1 ra portb
portd=0xf4; //chi led o vi tri dvi1 la sang
delay_ms(8);
portd=0xf0;

portb=dig[chuc2]; //dua gia tri chuc2 ra
portb
portd=0xf2; //chi led o vi tri chuc2
la sang
delay_ms(8);
portd=0xf0;

portb=dig[dvi2]; //dua gia tri dvi2 ra
portb
portd=0xf1; //chi led o vi tri dvi2 la
sang
delay_ms(8);
portd=0xf0;
}
}

Bai 4.A: Dung pic 16F877A giao tiep LCD
16x2 lam mach em san pham, dung ngon
ng assembly dung timer1

LU CHNH

KHI TO COUNTER

KHI TO LCD


HIN TH DONG 1:

HIN TH DONG 2:

GII MA HEX => BCD:

CHNG TRNH:
title "DIEM SAN PHAM HIEN THI LCD"
processor p16f877a
__CONFIG_CP_OFF&_WDT_OFF&_LVP_OFF&
_PWRTE_ON&_HS_OSC&_BODEN_OFF&_CP
D_OFF
;**************************************
;KHOI TAO CAC BIEN
;**************************************
COUNT1 EQU 0x20
COUNT2 EQU 0x21
COUNT3 EQU 0x22
COUNT EQU 0x23
A EQU 0x24
TAM EQU 0x25
TR EQU 0x26
CH EQU 0x27
DV EQU 0x28
NG EQU 0x29
;*********************************
ORG 0x000
CLRF STATUS
MOVLW 0x00
MOVWF PCLATH
GOTO START
;*************************************
;KHOI TAO PORTD,PORTB
;*************************************
ORG 0x005
START BCF STATUS,RP1
BSF STATUS,RP0
CLRF TRISB
CLRF TRISD

;************************************
;VONG LAP CHUONG TRINH CHINH
;************************************
MAIN
CALL KTCOUNTER1
CALL KHOITAOLCD
MOVLW D'0'
MOVWF NG
MOVLW D'0'
MOVWF TR
MOVLW D'0'
MOVWF CH
MOVLW D'0'
MOVWF DV
CALL DONG1

LOOP CALL
HEXTOBCD
CALL DONG2
GOTO LOOP
;*****************************************
KTCOUNTER1
BCF
STATUS,RP1
BCF
STATUS,RP0 ;CHON BANK 0
MOVLW
B'00000010' ;KHOI TAO COUNTER
MOVWF
T1CON
CLRF TMR1H
;XOA 8 BIT CAO
CLRF TMR1L
;XOA 8 BIT THAP
BSF
T1CON,TMR1ON ;cho couter bt dau
dem khi co xung
RETURN
;*****************************************
KHOITAOLCD
MOVLW 0X38
;Khoi tao hang 2 matrix 5x8.
MOVWF A
CALL GHIMADK
CALL DELAY40mS

MOVLW 0X0C
;Bat man hinh LCD.
MOVWF A
CALL GHIMADK
CALL DELAY40mS

MOVLW 0X01
;Xoa man hinh va dua con tro ve dau dong
thu 1.
MOVWF A
CALL GHIMADK
CALL DELAY40mS
RETURN
;*****************************************
*******
HEXTOBCD

MOVF TMR1L,0
; copy noi dung TMR1L vao w
MOVWF TAM
;copy noi dung w vao TAM
MOVLW D'10'
;w=10
XORWF TAM,0
BTFSS STATUS,Z
;nhay neu z=1<=> kq=0
GOTO X1
CLRF TMR1L
INCF CH
MOVLW D'10'
XORWF CH,0
BTFSS STATUS,Z
;nhay neu z=1<=> kp=0 (CH=10)
GOTO X2

INCF TR
CLRF CH
MOVLW D'10'
XORWF TR,0
BTFSS STATUS,Z
GOTO X1

INCF NG
CLRF TR
MOVLW D'10'
XORWF NG,0
BTFSS STATUS,Z
GOTO X2
CLRF NG
GOTO X2
X1 MOVF TMR1L,0
MOVWF DV

X2 RETURN

;*****************************************
*******
GHIMADK MOVF A,0

;dk LCD hoat dong
MOVWF PORTB
BCF PORTD,0
BCF PORTD,1
BSF PORTD,2
BCF PORTD,2
RETURN
;*****************************************
*******
DONG1

MOVLW 0X01
;Xoa man hinh va dua con tro ve dau dong
thu 1.
MOVWF A
CALL GHIMADK
CALL DELAY

MOVLW 0X80
;hien thi dong 1" SO san pham la"
MOVWF A
CALL GHIMADK
CALL DELAY

CLRF COUNT
DONG11 MOVF COUNT,0
CALL TABLE
MOVWF A
CALL GHIDATA
CALL DELAY
INCF COUNT,0
XORLW D'16'
BTFSS STATUS,Z
GOTO LB1
RETURN
LB1 INCF COUNT,1
GOTO DONG11
;*****************************************
*****
DONG2
MOVLW 0XC5
;DUA CON TRO HANG 5 CUA DONG 2
MOVWF A
CALL GHIMADK
CALL DELAY
MOVF NG,0
MOVWF A
MOVLW B'00110000'
;giai ma ra LCD
ADDWF A,1
CALL GHIDATA
CALL DELAY

MOVF TR,0
MOVWF A
MOVLW B'00110000'
;giai ma ra LCD
ADDWF A,1
CALL GHIDATA
CALL DELAY

MOVF CH,0
MOVWF A
MOVLW B'00110000';giai ma ra LCD
ADDWF A,1
CALL GHIDATA
CALL DELAY

MOVF DV,0
MOVWF A
MOVLW B'00110000'
ADDWF A,1
CALL GHIDATA
CALL DELAY

RETURN
;*****************************************
*******
GHIDATA
MOVF A,0
;chuong trinh hien thi LCD
MOVWF PORTB
BSF PORTD,0;RS
BCF PORTD,1;RW
BSF PORTD,2 ;E
BCF PORTD,2
RETURN

;*************************************
DELAY40mS MOVLW
D'255' ;delay 40ms(tan so 20MHz)
MOVWF
COUNT1
DEL1 MOVLW 0xFF
MOVWF COUNT2
DEL2 DECFSZ COUNT2
GOTO DEL2
DECFSZ COUNT1
GOTO DEL1
RETURN

;************************************

DELAY MOVLW D'255'
MOVWF COUNT3
LB DECFSZ COUNT3
GOTO LB
RETURN
;*****************************************
*******
TABLE ADDWF PCL,1

DT " SO SAN PHAM
LA:"
END
;***********************************
;KET THUC CHUONG TRINH
;***********************************

Bai 4.C: Dung pic 16F877A giao tiep LCD
16x2 lam mach em san pham, dung ngon
ng C dung timer0

LU

LU XUT LCD:

LU XUT M LNH RA LCD:

Chng trnh
//==============================
// Title : Dem san pham dung Timer 0 hien thi
LCD 16x2
// Hardware : PIC 16F877A
// Complier : CCS C
//==============================
#include <def_16f877a.h>
#use delay( clock=20000000 )

//------------Define signals------------------------

#define RS RD0 //Ket noi chan RS cua LCD voi chan
RD0 cua PIC
#define RW RD1 //Ket noi chan RW cua LCD voi chan
RD1 cua PIC
#define E RD2 //Ket noi chan E cua LCD voi chan
RD2 cua PIC
#define LCD PORTB //Ket noi LCD voi chan RB0-RB7
cua PIC

void cmd_lcd( int8 command ) ;
void data_lcd( int8 data ) ;
Void convert(int16 value) ;

int8 value ;
int8 donvi,chuc,tram,ngan ;
int16 solan,hienthi ;

//===================================
//------------ Sub-Program -----------------------------
//===================================

//Chuong trinh con gui command toi LCD
void cmd_lcd( int8 command )
{
RS = 0 ; //Bus se ket noi voi thanh ghi lenh IR de nhan
lenh
RW = 0 ; //LCD o che do ghi
LCD = command ;

E = 1 ; //Tao ra xung high-to-low o che do ghi
E = 0 ;

delay_ms( 10 ) ;
}
//Chuong trinh con gui du lieu hien thi len LCD
void data_lcd( int8 data )
{
RS = 1 ; //Bus se ket noi voi thanh ghi du lieu DR
RW = 0 ; //LCD o che do ghi

LCD = data ;

E = 1 ; //Tao ra xung high-to-low o che do ghi
E = 0 ;

delay_ms( 10 ) ;
}
//Chuong trinh con chuyen doi gia tri
thanh ky tu hien thi LCD
Void convert(int16 hienthi)
{

Int16 temp ;
temp = hienthi ; // Gan bien temp cho gia tri trong thanh
ghi TMR0
ngan = temp / 1000 + 0x30 ;
temp = temp % 1000 ;
tram = temp / 100 + 0x30 ;
temp = temp % 100 ;
chuc = temp / 10 + 0x30 ;
donvi = temp % 10 + 0x30 ;
}

//====================================
//-------------------Main program--------------------
//====================================

Void main()
{
//================================
// Khoi tao Timer0
//================================

Set_timer0(0) ;
//setup_timer_0(RTCC_EXT_L_TO_H) ;
//Chon bit canh ln trn chn RA4
T0CS = 1 ; //Cho phep nhan xung o chan T0CKI
T0SE = 0 ; //Cho phep xung vao chan T0CKI tich cuc
canh len
TMR0IE = 0 ; //Khong cho phep ngat T0
delay_ms(10) ;
//========================
// Khoi tao LCD
//=========================
TRISB = 0 ;
TRISD = 0 ;
delay_ms( 15 ) ; //Cho cho den khi nguon cua LCD
dat 4.5v
cmd_lcd( 0x0C ) ;
//LCD hien thi, khong hien thi con tro,
con tro khong nhap nhay.
cmd_lcd( 0x38 ) ; //LCD su dung Bus 8bit,hien thi 2
hang
cmd_lcd( 0x01 ) ; //Xoa man hinh LCD
cmd_lcd( 0x06 ) ; // Noi dung khong dich chuyen

//#####################################
cmd_lcd( 0x01 ) ;
cmd_lcd( 0x80 ) ; //Con tro o dau dong 1
printf(data_lcd,"Group 8 - Hello!");

delay_ms( 1000 ) ;

cmd_lcd( 0x01 ) ;
cmd_lcd( 0x80 ) ;
printf(data_lcd,"Member:");

delay_ms( 1000 ) ;

cmd_lcd( 0x01 ) ;
cmd_lcd( 0x80 ) ;
printf(data_lcd,"Xuan Len");

delay_ms( 1000 ) ;

cmd_lcd( 0x01 ) ;
cmd_lcd( 0x80 ) ;
printf(data_lcd,"Huynh Nhu");

delay_ms( 1000 ) ;

cmd_lcd( 0x01 ) ;
cmd_lcd( 0x80 ) ;
printf(data_lcd,"Thanh Thuy");

delay_ms( 1000 ) ;

cmd_lcd( 0x01 ) ;
cmd_lcd( 0x80 ) ;
printf(data_lcd,"Minh Quang");

delay_ms( 1000 ) ;
cmd_lcd( 0x01 ) ;

cmd_lcd( 0x80 ) ;
printf(data_lcd,"The Bao");

delay_ms( 1000 ) ;

cmd_lcd( 0x01 ) ;
cmd_lcd( 0x80 ) ;
printf(data_lcd,"Start Counter");

delay_ms( 500 ) ;

cmd_lcd( 0xC0 ) ; //Contro o dau dong 2
printf(data_lcd," So SP= ") ;

Set_timer0(0) ; //Gia tri cua TMR0 = 0

While (1)
{
cmd_lcd( 0xC0 + 0x07 ) ; //Cho con tro nhay toi vi tri
can hien thi

value = get_timer0() ; //Dua gia tri trong TMR0 vao
bien Value

if(value == 100)
{ solan++ ;
set_timer0(0) ;
value=0 ;
}
hienthi=solan*100+value;
if(hienthi==1000)
{ solan=0 ;
Set_timer0(0) ;
hienthi=0 ;
}
convert(hienthi) ;
data_lcd(ngan) ;
data_lcd(tram) ;
data_lcd(chuc) ;
data_lcd(donvi) ;

}
}

bai 5.A: Dung pic 16F877A giao tiep vi 3
led 7 oan va cam bien nhiet o LM35 noi
ngo vao kenh th 0, lap trnh o nhiet o
dung ngon ng assembly.

LU


CHNG TRNH
title "chuong trinh hien thi nhiet do"
processor p16f877a
__CONFIG
_CP_OFF&_PWRTE_ON&_WDT_OFF&_HS_OS
C&_LVP_OFF

;++++++++++++++++++++++++++++++++++++
; cac bien duoc su dung
;++++++++++++++++++++++++++++++++++++
cblock 0x020
count1
count2
count3
tram
chuc
dvi
tam
tam2
bien1
bien2
bien3
so55
dem
kqADC
endc
;---------- CT ----------
org 0x005
goto start
;--------- khoi tao port b,d ---------
start
bcf STATUS,RP1
bsf STATUS,RP0 ; chon bank 1
clrf TRISB
clrf TRISD ; lam ngo xuat du lieu

;---------- khoi tao ngo vao ADC ----------
ADC
movlw 0x0F
movwf ADCON1 ;chon AN2=Vref- va
AN3=Vref+
bcf STATUS,RP0 ; tro ve bank 0
;---------- MAIN ---------
main
movlw 0x01
call docADC
movwf kqADC
call chuyen
call bcd_7seg
call delhthi
goto main
;---- doc ADC dung bit GO/DONE --------
docADC
movwf ADCON0
movlw 0x14
movwf dem
delay12
decfsz dem,1
goto delay12
bsf ADCON0,2
gone btfsc ADCON0,2
goto gone
movf ADRESL,0
return
;---------doi ---------
chuyen bcf STATUS,C
movlw 0x37
subwf kqADC,0
Btfss STATUS,C ;neu phep tru kq duong C=1 va
nguoc lai
goto x4 ;ADC < 55 nhay den x4 de
tao dau "-"
movwf tam2
Movlw 0x00
Movwf tam
Movlw 0x00
Movwf tram
goto X3
x4
Movlw 0x00
Movwf tam
movlw 0x37
movwf so55
movf kqADC,0
subwf so55,0
movwf tam2
movlw 0x0a
movwf tram
X3
Movlw 0x00
Movwf chuc
X2 Movlw 0x00
Movwf dvi
X1
Movf tam,0
Xorwf tam2,0
Btfss STATUS,Z
Goto X5
Goto X6
X5
Incf tam,1
Incf dvi,1
Movf dvi,0
Xorlw 0x0A
Btfss STATUS,Z
Goto X1

Incf chuc,1
Movf chuc,0
Xorlw 0x0A
Btfss STATUS,Z
Goto X2

Incf tram,1
Movf tram,0
Xorlw 0x0A
Btfss STATUS,Z
Goto X3
X6 return
;--------- bcd_7seg -----------
bcd_7seg
movf dvi,0
call table
movwf bien1
movf chuc,0
call table
movwf bien2
movf tram,0
call table
movwf bien3
;---------- del_hthi -----------
delhthi
movlw 0x01
movwf count1
del1
movlw 0x10
movwf count2
del2
call hthi
decfsz count2,1
goto del2
ecfsz count1,1
goto del1
return
;---------- hien thi ----------
hthi
Movlw 0xC6
Movwf PORTB
Movlw 0x01
Movwf PORTD
Call delay
Movlw 0xff
Movwf PORTB

movf bien1,0
movwf PORTB
movlw 0x02
movwf PORTD
call delay
movlw 0xff
movwf PORTB

movf bien2,0
movwf PORTB
movlw 0x04
movwf PORTD
call delay
movlw 0xff
movwf PORTB

movf bien3,0
movwf PORTB
movlw 0x08
movwf PORTD
call delay
movlw 0xff
movwf PORTB
return
;--------- delay ---------
delay
movlw 0x20
movwf count3
del3
decfsz count3
goto del3
return
;--------- table ----------
table
addwf PCL,1
DT
0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0
x90,0xbf
end

bai 5.C: Dung pic 16F877A giao tiep vi 3
led 7 oan va cam bien nhiet o LM35 noi
ngo vao kenh th 0, lap trnh o nhiet o
dung ngon ng C

LU :
LU REAL ADC

LU HEX TO BCD:

LU CHUONG TRNH CHNH:

CHNG TRNH
#include <16F877a.h>
#fuses NOWDT,PUT,HS,NOPROTECT,NOLVP
#device ADC=8
#use fast_io(d)
#use fast_io(b)
int8 i,tram,chuc,donvi;
signed int16 tam,doc;
const unsigned char
tra[]={0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,
0x80,0x90,0xbf,0xff,0xc6};

void hex_bcd() //chuyen doi so hex sang so bcd

{
tram=tam/100;
tam=tam%100;
chuc=tam/10;
donvi=tam%10;
}
void hienthi()
{
i=0;
while(i<200)
{
portb=tra[chuc];//xuat hang chuc ra port
portd=0x02;
delay_us(5);
portd=0x00;

portb=tra[donvi];//xuat hang don vi
portd=0x04;
delay_us(5);
portd=0x00;

portb=tra[12];// xuat do c
portd=0x08;
delay_us(5);
portd=0x00;

if (doc<55)
{
portb=tra[10];//xuat dau am port
portd=0x01;
delay_us(5);
portd=0x00;
}

else if (doc<155)

{
portb=tra[11]; //xoa so 0 vo nghia
portd=0x01 ;

}
else
{
portb=tra[tram]; // xuat hang tram
portd=0x01;
delay_us(5);
portd=0x00;
}

i++;
}
}

void main()

{

set_tris_d(0x00); //thiet lap xuat cho port d
set_tris_b(0x00); //thiet lap xuat cho port b

setup_adc(adc_clock_internal); //thoi gian lay mau
bang xung clock IC(2-6us)

setup_adc_ports(an0_an1_vss_vref); //A0 A1
VRef+=A3,VRef-=0

set_adc_channel(0); //chon chan 0 doc tin hieu analog
delay_us(10); //delay 10us roi moi dung ham read_ADC
dam bao ket qua dung
while(1)
{
doc=read_adc();
tam=abs(doc-55);
hex_bcd();
hienthi();}
}

bai 6.A: Khao sat truyen d lieu SPI.

LU

Chng trnh
CHNG TRNH CA MASTER
list p=16F877A
#include "p16F877A.inc"
__CONFIG _CP_OFF & _DEBUG_OFF &
_WRT_OFF& _CPD_OFF& _LVP_OFF&
_BODEN_OFF& _PWRTE_ON& _WDT_OFF&
_XT_OSC
Ctr0 EQU 0x20 ; Bien dem gui du lieu den spi
Dly0 EQU 0x21 ; Bien delay 0
Dly1 EQU 0x22 ; Bien delay 1
#define SS PORTA,2 ; Gan chan chon slave (RA2)
ORG 0x000 ;

;xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
; Khoi tao ho tro SPI
BANKSEL TRISA ; Chon bank 1
movlw 0x00 ; Khoi tao port A
movwf TRISA ; Xuat port A
movlw 0x06 ; Tat che do A/D (tuong tu)(trg 92)
movwf ADCON1 ; cho phep port A su dung nhu la
port xuat nhap so

; Khoi tao SPI
BANKSEL TRISC ; Chon bank 1
movlw b'00010000' ; SCK chan ra xung (Master),SDI
chan nhan data
movwf TRISC ; SDO chan ra data
movlw b'01000000' ; du lieu dc lay mau tai thoi diem giua
xung clock
movwf SSPSTAT ; du lieu dc lay mau tai thoi diem
giua xung clock
BANKSEL SSPCON ; Chon bank 0
movlw b'00110001' ; 0001 SPI master mode,tan so
xung clock bang
;Fosc /16
movwf SSPCON ; bat che do SSP
Send_DT bcf SS ; Ngo ra cho phep lua chon chip
(muc thap)
movf Ctr0,W ; lay gia tri cua bien dem gan vao
t.ghi W
movwf SSPBUF ; W => SSPBUF
BANKSEL SSPSTAT ; Chon bank 1
Char1 btfss SSPSTAT,BF ; kiem tra da truyen
xong chua?
Goto Char1 ; nhay lai kiem tra tai nhan char1
neu chua truyen xong
BANKSEL SSPBUF ; Chon bank 0
movf SSPBUF,W ; doc data tu t.ghi SSPBUF =>W
; du lieu nay ko dc dung
bsf SS ; ngat ngo ra lua chon slave (muc cao la
xoa)
incf Ctr0,F ; tang bien dem

Delay movlw 0xF0 ;
movwf Dly1 ;
movlw 0x0F ;
movwf Dly0
DlyLoop decfsz Dly0,F ;
Goto DlyLoop ;
Decfsz Dly1,F ;
goto DlyLoop ;

goto Send_DT ; quay lai gui data tiep theo (byte)
END

Chng trnh cua slave
list p=16F877A
#include "p16F877A.inc"
__CONFIG _CP_OFF & _DEBUG_OFF &
_WRT_OFF & _CPD_OFF& _LVP_OFF &
_BODEN_OFF & _PWRTE_ON &
_WDT_OFF & _XT_OSC
ORG 0 ;
; Khoi tao ho tro SPI
BANKSEL TRISA ; Chon bank 1
movlw D'5' ; (trg 74)
movwf TRISA ; cho phep chan SS nhan du lieu
movlw 0x06 ; Tat che do A/D
movwf ADCON1 ; cho phep port A su dung
nhu la port xuat nhap so

; khoi tao port ngo ra
BANKSEL TRISB ;
movlw 0x00 ; khoi tao port B la port xuat
movwf TRISB ;

; khoi tao SPI
BANKSEL TRISC ; Chon bank 1
movlw B'00011000' ; SCK la ngo vao xung
clock (Slave), SDI ngo vao ;du lieu
movwf TRISC ; SDO la ngo ra du lieu (b.gom
cac ngo con lai cua port C)
movlw B'01000000' ; du lieu dc lay mau tai
thoi diem giua xung clock
movwf SSPSTAT ; du lieu dc lay mau tai thoi
diem giua xung clock
BANKSEL SSPCON ; Chon bank 0
movlw B'00110100' ; 0100 Mode 1,1 SPI Slave
Mode,
movwf SSPCON ; bat che do SSP
KT movlw SSPSTAT ; Kiem tra gian tiep
movwf FSR ; W=>FSR (trg 63)
btfss INDF,BF ; kiem tra bit BF trong t.ghi
INDF (trg 63)
goto KT ;
RX_Data
BANKSEL SSPBUF ; chon bank 0
movf SSPBUF,W ; SSPBUF=>W
BANKSEL PORTB ; chon bank 0
movwf PORTB ; Xuat du lieu ra port B

goto KT ; quay lai nhan byte tiep theo
END

Bai 7.A: Khao sat truyen d lieu USART.
ASSEMBLY

CHNG TRNH TRUYN PIC A

CHNG TRNH NHN PIC B


CHNG TRNH

Chng trnh truyen
title "TRUYEN USART"
processor p16f877a
__CONFIG
_CP_OFF&_WDT_OFF&_LVP_OFF&_P
WRTE_ON&_HS_OSC&_BODEN_OFF&_CPD_
OFF
;**************************************
;KHAI BAO CAC HANG SO
;**************************************
SW1 EQU 0
SW2 EQU 1
SW3 EQU 2
SW4 EQU 3
LED1 EQU 4
LED2 EQU 5
LED3 EQU 6
LED4 EQU 7
;**************************************
;KHAI BAO BIEN
;**************************************
COUNT EQU 0x20
COUNT1 EQU 0x21
COUNTa EQU 0x22
COUNTb EQU 0x23
;**************************************
;CHUONG TRINH CHINH
;**************************************
ORG 0x000
GOTO Start
Start
bcf STATUS,RP1
bsf STATUS,RP0 ; Chon bank 1
clrf PORTB
clrf PORTD
bsf STATUS,RP0 ;chon bank 0
movlw B'00001111'
movwf TRISB
movlw 0x00
movwf TRISD
call khoitaousart
bcf STATUS,RP0 ; Chon bank 0
Loop1
clrf COUNT
call CHECK_KEY
Loop2
movf COUNT,W
btfsc PORTB,LED1
call TABLE1

btfsc PORTB,LED2
call TABLE2

btfsc PORTB,LED3
call TABLE3

btfsc PORTB,LED4
call TABLE4
movwf PORTD
call transmitAtoB
call DELAY
incf COUNT,0
xorlw D'8'
btfsc STATUS,Z
goto Loop1

incf COUNT,1
goto Loop2
;**************************************
;SANG TU PHAI SANG TRAI
;**************************************
TABLE1
addwf PCL,F
retlw b'10000000'
retlw b'11000000'
retlw b'11100000'
retlw b'11110000'
retlw b'11111000'
retlw b'11111100'
retlw b'11111110'
retlw b'11111111'
;**************************************
;SANG TU GIUA RA 2 BEN
;**************************************
TABLE2
addwf PCL,F

retlw b'00011000'
retlw b'00100100'
retlw b'01000010'
retlw b'10000001'
retlw b'01000010'
retlw b'00100100'
retlw b'00011000'
retlw b'00100100'
;**************************************
;SANG XEN KE 2 DIEM
;**************************************
TABLE3
addwf PCL,F

retlw b'10000000'
retlw b'11000000'
retlw b'01100000'
retlw b'00110000'
retlw b'10011000'
retlw b'11001100'
retlw b'01100110'
retlw b'11011011'
;**************************************
;SANG DAN TU TRAI SANG PHAI
;**************************************
TABLE4
addwf PCL,F
retlw b'00000001'
retlw b'00000011'
retlw b'00000111'
retlw b'00001111'
retlw b'00011111'
retlw b'00111111'
retlw b'01111111'
retlw b'11111111'
;**************************************
;CHECK_KEY
;**************************************
CHECK_KEY
btfss PORTB,SW1
call SWITCH1

btfss PORTB,SW2
call SWITCH2

btfss PORTB,SW3
call SWITCH3

btfss PORTB,SW4
call SWITCH4
return
;**************************************
;CHECK_SWITCH
;**************************************

SWITCH1
clrf PORTB
bsf PORTB,LED1
return
SWITCH2
clrf PORTB
bsf PORTB,LED2
return
SWITCH3
clrf PORTB
bsf PORTB,LED3
return
SWITCH4
clrf PORTB
bsf PORTB,LED4
return
;**************************************
;DELAY
;**************************************

DELAY
movlw D'300'
movwf COUNT1
D1
movlw 0xC7
movwf COUNTa
movlw 0x01
movwf COUNTb
DELAY_0
decfsz COUNTa,1
goto $+2
decfsz COUNTb,1
goto DELAY_0
decfsz COUNT1,1
goto D1
return
;**************************************

;KhoiTaoUSART:
;**************************************

khoitaousart
movlw D'129' ;Gia tri toc do baud
ung voi 9600, BRGH = 1, xtal 20 MHz
; bcf STATUS,RP1
; bsf STATUS,RP0 ;Chon bank cho
SPBRG

movwf SPBRG ;Dat toc do baud =
9600
movlw 0x24 ;Che do: high-
speed, cho phep xuat TXEN=1, truyen bat dong bo
movwf TXSTA ;TXSTA cung bank
voi SPBRG

movlw 0x90 ;Che do: nhan lien
tuc, 8-bit, dung cac chan TX/RX
BCF STATUS,RP0 ; Chon bank
RCSTA bank0

movwf RCSTA
return
;**************************************
;chuongtrinhTRUYENA_B:
;**************************************
transmitAtoB
MOVWF TXREG
btfsc PIR1,10
GOTO transmitAtoB
RETURN
;**************************************
END

CHNG TRNH NHN

title "NHAN USART"
processor p16f877a
__CONFIG_CP_OFF&_WDT_OFF&_LVP_OFF&
_PWRTE_ON&_HS_OSC&_BODEN_OFF&_CP
D_OFF
;**************************************
;CHUONG TRINH CHINH
;**************************************
ORG 0x000
GOTO Start
Start
bcf STATUS,RP1
clrf PORTB
bsf STATUS,RP0 ;chon bank 0
movlw B'00000000'
movwf TRISB
call khoitaousart
loop call transmitAtoB
MOVWF PORTB
goto loop
;**************************************

;KhoiTaoUSART
;**************************************

khoitaousart
movlw D'129' ;Gia tri toc do baud
ung voi 9600, BRGH = 1, xtal 20 MHz
movwf SPBRG ;Dat toc do baud =
9600
movlw 0x04 ;Che do: high-
speed, truyen bat dong bo
movwf TXSTA ;TXSTA cung bank
voi SPBRG
movlw 0x90 ;Che do: nhan lien
tuc, 8-bit, dung cac chan TX/RX
BCF STATUS,RP0 ; Chon bank
RCSTA bank0
movwf RCSTA
return
;**************************************
;chuongtrinhTRUYENA_B
;**************************************
transmitAtoB
btfsc PIR1,20
GOTO transmitAtoB
MOVF RCREG,w
RETURN
;**************************************
end

bai 7.C: Khao sat truyen d lieu USART. C

TRUYN:
#include<16f877a.h>
#include<KhaiBaoTGhi_16F877A.H>
#use
rs232(baud=9600,xmit=pin_C6,rcv=pin_C7) //khai
bao toc do baud su dung chuan rs232
#use fast_io(b) //khai bao dung
port b
#use fast_io(d)
#use fast_io(a) //kb dung port d
#locate b_B=0x22
int8 i,giatri,luu,xoay;

//====================================
//chuong trinh con
//====================================
void A_to_B()
{
TXEN=1; //cho phep truyen du lieu
TXSTA<5>
TXREG=b_B; // load data vao TG dem truyen
while(~TXIF) // cho den khi load xog
PIR1<4>
}
void rota()
{
giatri=luu|xoay; // luu or xoay
luu=giatri;
xoay=xoay<<1;
}
//====================================
//chuong trinh chinh
//====================================
void main ()
{
set_tris_b(0x00); // set portB out
set_tris_d(0x00); // set port D out
set_tris_a(0x01);
while(1)
{
if(ra0==0)
{
i=0;
luu=0;
xoay=1;
portb=0;
portd=0;
b_B=0;
A_TO_B(); //goi b_B qua portb cua
PIC 2
delay_ms(100);
for(i=1;i<=8;i++)
{
rota();
portb=giatri;
delay_ms(100);
}

i=0;
luu=0;
xoay=1;
for(i=1;i<=8;i++)
{
rota();
portd=giatri;
delay_ms(100);
}
i=0;
luu=0;
xoay=1;
for(i=1;i<=8;i++)
{ rota();
b_B=giatri;
A_TO_B();
delay_ms(100);
}
}
else
{

i=0;
portb=0x00;
portd=0x00;
b_B=0x00;
A_TO_B(); //goi b_B qua portb cua PIC
2
delay_ms(100);
portb=0x01;
delay_ms(100);
for(i=1;i<=8;i++)
{
delay_ms(100);
portb=portb<<1;
}
portb=0x00;
i=0;
portd=0x01;
for(i=1;i<=8;i++)
{

delay_ms(100);
portd=portd<<1;
}
portd=0x00;
i=0;
b_B=0x01;
for(i=1;i<=8;i++)
{
A_TO_B();
delay_ms(100);
b_B=b_B<<1;
}

}
}
}
NHN:
#include<16f877a.h>
#include<KhaiBaoTGhi_16F877A.H>
#use
rs232(baud=9600,xmit=pin_C6,rcv=pin_C7) //khai
bao toc do baud
#use fast_io(b)

//====================================
// chuong trinh chinh

//====================================
main()
{
set_tris_b(0x00);
RCEN=1; //cho phep nhan du lieu
while(1)
{
while(~RCIF)
{
}
portb= rcreg;
rcreg=0;
}

Bai 8.A: Dung pic 16F877A ieu khien 1
LCD 16x2 e o nhiet o cua ngo vao kenh
th 0 dung cam bien LM35, dung ngon ng
assembly

CHNG TRNH:
; Ten chuong trinh :Mach do nhiet do dung cam
bien LM35 hien thi LCD
; Mo ta phan cung : Dung PIC16f877aA - thach
anh 20MHz
; :cam bien nhiet LM35 mac vao kenh AN0 cua
port0
; :LCD giao tiep 8 bit.
; :RS, RW, E mac vao E mac vao 3 chan RD0,
RD1 RD2
;====================================
======
TITLE "Mach Do Nhiet Dung Cam Bien LM35
Hien Thi LCD.asm"
PROCESSOR P16F877A
INCLUDE <P16F877A.inc>
_XT_OSC & _WDT_OFF & _HS_OSC &
_LVP_OFF
;====================================
======
CBLOCK 0x30
COUNT
TRAM
CHUC
DVI
KQCD
SOBICHIA
SOCHIA
SODU
THUONG
COUNT1
COUNT2
COUNT3
COUNT4
A
TAM
ENDC
;====================================
ORG 0X0000
GOTO START
START
BANKSEL TRISB
CLRF TRISB ;PORTB XUAT LED
CLRF TRISD
CALL KTADC
CALL KTLCD
MAIN
CALL CHUYENDOI
CALL HEXTOASCII
CALL DONG1
CALL DONG2
GOTO MAIN
;*****************************************
KTADC
BANKSEL ADCON1
MOVLW 0X01
;NGO VAO ANALOG,RIGHT JUSTIFY,Fosc/2
MOVWF ADCON1
BANKSEL ADCON0
MOVLW 0XC1 ;CHON RA0 LAM NGO
VAO,ADON=1,BAT ADC
MOVWF ADCON0
CALL DELAY1
;CHO 1 KHOANG THOI GIAN TRUOC KHI BAT DAU
;***************************************
;KIEM TRA KET QUA
CHUYENDOI
BSF ADCON0,GO
;SET BIT "GO",BAT DAU CONVERT
BTFSC ADCON0,GO
;KIEM TRA BIT "DONE" CUA ADCON0
GOTO $-1;NEU BANG 1 THI CHO TIEP TUC
MOVF ADRESL,W
MOVWF KQCD

RETURN
;*****************************************
DELAY1
MOVLW D'10'
MOVWF COUNT
BACK
MOVLW D'4'
MOVWF COUNT1
DECFSZ COUNT1,F
GOTO $-1
DECFSZ COUNT,F
GOTO BACK
RETURN
;*****************************************
;chuong trinh con chuyen ma hex sang MA LCD
;------------------------------------------------------------
HEXTOASCII
MOVF KQCD,0
SUBLW D'55' ;so
sanh ket qua voi 55
BTFSS STATUS,C ;so sanh voi
co c
GOTO NHIETDUONG
;co C=0, tuc phep toan co kq <0
GOTO NHIETAM ;co
C=1, tuc phep toan co kq >0
NHIETAM ;giai ma nhiet do am tu -55 den -1
do C
BTFSC STATUS,Z
GOTO Y1
MOVLW B'00101101'
MOVWF TRAM ;ma
asscii cua dau '-'
GOTO Y2
Y1 MOVLW B'00100000'
MOVWF TRAM
Y2 MOVLW D'55'
MOVWF TAM
MOVF KQCD, 0
SUBWF TAM, 0
MOVWF SOBICHIA
MOVLW D'10'
MOVWF SOCHIA
CALL DIVIDE
MOVF SODU, 0
ADDLW B'00110000'
MOVWF DVI
MOVF THUONG, 0
ADDLW B'00110000'
MOVWF CHUC
MOVF CHUC, 0;kiem tra hang chuc de
xoa so 0 vo nghia
XORLW B'00110000' ;so sanh voi so 0
BTFSS STATUS, Z
GOTO EXIT ;thoat chuong trinh con neu
chuc khac 0
MOVLW B'00100000' ;neu chuc
la 0 thi hien thi khoang trang
MOVWF CHUC
GOTO EXIT
NHIETDUONG
MOVLW D'55'
SUBWF KQCD,0
MOVWF SOBICHIA;sobichia =
kqcd - 55
MOVLW D'10'
MOVWF SOCHIA
CALL DIVIDE
MOVF SODU, 0
ADDLW B'00110000'
MOVWF DVI
MOVF THUONG, 0
MOVWF SOBICHIA
CALL DIVIDE
MOVF SODU, 0
ADDLW B'00110000'
MOVWF CHUC
MOVF THUONG, 0
ADDLW B'00110000'
MOVWF TRAM
MOVF TRAM, 0 ;kiem tra
hang tram de xoa so 0 vo nghia
XORLW B'00110000' ;so sanh voi
so 0
BTFSS STATUS, Z
GOTO EXIT ;thoat chuong trinh con neu
tram khac 0
MOVLW B'00100000'
;neu tram la 0 thi hien thi khoang trang
MOVWF TRAM
MOVF CHUC, 0 ;kiem tra hang chuc
de xoa so 0 vo nghia
XORLW B'00110000' ;so sanh voi
so 0
BTFSS STATUS, Z
GOTO EXIT ;thoat
chuong trinh con neu chuc khac 0
MOVLW B'00100000'
;neu chuc la 0 thi hien thi khoang trang
MOVWF CHUC
GOTO EXIT
EXIT
RETURN
;------------------------------------------------------------
;chuong trinh con divide
;------------------------------------------------------------
DIVIDE
CLRF THUONG
MOVF SOBICHIA,0
MOVWF SODU
X MOVF SOCHIA, 0
SUBWF SODU,0
;W=sodu-sochia, c=1 neu kq>=0 va nguoc
lai
BTFSS STATUS, C ;bo qua
lenh ke neu c=1, kq duong
GOTO EXIT1 ;thoat khoi
chuong trinh con neu kq am
INCF THUONG,1 ;tang thuong so len 1
MOVWF SODU
GOTO X
EXIT1
RETURN
;------------------------------------------------------------
;chuong trinh con khoi tao LCD
;------------------------------------------------------------
KTLCD
MOVLW 0x38;Set 8 bit mode, hien
thi 2 hang, kieu ki tu 5x8
MOVWF A
CALL GHIMADK
CALL DELAY40MS
MOVWF A
CALL GHIMADK
CALL DELAY40MS
MOVLW 0X0C ;display on/off
control
MOVWF A
CALL GHIMADK
CALL DELAY40MS
MOVLW 0X01 ;tat hien thi,con tro
doi ve goc trai
MOVWF A
CALL GHIMADK
CALL DELAY40MS
RETURN
GHIMADK
MOVF A,0
MOVWF PORTB
BCF PORTD,0
BCF PORTD,1
BSF PORTD,2
BCF PORTD,2
RETURN
;------------------------------------------------------------
;chuong trinh con ghi nhiet do ra dong 1
;------------------------------------------------------------
DONG1
MOVLW 0x80 ;ve dau dong thu
nhat
MOVWF A
CALL GHIMADK
CALL DELAY
CLRF COUNT4
LABEL1
MOVF COUNT4, 0
CALL TABLE1
MOVWF A
CALL GHIDL
CALL DELAY
INCF COUNT4,0
XORLW D'10'
BTFSC STATUS, Z
GOTO L1
INCF COUNT4,1
GOTO LABEL1
L1 MOVF TRAM, 0
MOVWF A
CALL GHIDL
CALL DELAY
MOVF CHUC, 0
MOVWF A
CALL GHIDL
CALL DELAY
MOVF DVI, 0
MOVWF A
CALL GHIDL
CALL DELAY
CLRF COUNT4
LABEL2
MOVLW B'11011111'
MOVWF A
CALL GHIDL
CALL DELAY
MOVF COUNT4, 0
CALL TABLE2
MOVWF A
CALL GHIDL
CALL DELAY
RETURN
;------------------------------------------------------------
;chuong trinh con hien thi chu dong 2
;------------------------------------------------------------
DONG2
MOVLW 0xc1
MOVWF A
CALL GHIMADK
CALL DELAY
CLRF COUNT4
LABEL3
MOVF COUNT4, 0
CALL TABLE3
MOVWF A
CALL GHIDL
CALL DELAY
INCF COUNT4,0
XORLW D'7'
BTFSC STATUS, Z
GOTO EX1
INCF COUNT4,1
GOTO LABEL3
EX1 RETURN

;------------------------------------------------------------
;bang ma ki tu cua tabel
;------------------------------------------------------------
TABLE1
ADDWF PCL, 1
DT "NHIET DO: "
TABLE2
ADDWF PCL, 1
DT "C"
TABLE3
ADDWF PCL, 1
DT "NHOM 13"
;------------------------------------------------------------
;chuong trinh con ghi ki tu ra LCD
;------------------------------------------------------------
GHIDL
MOVF A,0
MOVWF PORTB
BSF PORTD,0
BCF PORTD,1
BSF PORTD,2
BCF PORTD,2
RETURN
;------------------------------------------------------------
;cac chuong trinh con delay
;------------------------------------------------------------
DELAY MOVLW D'255'
MOVWF COUNT3
DELA1 DECFSZ COUNT3
GOTO DELA1
RETURN
DELAY40MS
MOVLW D'255'
MOVLW COUNT1
DE1 MOVLW 0XFF
MOVWF COUNT2
DE2 DECFSZ COUNT2
GOTO DE2
DECFSZ COUNT1
GOTO DE1
RETURN
END

Bai 8.C: Dung pic 16F877A ieu khien 1
LCD 16x2 e o nhiet o cua ngo vao kenh
th 0 dung cam bien LM35, dung ngon ng
C.

LU

CHNG TRNH
#include <16f877a.h>
#include "def_877a.h"
#fuses nowdt,noprotect,nolvp,put,hs
#define RS rD0
#define RW rD1
#define E rD2
#define LCD PORTB
signed int16 ADC0,tam;
int i=0;
int dv=0;
int chuc=0;
int tram=0;
const unsigned char
mht[]={'0','1','2','3','4','5','6','7','8','9','-',' '};
const unsigned char nd0[]="kenh 0: do C";

void gl(void)
{
RS = 0;
RW=0;
E=1;
E=0;
delay_ms(1);
}
void gdl(void)
{
Rw=0;
Rs=1;
E=1;
E=0;
DELAY_MS(1);
}

void hex_bcd(signed int16 adc )
{
ADC = ADC-55;
if(ADC>=0)
{
dv=ADC%10;
tam=ADC/10;
chuc=tam%10;
tram=tam/10;
if(tram==0)
{
tram=13;
if(chuc==0) chuc=13;
}
}
else
{
ADC=abs(ADC);
tram=10;
chuc=ADC/10;
dv=ADC%10;
if(chuc==0) chuc=13;
}
}

void ht()
{
LCD=mht[tram];
gdl();
LCD=mht[chuc];
gdl();
LCD=mht[dv];
gdl();
}

void kt_lcd()
{
LCD = 0x38;
gl();
LCD =0x38;
gl();
LCD=0x0C;
gl();
}
void main()
{
trisb=0;
trisd=0;
setup_adc(ADC_CLOCK_INTERNAL);
setup_adc_ports(an0_an1_vss_vref);

kt_LCD();

LCD=0x80;
gl();
while(i<=15)
{
LCD=nd0[i];
gdl();
i++;
}
i=0;
while(1)
{
set_ADC_channel(0);
delay_us(10);
ADC0=read_ADC();
hex_bcd(adc0);
LCD=0x88;
gl();
ht();
}
}

Bai 9.A: Du ng pic 16FS77A giuo liep roi
REALTME DS1JB07 ru 6 IeJ 7 Jou n, riel
chuong lrnh Jo ng ho so Ju ng ngon ngu
ussembIy

CHNG TRNH CHNH


Chng trnh
title "GIAO TIEP RTC DS1307 HIEN THI THOI
GIAN THUC"
processor p16f877a
_WDT_OFF & _HS_OSC & _LVP_OFF
;==================================
;----------KHAI BAO BIEN--------
CBLOCK 0X20
RAM_SEC
RAM_MIN
RAM_HOU
RAM_SEC1
RAM_MIN1
RAM_HOU1
RAM_SEC2
RAM_MIN2
RAM_HOU2
TEMP ; BIEN DUNG CHO CT DELAY
ENDC
;====================================
ORG 0X00
GOTO MAIN
MAIN
;KHOI TAO PORTD
BCF STATUS,RP1
BSF STATUS,RP0
CLRF TRISD ;THIET LAP PORTD
LA NGO RA DE DUA DU LIEU DEN LED
MOVLW 0X80 ;RB0->RB6
LA NGO RA DE QUET LED
MOVWF TRISB ;CHAN RB7
LA NGO VAO CHO TIN HIEU DIEU KHIEN
BCF STATUS,RP0
;KHOI TAO I2C MASTER MODE
BANKSEL SSPCON ; chon MSSP
che do MASTER MODE
MOVLW B'00101000' ; Thiet lap
MSSP cho chan PORTC o che do I2C
MOVWF SSPCON
BANKSEL SSPSTAT ; Thiet lap che
do Chuan cua toc do BAUD(100KHz)
MOVLW B'10000000'
MOVWF SSPSTAT
BANKSEL SSPADD ;
SSPADD=F(osc)/(tocdoBaud)
MOVLW 0X28 ; Tinh toan
gia tri cho thiet lap toc do 0X28=4MHz/100KHz
MOVWF SSPADD
;====================================
;THIET LAP TAN SO NGO RA CUA DS1307 LA
1Hz
CALL STARTBIT ; GUI BIT
START
MOVLW 0XD0 ;
GUI DIA CHI CHO PHEP RTC NHAN
CALL WRITE_BYTE
MOVLW 0x07 ; GUI DIA CHI
TG DIEU KHIEN NGO RA SQW/OUT CUA RTC
CALL WRITE_BYTE
MOVLW 0X10 ;
DU LIEU CHON TAN SO NGO RA SQW/OUT
CUA RTC LA 1Hz
CALL WRITE_BYTE
CALL STOPBIT
;====================================
START
CALL READ_RTC
CALL GIAIMA
CALL HIENTHI
BTFSS PORTB,7
GOTO $-2
CALL READ_RTC
CALL GIAIMA
CALL HIENTHI
BTFSC PORTB,7
GOTO $-2
GOTO START
;====================================
READ_RTC
CALL STARTBIT
MOVLW 0XD0 ;
GUI DIA CHI CHO PHEP RTC NHAN
CALL WRITE_BYTE
MOVLW 0x00 ; gui dia chi o nho GIAY
CALL WRITE_BYTE
CALL RESTARTBIT ; GUI BIT RESTART
MOVLW 0xD1; GUI DIA CHI CHO PHEP
RTC GUI
CALL WRITE_BYTE
;------------------------------------------------------------
; Qua trinh doc du lieu tu RTC
CALL READ_I2C ; Doc du lieu SECOND
CALL ACKBIT
CALL SAVE_BYTE
MOVWF RAM_SEC ; Luu du lieu GIAY
CALL READ_I2C ; Doc du lieu MINUTE
CALL ACKBIT
CALL SAVE_BYTE
MOVWF RAM_MIN ; Luu du lieu PHUT
CALL READ_I2C
CALL NACKBIT
CALL SAVE_BYTE
MOVWF RAM_HOU ;Luu du lieu HOU
CALL STOPBIT
RETURN
;====================================
WRITE_BYTE
BANKSEL SSPBUF
MOVWF SSPBUF
CALL WAITMSSP
RETURN
READ_I2C
BSF STATUS,RP0
BTFSC SSPSTAT,2 ; kiem tra bit
R/W, xem qua trinh Transmit da ket thuc chua
GOTO $-1
BANKSEL SSPCON2
BSF SSPCON2,RCEN ; cho phep
RECEIVE Mode (I2C )
CALL WAITMSSP ; Doi cho den
khi I2C thuc hien xong TUC LA NHAN DU LIEU XONG
RETURN
SAVE_BYTE
BANKSEL SSPBUF
MOVF SSPBUF,W
RETURN
;====================================
STARTBIT
BANKSEL SSPCON2
BSF SSPCON2,SEN ; gui bit START
CALL WAITMSSP
RETURN
RESTARTBIT
BANKSEL SSPCON2
BSF SSPCON2,RSEN ; gui bit
RESTART
CALL WAITMSSP
RETURN
ACKBIT
BANKSEL SSPCON2
BCF SSPCON2,ACKDT ; Chon gui
ACK
BSF SSPCON2,ACKEN ; Gui
CALL WAITMSSP
RETURN
NACKBIT
BANKSEL SSPCON2
BSF SSPCON2,ACKDT ; Chon gui
NACK
BSF SSPCON2,ACKEN ; Gui di
CALL WAITMSSP
RETURN
STOPBIT
BANKSEL SSPCON2
BSF SSPCON2,PEN ; gui bit STOP
CALL WAITMSSP
RETURN
WAITMSSP
BANKSEL PIR1
BTFSS PIR1,SSPIF ; Kiem tra trang
thai co
GOTO $-1 ; Chua hoan
thanh
BCF PIR1,SSPIF ; Da hoan thanh
cong viec, luc nay co the chuyen sang hoat dong
moi
RETURN
;====================================
GIAIMA
;HEX TO BCD
MOVLW 0X0F
ANDWF RAM_SEC,0
;LAY 4BIT THAP
MOVWF RAM_SEC1
SWAPF RAM_SEC,0
ANDLW 0X0F
MOVWF RAM_SEC2
MOVLW 0X0F
ANDWF RAM_MIN,0 ;LAY 4BIT
THAP
MOVWF RAM_MIN1
SWAPF RAM_MIN,0
ANDLW 0X0F
MOVWF RAM_MIN2

MOVLW 0X0F
ANDWF RAM_HOU,0 ;LAY 4BIT
THAP
MOVWF RAM_HOU1
SWAPF RAM_HOU,0
ANDLW 0X0F
MOVWF RAM_HOU2;LAY MA 7
DOAN
MOVF RAM_SEC1,0
CALL TABLE
MOVWF RAM_SEC1
MOVF RAM_SEC2,0
CALL TABLE
MOVWF RAM_SEC2
MOVF RAM_MIN1,0
CALL TABLE
MOVWF RAM_MIN1
MOVF RAM_MIN2,0
CALL TABLE
MOVWF RAM_MIN2
MOVF RAM_HOU1,0
CALL TABLE
MOVWF RAM_HOU1
MOVF RAM_HOU2,0
CALL TABLE
MOVWF RAM_HOU2
RETURN
;====================================
HIENTHI
;-------HIEN THI GIAY 1
MOVF RAM_SEC1,0
MOVWF PORTD
BSF PORTB,5
CALL DELAY
BCF PORTB,5
CALL DELAY
;-------HIEN THI GIAY 2
MOVF RAM_SEC2,0
MOVWF PORTD
BSF PORTB,4
CALL DELAY
BCF PORTB,4
CALL DELAY
;-------HIEN THI PHUT 1
MOVF RAM_MIN1,0
MOVWF PORTD
BSF PORTB,3
CALL DELAY
BCF PORTB,3
CALL DELAY
;-------HIEN THI PHUT 2
MOVF RAM_MIN2,0
MOVWF PORTD
BSF PORTB,2
CALL DELAY
BCF PORTB,2
CALL DELAY
;-------HIEN THI GIO 1
MOVF RAM_HOU1,0
MOVWF PORTD
BSF PORTB,1
CALL DELAY
BCF PORTB,1
CALL DELAY
;-------HIEN THI GIO 2
MOVF RAM_HOU2,0
MOVWF PORTD
BSF PORTB,0
CALL DELAY
BCF PORTB,0
CALL DELAY
RETURN
;====================================
DELAY
MOVLW D'50'
MOVWF TEMP
DECFSZ TEMP
GOTO $-1
RETLW 0X00
;====================================
TABLE
ADDWF PCL,1
DT
0x40,0x79,0x24,0x30,0x19,0x12,0x02,0x78,0x00,0
x10
END
Bai 9.C: Dung pic 16F877A giao tiep vi
REALTIME DS13B07 va 6 led 7 oan, viet
chng trnh ong ho so dung ngon ng C.


Chng trnh
#include "16f877a.h"
#include "def_877a.h"
#fuses
NOPROTECT,NOBROWNOUT,NOLVP,PUT,NO
WDT
#use i2c(Master,Fast,sda=PIN_C4,scl=PIN_C3)
#use fast_io(b)
#use fast_io(d)
#use fast_io(c)
#byte portb=0x06
#byte portd=0x08
#byte portc=0x07
//cac dinh nghia
#bit gio = portc.1
#bit phut = portc.2
#bit led0 = portb.1
#bit led1 = portb.2
#bit led2 = portb.3
#bit led3 = portb.4
#bit led4 = portb.5
#bit led5 = portb.6
int8 sec,min,hour,data;
int8 tam=0;
int8 secdv,secc,mindv,minc,hourdv,hourc;
const int
code_led[]={0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d
,0x07,0x7f,0x6f};
#int_EXT
void EXT_isr(void)
{
i2c_start();
i2c_write(0xD0); // WR to RTC
i2c_write(0x00); // REG 0
i2c_start();
i2c_write(0xD1); // RD from RTC
sec = i2c_read(0);
i2c_stop();
if ( sec == 0x00)
{
i2c_start();
i2c_start();
min = i2c_read(0);
i2c_stop();
if (min == 0x00)
{
i2c_start();
i2c_start();
hour = i2c_read(0);
i2c_stop();
}
}
}

void write_RTC()
{
i2c_start();
i2c_write(0x26); // Start oscillator with
current "seconds value
i2c_stop();
i2c_start();
i2c_write(0x07); // Control Register
i2c_write(0x10); // squarewave output pin
1Hz
i2c_stop();
i2c_start();
i2c_stop();
i2c_start();
sec = i2c_read();
min = i2c_read();
hour = i2c_read();
i2c_stop();
}

void hienthi()
{
secdv = sec & 0x0f;
secc = (sec & 0x70)>>4;
portd=code_led[secdv];
led5=0;
delay_ms(2);
led5=1;
portd=code_led[secc];
led4=0;
delay_ms(2);
led4=1;

mindv = min & 0x0F;
minc =(min & 0x70)>>4;
portd=code_led[mindv];
led3=0;
delay_ms(2);
led3=1;
portd=code_led[minc];
led2=0;
delay_ms(2);
led2=1;

hourdv = hour & 0x0F;
hourc =(hour & 0x30)>>4;
portd=code_led[hourdv];
led1=0;
delay_ms(2);
led1=1;
portd=code_led[hourc];
led0=0;
delay_ms(2);
led0=1;
}
void update_ds1307(unsigned int gtri)
{
if(gtri == 01)
{
i2c_start();
i2c_write(0xd0);
i2c_write(0x01); // ghi du lieu bat dau tu
vi tri 01
data=mindv+(minc<<4);
i2c_stop();
}
if(gtri == 02)
{
i2c_start();
i2c_write(0xd0);
i2c_write(0x02);
i2c_write(data);
data=hourdv+(hourc<<4);
i2c_write(data);
i2c_stop();
}
}
void set_incgio(void)
{
hourdv++; // tang gio
if(hourdv == 10) // khi hang don vi gio =
10
{
hourc++;
hourdv = 0;
}
if((hourc == 2)&(hourdv == 4)) // khi gio = 24
{
hourc = 0;
hourdv = 0;
}
hour = (hourc<<4)| hourdv;
}

void set_incphut(void)
{
mindv++; // tang phut
if(mindv == 10) // khi phut don vi = 10
{
mindv = 0;
minc++;
if(minc == 6) // khi phut chuc = 6
{
minc = 0;
mindv = 0;
}
}
min = (minc<<4)|mindv;
}

void main()
{
enable_interrupts(INT_EXT); // enable ext
interrupt
ext_int_edge(0,H_TO_L); // set external
interrupt to falling edge
enable_interrupts(GLOBAL);
set_tris_d(0x00);
set_tris_c(0x1f);
set_tris_b(0x01);
write_RTC();
while (TRUE)
{
hienthi();
if (phut==0)
{
tam++;
}
if (tam ==15)
{
set_incphut();
update_ds1307(01);
tam=0;
}

if (gio==0)
{
tam++;

}
if (tam ==15)
{
set_incgio();
update_ds1307(02);
tam=0;
}

}
}

Bai 10.A: Dung pic 16F877A giao tiep vi
DS18B20 (cam bien nhie t va co luon ADC
one wire) va 3 led 7 oan, viet chng
trnh do nhiet o dung ngon ng assembly.

Chng trnh:
PROCESSOR P16F877A
INCLUDE <P16F877A.INC>
__CONFIG _CP_OFF & _WDT_OFF
& _HS_OSC & _PWRTE_ON
#INCLUDE <P16F877A.INC>
;XXXXXXXXXXXXXXXXXXXXXXXXXXXX
CBLOCK 20H
PDBYTE
; Kiem tra qua trinh Reset
;-------Lay du lieu tu DS--------------------------------
BYTE0,BYTE1 Luu ket
qua
RBYTE0,RBYTE1 ; Xu ly ket
qua
XOAY ; XOAY 4 lan de lay ket
qua
;-------Dng cho Delay-----------------------------------
DELAY_TEMP0
DELAY_TEMP1
DELAY_TEMP2
;-------Ghi du lieu vao DS------------------------------
BYTE_8 ; Bien trung gian de ghi lenh vao DS
;-------Hien thi-------------------------------------------
TRAM,CHUC,DONVI
TAM
BDATA
DAU
ENDC
ORG 0X000
GOTO START
START
ORG 0X0005

BCF STATUS,RP1
BSF STATUS,RP0 ; Select
Bank1

CLRF TRISA ; PortA as output
CLRF TRISB ; PortB as
output
CLRF TRISC ; PortC as output
CLRF TRISD ; PortD as output
MOVLW B'00000110' ; Set
portA as digital port
MOVWF ADCON1 ;
BCF STATUS,RP0
; Select Bank0

CLRF PORTB
CLRF PORTC
CLRF PORTD
MAIN

;-------Initate 18B20-------------------------------
CALL RESET_18B20 ;
Khoi tao DS18B20 (Reset and wait for prensence
pulse)
BTFSS PDBYTE,0 ;
PDBYTE=1 -> Reset thnh cng
GOTO MAIN ;
PDBYTE=0 -> Quay lai tu dau
;-------SKIP ROM----------------------------------------
-
MOVLW 0CCH ; Truy cap thang
den DS18B20
MOVWF BYTE_8; BYTE_8 lm trung
gian de dich byte 0CCH vo RA0
CALL WRITE_18B20 ;
;-------CONVERT-------------------------------
MOVLW 44H ; o v chuyen doi gi
tri nhiet do thnh so
MOVWF BYTE_8; BYTE_8 lm trung
gian de dich byte 44H vo RA0
CALL WRITE_18B20 ;
CALL DELAY_762MS; Cho chuyen doi
xong

;-------Initate 18B20-----------------------
CALL RESET_18B20 ; Khoi tao
DS18B20 (Reset and wait for prensence pulse)
BTFSS PDBYTE,0 ;
PDBYTE=1 -> Reset thnh cng
GOTO MAIN ; PDBYTE=0 -> Quay lai tu dau
;-------SKIP ROM----------------------------------------
MOVLW 0CCH ; Truy cap thang den
DS18B20
MOVWF BYTE_8 ; BYTE_8 lm trung
gian de dich byte 0CCH vo RA0
CALL WRITE_18B20 ;
;-------READ SCRATCHPAD-------------------------
MOVLW 0BEH ; oc noi dung bo nho
nhp MOVWF BYTE_8 ; BYTE_8
lm trung gian de dich byte 0BEH vo RA0

CALL WRITE_18B20 ;
;-------Lay du lieu----------------------------------
CALL READ_18B20 ; Read 2 byte
BDATA (Luu vao Byte0 & Byte1)
;-------Initate 18B20-------------------------
CALL RESET_18B20 ; Reset
Ds18B20 ve trang thi nghi (bo 7 bit cn lai)
BTFSS PDBYTE,0; PDBYTE=1 -> Reset
thnh cng
GOTO MAIN ; PDBYTE=0 -> Quay lai
tu dau
;-------Xu ly ket qua----------------------------------
MOVF BYTE0,W ; RBYTTE0 =
BYTE0 , BYTE0 BYTE1 co dinh
MOVWF RBYTE0 ; RBYTTE0 = BYTE0
MOVF BYTE1,W ; RBYTTE1 =
BYTE1
MOVWF RBYTE1; RBYTTE1 = BYTE1
CALL LOC_KETQUA ; Loc lay ket qua,
luu vo bien BDATA
;-------Hien thi-------------------------
CALL HEXTOBCD
CALL HIENTHI
GOTO MAIN

RESET_18B20
CLRF PDBYTE ; Xa
PDBYTE (bit kiem tra Presence Pulse)
CALL OW_LOW
CALL DELAY_485 ; 480us
MINIMUM
CALL OW_HIGH_Z ; Release
the BUS
CALL DELAY_62
BTFSS PORTA,0; RA0=0 -> C xung
Presence
INCF PDBYTE
CALL DELAY_242
RETURN
XXXXX
OW_HIGH_Z
BSF STATUS,RP0 ; Chon Bank1 cua bo
nho du lieu
BSF TRISA,0 ; RA0 as OUTPUT -> DQ
o trang thi HIGH_Z
BCF STATUS,RP0 ; Chon BANK0

RETURN
;XXXXXXXXXXXXXXXXXXXXXXXXX
OW_LOW
BSF STATUS,RP0 ; Chon Bank1 cua bo
nho du lieu
BCF TRISA,0 ; RA0 as OUTPUT
BCF STATUS,RP0 ; Chon BANK0
BCF PORTA,0 ; RA0=0

RETURN
;
;XXXXXXXXXXXXXXXXXXXXXXXXXXX
WRITE_18B20 ; 3 giai doan
;--Dich 8 bit BYTE_8 vo RA0 de thuc hien lenh----
MOVLW 08H ; Dich 8 bit vo RA0
MOVWF TAM ;
BCF STATUS,C ; Co C lam cau noi de
dich
LB_WRITE
;-------Giai doan 1: Khoi tao-----------------------
CALL OW_LOW ; Ko QD xuong muc
thap
CALL DELAY_17 ; 15us MINIMUM
;-------Giai doan 2: Ghi du lieu-------------------------
RRF BYTE_8,1; Dich 1bit LSB cua
BYTE_8 vo C
BTFSS STATUS,C; C=0 th WRITE_0,
C=1 th WRITE_1
GOTO $+2
BSF PORTA,0; Neu C=1 ->
RA0=1
CALL DELAY_47 ; Delay 47 cho ghi
xong
;-------Giai doan 3: Release the Bus------------------
BANKSEL TRISA
BSF TRISA,0 ; RA0 as INPUT
BANKSEL PORTA ; 1us
NOP
; Cho thm 1us
;-------Dich bit tiep theo---------------------------------
DECFSZ TAM,1
GOTO LB_WRITE
RETURN
READ_18B20 ; 3 giai
doan
MOVLW D'16' ; oc 16 bit
tu RA0
MOVWF TAM
LB_READ
;-------Giai doan 1: Khoi tao---------------------------
CALL OW_LOW
NOP
;-------Giai doan 2: Release the Bus---------------
CALL OW_HIGH_Z ; Tu luc
RA0 o trang thai HIGH_Z den khi ket thuc ctr con
la 3us
CALL DELAY_11; Cho them
11us de lay du lieu trong khoang 14us cua TimeSlot
;-------Giai doan 2: Lay du lieu-------------------------
BTFSS PORTA,0; RA0=1
th C=1
GOTO $+3; RA0=0 th C
giu nguyn (=0)
BSF STATUS,C
GOTO $+2
BCF STATUS,C ; C=0 khi
DQ=0
RRF BYTE1,1 ; Dich C vo
BYTE1 v BYTE0 (16 lan)
RRF BYTE0,1 ; Dich C vo
BYTE1 v BYTE0 (16 lan)
CALL DELAY_47 ; Cho het
TimeSlot
;-------oc bit tiep theo-------------------
DECFSZ TAM,1
GOTO LB_READ
RETURN
LOC_KETQUA
BTFSS BYTE1,7 ; BYTE1.7 = 1 th l so m
GOTO EXIT ; BYTE1.7 = 0 th l so
duong
COMF RBYTE1,F ; B 2
RBYTE1
COMF RBYTE0,F ; B 2
RBYTE0
MOVLW 0X01 ; Cong thm
1
ADDWF RBYTE0,F ;
;-----------------------------------------------------------
BTFSS STATUS,C ; Neu C=1 th phai
cong 1 cho RBYTE1 do ph p ton truoc bi trn
GOTO EXIT; (Chi dnh cho truong hop
hien thi so thap phn)
MOVLW 0X01
ADDWF RBYTE1,F
;------------------------------------------------------------
EXIT
MOVLW D'4' ; Ket qua nguyn lay
trong BYTE0<4:7> v BYTE1<0:3>
MOVWF XOAY ; Do d phai xoay 4
lan
LOOP
RRF RBYTE1,1
RRF RBYTE0,1
DECFSZ XOAY,1; Xoay du 4 lan? (Bo 4
bit thap)
GOTO LOOP
MOVF RBYTE0,0 ; Ket qua nam trong
BYTE0
MOVWF BDATA; ua ket qua vo
BDATA
BCF BDATA,7 ; Chi lay 7 bit du lieu

RETURN
HEXTOBCD
CLRF TRAM ; TRAM=0
CLRF CHUC ; CHUC=0
CLRF DONVI ; DON VI=0
XET1
MOVLW .100 ; W=100
SUBWF BDATA,0; XET BDATA-W
BTFSS STATUS,C ; BANG CACH XET
CO C=1 -> BDATA>100
GOTO XET2 ; BDATA<100 THI DI DEN
XET2
MOVLW .100; CON NEUBDATA >= 100
THI
SUBWF BDATA,1; BDATA=DATA-
W (VOI W=100)
INCF TRAM,1; TRAM=TRAM+1 (DATA
SO LAN TAM LON HON 100)
GOTO XET1 ;
TIEP TUC QUAY LAI XET1 NHU TREN
XET2
MOVLW .10
; W=10
SUBWF BDATA,W
; XETBDATA-W
BTFSS STATUS,C ;
BANG CACH XET CO C=1 -> BDATA>10
GOTO THOATXET ;
NEU KHONG TRU HET TUC LA TAM<10 THI
DI DEN THOATXET
MOVLW .10
; CON NEUBDATA >= 100 THI
SUBWF BDATA,1
; BDATA=DATA-W (VOI W=10)
INCF CHUC,1
; CHUC=CHUC+1 (DATA SO LAN TAM
LON HON 10)
GOTO XET2 ; TIEP TUC QUAY LAI
XET2 NHU TREN
THOATXET
MOVF BDATA,0 ; SAU CUNG
THIBDATA<10 THI TA CHUA VAO DONVI
MOVWF DONVI ;
DONVI=W
RETURN
HIENTHI
BTFSS BYTE1,7; BYTE1.7 =1 -> So m
GOTO DUONG; BYTE1.7 =0 -> So duong
MOVLW 0XBF; M dau tru (common
anode)
MOVWF PORTB ; ua vo
PORTB
GOTO AM ; Khng hien thi TRAM
DUONG
MOVF TRAM,W ; W=TRAM
CALL TABLE ; Giai m TRAM sang LED
7 doan
MOVWF PORTB ; Xuat ra PORTB
AM
MOVF CHUC,W ; W=CHUC
CALL TABLE ; Giai m CHUC sang LED
7 doan
MOVWF PORTC ; Xuat ra PORTC

MOVF DONVI,W ; W=DONVI
CALL TABLE; Giai m DONVI sang LED
7 doan
MOVWF PORTD ; Xuat ra PORTD
RETURN
DELAY_242
MOVLW D'79'
MOVWF DELAY_TEMP0
DECFSZ DELAY_TEMP0,1
GOTO $-1
RETURN
DELAY_62
MOVLW D'19'
MOVWF DELAY_TEMP0
GOTO $-1
RETURN
DELAY_47
MOVLW D'14'
MOVWF DELAY_TEMP0
GOTO $-1
RETURN
DELAY_17
MOVLW D'4'
MOVWF DELAY_TEMP0
GOTO $-1
RETURN
DELAY_11
MOVLW D'2'
MOVWF DELAY_TEMP0
GOTO $-1
RETURN
DELAY_485
MOVLW D'160'
MOVWF DELAY_TEMP0
GOTO $-1
RETURN
DELAY_762MS
;(762.242MS)
MOVLW D'50'
MOVWF DELAY_TEMP2
MOVWF DELAY_TEMP1
MOVWF DELAY_TEMP0
GOTO $-1
GOTO $-4
GOTO $-7
RETURN
DELAY300MS

MOVLW D'40'
MOVWF DELAY_TEMP2
MOVWF DELAY_TEMP1
MOVWF DELAY_TEMP0
GOTO $-1
GOTO $-4
GOTO $-7
RETURN
TABLE
ADDWF PCL,1
DT
0C0H,0F9H,0A4H,0B0H,99H,92H,82H,0F
8H,80H,90H ;common anode
END

Bai 10.C: Dung pic 16F877A giao tiep vi
DS18B20 (cam bien nhiet va co luon ADC
one wire) va 3 led 7 oan, viet chng trnh
do nhiet o dung ngon ng C

Chng trnh
#include <16F877.h>
#fuses HS,NOPROTECT,NOLVP
#define TOUCH_PIN pin_a3
#include <touch.c>
void hienthi(int8 a,int8 b,int8 c);
int8 const seg7[11] =
{0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0
x6f,0x40};
//chuong trinh chinh
======================
void main() {

int8 tam1=0,tam2,ss,i;
int8 led1,led2,led3;
int16 nd;
//===========================
touch_present();
touch_write_byte(0xcc); // Phat lenh
skip ROM
touch_write_byte(0x4e); // Phat lenh
ghi 3byte du lieu to Scratchpad
touch_write_byte(0x0); // ghi 2 byte
rong
touch_write_byte(0x0); //
touch_write_byte(0x1f); //Cau hinh cho
thanh ghi nhiet do(do phan giai 9 bit)

touch_present();
touch_write_byte(0xCC); // skip ROM
touch_write_byte(0x48); // Sao chep
Scratchpad vao Eeprom
/===vong lp chng trnh chnh=======/
while (1) {
do {
if(touch_present())
{
touch_write_byte(0xCC);
touch_write_byte (0x44); //xuat
lenh chuyen doi nhiet do
for(i=0;i<7;++i) {
hienthi(led1,led2,led3);
}
touch_present();
touch_write_byte(0xCC);
touch_write_byte (0xBE);
//lenh doc bo nho nhap
tam1 = touch_read_byte();
//doc 2 byte nhiet do
tam2 = touch_read_byte();
}
}
while (tam1==ss); //so sanh
gia tri nhiet do doc duoc voi gia tri truoc do
ss=tam1;
/==chuyen doi nhiet do sang so thap phan====
nd=make16(tam2,tam1);
nd=nd>>4; //dich phai 4 bit
nd=nd&0x0ff; //lay 8 bit thap
if(bit_test(nd,7)) //nu gi tri nhit l m
{
led3=10; //led3 hin th du -
nd=~(--nd); //ly b 2 gi tri nhit
nd=nd&0x0ff; //xa byte cao
}
else //nu gi tr nht dng
{
led3=nd/100; //led3 hin th s hng trm
nd=nd%100;
}
led2=nd/10; //led2 hin th s hng chc
led1=nd%10; //led1 hin th s hng n
v
}
}

//chuong trinh hien thi_quet led===
void hienthi(int8 a,int8 b,int8 c)
{
output_b(seg7[a]);
output_low(pin_a0);
delay_ms(6);
output_high(pin_a0);
output_b(seg7[b]);
output_low(pin_a1);
delay_ms(6);
output_b(seg7[c]);
output_low(pin_a2);
delay_ms(6);
}

PHU LUC 2 THANH GHI SFR (SPECIAL FUNCTION REGISTER)

P2.1 Thanh ghi TMR0: a ch 01h, 101h.
Thanh ghi 8 bit cha gia tr cua bo nh thi Timer0.

P2.2 Thanh ghi PCL: a ch 02h, 82h, 102h, 182h.
Thanh ghi cha 8 bit thap cua bo em chng trnh (PC).

P2.3 Thanh ghi STATUS: a ch 03h, 83h, 103h, 183h

Bit 7: IRP bit chon bank bo nh d lie u can truy xuat (dung cho a ch gian
tiep).
IRP = 0: bank 2,3 (t 100h en 1FFh)
IRP = 1: bank 0,1 (t 00h en FFh)
Bit 6,5:RP1:RP0 hai bit chon bank bo nh d lieu ca n truy xua t (dung cho a
ch trc tiep)

Bit 4: bit ch th trang tha i cua WDT(Watch Dog Timer)
=1 khi vi ie u khien va c ca p nguon, hoa c sau khi lenh
CLRWDT hay SLEEP c thc thi.
=0 khi WDT b tran
Bit 3: bit ch th trang tha i nguon
= 1 khi vi ieu khien c cap nguon hoac sau le nh CLRWDT
= 0 sau khi lenh SLEEP c thc thi
Bit 2: Z bit Zero
Z =1 khi ket qua cua phep toan hay logic bang 0
Z = 0 khi ke t qua cua phep toa n hay logic khac 0
Bit 1: DC Digit carry/Borrow
DC = 1 khi ket qua phep toan tac ong len 4 bit tha p co nh.
DC = 0 khi ket qua phep toan tac ong len 4 bit tha p khong co nh.
Bit 0 C Carry/borrow
C =1 khi ket qua phep toan ta c ong len bit MSB co nh.
C=0 khi ket qua phep toan ta c ong len bit MSB khong co nh.
P2.4 Thanh ghi SFR: a ch 04h.
Thanh ghi cha con tro a ch gia n tiep cua bo nh d lieu. P2.5 Thanh ghi
P2.5 thanh ghi PORTA: a ch 05h.
Thanh ghi cha gia tr nhan va o hay xuat ra PORTA.

P2.6 Thanh ghi PORTB: a ch 06h, 106h.
Thanh ghi cha gia tr nhan va o hay xuat ra PORTB.

P2.7 Thanh ghi PORTC: a ch 07h.
Thanh ghi cha gia tr nhan va o hay xuat ra PORTC

P2.8 Thanh ghi PORTD: a ch 08h.
Thanh ghi cha gia tr nhan va o hay xuat ra PORTD.

P2.9 Thanh ghi PORTE: a ch 09h.
Thanh ghi cha gia tr nhan va o hay xuat ra PORTE.

P2.10 Thanh ghi PCLATCH: a ch 0Ah, 8Ah, 10Ah, 18Ah.
Thanh ghi ong vai tro la buffer em trong qua trnh ghi gia tr len 5 bit cao cua
bo em chng trnh PC.

P2.11 Thanh ghi INTCON: a ch 0Bh, 8Bh, 10Bh, 18Bh.
Thanh ghi cha cac bit ieu khien va ca c bit c hieu khi timer0 b tran, nga t
ngoai vi RB0/INT va ngat interrput-on-change ta i cac chan cua PORTB.

Bit 7 GIE Global Interrupt Enable bit
GIE = 1 cho phep ta t ca cac nga t.
GIE = 0 khong cho phep tat ca cac nga t.
Bit 6 PEIE Pheripheral Interrupt Enable bit
PEIE = 1 cho phep ta t ca ca c ngat ngoa i vi
PEIE = 0 khong cho phep tat ca ca c nga t ngoai vi
Bit 5 TMR0IE Timer0 Overflow Interrupt Enable bit
TMR0IE = 1 cho phep ngat Timer0
TMR0IE = 0 khong cho phep nga t Timer0
Bit 4 RBIE RB0/INT External Interrupt Enable bit
RBIE = 1 cho phep ngat ngoai vi RB0/INT
RBIE = 0 khong cho phep ngat ngoa i vi RB0/INT
Bit 3 RBIE RB Port change Interrupt Enable bit
RBIE = 1 cho phep ngat RB Port change
RBIE = 0 khong cho phep ngat RB Port change
Bit 2 TMR0IF Timer0 Interrupt Flag bit
TMR0IF = 1 thanh ghi TMR0 b tran (pha i xoa bang chng trnh) .
Bit 1 INTF BR0/INT External Interrupt Flag bit
INTF = 1 ngat RB0/INT xay ra (phai xoa c hie u bang chng trnh).
INTF = 0 ngat RB0/INT cha xay ra.
Bit 0 RBIF RB Port Change Interrupt Flag bit
RBIF = 1 t nha t co mo t chan RB7:RB4 co s thay o i trang thai.Bit nay phai
c xoa ba ng chng trnh sau khi a kie m tra lai cac gia tr cua ca c cha n ta i
PORTB.
RBIF = 0 khong co s thay oi tra ng tha i ca c chan RB7:RB4.

P2.12 Thanh ghi PIR1: a ch 0Ch
Thanh ghi cha c nga t cua ca c khoi ngoai vi.

Bit 7 PSPIF Parallel Slave Port Read/Write Interrupt Flag bit
PSPIF = 1 va hoan ta t thao ta c oc hoa c ghi PSP (phai xoa bang chng trnh).
PSPIF = 0 kho ng co thao tac oc ghi PSP na o dien ra.
Bit 6 ADIF ADC Interrupt Flag bit
ADIF = 1 hoa n ta t chuyen oi ADC.
ADIF = 0 cha hoan tat chuyen oi ADC.
Bit 5 RCIF USART Receive Interrupt Flag bit
RCIF = 1 buffer nha n qua chuan giao tiep USART a ay.
RCIF = 0 buffer nha n qua chuan giao tiep USART rong.
Bit 4 TXIF USART Transmit Interrupt Flag bit
TXIF = 1 buffer truye n qua chuan giao tiep USART rong.
TXIF = 0 buffer truye n qua chuan giao tiep USART ay.
Bit 3 SSPIF Synchronous Serial Port (SSP) Interrupt Flag bit
SSPIF = 1 nga t truyen nhan SSP xay ra.
SSPIF = 0 nga t truyen nhan SSP cha xay ra.
Khi CCP1 che o Capture
CCP1IF=1 a ca p nha t gia tr trong thanh ghi TMR1.
CCP1IF=0 cha cap nhat gia tr trong thanh ghi TMR1.
Khi CCP1 che o Compare
CCP1IF=1 gia tr ca n so sanh ba ng vi gia tr cha trong TMR1
CCP1IF=0 gia tr ca n so sanh khong bang vi gia tr trong TMR1.
Bit 1 TMR2IF TMR2 to PR2 Match Interrupt Flag bit
TRM2IF = 1 gia tr cha trong thanh ghi TMR2 bang vi gia tr cha trong thanh
ghi PR2.
TRM2IF = 0 gia tr cha trong thanh ghi TMR2 cha bang vi gia tr cha trong
thanh ghi PR2.
Bit 0 TMR1IF TMR1 Overflow Interrupt Flag bit
TMR1IF = 1 thanh ghi TMR1 b tran (pha i xoa bang chng trnh).

P2.13 Thanh ghi PIR2: a ch 0Dh

Bit 7, 5, 2, 1: khong quan ta m va ma c nh mang gia tr 0.
Bit 6 CMIF Comparator Interrupt Flag bit
CMIF = 1 tn hieu ngo vao bo so sanh thay oi.
CMIF = 0 tn hieu ngo vao bo so sanh khong thay oi.
Bit 4 EEIF EEPROM Write Operation Interrupt Flag bit
EEIF = 1 qua trnh ghi d lieu len EEPROM hoan tat.
EEIF = 0 qua trnh ghi d lieu len EEPROM cha hoan tat hoa c cha
bat a u.
Bit 3 BCLIF Bus Collision Interrupt Flag bit
BCLIF = 1 Bus truyen nhan ang ban khi (ang co d lieu truyen i trong bus)
khi SSP ha t ong che o I2C Master mode.
BCLIF = 0 Bus truyen nhan cha b tran (khong co d lieu truyen i trong bus).
che o Capture
CCP2IF = 1 a ca p nhat gia tr trong thanh ghi TMR1.
CCP2IF = 0 cha cap nhat gia tr trong thanh ghi TMR1.
che o Compare
CCP2IF = 1 gia tr ca n so sanh ba ng vi gia tr cha trong TMR1.
CCP2IF = 0 gia tr ca n so sanh cha ba ng vi gia tr cha trong TMR1.

P2.14 Thanh ghi TMR1L: a ch 0Eh
Thanh ghi cha 8 bit thap cua bo nh th i TMR1.

P2.15 Thanh ghi TMR1H: a ch 0Fh
Thanh ghi cha 8 bit cao cua bo nh th i TMR2. P2.16 Thanh ghi T1CON: a ch
10h

Bit 7,6 Khong quan tam va mang gia tr ma c nh ba ng 0.
Bit 5,4 T1CKPS1:T1CKPS0 Timer1 Input Clock Prescaler Select bit
11 t so chia ta n so cu a prescaler la 1:8
10 t so chia ta n so cu a prescaler la 1:4
01 t so chia tan so cua prescaler la 1:2
02 t so chia tan so cua prescaler la 1:1
Bit 3 T1OSCEN Timer1 Oscillator Enable Control bit
T1OSCEN = 1 cho phep Timer1 hoa t ong vi xung do oscillator cung cap.
T1OSCEN = 0 khong cho phep Timer1 hoat ong vi xung do oscillator cung
cap (ta t bo chuyen oi xung ben trong Timer1).
Bit 2 Timer1 ternal Clock Input Synchronization Control bit
Khi TMR1CS = 1:
= 1 kho ng ong bo xung clock ngoai vi a vao Timer1.
= 0 o ng bo xung clock ngoa i vi a vao Timer1.
Khi TMR1CS = 0
Bit khong c quan tam do Timer1 s dung xung clock ben trong.
Bit 1 TMR1CS Timer1 Clock Source Select bit
TMR1CS = 1 chon xung em la xung ngoai vi lay t pin RC0/T1OSC/T1CKI
(canh ta c ong la canh len).
TMR1CS = 0 chon xung em la xung clock ben trong (FOSC/4).
Bit 0 TMR1ON Timer1 On bit
TMR1ON = 1 cho phep Timer1 hoa t ong.
TMR1ON = 0 Timer1 ngng hoa t ong.

P2.17 Thanh ghi TMR2: a ch 11h
Thanh ghi cha gia tr bo em Timer2.

P2.18 Thanh ghi T2CON: a ch 12h
Thanh ghi ieu khien Timer2.
Bit 7 Khong quan tam va ma c nh mang gia tr 0
Bit 6-3 TOUTPS3:TOUTPS0 Timer2 Output Postscaler Select bit
Cac bit nay ieu khien vie c la chon t so chia tan so cho postscaler.
0000 t so 1:1
0001 t so 1:2
0010 t so 1:3

1111 t so 1:16
Bit 2 TMR2ON Timer2 On bit
TMR2ON = 1 bat Timer2.
TMR2ON = 0 ta t Timer2.
Bit 1,0 T2CKPS1:T2CKPS0 Timer2 Clock Prescaler Select bit
Cac bit nay ieu khien t so chi tan so cua prescaler
00 t so 1:1
01 t so 1:4
1x t so 1:16

P2.19 Thanh ghi SSPBUF: a ch 13h
Thanh ghi em d lieu 8 bit cho chuan giao tiep MSSP.

P2.20 Thanh ghi SSPCON: a ch 14h
Thanh ghi ieu khien chuan giao tiep MSSP.

Khi MSSP che o SPI:
Bit 7 WCOL Write Collition Detect bit
WCOL = 1 d lieu m i c a vao thanh ghi SSPBUF trong khi cha truyen
xong d lieu trc o.
WCOL = 0 khong co hie n tng tren xay ra.
Bit 6 SSPOV Receive Overflow Indicalor bit (bit nay ch co tac dung che o SPI
Slave mode).
SSPOV = 1 d lieu trong bufer e m (thanh ghi SSPBUF) b tran (d lieu cu cha
c oc th co d lieu m i gi e len).
SSPOV = 0 khong co hie n tng tren xay ra.
Bit 5 SSPEN Synchronous Serial Port Enable bit
SSPEN = 1 cho phep cong giao tiep MSSP (cac pin SCK, SDO, SDI va ).
SSPEN = 0 khong cho phep co ng giao tiep MSSP.
Bit 4 CKP Clock Polarity Select bit
CKP = 1 tra ng tha i ch cua xung clock la mc logic cao.
CKP = 0 tra ng tha i ch cua xung clock la mc logic tha p.
Bit 3-0 SSPM3:SSPM0 Synchronous Serial Mode Select bit
Cac bit nay ong vai tro la chon cac che o hoat ong cua MSSP. 0101 Slave
mode, xung clock la y t pin SCK, khong cho phep pin ie u khien ( la pin I/O bnh
thng).
0100 SPI Slave mode, xung clock la y t pin SCK, cho phep pin ieu
khien .
0011 SPI Master mode, xung clock bang (ngo ra TMR2)/2.
0010 SPI Master mode, xung clock bang (FOSC/64).
Cac trang tha i khong c lie t ke hoac khong co ta c dung ieu khie n hoa c ch
co tac dung oi vi che o I2C mode.

Khi MSSP che o I2C
Bit 7 WCOL Write Collition Detect bit
Khi truyen d lieu che o I2C Master mode:
WCOL = 1 a d lie u truyen i va o thanh ghi SSPBUF trong khi che o
truyen d lieu cua I2C cha san sang.
WCOL = 0 khong xay ra hien tng tren.
khi truyen d lieu che o I2C Slave mode:
WCOL = 1 d lieu m i c a va o thanh ghi SSPBUF trong khi d lie u
cu cha c truyen i.
WCOL = 0 khong co hien tng tren xay ra.
che o nha n d lieu (Master hoac Slave):
Bit nay khong co tac dung ch thi cac tra ng thai.
Bit 6 SSPOV Receive Overflow Indicator Flag bit.
Khi nha n d lie u:
SSPOV = 1 d lieu mi c nha n vao thanh ghi SSPBUF trong khi d
lieu cu cha c oc.
SSPOV = 0 khong co hie n tng tren xay ra.
Khi truyen d lie u:
Bit nay khong co tac dung ch th cac tra ng thai.
Bit 5 SSPEN Synchronous Serial Port Enable bit
SSPEN = 1 cho phep cong giao tie p MSSP (cac pin SDA va SCL).
SSPEN = 0 khong cho phep co ng giao tiep MSSP.
Can chu y la ca c pin SDA va SCL pha i c ie u khie n trang tha i bang ca c bit
tng ng trong thanh ghi TRISC trc o).
Bit 4 CKP SCK Release Control bit
che o Slave mode:
CKP = 1 cho xung clock tac ong.
CKP = 0 gi xung clock mc logic thap (e bao am thi gian thie t lap
d lieu).
Bit 3,0 SSPM3:SSPM0
Cac bit nay ong vai tro la chon ca c che o hoat ong cua MSSP.
1111 I2C Slave mode 10 bit a ch va cho phep ngat khi pha t hien
bit Start va bit Stop.
1110 I2C Slave mode 7 bit a ch va cho phep ngat khi phat hie n
bit Start va bit Stop.
1011 I2C Firmwave Controlled Master mode (khong cho phep che
o Slave).
1000 I2C Master mode, xung clock = FOSC/(4*(SSPADD+1)).
0111 I2C Slave mode 10 bit a ch. Cac tra ng thai khong c lie t
ke hoac khong co ta c dung ieu khie n hoac ch co ta c dung oi vi
che o SPI mode.

P2.21 Thanh ghi CCPR1L: a ch 15h
Thanh ghi cha 8 bit thap cua khoi CCP1.

P2.22 Thanh ghi CCPR1H: a ch 16h
Thanh ghi cha 8 bit cao cua khoi CCP1.

P2.23 Thanh ghi CCP1CON va thanh ghi CCP2CON: a ch 17h (CCP1CON) va
1Dh (SSP2CON)
Thanh ghi ieu khien khoi CCP1.

Bit 7,6 Khong co ta c dung va mac nh mang gia tr 0.
Bit 5,4 CCPxX:CCPxY: PWM least Significant bits (ca c bit nay khong co ta c dung
che o Capture va Compare)
che o PWM, ay la 2 bit MSB cha gia tr tnh o rong xung (duty
cycle) cua khoi PWM (8 bit con la i c ch a trong thanh ghi CCPRxL).
Bit 3-0 CCPxM3:CCPxM0 CCPx Mode Select bit
Cac bit dung e xa c la p ca c che o hoat ong cua khoi CCPx
0000 khong cho phep CCPx (hoac dung e reset CCPx)
0100 CCPx hoa t ong che o Capture, hien tng c thie t
lap la mo i ca nh xuong tai pin dung cho khoi CCPx.
lap la mo i ca nh len ta i pin dung cho khoi CCPx.
lap la mo i ca nh len th 4 tai pin dung cho khoi CCPx.
lap la mo i ca nh len th 16 tai pin dung cho khoi CCPx.
1000 CCPx hoa t ong che o Compare, ngo ra c a len m c
cao va bit CCPxIF c set khi ca c gia tr ca n so sanh bang nhau.
1001 CCPx hoat ong che o Compare, ngo ra c xuong m c
thap va bit CCPxIF c set khi cac gia tr can so sanh bang nhau.
1010 CCPx hoa t ong che o Compare, khi cac gia tr can so
sanh bang nhau, nga t xay ra, bit CCPxIF c set va trang tha i pin
output khong b anhhng. 1011 CCPx hoat ong che o
Compare, khi ca c gia tr ca n so sanh ba ng nhau, xung trigger a c
bie t (Trigger Special Event) se c tao ra, khi o c ngat CCPxIF
c set, ca c pin output khong thay o i trang thai, CCp1 reset
Timer1, CCP2 reset Timer1 va kh i ong kho i ADC. 11xx CCPx
hoat ong che o PWM.

P2.24 Thanh ghi RCSTA: a ch 18h
Thanh ghi cha ca c bit trang thai va cac bit ieu khien qua trnh nhan d lie u
qua chuan giao tiep USART.

Bit 7 SPEN Serial Port Enable bit
SPEN = 1 Cho phep cong giao tiep USART (pin RC7/RX/DT va RC6/TX/CK).
SPEN = 0 khong cho phep co ng giao tiep USART.
Bit 6 RX9 9-bit Receive Enable bit
RX9 = 1 nhan 9 bit d lieu.
RX9 = 0 nhan 8 bit d lieu.
Bit 5 SREN Single Receive Enable bit
che o USART bat ong bo: bit nay khong can quan tam.
che o USART Master ong bo:
SREN = 1 cho phep chc nang nhan 1 byte d lie u (8 bit hoa c 9 bit).
SREN = 0 khong cho phep chc nang nhan 1 byte d lieu.
Bit 4 CREN Continous Receive Enable bit
che o ba t ong bo:
CREN = 1 cho phep nhan 1 chuoi d lieu lie n tu c.
CREN = 0 khong cho phep nhan 1 chuoi d lieu lien tuc.
che o ba t ong bo:
CREN = 1 cho phep nhan d lieu cho ti khi xoa bit CREN.
CREN = 0 khong cho phep nhan chuo i d lieu.
Bit 3 ADDEN Address Detect Enable bit
che o USART bat ong bo 9 bit
ADDEN = 1 cho phep xac nhan a ch, khi bit RSR<8> c set th ngat c
cho phep thc thi va gia tr trong buffer c nhan va o.
ADDEN = 0 khong cho phep xa c nha n iz5 ch, ca c byte d lieu c nhan
vao va bit th 9 co the c s dung nh la bit parity.
Bit 2 FERR Framing Eror bit
FERR = 1 xua t hien lo i Framing trong qua trnh truyen nhan d lieu.
FERR = 0 khong xuat hien lo i Framing trong qua trnh truyen nhan d lieu.
Bit 1 OERR Overrun Error bit,
OERR = 1 xua t hien loi Overrun
OERR = 0 khong xuat hie n loi Overrun
Bit 0 RX9D
Bit nay cha bit d lieu th 9 cua d lieu truyen nhan.
P2.25 Thanh ghi XTREG: a ch 19h
Thanh ghi ong vai tro la buffer e m 8 bit trong qua trnh truyen d lieu thong
qua chuan giao tiep USART.

P2.26 Thanh ghi RCREG: a ch 1Ah
Thanh ghi ong vai tro la buffer em trong qua trnh nhan d lieu qua chuan
giao tiep USART.
P2.27 Thanh ghi CCPR2L: a ch 1Bh
Thanh ghi cha 8 bit thap cua khoi CCP2.
P2.28 Thanh ghi CCPR2H: a ch 1Ch
Thanh ghi cha 8 bit cao cua khoi CCP2.

P2.29 Thanh ghi ADRESH: a ch 1Eh
Thanh ghi cha byte cao cua ket qua qua trnh chuyen oi ADC.

P2.30 Thanh ghi ADCON0: a ch 1Fh
ay la mot trong hai thanh ghi ieu khien khoi chuyen o i ADC. Thanh ghi con
lai la thanh ghi ADCON1 (a ch 9Fh)

Bit 7,6 ADCS1:ADCS0 A/D Conversion Clock Select bit

Bit 5-3 CHS2:CHS0 Analog Channel Select bit
Cac bit nay dung e chon kenh chuyen oi ADC
000 kenh 0 (AN0)
001 kenh 1 (AN1)
010 kenh 2 (AN2)
011 kenh 3 (AN3)
100 kenh 4 (AN4)
101 kenh 5 (AN5)
110 kenh 6 (AN6)
111 kenh 7 (AN7)
Bit 2 A/D Conversion Status bit
Khi ADON = 1
= 1 A/D ang hoat ong (set bit nay se lam khi ong ADC va
t xoa khi qua trnh chuyen oi ket thuc).
= 0 A/D khong hoa t ong.
Bit 1 Khong can quan ta m va mac nh mang gia tr 0.
Bit 0 ADON A/D On bit
ADON = 1 bat A/D
ADON = 0 tat A/D

P2.31 Thanh ghi OPTION_REG: a ch 81h, 181h
Thanh ghi nay cho phep ie u khie n chc na ng pull-up cua ca c pin trong PORTB,
xac lap ca c tham so vexung tac ong, canh ta c ong cua ngat ngoai vi va bo e m
Timer0.

Bit 7 PORTB pull-up enable bit
= 1 kho ng cho phep chc nang pull-up cua PORTB
= 0 cho phep chc na ng pull-up cua PORTB
Bit 6 INTEDG Interrupt Edge Select bit
INTEDG = 1 nga t xa y ra khi canh dng cha n RB0/INT xua t hien.
INTEDG = 0 nga t xa y ra khi canh a m chan BR0/INT xuat hien.
Bit 5 TOCS Timer0 Clock Source select bit
TOSC = 1 clock lay t chan RA4/TOCK1.
TOSC = 0 dung xung clock ben trong (xung clock nay bang vi xung clock dung
e thc thi le nh).
Bit 4 TOSE Timer0 Source Edge Select bit
TOSE = 1 ta c ong ca nh len.
TOSE = 0 ta c ong ca nh xuong.
Bit 3 PSA Prescaler Assignment Select bit
PSA = 1 bo chia ta n so (prescaler) c dung cho WDT
PSA = 0 bo chia ta n so c dung cho Timer0
Bit 2:0 PS2:PS0 Prescaler Rate Select bit
Cac bit nay cho phep thie t la p t so chia ta n so cua Prescaler.

P2.32 Thanh ghi TRISA: a ch 85h
Thanh ghi ieu khien xuat nhap cua ca c pin trong PORTA.

P2.33 Thanh ghi TRISB: a ch 86h, 186h
Thanh ghi ieu khien xuat nhap cua ca c pin trong PORTB.

P2.34 Thanh ghi TRISC: a ch 87h
Thanh ghi ieu khien xuat nhap cua ca c pin trong PORTC.

P2.35 Thanh ghi TRISD: a ch 88h
Thanh ghi ieu khien xuat nhap cua ca c pin trong PORTD.

P2.36 Thanh ghi TRISE: a ch 89h
Thanh ghi ieu khien xuat nhap cua ca c pin trong PORTE, ieu khie n cong giao tie p
song song PSP (Parallel Slave Port).

Bit 7 BIF Input Buffer Full Status bit
BIF = 1 mo t Word d lieu va c nhan va ang ch CPU o c va o.
BIF = 0 cha co Word d lieu na o c nhan.
Bit 6 OBF Output Buffer Full Status bit
OBF = 1 Buffer truyen d lieu van con cha d lieu cu va van cha c oc.
OBF = 0 Buffer truye n d lieu a c oc.
Bit 5 IBOV Input Buffer Overflow Detect bit
IBOV = 1 d lieu c ghi le n buffer trong khi d lieu cu va n cha c oc.
IBOV = 0 buffer cha b tran.
Bit 4 PSPMODE Parallel Slave Port Mode Select bit
PSPMODE = 1 Cho phep PSP, PORTD ong vai tro la cong giao tiep song song
PSP.
PSPMODE = 0 Khong cho phep PSP.
Bit 3 Khong can quan tam va mac nh mang gia tr 0.
Bit 2 Bit2 Direction Control for pin .
Bit2 = 1 Input
Bit2 = 0 Output
Bit 1 Bit1 Direction Control for pin
Bit1 = 1 Input
Bit1 = 0 Output
Bit 0 Bit0 Direction Control for pin
Bit0 = 1 Input
Bit0 = 0 Output

P2.37 Thanh ghi PIE1: a ch 8Ch
Thanh ghi cha cac bit cho phep ca c ngat ngoai vi.

Bit 7 PSPIE Parallel Slave Port Read/Write Interrupt Enable bit
PSPIE = 1 cho phep ngat PSP read/write.
PSPIE = 0 khong cho phep nga PSP read/write.
Bit 6 ADIE ADC (A/D converter) Interrupt Enable bit
ADIE = 1 cho phep ngat ADC.
ADIE = 0 khong cho phep ngat ADC.
Bit 5 RCIE USART Receive Interrupt Enable bit
RCIE = 1 cho phep ngat nha n USART
RCIE = 0 khong cho phepn gat nhan USART
Bit 4 TXIE USART Transmit Interrupt Enable bit
TXIE = 1 cho phep ngat truyen USART
TXIE = 0 khong cho phep ngat truyen USART
Bit 3 SSPIE Synchronous Serial Port Interrupt Enable bit
SSPIE = 1 cho phep ngat SSP
SSPIE = 0 khong cho phep nga t SSP
CCP1IE = 1 cho phep ngat CCP1
CCP1IE = 0 khong cho phep nga t CCP1
Bt 1 TMR2IE TMR2 to PR2 Match Interrupt Enable bit
Bit 0 TMR1IE TMR1 Overflow Interrupt Enable bit
P2.38 Thanh ghi PIE2: a ch 8Dh
Thanh ghi cha cac bit cho phep ca c ngat ngoai vi.

Bit 7, 5, 2, 1 Khong can quan ta m va mac nh mang gia tr 0.
Bit 6 CMIE Comparator Interrupt Enable bit
CMIE = 1 Cho phep ngat cua bo so sa nh.
CMIE = 0 Khong cho phep nga t.
Bit 4 EEIE EEPROM Write Operation Interrupt Enable bit
EEIE = 1 Cho phep ngat khi ghi d lieu len bo nh EEPROM.
EEIE = 0 Khong cho phep ngat khi ghi d lieu le n bo nh EEPROM.
Bit 3 BCLIE Bus Collision Interrupt Enable bit
BCLIE = 1 Cho phep ngat.
BCLIE = 0 Khong cho phep nga t.
CCP2IE = 1 Cho phep ngat.
CCP2IE = 0 Khong cho phep nga t.

P2.39 Thanh ghi PCON: a ch 8Eh
Thanh ghi ie u khien cha ca c c hieu cho bie t trang thai cac che o reset cua vi ieu
khien.

Bit 7, 6, 5, 4, 3, 2 Khong can quan tam va mac nh mang gia tr 0.
Bit 1 Power-on Reset Status bit
= 1 khong co s tac ong cua Power-on Reset.
= 0 co s tac ong cua Power-on reset.
Bit 0 Brown-out Reset Status bit
= 1 khong co s tac ong cua Brown-out reset.
= 0 co s tac ong cua Brown-out reset.

P2.40 Thanh ghi SSPCON2: a ch 91h
Thanh ghi ieu khien cac che o hoa t ong cua chua n giao tie p I2C.

Bit 7 GCEN General Call Enable bit
GCEN = 1 Cho phep ngat khi a ch 0000h c nhan vao thanh ghi SSPSR
(a ch cua che o General Call Address).
GCEN = 0 Khong cho phep che o a ch tren.
Bit 6 ACKSTAT Acknowledge Status bit (bit nay ch co ta c dung khi truyen d lieu
che o I2C Master mode).
ACKSTAT = 1 nha n c xung t I2C Slave.
ACKSTAT = 0 chaq nhan c xung .
Bit 5 ACKDT Acknowledge Data bit (bit nay ch co tac dung khi nhan d lieu che
o I2C Master mode).
ACKDT = 1 cha nha n c xung .
ACKDT = 0 a nhan c xung .
Bit 4 ACKEN Acknowledge Sequence Enable bit (bit nay ch co tac dung khi nhan
d lieu che o I2C Master mode)
ACKEN = 1 cho phep xung xua t hie n 2 pin SDA va SCL khi ket thuc qua
trnh nhan d lieu.
ACKEN = 0 khong cho phep ta c ong tren.
Bit 3 RCEN Receive Enable bit (bit na y ch co tac dung che o I2C Master mode).
RCEN = 1 Cho phep nhan d lieu che o I2C Master mode.
RCEN = 0 Khong cho phep nhan d lieu.
Bit 2 PEN Stop Condition Enable bit
PEN = 1 cho phep thiet lap ieu kie n Stop 2 pin SDA va SCL.
PEN = 0 khong cho phep tac ong tren.
Bit 1 RSEN Repeated Start Condition Enable bit
RSEN = 1 cho phep thie t la p ieu kien Start lap lai lien tuc 2 pin SDA va SCL.
RSEN = 0 khong cho phep ta c ong tren.
Bit 0 SEN Start Condition Enable/Stretch Enable bit
che o Master mode:
SEN = 1 cho phep thie t la p ieu kien Start 2 pin SDA va SCL.
SEN = 0 khong cho phep tac ong tren.
che o Slave mode:
SEN = 1 cho phep khoa xung clock t pin SCL cua I2C Master.
Khong cho phep tac ong tren.
P2.41 Thanh ghi PR2: a ch 92h
Thanh ghi dung e an nh tr c gia tr e m cho Timer2. Khi vi ie u khien c
reset, PR2 mang gia tr FFh. Khi ta a mo t gia tr va o thanh ghi PR2, Timer2 se em
t 00h cho en khi gia tr bo em cua Timer2 bang vi gia tr cua bo em trong thanh
ghi PR2. Nh vay mac nh Timer2 se e m t 00h en FFh.

P2.42 Thanh ghi SSPADD: a ch 93h
Thanh ghi cha a ch cua vi ie u khien khi hoa t ong chuan giao tiep I2C
Slave mode. Khi khong dung e cha a ch (I2C Master mode) SSPADD c dung
e cha gia tr ta o ra xung clock ong bo ta i pin SCL.
P2.43 Thanh ghi SSPSTAT: a ch 94h
Thanh ghi cha ca c bit trang thai cua chuan giao tie p MSSP.

Khi MSSP hoa t ong che o SPI:
Bit 7 SMP Sample bit
SPI Master mode:
SMP = 1 d lieu c lay mau (xa c nh trang tha i logic) ta i thi ie m
cuoi xung clock.
SMP = 0 d lieu c lay mau tai thi iem gia xung clock.
SPI Slave mode: bit nay pha i c xoa ve 0.
Bit 6 CKE SPI Clock Select bit
CKE = 1 SPI Master truyen d lieu khi xung clock chuyen t trang tha i tch cc
en trang thai ch.
CKE = 0 SPI Master truye n d lie u khi xung clock chuyen t trang thai ch en
trang thai tch c c.
(trang tha i ch c xa c nh bi bit CKP (SSPCON<4>).
Bit 5 bit.
Bit nay ch co tac dung che o I2C mode.
Bit 4 P Stop bit
Bit nay ch s dung khi MSSP che o I2C.
Bit 3 S Start bit
Bit nay ch co tac dung khi MSSP che o I2C.
Bit 2 bit information
Bit 1 UA Update Address bit
Bit 0 BF Buffer Status bit
BF = 1 thanh ghi em SSPBUF a co d lieu.
BF = 0 thanh ghi em SSPBUF cha co d lieu.

Khi hoa t ong che o I2C
Bit 7 SPM Slew Rate Control bit
SPM = 1 dung toc o chuan (100 KHz va 1 MHz).
SPM = 0 dung toc o cao ( 400 KHz).
Bit 6 CKE MSBus Select bit
CKE = 1 cho phep MSBus.
CKE = 0 khong cho phep MSBus.
Bit 5 bit
I2C Master mode: khong quan tam.
= 1 byte va truyen i hoa c nhan c la d lieu.
= 0 byte va truyen i hoa c nhan c la a ch.
Bit 4 P Stop bit
P = 1 va nhan c bit Stop.
P = 0 cha nhan c bit Stop.
Bit 3 S Start bit
S = 1 va nhan c bit Start.
S = 0 cha nhan c bit Start.
Bit 2 bit information
I2C Slave mode:
= 1 o c d lieu.
= 0 ghi d lieu.
I2C Master mode:
= 1 ang truyen d lie u.
= 0 khong truyen d lieu.
Bit 1 UA Update Address
Bit nay ch co tac dung oi vi che o I2C Slave mode10 bit a ch.
UA = 1 vi ieu khien can cap nha t them a ch t thanh ghi SSPADD.
UA = 0 khong can cap nhat them a ch.
Bit 0 BF Buffer Full Status bit
BF = 1 Thanh ghi SSPBUF ang cha d lie u truyen i hoa c nha n c.
BF = 0 thanh ghi SSPBUF khong co d lieu.

P2.44 Thanh ghi TXSTA: a ch 98h
Thanh ghi cha cac bit trang thai va ieu khien viec truyen d lieu thong qua chuan
giao tiep USART.

Bit 7 CSRC Clock Source Select bit
che o ba t ong bo: khong can quan ta m.
che o ong bo:
CSRC = 1 Master mode (xung clock c la y t bo tao xung BRG).
CSRC = 0 Slave mode (xung clock c nhan t be n ngoai).
Bit 6 TX-9 9-bit Transmit Enable bit
TX-9 = 1 truyen d lie u 9 bit.
TX-9 = 0 truyen d lie u 8 bit.
Bit 5 TXEN Transmit Enable bit
TXEN = 1 cho phep truyen.
TXEN = 0 khong cho phep truyen.
Bit 4 SYNC USART Mode Select bit SYNC = 1 dang ong bo
SYNC = 0 dang bat ong bo.
Bit 2 BRGH High Baud Rate Select bit
Bit nay ch co tac dung che o bat ong bo .
BRGH = 1 toc o cao.
BRGL = 0 toc o thap.
Bit 1 TRMT Transmit Shift Register Status bit
TRMT = 1 thanh ghi TSR kho ng co d lieu.
TRMT = 0 thanh ghi TSR co cha d lieu.
Bit 0 TX9D
Bit nay cha bit d lieu th 9 khi d lieu truyen nhan la 9 bit.

P2.45 Thanh ghi SPBRG: a ch 99h
Thanh ghi cha gia tr tao xung clock cho bo tao xung BRG (Baud Rate
Generator). Tan so xung clock do BRG tao ra c tnh theo ca c cong thc trong bang
sau:

Trong o X la gia tr cha trong thanh ghi SRBRG.

P2.46 Thanh ghi CMCON: a ch 9Ch
Thanh ghi ieu khien va ch th ca c trang tha i cung nh ke t qua cua bo so sa nh.

Bit 7 C2OUT Comparator 2 (C2) Output bit
Khi C2INV = 0
C2OUT = 1 khi (pin VIN+ cua C2)> (pin VIN- cua C2).
C2OUT = 0 khi (pin VIN+ cua C2) < (pin VIN- cua C2).
Khi C2INV = 1
C2OUT = 1 khi (pin VIN+ cua C2)< (pin VIN- cua C2).
C2OUT = 0 khi (pin VIN+ cua C2) > (pin VIN- cua C2).
Bit 6 C1OUT Comparator 1 (C1) Output bit
Khi C1INV = 0
C1OUT = 1 khi (pin VIN+ cua C1)> (pin VIN- cua C1).
C1OUT = 0 khi (pin VIN+ cua C1) < (pin VIN- cua C1).
Khi C1INV = 1
C1OUT = 1 khi (pin VIN+ cua C1)< (pin VIN- cua C1).
C1OUT = 0 khi (pin VIN+ cua C1) > (pin VIN- cua C1).
Bit 5 C2INV Comparator 2 Output Conversion bit
C2INV = 1 ngo ra C2 c ao tra ng tha i.
C2INV = 0 ngo ra C2 khong ao tra ng tha i.
Bit 4 C1INV Comparator 1 Output Conversion bit
C1INV = 1 ngo ra C1 c ao tra ng tha i.
C1INV = 0 ngo ra C1 khong ao tra ng tha i.
Bit 3 CIS Comparator Input Switch bit
Bit nay ch co tac dung khi CM2:CM0 = 110
CIS = 1 khi pin VIN- cua C1 no i vi RA3/AN3 va pin VIN- cu a C2 noi
vi RA2/AN2
CIS = 0 khi pin VIN- cua C1 noi vi RA0/AN0 va pin VIN- cua C2 noi
vi RA1/AN1
Bit 2-0 CM2:CM0 Comparator Mode bit
Cac bit nay ong vai tro trong viec thie t lap cac ca u hnh hoat ong cua bo
Comparator. Ca c dang cau hnh cua bo Comparator c trnh ba y trong bang sau:


Trong o: A la ngo va o Analog, khi o gia tr cua cac pin na y oc t ca c PORT
luon bang 0. B la ngo vao Digital.

P2.47 Thanh ghi CVRCON: a ch 9Dh
Thanh ghi ieu khien bo tao ien a p so sanh khi bo Comparator hoat ong vi
cau hnh 110.
Bit 7 CVREN Comparator Voltage Reference Enable bit.
CVREN = 1 bo tao ie n ap so sanh c cap ie n ap hoat ong.
CVREN = 0 bo tao ie n ap so sanh khong c cap ien ap hoa t o ng.
Bit 6 CVROE Comparator VREF Output Enable bit
CVROE = 1 ien ap do bo tao ien ap so sa nh ta o ra c a ra pin RA2.
CVROA = 0 ien ap do bo tao ien ap so sa nh ta o ra khong c a ra ngoai.
Bit 5 CVRR Comparator VREF Range Selection bit
CVRR = 1 mo t m c ie n ap co gia tr VDD/24 (ien ap do bo tao ien ap so
sanh ta o ra co gia tr t 0 en 0.75VDD).
CVRR = 0 mo t m c ie n ap co gia tr VDD/32 (ien ap do bo tao ien ap so
sanh ta o ra co gia tr t 0.25 en 0.75VDD).
Bit 3-0 CVR3:CVR0 Cac bit chon ien ap ngo ra cua bo tao ie n ap so sanh.
Khi CVRR = 1:
ien a p tai pin RA2 co gia tr CVREF = (CVR<3:0>/24)*VDD.
Khi CVRR = 0
ien a p tai pin RA2 co gia tr CVREF = (CVR<3:0>/32)*VDD + VDD.

P2.48 Thanh ghi ADRESL: a ch 9Eh
Thanh ghi cha ca c bit thap cua ket qua bo chuyen oi A/D (8 bit cao cha trong
thanh ghi ADRESH a ch 1Eh).

P2.49 Thanh ghi ADCON1: a ch 9Fh
Thanh ghi cha cac bit ieu khie n bo chuyen oi ADC (ADC co hai thanh ghi
ie u khie n la ADCON1 va ADCON0).

Bit 7 ADFM A/D Result Format Select bit
ADFM = 1 Ket qua c lu ve pha ben phai 2 thanh ghi ADRESH:ADRESL
(6 bit cao mang gia tr 0).
ADFM = 0 Ket qua c lu ve pha ben tra i 2 thanh ghi ADRESH:ADRESL
(6 bit thap mang gia tr 0).
Bit 6 ADCS2 A/D Conversion Clock Select bit
ADCS2 ket hp v i 2 bit ADCS1:ADCS0 trong thanh ghi ADCON0 e ieu
khien vie c chon xung clock cho khoi chuyen oi ADC.

Bit 5,4 Khong can quan ta m va ma c nh mang gia tr 0.
Bit 3-0 PCFG3:PCFG0 A/D Port Configuration Control bit
Cac bit nay ieu khien vie c chon ca u hnh hoat ong cac cong cua bo chuyen
oi ADC.

Trong o A la ngo vao Analog.
D la ngo vao Digital.
C/R la so ngo va o Analog/so ien a p mau.

P2.50 Thanh ghi EEDATA: a ch 10Ch
Thanh ghi cha byte thap cua d lieu trong qua trnh ghi oc tren bo nh d lieu
EEPROM.

P2.51 Thanh ghi EEADR: a ch 10Dh
Thanh ghi cha byte thap cua a ch trong qua trnh ghi oc tren bo nh d lieu
EEPROM.

P2.52 Thanh ghi EEDATH: a ch 10Eh
Thanh ghi cha byte cao cua d lieu trong qua trnh ghi oc tren bo nh d lieu
EEPROM (thanh ghi nay ch s dung 6 bit thap).

P2.53 Thanh ghi EEADRH: a ch 10Fh
Thanh ghi cha byte cao cua a ch trong qua trnh ghi oc tren bo nh d lieu
EEPROM (thanh ghi nay ch s dung 4 bit thap).

P2.54 Thanh ghi EECON1: a ch 18Ch
Thanh ghi ieu khien bo nh EEPROM.

Bit 7 EEPGD Program/Data EEPROM Select bit
EEPGD = 1 truy xua t bo nh chng trnh.
EEPGD = 0 truy xua t bo nh d lieu.
Bit 6-4 Khong ca n quan ta m va ma c nh mang gia tr 0.
Bit 3 WRERR EEPROM Error Flag bit
WRERR = 1 qua trnh ghi len bo nh b gia n oan va khong the tiep tu c (do
cac che o Reset WDT hoa c ).
WRERR = 0 qua trnh ghi len bo nh hoa n ta t.
Bit 2 WREN EEPROM Write Enable bit
WREN = 1 cho phep ghi.
WREN = 0 khong cho phep ghi.
Bit 1 WR Write Control bit
WR = 1 ghi d lieu. Bit nay ch c set ba ng chng trnh va t ong xoa ve 0
khi qua trnh ghi d lie u hoan ta t.
WR = 0 hoan ta t qua trnh ghi d lieu.
Bit 0 RD Read Control bit
RD = 1 o c d lieu. Bit nay ch c set ba ng chng trnh va t ong xoa ve 0
khi qua trnh oc d lieu hoan tat.
RD = 0 qua trnh oc d lie u khong xay ra.

P2.55 Thanh ghi EECON2: a ch 18Dh.
ay la mot trong 2 thanh ghi ieu khie n bo nh EEPROM. Tuy nhien ay khong
phai la thanh ghi va t l thong thng va khong cho phep ngi1 s dung truy xuat d
lieu tren thanh ghi.

TAI LIEU THAM KHAO
SACH VI X 2 CU A NGUYEN NH PHU TRNG AI HOC
SPKT.TPHCM
PIC16F877A DATASHEET WWW.MICROCHIP.COM
MIDRANGE PICmicro FAMILY WWW.MICROCHIP.COM
CAC TRANG WEB
WWW.MICROCHIP.COM
WWW.DIENDANDIENTU.COM
WWW.PICVIETNAM.NET
VA CAC TRANG WEB KHAC

Bao Cao Thuc Tap VXL Nguyen Duy Tuong 688

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