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VCC3V3 VCC3V3 D7 E12 F7 F8 G10 H10 J6 J7 K7 L9 L10 N7 N13 E8 F9 F10 L7 L8 A9 A10 C9 D8 EMC_A0 EMC_A1 EMC_A2 EMC_A3 EMC_A4 EMC_A5

EMC_A6 EMC_A7 EMC_A8 EMC_A9 EMC_A10 EMC_A11 EMC_A12 EMC_A13 EMC_A14 EMC_CKE0 EMC_CLK0 EMC_DMT0 EMC_DMT1 EMC_nDYS0 EMC_nCAS EMC_nRAS EMC_nWE H16 G16 F16 E15 C16 P2 R2 R3 J16 H14 K16 M15 N15 T16 H13 H12 N5 G15 H15 J15 R16 P16 T4 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VPP VDDREG1 VDDREG2 VDDREG3 VDDREG4 WAKEUP0 WAKEUP1 WAKEUP2 WAKEUP3 VSSIO14 VSSIO13 VSSIO12 VSSIO11 VSSIO10 VSSIO9 VSSIO8 VSSIO7 VSSIO6 VSSIO5 VSSIO4 VSSIO3 VSSIO2 VSSIO1 VSS5 VSS4 VSS3 VSS2 VSS1 P13 P7 M13 K10 K9 J9 J8 H9 H8 G8 G7 G6 D13 C4 K8 J11 J10 H7 G9 B4 B2 L4 J4 J5 K5 K6 M4 D9 D1 E1 A11 B10 B8 A8 T5 R7 T7 R8 T9 R9 R10 R11 P9 P10 T13 R12 N3 P3 R4 T8 VDDA VSSA VCC3V3 C6 10uF + C7 100nF C8 100nF C9 100nF C10 100nF

VCC3V3

FB1

VDDA C84 100nF C85 100nF VSSA

BLM15HG601SN1D

FB2 BLM15HG601SN1D

VCC3V3 DECAP + C24 10uF C11 100nF C12 100nF C13 100nF C14 100nF C15 100nF C16 100nF C17 100nF C18 100nF C19 100nF C20 100nF C21 100nF C22 100nF C23 100nF C35 100nF

close to the processor

VDDA VSSA U4A DBGEN LPC4357FET256 TDI EMC_A0 TCK/SWDCLK EMC_A1 TDO/SWO EMC_A2 TMS/SWDIO EMC_A3 TRST EMC_A4 /RESET EMC_A5 XTAL1 EMC_A6 XTAL2 EMC_A7 RTC_ALARM EMC_A8 VBAT EMC_A9 B8 EMC_A10 A8 EMC_A11 EMC_D0 EMC_A12 EMC_D1 EMC_A13 EMC_D2 EMC_A14 EMC_D3 EMC_D4 EMC_D5 EMC_CKEOUT0 EMC_D6 EMC_CLK0 EMC_D7 EMC_DQMOUT0 EMC_D8 EMC_DQMOUT1 EMC_D9 EMC_D10 EMC_DYCS0 EMC_D11 EMC_CAS EMC_D12 EMC_RAS EMC_D13 EMC_WE EMC_D14 EMC_D15 U5

R3 10K NC/TDI SWDCLK/TCLK SWO/TDO SWIO/TMS nRST XTAL1 XTAL2 VBAT D10

nRST

(2) VCC3V3 nRST R1 DNP

VCC3V3 VCC3V3 R65 100K R67 100K R28 100K R66 100K R27 100K 1 3 5 7 9 11 13 15 17 19

PMEG2005AED

R2 10K EMC_D0 EMC_D1 EMC_D2 EMC_D3 EMC_D4 EMC_D5 EMC_D6 EMC_D7 EMC_D8 EMC_D9 EMC_D10 EMC_D11 EMC_D12 EMC_D13 EMC_D14 EMC_D15 Y2 32.768 kHz 2 C25 18pF C26 18pF 2 1 3 1 4 3 C1 100nF

J9 HE10 20PTS VTref Vsupply nTRST GND1 TDI GND2 TMS GND3 TCK GND4 RTCK GND5 TDO GND6 nSRST GND7 DBGRQ GND8 DBGACK GND9 2 4 6 8 10 12 14 16 18 20

VCC /RESET GND

SW1
RESET

NC/TDI SWIO/TMS SWDCLK/TCLK SWO/TDO nRST R68 0R

U19 MAX809TTRG

close to the processor

Note: if U19 used,R1 not placed.they mutual exclusion;

RESET

User

JTAG
VCC3V3

EMC_A0 EMC_A1 EMC_A2 EMC_A3 EMC_A4 EMC_A5 EMC_A6 EMC_A7 EMC_A8 EMC_A9 EMC_A10 EMC_A11 EMC_A12 EMC_A13 EMC_A14 EMC_CKE0 EMC_CLK0 EMC_DMT0 EMC_DMT1 EMC_nCAS EMC_nRAS EMC_nWE EMC_nDYS0

8 7 6 5 C87 18pF 1 2 XTAL1 1 2 3 4 RN1 4x100K Boot from Quad SPI Flash 1110 J2 BOOT0 BOOT1 BOOT2 BOOT3 1 3 5 7 ON1 ON2 ON3 ON4 SW OFF1 OFF2 OFF3 OFF4 2 4 6 8 5 6 7 8 RN2 4x1K 4 3 2 1 Y4 12MHz 4 C86 18pF 3 XTAL2 close to the processor

BOOT3

BOOT0 BOOT1 BOOT2

23 24 25 26 29 30 31 32 33 34 22 35 36 20 21 37 38 15 39 17 18 16 19 40

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 BA0 BA1 CKE CLK DQML DQMH /CAS /RAS /WE /CS NC

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VDD1 VDD2 VDD3 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VSS1 VSS2 VSS3 VSSQ1 VSSQ2 VSSQ3 VSSQ4

2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 1 14 27 3 9 43 49 28 41 54 6 12 46 52

EMC_D0 EMC_D1 EMC_D2 EMC_D3 EMC_D4 EMC_D5 EMC_D6 EMC_D7 EMC_D8 EMC_D9 EMC_D10 EMC_D11 EMC_D12 EMC_D13 EMC_D14 EMC_D15 VCC3V3

BOOT SELECT

VCC3V3 DECAP + C32 10uF C27 100nF C28 100nF C29 100nF C30 100nF C31 100nF C33 100nF C34 100nF

close to the SRAM

MT48LC16M16A2

http://arm.embedinfo.com
Title: LPC4357-EVB Size: Document Number: Custom PWR&SDRAM&JTAG Draw By: CS Date: Sunday, January 06, 2013 Rev: B Sheet: 1 of 2

L3 10uH D1 BAT54C U6 TP6 3 Test Point D12 C38 1uF 1 2 1 3 2 SW FB GND /SHDN 4 VIN 5 R5 10K + C36 C37 100nF 10uF D12 E11 A3 USART0_TXD1 A2 USART0_RXD1 D11 E10 D10 E9 E7 B7 E6 D6 E3 ADC0_0 C3 ADC0_1 A4 ADC0_2 B5 ADC0_3 C6 ADC0_4 B3 ADC0_5 A5 ADC0_6 C5 ADC0_7 T10 P12 B9 L3 M2 T12 M7 M8 N12 M11 M10 P5 T3 FLSH_RST R5 D5 M12 R15 L12 P15 L14 J13 B16 E5 H5 K4 L1 VCC5V

VCC3V3 USART0_TXD0 USART2_TXD USART3_TXD USART0_TXD1 I2C0_SCL I2C1_SCL SPI_MISO SPI_SIO2 SPI_SCK ADC0_0 ADC0_2 ADC0_4 ADC0_6 J4 6 5 4 FB5 BLM15HG601SN1D VCC3V3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

J12 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

VCC5V USART0_RXD0 USART2_RXD USART3_RXD USART0_RXD1 I2C0_SDA I2C1_SDA SPI_MOSI SPI_SIO3 SPI_CS ADC0_1 ADC0_3 ADC0_5 ADC0_7

USB ROUTING GUIDELINES Route usb trace pairs together [DP&DM]. Do not route usb traces under crystals,oscillators, magnetic devices or ICs that use and/or duplicate clocks. Route high-speed usb signals using a minimum of vias and corners. use 20-mil minimum spacing between high-speed usb signal pairs and other signal traces for optimal signal quality.

FAN5333B PTVS24VS1UR R26 DNP

J3 VLed+ VLedR0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 GND B4 GND B5 B6 B7 DCLK DISP HSYNC VSYNC DE VDD TP_XN TP_YN TP_XP TP_YP D2 TVS 2 2 37 38 39 40 D3 TVS U7 1 16 15 13 12 D4 D5 TVS TVS 2 2 R8 10K 8 11 9 YXY+ X+ IN3 IN2 IN1 IN0 DATAIN INT SCLK SDAT A0/DATAOUT 7 2 4 5 3 R14 10K VCC VIO GND GND X- GND Y- GND X+ GND Y+ N.C. FPC-40A 2 1 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 31 32 33 34 4 3 29 36 35 C40 100nF + 10uF C39 LCD_VD0 LCD_VD1 LCD_VD2 LCD_VD3 LCD_VD4 LCD_VD5 LCD_VD6 LCD_VD7 LCD_VD8 LCD_VD9 LCD_VD10 LCD_VD11 LCD_VD12 LCD_VD13 LCD_VD14 LCD_VD15 LCD_VD16 LCD_VD17 LCD_VD18 LCD_VD19 LCD_VD20 LCD_VD21 LCD_VD22 LCD_VD23 LCD_DCLK LCD_DISP LCD_HSYNC LCD_VSYNC LCD_DE

R4 15.8R

R25 15.8R

USB_A D+ and D- are differential 1 2 3

HEADER 15X2

U18 1 2 3 4 ENA OUT_A FLG_A IN FLG_B GND ENB OUT_B LM3526M-H/NOPB 8 7 6 5 VCC5V

VBUS DM DP ID GND

USB0_PWR_EN USB0_PWR_FAULT USB0_VDDA3V3_DRIVER USB0_VDDA3V3 USB0_VSSA_TERM USB0_VSSA_VREF USB1_VBUS USB1_DP USB1_DM USB0_RREF U4B LPC4357FET256 PE_0 PE_1 PE_2 PE_3 PE_4 PE_5 PE_6 PE_7 PE_14 PD_2 PD_3 PD_4 PD_5 PD_6 PD_7 PD_8 PD_9 I2C1_SCL I2C1_SDA

F3 G3 H3 G1 K14 F12 G12 H1 P14 N14 M14 K12 K13 N16 M16 F15 C15 R1 P4 T2 P6 R6 T6 P8 T11 E13 G14 USB0_VSSA USB1_VBUS USB1_DP USB1_DM R53 KEY0 KEY1 KEY2 KEY3 KEY4 LED_3V3 KEY5 KEY6 KEY7 KEY8 KEY9 G_INT ADXL_INT1 ADXL_INT2 I2C1_SCL I2C1_SDA 15K

C76

C77

BLM15HG601SN1D FB4

100nF 100nF

BLM15HG601SN1D D+ and D- are differential pair with 90 ohm impedance. R54 R55 33R 33R C88 47pF C89 VCC3V3 47pF R43 1K KEY0 R44 1K R45 1K R46 1K R47 1K R56 R57 15K 15K

41 42

VCC3V3 R72 DNP

1 2 3 4 5

FB3

VCC3V3

3 TP5 Test Point 1 IRLML6402 Q2

2 R7 4.7K

C1 LCD_DE LCD_HSYNC C7 LCD_VSYNC D2 D4 LCD_DCLK L13 LCD_DISP H11 LCD_BL B6 LCD_PWR L11 USART0_RXD0 M9 USART0_TXD0 N10 USART3_RXD M6 USART3_TXD N8 N6 T1 TP_PENIRQ

I2S0_TX_SDA I2S0_TX_SCK I2S0_TX_WS I2S0_RX_SDA I2S0_RX_SCK I2S0_RX_WS I2S0_SCL I2S0_SDA

LCD_DE LCD_LP LCD_FP LCD_DCLK LCD_DISP LCD_BL LCD_PWR USART0_RXD USART0_TXD TP_/CS TP_DI TP_BUSY TP_DOUT TP_/PENIRQ

KEY1

KEY2

VCC3V3 6 14 10 17 C48 100nF R15 10K R16 10K I2C0_SCL I2C0_SDA

PA_1 PA_2 PA_4 PC_1 PC_11 PC_14 PC_2 PC_3 PE_9 PC_9 PD_0 PD_1 PD_10 PD_11 PD_12 PD_13 PD_14 PD_15 PD_16 PE_10 PE_11 PE_12 PE_8 PC_8 SPI_MISO SPI_MOSI SPI_SIO2 SPI_SIO3 SPI_CLK SPI_CS SD_CMD SD_CLK SD_D0 SD_D1 SD_D3 SD_D2

L6 H4 M1 F11 F13 G11 L15 L16

J14 K15 G13 E4 L5 N1 F6 F5 E16 K2 N2 P1 P11 N9 N11 T14 R13 T15 R14 E14 D16 D15 F14 N4 B13 C11 C12 A15 B14 C10 M5 D14 F4 G4 G5 H6

TP_YN TP_XN TP_YP TP_XP

KEY3

I2S0_TX_SDA I2S0_TX_SCK I2S0_TX_WS I2S0_RX_SDA I2S0_RX_SCK I2S0_RX_WS I2C0_SCL I2C0_SDA

USART2_TXD USART2_RXD

SD_CD SPI_MISO SPI_MOSI SPI_SIO2 SPI_SIO3 SPI_SCK SPI_CS SD_CMD SD_CLK SD_D0 SD_D1 SD_D3 SD_D2

VCC3V3 C41 100nF J10 SD_D2 R74 SD_D3 R75 SD_CMD 0R 0R 10K 10K 10K 10K 10K 10K 1 2 3 4 5 6 7 8 10 9

KEY4

R80 R79 R73 R71 R70 R69

LED_3V3

R48

1K

SD CARD
R34 10K KEY7 KEY8 KEY9 KEY6 KEY5 C66 100nF

D6 BLUE VCC3V3

STMPE811

U7 I2C Address=0X82
VCC5V R33 2K R29 0R R30 DNP TP3 TP4 DNP U8 I2S0_RX_SCK I2S0_RX_WS I2S0_RX_SDA I2S0_TX_SCK I2S0_TX_WS I2S0_TX_SDA I2C0_SCL I2C0_SDA 3 4 5 6 7 8 13 14 12 1 25 C52 10uF C47 100nF 9 33 BCKO WSO DATA0 BCKI WSI DATAI L3CLK/SCL L3DATA/SDA L3MODE RESET VREF VINR VINM VINL VOUTL VOUTR VOUTLHP VREF_HP VOUTRHP VDD SEL_L3_IIC VADCP VDDA_HP VDDA_DA VDDA_AD RTCB VADCN VSSA VSSA_AD VSSA_HP VSS 29 31 27 23 21 19 18 17 2 15 32 20 22 28 11 30 24 26 16 10 C50 10uF C51 100nF 2 C53 10uF C54 C55 100nF 10uF C56 100nF C57 10uF C58 100nF R40 1K 3 C61 C60 C59 47uF 47uF 47uF VINR VINM VINL VOUTL VOUTR VOUTLHP VREFHP VOUTRHP R31 0R R32 DNP 2 5 4 3 1 2 5 4 3 1 SJ-3524-SMT

SD_CLK SD_D0 SD_D1 SD_CD R76 R77 0R 0R 0R

DAT2 DAT3 CMD VCC CLK VSS DAT0 DAT1 GND CD TF01A

Sh1 Sh2 Sh3

11 12 13

R35 10K

R36 10K

R37 10K

MIC
J5

R78

Test Point Test Point

HEADPHONE

SJ-3524-SMT VCC3V3 U15 8 J6 R39 10K C70 100nF 4 VCC /CS DO /WP DI CLK GND HOLD 1 2 3 5 6 7 SPI_CS SPI_MISO SPI_SIO2 SPI_MOSI SPI_SCK SPI_SIO3

VCC3V3 2 4 5 6 11 12 13 14 10 3

U16 VCC NC2 NC3 NC4 NC5 NC6 NC7 NC8 GND /HOLD /CS SO /WP SI 1 7 8 9 15 16 SPI_SIO3 SPI_CS SPI_MISO SPI_SIO2

C65 100nF

C64 100nF

C63 100nF

VCC3V3 R10 4.7K R11 4.7K

R13 0R R12 0R VCC3V3

TP1 TP2 Test Point Test Point

C43 100nF

C69 100nF

VCC3V3 SPI_MOSI SPI_SCK I2C1_SCL I2C0_SCL FLSH_RST nRST (1) I2C1_SDA I2C0_SDA ADXL_INT2 ADXL_INT1 DNP R21 0R R22 R20 4.7K R19 4.7K 14 13 11 10 9 8 12 R18 10K SCL SDA RES2 NC INT2 INT1 ADDR ADXL345 U9 VDD VS /CS RES1 GND1 GND2 GND3 1 6 7 3 2 4 5 VCC3V3

UDA_RST C49 4.7uF R9 47K C46 4 10nF 2 1 3

BLM15HG601SN1D FB8 S25FL032P0XMFI013/ DNP

/RESET SCK S25FL256S

SP1 U14 IN- VOUT VCC BP G1 G2 IN+ GND 5 VCC5V 6 7 1 8 4 C45 C44 100nF 100nF R41 1K C68 33nF 2 AST-03008MR-R C67 100uF 1

R81 R82

DNP 0R

DNP R23 0R R24

Vdd TriState GND OutPut Y3 24.576MHZ

SYSCLK PAD_GND UDA1380HN

I2C Address = 0X53


VCC3V3 DN1 KEY0 6 5 4 1 2 3 BAS16VY DN2 KEY3 6 5 4 1 2 3 BAS16VY G_INTX R63 G_INT 0R R64 KEY8 KEY9 6 5 4 G_INT1 0R R61 10K KEY5 KEY6 KEY7 6 5 4 DN3 BAS16VY 1 2 3 DN4 BAS16VY 1 2 3 R62 10K VCC3V3 the default configuration of the interrupt pins is active high. this can be changed to active low by setting the int_invert bit in the data_format(address 0x31) register.

LM386N-4/NOPB

USB1_VBUS KEY1 D11 PMEG2005AED DC5V J8 1 2 3 SW2 D7 PMEG2005AED C78 220uF SW KEY-SPDT C79 100nF VCC5V D9 PMEG2005AED L1 10uH R60 C82 100uF C83 100nF Test Point C80 47uF C81 100nF 1K D8 GREEN VCC3V3 KEY2 U13 NX1117-3.3/SOT223 3 2 VIN VOUT 1 GND VCC3V3

Jack 2.1mm

KEY4

GND1 Test Point TP7

SHD FB6 BLM15HG601SN1D

LCD_BL LCD_VD0 LCD_VD1 LCD_VD2 LCD_VD3 LCD_VD4 LCD_VD5 LCD_VD6 LCD_VD7 LCD_VD8 LCD_VD9 LCD_VD10 LCD_VD11 LCD_VD12 LCD_VD13 LCD_VD14 LCD_VD15 LCD_VD16 LCD_VD17 LCD_VD18 LCD_VD19 LCD_VD20 LCD_VD21 LCD_VD22 LCD_VD23

PF_0 PF_1 PF_10 PF_11 PF_2 PF_3 PF_4 PF_5 PF_6 PF_7 PF_8 PF_9 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 CLK1 CLK3 N.C. P0_0 P0_1 P1_15 P1_16 P1_17 P1_18 P1_19 P1_20 P1_3 P1_4 P1_5 P4_0 P6_0 P6_1 I2S1_MCLK P6_3 P6_6 P6_7 P7_0 P8_0 P8_1 P8_2 P8_8

A1 B1 C2 D3 K1 K3 J1 J2 A7 E2 M3 L2 J3 A6 A12 B11 C8 C13 A16 C14 A13 B12 A14 B15

LCD_VD0 LCD_VD1 LCD_VD2 LCD_VD3 LCD_VD4 LCD_VD5 LCD_VD6 LCD_VD7 LCD_VD8 LCD_VD9 LCD_VD10 LCD_VD11 LCD_VD12 LCD_VD13 LCD_VD14 LCD_VD15 LCD_VD16 LCD_VD17 LCD_VD18 LCD_VD19 LCD_VD20 LCD_VD21 LCD_VD22 LCD_VD23

USB0_VBUS USB0_DP USB0_DM USB0_ID

pair with 90 ohm impedance. F1 USB0_VBUS R49 33R F2 USB0_DP R51 15K USB-AF-4 G2 USB0_DM H2 R50 33R R52 15K J12 USB0_PWR_EN K11 USB0_PWR_FAULT

J7 R58 10K R59 10K USB0_VBUS FB7 BLM15HG601SN1D 8 7

USB Mini B 9 6

K1
1 2 3 4 SELECT C71 100nF User

K2

1 2

3 4

UP

C72 100nF User

K3

1 2

3 4

RIGHT

C73 100nF User

K4

1 2

3 4 Down

C74 100nF User

K5

1 2

3 4 LEFT

C75 100nF User

R38 10K 2 3 1 4 6 C62 100nF 5 R42 100R

U10 Selection DWON LEFT RIGHT UP COMMON

MT008-A

R17 10K

C42 100nF

http://arm.embedinfo.com
Title: LPC4357-EVB Size: Document Number: Custom LCM&AUDIO&OTHER Draw By: CS Date: Sunday, January 06, 2013 Rev: B Sheet: 2 of 2

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