EXPERIM ENT: 1 (A)

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EXPERIM ENT: 1 (A)

AIM:- Design of gates TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity and_beh is Port ( a,b : in STD_LOGIC; c : out STD_LOGIC); end and_beh; architecture Behavioral of and_beh is begin c<= a and b; end Behavioral;

Experiment: 1(b)

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Experiment: 1(b)
AIM:- Design of gates TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity or_beh is Port ( a,b : in STD_LOGIC; c : out STD_LOGIC); end or_beh; architecture Behavioral of or_beh is begin c<= a or b; end Behavioral;

Experiment: 1(c1)

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Experiment: 1(c1)
AIM:- Design of gates TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity xor_beh is Port ( a,b : in STD_LOGIC; c : out STD_LOGIC); end xor_beh; architecture Behavioral of xor_beh is begin c<=a xor b; end Behavioral;

Experiment: 1(c2)

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Experiment: 1(c2)
AIM:- Design of gates TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity xor1_beh is Port ( a,b : in STD_LOGIC; c : out STD_LOGIC); end xor1_beh; architecture Behavioral of xor1_beh is begin c<= (a and (not b)) or ((not a) and b); end Behavioral;

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Experiment: 2

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Experiment: 2
AIM:- Design of XOR gate using other basic gates TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity xor_str1 is Port ( a,b : in STD_LOGIC; c : out STD_LOGIC); end xor_str1; architecture structural of xor_str1 is signal abar,bbar,s0,s1: std_logic; component and1 is Port ( a,b : in STD_LOGIC; c : out STD_LOGIC); end component;

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component or1 is Port ( a,b : in STD_LOGIC; c: out STD_LOGIC); end component;

component not1 is port( a: in std_logic; c: out std_logic); end component; begin N1:not1 port map(a,abar); N2:not1 port map(b,bbar); A1:and1 port map(abar,b,s0); A2:and1 port map(a,bbar,s1); O1:or1 port map(s0,s1,c);

end structural;

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Experiment: 3

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Experiment: 3
AIM:- Design of 2 : 1 MUX using other basic gates TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity mux_str is Port ( a,b,s : in STD_LOGIC; c : out STD_LOGIC); end mux_str; architecture structural of mux_str is signal sbar,s1,s2: std_logic; component and1 is Port ( a,b : in STD_LOGIC; c : out STD_LOGIC); end component;

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component or1 is Port ( a,b : in STD_LOGIC; c: out STD_LOGIC); end component;

component not1 is port( a: in std_logic; c: out std_logic); end component; begin n1: not1 port map(s,sbar); a1: and1 port map(a,s,s1); a2: and1 port map(b,sbar,s2); o1: or1 port map(s1,s2,c);

end structural;

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Experiment: 4

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Experiment: 4
AIM:- Design of 2 to 4 decoder TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity decoder2_4 is Port ( x : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC_VECTOR (3 downto 0)); end decoder2_4; architecture Behavioral of decoder2_4 is begin process(x) begin case (x) is when "00" =>y <= "0001" ; when "01" =>y <= "0010" ; when "10" =>y <= "0100" ; when "11" =>y <= "1000" ; when others => y <= "0000" ; end case; end process; end Behavioral;

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Experiment: 5(a)

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Experiment: 5(a)
AIM:- Design of Half - Adder TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity halfadder_beh is Port ( a,b : in STD_LOGIC; s,c : out STD_LOGIC); end halfadder_beh;

architecture Behavioral of halfadder_beh is begin s<=a xor b; c<= a and b; end Behavioral;
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Experiment: 5(b)

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Experiment: 5(b)
AIM :- Design of Full Adder TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity fulladder2_1 is Port ( a,b,c : in STD_LOGIC; s,cout : out STD_LOGIC); end fulladder2_1; architecture Behavioral of fulladder2_1 is begin s <= (a xor b) xor c; cout <= (a and b) or (b and c) or (a and c); end Behavioral;

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Experiment: 5(c)

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Experiment: 5(c)
AIM :- Design of Half Substractor TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity halfsub_beh is Port ( a,b : in STD_LOGIC; diff, borrow : out STD_LOGIC); end halfsub_beh;

architecture Behavioral of halfsub_beh is begin diff<= a xor b; borrow<=a and(not b); end Behavioral;
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Experiment: 5(d)

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Experiment: 5(d)
AIM :- Design of Full Substractor TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity fullsub is Port ( a,b,bin : in STD_LOGIC; diff, borrow : out STD_LOGIC); end fullsub; architecture Behavioral of fullsub is begin diff<= (a xor b) xor bin; borrow<=(a and (not b))or (bin and (not(a xor b))); end Behavioral;

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Experiment: 6

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Experiment: 6
AIM :- Design of 3 : 8 Decoder TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dec3_8 is Port ( a : in STD_LOGIC_VECTOR (2 downto 0); y : out STD_LOGIC_VECTOR (7 downto 0)); end dec3_8; architecture Behavioral of dec3_8 is begin process(a)

begin case (a) is when"000" => y <= "00000001"; when"001" => y <= "00000010"; when"010" => y <= "00000100"; when"011" => y <= "00001000"; when"100" => y <= "00010000"; when"101" => y <= "00100000"; when"110" => y <= "01000000";
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when"111" => y <= "10000000"; when others => y <= "00000000"; end case; end process;

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Experiment: 7

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Experiment: 7
AIM :- Design of 8 : 3 Priority Encoder TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity parityencoder8_3 is Port ( a : in STD_LOGIC_VECTOR (7 downto 0); y : out STD_LOGIC_VECTOR (2 downto 0); valid : out STD_LOGIC); end parityencoder8_3;

architecture Behavioral of parityencoder8_3 is

begin process(a) begin

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valid<='1'; if (a(7)='1') then y<="111"; elsif (a(6)='1') then y<="110"; elsif (a(5)='1') then y<="101"; elsif (a(4)='1') then y<="100"; elsif (a(3)='1') then y<="011"; elsif (a(2)='1') then y<="010"; elsif (a(1)='1') then y<="001"; elsif (a(0)='1') then y<="000";

else y<="XXX"; end if; end process;

end Behavioral;end Behavioral;

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Experiment: 8

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Experiment: 8
AIM :- Design of 4 bit binary to grey code converter TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity binary2grey4bit is Port ( bin : in STD_LOGIC_VECTOR (3 downto 0); grey : out STD_LOGIC_VECTOR (3 downto 0)); end binary2grey4bit;

architecture Behavioral of binary2grey4bit is

begin process(bin) begin case bin is

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when "0000"=>grey<="0000"; when "0001"=>grey<="0001"; when "0010"=>grey<="0011"; when "0011"=>grey<="0010"; when "0100"=>grey<="0110"; when "0101"=>grey<="0111"; when "0110"=>grey<="0101"; when "0111"=>grey<="0100"; when "1000"=>grey<="1100"; when "1001"=>grey<="1101"; when "1010"=>grey<="1111"; when "1011"=>grey<="1110"; when "1100"=>grey<="1010"; when "1101"=>grey<="1011"; when "1110"=>grey<="1001"; when "1111"=>grey<="1000"; when others=>grey<="0000"; end case; end process;

end Behavioral;

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Experiment: 9

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Experiment: 9
AIM :- Design of 4 bit binary to BCD converter using sequential statement TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity bin2bcd_4 is Port ( bin : in STD_LOGIC_VECTOR (3 downto 0); bcd : out STD_LOGIC_VECTOR (4 downto 0)); end bin2bcd_4;

architecture Behavioral of bin2bcd_4 is

begin process(bin) begin case bin is

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when "0000"=>bcd<="00000"; when "0001"=>bcd<="00001"; when "0010"=>bcd<="00010"; when "0011"=>bcd<="00011"; when "0100"=>bcd<="00100"; when "0101"=>bcd<="00101"; when "0110"=>bcd<="00110"; when "0111"=>bcd<="00111"; when "1000"=>bcd<="01000"; when "1001"=>bcd<="01001"; when "1010"=>bcd<="10000"; when "1011"=>bcd<="10001"; when "1100"=>bcd<="10010"; when "1101"=>bcd<="10011"; when "1110"=>bcd<="10100"; when "1111"=>bcd<="10101"; when others=>bcd<="00000"; end case; end process;

end Behavioral;

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Experiment: 10

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Experiment: 10
AIM :- Design an 8 bit parity generator TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity paritygen_8 is Port ( d : in STD_LOGIC_VECTOR (7 downto 0); par : out STD_LOGIC); end paritygen_8;

architecture Behavioral of paritygen_8 is

begin process(d) variable pbit: std_logic;

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begin pbit:='0'; for i in 0 to 7 loop pbit:=pbit xor d(i); end loop; par<=pbit; end process; end Behavioral;

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Experiment: 11

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Experiment: 11
AIM :- Design of 2s complement for 8-bit number using generate statements TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity comp_8 is Port ( num : in STD_LOGIC_VECTOR (7 downto 0); comp : out STD_LOGIC_VECTOR (7 downto 0)); end comp_8;

architecture Behavioral of comp_8 is begin comp<= (not num)+1;

end Behavioral;

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Experiment: 12(a)

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Experiment: 12(a)
AIM :- Design of D flip-flop using sequential constructs TOOLS USED:- ISE Project Navigator,Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; entity d_ff is Port ( d,clk : in STD_LOGIC; q : out STD_LOGIC); end d_ff; architecture Behavioral of d_ff is begin process(clk) begin if clk'event and clk='1' then q<= d; end if; end process; end Behavioral;
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Experiment: 12(b)

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Experiment: 12(b)
AIM :- Design of T flip-flop using sequential constructs TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity t_ff is Port ( t,clk,rst : in STD_LOGIC; q,qbar : out STD_LOGIC); end t_ff;

architecture Behavioral of t_ff is

begin process(clk,rst) variable state:std_ulogic; begin if (rst='0') then

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elsif rising_edge(clk) then if t='1' then state:=not state; end if; end if; q<=state; qbar<=not state; end process; end Behavioral;

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Experiment: 12(c)
AIM :- Design of RS flip-flop using sequential constructs TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity rs_ff is Port ( r,s,clk,rst : in STD_LOGIC; qout : inout STD_LOGIC); end rs_ff; architecture Behavioral of rs_ff is begin process(clk) begin if clk' event and clk='1' then if rst='1' then qout <='0'; elsif r ='0'and s='0' then qout <= qout; elsif r ='1'and s='0' then qout <='0'; elsif r ='0'and s='1' then qout <='1'; elsif r ='1'and s='1' then
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qout <='Z'; end if; end if; end process; end Behavioral;

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Experiment: 12(d)
AIM :- Design of JK flip-flop using sequential constructs TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity JK_FF is Port ( j,k,clk,rst : in STD_LOGIC; qout : inout STD_LOGIC); end JK_FF; architecture Behavioral of JK_FF is begin process(clk) begin if clk' event and clk='1' then if rst='1' then qout <='0'; elsif j ='0'and k='0' then qout <= qout; elsif j ='1'and k='0' then qout <='1'; elsif j ='0'and k='1' then qout <='0'; elsif j='1'and k='1' then
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qout <='Z'; end if; end if; end process; end Behavioral;

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Experiment: 13
AIM :- Design of 8-bit shift register

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Experiment: 13
AIM :- Design of 8-bit shift register TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --library UNISIM; --use UNISIM.VComponents.all; entity univsr_8 is Port ( sin,sr_l,load,rst,clk : in STD_LOGIC; sout : out STD_LOGIC); end univsr_8; architecture Behavioral of univsr_8 is signal :std_logic_vector(7 downto 0); begin process(clk) begin ifrising_edge(clk)then ifrst='1' then s<=(others=>0); else if load<='1' then s<=(sin & s(7 downto 1)); else if (sr_1='1')then s<=(sin & s(7 downto 1)); else s<=(s(6 downto 0)& sin); end if; end if; if(sr_1='1')then sout<=s(0); else sout<=s(7); end if; end process; end Behavioral;
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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --library UNISIM; --use UNISIM.VComponents.all; entity univsr_8 is Port ( sin,sr_l,load,rst,clk : in STD_LOGIC; sout : out STD_LOGIC); end univsr_8; architecture Behavioral of univsr_8 is signal :std_logic_vector(7 downto 0); begin process(clk) begin ifrising_edge(clk)then ifrst='1' then s<=(others=>0); else if load<='1' then s<=(sin & s(7 downto 1)); else if (sr_1='1')then s<=(sin & s(7 downto 1)); else s<=(s(6 downto 0)& sin); end if; end if; if(sr_1='1')then sout<=s(0); else sout<=s(7); end if; end process; end Behavioral;

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Experiment: 14
AIM :- Design synchronous 4-bit Johnson counter

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Experiment: 14
AIM :- Design synchronous 4-bit Johnson counter TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity johnson_counter is Port ( clk,rst : in STD_LOGIC; dout :inout STD_LOGIC_vector(3 downto 0)); end johnson_counter; architecture Behavioral of johnson_counter is begin process(clk) begin if clk' event and clk='1' then if rst='1' then dout<="0000"; else dout<=(not dout(0)) & dout(3 downto 1); end if; end if; end process;
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end Behavioral;

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Experiment: 15(a)

AIM :- Design of Mod 3 counter

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Experiment: 15(a)
AIM :- Design of Mod 3 counter TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mod3_counter is Port ( clk,rst,din : in STD_LOGIC; dout : inout STD_LOGIC_vector(1 downto 0)); end mod3_counter; architecture Behavioral of mod3_counter is begin process(clk) begin if clk' event and clk='1' then if (rst='1') or (dout="10") then dout<="00"; else dout<= dout + 1; end if; end if; end process; end Behavioral;
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Experiment: 15(b)
AIM :- Design of Mod 5 counter TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity MOD5_COUNT is Port ( clk,rst : in STD_LOGIC; qout : inout STD_LOGIC_VECTOR (2 downto 0)); end MOD5_COUNT; architecture Behavioral of MOD5_COUNT is begin process(clk) begin if clk' event and clk='1' then if (rst ='1') or (qout ="100") then qout<="000"; else qout<= qout + 1; end if; end if; end process;
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Experiment: 15(c)
AIM :- Design of Mod 7 counter TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mod7_count is Port ( clk,rst : in STD_LOGIC; qout : inout STD_LOGIC_VECTOR (2 downto 0)); end mod7_count; architecture Behavioral of mod7_count is begin process(clk) begin if clk' event and clk='1' then if (rst='1') or (qout="110") then qout<="000"; else qout<= qout + 1; end if; end if; end process;
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Experiment: 15(d)
AIM :- Design of Mod 8 counter

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Experiment: 15(d)
AIM :- Design of Mod 8 counter TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mod8_count is Port ( clk,rst : in STD_LOGIC; qout : inout STD_LOGIC_VECTOR (2 downto 0)); end mod8_count; architecture Behavioral of mod8_count is begin process(clk) begin if clk' event and clk='1' then if (rst='1') or (qout="111") then qout<="000"; else qout<= qout + 1; end if; end if; end process; end Behavioral;
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Experiment: 15(e)
AIM :- DESIGN OF MOD 16 COU NTER

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Experiment: 15(e)
AIM :- Design of Mod 16 counter TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mod16_count is Port ( clk,rst : in STD_LOGIC; qout : inout STD_LOGIC_VECTOR (3 downto 0)); end mod16_count; architecture Behavioral of mod16_count is begin process(clk) begin if clk' event and clk='1' then if (rst='1') or (qout="1111") then qout<="0000"; else qout<= qout + 1; end if; end if; end process; end Behavioral;
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Experiment: 16
AIM :- Design a decimal up/down counter that counts up from 00 to 99 or down from 99 to 00

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Experiment: 16
AIM :- Design a decimal up/down counter that counts up from 00 to 99 or down from 99 to 00 TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity up_downcount is Port ( clk,rst,count : in STD_LOGIC; qout : inout STD_LOGIC_VECTOR (6 downto 0)); end up_downcount; architecture Behavioral of up_downcount is begin process(clk) begin if clk' event and clk='1' then if count = '0'then if (rst='1') or (qout="1100011") then qout<="0000000"; else qout<= qout + 1; end if; else if (rst='1') or (qout="0000000") then qout<="1100011";

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else qout<= qout - 1; end if; end if; end if; end process; end Behavioral;

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Experiment: 17
AIM :- Design 3-line to 8-line decoder with address latch

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Experiment: 17
AIM :- Design 3-line to 8-line decoder with address latch TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity dec3_8withlatch is Port ( x : in STD_LOGIC_VECTOR (2 downto 0); y : out STD_LOGIC_VECTOR (7 downto 0); latch : in STD_LOGIC); end dec3_8withlatch; architecture Behavioral of dec3_8withlatch is signal int:std_logic_vector(7 downto 0); begin process(x,latch) begin case (x) is when"000" =>int<="00000001"; when"001" =>int<="00000010"; when"010" =>int<="00000100"; when"011" =>int<="00001000"; when"100" =>int<="00010000"; when"101" =>int<="00100000"; when"110" =>int<="01000000"; when"111" =>int<="10000000";

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when others =>int<="00000000"; end case; if latch='1' then y<=int; end if; end process; end Behavioral;

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EXPERIMENT :18 RTL SCHEMATIC VIEW:

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Experiment: 18
AIM :- Design OF ALU TOOLS USED:- ISE Project Navigator, Modelsim VHDL CODES:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity alu_8 is Port ( a,b : in STD_LOGIC_VECTOR (7 downto 0); y : out STD_LOGIC_VECTOR (7 downto 0); sel : in STD_LOGIC_VECTOR (2 downto 0); l_a:in std_logic; cin : in STD_LOGIC); end alu_4; architecture Behavioral of alu_4 is signal arith,logic:std_logic_vector(7 downto 0); begin with sel(2 downto 0)select arith<=a when "000", a+1 when "001", a-1 when "010", b when "011", b+1 when "100",
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b-1 when "101", a+b when "110", a+b+cin when others; with sel(2 downto 0)select logic<=not a when "000", not b when "001", a and b when "010", a or b when "011", a nand b when "100", a nor b when"101", a xor b when "110", not(a xor b)when others; y<=arith when l_a='1' else logic ; end Behavioral;

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