TRAFFIC AND POWER REDUCTION ROUTING ALGORITHM FOR

NOC CORES

NAME

: SILAMBARASAN.R

VMP NO

: VMP 371

DEGREE

: M.E VLSI DESIGN

COLLEGE

: VELTECH MULTITECH DR. RANGARAJAN

DR. SAKUNTHALA ENGINEERING COLLEGE

ABSTRACT:
With the progress of VLSI technology, the number of cores on a chip keeps increasing, Now a
days we are increasing the processing level of the chip ,NOC is a best method to interconnect the
core with each other core on the chip, it reducing the overall chip power and Traffic level by sharing
the work load with other cores on the chip. And Dynamic Voltage Frequency Scaling (DVFS) is the
technique for monitoring the Frequency/Voltage level of each core of the chip and providing
sufficient power to the cores, ATPT is a Table that having (low and high) Frequency level table of
the Each core. ATPT has very high prediction accuracy system. Depends upon the data speed of the
core the voltage/frequency will be given by DVFS. If the core is in ideal state for a while, that core is
moved to low power mode.so the power of the each core will be reduced.

OBJECTIVE
The main objective of the project is to reduce the power consumption and the time taken
for processing when the work load of the core is high by sharing the workload with other cores in
the processor.
APPLICATION

Used in nanometer CMOS technology

Used in large and typical processors