CXA1082BQ(1/3)

********* IL08

SERVO SIGNAL PROCESSOR FOR CD

-TOP VIEW-

36
35
34
33
32
31
30
29
28
27
26
25
DGND
37 DVCC 24
(+5V)
38 23
39 22
40 21
41 20
42 AVEE 19
DVEE (-5V)
43 18
(-5V)
44 17
45 16
46 15
47 14
(+5V)

48 13
AVCC
1
2
3
4
5
6
7
8
9
10
11
12

PIN I/O SIGNAL PIN I/O SIGNAL PIN I/O SIGNAL PIN I/O SIGNAL
No. No. No. No.
1 I VC 13 I SL+ 25 I CLK 37 I DVCC
2 I FGD 14 O SLO 26 - DGND 38 I SPDL-
3 I FS3 15 I SL- 27 I BW 39 O SPDLO
4 I FLB 16 I SSTOP 28 I PDI 40 I WDCK
5 O FEO 17 I FSET 29 I ISET 41 I FOK
6 I FE- 18 O SENS 30 I VCOF 42 I MIRR
7 I SRCH 19 I AVEE 31 O 3.5V 43 I DVEE
8 I TGU 20 O C.OUT 32 O C864 44 I DFCT
9 I TG2 21 I DIRC 33 I LOCK 45 I TE
10 - AV CC 22 I XRST 34 I MDP 46 I TZC
11 O TAO 23 I DATA 35 I MON 47 I ATSC
12 I TA- 24 I XLT 36 I FSW 48 I FE
 CXA1082BQ(2/3)

1
VC
34
MDP
35 CLV
MON
36 LPF
FSW
39
38 SPDLO
SPDL-
27
BW
29
ISET
28
PDI
30
VCOF
16
SSTOP
VCO LOOP FILTER

3.5V REGULATOR V I
33
LOCK 31
25 3.5V
CLK 32
24 TTL C864
XLT
23
DATA I 2 L DATA REGISTER INPUT SHIFT REGISTER
22 I2 L
XRST ADDRESS DECODER
21
DIRC

40 SEQUENCER
WDCK TTL I2 L 20
41 C.OUT
FOK 18
42 2 OUTPUT DECODER SENS
MIRR I L TTL
44
DFCT
46
TZC
FS1-4 TG1-2 TM1-7 PS1-3
47 WINDOW
ATSC BPF
COMPARATOR
12
TA-
13
SL+
15
SL-

45 TRACKING TM6
TE
PHASE 14
COMPENSATION TM5 SLO
3
FS3
TM4
8
TGU
9 TM3
TG2
10 11
AVCC TAO
48 FOCUS
FE
PHASE
COMPENSATION
2
FGD

4
FLB
5
6 FEO
FE- 26
7 DGND
SRCH
17
FSET
19
AVEE
37
DV CC
43
DV EE
 CXA1082BQ(3/3)

34 39
MDP SPDLO
35 INPUT
MON
36 ATSC ;WINDOW COMPARATOR INPUT PIN FOR ATSC DETECTION.
FSW BW ;TIME CONSTANT EXTERNAL PIN FOR LOOP FILTER.
38
SPDL- CLK ;SERIAL DATA TRANSFER CLOCK INPUT FROM CPU.
DATA ;SERIAL DATA INPUT FROM CPU.
27 31 DFCT ;DEFECT SIGNAL INPUT.
BW 3.5V DIRC ;PIN FOR ONE-TRACK JUMP.
29 32
ISET C864 FE ;INPUT FOR FOCUS ERROR.
28 FE- ;INVERSE INPUT PIN FOR FOCUS AMPLIFIER.
PDI
30 FGD ;CONNECT A CAPACITOR BETWEEN THIS PIN AND
VCOF PIN 3 TO REDUCE HIGH-FREQUENCY GAIN.
FLB ;TIME CONSTANT EXTERNAL PIN TO RAISE THE
33 20 LOW BANDWIDTH OF THE FOCUS SERVO.
LOCK C.OUT
25 18 FOK ;FOCUS OK SIGNAL INPUT.
CLK SENS FS3 ;THE HIGH-FREQUENCY GAIN OF THE FOCUS
24
XLT SERVO IS SWITCHED THROUGH FS3 ON AND OFF.
23 FSET ;PIN TO SET PEAK FREQUENCY OF FOCUS TRACKING
DATA
22 PHASE COMPENSATION AND FC OF CLV LPF.
XRST FSW ;TIME CONSTANT EXTERNAL PIN FOR CLV SERVO ERROR SIGNAL
21
DIRC ISET ;CURRENT IS INPUT TO DETERMINE FOCUS SEARCH,
40 TRACK JUMP,AND SLED KICK HEIGHT.
WDCK
41 LOCK ;AT”L”SLED RUNAWAY PREVENTION CIRCUIT OPERATES.
FOK MDP ;MDP SIGNAL INPUT.
42
MIRR MIRR ;MIRR SIGNAL INPUT.
MON ;MON SIGNAL INPUT.
44 PDI ;PDO SIGNAL INPUT.
DFCT SL+ ;NON-INVERSE INPUT PIN FOR SLED AMPLIFIER.
46
TZC SL- ;INVERSE INPUT PIN FOR SLED AMPLIFIER.
47 SPDL- ;INVERSE INPUT FOR SPINDLE DRIVE AMP.
ATSC
16 SRCH ;TIME CONSTANT EXTERNAL PIN FOR THE
SSTOP FORMATION OF FOCUS SEARCH WAVEFORMS.
SSTOP ;LIMIT SW ON/OFF SIGNAL DETECTION PIN FOR
12 14 DISC INNER PERIPHERY DETECTION.
TA- SLO
13 TA- ;INVERSE INPUT PIN FOR TRACKING AMPLIFIER.
SL+ TE ;TRACKING ERROR SIGNAL INPUT.
15
SL- TG2 ;TIME CONSTANT EXTERNAL PIN FOR
THE SELECTION OF TRACKING HIGH BAND GAIN.
45 11 TGU ;TIME CONSTANT EXTERNAL PIN FOR
TE TAO THE SELECTION OF TRACKING HIGH BAND GAIN.
3
FS3 TZC ;INPUT FOR TRACKING ZERO-CROSS COMPARATOR.
8 VCOF ;VCO FREQUENCY CONTROL.
TGU
9 WDCK ;CLOCK INPUT FOR AUTO.
TG2 XLT ;LATCH INPUT FROM CPU.
XRST ;RESET INPUT PIN,RESET AT”L”
48 5
FE FEO
2 OUTPUT
FGD C864 ;8.64MHz VCO OUTPUT
4
FLB C.OUT ;TRACK NUMBER COUNT SIGNAL OUTPUT.
6 FEO ;FOCUS DRIVE OUTPUT.
FE-
7 SENS ;OUTPUTS FZC,AS,TZC,SSTOP AND BUSY THROUGH COMMAND FROM CPU.
SRCH SLO ;SLED DRIVE OUTPUT.
17
FSET SPDL ;SPINDLE DRIVE OUTPUT.
TAO ;TRACKING DRIVE OUTPUT.