V15 Apex Precision Power Databook (Complete)

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For product selection assistance
or technical support with Apex
Precision Power products
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or contact the Cirrus Logic
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sales representatives and
distributors, please visit the
Contacts page at www.cirrus.com.
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0 2 3 5 - V15 - DB - AP P
Product Data Book
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VOLTAGE REFERENCES
HI GH VOLTAGE, HI GH CURRENT
PWM AMPLI FI ERS
LI NEAR AMPLI FI ERS
HI GH SPEED LI NEAR AMPLI FI ERS
EVALUATI ON KI TS
ACCESSORI ES
PACKAGI NG
APPLI CATI ON NOTES
Product Innovation from Cirrus Logic
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POWER ANALOG ICs,
MODULES AND HYBRIDS
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.15
.09
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.01
.02
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.04
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.07
10
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50
40
30
20
15
.2
.9
6
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1.5
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2.5
3.5
.8
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.5
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.7
38 50 44 56 700 7280 90 100 200 150 300 350 450 600 900 1200
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Supply Voltage
.015
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38 50 44 56 700 7280 90 100 200 150 300 350 450 600 900 1200
MSA240
MSA260
MP39
MP103
MP108
MP230
MP240
MP111
MP38A
MP39A MP108A
MP38
MP400
SA08
SA60
SA01
SA09
SA50
SA03
SA12
SA57
SA306
SA57A
SA306A
SA53
SA303
PA51A
PA16
PA02
PA73
PA01
PA74
PA76
PA09
PA51
PB50
PA04
PA12A
PA93
PA92
PB51A
PB58A
PA74A
PA76A
PA61
PA61A
PA13
PA12
PA13A
PA10
PA05
PA50
PA50A
PA52
PA52A
PA03
PA89
PA94
PA95
PA84
PA90
PA88
PA83
PA08
PA08V
PA78
PA79
PA81J
PA82J
PA97
PA96
PB51
PB58
PA15
PA15A
PA85
PA91
PA98
PA07
PA10A
PA119
PA12H
PA60
PA75
PA69
PA86
PA162
PA240/PA241/PA243
PA107
Linear Switching Open Frame
Linear
Open Frame
Switching
LEARN MORE AT
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PRECI SION POWER ANALOG DESIGN TOOLS
Cirrus Logic provides customers with dedicated technical support for its family of Apex Precision Power

products. Our team of power analog applications engineers has developed a comprehensive set of design
tools that put a wealth of circuit design expertise right on your desktop.
PRECI SION POWER ANALOG TECHNI CAL SEMINAR
A how to learning tool addressing real world power analog technical issues and product applications.
PRECI SION POWER DESIGN SOFTWARE
A self-documenting spreadsheet program simplifies and automates painstaking calculations and graphical
interpretations required to design power analog circuits.
EE FRIEND DESIGN SOFTWARE
A supplement to the Precision Power Design Software, this tool combines lookup tables and formulas
with the ability to calculate values for a specific application.
SPI CE MODELS
SPICE models available for both linear and PWM amplifiers.
PRECI SION POWER DESIGN LIBRARY
An in depth library of technical articles
and white papers covering a broad list of
design topics based on more than two
decades of customer and product applica-
tions support.
CONTACT US
For product selection assistance or techni-
cal support with Apex Precision Power
products, call 800-546-2739 (in the US
and Canada), via email at apex.support@
cirrus.com, or contact the Cirrus Logic
office in your region. For a complete list of
Cirrus Logic sales representatives and dis-
tributors, please visit the Contacts page at
www.cirrus.com.
PRODUCT SELECTOR MATRI X AMPLIFIERS
Product
Data Book
Volume
15
POWER ANALOG ICs,
MODULES AND HYBRIDS
Accessories, Product Marking,
Packaging Outlines
Evaluation Kits
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Applications Notes
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Subject Index, Application Note
Cross Reference
I H I
Linear Ampliers, Power Boosters
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PWM Ampliers
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Voltage References
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Quality, Grade Comparisons,
Screening Programs, RoHS
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General Information, Customer Service,
Table of Contents
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LEARN MORE AT
www.cirrus.com
2 General Information
CIRRUS LOGIC
APEX PRECISION POWER
T +1-520-690-8600
F +1-520-888-3329
Toll-Free +1-800-546-2739
apex.support@cirrus.com
Copyright 2009 Cirrus Logic, Inc.
All rights reserved
Printed in the USA
Cirrus Logic, Inc. and its subsidiaries (Cirrus) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is
provided as is without warranty of any kind (expressed or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information
being relied upon is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty,
indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, or for infringement of patents or other rights of third parties. This document is the
property of Cirrus and, by furnishing this information, Cirrus grants no license, express or implied, under any patents, mask work rights, copyrights, trademarks, trade secrets, or other intellectual
property rights. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) unless distributed in its entirety with all copyright notices attached. No part of this publication may be used as a basis for manufacture or sale of any items without the prior written
consent of Cirrus.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (critical applications). Cirrus products are
not designed, authorized, or warranted to be suitable for use in products surgically implanted into the body, automotive safety or security devices, life-support products or other critical applica-
tions. Inclusion of Cirrus products in such applications is understood to be fully at the customers risk and Cirrus disclaims and makes no warranty of merchantability and fitness for particular pur-
pose, with regard to any Cirrus product that is used in such a manner. If the customer uses or permits the use of Cirrus products in critical applications, customer agrees, by such use, to fully
indemnify Cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys fees and costs, that may result from or arise in connection with
these uses.
Cirrus Logic, Cirrus, the Cirrus Logic logo, Cirrus Rocks, Innovation That Rocks, Apex Precision Power, Apex, and the Apex Precision Power logo designs are the trademarks of Cirrus Logic, Inc. All
other brand and product names in this document may be trademarks or service marks of their respective owners.
General Information 3
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SECTION B Quality, Grade Comparisons,
Compliance
SECTION C Voltage References
SECTION A General Information, Customer
Service, Table of Contents
TABLE OF CONTENTS
SWR200 .................................................................................................................................26
VRE100, VRE101, VRE102 ...................................................................................................30
VRE104 ..................................................................................................................................35
VRE107 ..................................................................................................................................39
VRE117, VRE119 ...................................................................................................................43
VRE202 ..................................................................................................................................47
VRE204 ..................................................................................................................................51
VRE205 ..................................................................................................................................55
VRE210 ..................................................................................................................................59
VRE302 ..................................................................................................................................63
VRE304 ..................................................................................................................................67
VRE305 ..................................................................................................................................71
VRE306 ..................................................................................................................................75
VRE310 ..................................................................................................................................79
VRE405 ..................................................................................................................................83
VRE410 ..................................................................................................................................87
VRE505 ..................................................................................................................................91
VRE3025 ................................................................................................................................95
VRE3050 ..............................................................................................................................101
VRE4112, VRE4125, VRE4141 ............................................................................................107
ISO9001 and MIL-PRF-38534 Certifcates .............................................................................12
Grade Comparisons ...............................................................................................................13
SMD Grade Availability ...........................................................................................................14
RoHS Compliance ..................................................................................................................15
M and /883 Screening Program..............................................................................................17
Reactance Chart.....................................................................................................................23
Table of Contents......................................................................................................................3
Customer Service: Technical Support, How To Order Samples, Production Orders ................8
Cirrus Logic Mission .................................................................................................................9
Section
A
Section
B
Section
C
SECTION D PWM Amplifers
SECTION E Linear Amplifers, Power Boosters
TABLE OF CONTENTS
Product Selector Matrix - Hybrids .........................................................................................212
Product Selector Matrix - ICs................................................................................................213
Product Selector Matrix - Open Frame Modules ..................................................................214
Open Frame Product Design Technology .............................................................................215
Equivalent/Second sources ..................................................................................................216
LINEAR AMPLIFIERS
MP38, MP38A.......................................................................................................................217
MP39, MP39A.......................................................................................................................221
MP103 ..................................................................................................................................225
MP108, MP108A...................................................................................................................230
MP111, MP111A ....................................................................................................................234
MP230 ..................................................................................................................................238
MP240 ..................................................................................................................................244
MP400FC .............................................................................................................................250
PA01, PA73 ..........................................................................................................................262
PA73M/883 ...........................................................................................................................266
PA02, PA02A ........................................................................................................................267
PA02M/883 ...........................................................................................................................271
PA02 Design Ideas ...............................................................................................................272
PA03, PA03A ........................................................................................................................274
PA04, PA04A ........................................................................................................................279
PA05, PA05A ........................................................................................................................283
PA07, PA07A ........................................................................................................................287
PA07M/883 ...........................................................................................................................291
PA08, PA08A ........................................................................................................................292
PA08M/883 ...........................................................................................................................296
PA08V ...................................................................................................................................297
PA09, PA09A ........................................................................................................................298
PA09M/883 ...........................................................................................................................303
PA10, PA10A ........................................................................................................................304
Product Selector Matrix - PWM ............................................................................................ 116
MSA240 ................................................................................................................................ 117
MSA260 ................................................................................................................................121
SA01 SA01-6 .....................................................................................................................128
SA03 .....................................................................................................................................132
SA08 .....................................................................................................................................136
SA09 .....................................................................................................................................140
SA12 .....................................................................................................................................146
SA50CE ................................................................................................................................150
SA53 .....................................................................................................................................154
SA57 SA57A ......................................................................................................................166
SA60 .....................................................................................................................................178
SA303 ...................................................................................................................................183
SA306 SA306A ..................................................................................................................196
Section
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Section
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SECTION E Cont.
TABLE OF CONTENTS
PA10M/883 ...........................................................................................................................308
PA12, PA12A ........................................................................................................................309
PA12M/883 ...........................................................................................................................313
PA12H ..................................................................................................................................314
PA13, PA13A ........................................................................................................................315
PA15FL, PA15FLA ................................................................................................................322
PA16, PA16A ........................................................................................................................326
PA50, PA50A ........................................................................................................................332
PA51, PA51A ........................................................................................................................336
PA51M/883 ...........................................................................................................................340
PA52, PA52A ........................................................................................................................341
PA60EU ................................................................................................................................345
PA61, PA61A ........................................................................................................................349
PA61M/883 ...........................................................................................................................353
PA69 .....................................................................................................................................354
PA74, PA76, PA74A, PA76A .................................................................................................362
PA74M ..................................................................................................................................366
PA75 .....................................................................................................................................367
PA75 Design Ideas ...............................................................................................................371
PA78 .....................................................................................................................................372
PA79 .....................................................................................................................................382
PA81J , PA82J .......................................................................................................................392
PA83, PA83A ........................................................................................................................396
PA83M/883 ...........................................................................................................................400
PA84, PA84A, PA84S ...........................................................................................................401
PA84M/883 ...........................................................................................................................405
PA85, PA85A ........................................................................................................................406
PA85M ..................................................................................................................................410
PA86 ..................................................................................................................................... 411
PA88, PA88A ........................................................................................................................419
PA89, PA89A ........................................................................................................................423
PA90 .....................................................................................................................................427
PA91 .....................................................................................................................................432
PA92 .....................................................................................................................................437
PA93 .....................................................................................................................................442
PA94 .....................................................................................................................................447
PA95 .....................................................................................................................................453
PA96 .....................................................................................................................................458
PA97DR ................................................................................................................................462
PA98, PA98A ........................................................................................................................467
PA107DP ..............................................................................................................................473
PA119CE, PA119CEA ...........................................................................................................480
PA162 ...................................................................................................................................485
PA240 ...................................................................................................................................491
PA241 ...................................................................................................................................496
PA241M ................................................................................................................................502
CPA241 ................................................................................................................................503
PA243 ...................................................................................................................................504
POWER BOOSTERS
PB50 .....................................................................................................................................509
PB51, PB51A ........................................................................................................................513
PB58, PB58A ........................................................................................................................517
Section
E
SECTION F Evaluation Kits
SECTION G Accessories, Product Marking,
Package Outlines
TABLE OF CONTENTS
KIT SUPPORTED PART(s)
EK01 ............................SA01 ................................................................................................. 522
EK03 ............................SA03 ................................................................................................. 526
EK06 ............................SA60 ................................................................................................. 529
EK07 ............................SA07 ................................................................................................. 531
EK09 ............................CE (TO-3), CR, CU, DC, DD (MO-127) Packages ........................... 534
EK11 ............................PA90, PA91, PA98 ............................................................................ 537
EK13 ............................PA241DF .......................................................................................... 539
EK14 ............................PA13, PA16 ...................................................................................... 541
EK15 ............................SA08 ................................................................................................. 543
EK16 ............................PA90, PA91, PA92, PA93, PA98 ....................................................... 546
EK17 ............................SA12 ................................................................................................. 550
EK19 ............................PA94, PA95 ...................................................................................... 553
EK21 ............................PA74 ................................................................................................. 555
EK26 ............................PA60EU ............................................................................................ 559
EK27 ............................PA50, PA52 ...................................................................................... 561
EK28 ............................PA97DR ............................................................................................ 564
EK29 ............................PB51 ................................................................................................. 566
EK33 ............................PA75CX ............................................................................................ 569
EK34 ............................PA240CX .......................................................................................... 571
EK42 ............................PA15FL, PA241DW .......................................................................... 573
EK50 ............................PB50, PB58 ...................................................................................... 574
EK51 ............................DF Packages (24-pin PSOP) ........................................................... 576
EK52 ............................MP230, MP240................................................................................. 578
EK56 ............................MSA240, MSA260 ............................................................................ 582
EK57 ............................MP108, MP111 ................................................................................. 586
EK59 ............................MP38, MP39 ..................................................................................... 590
EK60 ............................PA78EU ............................................................................................ 594
EK61 ............................PA78DK, PA79DK ............................................................................ 597
EK65 ............................MP400 .............................................................................................. 600
EK71 ............................PA107DP .......................................................................................... 604
EK-SA50 ......................SA50CE ............................................................................................ 608
DB53R .........................SA53-IHZ .......................................................................................... 609
DB63R .........................SA57-IHZ .......................................................................................... 614
DB64R .........................SA306-IHZ ........................................................................................ 619
DB303R .......................SA303-IHZ ........................................................................................ 624
Section
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Section
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Accessories ..........................................................................................................................630
Product Marking ...................................................................................................................651
Package Outlines and Dimensions.......................................................................................659
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SECTION H Application Notes
SECTION I Subject Index .................................................... 955
TABLE OF CONTENTS
Application Notes Cross Reference...................................................................................... 678
AN01........ General Operating Considerations ..................................................................... 679
AN02........ Optoelectronic Position Control .......................................................................... 692
AN03........ Bridge Circuit Drives ........................................................................................... 694
AN05........ Precision Magnetic Defection............................................................................. 697
AN06........ Applying the Super Power PA03 ......................................................................... 701
AN07........ Progammable Power Supplies............................................................................ 707
AN08........ Optimizing Output Power .................................................................................... 709
AN09........ Current Limiting................................................................................................... 713
AN10........ Power Amp Output Impedance ........................................................................... 716
AN11 ........ Thermal Techniques ............................................................................................ 717
AN13........ Voltage to Current Conversion ............................................................................ 721
AN14........ Power Booster Applications ................................................................................ 724
AN16........ SOA Advantages of MOSFETs ........................................................................... 727
AN17........ Wideband, Low Distortion Techniques ................................................................ 730
AN19........ Stability for Power Operational Amplifers ........................................................... 733
AN20........ Bridge Mode Operation of Power Operational Amplifers ................................... 753
AN21........ Single Supply Operation of Power Operational Amplifers .................................. 757
AN22........ SOA and Load Lines ........................................................................................... 763
AN24........ Brush Type DC Motor Drive with Power Op-Amps ............................................. 768
AN25........ Driving Capacitive Loads .................................................................................... 770
AN26........ Parallel Connection ............................................................................................. 789
AN28........ Proper Analog Wiring for Power Operational Amplifers ..................................... 792
AN30........ PWM Basics ........................................................................................................ 794
AN31........ Operational Amplifer Basics ............................................................................... 802
AN32........ PWM Low Pass Filtering ..................................................................................... 804
AN33........ Spice Model and PWM Amplifer Applications .................................................... 814
AN37........ Power Dissipation the Easy Way ........................................................................ 819
AN38........ Loop Stability with Reactive Loads ..................................................................... 827
AN39........ Filters and Power Dissipation for PWMs............................................................. 837
AN41........ Stablility and Biasing for PWM Amplifers ........................................................... 847
AN43........ Heatsinks, Mating Sockets, Washers, Vendors .................................................. 863
AN44........ Driving Piezoelectric Actuators ........................................................................... 868
AN45........ Driving 3-Phase Brushless Motors...................................................................... 880
AN46........ 3-Phase Switching Amplifer - SA306-IHZ .......................................................... 890
AN47........ Techniques for Stabilizing Power Operational Amplifers .................................... 903
AN48........ Increasing Output Swing in Power Operational Amplifers.................................. 914
AN49........ Jumper Confgurable 100 Watt+ DC-to-DC Converter
Fulflls Buck-Boost & Motor Drive Roles ............................................................. 923
AN50........ Optimizing Power Delivery in PWM Motor Driver ICs ......................................... 930
AN51........ Thermal Modeling of Power Devices in a Surface Mount Confguration............. 946
Technical Seminar ................................................................................................................ 952
Power Design Software Tools, Spice Models ....................................................................... 953
Power Design Technical Library ........................................................................................... 954
Section
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Section
H
TECHNICAL SUPPORT AND CUSTOMER SERVICE
PRODUCT TECHNICAL SUPPORT
For product selection assistance, design suggestions, schematic review and
circuit debugging with Apex Precision Power products, contact our team
of dedicated power analog applications engineers.
Call Toll-Free +1-800-546-2739
eMail apex.support@cirrus.com
SALES SUPPORT
Sales support for Apex Precision Power products from Cirrus Logic is provided by our extensive
network of worldwide third party sales representatives and distributors. Sample requests, pric-
ing information and product volume orders can be obtained online under Sales Support at
www.cirrus.com.
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CORPORATE MISSION
Cirrus Logic provides innovative, high-performance analog and digital signal
processing components that rock (advance our customers, benefit our
shareholders and reward our employees)
To exceed our customers expectations
Deliver solid value to our shareholders
Build confidence and pride in our company
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ISO9001 and MIL-PRF-38534 Certifcates ............................................12
Grade Comparisons ..............................................................................13
SMD Grade Availability ..........................................................................14
RoHS Compliance .................................................................................15
M and /883 Screening Program.............................................................17
Reactance Chart....................................................................................23
Screening Program ,
RoHS Compliance
Screening Program ,
RoHS Compliance
12
ISO9001 and MIL-PRF-38534 Certifcates
See www.cirrus.com for current ISO9001 and MIL-PRF-38534 Certifcates
Industrial and Military Products
Certifications
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Grade Comparisons
Quick Reference Guide
Grade Comparisons
Apex Precision Power
TM
Products Grade Comparisons:
Industrial, Non-Compliant M , /883 Military Grade
TM
products from Cirrus Logic are available in different levels of quality screening: INDUS-
TRIAL, NON-COMPLIANT MILITARY or M, and M/883 COMPLIANT MILITARY. All INDUSTRIAL grade products
are 100% static and dynamic tested at +25C. MILITARY grade product is 100% tested over the products respec-
tive full temperature range for both static and dynamic parameters. Below is a re-cap of the static and dynamic test
operations performed for each available grade.
OPERATION INDUSTRIAL
NON-COMPLIANT
M
/883 COMPLIANT
MILITARY
Clean Room Procesing Yes Yes Yes
Clean Room Testing Yes Yes Yes
Solder Integrity Testing Yes Yes Yes
Wire Bond Integrity Yes Yes Yes
All Processing Under Document Control Yes Yes Yes
High Power Die Inspection No Yes Yes
Processed on Military Line Yes Yes Yes
Maximum Number of Re-work Cycles Specifed:
Solder Yes Yes Yes
Epoxy No Yes Yes
Wirebond Yes Yes Yes
Pre-cap Visual Sample 100% 100%
Pre-seal Vacuum Bake Yes Yes Yes
Welded in Controlled Atmosphere
2
Yes Yes Yes
Each Unit Checked for Hermeticity
2
No Yes Yes
Temperature Cycle:
-65C to +150C for 10 cycles
No Yes Yes
Constant Acceleration Condition 5000G No Yes Yes
Burn-In: 160 hours @ TC = 125C No Yes Yes
Dynamic Testing +25C 55C, +25C, +125C 55C, +25C, +125C
External Visual Yes Yes Yes
Pin Finish Ni or Solder Solder Solder
1
Open Frame, Hybrid models
2
Metal Packaged Hybrid models
14
SMD Grade Availability
Industrial and Military Products
SMD Grade Availability
Several Apex Precision Power
TM
products from Cirrus Logic are available with Standard Military Drawing (SMD)
numbers. Below is a sample listing. Please check online at www.cirrus.com for updates.
BASE MODEL STOCKED SMD #
PA02 5962-9067901HXA
PA07 5962-9063801HXA
PA08 5962-9072301HXA
PA09 5962-9170001HXA
PA10 5962-9082801HXA
PA12 5962-9065901HXA
PA51 5962-8762001,02YA
PA83 5962-9162101HXA
PA84 5962-9073601HXA
15
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RoHS Compliance
RoHS Compliance
Cirrus Logic is actively committed to our role in protecting the environment by reducing the amount of hazardous
substances in our products. As a member of JEDEC, the semiconductor standardization body of the Electronics
Industries Alliance (EIA), Cirrus Logic is working with customers and suppliers to comply with industry standards.
The European Union has enacted legislation (Directive 2002/95/EC) effective July 1st, 2006, that restricts the use
of Lead, Cadmium, Mercury, Hexavalent Chromium, Poly-Brominated Bi-Phenyls (PBB), and Poly-Brominated Di-
Phenyl Ethers (PBDE) in a wide variety of electronic products and applications.
RoHS Compliant Devices
The following Apex Precision Power
TM
devices are RoHS compliant as of the date code listed. Please refer to the
Quality/RoHS area for Apex Precision Power products at www.cirrus.com for the most current information regard-
ing RoHS complaint status.
RoHS Compliant Monolithic Devices
TM
monolithic devices are RoHS compliant sice release:
RoHS Compliance
Model Package
PA60EU 12 Pin Plastic SIP
PA75CC 7DDPAK
PA75CD 7TO220
PA75CX 7TO220 SL
PA78DK 12 Pin PSOP
PA79DK 12 Pin PSOP
Model Package
PA162DK 20 Pin PSOP
PA240CC 7DDPAK
PA240CX 7TO220 SL
CPA241 Die
PA241CE TO-3
PA241DF 24 Pin PSOP
PA243DF 24 Pin PSOP
Model Package
SA53-IHZ 64 Pin QFP
SA57-IHZ 64 Pin QFP
SA57A-FHZ 64 Pin QFP
SA303-IHZ 64 Pin QFP
SA306-IHZ 64 Pin QFP
SA306A-FHZ 64 Pin QFP

RoHS Compliant Hybrid Devices
TM
hybrid devices from Cirrus Logic are RoHS compliant in both standard
and A grades (e.g. the PA51 is listed; therefore, the PA51 and the PA51A are both compliant). For listed Voltage
Regulators (VRE###), any devices listed are compliant in all grades (e.g. VRE100 is listed; therefore VRE100C,
VRE100CA, VRE100M and VRE100MA are all compliant). Unless otherwise noted by a date, all devices below
have been compliant since July 1, 2006, or earlier:
PA01 PA02 PA04 PA05 PA07 PA08 PA08V
PA09 PA10 PA12 PA12H PA50 PA51 PA52
PA61 PA74 PA76 PA81J PA82J PA83 PA84
PA85 PA88 PA89 PA90 (5/25/09) PA91 (5/25/09) PA92 (5/25/09) PA94 (1/15/09)
PA95 (5/25/09) PA96CE PA119 PB50 PB51 (5/25/09) PB58 SA01
SA03 SA08 SA09
(since
release)
SA12 SA60 (5/25/09) SWR200 VRE100
VRE101 VRE102 VRE104 VRE107 VRE117 VRE119 VRE202
VRE4112 VRE4125 VRE4141
Non-RoHS Compliant Hybrid Devices
TM
devices are not currently offered in a RoHS compliant package:
PA03 PA12A-S PA13 PA15FL PA16 PA93 PA97DR PA98
PA241DW SA50CE
16
Non-RoHS Compliant Open Frame Products
TM
MP38CL MP39CL MP108FL MP111FL MP230FC MP240FC MSA240KC MSA260KC
RoHS Compliant Accessories
TM
accessories are RoHS compliant:
DB53R DB63R DB64R DB303R CLAMP02 CLAMP04 CLAMP05 HS01
HS02 HS03 HS04 HS05 HS06 HS09 HS11 HS13
HS14 HS16 HS18 HS20 HS21 HS22 HS23 HS26
HS27 HS28 HS29 HS31 HS32 HS33 MS02 MS03
MS04 MS05 MS06 TW03 TW05 TW07 TW09 TW10
TW12 TW13 TW14
Non-RoHS Compliant Accessories
TM
EK01 EK03 EK06 EK07 EK09 EK11 EK13 EK14
EK57 EK59 EK60 EK61 EK65 EK-SA50 HK26 HS24
MS11
Additional Information Regarding RoHS Compliance
1. Cirrus Logic is working on qualifying the following PSIP line of products to RoHS compliant versions by 9/30/09:
PA13, PA15FL, PA16, PA93 and PA98. Other PSIP products will be introduced in RoHS compliant versions at a
later date (PA241DW and PA97DR).
2. Due to the high power performance of Apex Precision Power products, a signifcant number of customer ap-
plications involve large-scale stationary industrial tools. The use of APEX products in large scale industrial tools
is exempt under the RoHS directive, even if the product contains levels of RoHS prohibited materials higher than
otherwise allowed. Please refer to websites such as www.pb-free.info/rohsexemptions.htm for specifc details
regarding this exemption.
3. At this time, Cirrus anticipates that certain APEX models will remain non-compliant due to physical or customer
requirements. These models include PA03, PA03A, M/883 compliant devices, and M grade devices (except for
VRE series M grades).
4. Cirrus understands the lead and cadmium used in thickflm hybrid applications (except for the VRE/SWR series)
is exempt per points 5 and 38 respectively of the 2002/95/EC Annex. The VRE/SWR series are similarly exempt
per points 5 and 8 of the 2002/95/EC Annex.
Disclaimer
Cirrus Logic will continue to pursue reasonable steps in providing representative and accurate information regard-
ing product compliancy with the RoHS Directive. To the maximum extent permitted by law, Cirrus Logic shall not be
liable for any indirect, special, incidental, consequential or any other exemplary damages arising out of the informa-
tion provided herein, or arising out of its provision of non-RoHS compliant electronic products or materials.
Additional Assistance
For questions regarding the RoHS compliance status of Apex Precision Power
TM
products, please contact the Cirrus
Logic Quality Engineering Team for Apex Precision Power products at apex.quality@cirrus.com.
RoHS Compliance
17
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M and /883 Screening Program
M/883
DESCRIPTION
TM
products from Cirrus Logic have been screened to MIL-PRF-38534, Class H and manu-
factured in a DSCC Certifed Facility using the baseline documents listed herein. These products provide a high
reliability product option and satisfy the requirements for components used in airborne and ground-based military
applications. Compliance with these requirements is signifed by the /883 suffx in the model number. Non-com-
pliant version is identifed using M only in the model number.
Complete description of an APEX M or /883 product consists of the following:
1. Industrial Grade Data Sheet (i.e. PA02/PA02A).
This contains Typical Characteristics and Performance Graphs.
2. M Data Sheet (i.e. PA02M).
This is the Table 4 Group A Inspection which defnes the parameters and limits that the product must meet
when tested over the full military case temperature range of 55C to +125C.
3. /883 Screening Program Data Sheet (i.e. this document).
This defnes the manufacturing processes and screening steps for an M or /883 product. (Refer to Figure 1
for order of fow.)
4. Package and Accessories Information Data Sheet
This contains the package outline dimensions (i.e. 8-pin TO-3).
All applications data and performance optimization suggestions given for the Industrial product apply to the "M"
or "/883" versions of a given product family as well. Package outlines are identical except that the "M" or "/883"
grade pins are hot solder dipped over nickel plating to meet the solderability requirements of MIL-STD-883,
Method 2003.
QML-38534 FACILITY APPROVAL STATUS
The Cirrus Logic manufacturing facility for Apex Precision Power products in Tucson, AZ, USA, is a DSCC certifed
and qualifed QML-38534 facility. Certifcation has been maintained since November 8, 1989, and a QML listing as
of May 31, 1990.
CONSTRUCTION
These power products have been built and assembled using standard compliant hybrid processes including high
temperature solder and conductive epoxy. A metallized ceramic (beryllia) substrate has thickflm resistors, thickflm
gold conductors and thickflm silver conductor. Die to substrate and pin to substrate wirebonds are aluminum. The
package is hermetically sealed using resistance welding in a dry nitrogen atmosphere.
1.0 APPLICABLE DOCUMENTS
1.1 SPECIFICATIONS
MIL-PRF-38534 General Specifcation for Hybrid Microcircuits
1.2 STANDARDS
MIL-STD-883 Test Methods and Procedures for Microelectronics
1.3 BASELINE DOCUMENTS
Cirrus Logic maintains on fle the procedures, process specifcations and process qualifcation reports that are in
general the documents which have established the baseline for Cirrus Logic in satisfying the requirements of certi-
fcation in accordance with Appendix D of MIL-PRF-38534.
1.4 PERFORMANCE SPECIFICATIONS
The performance specifcations for a particular M or /883 hybrid circuit are contained in the following documents:
1. Industrial Grade Data Sheet (i.e. PA02/PA02A).
This contains Typical Characteristics and Performance Graphs.
2. M Data Sheet (i.e. PA02M).
This is the Table 4 Group A Inspection which defnes the parameters and limits that the product must meet
when tested over the full military case temperature range of -55C to +125C.
18
In the event of conficting requirements, the order of precedence will be: purchase order, customers SCD, the
APEX M data sheet, and other reference documents.
2.0 GENERAL REQUIREMENTS
The individual requirements are specifed herein and in accordance with the applicable APEX M data sheet. The
static and dynamic electrical performance requirements for the hybrid circuit and test conditions are as specifed in
the applicable APEX M data sheet.
2.1 PROCESS CONDITIONING, TESTING, RELIABIITY, and QUALITY ASSURANCE
SCREENING
Process conditioning, screening and testing are as specifed in Section 4.0. Figure 1 illustrates the process fow for
M or /883 products processed to MIL-PRF-38534, Class H.
2.1.1 PRODUCT or PROCESS CHANGE
Cirrus Logic will not implement any major change, as listed in MIL-PRF-38534, to the design, materials, construc-
tion, confguration, or manufacturing process which may affect the performance, quality, reliability, or interchange-
ability of the circuit without full or partial re-qualifcation. M product is a HI-REL non-compliant product.
2.2 QUALITY CONFORMANCE
The M or /883 hybrid circuits furnished under this specifcation are products which have been produced and
tested in conformance with all the provisions of this specifcation.
2.3 MARKING
2.3.1 MARKING EACH DEVICE
The following marking is placed on each product:
a) Index point (see 2.3.4)
b) Part number (see 2.3.5)
c) CAGE code number (see 2.3.6)
d) Lot identifcation code (see 2.3.7)
e) Manufacturers identifcation (see 2.3.8)
f) Country of origin (see 2.3.9)
g) BeO warning (if applicable, see 2.3.10)
h) ESD identifer
These units are Class 1 as defned in MIL-PRF-38534; therefore, the ESD identifer is incorporated in the mark.
2.3.2 MARKING ON INITIAL CONTAINER
Marking on initial anti-static packaging for delivery includes:
a) Manufacturers identifcation
b) Customer name
c) Customers P.O. number
d) Quantity packaged
e) Lot code
f) Date packaged
g) Packaging operators initials
2.3.3 MARKING PERMANENCE
Marking is permanent in nature to MIL-STD-883, Method 2015.
2.3.4 INDEX POINT
The index point, denoting location of Pin 1, is indicated as shown on the appropriate Package Outline.
M/883
19
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2.3.5 PART NUMBER
The part number is the APEX generic part number and DSCC SMD part number, when applicable.
2.3.6 CAGE CODE NUMBER
The CAGE code number for APEX is 60024 as designated by the Federal government.
2.3.7 LOT IDENTIFICATION CODE
The lot identifcation and date code are shown as one alphanumeric string. The frst 5 characters are the lot number
identifcation. The last 4 digits are the date code as YYWW.
2.3.8 MANUFACTURERS IDENTIFICATION
The manufacturers identifcation is signifed by the name, logo, or trademark of APEX incorporated in the mark.
2.3.9 COUNTRY OF ORIGIN
The country of origin is signifed by USA incorporated in the mark.
2.3.10 BeO WARNING
Since hybrid circuits contain beryllium oxide substrates, the BeO identifer is marked on the package as an alert
to the user, that if the package seal is broken, not to crush, machine, or subject the substrate to temperatures in
excess of 850C to avoid generating toxic fumes or inhalable particles.
3.0 CONDITIONS AND METHODS OF TEST
Conditions and methods of test are to MIL-PRF-38534 and as specifed herein. This section establishes the stress
screening tests and quality conformance inspection tests for this program. The purpose of these tests is to assure
the quality and reliability of the product to a particular process level commensurate with the products intended ap-
plication. All tests are performed on a 100% basis except where indicated.
3.1 HIGH POWER DIE INSPECTION
High power die inspection is performed to MIL-STD-750 Method 2072 and 2073, and MIL-STD-883 Method 2010.
3.2 INTERNAL VISUAL INSPECTION (PRECAP)
Internal visual inspection is performed to MIL-STD-883, Method 2017 and 2032.
3.3 TEMPERATURE CYCLING
Temperature cycling is performed to MIL-STD-883, Method 1010, Condition C, using 10 cycles from 65C to
+150C.
3.4 BURN-IN
Burn-in is performed to MIL-STD-883, Method 1015, Condition D for 160 hours at a case temperature of 125C.
3.5 CONSTANT ACCELERATION
Constant acceleration is performed to MIL-STD-883, Method 2001, Condition A, at 5,000 Gs, in the Y1 axis only.
3.6 FINAL ELECTRICAL TEST
Final electrical tests are performed to MIL-PRF-38534*. Both static and dynamic parameters from Group A, Sub-
groups 1-6, are 100% tested to the M data sheet limits at 55C, +25C and +125C. The PDA (Percent Defective
Allowable) shall be 10% maximum and shall only apply to static (DC) measurements at +25C.
3.7 HERMITICITY
Hermiticity tests are performed per the following:
3.7.1 FINE LEAK TESTING
Fine leak testing is performed to MIL-STD-883, Method 1014, Condition A2, at 1X10
-7
cc/sec standard leak rate.
M/883
20
3.7.2 GROSS LEAK TESTING
Gross leak testing is performed to MIL-STD-883, Method 1014, Condition C, at 60 PSIG pre-pressurization.
3.8 EXTERNAL VISUAL INSPECTION
All M and /883 circuits receive external visual to MIL-STD-883, Method 2009.
4.0 QUALITY ASSURANCE PROVISION* SEE FIGURE 1.
4.1 QUALITY CONFORMANCE INSPECTION
Quality Conformance Inspection (QCI) is to MIL-PRF-38534, Option 1, in-line qualifcation method. Lots failing to
meet quality conformance inspection for a given product assurance level are rejected.
4.1.1 GROUP A ELECTRICAL TESTING
Group A electrical testing is performed using in-line verifcation in accordance with Option 1 of MIL-PRF-38534.
Electrical parameters and test limits are as shown in the M data sheet.
4.1.2 GROUP B INSPECTION
Group B inspection is satisfed by performing in-line inspection sampling, to MIL-PRF-38534, Option 1.
4.1.3 GROUP C INSPECTION
Group C inspection is performed on the frst lot submitted for inspection and as required to evaluate or qualify
changes in manufacturing processes per MIL-PRF-38534, Option 1.
4.1.4 GROUP D INSPECTION
Group D testing in accordance with MIL-PRF-38534, Option 1, is accomplished during package evaluation at in-
coming inspection and is not repeated.
5.0 DATA AND REPORTS*
5.1 CERTIFICATE of COMPLIANCE
All /883 circuits are accompanied by a Certifcate of Compliance.
5.2 QUALITY CONFORMANCE REPORTS
MIL-PRF-38534, Option 1, Group A lot data is kept on fle with the production records. In-line Groups B, C and D
(reference 4.1.4) generic data is also on fle.
5.3 TRACEABILITY
Traceability is in accordance with MIL-PRF-38534. Each circuit is traceable to the production lot. Re-worked or
repaired circuits maintain traceability.
6.0 PACKAGING
Packing and packaging are to MIL-STD-2073/1D.
7.0 CUSTOM MARKING
Production quantities of M and /883 devices may be dual or solely marked with an applicable SCD number.
* Applies to compliant (/883) product only.
M/883
21
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FIGURE 1: CIRRUS LOGIC MILITARY PROCESS FLOW FOR APEX PRECISION
POWER
TM
PRODUCT
Header and cap: Package evaluation to MIL-PRF-38534
Raw Substrate: Inspected in accordance with APEX specifcation QUAL52
visual criteria based on MIL-STD-883, Method 2032.
Small signal die: Component element evaluation to MIL-PRF-38534
Large signal die: Component element evaluation to MIL-PRF-38534
Chip Components: Component element evaluation to MIL-PRF-38534
(diodes, capacitors, etc.)
Wire: Inspected in accordance with APEX specifcation WIRE01
Epoxy: Inspected to MIL-STD-883, Method 5011
Thick flm paste: Inspected in accordance with APEX specifcation PASTEI
Solder: Inspected in accordance with APEX specifcation PASTEI
High power die
inspection to
MIL-STD-883,
Method 2010,
MIL-STD-750,
Methods 2072
and 2073
100% substrate manufacturing
inspection per APEX specifca-
tion PROC294; based on
MIL-STD-883, Method 2032
Substrate fabrication
Kitting/Kitting Inspection
Small signal die attach,
conductive/nonconductive epoxy
Substrate/power die
attach in refow fur-
nace, as applicable
Ultrasonic Aluminum wire bond
and assembly inspection
Sample non-destruct wire-pull
Sample destruct wire-pull
A
Substrate attach
Non-conductive epoxy
(SWR/VRE)
Optional functional test,
room temp static and
dynamic parameters
tested per data sheet with
widened min/max limits
Pre-seal Burn-in
(SWR/VRE only),
72 hrs @ 150C
Optional Laser Trim and
100% inspection to
MIL-STD-883,
Method 2032
Temperature Test/
Laser Trim
(SWR/VRE only)
PRECAP TEST
25C static and dynamic parameters tested per
Industrial data sheet
PRECAP VISUAL INSPECTION
100% manufacturing inspection to MIL-STD-883,
Method 2017 and 2032
22
No
Yes
A
PACKAGING FOR SHIPMENT
is done per MIL-STD-2073/1D
LOT QUALIFICATION
Quality Conformance Inspection (QCI) is done
to MIL-PRF-38534 Option 1,
in-line inspection and is performed throughout
the lot processing
PDA = 10% For Static DC Parameters
@ +25C Only
QCI?
FIGURE 1: CIRRUS LOGIC MILITARY PROCESS FLOW FOR APEX PRECISION
POWER
TM
PRODUCT
QI sample Precap Inspection
To MIL-STD-883, Method 2017 and 2032,
And APEX specifcation QUAL50
VACUUM BAKEOUT
Preseal @ 150C
PACKAGE SEAL
Resistance Weld,
Moisture = 5000 PPM
SEAM SEAL
(SWR/VRE)
Moisture = 5000 PPM
TEMPERATURE CYCLE
To MIL-STD-883, Method 1010,
Cond. C, -65C to +150 C for 10 Cycles
BURN-IN
MIL-STD-883, Method
1016, Cond. D,
160 hrs @ +125C
BURN-IN
(SWR/VRE)
96 hrs @ +125C
CONSTANT ACCELERATION
To MIL-STD-883, Method 2001, Cond. A
5000 Gs Y1 axis
FINAL ELECTRICAL TEST
APEX M data sheet; Static and dynamic
parameters at T
C
+ -55C, +25C and +125C
MARKING
To MIL-PRF-38534
EXTERNAL VISUAL
100% Manufacturing Inspection To
MIL-STD-883, Method 2009
QI FINAL GATE
Sample Inspection To MIL-STD-883,
Method 2009 And
Apex Specifcation PROC99
GROSS LEAK TEST
To MIL-STD-883, Method 1014
Cond. C, 60 PSIG Pre-Pressurization
FINE LEAK TEST
To MIL-STD-883, Method 1014,
Cond. A2, 1 x 10
-7
Standard Leak Rate
23
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Reactance Chart
Reactance Chart
.01
.1
1
10
100
1K
10K
100K
1M
10~ 100~ 1000~ 10 KC 100 KC 1000 KC
1
0
0
0

H
1
0
0

H
1
0

H
1

H
.
1

H
.
0
1

H
.
0
0
1

H
1
0
0
H
1
0
H
1
H
.
1
H
.
0
1
H
.
0
0
1
H
.
1
F
.
0
0
1
F
.
0
1
F
.
1
F
1
F
1
F
1
0
0
F
1
0
F
1
0
F
24
NOTES:
Volt Ref 25
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Voltage References
SWR200 ................................................................................................26
VRE100, VRE101, VRE102 ..................................................................30
VRE104 .................................................................................................35
VRE107 .................................................................................................39
VRE117, VRE119 ..................................................................................43
VRE202 .................................................................................................47
VRE204 .................................................................................................51
VRE205 .................................................................................................55
VRE210 .................................................................................................59
VRE302 .................................................................................................63
VRE304 .................................................................................................67
VRE305 .................................................................................................71
VRE306 .................................................................................................75
VRE310 .................................................................................................79
VRE405 .................................................................................................83
VRE410 .................................................................................................87
VRE505 .................................................................................................91
VRE3025 ...............................................................................................95
VRE3050 .............................................................................................101
VRE4112, VRE4125, VRE4141 ...........................................................107
Voltage References Voltage References
SWR200
26 SWR200DS
P r o d u c t I n n o v a t i o n F r o m
SWR200
DESCRIPTION
SWR200 is a Precision Sine Wave Reference provid-
ing an ultra stable sine wave output of +7.071 V at
0.05% initial accuracy and temperature coeffcient
as low as 30 ppm/C over the full military temperature
range. The extreme accuracy is made possible by a
chopper-based AGC circuit. The temperature charac-
teristic of the chopper circuit compensates the typical
nonlinearity of the internal DC zener reference, result-
ing in a nearly linear amplitude-temperature character-
istic. Frequency of the SWR200 is programmable with
two external capacitors.
The SWR200 is available in a 14-pin bottom braze
package. They are hermetically sealed and M ver-
sions are screened for high reliability and quality.
SWR200 is well suited for any application requiring a
stable sine wave source. The SWR200 can be used as
a reference source in precision sensing systems based
on L
VDT
or R
VDT
position sensors. A programmable AC
reference can be constructed using the SWR200 as
a reference for a high accuracy multiplying Digital to
Analog Converter.
FEATURES
Very High Accuracy: +7.071 Vrms 0.05%
Extremely Low Drift: 30 ppm/C
(-55C to +125C)
Excellent Stability: 10 ppm/1000 Hrs. Typical
Low Distortion: 0.1% Thd @ f = 3300 Hz
Hermetic 14-pin Ceramic DIP
Military Processing Option
APPLICATIONS
Transducer Excitation
High Resolution Servo Systems
High Precision Test and Measurement Instru-
ments
AC Voltage Standard
L
VDT
Or R
VDT
Reference
Multiplying D/A Reference
+15V
-15V
+15V
-15V
+15V
-15V
3
+15V
12
Figure 1. BLOCK DIAGRAM
Precision Sine Wave Reference
SWR200 P r o d u c t I n n o v a t i o n F r o m
Copyright Cirrus Logic, Inc. 2009
(All Rights Reserved)
http://www.cirrus.com
AUG 2009
APEX SWR200DSREVG
SWR200
SWR200DS 27
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1. CHARACTERISTICS AND SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
V
PS
=15V, T = +25C, R
L
= 10K UNLESS OTHERWISE NOTED.
Model SWR200C SWR200M
Parameter Min Typ Max Min Typ Max Units
ABSOLUTE MAXIMUM RATINGS
Power Supply 13.5 15 22 * * * V
Operating Temperature -25 +85 -55 +125 C
Storage Temperature -65 +85 * * C
Short Circuit Protection Continuous * Vrms
OUTPUT VOLTAGE 7.071 * V
OUTPUT VOLTAGE ERRORS
Initial Error 0.05 * %
Warmup Drift 100 * V
DC Offset 3 * mV
DC Offset Over Temp. 3 18 * * V/ C
T
MIN
- T
MAX
1 20.0 1 30.0 ppm/ C
Long-Term Stability 10 * ppm/ C
OUTPUT CURRENT
Range 10 * mA
REGULATION
Line 10 * ppm/V
Load 3 * ppm/mA
POWER SUPPLY CURRENTS
+PS 10.5 13 * * mA
-PS 9.5 13 * * mA
DISTORTION 0.5 * %
FREQUENCY
Range (f)
f =
10
-5
C
1
C
2
f
f
vs. temperature
.98 1 1.02 * * * Hz
400 10K * * Hz
15 * ppm/C
Type Output (Typ.)
Temperature
Operating Range Package
SWR200C +7.071V -25C to +85C DIP
SWR200M +7.071V -55C to +125C DIP
SELECTION GUIDE
Package Style HC
SWR200
28 SWR200DS
NOTES:
* Same as C Models.
1. Using the box method, the specifed value is the maximum deviation from the output voltage at
+25C over the specifed operating temperature range.
2. The specifed values are unloaded.
3. Pin 8 is internally connected to Pin 7 and can be used as Ref. GND.
4. The frequency range can be extended to any desired lower value by using 2 external AGC capacitors
(see AN-3).
5. The increase in distrotion at lower frequencies can be eliminated by using external AGC capacitors
(see AN-3).
2. TYPICAL PERFORMANCE GRAPHS
Temperature
o
C
SWR200C
V
OUT
vs. TEMPERATURE V
OUT
vs. TEMPERATURE % FREQ. vs. TEMP.
Temperature
o
C
SWR200M
Temperature
o
C
SWR200C
Temperature
o
C
SWR200M
DISTORTION VS. TEMP
Temperature
o
C
DISTORTION vs. FREQUENCY
Frequency (Hz)
NORMALIZED DISTORTION vs. C2/C1
C2/C1
POWER SUPPLY CURRENT vs. TEMP.
Temperature
o
C
CASE TEMP. RISE ABOVE AMBIENT
vs. OUTPUT CURRENT
Output Current (mA)
JUNCTION TEMP. RISE
ABOVE CASE TEMP. vs
OUTPUT CURRENT
Output Current (mA)
% FREQ. vs. TEMP.
0
-20
15.6
20
-15.6
-50
50
35
0
-35
SWR200
SWR200DS 29
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3. THEORY OF OPERATION
The following refers to the schematic in Figure 1. A1 and A2 are connected as a phase-shift oscillator circuit with
the frequency set by the external capacitors C1 and C2. Q4 is included in the feedback loop of A1 as a gain control
element.
The oscillator output is fed to the chopper amplifer which develops an absolute value representation of the oscillator
output. The chopper output is compared to a precision DC reference in integrator amplifer A3. This DC error signal
is used ot control the gain setting FET Q4.
As in all precision zener based DC references, the drift of the zener becomes nonlinear at temperature extremes.
The chopper amplifer drift characteristic is complementary to this nonlinearity and compensates for the reference
drift.
4. APPLICATION INFORMATION
Figure 1 shows the connections for the SWR200 including the two frequency setting capacitors. The frequency is:
f =
10
-5
C
1
C
2
The frequency stability is directly related to the stability of the capacitors, therefore stable capacitors like NPO ce-
ramic, or polycarbonate or polystyrene flm should be used.
Two separate ground pins are provided for accurate ground sensing. This minimizes errors due to drops in the
ground pin which can become a signifcant source of error in sockets.
The offset of the SWR200 is fully specifed for initial offset and drift and is low enough that it can normally be ne-
glected. In applications which are especially sensitive to offset the output can be AC coupled. Proper capacitor siz-
ing and high impedance sensing will minimize errors due to capacitive coupling.
EXTERNAL CONNECTIONS
PIN CONFIGURATION
TOP VIEW
SWR200
NC
NC
OUTPUT
GND SENSE GND
NC
NC
NC
C1
C1
-PS
C2
+PS
C2
VRE100
30 VRE100DS
VRE100, VRE101, VRE102
DESCRIPTION
VRE100 Series Precision Voltage References provide
ultrastable +10 V (VRE100), -10 V (VRE101) and 10
V (VRE102) outputs with 0.5 mV initial accuracy and
temperature coeffcient as low as 0.5 ppm/C over the
full military temperature range. This improvement in
accuracy is made possible by a unique, proprietary
multipoint laser compensation technique.
Signifcant improvements have been made in other
performance parameters as well, including initial ac-
curacy, warm-up drift, line regulation, and long-term
stability, making the VRE100 series the most accurate
and stable 10 V reference available.
VRE100/101/102 devices are available in two oper-
ating temperature ranges, -25C to +85C and -55C
to +125C, and two performance grades. All devices
are packaged in 14-pin hermetic ceramic packages
for maximum long-term stability. M versions are
screened for high reliability and quality.
Superior stability, accuracy, and quality make these
references ideal for precision applications such as A/D
and D/A converters, high-accuracy test and measure-
ment instrumentation, and transducer excitation.
FEATURES
Very High Accuracy: 10 V Output, 0.5 mV
Extremely Low Drift: 0.5 ppm/C (-55C to
+125C)
Low Warm-up Drift: 1.0 ppm Typical
Excellent Line Regulation: 3 ppm/V Typical
APPLICATIONS
Precision A/D and D/A Converters
Accurate Comparator Threshold Reference
Digital Voltmeters
ments
Precision Voltage Reference
VRE100/101/102 P r o d u c t I n n o v a t i o n F r o m
VRE100
VRE102
Figure 1. BLOCK DIAGRAMS
JUN 2009
APEX VRE100DSREVF
VRE100
VRE100DS 31
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B
A
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B
A
V
PS
=15V, T = +25C, R
L
Grade C CA M MA
Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units
Power Supply 13.5 22 * * * * * * V
Operating Temperature -25 +85 * * -55 +125 -55 +125 C
Storage Temperature -65 +150 * * * * * * C
Short Circuit Protection Continuous * * *
OUTPUT VOLTAGE
VRE100 +10 * * * V
VRE101 -10 * * * V
VRE102 10 * * * V
Initial Error 1.0 0.5 1.5 0.8 mV
Warmup Drift 2 1 2 1 ppm
T
MIN
- T
MAX
(Note1) 0.6 0.3 1.0 0.5 mVz
Long-Term Stability 6 * * * ppm/1000hrs
Noise (0.1 - 10Hz) 6 * * * Vpp
OUTPUT CURRENT
Range 10 * * * mA
REGULATION
Line 3 10 * * * * * * ppm/V
Load 3 * * * ppm/mA
OUTPUT ADJUSTMENT
Range 20 * * * mV
Temperature Coeffcient 4 * * * V/C/mV
POWER SUPPLY CURRENT (Note 2)
VRE100 +PS 5 7 * * * * * * mA
VRE101 -PS 5 7 * * * * * * mA
VRE102 +PS 7 9 * * * * * * mA
VRE102 -PS 4 6 * * * * * * mA
NOTES:
* Same as C Models.
1. Using the box method, the specifed value is the maximum deviation from the output voltage at 25C
over the specifed operating temperature range.
VRE100
32 VRE100DS
Model Output (V)
Temperature
Operating Range Volt Deviation (MAX)
VRE100C
VRE100CA
VRE100M
VRE100MA
+10
+10
+10
+10
-25C to +85C
-25C to +85C
-55C to +125C
-55C to +125C
0.6mV
0.3mV
1.0mV
0.5mV
VRE101C
VRE101CA
VRE101M
VRE100MA
-10
-10
-10
-10
-25C to +85C
-25C to +85C
-55C to +125C
-55C to +125C
0.6mV
0.3mV
1.0mV
0.5mV
VRE102C
VRE102CA
VRE102M
VRE102MA
10
10
10
10
-25C to +85C
-25C to +85C
-55C to +125C
-55C to +125C
0.6mV
0.3mV
1.0mV
0.5mV
SELECTION GUIDE
The following discussion refers to the block diagrams in Figure 1. In operation, approximately 6.3 volts is applied
to the noninverting input of the op amp. The voltage is amplifed by the op amp to produce a 10.000 V output. The
gain is determined by the networks R1 and R2: G=1 + R2/R1. The 6.3 V zener diode is used because it is the most
stable diode over time and temperature.
The zener operating current is derived from the regulated output voltage through R3. This feedback arrangement
provides a closely regulated zener current. This current determines the slope of the references voltage vs. tempera-
ture function. By trimming the zener current a lower drift over temperature can be achieved. But since the voltage
vs. temperature function is nonlinear this compensation technique is not well suited for wide temperature ranges.
A nonlinear compensation network of thermistors and resistors is used in the VRE series voltage references. This
proprietary network eliminates most of the nonlinearity in the voltage vs. temperature function. By then adjusting the
slope, this series produces a very stable voltage over wide temperature ranges. This network is less than 2% of the
overall network resistance so it has a negligible effect on long term stability. By using highly stable resistors in our
network, we produce a voltage reference that also has very good long term stability.
Page 5 shows the proper connection of the VRE100 series voltage reference with the optional trim resistors. When
trimming the VRE102, the positive voltage should be trimmed frst since the negative voltage tracks the positive
side. Pay careful attention to the circuit layout to avoid noise pickup and voltage drops in the lines.
The VRE100 series voltage references have the ground terminal brought out on two pins (pin 6 and pin 7) which
are connected together internally. This allows the user to achieve greater accuracy when using a socket. Voltage
references have a voltage drop across their power supply ground pin due to quiescent current fowing through the
contact resistance. If the contact resistance was constant with time and temperature, this voltage drop could be
trimmed out. When the reference is plugged into a socket, this source of error can be as high as 20 ppm. By con-
necting pin 7 to the power supply ground and pin 6 to a high impedance ground point in the measurement circuit,
the error due to the contact resistance can be eliminated. If the unit is soldered into place the contact resistance is
suffciently small that it doesnt effect performance. The VRE series voltage references can be connected with or
without the use of pin 6 and still provide superior performance.
Package Style HC
VRE100
VRE100DS 33
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A
Temperature
o
C
VRE100/101/102C
V
OUT
vs. TEMPERATURE V
OUT
vs. TEMPERATURE V
OUT
vs. TEMPERATURE V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE100/101/102CA
Temperature
o
C
VRE100/101/102M
Temperature
o
C
VRE100/101/102MA
QUIESCENT CURRENT VS. TEMP
Temperature
o
C
JUNCTION TEMP. RISE VS. OUTPUT CURRENT
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
VRE100/101
VRE102
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
POSITIVE OUTPUT
NEGATIVE OUTPUT
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
4. TYPICAL PERFORMANCE CURVES
VRE100
34 VRE100DS
PIN CONFIGURATION
1. Optional Fine Adjust for approximately 20mV. VRE101 center tap connects to -PS.
TOP VIEW TOP VIEW TOP VIEW
VRE102 VRE100 VRE101
GND
REF.
GND
NC
NC
NC
NC
NC
FINE
ADJ .
+10V
FINE
ADJ .
+PS
NC
NC
NC
-PS
NC
NC
NC
+ADJ .
+10V
+ADJ .
+PS
NC
NC
NC
GND
REF.
GND
NC
NC
NC
NC
NC
GND
REF.
GND
NC
FINE
ADJ .
FINE
ADJ .
-10V
-10V
-ADJ .
-ADJ .
-PS
CONTACTING CIRRUS LOGIC SUPPORT
For all Apex Precision Power product questions and inquiries, call toll free 800-546-2739 in North America.
For inquiries via email, please contact apex.support@cirrus.com.
International customers can also request support by contacting their local Cirrus Logic Sales Representative.
To fnd the one nearest to you, go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnifcation, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-
sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE (CRITICAL APPLICATIONS). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED TO BE
SUITABLE FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PROD-
UCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUS-
TOMERS RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE
CUSTOMER OR CUSTOMERS CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES,
BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL
LIABILITY, INCLUDING ATTORNEYS FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, Apex Precision Power, Apex and the Apex Precision Power logo designs are trademarks of Cirrus Logic, Inc.
All other brand and product names in this document may be trademarks or service marks of their respective owners.
VRE104
VRE104DS 35
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B
A
VRE104
DESCRIPTION
ultrastable +4.5 V outputs with up to 0.4 mV initial
accuracy and temperature coeffcient as low as 0.6
ppm/C over the full military temperature range.
These references are specifcally designed to be used
with the Crystal Semiconductor line of successive-ap-
proximation type Analog to Digital Converters (ADCs).
This line of ADCs sets new standards for temperature
drift, which can only be as good as the external refer-
ence used. The VRE104 combined with an ADC will
provide the lowest drift data conversion obtainable.
VRE104 series devices are available in two operat-
ing temperature ranges, -25C to +85C and -55C
Superior stability, accuracy, and quality make the
VRE104 ideal for all precision applications which may
require a 4.5 V reference. High-accuracy test and
measurement instrumentation, and transducer exci-
tation are some other applications which can beneft
from the high accuracy of the VRE104.
FEATURES
Very High Accuracy: +4.5 V Output, 0.4 mV
+125C)
Wide Supply Range: 13.5 to 22.0 V
Military Processing Options
APPLICATIONS
Precision A/D And D/A Converters
Digital Voltmeters
ments
VRE104 P r o d u c t I n n o v a t i o n F r o m
APR 2009
APEX VRE104DSREVD
VRE104
36 VRE104DS
V
PS
=+15V, T = 25C, R
L
Grade VRE104C VRE104CA VRE104M VRE104MA
Power Supply 13.5 22 * * * * * * V
OUTPUT VOLTAGE
VRE104 +4.5 * * * V
Initial Error 800 400 800 400 V
T
MIN
- T
MAX
(Note1) 400 200 600 300 V
Noise (0.1 - 10Hz) 3 * * * Vpp
OUTPUT CURRENT
Range 10 * * * mA
REGULATION
Line 6 10 * * * * * * ppm/V
Load 3 * * * ppm/mA
OUTPUT ADJUSTMENT
Range 10 * * * mV
VRE104 +PS 5 7 * * * * * * mA
Model Output (V)
Temperature
VRE104C
VRE104CA
+4.5
+4.5
-25C to +85C
-25C to +85C
0.4mV
0.2mV
VRE101M
VRE100MA
+4.5
+4.5
-55C to +125C
-55C to +125C
0.6mV
0.3mV
SELECTION GUIDE
NOTES:
* Same as C Models.
Package Style HC
VRE104
VRE104DS 37
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H
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D
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B
A
G
H
I
F
E
D
C
B
A
Temperature
o
C
VRE104C
V
OUT
vs. TEMPERATURE V
OUT
vs. TEMPERATURE V
OUT
vs. TEMPERATURE V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE104CA
Temperature
o
C
VRE104M
Temperature
o
C
VRE104MA
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
The following discussion refers to the block diagram in Figure 1. A FET current source is used to bias a 6.3 V zener
diode. The zener voltage is divided by the resistor network R1 and R2. This voltage is then applied to the noninvert-
ing input of the operational amplifer which amplifes the voltage to produce a 4.5 V output. The gain is determined
by the resistor networks R3 and R4: G=1 + R4/R3. The 6.3 V zener diode is used because it is the most stable
diode over time and temperature.
The current source provides a closely regulated zener current, which determines the slope of the references volt-
age vs. temperature function. By trimming the zener current a lower drift over temperature can be achieved. But
since the voltage vs. temperature function is nonlinear, this method leaves a residual error over wide temperature
ranges.
To remove this residual error, a nonlinear compensation network of thermistors and resistors has been developed
that is used in the VRE104 series references. This proprietary network eliminates most of the nonlinearity in the
voltage vs. temperature function. By then adjusting the slope, the VRE104 series produces a very stable voltage
over wide temperature ranges. This network is less than 2% of the overall network resistance so it has a negligible
effect on long term stability.
VRE104
38 VRE104DS
The proper connection of the VRE104 series voltage references is shown below with the optional trim resistors. Pay
careful attention to the circuit layout to avoid noise pickup and voltage drops in the lines.
the error due to the contact resistance can be eliminated. If the unit is soldered into place, the contact resistance is
suffciently small that it does not effect performance.
VRE104 Used With Crystal Semiconductor ADC
Suggested Reading: Crystal Semiconductor Application Note -
Voltage References for the CS501X/CS25IIX Series of A/D Converters"
PIN CONFIGURATION
1. Optional Fine Adjust for approximately 10mV.
TOP VIEW
VRE104
+PS
NC
NC
NC GND
REF. GND
NC
NC
NC
NC
NC
FINE ADJ.
FINE ADJ.
+4.5V
VRE107
VRE107DS 39
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A
G
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B
A
P r o d u c t I n n o v a t i o n F r o m VRE107
DESCRIPTION
ultrastable 5 V outputs with 0.4 mV initial accuracy
and temperature coeffcient as low as 0.6 ppm/C over
the full military temperature range. This impovement
in accuracy is made possible by a unique, proprietary
multipoint laser compensation technique.
Signifcant improvements have been made in other
performance parameters as well, including initial ac-
curacy, warm-up drift, line regulation, and long-term
stability, making the VRE107 series the most accurate
and stable 5 V references available.
are packaged in 14-pin hermetic ceramic packages for
maximum long-term stablity. M versions are screened
for high reliability and quality.
and D/A converters, high accuracy test and measure-
ment instrumentation, and tranducer excitation.
FEATURES
Very High Accuracy: 5 V, 0.4 mV
+125C)
Wide Supply Range: 13.5 V to 22 V
APPLICATIONS
Digital Voltmeters
ments
MAR 2009
APEX VRE107DSREVD
VRE107
40 VRE107DS
V
PS
=15V, T = +25C, R
L
Model VRE107M VRE107MA
Power Supply 13.5 22 * * V
Operating Temperature -55 +125 * * C
Short Circuit Protection Continuous *
OUTPUT VOLTAGE
VRE107 5 * V
Initial Error 800 400 V
Warmup Drift 2 1 ppm
T
MIN
- T
MAX
(Note1) 600 300 V
Long-Term Stability 6 * ppm/1000hrs.
Noise (0.1 - 10Hz) 3 * Vpp
OUTPUT CURRENT
Range 10 * mA
REGULATION
Line 6 10 * * ppm/V
Load 3 * ppm/mA
OUTPUT ADJUSTMENT
Range 10 * mV
Temperature Coeffcient 4 * V/C/mV
VRE107 +PS 7 9 * * mA
VRE107 -PS 4 6 * * mA
NOTES:
* Same as M Models.
Model Output (V)
Temperature
VRE107M
VRE107MA
5
5
-55C to +125C
-55C to +125C
0.6mV
0.3mV
SELECTION GUIDE
Package Style HC
VRE107
VRE107DS 41
G
H
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E
D
C
B
A
G
H
I
F
E
D
C
B
A
V
OUT
vs. TEMPERATURE V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE107M
Temperature
o
C
VRE107MA
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
POSITIVE OUTPUT
NEGATIVE OUTPUT
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
TYPICAL PERFORMANCE GRAPHS
ing input of the operational amplifer which amplifes the voltage to produce a 5 V output. The gain is determined by
the resistor networks R3 and R4: G=1 + R4/R3. The 6.3 V zener diode is used because it is the most stable diode
over time and temperature.
age vs. temperature function. By trimming the zener current, a lower drift over temperature can be achieved. But
ranges.
To remove this residual error, a nonlinear compensation network of thermistors and resistors is used in the VRE107
VRE107
42 VRE107DS
series references. This proprietary network eliminates most of the nonlinearity in the voltage vs. temperature func-
tion. By then adjusting the slope, The VRE107 series produces a very stable voltage over wide temperature ranges.
This network is less than 2% of the overall network resistance so it has a negligible effect on long term stability.
The proper connection of the VRE107 series voltage reference is shown below with the optional trim resistors.
When trimming the VRE107, the positive voltage should be trimmed frst since the negative voltage tracks the posi-
tive side. Pay careful attention to the circuit layout to avoid noise pickup and voltage drops in the lines.
suffciently small that it doesnt effect performance.
TOP VIEW
VRE107
FINE+ADJ.
+5V
FINE+ADJ.
+PS
NC
NC
NC GND
REF. GND
NC
-5V
FINE-ADJ.
FINE-ADJ.
-PS
PIN CONFIGURATION
IMPORTANT NOTICE
VRE117/119
VRE117DS 43
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A
VRE117, VRE119
DESCRIPTION
VRE117/119 Series Precision Voltage References pro-
vide ultrastable +3 V (VRE117), and 3 V (VRE119)
output with 0.2 mV initial accuracy and temperature
coeffcient as low as 0.6 ppm/C over the full military
temperature range. This improvement in accuracy is
made possible by a unique, proprietary multipoint laser
compensation technique. Signifcant improvements
have been made in other performance parameters as
well, including initial accuracy, warm-up drift, line regu-
lation, and long-term stability, making the VRE117/119
series the most accurate and stable 3 V reference
available.
VRE117/119 devices are available in two operat-
and D/A converters, high-accuracy test and measure-
ment instrumentation, and transducer excitation.
FEATURES
+125C)
Low Warm-up Drift: 1 ppm Typical
APPLICATIONS
Digital Voltmeters
ments
VRE117/119 P r o d u c t I n n o v a t i o n F r o m
VRE117
VRE119
Figure 1. BLOCK DIAGRAMS
MAR 2009
APEX VRE117DSREVD
VRE117/119
44 VRE117DS
V
PS
=15V, T = +25C, R
L
Model VRE119C VRE117M VRE117MA
Units Parameter Min Typ Max Min Typ Max Min Typ Max
Power Supply 13.5 22 * * * * V
Operating Temperature -25 +85 -55 +125 -55 +125 C
Storage Temperature -65 +150 * * * * C
Short Circuit Protection Continuous * *
OUTPUT VOLTAGE
VRE117 +3.0 * * V
VRE119 3.0 * * V
Initial Error 300 300 200 V
Warmup Drift 2 2 1 ppm
T
MIN
- T
MAX
(Note1) 200 400 200 V
Long-Term Stability 6 * * ppm/1000hrs.
Noise (0.1 - 10Hz) 1.5 * * Vpp
OUTPUT CURRENT
Range 10 * * mA
REGULATION
Line 3 10 * * * * ppm/V
Load 3 * * ppm/mA
OUTPUT ADJUSTMENT
Range 5 * * mV
Temperature Coeffcient 1 * * V/C/mV
VRE117 PS 5 7 * * * * mA
VRE119 +PS 7 9 * * * * mA
VRE119 -PS 4 6 * * * * mA
NOTES:
* Same as C Models.
Model Output (V)
Temperature
VRE117M
VRE117MA
+3
+3
-55C to +125C
-55C to +125C
400V
200V
VRE119C 3 -25C to +85C 200V
SELECTION GUIDE
Package Style HC
VRE117/119
VRE117DS 45
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Temperature
o
C
VRE119C
V
OUT
vs. TEMPERATURE V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE117M
Temperature
o
C
VRE117MA
V
OUT
vs. TEMPERATURE
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
VRE117
VRE119
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
POSITIVE OUTPUT
NEGATIVE OUTPUT
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
VRE117/119
46 VRE117DS
age vs. temperature function. By trimming the zener current, a lower drift over temperature can be achieved. But
ranges.
To remove this residual error, a nonlinear compensation network of thermistors and resistors is used in the
VRE117/119 series references. This proprietary network eliminates most of the nonlinearity in the voltage vs. tem-
perature function. By then adjusting the slope, The VRE117/119 series produces a very stable voltage over wide
temperature ranges. This network is less than 2% of the overall network resistance so it has a negligible effect on
long term stability.
The proper connection of the VRE117 series voltage reference with the optional trim resistors is shown below. When
trimming the VRE119, the positive voltage should be trimmed frst since the negative voltage tracks the positive
side. Pay careful attention to the circuit layout to avoid noise pickup and voltage drops in the lines.
The VRE117/119 series voltage references have the ground terminal brought out on two pins (pin 6 and pin 7) which
PIN CONFIGURATION
TOP VIEW TOP VIEW
VRE119
VRE117
GND
REF. GND
NC
-PS
NC
NC
NC
FINE ADJ .
+3.0V (-3.0V)
FINE ADJ .
+PS (-PS)
NC
NC
NC
FINE +ADJ .
+3.0V
FINE +ADJ .
+PS
NC
NC
NC GND
REF. GND
NC
-3.0V
FINE -ADJ .
FINE -ADJ .
-PS
VRE202
VRE202DS 47
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B
A
G
H
I
F
E
D
C
B
A
DESCRIPTION
ultrastable +2.5 V outputs with 200 V initial accuracy
the full military temperature range. This improvement
multipoint laser compensation technique. Signifcant
improvements have been made in other performance
parameters as well, including initial accuracy, warm-
up drift, line regulation, and longterm stability, making
the VRE202 series the most accurate and stable 2.5 V
surface mount references available.
VRE202 devices are available in two operating tem-
perature ranges, -25C to +85C and -55C to +125C,
and two electrical performance grades. All devices
are packaged in 20-terminal ceramic LCC packages
FEATURES
Very High Accuracy: +2.5 V Output, 200 V
Extremely Low Drift: 0.6 ppm/C (25C to
+85C)
Hermetic 20-Terminal Ceramic LCC
APPLICATIONS
Digital Voltmeters
ments
11
JUL 2009
APEX VRE202DSREVH
Model Output (V)
Temperature
Operating Range
Volt Deviation
(MAX)
VRE202C
VRE202CA
+2.5V
+2.5V
-25C to +85C
-25C to +85C
200V
100V
VRE202M
VRE202MA
+2.5V
+2.5V
-55C to +125C
-55C to +125C
400V
200V
SELECTION GUIDE
20-terminal Ceramic LCC
Package Style HD
VRE202
48 VRE202DS
V
PS
=+15V, T = +25C, R
L
Grade C CA
Power Supply +13.5 +22 * * V
OUTPUT VOLTAGE
VRE202 +2.5 * V
T
MIN
- T
MAX
(Note1) 200 100 V
Noise (0.1 - 10Hz) 1.5 * Vpp
OUTPUT CURRENT
Range 10 * mA
REGULATION
Line 6 10 * * ppm/V
Load 3 * ppm/mA
OUTPUT ADJUSTMENT
Range 10 * mV
VRE202 +PS 5 7 * * mA
VRE202 -PS 5 7 * * mA
NOTES:
* Same as C Models.
VRE202
VRE202DS 49
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F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Temperature
o
C
VRE202C
V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE202CA
V
OUT
vs. TEMPERATURE
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
Temperature
o
C
VRE202M
V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE202MA
V
OUT
vs. TEMPERATURE
VRE202
50 VRE202DS
since the voltage vs. temperature function is nonlinear this compensation technique is not well suited for wide tem-
perature ranges.
A nonlinear compensation network of thermistors and resistors is used in the VRE series voltage references. this
proprietary network eliminates most of the nonlinearity in the voltage vs. temperature function. Then by adjusting
the slope, a very stable voltage over wide temperature ranges is produced. This network is less than 2% of the
overall network resistance so it has a negligible effect on long term stability. By using highly stable resistors in our
network, a voltage reference is produced that also has very good long term stability.
The proper connection of the VRE202 series voltage references with the optional trim resistors is shown below. Pay
EXTERNAL CONNECTIONS PIN CONFIGURATION
11 12 13 9 10
18
17
16
15
14
4
5
6
7
8
1 20 19 3 2
+15V
V
OUT
=+2.5V
10K
Ref. Gnd.
-15V
TOP VIEW
VRE202
4 5 6 7 8
19
20
1
2
3
NC
NC
TRIM
GND
REF GND
NC V
IN
NC NC NC
NC
NC
NC
NC
NC
13
12
11
10
9
NC NC NC V
OUT
NC
18 17 16 15 14
VRE204
VRE204DS 51
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F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
VRE204
DESCRIPTION
ultrastable +4.5 V outputs with up to 0.4 mV initial
accuracy and temperature coeffcient as low as 0.6
ppm/C over the full military temperature range.
These references are specifcally designed to be used
with successive-approximation type Analog-to-Digital
Converters (ADCs). Specify an ADC with exceptional
temperature drift, which can only be as good as the
external reference used. The VRE204 combined with
the right ADC will provide the lowest drift data conver-
sion obtainable.
The VRE204 series is available in the military operat-
ing temperature range -55C to +125C, and two per-
formance grades. All devices are packaged in 20-ter-
minal LCC ceramic packages for maximum long-term
stability. These M versions are screened for high reli-
ability and quality.
Superior stability, accuracy, and quality make the
VRE204 ideal for all precision applications which may
require a 4.5 V reference. High-accuracy test and
measurement instrumentation, and transducer exci-
tation are some other applications which can beneft
from the high accuracy of the VRE204.
FEATURES
Very High Accuracy: +4.5 V Output, 0.4 mV
+125C)
Wide Supply Range: 13.5 V to 22.0 V
Hermetic 20-terminal Ceramic LCC
Military Processing Available
APPLICATIONS
Digital Voltmeters
ments
11
Model Output (V)
Temperature
VRE204M
VRE204MA
+4.5V
+4.5V
-55C to +125C
-55C to +125C
0.6mV
0.3mV
SELECTION GUIDE
Package Style HD
JUL 2009
APEX VRE204DSREVG
VRE204
52 VRE204DS
V
PS
=+15V, T = +25C, R
L
Model M MA
Power Supply +13.5 +22 * * V
OUTPUT VOLTAGE
VRE204 +4.5 * V
T
MIN
- T
MAX
(Note1) 600 300 V
Noise (0.1 - 10Hz) 3 * Vpp
OUTPUT CURRENT
Range 10 * mA
REGULATION
Line 6 10 * * ppm/V
Load 3 * ppm/mA
OUTPUT ADJUSTMENT
Range 10 * mV
VRE204 +PS 5 7 * * mA
NOTES:
* Same as M Models.
VRE204
VRE204DS 53
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H
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F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
Temperature
o
C
VRE204M
V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE204MA
V
OUT
vs. TEMPERATURE
The following discussion refers to the block diagram in Figure 1. A FET current source is used to bias a 6.3 zener
by the resistor networks R3 and R4: G=1 + R4/R3. The 6.3 zener diode is used because it is the most stable diode
perature ranges.
proprietary network eliminates most of the nonlinearity in the voltage vs. temperature function. By then adjusting
the slope, the VRE204 series produces a very stable voltage over wide temperature ranges. This network is less
than 2% of the overall network resistance so it has a negligible effect on long term stability. By using highly stable
resistors in our network, we produce a voltage reference that also has very good long term stability.
VRE204
54 VRE204DS
The proper connection of the VRE204 series voltage references with the optional trim resistors is shown below. Pay
11 12 13 9 10
18
17
16
15
14
4
5
6
7
8
1 20 19 3 2
+15V
V
OUT
=+4.5V
10K
Ref. Gnd.
TOP VIEW
VRE204
4 5 6 7 8
19
20
1
2
3
NC
NC
TRIM
GND
REF GND
NC V
IN
NC NC NC
NC
NC
NC
NC
NC
13
12
11
10
9
NC NC NC V
OUT
NC
18 17 16 15 14

IMPORTANT NOTICE
PIN CONFIGURATION
VRE205
VRE205DS 55
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E
D
C
B
A
G
H
I
F
E
D
C
B
A
VRE205
DESCRIPTION
VRE205 Series Precision Voltage References provides
ultrastable 5 V outputs with 0.4 mV initial accuracy
parameters as well, including initial accuracy, warm-up
drift, line regulation, and longterm stability, making the
VRE205 series the most accurate and stable 5 V refer-
ences available.
FEATURES
+125C)
Wide Supply Range: 13.5 V to 22 V
Hermetic 20-terminal Ceramic LCC
APPLICATIONS
Digital Voltmeters
ments
11
Model Output (V)
Temperature
Operating Range Volt Deviation (Max)
VRE205C
VRE205CA
5V
5V
-25C to +85C
-25C to +85C
0.4mV
0.2mV
VRE205M
VRE205MA
5V
5V
-55C to +125C
-55C to +125C
0.6mV
0.3mV
SELECTION GUIDE
Package Style HD
JUL 2009
APEX VRE205DSREVG
VRE205
56 VRE205DS
V
PS
=+15V, T = +25C, R
L
NOTES:
* Same as C Models.
Model C CA M MA
Power Supply +13.5 +22 * * * * * * V
OUTPUT VOLTAGE
VRE205 5 * * * V
T
MIN
- T
MAX
(Note1) 400 200 600 300 V
Noise (0.1 - 10Hz) 3 * * * Vpp
OUTPUT CURRENT
Range 10 * * * mA
REGULATION
Line 6 10 * * * * * * ppm/V
Load 3 * * * ppm/mA
OUTPUT ADJUSTMENT
Range 10 * * * mV
VRE205 +PS 5 7 * * * * * * mA
VRE205
VRE205DS 57
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Temperature
o
C
VRE205C
V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE205CA
V
OUT
vs. TEMPERATURE
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
Temperature
o
C
VRE205M
V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE205MA
V
OUT
vs. TEMPERATURE
The following discussion refers to the schematic in Figure 1. A FET current source is used to bias a 6.3 V zener
perature ranges.
A nonlinear compensation network of thermistors and resistors is used in the VRE series voltage. This proprietary
network eliminates most of the nonlinearity in the voltage vs. temperature function. By then adjusting the slope, a
very stable voltage over wide temperature ranges is produced. This network is less than 2% of the overall network
resistance so it has a negligible effect on long term stability. By using highly stable resistors in our network, we pro-
duce a voltage reference that also has very good long term stability.
VRE205
58 VRE205DS
The proper connection of the VRE205 series voltage references with the optional trim resistor is shown below. Pay
11 12 13 9 10
18
17
16
15
14
4
5
6
7
8
1 20 19 3 2
+15V
V
OUT
=+5V
10K
Ref. Gnd.
TOP VIEW
VRE205
4 5 6 7 8
19
20
1
2
3
NC
NC
TRIM
GND
REF GND
NC V
IN
NC NC NC
NC
NC
NC
NC
NC
13
12
11
10
9
NC NC NC V
OUT
NC
18 17 16 15 14

IMPORTANT NOTICE
PIN CONFIGURATION
VRE210
VRE210DS 59
G
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F
E
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B
A
G
H
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F
E
D
C
B
A
VRE210
DESCRIPTION
ultrastable +10 V outputs with 0.3 mV initial accuracy
parameters as well, including initial accuracy, warm-
up drift, line regulation, and longterm stability, making
the VRE210 series the most accurate and stable 10 V
surface mount references available.
VRE210 devices are available in two operating tem-
perature ranges, -25C to +85C and -55C to +125C,
and two electrical performance grades. All devices
FEATURES
Very High Accuracy: +10 V Output, 0.3 mV
+125C)
Hermetic 20-terminal Ceramic LCC Package
APPLICATIONS
Digital Voltmeters
ments
11
Model Output (V)
Temperature
Operating Range
Volt Deviation
(Max)
VRE210C
VRE210CA
+10
+10
-25C to +85C
-25C to +85C
0.6mV
0.3mV
VRE210M
VRE210MA
+10
+10
-55C to +125C
-55C to +125C
1.0mV
0.5mV
SELECTION GUIDE
Package Style HD
JUL 2009
APEX VRE210DSREVG
VRE210
60 VRE210DS
V
PS
=+15V, T = +25C, R
L
= 10K Unless Otherwise Noted.
NOTES:
* Same as C Models.
Model VRE210C VRE210CA VRE210M VRE210MA
Power Supply +13.5 +22 * * * * * * V
OUTPUT VOLTAGE
VRE210 +10 * * * V
T
MIN
- T
MAX
(Note1) 600 300 1000 500 V
Noise (0.1 - 10Hz) 6 * * * Vpp
OUTPUT CURRENT
Range 10 * * * mA
REGULATION
Line 3 10 * * * * * * ppm/V
Load 3 * * * ppm/mA
OUTPUT ADJUSTMENT
Range 20 * * * mV
Temperature Coeffcient 4 * * * mV/C/mV
VRE210 +PS 5 7 * * * * * * mA
VRE210
VRE210DS 61
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H
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F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Temperature
o
C
VRE210C
V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE210CA
V
OUT
vs. TEMPERATURE
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
Temperature
o
C
VRE210M
V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE210MA
V
OUT
vs. TEMPERATURE
The following discussion refers to the block diagram in Figure 1. In operation, approximately 6.3 volts is applied to
the noninverting input of the op amp. The voltage is amplifed by the op amp to produce a 10 V output. The gain is
determined by the networks R1 and R2: G=1 + R2/R1. The 6.3V zener diode is used because it is the most stable
A nonlinear compensation network of thermistors and resistors that is used in the VRE series voltage references.
This proprietary network eliminates most of the nonlinearity in the voltage vs. temperature function. By then adjust-
ing the slope, Thaler Corporation produces a very stable voltage over wide temperature ranges. This network is less
than 2% of the overall network resistance so it has a negligible effect on long term stability. By using highly stable
resistors in our network, we produce a voltage reference that also has very good long term stability.
VRE210
62 VRE210DS
The proper connection of the VRE210 series voltage references with the optional trim resistor is shown below. Pay
11 12 13 9 10
18
17
16
15
14
4
5
6
7
8
1 20 19 3 2
+15V
V
OUT
=+10V
Ref. Gnd.
10K
TOP VIEW
VRE210
4 5 6 7 8
19
20
1
2
3
NC
NC
TRIM
GND
REF GND
NC V
IN
NC NC NC
NC
NC
NC
NC
NC
13
12
11
10
9
NC NC NC V
OUT
NC
18 17 16 15 14
PIN CONFIGURATION
IMPORTANT NOTICE
VRE302
VRE302DS 63
G
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F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
DESCRIPTION
The VRE302 is a low cost, high precision +2.5 V refer-
ence. Packaged in the industry standard 8-pin DIP, the
device is ideal for upgrading systems that use lower
performance references.
The device provides ultrastable +2.5 V output with
0.25 mV (.01%) initial accuracy and a temperature
coeffcient of 0.6 ppm/C. This improvement in accu-
racy is made possible by a unique, patented multipoint
laser compensation technique. Signifcant improve-
ments have been made in other performance param-
eters as well, including initial accuracy, warm-up drift,
line regulation, and long-term stability, making the
VRE302 series the most accurate reference available
in the standard 8-pin DIP package.
For enhanced performance, the VRE302 has an ex-
ternal trim option for users who want less than 0.01%
initial error. A reference ground pin is provided to elimi-
nate socket contact resistance errors.
FEATURES
+2.5 V Output, 0.250 mV (.01%)
Temperature Drift: 0.6 ppm/C
Low Noise: 1.5 V
P-P
(0.1-10Hz)
Industry Standard Pinout: 8-pin DIP or Surface
Mount Package
Output Trim Capability
APPLICATIONS
The VRE302 is recommended for use as a refer-
ence for 14, 16, or 18 bit D/A converters which re-
quire an external precision reference. The device
is also ideal for calibrating scale factor on high
resolution A/D converters. The VRE302 offers su-
perior performance over monolithic references.
Model
Initial Error
(mV)
Temp. Coeff.
(ppm/C)
Temp. Range
(C)
Package
Options
VRE302CS
VRE302CD
VRE302JS
VRE302JD
VRE302KS
VRE302LS
VRE302LD
0.50
0.50
0.25
0.25
0.40
0.50
0.50
2.0
2.0
0.6
0.6
1.0
2.0
2.0
0C to +70C
0C to +70C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
SMT8 (GD)
DIP8 (KD)
SMT8 (GD)
DIP8 (KD)
SMT8 (GD)
SMT8 (GD)
DIP8 (KD)
SELECTION GUIDE
8-pin Surface Mount
Package Style GD
8-pin DIP
Package Style KD
JUL 2009
APEX VRE302DSREVH
VRE302
64 VRE302DS
V
PS
=15V, T = +25C, R
L
Model A/J K C/L
Parameter Min Typ Max Min Typ Max Min Typ Max Units
Power Supply 13.5 15 22 * * * * * * V
Operating Temperature (A,B) 0 +70 * * * * C
Operating Temperature (K) -40 +85 * * * * C
OUTPUT VOLTAGE
VRE302 +2.5 * * V
Temp. Sensor Voltage (Note 1) 630 * * mV
Initial Error (Note 2) 0.25 0.40 0.50 mV
T
MIN
- T
MAX
(Note3) 0.6 1.0 2.0 ppm/C
Noise (0.1 - 10Hz) (Note 4) 1.5 * * Vpp
OUTPUT CURRENT
Range 10 * mA
REGULATION
Line 6 10 * * * * ppm/V
Load 3 * * ppm/mA
OUTPUT ADJUSTMENT
Range 10 * * mV
VRE302 +PS 5 7 * * * * mA
NOTES:
* Same as A Models.
1. The temp. reference TC is 2.1mV/ C
2. The specifed values are without external trim.
3. The temperature coeffcient is determined by the box method using the following formula:
4. The specifed values are without the external noise reduction capacitor.
V
NOMINAL
x (T
MAX
T
MIN
)
V
MAX
V
MIN
T.C. = x 10
6
VRE302
VRE302DS 65
G
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E
D
C
B
A
G
H
I
F
E
D
C
B
A
Temperature
o
C
VRE302A
V
OUT
vs. TEMPERATURE V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE302C
Temperature
o
C
VRE302J
V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE302K
V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE302L
V
OUT
vs. TEMPERATURE
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency
(Hz)
POSITIVE OUTPUT (TYP)
VRE302
66 VRE302DS
The following discussion refers to the schematic in Figure 1. A FET current source is used to bias a 6.3 V zener di-
ode. The zener voltage is divided by the resistor network R1 and R2. This voltage is then applied to the noninverting
input of the operational amplifer which amplifes the voltage to produce a 2.5 V output. The gain is determined by
perature ranges.
proprietary network eliminates most of the nonlinearity in the voltage vs. temperature function. By adjusting the
slope, a very stable voltage is produced over wide temperature ranges.
The proper connection of the VRE302 series voltage references with the optional trim resistor for initial error is
shown below. The VRE302 reference has the ground terminal brought out on two pins (pin 4 and pin 7) which
suffciently small that it does not effect performance. Pay careful attention to the circuit layout to avoid noise pickup
and voltage drops in the lines.
PIN CONFIGURATION
8
4
6
5
+ V
OUT
2
+ V
IN
VRE302
10k
C
N
1F
OPTIONAL
NOISE REDUCTION
CAPACITOR
OPTIONAL
FINE TRIM
ADJUSTMENT
3
V TEMP OUT
7
REF. GND
5
6
7
8
VRE302
TOP
VIEW
1
2
3
4
N.C.
+V
IN
TEMP
GND
NOISE
REF. GND
V
OUT
TRIM
VRE304
VRE304DS 67
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
DESCRIPTION
The VRE304 is a low cost, high precision +4.5 V refer-
ence. Available in an industry standard 8-pin surface
mount package, the device is ideal for upgrading sys-
tems that use lower performance references.
line regulation, and long-term stability.
For enhanced performance, the VRE304 has an exter-
nal trim option for users who want less than 0.01% ini-
tial error. For ultra low noise applications, an external
capacitor can be attached between the noise reduc-
tion pin and the ground pin. A reference ground pin is
provided to eliminate socket contact resistance errors.
FEATURES
+4.5 V Output, 0.450 mV (.01%)
Low Noise: 3V
p-p
(0.1-10Hz)
Industry Standard Pinout: 8-Pin Surface Mount
Package
APPLICATIONS
Model
Initial Error
(mV)
Temp. Coeff.
(ppm/C)
Temp. Range
(C)
VRE304A
VRE304C
0.45
0.90
0.6
2.0
0C to +70C
0C to +70C
SELECTION GUIDE
8-pin Surface Mount
Package Style GD
MAR 2009
APEX VRE304DSREVE
VRE304
68 VRE304DS
V
PS
=15V, T = +25C, R
L
Model A C
Power Supply 13.5 15 22 * * * V
Operating Temperature 0 +70 * * C
OUTPUT VOLTAGE
VRE304 (Note 1) +4.5 * V
Temp. Sensor Voltage 630 * mV
Initial Error (Note 2) 0.45 0.90 mV
T
MIN
- T
MAX
(Note3) 0.6 2.0 ppm/C
Noise (0.1 - 10Hz) (Note 4) 3 * Vpp
OUTPUT CURRENT
Range 10 mA
REGULATION
Line 6 10 * * ppm/V
Load 3 * ppm/mA
OUTPUT ADJUSTMENT
Range 10 * mV
VRE304 +PS 5 7 * * mA
NOTES:
* Same as A Model.
1. The temp. reference TC is 2.1 mV/ C
V
NOMINAL
x (T
MAX
T
MIN
)
V
MAX
V
MIN
T.C. = x 10
6
VRE304
VRE304DS 69
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Temperature
o
C
VRE304A
V
OUT
vs. TEMPERATURE V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE304C
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
perature ranges.
VRE304
70 VRE304DS
The proper connection of the VRE304 series voltage references with the optional trim resistor for initial error and
the optional capacitor for noise reduction is shown below. The VRE304 reference has the ground terminal brought
out on two pins (pin 4 and pin 7) which are connected together internally. This allows the user to achieve greater
accuracy when using a socket. Voltage references have a voltage drop across their power supply ground pin due to
quiescent current fowing through the contact resistance. If the contact resistance was constant with time and tem-
perature, this voltage drop could be trimmed out. When the reference is plugged into a socket, this source of error
can be as high as 20ppm. By connecting pin 4 to the power supply ground and pin 7 to a high impedance ground
point in the measurement circuit, the error due to the contact resistance can be eliminated. If the unit is soldered
into place, the contact resistance is suffciently small that it does not effect performance. Pay careful attention to the
circuit layout to avoid noise pickup and voltage drops in the lines.
8
4
6
5
+ V
OUT
2
+ V
IN
VRE304
10k
C
1F
OPTIONAL
NOISE REDUCTION
CAPACITOR
OPTIONAL
FINE TRIM
ADJUSTMENT
3
V TEMP OUT
7
REF. GND
5
6
7
8
VRE304
TOP
VIEW
1
2
3
4
N/C
+V
IN
TEMP
GND
NOISE
REDUCTION
REF. GND
V
OUT
TRIM
IMPORTANT NOTICE
PIN CONFIGURATION
VRE305
VRE305DS 71
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
VRE305
DESCRIPTION
The VRE305 is a low cost, high precision +5 V refer-
ence. Packaged in an industry standard 8-pin DIP or
SMT, the device is ideal for upgrading systems that
use lower performance references.
The device provides ultrastable +5 V output with 0.5
mV (.01%) initial accuracy and a temperature coeff-
cient of 0.6 ppm/C. This improvement in accuracy is
made possible by a unique, patented multipoint laser
have been made in other performance parameters
as well, including initial accuracy, warm-up drift, line
regulation, and long-term stability, making the VRE305
series the most accurate reference available in a stan-
dard 8-pin DIP or SMT.
FEATURES
+5 V Output, 0.5 mV (.01%)
Low Noise: 3 V
P-P
(0.1-10Hz)
Industry Standard Pinout: 8-pin DIP or
Surface Mount Package
APPLICATIONS
Model
Initial Error
(mV)
Temp. Coeff.
(ppm/C)
Temp. Range
(C)
Package
Options
VRE305AS
VRE305AD
VRE305BS
VRE305BD
VRE305CS
VRE305CD
VRE305JS
VRE305JD
VRE305KS
VRE305KD
VRE305LS
VRE305LD
0.5
0.5
0.8
0.8
1.0
1.0
0.5
0.5
0.8
0.8
1.0
1.0
0.6
0.6
1.0
1.0
2.0
2.0
0.6
0.6
1.0
1.0
2.0
2.0
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
SIP8 (GD)
DIP8 (KD)
SIP8 (GD)
DIP8 (KD)
SIP8 (GD)
DIP8 (KD)
SIP8 (GD)
DIP8 (KD)
SIP8 (GD)
DIP8 (KD)
SIP8 (GD)
DIP8 (KD)
SELECTION GUIDE
8-pin Surface Mount
Package Style GD
8-pin DIP
Package Style KD
MAR 2009
APEX VRE305DSREVE
VRE305
72 VRE305DS
V
PS
=15V, T = +25C, R
L
Model A/J B/K C/L
Power Supply 13.5 15 22 * * * * * * V
Operating Temperature (A,B,C) 0 +70 * * * * C
Operating Temperature (J,K,L) -40 +85 * * * * C
OUTPUT VOLTAGE
VRE305 +5.0 * * V
T
MIN
- T
MAX
(Note3) 0.6 1.0 2.0 ppm/C
Noise (0.1 - 10Hz) (Note 4) 3 * * Vpp
OUTPUT CURRENT
Range 10 * mA
REGULATION
Line 6 10 * * * * ppm/V
Load 3 * * ppm/mA
OUTPUT ADJUSTMENT
Range 10 * * mV
VRE305 +PS 5 7 * * * * mA
NOTES:
* Same as A/J Models.
V
NOMINAL
x (T
MAX
T
MIN
)
V
MAX
V
MIN
T.C. = x 10
6
VRE305
VRE305DS 73
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Temperature
o
C
VRE305A
V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE305B
V
OUT
vs. TEMPERATURE
V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE305C
Temperature
o
C
VRE305J
V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE305K
V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE305L
V
OUT
vs. TEMPERATURE
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
VRE305
74 VRE305DS
perature ranges.
can be as high as 20 ppm. By connecting pin 4 to the power supply ground and pin 7 to a high impedance ground
PIN CONFIGURATION
8
4
6
5
+ V
OUT
2
+ V
IN
VRE305
10K
C
N
1F
OPTIONAL
NOISE REDUCTION
CAPACITOR
OPTIONAL
FINE TRIM
ADJUSTMENT
3
V TEMP OUT
7
REF. GND
5
6
7
8
VRE305
TOP
VIEW
1
2
3
4
N/C
+V
IN
TEMP
GND
NOISE
REDUCTION
REF. GND
V
OUT
TRIM
VRE306
VRE306DS 75
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
VRE306
DESCRIPTION
ence. Available in an industry standard 8-pin surface
mount package, the device is ideal for upgrading sys-
tems that use lower performance references.
dard 8-pin SMT package.
FEATURES
+6 V Output, 0.6 mV (.01%)
Low Noise: 4 V
P-P
(0.1-10Hz)
Industry Standard Pinout: 8-pin Surface Mount
Package
APPLICATIONS
Model
Initial Error
(mV)
Temp. Coeff.
(ppm/C)
Temp. Range
(C)
VRE306A
VRE306C
0.6
1.2
0.6
2.0
0C to +70C
0C to +70C
SELECTION GUIDE
8-pin Surface Mount
Package Style GD
MAR 2009
APEX VRE306DSREVC
VRE306
76 VRE306DS
V
PS
=15V, T = +25C, R
L
Model VRE306A VRE306C
Power Supply 14 15 16 * * * V
Operating Temperature (A,C) 0 +70 * * C
OUTPUT VOLTAGE
VRE306 +6.0 * V
Temp. Sensor Voltage (Note 1) 630 * mV
Initial Error (Note 2) 0.6 1.2 mV
T
MIN
- T
MAX
(Note3) 0.6 2.0 ppm/C
Noise (0.1 - 10Hz) (Note 4) 4 * Vpp
OUTPUT CURRENT
Range 10 mA
REGULATION
Line 6 10 * * ppm/V
Load 3 * ppm/mA
OUTPUT ADJUSTMENT
Range 10 * mV
VRE306 +PS 5 7 * * mA
NOTES:
* Same as A Models.
V
NOMINAL
x (T
MAX
T
MIN
)
V
MAX
V
MIN
T.C. = x 10
6
VRE306
VRE306DS 77
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Temperature
o
C
VRE306A
V
OUT
vs. TEMPERATURE V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE306C
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
ing input of the operational amplifer which amplifes the voltage to produce a 6.0V output. The gain is determined by
perature ranges.
VRE306
78 VRE306DS
8
4
6
5
+ V
OUT
2
+ V
IN
VRE306
10kW
C
N
1F
OPTIONAL
NOISE REDUCTION
CAPACITOR
OPTIONAL
FINE TRIM
ADJUSTMENT
3
V TEMP OUT
7
REF. GND
5
6
7
8
VRE306
TOP
VIEW
1
2
3
4
N/C
+V
IN
TEMP
GND
NOISE
REDUCTION
REF. GND
V
OUT
TRIM
IMPORTANT NOTICE
PIN CONFIGURATION
VRE310
VRE310DS 79
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
DESCRIPTION
ence. Available in an industry standard 8-pin DIP or
SMT, the device is ideal for upgrading systems that
dard 8-pin DIP or SMT package.
FEATURES
+10 V Output, 1.0 mV (.01%)
Low Noise: 6 V
P-P
(0.1-10Hz)
Industry Standard Pinout: 8-pin DIP or Surface
Mount Package
APPLICATIONS
ence for 14, 16, or 18-bit D/A converters which re-
Model
Initial Error
(mV)
Temp. Coeff.
(ppm/C)
Temp. Range
(C)
Package
Options
VRE310AS
VRE310AD
VRE310BS
VRE310BD
VRE310CS
VRE310CD
VRE310JS
VRE310JD
1.0
1.0
1.6
1.6
2.0
2.0
1.0
1.0
0.6
0.6
1.0
1.0
2.0
2.0
0.6
0.6
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
-40C to +85C
-40C to +85C
SMT8 (GD)
DIP8 (KD)
SMT8 (GD)
DIP8 (KD)
SMT8 (GD)
DIP8 (KD)
SMT8 (GD)
DIP8 (KD)
SELECTION GUIDE
8-pin Surface Mount
Package Style GD
8-pin DIP
Package Style KD
MAR 2009
APEX VRE310DSREVE
VRE310
80 VRE310DS
V
PS
=15V, T = +25C, R
L
Model A/J B C
Power Supply 13.5 15 22 * * * * * * V
Operating Temperature (J) -40 +85 * * * * C
OUTPUT VOLTAGE
VRE310 +10.0 * * V
T
MIN
- T
MAX
(Note3) 0.6 1.0 2.0 ppm/C
Noise (0.1 - 10Hz) (Note 4) 6 * * Vpp
OUTPUT CURRENT
Range 10 * mA
REGULATION
Line 6 10 * * * * ppm/V
Load 3 * * ppm/mA
OUTPUT ADJUSTMENT
Range 20 * * mV
VRE310 +PS 5 7 * * * * mA
NOTES:
V
NOMINAL
x (T
MAX
T
MIN
)
V
MAX
V
MIN
T.C. = x 10
6
VRE310
VRE310DS 81
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Temperature
o
C
VRE310A
V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE310B
V
OUT
vs. TEMPERATURE
V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE310C
Temperature
o
C
VRE310J
V
OUT
vs. TEMPERATURE
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
VRE310
82 VRE310DS
The following discussion refers to the block diagram in Figure 1. In operation, approximately 6.3 V is applied to
determined by the networks R1 and R2: G=1 + R2/R1. The 6.3 V zener diode is used because it is the most stable
By using highly stable resistors in our network, we produce a voltage reference that also has very good long term
stability.
The proper connection of the VRE310 series voltage references with the optional trim resistor is shown below. The
VRE310 reference has the ground terminal brought out on two pins (pin 4 and pin 7) which are connected together
internally. This allows the user to achieve greater accuracy when using a socket. Voltage references have a volt-
age drop across their power supply ground pin due to quiescent current fowing through the contact resistance. If
the contact resistance was constant with time and temperature, this voltage drop could be trimmed out. When the
reference is plugged into a socket, this source of error can be as high as 20 ppm. By connecting pin 4 to the power
supply ground and pin 7 to a high impedance ground point in the measurement circuit, the error due to the contact
resistance can be eliminated. If the unit is soldered into place, the contact resistance is suffciently small that it does
not effect performance. Pay careful attention to the circuit layout to avoid noise pickup and voltage drops in the lines.
PIN CONFIGURATION
8
4
6
5
+ V
OUT
2
+ V
IN
VRE310
10k
C
N
1F
OPTIONAL
NOISE REDUCTION
CAPACITOR
OPTIONAL
FINE TRIM
ADJUSTMENT
3
V TEMP OUT
7
REF. GND
5
6
7
8
VRE310
TOP
VIEW
1
2
3
4
N/C
+V
IN
TEMP
GND
NOISE
REDUCTION
REF. GND
V
OUT
TRIM
VRE405
VRE405DS 83
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
VRE405
DESCRIPTION
The VRE405 is a low cost, high precision, 5 V refer-
ence. Available in 14-pin DIP or SMT packages, the
device is ideal for new designs that need a high perfor-
mance reference.
The device provides ultrastable 5 V output with 0.5
compensation technique.
Another key feature of this reference is the 0.3 mV
maximum tracking error between the positive and neg-
ative output voltages over the operating temperature
range. This is extremely important in high performance
systems for reducing overall system errors.
For designs which use the DIP package in a socket,
there is a reference ground pin to eliminate the refer-
ence ground errors.
FEATURES
5 V Output, 0.5 mV (.01%)
Low Noise: 3 V
P-P
(0.1-10hz)
Tracking Error: 0.3 mV Max.
Surface Mount and DIP Package Options
APPLICATIONS
ence for high precision D/A and A/D converters
which require an external precision reference.
The device is ideal for calibrating scale factor on
high resolution A/D converters. The VRE405 of-
fers superior performance over monolithic refer-
ences.
Precision Dual Voltage Reference
Model
Initial
Error
(mV)
Temp.
Coeff.
(ppm/C)
Temp.
Range
(C)
Package
Options
VRE405AS
VRE405AD
VRE405BS
VRE405BD
VRE405CS
VRE405CD
0.5
0.5
0.8
0.8
1.0
1.0
0.6
0.6
1.0
1.0
2.0
2.0
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
SMT14 (GE)
DIP14 (KE)
SMT14 (GE)
DIP14 (KE)
SMT14 (GE)
DIP14 (KE)
SELECTION GUIDE
14-pin Surface Mount
Package Style GE
14-pin DIP
Package Style KE
MAR 2009
APEX VRE405DSREVB
VRE405
84 VRE405DS
V
PS
=15V, T = +25C, R
L
Model VRE405A VRE405B VRE405C
ABSOLUTE RATINGS
Power Supply 13.5 15 22 * * * * * * V
Operating Temperature 0 +70 * * * * C
OUTPUT VOLTAGE
VRE405 5.0 * * V
T
MIN
- T
MAX
(Note2) 0.6 1.0 2.0 ppm/C
Tracking Error 0.3 0.4 0.5 mV
Noise (0.1 - 10Hz) (Note 3) 3 * * Vpp
OUTPUT CURRENT
Range 10 * mA
REGULATION
Line 3 10 * * * * ppm/V
Load 3 * * ppm/mA
OUTPUT ADJUSTMENT
Range 20 * * mV
+PS 7 9 * * * * mA
-PS 4 6 * * * * mA
NOTES:
* Same as A Models.
2. The temperature coeffcient (TC) is determined by the box method using the following formula:
4. The tracking error is the deviation between the positive and negative output over the operating
temp. range.
V
NOMINAL
x (T
MAX
T
MIN
)
V
MAX
V
MIN
T.C. = x 10
6
VRE405
VRE405DS 85
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
Temperature
o
C
VRE405C
Temperature
o
C
VRE405B
V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE405A
V
OUT
vs. TEMPERATURE V
OUT
vs. TEMPERATURE
NEGATIVE OUTPUT (TYP)
VRE405
86 VRE405DS
perature ranges.
This proprietary network eliminates most of the nonlinearity in the voltage vs. temperature function. By adjusting the
The VRE405 reference has its ground terminal brought out on two pins (pin 6 and 7) which are connected internally.
This allows the user to achieve greater accuracy when using a socket. Voltage references have a voltage drop
across their power supply ground pin due to quiescent current fowing through the contact resistance. If the contact
resistance was constant with time and temperature, this voltage drop could be trimmed out. When the reference
is plugged into a socket, this source of error can be as high as 20 ppm. By connecting pin 7 to the power supply
ground and pin 6 to a high impedance ground point in the measurement circuit, the error due to the contact resis-
tance can be eliminated. If the unit is soldered into place, the contact resistance is suffciently small that it does not
effect performance.
PIN CONFIGURATION
11
12
13
14
VRE405
TOP
VIEW
1
2
3
4
N/C
+V
IN
GND
REF. GND
+V
OUT
5
6
7
10
9
8
- V
OUT
N/C
- V
IN
N/C
N/C
N/C
N/C
N/C
N/C
VRE410
VRE410DS 87
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
VRE410
DESCRIPTION
The VRE410 is a low cost, high precision, 10 V refer-
ence. Available in a 14-pin SMT package, the device
is ideal for new designs that need a high performance
reference.
The device provides ultrastable 10 V output with 1.0
compensation technique.
Another key feature of this reference is the 0.5 mV
maximum tracking error between the positive and neg-
ative output voltages over the full operating tempera-
ture range. This is extremely important in high perfor-
mance systems for reducing overall system errors.
FEATURES
10 V Output, 1.0 mV (.01%)
Low Noise: 6 V
P-P
(0.1-10Hz)
Tracking Error: 0.5 mV Max.
APPLICATIONS
ence for high precision D/A and A/D converters
which require an external precision reference.
The device is also ideal for calibrating scale factor
on high resolution A/D converters. The VRE410
offers superior performance over monolithic refer-
ences.
Precision Dual Voltage Reference
Model
Initial Error
(mV)
Temp. Coeff.
(ppm/C)
Temp. Range
(C)
VRE410A
VRE410B
VRE410C
VRE410J
VRE410L
1.0
1.6
2.0
1.0
2.0
0.6
1.0
2.0
0.6
2.0
0C to +70C
0C to +70C
0C to +70C
-40C to +85C
-40C to +85C
SELECTION GUIDE
14-pin Surface Mount
Package Style GE
MAR 2009
APEX VRE410DSREVB
VRE410
88 VRE410DS
4. The tracking error is the deviation be-
tween the positive and negative output
over the operating temp. range.
V
PS
=15V, T = +25C, R
L
Model A/J B C/L
ABSOLUTE RATINGS
Power Supply 13.5 15 22 * * * * * * V
Operating Temperature (J,L) -40 +85 * * * * C
OUTPUT VOLTAGE
VRE410 10.0 * * V
T
MIN
- T
MAX
(Note 2) 0.6 1.0 2.0 ppm/C
Tracking Error (Note 3) 0.5 0.7 1.0 mV
Noise (0.1 - 10Hz) 6 * * Vpp
OUTPUT CURRENT
Range 10 * mA
REGULATION
Line 3 10 * * * * ppm/V
Load 3 * * ppm/mA
+PS 7 9 * * * * mA
-PS 4 6 * * * * mA
NOTES:
1. The specifed values are without external
trim.
2. The temperature coeffcient (TC) is
determined by the box method using the
following formula:
V
NOMINAL
x (T
MAX
T
MIN
)
V
MAX
V
MIN
T.C. = x 10
6
VRE410
VRE410DS 89
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Temperature
o
C
VRE410A
V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE410B
V
OUT
vs. TEMPERATURE V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE410C
Temperature
o
C
VRE410J
V
OUT
vs. TEMPERATURE
Temperature
o
C
VRE410L
V
OUT
vs. TEMPERATURE
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
NEGATIVE OUTPUT (TYP)
VRE410
90 VRE410DS
The following discussion refers to the block diagram in Figure 1. In operation, approximately 6.3 V is applied to
determined by the networks R1 and R2: G=1 + R2/R1. The 6.3 V zener diode is used because it is the most stable
The VRE400 series voltage references have the ground terminal brought out on two pins (pin 6 and 7) which are
connected together internally. This allows the user to achieve greater accuracy when using a socket. Voltage ref-
erences have a voltage drop across their power supply ground pin due to quiescent current fowing through the
PIN CONFIGURATION
11
12
13
14
VRE410
TOP
VIEW
1
2
3
4
N/C
+V
IN
GND
REF. GND
+V
OUT
5
6
7
10
9
8
- V
OUT
N/C
- V
IN
N/C
N/C
N/C
N/C
N/C
N/C
VRE505
VRE505DS 91
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
VRE505
well, including initial accuracy, warm-up drift, line regu-
lation, and long-term stability, making the VRE505 the
most accurate reference available.
The VRE505 is recommended for use as a reference
for 14, 16, or 18 bit D/A converters which require an
external precision reference. The device is also ideal
for calibrating scale factor on high resolution A/D con-
verters. The VRE505 offers superior performance over
monolithic references.
FEATURES
+5 V Output, 1.0 mV (.02%)
Temperature Drift: 1 ppm/C
Low Noise: 3 V
P-P
(0.1-10 Hz)
Package
Excellent Line Regulation: 6 ppm/V Typ.
DESCRIPTION
ence. The device is ideal for upgrading systems that
Model
Initial Error
(mV)
Temp. Coeff.
(ppm/C)
Temp. Range
(C)
VRE505K 1.0 2.0 -40C to +85C
SELECTION GUIDE
8-pin Surface Mount
Package Style GF
AUG 2009
APEX - VRE505DSREVC
VRE505
92 VRE505DS
V
PS
= +15V, T = +25C, R
L
Parameter Min Typ Max Units
ABSOLUTE RATINGS
Power Supply 13.5 15 22 V
Operating Temperature -40 +85 C
Storage Temperature -65 +150 C
Short Circuit Protection Continuous
OUTPUT VOLTAGE
VRE505 +5.0 V
Temperature Sensor Voltage (Note 1) 630
Initial Error (Note 2) 1.0 mV
Warmup Drift 2 ppm
T
MIN
- T
MAX
(Note 3) 2.0 ppm/C
Long-Term Stability 6 ppm/1000hrs.
Noise (0.1 - 10Hz) (Note 4) 3 Vpp
OUTPUT CURRENT
Range 10 mA
REGULATION
Line 6 10 ppm/V
Load 3 ppm/mA
OUTPUT ADJUSTMENT
Range 10 mV
+PS 5 7 mA
NOTES:
1. The temp. reference T
C
is 2.1 mV/C
V
NOMINAL
x (T
MAX
T
MIN
)
V
MAX
V
MIN
TC = x 10
6
VRE505
VRE505DS 93
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Temperature
o
C
VRE505K
V
OUT
vs. TEMPERATURE
Temperature
o
C
Output Current (mA)
PSRR VS. FREQUENCY
Frequency (Hz)
The following discussion refers to the Block Diagram. A FET current source is used to bias a 6.3 V zener diode.
The zener voltage is divided by the resistor network R1 and R2. This voltage is then applied to the noninverting
input of the operational amplifer which amplifes the voltage to produce a 5.0 V output. The gain is determined by
the resistor networks R3 and R4: G = 1 + R4/R3. The 6.3 V zener diode is used because it is the most stable diode
perature ranges.
slope, this device produces a very stable voltage over wide temperature ranges.
VRE505
94 VRE505DS
5
6
7
8
VRE505
TOP
VIEW
1
2
3
4
N/C
+V
IN
TEMP
GND
NOISE
REDUCTION
REF. GND
V
OUT
TRIM
8
4
6
5
+ V
OUT
2
+ V
IN
VRE505
10K
C
N
1F
OPTIONAL
NOISE REDUCTION
CAPACITOR
OPTIONAL
FINE TRIM
ADJUSTMENT
3
V TEMP OUT
7
REF. GND
PIN CONFIGURATION
IMPORTANT NOTICE
VRE3025
VRE3025DS 95
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
DESCRIPTION
The VRE3025 is a low cost, high precision +2.5 V ref-
erence that operates from +10 V. The device features
a buried zener for low noise and excellent long term
stability. Packaged in either an 8-pin DIP or SMT op-
tion, the device is ideal for high resolution data conver-
sion systems.
line regulation, and long-term stability, making the
VRE3025 series the most accurate reference avail-
able.
initial error. For ultra low noise applications, an exter-
nal capacitor can be attached between the noise re-
duction pin and the ground pin.
FEATURES
+2.5 V Output, 0.25 mV (.01%)
Temperature Drift: 0.6 ppm/c
Low Noise: 1.5 V
P-P
(0.1Hz-10Hz)
Low Thermal Hysteresis: 1 ppm Typical
15 mA Output Source and Sink Current
Optional Noise Reduction and Voltage Trim
Industry Standard Pinout: 8-pin DIP or
APPLICATIONS
ence for 14, 16, or 18 bit data converters which re-
resolution data converters. The VRE3025 offers
superior performance over monolithic references.
6
8
5
2
4
R1
R2
R3
R4
+
-
Model
Initial
Error
(mV)
Temp.
Coeff.
(ppm/C)
Temp. Range
(C)
Package
Options
VRE3025AS
VRE3025AD
VRE3025BS
VRE3025BD
VRE3025CS
VRE3025CD
VRE3025JS
VRE3025JD
VRE3025LS
0.250
0.250
0.375
0.375
0.500
0.500
0.250
0.250
0.500
0.6
0.6
1.0
1.0
2.0
2.0
0.6
0.6
2.0
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
-40C to +85C
-40C to +85C
-40C to +85C
SMT8 (GF)
DIP8 (KD)
SMT8 (GF)
DIP8 (KD)
SMT8 (GF)
DIP8 (KD)
SMT8 (GF)
DIP8 (KD)
SMT8 (GF)
SELECTION GUIDE
8-pin Surface Mount
Package Style GF
8-pin DIP
Package Style KD
JUN 2009
APEX VRE3025DSREVG
VRE3025
96 VRE3025DS
Parameter Symbol Conditions Min Typ Max Units
Input Voltage V
IN
+8 +36 V
Output Voltage (Note 1) V
OUT
VRE3025A/J +2.4998 +2.500 +2.5003
V VRE3025B +2.4996 +2.500 +2.5004
VRE3025C/L +2.4995 +2.500 +2.5005
Output Voltage
Temperature Coeffcient
(Note 2)
TCV
OUT
VRE3025A/J 0.3 0.6
ppm/C VRE3025B 0.5 1.0
VRE3025C/L 1.0 2.0
Trim Adjustment Range V
OUT
Figure 3 2.5 mV
Turn-On Settling Time T
ON
To 0.01% of fnal value 2 s
Output Noise Voltage e
n
0.1Hz < f < 10Hz 1.5 Vp-p
10Hz < f < 1kHz 1.5 3.0 V
RMS
Temperature Hysterisis Note 4 1 ppm
Long Term Stability V
OUT/t
6 ppm/1000hrs.
Supply Current I
IN
3.5 4.0 mA
Load Regualtion V
OUT
/ I
OUT
Sourcing: 0mA I
OUT
15mA 8 12
ppm/mA
Sinking: -15mA I
OUT
0mA 8 12
Line Regulation V
OUT
/ V
IN
8V V
IN
10V 25 35
ppm/V
10V V
IN
18V 5 10
NOTES:
2. The temperature coeffcient is determined by the box method. See discussion on temperature perfor-
mance.
3. Line and load regulation are measured with pulses and do not include voltage changes due to tem-
perature.
4. Hysterisis over the operating temperature range.
Power Supply ........................... -0.3V to +40V
OUT, TRIM ................................ -0.3V to +12V
NR .............................................. -0.3V to +6V
Operating Temp. (A,B,C) ........... 0C to +70C
Operating Temp. (J,L) ............. -40C to +85C
Out Short Circuit to GND Duration (V
IN
< 12V) ........... Continuous
IN
< 40V) .....................5 sec
Out Short Circuit to IN Duration (V
IN
< 12V) ............... Continuous
Continuous Power Dissipation (T
A
= +70C) ....................300mW
Storage Temperature ......................................... -65C to +150C
Lead Temperature (soldering,10 sec) .............................. +250C
V
PS
=15V, T = +25C, R
L
VRE3025
VRE3025DS 97
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Temperature (
o
C)
VRE3025A
V
OUT
vs. TEMPERATURE
SUPPLY CURRENT
VS. SUPPLY VOLTAGE
Temperature (
o
C)
OUTPUT IMPEDIANCE
VS. FREQUENCY
Temperature (
o
C)
VRE3025B
V
OUT
vs. TEMPERATURE V
OUT
vs. TEMPERATURE
Temperature (
o
C)
VRE3025C
Temperature (
o
C)
VRE3025J
V
OUT
vs. TEMPERATURE
Temperature (
o
C)
VRE3025L
V
OUT
vs. TEMPERATURE
Supply Voltage (V)
S
u
p
p
l
y

C
u
r
r
e
n
t

(
m
A
)
Frequency (Hz)
V
o
u
t
(
m
V
)
V
o
u
t
(
m
V
)
V
o
u
t
(
m
V
)
V
o
u
t
(
m
V
)
V
o
u
t
(
m
V
)
Q
u
i
e
s
c
e
n
t

C
u
r
r
e
n
t

(
m
A
)
O
u
t
p
u
t

I
m
p
e
d
i
a
n
c
e
(

)
0 50 -50 100
6.0
4.0
2.0
0
8.0
15 25 5 35
5.0
4.0
3.0
0
6.0
10 20 30 40 0
-50 -25 0 25 50 75 100
2.0
1.5
1.0
0.5
0
-1.0
-0.5
-1.5
-2.0
Lower Limit
Upper Limit
0 20 30 40 50 60 70
1.00
0.75
0.50
0.25
0
-0.50
-0.25
-0.75
-1.00
Lower Limit
Upper Limit
0 20 30 40 50 60 70
1.00
0.75
0.50
0.25
0
-0.50
-0.25
-0.75
-1.00
Lower Li mi t
Upper Li mi t
Lower Limit
Upper Limit
-0.75
0 20 30 40 50 60 70
1.00
0.75
0.50
0.25
0
-0.50
-0.25
-1.00
Lower Limit
Upper Limit
-50 -25 0 25 50 75 100
2.0
1.5
1.0
0.5
0
-1.0
-0.5
-1.5
-2.0
Lower Limit
Upper Limit
RIPPLE REJ ECTION
Vs. FREQUENCY(C
NR
=0F)
J UNCTION TEMP. RISE VS.
OUTPUT CURRENT
Output Current (mA) Frequency (Hz)
1k 10k
90
80
70
60
100
100 10 0 4 2 8 6 10
30
20
10
0
40
V
c
c
=
1
0
V
R
i
p
p
l
e

R
e
j
e
c
t
i
o
n

(
d
B
)
J
u
n
c
t
i
o
n

T
e
m
p
e
r
a
t
u
r
e
R
i
s
e

A
b
o
v
e

A
m
b
i
e
n
t

(
o
C
)
TURN-ON AND TURN-OFF
TRANSIENT RESPONSE
1 s/div
B
A
0V
+10V
A: Vin, 10V/div
B: Vout, 1V/div
VRE3025
98 VRE3025DS
perature ranges.
This network is less than 2% of the overall network resistance so it has a negligible effect on long term stability. The
proper connection of the VRE3025 series voltage references with the optional trim resistor for initial error and the
optional capacitor for noise reduction is shown below.
OUTPUT NOISE-VOLTAGE
DENSITY vs. FREQUENCY
CHANGE IN OUTPUT VOLTAGE
VS. INPUT VOLTAGE
VS. OUTPUT CURRENT
V
in
(V)
V
o
u
t

(
p
p
m
)
I
out
(mA)
V
o
u
t

(
V
)
Frequency (Hz)
12 13 9 15
20
0
-20
14 16 11 10 0
-10
10
30
40
50
60
O
u
t
p
u
t

N
o
i
s
e

D
e
n
s
i
t
y

(
n
V
/
H
z
)
8 10 2 14
0
-200
-400
12 16 6 4 0
-300
-100
100
200
300
400
1k 10k
40
30
20
10
50
100 10
0.1Hz to 10Hz Noise
V
o
u
t
,

0
.
5
V
/
D
i
v
1 Sec/Div
VRE3025
VRE3025DS 99
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PIN DESCRIPTIONS
1, 3, 7 N. C. Internally connected. Do not use
2 V
IN
Positive power supply input
4 GND Ground
5 TRIM External trim input. Leave open if not
used.
6 OUT Voltage reference output
8 NR Noise Reduction
4. BASIC CIRCUIT CONNECTION
To achieve the specifed performance, pay careful attention to the layout. A low resistance star confguration will
reduce voltage errors, noise pickup, and noise coupled from the power supply. Commons should be connected to
a single point to minimize interconnect resistances.
5. TEMPERATURE PERFORMANCE
The VRE3025 is designed for applications where the initial error at room temperature and drift over temperature are
important to the user. For many instrument manufacturers, a voltage reference with a temperature coeffcient less
than 1 ppm/C makes it possible to not have to perform a system temperature calibration, a slow and costly process.
Of the three TC specifcation methods (slope, butterfy, and box), the box method is used commonly used. A box
is formed by the min/max limits for the nominal output voltage over the operating temperature range. The equation
follows:

V
NOMINAL
x (T
MAX
T
MIN
)
V
MAX
V
MIN
T.C. = x 10
6
This method corresponds more accurately to the method of test and provides a closer estimate of actual error than
the other methods. The box method guarantees limits for the temperature error but does not specify the exact shape
and slope of the device under test.
A designer who needs a 14-bit accurate data acquisition system over the industrial temperature range (-40C to
+85C), will need a voltage reference with a temperature coeffcient (TC) of 1.0 ppm/C if the reference is allowed
to contribute an error equivalent to 1LSB. For 1/2LSB equivalent error from the reference you would need a volt-
age reference with a temperature coeffcient of 0.5 ppm/C. Figure 4 shows the required reference TC vs. delta T
change from 25C for resolution ranging from 8 bits to 20 bits.
8
6
5
+V
OUT
2
+V
IN
4
VRE3025
10k
C
N
1F
Optional Noise
Reduction
Capacitor
Optional Fine
Trim Adjustment
VRE3025
100 VRE3025DS
6. THERMAL HYSTERISIS
A change in output voltage as a result of a temperature change. When references experience a temperature change
and return to the initial temperature, they do not always have the same initial voltage. Thermal hysterisis is diffcult to
correct and is a major error source in systems that experience temperature changes greater than 25C. Reference
vendors are starting to include this important specifcation in their datasheets.
PIN CONFIGURATION
IMPORTANT NOTICE
0.01
0.1
1
10
100
1000
10000
0 0 1 0 1 1
20 BIT
18 BIT
16 BIT
14 BIT
12 BIT
10 BIT
8 BIT
R
e
f
e
r
e
n
c
e

T
C

(
p
p
m
/
C
)
Reference TC vs. T change from 25C for 1 LSB change
5
6
7
8
VRE3025
TOP
VIEW
1
2
3
4
N/C
+V
IN
N/C
GND
NOISE
REDUCTION
V
OUT
TRIM
N/C
VRE3050
VRE3050DS 101
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
VRE3050
DESCRIPTION
The VRE3050 is a low cost, high precision 5 V refer-
ence that operates from +10 V. The device features
a buried zener for low noise and excellent long term
stability. Packaged in an 8-pin SMT, the device is ideal
for high resolution data conversion systems.
well, including initial accuracy, warm-up drift, line reg-
ulation, and long-term stability, making the VRE3050
series the most accurate reference available.
initial error. For ultra low noise applications, an exter-
nal capacitor can be attached between the noise re-
duction pin and the ground pin.
FEATURES
+5 V Output, 0.5 mV (.01%)
Low Noise: 3 V
P-P
(0.1Hz-10Hz)
Low Thermal Hysterisis: 1 ppm Typical
15mA Output Source and Sink Current
Optional Noise Reduction and Voltage Trim
Package
APPLICATIONS
ence for 14, 16, or 18 bit data converters which re-
resolution data converters. The VRE3050 offers
superior performance over monolithic references.
6
8
5
2
4
R1
R2
R3
R4
+
-
Model
Initial Error
(mV)
Temp. Coeff.
(ppm/C)
Temp. Range
(C)
VRE3050A
VRE3050B
VRE3050C
VRE3050J
VRE3050K
VRE3050L
0.5
0.8
1.0
0.5
0.8
1.0
0.6
1.0
2.0
0.6
1.0
2.0
0C to +70C
0C to +70C
0C to +70C
-40C to +85C
-40C to +85C
-40C to +85C
SELECTION GUIDE
8-pin Surface Mount
Package Style GF
MAR 2009
APEX VRE3050DSREVF
VRE3050
102 VRE3050DS
Input Voltage V
IN
+8 +36 V
Output Voltage (Note 1) V
OUT
VRE3050A/J +2.4995 +5.0000 +5.0005
V VRE3050B/K +2.4992 +5.0000 +5.0008
VRE3050C/L +2.4990 +5.0000 +5.0010
Output Voltage
(Note 2)
TCV
OUT
VRE3050A/J 0.3 0.6
ppm/C VRE3050B/K 0.5 1.0
VRE3050C/L 1.0 2.0
Trim Adjustment Range V
OUT
Figure 3 5.0 mV
ON
To 0.01% of fnal value 2.0 s
Output Noise Voltage e
n
0.1Hz < f < 10Hz 3.0 Vp-p
10Hz < f < 1kHz 2.5 5.0 V
RMS
Temperature Hysterisis Note 4 1 ppm
OUT/t
6 ppm/1000hrs.
Supply Current I
IN
3.5 4.0 mA
Load Regualtion (Note 3) V
OUT
/ I
OUT
Sourcing: 0mA I
OUT
15mA 8 12
ppm/mA
Sinking: -15mA I
OUT
0mA 8 12
Line Regulation (Note 3) V
OUT
/ V
IN
8V V
IN
10V 25 35
ppm/V
10V V
IN
18V 5 10
NOTES:
mance.
3. Line and load regulation are measured with pulses and do not include voltage changes due to tem-
perature.
4. Hysterisis over the operating temperature range.
Power Supply ........................... -0.3V to +40V
OUT, TRIM ................................ -0.3V to +12V
NR .............................................. -0.3V to +6V
Operating Temp. (A,B,C) ........... 0C to +70C
Operating Temp. (J,K,L) ......... -40C to +85C
IN
< 12V) ........... Continuous
IN
< 40V) .....................5 sec
Out Short Circuit to IN Duration (V
IN
< 12V) ............... Continuous
Continuous Power Dissipation (T
A
= +70C) ....................300mW
Storage Temperature ......................................... -65C to +150C
Lead Temperature (soldering,10 sec) .............................. +250C
V
PS
=15V, T = +25C, R
L
VRE3050
VRE3050DS 103
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Temperature (
o
C)
VRE3050A
V
OUT
vs. TEMPERATURE
SUPPLY CURRENT
VS. SUPPLY VOLTAGE
Temperature (
o
C)
OUTPUT IMPEDIANCE
VS. FREQUENCY
Temperature (
o
C)
VRE3050B
V
OUT
vs. TEMPERATURE V
OUT
vs. TEMPERATURE
Temperature (
o
C)
VRE3050C
Temperature (
o
C)
VRE3050J
V
OUT
vs. TEMPERATURE
Temperature (
o
C)
VRE3050K
V
OUT
vs. TEMPERATURE
Temperature (
o
C)
VRE3050L
V
OUT
vs. TEMPERATURE
Supply Voltage (V)
S
u
p
p
l
y

C
u
r
r
e
n
t

(
m
A
)
Frequency (Hz)
V
o
u
t
(
m
V
)
V
o
u
t
(
m
V
)
V
o
u
t
(
m
V
)
V
o
u
t
(
m
V
)
V
o
u
t
(
m
V
)
V
o
u
t
(
m
V
)
Q
u
i
e
s
c
e
n
t

C
u
r
r
e
n
t

(
m
A
)
O
u
t
p
u
t

I
m
p
e
d
i
a
n
c
e
(

)
0 50 -50 100
6.0
4.0
2.0
0
8.0
15 25 5 35
5.0
4.0
3.0
0
6.0
10 20 30 40 0
-50 -25 0 25 50 75 100
2.0
1.5
1.0
0.5
0
-1.0
-0.5
-1.5
-2.0
Lower Limit
Upper Limit
-50 -25 0 25 50 75 100
2.0
1.5
1.0
0.5
0
-1.0
-0.5
-1.5
-2.0
Lower Limit
Upper Limit
0 20 30 40 50 60 70
1.00
0.75
0.50
0.25
0
-0.50
-0.25
-0.75
-1.00
Lower Limit
Upper Limit
0 20 30 40 50 60 70
1.00
0.75
0.50
0.25
0
-0.50
-0.25
-0.75
-1.00
Lower Li mi t
Upper Li mi t
Lower Limit
Upper Limit
-0.75
0 20 30 40 50 60 70
1.00
0.75
0.50
0.25
0
-0.50
-0.25
-1.00
Lower Limit
Upper Limit
-50 -25 0 25 50 75 100
2.0
1.5
1.0
0.5
0
-1.0
-0.5
-1.5
-2.0
Lower Limit
Upper Limit
VRE3050
104 VRE3050DS
RIPPLE REJ ECTION
Vs. FREQUENCY(C
NR
=0F)
OUTPUT NOISE-VOLTAGE
DENSITY vs. FREQUENCY
TURN-ON AND TURN-OFF
TRANSIENT RESPONSE
J UNCTION TEMP. RISE VS.
OUTPUT CURRENT
Output Current (mA)
VS. INPUT VOLTAGE
VS. OUTPUT CURRENT
V
in
(V)
V
o
u
t

(
p
p
m
)
I
out
(mA)
V
o
u
t

(
V
)
Frequency (Hz)
Frequency (Hz)
0 4 2 8 6 10
30
20
10
0
40
V
c
c
=
1
0
V
12 13 9 15
20
0
-20
14 16 11 10 0
-10
10
30
40
50
60
R
i
p
p
l
e

R
e
j
e
c
t
i
o
n

(
d
B
)
J
u
n
c
t
i
o
n

T
e
m
p
e
r
a
t
u
r
e
R
i
s
e

A
b
o
v
e

A
m
b
i
e
n
t

(
o
C
)
O
u
t
p
u
t

N
o
i
s
e

D
e
n
s
i
t
y

(
n
V
/
H
z
)
8 10 2 14
0
-200
-400
12 16 6 4 0
-300
-100
100
200
300
400
1 s/div
B
A
0V
+10V
A: Vin, 10V/div
B: Vout, 1V/div
1k 10k
90
80
70
60
100
100 10
1k 10k
80
60
40
20
100
100 10
0.1Hz to 10Hz Noise
V
o
u
t
,

1
V
/
D
i
v
1 Sec/Div
VRE3050
VRE3050DS 105
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
perature ranges.
This network is less than 2% of the overall network resistance so it has a negligible effect on long term stability. The
proper connection of the VRE3050 series voltage references with the optional trim resistor for initial error and the
optional capacitor for noise reduction is shown below.
PIN DESCRIPTION
1, 3, 7 N. C. Internally connected. Do not use
2 V
IN
4 GND Ground
5 TRIM External trim input. Leave open if not
used.
6 OUT Voltage reference output
8 NR Noise Reduction
To achieve the specifed performance, pay careful attention to the layout. A low resistance star confguration will
reduce voltage errors, noise pickup, and noise coupled from the power supply. Commons should be connected to
a single point to minimize interconnect resistances.
8
6
5
+V
OUT
2
+V
IN
4
VRE3050
10k
C
N
1F
Optional Noise
Reduction
Capacitor
Optional Fine
Trim Adjustment
VRE3050
106 VRE3050DS
Figure 3.
The VRE3050 is designed for applications where the initial error at room temperature and drift over temperature
are important to the user. For many instrument manufacturers, a voltage reference with a temperature coeffcient
less than 1 ppm/C makes it possible to not perform a system temperature calibration, a slow and costly process.
Of the three TC specifcation methods (slope, butterfy, and box), the box method is most commonly used. A box
follows:

V
NOMINAL
x (T
MAX
T
MIN
)
V
MAX
V
MIN
T.C. = x 10
6
and slope of the device under test.
A designer who needs a 14-bit accurate data acquisition system over the industrial temperature range (-40C to
+85C), will need a voltage reference with a temperature coeffcient (TC) of 1 ppm/C if the reference is allowed
to contribute an error equivalent to 1LSB. For 1/2LSB equivalent error from the reference you would need a volt-
age reference with a temperature coeffcient of 0.5 ppm/C. Figure 4 shows the required reference TC vs. delta T
change from 25C for resolution ranging from 8 bits to 20 bits.
6. THERMAL HYSTERISIS
A change in output voltage as a result of a temperature change. When references experience a temperature change
and return to the initial temperature, they do not always have the same initial voltage. Thermal hysterisis is diffcult to
correct and is a major error source in systems that experience temperature changes greater than 25C. Reference
vendors are starting to include this important specifcation in their datasheets.
PIN CONFIGURATION
0.01
0.1
1
10
100
1000
10000
0 0 1 0 1 1
20 BIT
18 BIT
16 BIT
14 BIT
12 BIT
10 BIT
8 BIT
R
e
f
e
r
e
n
c
e

T
C

(
p
p
m
/
C
5
6
7
8
VRE3050
TOP
VIEW
1
2
3
4
N/C
+V
IN
N/C
GND
NOISE
REDUCTION
V
OUT
TRIM
N/C
VRE4100
VRE4100DS 107
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
VRE4112, VRE4125, VRE4141
APPLICATIONS
This series is recommended for use as a reference for
14, 16, or 18-bit data converters which require a preci-
sion reference. The series offers superior performance
over standard on-chip references commonly found
with data converters.
DESCRIPTION
The VRE4112/VRE4125/VRE4141 are low cost, high
precision bandgap references that operate from +5 V.
These devices feature low noise, digital error correc-
tion, and an SOIC-8 package. The ultra stable output
is 0.05% accurate with a temperature coeffcient as
low as 1.0 ppm/C. The improvement in overall accu-
racy is made possible by using EEPROM registers and
CMOS DACs for temperature and initial error correc-
tion. The DAC trimming is done after assembly which
eliminates assembly related shifts.
FEATURES
+1.250, +2.500, +4.096 V Output
Initial Error: 0.05% Max.
Temperature Drift: 1.0 ppm/C Max.
Low Noise: 2.2 V
P-P
(0.1 Hz-10 Hz, 1.024 V)
Low Thermal Hysteresis: 20 ppm
8 mA Output Source
Power Down Mode
Industry Standard SOIC 8-pin Package
Commercial and Industrial Temp Ranges
Second source for ADR29X, REF19X ,LT1460,
LT1461, LT1798, MAX616X, REF102
VRE4112
VRE4125
VRE4141
Model
Output
(V)
Temp. Coeff.
(ppm/C)
Temp. Range
(C)
VRE4112C
VRE4112K
+1.250
+1.250
2.0
3.0
0C to +70C
-40C to +85C
VRE4125B
VRE4125K
+2.500
+2.500
1.0
3.0
0C to +70C
-40C to +85C
VRE4141B
VRE4141K
+4.096
+4.096
1.0
3.0
0C to +70C
-40C to +85C
SELECTION GUIDE
8-pin SOIC
Package Style FX
AUG 2009
APEX VRE4100DSREVB
VRE4100
108 VRE4100DS
Input Voltage V
IN
+1.8 +5.5 V
Output Voltage Error
(Note 1)
V
OUT
B Grade 0.025 0.050
%
C/K Grade 0.040 0.080
Output Voltage
(Note 2)
TCV
OUT
B Grade +0.5 +1.0
ppm/C C Grade +1.0 +2.0
K Grade +1.5 +3.0
Dropout Voltage (Note 3) V
IN
- V
OUT
I
L
= 8mA 160 235 mV
ON
To 0.01% of fnal value 2 s
Output Noise Voltage
(Note 4)
E
n
0.1Hz < f < 10Hz 2.2 Vp-p
Temperature Hysteresis Note 5 20 ppm
OUT/T
1000 Hours 50 ppm
Supply Current I
IN
V
LOAD
= 0mA 230 320 A
Load Regulation (Note 6) V
OUT
/ I
OUT
1mA I
LOAD
8mA 1 20 ppm/mA
Line Regulation (Note 6) V
OUT
/ V
IN
V
REF
+ 200mV V
IN
5.5V 20 200 ppm/V
Logic High Input Voltage V
H
0.8 V
Logic High Input Current I
H
2 nA
Logic Low Input Voltage V
L
0.4 V
Logic Low Input Current I
L
1 nA
NOTES:
1. High temperature and mechanical stress can effect the initial accuracy of this reference series.See
discussion on output accuracy.
mance. All units are 100% tested over temperature.
3. The minimum input to output differential voltage at which the output voltage drops by 0.5% from
nominal.
4. Based on 1.024 V output. Noise is linearly proportional to V
REF
.
5. Defned as change in 25C output voltage after cycling device over operating temperature range.
6. Line and load regulation are measured with pulses and do not include output voltage changes due to
self heating.
Power Supply to any input pin ......-0.3V to +5.6V
Operating Temp. (B,C) ...................... 0C to 70C
Operating Temp. (K) ....................-40C to +85C
Storage Temperature Range .....-65C to +150C
Output Short Circuit Duration .............................. Indefnite
ESD Susceptibility Human Body Model....................... 2kV
ESD Susceptibility Machine Model ............................ 200V
Lead Temperature (soldering, 10 sec) ....................+260C
V
PS
= +3 V for VRE4112, V
PS
= +5 V for VRE4125 and VRE4141. T = +25C, I
LOAD
= 1mA, C
OUT
= 1F Unless Otherwise Noted.
VRE4100
VRE4100DS 109
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GROUND CURRENT vs. LOAD CURRENT
LOAD CURRENT (mA)
2 10 6 0.1
500
200
300
400
G
R
O
U
N
D

C
U
R
R
E
N
T

(
A
)
0C
70C
25C
TOTAL CURRENT (Is
(OFF)
) vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
1 4 3 2 0
16
6
8
10
12
14
T
O
T
A
L

C
U
R
R
E
N
T

(
A
)
0
2
4
6 5
-2
V
EN
=0.4V
2.048V
TOTAL CURRENT (Is
(ON)
) vs. SUPPLY VOLTAGE
0
SUPPLY VOLTAGE (V)
6 5 4 3 2 1
0
800
700
600
500
400
300
200
100
-100
T
O
T
A
L

C
U
R
R
E
N
T

(
A
)
1.024V & 1.25V
2.048V
2.50V
4.096V
V
EN
=V
IN
- 0.8V
POWER SUPPLY REJECTION RATIO
FREQUENCY (Hz)
1K 1M 100K 10K 100
0
-50
-40
-30
-20
-10
P
S
R
R

(
d
B
)
-80
-70
-60
10
OUTPUT IMPEDANCE
FREQUENCY (Hz)
1K 1M 100K 10K 100
8
3
4
5
6
7
Z
O

(
)
0
1
2
ENABLE RESPONSE
I
LOAD
=10mA
TIME (ms)
10 0 5
5.0V
V
IN
I
GND
*
V
REF
35mA
4.096V
LINE TRANSIENT RESPONSE
C
IN
=0
I
LOAD
=10mA
TIME (ms)
1 0 0.5
500mV
V
IN
V
REF
20mV
POWER UP/DOWN GROUND CURRENT
I
LOAD
=10mA
TIME (ms)
10 0 5
5.0V
V
IN
I
GND
*
V
REF
48mA
4.096V
LINE REGULATION vs. TEMPERATURE
TEMPERATURE (C)
20 70 50 30 0
50
-75
-50
-25
0
25
L
I
N
E

R
E
G
.

(
P
P
M
/
V
)
LOAD TRANSIENT RESPONSE
I
LOAD
=10mA
TIME (ms)
1 0 0.5
50 mV
10 mA
OUTPUT VOLTAGE vs. LOAD CURRENT
SOURCE CURRENT (mA)
2 10 6 0.1
100
-150
-100
-50
0
50
O
U
T
P
U
T

V
O
L
T
A
G
E

C
H
A
N
G
E

(
P
P
M
/
V
)
0C
70C 25C
LOAD REGULATION vs. TEMPERATURE
TEMPERATURE (C)
20 70 50 30 0
35
-15
-5
5
15
25
L
O
A
D

R
E
G
.

(
P
P
M
/
m
A
)
VRE4100
110 VRE4100DS
SPECTRAL NOISE DENSITY (10HZ TO 100KHZ)
FREQUENCY (Hz)
10 8 6 4 2 0
100
10
1
0.1
N
O
I
S
E

D
E
N
S
I
T
Y

(
V
/
H
z
)
1000
SPECTRAL NOISE DENSITY (0.1HZ TO 10HZ)
FREQUENCY (Hz)
10 8 6 4 2 0
100
10
1
0.1
N
O
I
S
E

D
E
N
S
I
T
Y

(
V
/
H
z
)
DROPOUT VOLTAGE vs. LOAD CURRENT
(V
OUT
) =2.0V
LOAD CURRENT (mA)
70C
0C
25C
100A 10 8 6 4 2 1
-50
250
200
150
100
50
0
D
R
O
P
O
U
T

V
O
L
T
A
G
E

(
m
V
)
I
Q
vs. TEMPERATURE
TEMPERATURE (C)
0 70 50 30 20
280
260
240
220
I
Q

(
A
)
DROPOUT VOLTAGE vs. LOAD CURRENT
LOAD CURRENT (mA)
2.048V
2.50V
4.096V
0 12 10 8 6 4 2
0
0.3
0.25
0.2
0.15
0.1
0.05
D
R
O
P
O
U
T

V
O
L
T
A
G
E

(
V
)
OUTPUT VOLTAGE CHANGE vs. SINK CURRENT I
(SINK)
V
IN
=V
EN
=5.0V
SINK CURRENT (A)
2.048V
2.50V
1.024V
1.25V
4.096V
-30 0 -5 -10 -15 -20 -25
-20
140
120
100
80
60
40
20
0
O
U
T
P
U
T

V
O
L
T
A
G
E

C
H
A
N
G
E

(
%
)
2. TYPICAL PERFORMANCE CURVES, Cont.
This series is designed for applications where the initial error at room temperature and drift over temperature are
important to the user. For many instrument manufacturers, a voltage reference with a temperature coeffcient of
1ppm/C makes it possible to eliminate a system temperature calibration, a slow and costly process.
Of the three TC specifcation methods (slope, butterfy, and box), the box method is most commonly used. A box
follows:

V
NOMINAL
x (T
MAX
T
MIN
)
V
MAX
V
MIN
TC = x 10
6
or slope of the device under test.
The proper connection for the VRE4112/VRE4125/
VRE4141 series voltage references is shown here.
To achieve the specifed performance, pay careful
attention to the layout. Commons should be con-
nected to a single point to minimize interconnect
resistances. This will reduce voltage errors, noise
pickup, and noise coupled from the power supply.
2
6
+V
OUT
3
+V
IN
VRE4112
VRE4125
VRE4141
NC
Enable
4
C
OUT
1F
1,5,7,8
VRE4100
VRE4100DS 111
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PIN DESCRIPTION
4 GND These must be connected to ground
2 V
IN
3 Enable Pulled to V
IN
for nominal operation
1,5,7,8 NC This pin must be left open
6 V
OUT
Reference output
For example a designer who needs a 14-bit accurate data acquisition system over the industrial temperature range
(-40C to +85C), will need a voltage reference with a temperature coeffcient (TC) of 1.0ppm/C if the reference is
allowed to contribute an error equivalent to 1LSB. The required reference TC vs. T change from 25C for resolution
ranging from 8 bits to 20 bits is shown below.
5. OPERATIONAL NOTES
INPUT CAPACITOR
An input capacitor is recommended for the VRE4112/VRE4125/VRE4141. A supply bypass capacitor on the input
will assure that the reference is working from a low impedance source which will improve stability. It can improve
the transient response when the load current is suddenly increased.
OUTPUT CAPACITOR
This series requires a 1 F output capacitor for loop stabilization (compensation) as well as transient response.
When the load current changes, the output capacitor must source or sink current during the time it takes the control
loop of the device to respond.
The output capacitor must meet the requirements of minimum capacitance and equivalent series resistance (ESR)
range. See Capacitor Selection below.
CAPACITOR SELECTION
A minimum value of 0.2 F over the operating temperature range is recommended. For a 0.22 F capacitor the ESR
range for 0C to +70C is 0.9 to 6.0; 1.0 F is 0.8 to 6.0; and 10 F is 0.4 to 7.0.
Surface mount tantalum capacitors offer small size for the value and ESR in the range required for this series. The
optimum performance for the output capacitor is achieved with a 1.0 F value.
Aluminum electrolytic capacitors have a relatively large size for the value. They meet the ESR requirements at 1.0
F as long as the temperature is above 0C. Below 0C, the ESR increases and it may exceed the limits indicated
in the fgures.
0.01
0.1
1
10
100
1000
10000
0 0 1 0 1 1
20 BIT
18 BIT
16 BIT
14 BIT
12 BIT
10 BIT
8 BIT
R
e
f
e
r
e
n
c
e

T
C

(
p
p
m
/
C
)
VRE4100
112 VRE4100DS
ultilayer ceramic capacitors have a small size for the value, are available in surface mount, and have excellent RF
characteristics. They may not meet the minimum ESR requirements and have a large change in value with tem-
perature.
REVERSE CURRENT PATH
The P-channel pass transistor used in this series has an inherent diode connected between the Vin and VOUT pins.
Forcing the output to voltages higher than the input or pulling Vin below the voltage stored in the output capacitor
by more than the Vbe will forward bias this diode and current will fow from the Vout pin to Vin. This will not damage
the device as long as the current does not exceed 50 mA.
ON/OFF OPERATION
This series features a sleep mode that is activated by pulling the enable pin low. To turn the reference on, the en-
able pin is pulled high. If this feature is not used, the enable pin should be tied to Vin to keep the reference on at all
times. The enable pin must not be left unconnected (foating).
When powered off, these devices will quickly reduce both Vout and IQ to zero. During power down, the charge
across the output capacitor is discharged to ground through the internal circuitry. On power up, the Vout is restored
in less than 200 s.
The signal source used to drive the enable pin can come from either a totem-pole output or an open collector output
with a pull-up resistor to the input voltage. The signal source must be able to swing above and below the voltage
thresholds to guarantee an ON or OFF state. It must not exceed the absolute maximum rating for the enable pin.
OUTPUT ACCURACY
The output accuracy after assembly at room temperature is made up of three components: initial accuracy of the de-
vice, thermal hysteresis, and mechanical stress. The initial accuracy is measured at the factory and may not refect
the actual output voltage when the devices are mounted to a PCB. The effects of mechanical stress and thermal
hysteresis can shift the output voltage.
THERMAL HYSTERESIS
Thermal hysteresis is a change in output voltage as a result of a temperature change. When references experience
a temperature change and return to the initial temperature, they do not always have the same initial voltage. Ther-
mal hysteresis is diffcult to correct and is a major error source in systems that experience temperature changes
greater than 25C. Reference vendors are starting to include this important specifcation in their datasheets
MECHANICAL HYSTERESIS
Recommendations to minimize mechanical stress:
1) Mount the VRE4112/VRE4125/VRE4141 near the edges or corners of the PCB. The center of the board generally
has the highest mechanical and thermal stress.
2) Mechanically isolate the device by cutting a U shaped slot around the package. This provides some mechanical
and thermal isolation from the rest of the circuit.
PIN CONFIGURATION
5
6
7
8
VRE4100
TOP
VIEW
1
2
3
4
NC
+V
IN
Enable
GND
NC
V
REF
NC
NC
113
NOTES: ___________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
114
NOTES: ___________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
PWM 115
PWM Ampliers
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Product Selector Matrix - PWM ...........................................................116
MSA240 ...............................................................................................117
MSA260 ...............................................................................................121
SA01 SA01-6 ....................................................................................128
SA03 ....................................................................................................132
SA08 ....................................................................................................136
SA09 ....................................................................................................140
SA12 ....................................................................................................146
SA50CE ...............................................................................................150
SA53 ....................................................................................................154
SA57 SA57A .....................................................................................166
SA60 ....................................................................................................178
SA303 ..................................................................................................183
SA306 SA306A .................................................................................196
PWM Ampliers PWM Ampliers
116 PWM
PWM Ampliers
Product Selector Matrix - PWM
PRODUCT SELECTOR MATRIX - PWM (SWITCHING)
10
4
5
8
50
40
30
20
15
6
7
9
3
2
40 50 60 700 70 80 90 100 200 300 450 600 900
O
u
t
p
u
t

C
u
r
r
e
n
t
Supply Voltage
40 50 60 700 70 80 90 100 200 300 350 450 600 900
MSA240
MSA260 SA08
SA60
SA01
SA09
SA50
SA03
SA12
SA57
SA306
SA57A
SA306A
SA53
SA303
Switching Open Frame
Switching
MSA240
MSA240U 117
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
MSA240
Pulse Width Modulation Amplifiers
MSA240 P r o d u c t I n n o v a t i o n F r o m
FEATURES
LOW COST
HIGH VOLTAGE - 100 VOLTS
HIGH OUTPUT CURRENT - 20 AMPS
2kW OUTPUT CAPABILITY
VARIABLE SWITCHING FREQUENCY
APPLICATIONS
BRUSH MOTOR CONTROL
MRI
MAGNETIC BEARINGS
CLASS D SWITCHMODE AMPLIFIER
DESCRIPTION
The MSA240 is a surface mount constructed PWM amplifer
that provides a cost effective solution in many industrial applica-
tions. The MSA240 offers outstanding performance that rivals
many much more expensive hybrid components. The MSA240
is a complete PWM amplifer including an oscillator, comparator,
error amplifer, current limit comparators, 5V reference, a smart
controller and a full bridge output circuit. The switching frequency
is user programmable up to 50 kHz. The MSA240 is built on a
thermally conductive but electrically insulating substrate that
can be mounted to a heatsink.
EQUIVALENT CIRCUIT DIAGRAM
58-PIN DIP
PACKAGE STYLE KC
TYPICAL APPLICATION
TORQUE MOTOR CONTROL
With the addition of a few external components the MSA240
becomes a motor torque controller. In the MSA240 the source
terminal of each low side MOSFET driver is brought out for
current sensing via R
S
A and R
S
B. A1 is a differential amplifer
that amplifes the difference in currents of the two half bridges.
This signal is fed into the internal error amplifer that mixes the
current signal and the control signal. The result is an input
signal to the MSA240 that controls the torque on the motor.
49-53
A OUT
35-39
B OUT
Is B Is A
Rs B
Rs A
40-43 54-57
CONTROL
SIGNAL
15
2,18,26
DIG
RET
PWR
GND
58
ROSC
A1
PWM AMPLIFIER
+5V REF OUT
CLK OUT
17
22
24
20
1
RRAMP IN
CLK/2 OUT
ROSC
RRAMP
E/A OUT
16
2.5V
E/A -IN
E/A +IN
19
SINGLE POINT GND @ 26
+IN
13
2.5V
SIG
GND
AC
BACK
PLATE
28 23
C2 IS ELECTROLYTIC 10UF PER AMP OUTPUT CURRENT
C1,3 HIGH QUALITY CERAMIC 1.0UF
ALL +Vs MUST BE TIED TOGETHER
ALL SIG GND PINS MUST BE TIED TOGETHER
SINGLE POINT GROUND @ PIN 26
VIEW FROM
COMPONENT SIDE
R
OSC
R
RAMP
+
SINGLE
POINT
GND
C3 C1 C2
NOTES:
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
5 10 9 8 7 6 15 14 13 12 11 20 19 18 17 16 25 24 23 22 21 26 27 28 2 1
VCC
4 3
+Vs A OUT I
SENSE
A +Vs B OUT I
SENSE
B PWR
GND
D
I
G

R
T
N
I
L
IM

B
I
L
IM

A
/
S
H
D
N
+
I
N
E
A

-
I
N
E
A

+
I
N
E
A

O
U
T
R
O
S
C
C
L
K

O
U
T
C
L
K
/
2

O
U
T
C
L
K

I
N
S
I
G

G
N
D
N
C
N
C
N
C
N
C
N
C
N
C
N
C
S
I
G

G
N
D
R
R
A
M
P

I
N
33
N
C
N
C
32 30 29 31
+
5
V

O
U
T
A
C

B
A
C
K
P
L
A
T
E
A
P
E
X

T
P
S
I
G

G
N
D
N
C
55 56 58 57
GND
+IN
A OUT
I SENSE B
+Vs
I SENSE A
35-39
54-57
40-43
58
1
13
5V
SIGNAL
R3
R2
29 VCC
PWR
+Vs
44-48
49-53
B OUT
SMART
CONTROLLER
GND
-
+
-
+
-
+
200mV
REF
5V REF
19
OUT
RRAMP IN
20 CLK/2 OUT
21 CLK IN
OSC
CLK OUT 24
ROSC 22
7 ILIM B
10 ILIM A/SHDN
CLK/2
-
+
17
16
15
E/A OUT
E/A -IN
E/A +IN
30-34
SIGNAL
GND
26
SIGNAL
GND
18
2
27 APEX TP
DIGITAL
RETURN
23
2200pF
2200pF
1K
1K
.01F
.01F
2.68K
28
AC BACK
PLATE
1F
BACK PLATE
Q1
D2
D1
Q4
Q3
Q2
5.36K
MAY 2009
APEX MSA240UREVD
MSA240
118 MSA240U
SPECIFICATIONS
PARAMETER TEST CONDITIONS
1
MIN TYP MAX UNITS
ERROR AMPLIFIER
OFFSET VOLTAGE Full temperature range 9 mV
BIAS CURRENT Full temperature range 500 nA
OFFSET CURRENT Full temperature range 150 nA
COMMON MODE VOLTAGE RANGE Full temperature range 0 4 V
SLEW RATE Full temperature range 1 V/S
OPEN LOOP GAIN R
L
= 2K 96 dB
UNITY GAIN BANDWIDTH 1 MHz
CLOCK
LOW LEVEL OUTPUT VOLTAGE Full temperature range .2 V
HIGH LEVEL OUTPUT VOLTAGE Full temperature range 4.8 V
RISE TIME 7 nS
FALL TIME 7 nS
BIAS CURRENT, pin 22 Full temperature range 0.6 A
5V REFERENCE OUTPUT
VOLTAGE 4.85 5.15 V
LOAD CURRENT 2 mA
OUTPUT
TOTAL R
ON
, both MOSFETs
4
I
O
= 20A , T
J
= 85C 155 m
CURRENT, continuous 20 A
CURRENT, peak 100mS 30 A
OUTPUT MOSFET BODY DIODE
CONTINUOUS CURRENT 20 A
FORWARD VOLTAGE I = 16A 1.3 V
REVERSE RECOVERY I
F
= 16A 250 nS
POWER SUPPLY
VOLTAGE, V
S
3 60 100 V
VOLTAGE, V
CC
14 15 16 V
CURRENT, V
S
, quiescent 22kHz switching 4 28 mA
CURRENT, V
CC
, quiescent 22kHz switching 18 mA
CURRENT, V
CC
, shutdown 10 mA
THERMAL
RESISTANCE, DC, junction to case Full temperature range 1.2 C/W
RESISTANCE, junction to air Full temperature range 14 C/W
TEMPERATURE RANGE, case -40 85 C/W
SUPPLY VOLTAGE, VS 100V
SUPPLY VOLTAGE, VCC 16V
OUTPUT CURRENT, peak 30A, within SOA
POWER DISSIPATION, internal, DC 250W
3
SIGNAL INPUT VOLTAGES 5.4V
TEMPERATURE, pin solder, 10s 225C.
TEMPERATURE, junction
2
175C.
TEMPERATURE RANGE, storage -40 to 105C.
OPERATING TEMPERATURE, case -40 to 85C.
NOTES: 1. Unless otherwise noted: T
C
=25C, V
CC
= 15V, V
S
= 60V
2. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation
to achieve high MTBF.
3. Each of the two output transistors on at any one time can dissipate 125W.
4. Maximum specifcation guaranteed but not tested.
MSA240
MSA240U 119
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
0 20 40 60 80 100
0
25
50
75
100
125
POWER DERATING
CASE TEMPERATURE, (C)
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

(
W
)
97
98
99
100
FREQUENCY = 44KHz
10K 100K 1M
N
O
R
M
A
L
I
Z
E
D

F
R
E
Q
U
E
N
C
Y
,

(
%
)
CLOCK LOAD RESISTANCE, ()
CLOCK LOADING
-40 -20 0 20 40 60 80 100
99.2
99.4
99.6
99.8
100.0
100.2
N
O
R
M
A
L
I
Z
E
D

F
R
E
Q
U
E
N
C
Y
,

(
%
)
CLOCK FREQUENCY OVER TEMP.
0.4 0.6 0.8 1.0 1.2
0
4
8
12
16
20
SOURCE TO DRAIN DIODE VOLTAGE
F
L
Y
B
A
C
K

C
U
R
R
E
N
T
,

I
S
D

(
A
)
REVERSE DIODE
T
J

=

1
2
5
C
T
J

=

2
5
C
0 4 8 12 16 20
0
1
2
3
4
5
OUTPUT CURRENT, (A)
T
O
T
A
L

V
O
L
T
A
G
E

D
R
O
P
,

(
V
)
TOTAL VOLTAGE DROP
T
C

=

8
5
C
TC

=

2
5
C
0 25 50 75 100
0
5
10
15
20
25
CONTINUOUS OUTPUT
C
O
N
T
I
N
U
O
U
S

A
M
P
S
1.5 2.0 2.5 3.0 3.5
0
20
40
60
80
100
DUTY CYCLE VS. ANALOG INPUT
D
U
T
Y

C
Y
C
L
E
,

(
%
)
ANALOG INPUT, (V)
A OUT
B OUT
0 10 20 30 40 50
4
8
12
16
20
24
V
CC
QUIESCENT CURRENT
V
C
C

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
m
A
)
SWITCHING FREQUENCY, F (kHz)
50% DUTY CYCLE
-40 -20 0 20 40 60 80 100
97
98
99
100
101
102
V
CC
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)
NORMAL or SHUTDOWN
OPERATION
0 20 40 60 80 100
1
2
3
4
5
V
S
QUIESCENT CURRENT
V
S
, (V)
F = 22kHz,
50% DUTY CYCLE
V
S

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
m
A
)
0 10 20 30 40 50
0
2
4
6
8
V
S
QUIESCENT CURRENT vs. FREQUENCY
V
S

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
m
A
)
V
S
= 60V,
50% DUTY CYCLE
MSA240
120 MSA240U
GENERAL
Please read Application Note 30 PWM Basics. Refer also
to Application Note 1 General Operating Considerations for
helpful information regarding power supplies, heat sinking,
mounting, SOA interpretation, and specifcation interpretation.
Visit www.Cirrus.com for design tools that help automate tasks
such as calculations for stability, internal power dissipation,
current limit, heat sink selection, Apex Precision Powers com-
plete Application Notes library, Technical Seminar Workbook
and Evaluation Kits.
OSCILLATOR
The MSA240 includes a user frequency programmable
oscillator. The oscillator determines the switching frequency
of the amplifer. The switching frequency of the amplifer is 1/2
the oscillator frequency. Two resistor values must be chosen
to properly program the switching frequency of the amplifer.
One resistor, R
OSC
, sets the oscillator frequency. The other
resistor, R
RAMP
, sets the internal ramp amplitude. In all cases
the ramp voltage will oscillate between 1.5V and 3.5V. See
Figure 1. If an external oscillator is applied use the equations
to calculate R
RAMP
.
To program the oscillator, R
OSC
is given by:
R
OSC
= (1.32X10
8
/ F) - 2680
where F is the desired switching frequency and:
R
RAMP
= 2 X R
OSC
Use 1% resistors with 100ppm drift (RN55C type resistors,
for example). Maximum switching frequency is 50kHz.
Example:
If the desired switching frequency is 22kHz then R
OSC
= 3.32K
and R
RAMP
= 6.64K. Choose the closest standard 1% values:
R
OSC
= 3.32K and R
RAMP
= 6.65K.
FIGURE 1. EXTERNAL OSCILLATOR CONNECTIONS
SHUTDOWN
The MSA240 output stage can be turned off with a shutdown
command voltage applied to Pin 10 as shown in Figure 2. The
shutdown signal is ORed with the current limit signal and
simply overrides it. As long as the shutdown signal remains
high the output will be off.
CURRENT SENSING
The low side drive transistors of the MSA240 are brought
out for sensing the current in each half bridge. A resistor from
each sense line to PWR GND (pin 58) develops the current
sense voltage. Choose R and C such that the time constant
is equal to 10 periods of the selected switching frequency. The
internal current limit comparators trip at 200mV. Therefore,
current limit occurs at I = 0.2/R
SENSE
for each half bridge. See
Figure 2. Accurate milliohm power resistors are required and
there are several sources for these listed in the Accessories
Vendors section of the Databook.
FIGURE 2. CURRENT LIMIT WITH OPTIONAL SHUTDOWN
POWER SUPPLY BYPASSING
Bypass capacitors to power supply terminals +V
S
must be
connected physically close to the pins to prevent local parasitic
oscillation and overshoot. All +V
S
pins must be connected
together. Place an electrolytic capacitor of at least 10F per
output amp required midpoint between these sets of pins. In
addition place a ceramic capacitor 1F or greater directly at
each set of pins for high frequency bypassing. V
CC
is bypassed
internally.
GROUNDING AND PCB LAYOUT
Switching amplifers combine millivolt level analog signals
and large amplitude switching voltages and currents with fast
rise times. As such grounding is crucial. Use a single point
ground at SIG GND (pin 26). Connect signal ground pins 2 and
18 directly to the single point ground on pin 26. Connect the
digital return pin 23 directly to pin 26 as well. Connect PWR
GND pin 58 also to pin 26. Connect AC BACKPLATE pin 28
also to the single point ground at pin 26. Connect the ground
terminal of the V
CC
supply directly to pin 26 as well. Make sure
no current from the load return to PWR GND fows in the analog
signal ground. Make sure that the power portion of the PCB
layout does not pass over low-level analog signal traces on
the opposite side of the PCB. Capacitive coupling through the
PCB may inject switching voltages into the analog signal path.
Further, make sure that the power side of the PCB layout does
not come close to the analog signal side. Fast rising output
signal can couple through the trace-to-trace capacitance on
the same side of the PCB.
DETERMINING THE OUTPUT STATE
The input signal is applied to +IN (Pin 13) and varies from
1.5 to 3.5 volts, zero to full scale. As +IN varies from 1.5 to 2.5
volts the A output "high" duty cycle (relative to ground) is greater
than the B output "high" duty cycle. The reverse occurs as the
input signal varies from 2.5 to 3.5 volts. When +IN = 2.5 volts
the duty cycles of both A and B outputs are 50%. Consequently,
when the input voltage is 1.5V the A output is close to 100%
duty cycle and the B output is close to 0% duty cycle. The
reverse occurs with an input voltage of 3.5V. The output duty
cycle extremes vary somewhat with switching frequency and
are internally limited to approximately 5% to 95% at 10kHz and
7% to 93% at 50kHz.
I
s
e
n
s
e

A
I
s
e
n
s
e

B
Rs A Rs B
40-43 54-57
PWR
GND
58
PWM AMPLIFIER
R
R
I
l
i
m
A
/
S
H
D
N
I
l
i
m
B
7 10
C
C
9R
5V SHDN
SIGNAL
24 20
T
U
O

K
L
C
T
U
O

2
/
K
L
C
1
R
C
S
O
22
PWM AMPLIFIER
R
OSC
21
N
I

K
L
C
R
P
M
A
R
N
I

R
RAMP
MSA260
MSA260U 121
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
MSA260
A OUT
I SENSE B
+Vs
I SENSE A
35-39
54-57
40-43
+Vs
44-48
49-53
B OUT
SMART
CONTROLLER
-
+
30-34
GND
+IN
58
1
13
5V
SIGNAL
R3
R2
29
V
CC
PWR
GND
-
+
-
+
200mV
REF
5V REF
19
OUT
R
RAMP
IN
20 CLK/2 OUT
21 CLK IN
OSC
CLK OUT
24
R
OSC 22
7 I
LIM
B
10
I
LIM
A/
SHDN
CLK/2
-
+
17
16
15
E/A OUT
E/A -IN
E/A +IN
SIGNAL
GND
26
18
2
27 APEX TP
23
2200pF
2200pF
1K
1K
.01F
.01F
2.68K
28
AC BACK
PLATE
1F
BACK PLATE
SIGNAL
GND
DIGITAL
RETURN
5.36K
Q1
Q4
Q3
Q2
GENERAL DESCRIPTION
The MSA260 is a surface mount constructed PWM
amplifer that provides a cost effective solution in many
industrial applications. The MSA260 offers outstand-
ing performance that rivals many much more expen-
sive hybrid components. The MSA260 is a complete
PWM amplifer including an oscillator, comparator, er-
ror amplifer, current limit comparators, 5V reference,
a smart controller and a full bridge IGBT output circuit.
The switching frequency is user programmable up to
50 kHz. The MSA260 is built on a thermally conductive
but electrically insulating substrate that can be mount-
ed to a heatsink.
FEATURES
LOW COST
9kW OUTPUT CAPABILITY
VARIABLE SWITCHING FREQUENCY
IGBT FULL BRIDGE OUTPUT
APPLICATIONS
BRUSH MOTOR CONTROL
MRI
MAGNETIC BEARINGS
Pulse Width Modulation Amplifier
MSA260 P r o d u c t I n n o v a t i o n F r o m
NOV 2008
APEX MSA260UREVC
MSA260
122 MSA260U
Parameter Symbol Min Max Units
SUPPLY VOLTAGE V
S
450 V
SUPPLY VOLTAGE V
CC
16 V
OUTPUT CURRENT, peak, within SOA 30 A
POWER DISSIPATION, internal, DC (Note 3) 250 W
SIGNAL INPUT VOLTAGES 5.4 V
TEMPERATURE, pin solder, 10s 225 C
TEMPERATURE, junction (Note 2) 150 C
TEMPERATURE RANGE, storage 40 105 C
OPERATING TEMPERATURE, case 40 85 C
CHARACTERISTICS AND SPECIFICATIONS
Parameter Test Conditions (Note 1) Min Typ Max Units
ERROR AMPLIFIER
OFFSET VOLTAGE Full temperature range 9 mV
BIAS CURRENT, initial (Note 3) Full temperature range 500 nA
OFFSET CURRENT, initial Full temperature range 150 nA
COMMON MODE VOLTAGE RANGE, pos. Full temperature range 0 4 V
SLEW RATE Full temperature range 1 V/s
OPEN LOOP GAIN R
L
= 2K 96 dB
UNITY GAIN BANDWIDTH 1 MHz
CLOCK
LOW LEVEL OUTPUT VOLTAGE Full temperature range 0.2 V
HIGH LEVEL OUTPUT VOLTAGE Full temperature range 4.8 V
RISE TIME 7 nS
FALL TIME 7 nS
BIAS CURRENT, pin 22 Full temperature range 0.6 A
5V REFERENCE OUTPUT
VOLTAGE 4.85 5.15 V
LOAD CURRENT 2 mA
OUTPUT (Note 4)
V
CE(ON)
, each active IGBT I
CE
= 15A 2.25 V
CURRENT, continuous V
S
= 400V, F = 22kHz 20 A
CURRENT, peak 1mS, V
S
= 400V, F = 22kHz 30 A
FLYBACK DIODE
CONTINUOUS CURRENT 44 20 A
FORWARD VOLTAGE I
F
= 15A 200 1.5 V
REVERSE RECOVERY I
F
= 15A 0.2 0.7 150 nS
SPECIFICATIONS
MSA260
MSA260U 123
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
NOTES:
1. Unless otherwise noted: T
C
=25C, V
CC
= 15V, V
S
= 400V, F = 22kHz.
2. Long term operation at the maximum junction temperature will result in reduced product life. Derate
internal power dissipation to achieve high MTBF.
3. Each of the two output transistors on at any one time can dissipate 125W.
4. Maximum specifcation guaranteed but not tested.
POWER SUPPLY
VOLTAGE, V
S
5 400 450 V
VOLTAGE, V
CC
14 15 16 V
CURRENT, V
S
, quiescent 22kHz switching 9 28 mA
CURRENT, V
CC
, quiescent 22kHz switching 18 mA
CURRENT, V
CC
, shutdown 10 mA
THERMAL
RESISTANCE, DC, junction to case Full temperature range 1 C/W
TEMPERATURE RANGE, case -40 85 C
0 20 40 60 80 100
0
25
50
75
100
125
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

(
W
)

97
98
99
100
FREQUENCY = 44KHz
10K 100K 1M
N
O
R
M
A
L
I
Z
E
D

F
R
E
Q
U
E
N
C
Y
,

(
%
)

CLOCK LOADING
-40 -20 0 20 40 60 80 100
99.2
99.4
99.6
99.8
100.0
100.2
N
O
R
M
A
L
I
Z
E
D

F
R
E
Q
U
E
N
C
Y
,

(
%
)

0.4 0.6 0.8 1.0
0
4
8
12
16
20
F
L
Y
B
A
C
K

C
U
R
R
E
N
T
,

I
S
D

(
A
)

REVERSE DIODE
T
J

=

1
2
5
C

T
J

=

2
5
C

0 4 8 12 16 20
1
2
3
4
5
OUTPUT CURRENT, (A)
T
O
T
A
L

V
O
L
T
A
G
E

D
R
O
P
,

(
V
)

TOTAL VOLTAGE DROP
0 25 50 75 100
0
5
10
15
20
25
CONTINUOUS OUTPUT
C
O
N
T
I
N
U
O
U
S

A
M
P
S

1.5 2.0 2.5 3.0 3.5
0
20
40
60
80
100
D
U
T
Y

C
Y
C
L
E
,

(
%
)

ANALOG INPUT, (V)
A OUT
B OUT
0 10 20 30 40 50
4
8
12
16
20
24
V
CC
QUIESCENT CURRENT
V
C
C

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
m
A
)

50% DUTY CYCLE
-40 -20 0 20 40 60 80 100
97
98
99
100
101
102
V
CC
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)

NORMAL or SHUTDOWN
OPERATION
0 100 200 300 400 500
2
4
6
8
10
V
S
QUIESCENT CURRENT
V
S
, (V)
F = 22kHz,
50% DUTY CYCLE
V
S

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
m
A
)

0 10 20 30 40 50
0
8
12
24
V
S
V
S

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
m
A
)

V
S
= 400V,
50% DUTY CYCLE
4
16
20
T
C

=

8
5
C

TC

=

2
5
C

EACH ACTIVE
COMPONENT
MSA260
124 MSA260U
0 20 40 60 80 100
0
25
50
75
100
125
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

(
W
)

97
98
99
100
FREQUENCY = 44KHz
10K 100K 1M
N
O
R
M
A
L
I
Z
E
D

F
R
E
Q
U
E
N
C
Y
,

(
%
)

CLOCK LOADING
-40 -20 0 20 40 60 80 100
99.2
99.4
99.6
99.8
100.0
100.2
N
O
R
M
A
L
I
Z
E
D

F
R
E
Q
U
E
N
C
Y
,

(
%
)

0.4 0.6 0.8 1.0
0
4
8
12
16
20
F
L
Y
B
A
C
K

C
U
R
R
E
N
T
,

I
S
D

(
A
)

REVERSE DIODE
T
J

=

1
2
5
C

T
J

=

2
5
C

0 4 8 12 16 20
1
2
3
4
5
OUTPUT CURRENT, (A)
T
O
T
A
L

V
O
L
T
A
G
E

D
R
O
P
,

(
V
)

TOTAL VOLTAGE DROP
0 25 50 75 100
0
5
10
15
20
25
CONTINUOUS OUTPUT
C
O
N
T
I
N
U
O
U
S

A
M
P
S

1.5 2.0 2.5 3.0 3.5
0
20
40
60
80
100
D
U
T
Y

C
Y
C
L
E
,

(
%
)

ANALOG INPUT, (V)
A OUT
B OUT
0 10 20 30 40 50
4
8
12
16
20
24
V
CC
QUIESCENT CURRENT
V
C
C

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
m
A
)

50% DUTY CYCLE
-40 -20 0 20 40 60 80 100
97
98
99
100
101
102
V
CC
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)

NORMAL or SHUTDOWN
OPERATION
0 100 200 300 400 500
2
4
6
8
10
V
S
QUIESCENT CURRENT
V
S
, (V)
F = 22kHz,
50% DUTY CYCLE
V
S

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
m
A
)

0 10 20 30 40 50
0
8
12
24
V
S
V
S

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
m
A
)

V
S
= 400V,
50% DUTY CYCLE
4
16
20
T
C

=

8
5
C

TC

=

2
5
C

EACH ACTIVE
COMPONENT
C2 IS ELECTROLYTIC 10UF PER AMP OUTPUT CURRENT
C1,3 HIGH QUALITY CERAMIC 1.0UF
ALL +Vs MUST BE TIED TOGETHER
ALL SIG GND PINS MUST BE TIED TOGETHER
SINGLE POINT GROUND @ PIN 26
VIEW FROM
COMPONENT SIDE
R
OSC
R
RAMP
+
SINGLE
POINT
GND
C3 C1 C2
NOTES:
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
5 10 9 8 7 6 15 14 13 12 11 20 19 18 17 16 25 24 23 22 21 26 27 28 2 1
V
CC
4 3
+Vs A OUT I
SENSE
A +Vs B OUT I
SENSE
B PWR
GND
D
I
G

R
T
N
I
L
I
M

B
I
L
I
M

A
/
S
H
D
N
+
I
N
E
A

-
I
N
E
A

+
I
N
E
A

O
U
T
R
O
S
C
C
L
K

O
U
T
C
L
K
/
2

O
U
T
C
L
K

I
N
S
I
G

G
N
D
N
C
N
C
N
C
N
C
N
C
N
C
N
C
S
I
G

G
N
D
R
R
A
M
P

I
N
33
N
C
N
C
32 30 29 31
+
5
V

O
U
T
A
C

B
A
C
K
P
L
A
T
E
A
P
E
X

T
P
S
I
G

G
N
D
N
C
55 56 58 57
MSA260
MSA260U 125
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
TYPICAL APPLICATION
TORQUE MOTOR CONTROL
With the addition of a few exter-
nal components the MSA260 be-
comes a motor torque controller.
In the MSA260 the source termi-
nal of each low side IGBT driver
is brought out for current sensing
via R
S
A and R
S
B. A1 is a differen-
tial amplifer that amplifes the dif-
ference in currents of the two half
bridges. This signal is fed into the
internal error amplifer that mixes
the current signal and the control
signal. The result is an input sig-
nal to the MSA260 that controls
the torque on the motor.
GENERAL
Please read Application Note 30 PWM Basics. Refer also to Application Note 1 General Operating Consider-
ations for helpful information regarding power supplies, heat sinking, mounting, SOA interpretation, and specifca-
tion interpretation. Visit www.cirrus.com for design tools that help automate tasks such as calculations for stability,
internal power dissipation, current limit, heat sink selection, Apex Precision Powers complete Application Notes
library, Technical Seminar Workbook and Evaluation Kits.
49-53
A OUT
35-39
B OUT
Is B Is A
Rs B
Rs A
40-43 54-57
CONTROL
SIGNAL
15
2,18,26
DIG
RET
PWR
GND
58
R
OSC
A1
PWM AMPLIFIER
+5V REF OUT
CLK OUT
17
22
24
20
1
R
RAMP
IN
CLK/2 OUT
R
OSC
R
RAMP
E/A OUT
16
2.5V
E/A -IN
E/A +IN
19
SINGLE POINT GND @ 26
+IN
13
2.5V
SIG
GND
AC
BACK
PLATE
28 23
58-pin DIP
PACKAGE STYLE KC
MSA260
126 MSA260U
OSCILLATOR
The MSA260 includes a user frequency programmable oscillator. The oscillator determines the switching frequency
of the amplifer. The switching frequency of the amplifer is 1/2 the oscillator frequency. Two resistor values must
be chosen to properly program the switching frequency of the amplifer. One resistor, R
OSC
, sets the oscillator fre-
quency. The other resistor, R
RAMP
, sets the ramp amplitude. In all cases the ramp voltage will oscillate between 1.5V
and 3.5V. See Figure 1. If an external oscillator is applied use the equations to calculate R
RAMP
.
To program the oscillator, R
OSC
is given by:
R
OSC
= (1.32X10
8
/ F) - 2680
where F is the desired switching frequency and:
R
RAMP
= 2 X R
OSC
Use 1% resistors with 100ppm drift (RN55C type resistors,
for example). Maximum switching frequency is 50kHz.
Example:
If the desired switching frequency is 22kHz then R
OSC
=
3.32K and R
RAMP
= 6.64K. Choose the closest standard 1%
values: R
OSC
= 3.32K and R
RAMP
= 6.65K or simply use two
of selected R
OSC
in series for R
RAMP
.
SHUTDOWN
The MSA260 output stage can be turned off with a shutdown command volt-
age applied to Pin 10 as shown in Figure 2. The shutdown signal is ORed
with the current limit signal and simply overrides it. As long as the shutdown
signal remains high the output will be off.
CURRENT SENSING
The low side drive transistors of the MSA260 are brought out for sensing the
current in each half bridge. A resistor from each sense line to PWR GND (pin
58) develops the current sense voltage. Choose R and C such that the time
constant is equal to 10 periods of the selected switching frequency. The in-
ternal current limit comparators trip at 200mV. Therefore, current limit occurs
at I = 0.2/R
SENSE
for each half bridge. See Figure 2. Accurate milliohm power resistors are required and there are
several sources for these listed in the Accessories Vendors section of the Databook.
S
must be connected physically close to the pins to prevent local
parasitic oscillation and overshoot. All +V
S
must be connected together. Place and electrolytic capacitor of at least
10F per output amp required midpoint between these sets of pins. In addition place a ceramic capacitor 1.0F or
greater directly at each set of pins for high frequency bypassing. V
CC
is bypassed internally.
GROUNDING AND PCB LAYOUT
Switching amplifers combine millivolt level analog signals and large amplitude switching voltages and currents with
fast rise times. As such grounding is crucial. Use a single point ground at SIG GND (pin 26). Connect signal ground
pins 2 and 18 directly to the single point ground on pin 26. Connect the digital return pin 23 directly to pin 26 as well.
Connect PWR GND pin 58 also to pin 26. Connect AC BACKPLATE pin 28 also to the single point ground at pin 26.
Connect the ground terminal of the V
CC
supply directly to pin 26 as well. Make sure no current from the load return
to PWR GND fows in the analog signal ground. Make sure that the power portion of the PCB layout does not pass
over low-level analog signal traces on the opposite side of the PCB. Capacitive coupling through the PCB may inject
switching voltages into the analog signal path. Further, make sure that the power side of the PCB layout does not
come close to the analog signal side. Fast rising output signal can couple through the trace-to-trace capacitance on
the same side of the PCB.
I
s
e
n
s
e

A
I
s
e
n
s
e

B
Rs A Rs B
40-43 54-57
PWR
GND
58
PWM AMPLIFIER
R
R
I
l
i
m
A
/
S
H
D
N
I
l
i
m
B
7 10
C
C
9R
5V SHDN
SIGNAL
24 20
T
U
O

K
L
C
T
U
O

2
/
K
L
C
1
R
C
S
O
22
PWM AMPLIFIER
R
OSC
21
N
I

K
L
C
R
P
M
A
R
N
I

R
RAMP
FIGURE 1. EXTERNAL OSCILLATOR CONNECTIONS
FIGURE 2. CURRENT LIMIT WITH
OPTIONAL SHUTDOWN
MSA260
MSA260U 127
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
DETERMINING THE OUTPUT STATE
The input signal is applied to +IN (Pin 13) and varies from 1.5 to 3.5 volts, zero to full scale. The ramp also varies
over the same range. When:
Ramp > +IN A
OUT
> B
OUT
The output duty cycle extremes vary somewhat with switching frequency and are internally limited to approximately
5% to 95% at 10kHz and 7% to 93% at 50kHz.
CALCULATING INTERNAL POWER DISSIPATION
Detailed calculation of internal power dissipation is complex but can be approximated with simple equations. Con-
duction loss is given by:
W = I 2.5 + I
2
0.095
where I = output current
Switching loss is given by:
W = 0.00046 I Vsupply Fswitching (in kHz)
Combine these two losses to obtain total loss. Calculate heatsink ratings and case temperatures as would be done
for a linear amplifer. For calculation of junction temperatures, assume half the loss is dissipated in each of two
switches:
Tj = Ta + Wtotal Rhs + 1/2Wtotal Rjc, where:
Rhs = heatsink rating
Rjc = junction-to-case thermal resistance of the MSA260.
The SOA typical performance graphs below show performance with the MSA260 mounted with thermal grease on
the Apex Precision Power HS26. The Free Air graph assumes vertical orientation of the heatsink and no obstruction
to air fow in an ambient temperature of 30C. The other two graphs show performance with two levels of forced air.
Note that air velocity is given in linear feet per minute. As fans are rated in cubic delivery capability, divide the cubic
rating by the square area this air fows through to fnd velocity. As fan delivery varies with static pressure, these
calculations are approximations, and heatsink ratings vary with amount of power dissipated, there is no substitute
for temperature measurements on the heatsink in the center of the amplifer footprint as a fnal check.
SOA, HS26, FREE AIR
7
10
13
16
19
5 10 15 20 25 30 35 40 45 50
SWITCHING FREQUENCY, KHz
O
U
T
P
U
T

C
U
R
R
E
N
T
,

A
V
s
=
1
5
0
V
s
=
2
5
0
V
s
=
3
5
0
V
s
=
4
5
0
SOA, HS26, 150LFM FORCED AIR
10
12
16
18
5 10 15 20 25 30 35 40 45 50
O
U
T
P
U
T

C
U
R
R
E
N
T
,

A
Vs=150
Vs=250
Vs=350
Vs=450
14
20
SOA, HS26, 500LFM FORCED AIR
12
13
14
15
16
17
18
19
20
15 20 25 30 35 40 45 50
O
U
T
P
U
T

C
U
R
R
E
N
T
,

A
Vs=250
Vs=350
Vs=450
SA01 SA01-6
128 SA01U
SA01 SA01-6
FEATURES
SINGLE SUPPLY OPERATION
WIDE SUPPLY RANGE 16-100V
20A CONTINUOUS OUTPUT
PROGRAMMABLE CURRENT LIMIT
SHUTDOWN CONTROL
HERMETIC PACKAGE
2 IN
2
FOOTPRINT
APPLICATIONS
BRUSH TYPE MOTOR CONTROL
PELTIER CONTROL
REACTIVE LOADS
MAGNETIC COILS (MRI)
ACTIVE MAGNETIC BEARING
VIBRATION CANCELLING
DESCRIPTION
The SA01 amplifer is a pulse width modulation amplifer that
can supply 2KW to the load. The full bridge output amplifer
can be operated from a single power supply over a wide range
of voltages. An error amplifer is included which can provide
gain for the velocity control loop in brush type motor control
applications. Current limit is programmable by a single resistor.
A shutdown input turns off all four drivers of the H bridge output.
A precision reference output is provided for use in offsetting
the error amplifer. The error amplifer can then be scaled for
standard input signals. The amplifer is protected from shorts to
supply or ground. The H bridge output MOSFETs are protected
from thermal overloads by directly sensing the temperature of
the die. The 10-pin hermetic power package occupies only 2
square inches of board space and is isolated.
BLOCK DIAGRAM
TYPICAL APPLICATION
ERROR
AMP
PWM
SUP/
REF
OUTPUT
DRIVERS
CURRENT
LIMIT
AND
SHUTDOWN
CONTROL
3
1
2
4
7
9
6
8
10
+V
S
B OUT
A OUT
I
SENSE
SHDN/
FILTER
5
7.5V REF OUT
EA OUT
IN
+IN
GND
AS EA OUT (3) GOES MORE POSITIVE, HIGH STATE OF A OUT (6)
INCREASES AND HIGH STATE OF B OUT (9) DECREASES.
IN
+IN
EA OUT
GND
REF
SHDN/
FILTER
B OUT
I
SENSE
+V
S
A OUT
1
2
3
4
5
10
9
8
7
6
+
R
LIMIT
=
.2
I
LIMIT
R
LIMIT
R
FILTER
C
FILTER
TOP
VIEW
.1F
C1
EA
PWM
+V
S
EA
OUT
IN
7.5V
REF
+IN
M T
GND
SHDN/
FILTER
I
SENSE
R
LIMIT
R
FILTER
C
FILTER
A
OUT
B
OUT
SA01
1
5
2
3 7
6
9
4 8 10
+V
IN
SHUT
DOWN
C1
.1F
Motor Driver With Tach Feedback
SA01
USA
BeO
TE949311
10-PIN POWER DIP
PACKAGE STYLE DE
SA01 SA01-6 P r o d u c t I n n o v a t i o n F r o m
MAY 2009
APEX SA01UREVI
SA01 SA01-6
SA01U 129
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SUPPLY VOLTAGE, +V
S
100V
OUTPUT CURRENT, peak 30A
POWER DISSIPATION, internal 185W
1
TEMPERATURE, pin solder - 10s 300C
2
150C
TEMPERATURE, storage 65 to +150C
OPERATING TEMPERATURE RANGE, case 55 to +125C
SHUTDOWN VOLTAGE 10V
REFERENCE LOAD CURRENT 10mA
ERROR AMP INPUT 0 to +12V
SPECIFICATIONS
SA01 SA01-6
2
MIN TYP MAX MIN TYP MAX UNITS
ERROR AMP
OFFSET VOLTAGE, initial T
C
= 25C 10 * mV
OFFSET VOLTAGE, vs. temperature Full Temperature Range
5
50 50 V/C
BIAS CURRENT, initial T
C
= 25C 5 * A
BIAS CURRENT, vs. temperature Full Temperature Range
5
400 400 nA/C
OFFSET CURRENT, initial T
C
= 25C 1 * A
OFFSET CURRENT, vs. temperature Full Temperature Range
5
80 80 nA/C
COMMON MODE VOLTAGE RANGE
4
2 8 * * V
COMMON MODE REJECTION, DC
4
75 * dB
SLEW RATE 15 * V/S
OPEN LOOP GAIN
4
75 * dB
GAIN BANDWIDTH PRODUCT 2 * MHz
OUTPUT
TOTAL R
ON
.25 *
EFFICIENCY, 10A OUTPUT V
S
= 100V 97 * %
SWITCHING FREQUENCY Full temperature range
5
35.3 42 48.7 35 42 49 KHz
CURRENT, continuous
4
20 * A
CURRENT, peak
4
30 * A
REFERENCE
VOLTAGE I
REF
= 5mA 7.46 7.50 7.54 * * * V
VOLTAGE VS. TEMP Full temperature range
5
50 50 PPM/C
OUTPUT CURRENT 5 5 mA
LOAD REGULATION
4
20 50 * * PPM/mA
LINE REGULATION 1 * PPM/V
POWER SUPPLY
VOLTAGE Full temperature range
5
16 50 100 16 50 100 V
CURRENT I
OUT
= 0, I
REF
= 0, 76 90 76 93 mA
Full temperature range
5
CURRENT, shutdown I
REF
= 0 25 * mA
SHUTDOWN
TRIP POINT .18 .22 * * V
INPUT CURRENT 100 * nA
THERMAL
2
RESISTANCE, junction to case
4
Full temp range, for each transistor 1.0 * C/W
RESISTANCE, junction to air
4
Full temperature range 12 * C/W
TEMPERATURE RANGE, case Meets full range specifcations
5
25 +85 55 125 C
The SA01 is constructed from MOSFET transistors. ESD handling procedures must be observed.
The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not crush, machine, or
subject to temperatures in excess of 850C to avoid generating toxic fumes.
CAUTION
NOTES: 1. Each of the two active output transistors can dissipate 125W, however the N-channel will be about 1/3 of the total dissipated
power. Internal connection resistance is .05.
C
= 25C.
to achieve high MTTF. For guidance, refer to the heatsink data sheet.
4. Guaranteed but not tested.
5. Full temperature range specifcations apply to the operating case temperature range as specifed under THERMAL. For the
SA01 these specifcations are guaranteed but not tested. For the SA01-6 these specifcations are tested over the SA01-6
operating case temperature range.
SA01 SA01-6
130 SA01U
0.1 0.4 1.0 2.0 6.010.0 40.0
0.02
0.06
0.10
0.40
1.00
2.00
6.00
10.0
BRIDGED OUTPUT SWING
V
O
L
T
A
G
E

D
R
O
P
,

V
S

-

[
A
O
U
T

-

B
O
U
T
]

(
V
)
55 125
98
100
101
NORMALIZED CLOCK DRIFT
99
0
OUTPUT CURRENT, (A)
VOLTAGE DROP
V
O
L
T
A
G
E

D
R
O
P
,

(
V
)
6
7
8
9
15 25 85 2 4 6 8 10 12 14 16 18 20
N
O
R
M
A
L
I
Z
E
D

S
W
I
T
C
H
I
N
G

F
R
E
Q
U
E
N
C
Y
,

(
%
)
0
1
2
3
4
5
BRIDGE DRIVE CURRENT, I
OUT
(A)
CASE TEMPERATURE, T (C)
C
25 125
CASE TEMPERATURE, T
C
(C)
0
20
25
MAXIMUM CONTINUOUS OUTPUT
O
U
T
P
U
T

C
U
R
R
E
N
T

,

(
A
)
5
10
15
1 10 100 10M
80
120
ERROR AMP SMALL SIGNAL GAIN
40
FREQUENCY, F (Hz)
180
ERROR AMP SMALL SIGNAL PHASE
45 65 85 105
55 50 25 0 25 50 75 100 125 125 15 25 85
1K 10K 100K 1M 1 10 100 10M 1K 10K 100K 1M
FREQUENCY, F (Hz)
O
P
E
N

L
O
O
P

G
A
I
N

R
E
S
P
O
N
S
E
,

A

(
d
B
)
135
90
45
0
O
P
E
N

L
O
O
P

P
H
A
S
E
,

)
0
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
0 15
FLYBACK CURRENT, I
SD
(A)
0
FLYBACK DIODES
4
5
FET ON RESISTANCE
O
N

R
E
S
I
S
T
A
N
C
E
,

(
)
POWER DERATING
0
75
125
100
25
50
10 20
1
2
3
0
.05
.1
.15
.2
.25
.3
S
O
U
R
C
E

T
O

D
R
A
I
N

D
I
O
D
E

V
O
L
T
A
G
E
JUNCTION TEMPERATURE, T
J
(C)
50 110 130 70 90 150
75
CASE TEMPERATURE, T (C)
100 0 25 50 125
C
CASE TEMPERATURE, T
C
(C) CASE TEMPERATURE, T
C
(C)
60
70
80
QUIESCENT CURRENT DRIFT
Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
m
A
)
0.9996
0.9998
1.0000
1.0002
1.0004
NORMALIZED REFERENCE DRIFT
2 8
CONTROL, EA OUT (V)
0
DUTY CYCLE
P
E
R
C
E
N
T

H
I
G
H
80
4
40
6 N
O
R
M
A
L
I
Z
E
D

R
E
F
E
R
E
N
C
E
,

V
R
E
F
,

(
X
)
125 C
85C
25C
A
/B
O
U
T
T
O
+
VS
P
-C
H
A
N
N
E
L
P
-C
H
A
N
N
E
L
A

O
U
T
B

O
U
T
N
-C
H
A
N
N
E
L
A/B OUT TO I
SENSE
N-CHANNEL
V
S
= 100V
JUNCTION TEMPERATURE
V
S
= 80V
V
S
= 60V
V
S
= 40V
V
S
= 20V
T
J
= 150C
25C
EACH OUTPUT TRANSISTOR
CASE TEMP. 35C
CASE TEMP. 110C
CASE TEMP. 60C
CASE TEMP. 85C
SA01 SA01-6
SA01U 131
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
Please read Application Note 30 on "PWM Basics". Refer
to Application Note 1 "General Operating Considerations" for
helpful information regarding power supplies, heat sinking
and mounting. Visit www.Cirrus.com for design tools that help
automate pwm flter design; heat sink selection; Apex Precision
Powers complete Application Notes library; Technical Seminar
Workbook; and Evaluation Kits.
CURRENT LIMIT
The current limit function sets a peak limit on current fow in
pin 8 (Isense). This limits load current and also limits current
in the event of a short of either output to +Vs. This circuit can
trip anytime during the conduction period and will hold the
output transistors off for the remainder of that conduction period.
For proper operation the current limit sense resistor must
be connected as shown in the external connection diagram.
It is recommended that the resistor be a non-inductive type.
Load current fows in pin 8. No current fows in pin 10 (Shut-
down/flter) so no error will be introduced by the length of
the connection to pin 10. However, the voltage at pin 10 is
compared to GND (pin 4) and an error could be introduced if
the grounded end of R
LIMIT
is not directly tied to pin 4. Good
circuit board layout practice would be to connect R
LIMIT
directly
between pins 8 and 4.
Switching noise spikes will invariably be found at pin 8. The
amplitude and duration will be load dependent. The noise
spikes could trip the current limit threshold which is only 200
mV. R
FILTER
and C
FILTER
should be adjusted so as to reduce the
switching noise well below 200 mV to prevent false current
limiting. The sum of the DC level plus the noise peak will de-
termine the current limiting value. Suggested starting values
are C
FILTER
= .01F, R
FILTER
= 5k.
The required value of R
LIMIT
may be calculated by:
R
LIMIT
= .2 V / I
LIMIT
where R
LIMIT
is the required resistor value, and I
LIMIT
is the
maximum desired current.
SHUTDOWN
The shutdown circuitry makes use of the internal current
limiting circuitry. The two functions may be externally combined
as shown below in Figure 1. R
LIMIT
will normally be a very low
value resistor and can be considered zero for this application.
R
SD
and R
FILTER
form a voltage divider for the shutdown signal.
After a suitable noise flter is designed for the current limit
adjust the value of R
SD
to give 317 mV of shutdown signal at
pin 10 when the shutdown signal is high. This means pin 10
will reach the 200 mV trip point in about one time constant
with low output current and
less time as output current
increases. The voltage at
pin 10 is referenced to pin
4 (GND). C
FILTER
will flter
both the current limit noise
spikes and the shutdown
signal. Shutdown and
current limit operate on
each cycle of the internal
switching rate. As long as
the shutdown signal is high the output will be disabled.
PROTECTION CIRCUITS
There are two conditions which will latch all the output tran-
sistors off. The frst of these conditions is activation of the high
side current limit. Specifcally, current in pin 7 (+V
S
) is moni-
tored. The DC trip level is about 35A and response time about
5us. As actual currents increase the response time decreases.
The external fault generally associated with this condition is
shorting one of the outputs to ground. However, a load fault
can also activate this high side current limit if the current rise
time is less than the response time of the flter discussed under
Current Limit. The second of these conditions is activation of
any of the four output transistor over-temperature sensors at
about 165C. Ambient temperature, air fow, amplifer mounting
problems and all the previously mentioned high current faults
contribute to junction temperature. When either of these pro-
tection circuits are activated, the root fault must be corrected
and power cycled to restore normal operation.
DEAD TIME
There is a dead time between the on and off of each out-
put. The dead time removes the possibility of a momentary
conduction path through the upper and lower transistors of
each half bridge output during the switching interval. During
the dead time all output transistors are off. Noise or fyback
may be observed at the outputs during this time due to the
high impedance of the outputs in the off state. This will vary
with the nature of the load.
ERROR AMPLIFIER
The internal error amplifer is an operational amplifer. For
highest loop accuracy it is best to confgure the op amp as an
integrator (See Figure 2). Feedback can be adjusted with ap-
propriate poles and zeroes to properly compensate the velocity
loop for optimum stability.
The op amp is operated from a single supply voltage gener-
ated internally. The non-inverting input of the op amp does not
have a common mode range which includes ground. R2 and
R7 are used with the reference voltage provided at pin 5 to
bias the non-inverting input to +5 volts, which is approximately
half of the voltage supplied internally to the op amp. Similarly,
R1 and the parallel combination of R5 R6 are selected to bias
the inverting input also at +5 volts. Resistors R1 R2 must be
matched. Likewise the parallel combination of R5 R6 must
be matched with R7. The source impedances of the tach
and the signal source may affect the matching and should be
considered in the design.
10
8
SHDN/FILTER
I
SENSE
R
FILTER
R
LIMIT
C
FILTER
R
SD
SHUTDOWN
SIGNAL
FIGURE 1.
REF OUT
R2 R1
R4
C2
R6
R7
R5
R3
C1
E/A OUT
IN
+IN
1
2
3
5
TO TACH
SIGNAL
FIGURE 2.
.1F
SA03
132 SA03U
P r o d u c t I n n o v a t i o n F r o m SA03
SA03
USA
BeO
TE949311
FEATURES
WIDE SUPPLY RANGE16-100V
30A CONTINUOUS TO 60C case
3 PROTECTION CIRCUITS
ANALOG OR DIGITAL INPUTS
SYNCHRONIZED OR EXTERNAL OSCILLATOR
FLEXIBLE FREQUENCY CONTROL
APPLICATIONS
MOTORS TO 4HP
REACTIVE LOADS
LOW FREQUENCY SONAR
LARGE PIEZO ELEMENTS
OFF-LINE DRIVERS
C-D WELD CONTROLLER
DESCRIPTION
The SA03 is a pulse width amplifer that can supply 3000W
to the load. An internal 45kHz oscillator requires no external
components. The clock input stage divides the oscillator fre-
quency by two, which provides the basic switching of 22.5 kHz.
External oscillators may also be used to lower the switching
frequency or to synchronize multiple amplifers. Current sensing
is provided for each half of the bridge giving amplitude and
direction data. A shutdown input turns off all four drivers of the
H bridge output. A high side current limit and the programmable
low side current limit protect the amplifer from shorts to sup-
ply or ground in addition to load shorts. The H bridge output
MOSFETs are protected from thermal overloads by directly
sensing the temperature of the die. The 12-pin hermetic MO-127
power package occupies only 3 square inches of board space.
BLOCK DIAGRAM AND TYPICAL APPLICATION
TOP
VIEW
CLK IN
CLK OUT
+PWM
PWM/RAMP
GND
ILIM/SHDN
ISENSE A
A OUT
+VS
VCC
*
*
B OUT
I SENSE B
1
2
3
4
5
6
12
11
10
9
8
7
TOP
VIEW
Case tied to pin 5. Allow no current in case. Bypassing of supplies
is required. Package is Apex MO-127 (STD). See Outline
Dimensions/Packages in Apex data book.
If +PWM > RAMP/PWM then A OUT > B OUT.
* See text.
+V
S
A OUT
B OUT
ILIM/SHDN
I SENSE A
I SENSE B RSENSE
RSENSE
MOTOR
GND
CLK IN
CONTROL
SIGNAL
CLK OUT
PWM/RAMP
+PWM
Vcc
5V
5V
SHUTDOWN
CONTROL
OUTPUT
DRIVERS
PWM
56K
1K
1K
5K
.01F
470pF
2 OSC
CURRENT
LIMIT
9
8
3
10
4
2
1
5
11
12
6
7
12-PIN POWER DIP
PACKAGE STYLE CR
SA03 P r o d u c t I n n o v a t i o n F r o m
MAY 2009
APEX SA03UREVH
SA03
SA03U 133
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SUPPLY VOLTAGE, +V
S
100V
SUPPLY VOLTAGE, V
CC
16V
2
150C
INPUT VOLTAGE, +PWM 0 to +11V
INPUT VOLTAGE, PWM 0 to +11V
INPUT VOLTAGE, I
LIM
0 to +10V
The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not crush,
machine, or subject to temperatures in excess of 850C to avoid generating toxic fumes.
CAUTION
NOTES: 1. Each of the two active output transistors can dissipate 150W.
C
= 25C, V
S
, V
CC
at typical specifcation.
3. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power
dissipation to achieve high MTTF. For guidance, refer to the heatsink data sheet.
5. If 100% duty cycle is not required V
S(MIN)
= 0V.
SPECIFICATIONS
2
MIN TYP MAX UNITS
CLOCK (CLK)
CLK OUT, high level
4
I
OUT
1mA 4.8 5.3 V
CLK OUT, low level
4
I
OUT
1mA 0 .4 V
FREQUENCY 44 45 46 kHz
RAMP, center voltage 5 V
RAMP, P-P voltage 4 V
CLK IN, low level
4
0 .9 V
CLK IN, high level
4
3.7 5.4 V
OUTPUT
TOTAL R
ON
.16
EFFICIENCY, 10A output V
S
= 100V 97 %
SWITCHING FREQUENCY OSC in 2 22 22.5 23 kHz
CURRENT, continuous
4
60C case 30 A
CURRENT, peak
4
40 A
POWER SUPPLY
VOLTAGE, V
S
Full temperature range 16
5
60 100 V
VOLTAGE, V
CC
Full temperature range 14 15 16 V
CURRENT, V
CC
I
OUT
= 0 80 mA
CURRENT, V
CC,
shutdown 50 mA
CURRENT, V
S
No Load 50 mA
I
LIM
/SHUTDOWN
TRIP POINT 90 110 mV
INPUT CURRENT 100 nA
THERMAL
3
RESISTANCE, junction to case Full temperature range, for each die .83 C/W
TEMPERATURE RANGE, case Meets full range specifcations 25 +85 C
SA03
134 SA03U
50 25 0 25 50 75 100 125
80
85
90
95
100
105
110
115
Vcc QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D

V
c
c

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)
1M 100K
95
98
99
100
CLOCK LOADING
96
97
10K
N
O
R
M
A
L
I
Z
E
D

F
R
E
Q
U
E
N
C
Y
,

(
%
)
0.6
10
REVERSE DIODE
F
L
Y
B
A
C
K

C
U
R
R
E
N
T
,

I
s
d

(
A
)
5
6
7
8
3
2
2
3
4
5
6
7
9
1
25 50 75 100 125 150
24
26
28
30
CONTINUOUS OUTPUT
22
0.8 1.0 1.2 1.4 1.6
5
0 20 40 60 80 100
25 10 15 20
C
O
N
T
I
N
U
O
U
S

A
M
P
S
16
18
20
0 75 100
0
POWER DERATING
150
25
DUTY CYCLE VS ANALOG INPUT
D
U
T
Y

C
Y
C
L
E
,

(
%
)
50 125
25
50
75
100
125
0
20
40
60
80
100
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

(
W
)
ANALOG INPUT, (V)
3 5 4 7 6
Vs, (V)
75
80
85
90
100
95
N
O
R
M
A
L
I
Z
E
D

V
c
c

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)
20
40
60
80
100
120
140
160
180
Vs QUIESCENT VS VOLTAGE
5 25
40
50
60
70
80
90
Vs QUIESCENT VS FREQUENCY
N
O
R
M
A
L
I
Z
E
D

V
s

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)
N
O
R
M
A
L
I
Z
E
D

V
s

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)
100
10 15 20
125C
55C
A OUT
B OUT
EACH ACTIVE
OUTPUT TRANSISTOR
F NOMINAL = 45kHz
Vcc = 15V
F = 22.5 kHz
NORMAL
OPERATION
SHUTDOWN
OPERATION
Vs = 60V, NO LOAD
0 5 10 15 20 25 30
OUTPUT CURRENT, (A)
0
2
4
6
8
10
TOTAL VOLTAGE DROP
T
O
T
A
L

V
O
L
T
A
G
E

D
R
O
P
,

(
V
)
125C
100C
85C
60C
25C
25C
55C
CASE TEMPERATURE
50
CLOCK FREQUENCY OVER TEMP
N
O
R
M
A
L
I
Z
E
D

F
R
E
Q
U
E
N
C
Y
,

(
%
)
25 0 25 50 75 100 125
98.0
98.5
99.0
99.5
100
100.5
101.0
101.5
102.0
SA03
SA03U 135
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
CLOCK CIRCUIT AND RAMP GENERATOR
The clock frequency is internally set to a frequency of ap-
proximately 45kHz. The CLK OUT pin will normally be tied
to the CLK IN pin. The clock is divided by two and applied to
an RC network which produces a ramp signal at the PWM/
RAMP pin. An external clock signal can be applied to the CLK
IN pin for synchronization purposes. If a clock frequency lower
than 45kHz is chosen an external capacitor must be tied to the
PWM/RAMP pin. This capacitor, which parallels an internal
capacitor, must be selected so that the ramp oscillates 4 volts
p-p with the lower peak 3 volts above ground.
PWM INPUTS
The full bridge driver may be accessed via the pwm input
comparator. When +PWM > -PWM then A OUT > B OUT. A
motion control processor which generates the pwm signal can
drive these pins with signals referenced to GND.
PROTECTION CIRCUITS
In addition to the externally programmable current limit there
is also a fxed internal current limit which senses only the high
side current. It is nominally set to 140% of the continuous
rated output current. Should either of the outputs be shorted
to ground the high side current limit will latch off the output
transistors. Also, the temperature of the output transistors is
continually monitored. Should a fault condition occur which
raises the temperature of the output transistors to 165C the
thermal protection circuit will activate and also latch off the
output transistors. In either case, it will be necessary to remove
the fault condition and recycle power to V
CC
to restart the circuit.
CURRENT LIMIT
There are two load current sensing pins, I SENSE A and I
SENSE B. The two pins can be shorted in the voltage mode
connection but both must be used in the current mode connec-
tion (see fgures A and B). It is recommended that R
LIMIT
resistors
be non-inductive. Load current fows in the I SENSE pins. To
avoid errors due to lead lengths connect the I LIMIT/SHDN pin
directly to the R
LIMIT

resistors (through
the filter network
and shutdown di-
vider resistor) and
connect the R
LIMIT

resistors directly to
the GND pin.
Switching noise
spikes will invariably
be found at the I
SENSE pins. The
noise spikes could trip the cur-
rent limit threshold which is only
100 mV. R
FILTER
and C
FILTER
should
be adjusted so as to reduce the
switching noise well below 100
mV to prevent false current limit-
ing. The sum of the DC level plus
the noise peak will determine
the current limit-
ing value. As in
most switching
circuits it may
be difficult to de-
termine the true
noise amplitude
without careful attention to grounding of the oscilloscope probe.
Use the shortest possible ground lead for the probe and con-
nect exactly at the GND terminal of the amplifer. Suggested
starting values are C
FILTER
= .01uF, R
FILTER
= 5k .
LIMIT
in voltage mode may be cal-
culated by:
R
LIMIT
= .1 V / I
LIMIT
where R
LIMIT
LIMIT
is the
maximum desired current. In current mode the required value
of each R
LIMIT
is 2 times this value since the sense voltage is
divided down by 2 (see Figure B). If R
SHDN
is used it will further
divide down the sense voltage. The shutdown divider network
will also have an effect on the fltering circuit.
BYPASSING
Adequate bypassing of the power supplies is required for
proper operation. Failure to do so can cause erratic and low
efficiency operation as well as excessive ringing at the out-
puts. The Vs supply should be bypassed with at least a 1F
ceramic capacitor in parallel with another low ESR capacitor
of at least 10F per amp of output current. Capacitor types
rated for switching applications are the only types that should
be considered. The bypass capacitors must be physically
connected directly to the power supply pins. Even one inch of
lead length will cause excessive ringing at the outputs. This
is due to the very fast switching times and the inductance of
the lead connection. The bypassing requirements of the Vcc
supply are less stringent, but still necessary. A .1F to .47F
ceramic capacitor connected directly to the Vcc pin will suffice.
STARTUP CONDITIONS
The high side of the all N channel output bridge circuit is
driven by bootstrap circuit and charge pump arrangement. In
order for the circuit to produce a 100% duty cycle indefnitely
the low side of each half bridge circuit must have previously
been in the ON condition. This means, in turn, that if the input
signal to the SA03 at startup is demanding a 100% duty cycle,
the output may not follow the command and may be in a tri-
state condition. The ramp signal must cross the input signal
at some point to correctly determine the output state. After the
ramp crosses the input signal level one time, the output state
will be correct thereafter.
I SENSE A
I SENSE B
I LIMIT/SHDN
R
FILTER
C
FILTER
R
LIMIT
R
SHDN
SHUTDOWN
SIGNAL
1K
FIGURE A. CURRENT LIMIT WITH
SHUTDOWN VOLTAGE MODE.
I SENSE A
I SENSE B
I LIMIT/SHDN
R
FILTER
C
FILTER
R
SHDN
SHUTDOWN
SIGNAL
1K
1K
FIGURE B. CURRENT LIMIT WITH
SHUTDOWN CURRENT MODE.
R
LIMIT
R
LIMIT
SA08
136 SA08U
P r o d u c t I n n o v a t i o n F r o m SA08
FEATURES
IGBT OUTPUTS
20A TO 100C CASE
APPLICATIONS
MOTORS
REACTIVE LOADS
MAGNETIC BEARINGS
OFF-LINE DRIVERS
C-D WELD CONTROLLER
DESCRIPTION
The SA08 is a pulse width modulation amplifer that can
supply 9KW to the load. An internal oscillator requires no
external components. The clock input stage divides the oscil-
lator frequency by two, which provides the switching frequency
of 22.5 kHz. The oscillator may also be used to synchronize
multiple amplifers. Current sensing is provided for each half
of the bridge giving amplitude and direction data. A shutdown
input turns off all four drivers of the H-bridge output. A high
side current limit and the programmable low side current limit
protect the amplifer from shorts to supply or ground in addition
to load shorts. The H-bridge output IGBTs are protected from
thermal overloads by directly sensing the temperature of the
die. The 12-pin hermetic MO-127 power package occupies
only 3 square inches of board space.
MOTOR TORQUE CONTROL
TOP
VIEW
CLK IN
CLK OUT
+PWM
FLAG
GND
ILIM/SHDN
ISENSE A
A OUT
+VS
VCC
*
*
B OUT
I SENSE B
1
2
3
4
5
6
12
11
10
9
8
7
TOP
VIEW
*See text. As +PWM goes more positive, A OUT duty cycle
increases.
+V
S
A OUT
B OUT
ILIM/SHDN
I SENSE A
I SENSE B RSENSE
RSENSE
MOTOR
GND
CLK IN
CONTROL
SIGNAL
CLK OUT
FLAG
+PWM
Vcc
5V
5V
SHUTDOWN
CONTROL
OUTPUT
DRIVERS
PWM
45K
1K
1K
5K
.01F
470pF
2 OSC
CURRENT
LIMIT
9
8
3
10
4
2
1
5
11
12
6
7
12-PIN POWER DIP
PACKAGE STYLE CR
MAY 2009
APEX SA08UREVF
SA08
SA08U 137
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
2
MIN TYP MAX UNITS
CLOCK (CLK)
CLK OUT, high level
4
I
OUT
1mA 4.8 5.3 V
CLK OUT, low level
4
I
OUT
1mA 0 .4 V
CLK IN, low level
4
0 .9 V
CLK IN, high level
4
3.7 5.4 V
FREQUENCY 44.10 45.00 46.90 kHz
ANALOG INPUT (+PWM)
center voltage 5 V
P-P voltage 0/100% modulation 4 V
FLAG
FLAG, high level 10 V
FLAG, low level 0 V
OUTPUT
TOTAL DROP I = 20A 5.4 V
S
= 380V 98 %
SWITCHING FREQUENCY OSC in 2 22.05 22.50 22.95 kHz
CURRENT, continuous
4
100C case 20 A
CURRENT, peak
4
28 A
POWER SUPPLY
VOLTAGE, V
S
5
240 450 V
VOLTAGE, V
CC
CURRENT, V
CC
I
OUT
= 0 80 mA
CURRENT, V
CC,
shutdown 50 mA
CURRENT, V
S
No Load 90 mA
I
LIM
/SHUTDOWN
THERMAL
3
RESISTANCE, junction to case Full temperature range, for each die 1 C/W
SUPPLY VOLTAGE, +V
S
450V
SUPPLY VOLTAGE, V
CC
16V
POWER DISSIPATION, internal
1
250W
2
150C
INPUT VOLTAGE, +PWM 0 TO +11V
INPUT VOLTAGE, I
LIM
0 TO +10V
The SA08 is constructed from static sensitive components. ESD handling procedures must be observed.
CAUTION
C
= 25C, V
S
, V
CC
3. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dis-
sipation to achieve high MTTF. For guidance, refer to the heatsink data sheet.
5. If 100% duty cycle is not required V
S(MIN)
= 0V.
SPECIFICATIONS
SA08
138 SA08U
50 25 0 25 50 75 100 125
80
85
90
95
100
105
110
115
1M 100K
95
98
99
100
CLOCK LOADING
96
97
10K
N
O
R
M
A
L
I
Z
E
D

F
R
E
Q
U
E
N
C
Y
,

(
%
)
D
U
T
Y

C
Y
C
L
E
,

(
%
)
0
20
40
60
80
100
ANALOG INPUT, (V)
3 5 4 7 6
N
O
R
M
A
L
I
Z
E
D

V
c
c

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)
A OUT
B OUT
F NOMINAL = 45kHz
Vcc = 15V
F = 22.5 kHz
NORMAL
OPERATION
SHUTDOWN
OPERATION
50
N
O
R
M
A
L
I
Z
E
D

F
R
E
Q
U
E
N
C
Y
,

(
%
)
25 0 25 50 75 100 125
98.0
98.5
99.0
99.5
100
100.5
101.0
101.5
102.0
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)
0.5
DIODE FORWARD VOLTAGE DROP, (V)
REVERSE DIODE
F
O
R
W
A
R
D

C
U
R
R
E
N
T
,

(
A
)
25 50 75 100 125
14
16
18
20
CONTINUOUS AMPS
12
1.0 1.5 2.0 3.0 2.5
5
0 100 200 300 400 500
25 10 15 20
C
O
N
T
I
N
U
O
U
S

A
M
P
S
,

(
A
)
10
0 75 100
0
POWER DERATING
25 50 125
25
50
75
100
125
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

(
W
)
Vs, (V)
84
88
92
96
100
50
75
100
125
150
5 25
60
70
50
80
90
N
O
R
M
A
L
I
Z
E
D

V
s

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)
N
O
R
M
A
L
I
Z
E
D

V
s

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)
100
10 15 20
EACH ACTIVE
OUTPUT TRANSISTOR
0 4 8 12 16 20
OUTPUT CURRENT, I (A)
2
3
4
5
6
TOTAL VOLTAGE DROP
T
O
T
A
L

V
O
L
T
A
G
E

D
R
O
P
,

(
V
)
100C
Tc = 100C Tc = 25C
25C
CASE TEMPERATURE
20
0
4
8
12
16
SA08
SA08U 139
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
adjusted so as to
reduce the switch-
ing noise well below
100 mV to prevent
false current limit-
ing. The sum of the
DC level plus the
noise peak will de-
termine the current
limiting value. As
in most switching
circuits it may be
difficult to deter-
mine the true noise
amplitude without
careful attention to
grounding of the oscilloscope probe. Use the shortest possible
ground lead for the probe and connect exactly at the GND
terminal of the amplifer. Suggested starting values are C
FILTER

= .1uF, R
FILTER
= 5k .
LIMIT
culated by:
R
LIMIT
= .1 V / I
LIMIT
where R
LIMIT
LIMIT
is the
of each R
LIMIT
SHDN
BYPASSING
STARTUP CONDITIONS
The high side of the IGBT output bridge circuit is driven by
bootstrap circuit and charge pump arrangement. In order for
the circuit to produce a 100% duty cycle indefnitely the low
side of each half bridge circuit must have previously been in
the ON condition. This means, in turn, that if the input signal
to the SA08 at startup is demanding a 100% duty cycle, the
output may not follow the command and may be in a tri-state
condition. The ramp signal must cross the input signal at some
point to correctly determine the output state. After the ramp
crosses the input signal level one time, the output state will
be correct thereafter.
GENERAL
proximately 45kHz. The CLK OUT pin will normally be tied to
the CLK IN pin. The clock is divided by two and applied to an
RC network which produces a ramp signal. An external clock
signal can be applied to the CLK IN pin for synchronization
purposes, but must be 45 kHz +/- 2%.
FLAG OUTPUT
Whenever the SA08 has detected a fault condition, the fag
output is set high (10V). When the programmable low side
current limit is exceeded, the FLAG output will be set high.
The FLAG output will be reset low on the next clock cycle. This
refects the pulse-by-pulse current limiting feature. When the
internally-set high side current limit is tripped or the thermal
limit is reached, the FLAG output is latched high. See PRO-
TECTION CIRCUITS below.
PROTECTION CIRCUITS
A fxed internal current limit senses the high side current.
Should either of the outputs be shorted to ground the high side
current limit will latch off the output transistors. The temperature
of the output transistors is also monitored. Should a fault condi-
tion raise the temperature of the output transistors to 165C
the thermal protection circuit latch off the output transistors.
The latched condition can be cleared by either recycling the
V
cc
power or by toggling the I LIMIT/SHDN input with a 10V
pulse. See Figures A and B. The outputs will remain off as long
as the shutdown pulse is high (10V).
CURRENT LIMIT
There are two load current sensing pins, I SENSE A and I
SENSE B. The two pins can be shorted in the voltage mode
connection but both must be used in the current mode connec-
tion (see fgures A and B). It is recommended that R
LIMIT
resistors
be non-inductive. Load current fows in the I SENSE pins. To
avoid errors due to lead lengths connect the I LIMIT/SHDN pin
directly to the R
LIMIT
resistors (through the flter network and
shutdown divider resis-
tor) and connect the
R
LIMIT
resistors directly
to the GND pin.
Swi t chi ng noi se
spikes will invariably
be found at the I SENSE
pins. The noise spikes
could trip the current
limit threshold which
is only 100 mV. R
FILTER

and C
FILTER
should be
I SENSE A
I SENSE B
I LIMIT/SHDN
R
FILTER
C
FILTER
R
LIMIT
1N4148
SHUTDOWN
SIGNAL
5K
0/10V
I SENSE A
I SENSE B
I LIMIT/SHDN
R
FILTER
C
FILTER
1N4148
0/10V
SHUTDOWN
SIGNAL
5K
5K
R
LIMIT
R
LIMIT
SA09
140 SA09U
SA09
FEATURES
500kHz SWITCHING
FULL BRIDGE OUTPUT 5-40V (80V P-P)
5A OUTPUT
1 IN
2
FOOTPRINT
FAULT PROTECTION
SHUTDOWN CONTROL
SYNCHRONIZABLE CLOCK
HERMETIC PACKAGE
APPLICATIONS
HIGH FIDELITY AUDIO AMPLIFIER
VIBRATION CANCELLING AMPLIFIER
B
R
I
D
G
E
D
R
I
V
E
R
THERMAL,
SHORT
CIRCUIT
PROTECT.
REG.
5V
+V
S
A OUT
5V OUT
B OUT
ILIM/SHDN
I SENSE A
I SENSE B
+PWM
RAMP/PWM
CLK OUT
18K
100pF
CLK IN
OSC CLK/2
R
FILTER
C
FILTER
R
SHDN
1K
R
LIMIT
SIGNAL
GND
5V
LOAD
SA09
Vcc
13
10
12
14
16
11
15
1
5
6
18
17
7
DESCRIPTION
The SA09 amplifer is a 40 volt, 500kHz PWM ampli-
fer. The full bridge output circuit provides 5 amps of
continuous drive current for applications as diverse as
high fdelity audio and brush type motors. Clock output
and input pins can be used for synchronization with
other amplifers or an externally generated clock. Direct
access to the pwm input is provided for connection to
digital motion control circuits. Protection circuits guard
against thermal overloads as well as shorts to supply
or ground. The current limit is programmable with one
or two external resistors depending on the application.
A shutdown input disables all output bridge drivers.
The 18 pin steel package is hermetically sealed.

BLOCK DIAGRAM
AND TYPICAL APPLICATION CONNECTIONS HIGH FIDELITY AUDIO
JAN 2009
APEX SA09REVA
SA09
SA09U 141
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SUPPLY VOLTAGE, +Vs to GND, 10mS surge 60 V
SUPPLY VOLTAGE, +V
CC
to GND 16 V
OUTPUT CURRENT, peak 7.5 A
POWER DISSIPATION, internal (Note 3) 80 W
TEMPERATURE, storage 65 150 C
OPERATING TEMPERATURE RANGE, case 55 125 C
INPUTS 0.4 +5.4 V
The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not
crush, machine, or subject to temperatures in excess of 850C to avoid generating toxic fumes.
CAUTION
* See text.
5V OUT
NC
NC
NC
+PWM
RAMP/-PWM
GND
NC
NC
CLK OUT*
CLK IN
I
LIM
/SHDN
I
SENSE
B
R
LIMIT
*
B OUT
+V
S
A OUT
I
SENSE
A
V
CC
+
R
LIMIT
*
+
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
18-pin DIP
PACKAGE STYLE EL
Case tied to Pin 7. Allow no current in case. Bypassing of sup-
plies is required. If +PWM > RAMP then A OUT > B OUT.
SA09
142 SA09U
SPECIFICATIONS
Parameter (Note 1) Test Conditions Min Typ Max Units
CLOCK OUT 0.98 1 1.02 MHz
CLOCK OUT, high level 4.7 5.3 V
CLOCK OUT, low level 0 0.2 V
5V OUT LOAD 5mA 4.988 5 5.012 V
OUTPUT
S
= 40V 94 %
SWITCHING FREQUENCY 500 kHz
CURRENT, peak (Note 4) 100 ms, 10% duty cycle 7 A
R
DS(ON)
(Note 4) 0.55
POWER SUPPLY
VOLTAGE, V
CC
VOLTAGE, V
S
Full temperature range 5 40 V
CURRENT, V
CC
Switching 50 mA
CURRENT, V
S
Switching, no load 90 mA
INPUTS (Note 4)
I
LIM
/SHDN, trip point 90 110 mV
PWM, +PWM, low level 0 0.8 V
PWM, +PWM, high level 2.7 V
CC
V
CLOCK IN, low level 0 0.3 V
CLOCK IN, high level 3 5.6 V
THERMAL (Note 2)
RESISTANCE, junction to case Full temperature range 3.5 C/W
TEMPERATURE RANGE, case Meets full range specifcations -25 85 C
NOTES:
1. All Min/Max characteristics and specifcations are guaranteed over the Specifed Operating Condi-
tions. Typical performance characteristics and specifcations are derived from measurements taken
at typical supply voltages and T
C
= 25C.
internal power dissipation to achieve high MTTF. For guidance, refer to the heatsink datasheet.
3. 40W in each of the two active output transistors on at any one time.
4. Min max values guaranteed but not tested.
SA09
SA09U 143
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
0 100 200 300 400 500
40
50
60
70
80
90
100
N
O
R
M
A
L
I
Z
E
D

V
c
c

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)
100
97.5
99.0
99.5
100
CLOCK LOADING
98.0
98.5
1K 10K
N
O
R
M
A
L
I
Z
E
D

F
R
E
Q
U
E
N
C
Y
,

(
%
)
0.6 1.8 2.2 2.4
5
REVERSE DIODE
F
L
Y
B
A
C
K

C
U
R
R
E
N
T
,

I
s
d

(
A
)
2
3
4
1.0
2
3
4
5
25 50 75 100 125 150
3
4
5
CONTINUOUS OUTPUT
2
1.0 1.4
50 10 15 20 25 30 35 40 125 25 0 25 50 75 100
C
O
N
T
I
N
U
O
U
S

A
M
P
S
0
1
0 75 100
0
POWER DERATING
40
25
D
U
T
Y

C
Y
C
L
E
,

(
%
)
50 125
10
20
30
0
20
40
60
80
100
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

(
W
)
ANALOG INPUT, (V)
1 3 2 4
CASE TEMPERATURE, T
C
(C) Vs, (V)
25
50
75
100
125
N
O
R
M
A
L
I
Z
E
D

V
c
c

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)
20
40
60
80
100
120
0 500
0
N
O
R
M
A
L
I
Z
E
D

V
s

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)
N
O
R
M
A
L
I
Z
E
D

V
s

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)
80
90
100
100
10
20
30
40
50
60
70
200 300 400
125C
85C
25C
55C
NORMAL OPERATION
SHUTDOWN OPERATION
B OUTPUT
A OUTPUT
EACH ACTIVE
OUTPUT TRANSISTOR
Vcc = 12V
F = 500kHz
F NOMINAL = 1M
50
N
O
R
M
A
L
I
Z
E
D

F
R
E
Q
U
E
N
C
Y
,

(
%
)
25 0 25 50 75 100 125
98.0
98.5
99.0
99.5
100
100.5
101.0
101.5
102.0
0 1 2 3 4 5
OUTPUT, I (A)
0
1
2
3
4
5
6
TOTAL VOLTAGE DROP
T
O
T
A
L

V
O
L
T
A
G
E

D
R
O
P
,

(
V
)
25C
55C
25C
125C
100C
85C
SA09
144 SA09U
GENERAL
Please read Application Note 30 on "PWM Basics". Refer to Application Note 1 "General Operating Considerations"
for helpful information regarding power supplies, heat sinking and mounting. Visit www.Cirrus.com for design tools
that help automate pwm flter design and heat sink selection. The "Application Notes" and "Technical Seminar" sec-
tions contain a wealth of information on specifc types of applications. Information on package outlines, heat sinks,
mounting hardware and other accessories are located in the "Packages and Accessories" section. Evaluation Kits
are available for most Apex Precision Power product models, consult the "Evaluation Kit" section for details. For the
most current version of all Apex Precision Power product data sheets, visit www.Cirrus.com.
The clock frequency is internally set to a frequency of approximately 1MHz. The CLK OUT pin will normally be
tied to the CLK IN pin. The clock is divided by two and applied to an RC network which produces a ramp signal at
the RAMP pin. An external clock signal can be applied to the CLK IN pin for synchronization purposes. If a clock
frequency lower than 1MHz is chosen an external capacitor must be tied to the RAMP pin. This capacitor, which
parallels an internal capacitor, must be selected so that the ramp oscillates 2.5 volts p-p with the lower peak 1.25
volts above ground.
BYPASSING
Adequate bypassing of the power supplies is required for proper operation. Failure to do so can cause erratic and
low effciency operation as well as excessive ringing at the outputs. The Vs supply should be bypassed with at least
a 1F ceramic capacitor in parallel with another low ESR capacitor of at least 10F per amp of output current. Ca-
pacitor types rated for switching applications are the only types that should be considered. The bypass capacitors
must be physically connected directly to the power supply pins. Even one inch of lead length will cause excessive
ringing at the outputs. This is due to the very fast switching times and the inductance of the lead connection. The
bypassing requirements of the V
CC
supply are less stringent, but still necessary. A 0.1F to 0.47F ceramic capacitor
connected directly to the V
CC
pin will suffce.
NOISE FILTERING
Switching noise can enter the SA09 through the external error amp to +PWM connection. A wise precaution is to low
pass flter this connection. Adjust the pass band of the flter to 10 times the bandwidth required by the application.
Keep the resistor value to 100 ohms or less since this resistor becomes part of the hysteresis circuit on the pwm
comparator.
PCB LAYOUT
The designer needs to appreciate that the SA09 combines in one circuit both high speed high power switching and
low level analog signals. Certain layout rules of thumb must be considered when a circuit board layout is designed
using the SA09:
1. Bypassing of the power supplies is critical. Capacitors must be connected directly to the power supply pins with
very short lead lengths (well under 1 inch). Ceramic chip capacitors are best.
2. Make all ground connections with a star pattern at pin 7.
3. Beware of capacitive coupling between output connections and signal inputs through the parasitic capacitance
between layers in multilayer PCB designs.
4. Do not run small signal traces between the pins of the output section (pins 11-16).
5. Do not allow high currents to fow into the ground plane.
6. Separate switching and analog grounds and connect the two only at pin 7 as part of the star pattern.
INTEGRATOR
The integrator provides the inverted signal for negative feedback and also the open loop gain for the overall applica-
tion circuit accuracy. Recommended value of C
INT
is 10 pF for stability. However, poles and zeroes can be added to
the circuit for overall loop stability as required.
SA09
SA09U 145
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
CURRENT LIMIT
There are two load current sensing pins, I SENSE A and I SENSE B. The two pins can be shorted in the voltage
mode connection but both must be used in the current mode connection (see fgures A and B). It is recommended
that R
LIMIT
resistors be non-inductive. Load current fows in the I SENSE pins. To avoid errors due to lead lengths
connect the I LIMIT/SHDN pin directly to the R
LIMIT
resistors (through the flter network and shutdown divider resistor)
and connect the R
LIMIT
resistors directly to the GND pin. Do not connect R
LIMIT
sense resistors to the ground plane.
Switching noise spikes will invariably be found at the I SENSE pins. The noise spikes could trip the current limit
threshold which is only 100 mV. R
FILTER
and C
FILTER
should be adjusted so as to reduce the switching noise well be-
low 100 mV to prevent false current limiting. The sum of the DC level plus the noise peak will determine the current
limiting value. As in most switching circuits it may be diffcult to determine the true noise amplitude without careful
attention to grounding of the oscilloscope probe. Use the shortest possible ground lead for the probe and connect
exactly at the GND terminal of the amplifer. Suggested starting values are C
FILTER
= 0.001uF, R
FILTER
= 5k .
LIMIT
in voltage mode may be calculated by: R
LIMIT
= 0.1 V / I
LIMIT
where R
LIMIT
LIMIT
is the maximum desired current. In current mode the required
value of each R
LIMIT
is 2 times this value since the sense voltage is divided down by 2 (see Figure B). If R
SHDN
is used
it will further divide down the sense voltage. The shutdown divider network will also have an effect on the fltering
circuit.
SHUTDOWN
The shutdown circuitry makes use of the internal current limiting circuitry. The two functions may be externally
combined in voltage and current modes as shown below in Figures A and B. The R
LIMIT
resistors will normally be
very low values and can be considered zero for this application. In Figure A, R
SHDN
and 1K form a voltage divider for
the shutdown signal. After a suitable noise flter is designed for the current limit, adjust the value of R
SHDN
to give a
minimum 110 mV of shutdown signal at the I LIMIT/SHDN pin when the shutdown signal is high. Note that C
FILTER
will
flter both the current limit noise spikes and the shutdown signal. Shutdown and current limit operate on each cycle
of the internal switching rate. As long as the shutdown signal is high the output will be disabled.
PROTECTION CIRCUITS
Circuits monitor the temperature and load on each of the bridge output transistors. On each cycle should any fault
condition be detected all output transistors in the bridge are shut off. Faults protected against are: shorts across
the outputs, shorts to ground, and over temperature conditions. Should any of these faults be detected, the output
transistors will be latched off *. In addition there is a built in dead time during which all the output transistors are off.
The dead time removes the possibility of a momentary conduction path through the upper and lower transistors of
each half bridge during the switching interval. Noise or fyback may be observed at the outputs during this time due
to the high impedance of the outputs in the off state. This will vary with the nature of the load.
*
To restart the SA09 remove the fault and recycle V
CC
or, alternatively, toggle the I LIMIT/SHDN (pin16) with a shut
down pulse.
I SENSE A
I SENSE B
I LIMIT/SHDN
R
FILTER
C
FILTER
R
LIMIT
R
SHDN
SHUTDOWN
SIGNAL
1K
I SENSE A
I SENSE B
I LIMIT/SHDN
R
FILTER
C
FILTER
R
SHDN
SHUTDOWN
SIGNAL
1K
1K
R
LIMIT
R
LIMIT
SA12
146 SA12U
SA12
FEATURE
HIGH FREQUENCY SWITCHING 200 kHz
15A CONTINUOUS TO 65C CASE
ANALOG OR DIGITAL INPUTS
APPLICATIONS
REACTIVE LOADS
LOW FREQUENCY SONAR
OFF-LINE DRIVERS
C-D WELD CONTROLLER
DESCRIPTION
The SA12 is a pulse width modulation amplifer that can
supply 3000W to the load. An internal 400kHz oscillator re-
quires no external components. The clock input stage divides
the oscillator frequency by two, which provides the 200 kHz
switching frequency. External oscillators may also be used to
lower the switching frequency or to synchronize multiple ampli-
fers. Current sensing is provided for each half of the H-bridge
giving amplitude and direction data. A shutdown input turns
off all four drivers of the H-bridge output. A high side current
limit and the programmable low side current limit protect the
amplifer from shorts to supply or ground in addition to load
shorts. The H-bridge output MOSFETs are protected from
thermal overloads by directly sensing the temperature of the
die. The 12-pin hermetic MO-127 power package occupies
only 3 square inches of board space.
TORQUE MOTOR DRIVER
TOP
VIEW
CLK IN
CLK OUT
+PWM
-PWM/RAMP
GND
ILIM/SHDN
ISENSE A
A OUT
+VS
VCC
*
*
B OUT
I SENSE B
1
2
3
4
5
6
12
11
10
9
8
7
TOP
VIEW
*See text. As +PWM goes more positive, A OUT duty cycle
increases.
+V
S
A OUT
B OUT
ILIM/SHDN
I SENSE A
I SENSE B
RSENSE
RSENSE
MOTOR
GND
CLK IN
CONTROL
SIGNAL
CLK OUT
PWM/RAMP
+PWM
Vcc
5V
SHUTDOWN
CONTROL
OUTPUT
DRIVERS
PWM
28K
1K
1K
5K
.01F
100pF
2 OSC
CURRENT
LIMIT
9
8
3
10
4
2
1
5
11
12
6
7
5V
12-PIN POWER DIP
PACKAGE STYLE CR
MAY 2009
APEX SA12UREVH
SA12
SA12U 147
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SUPPLY VOLTAGE, +V
S
200V
SUPPLY VOLTAGE, V
CC
16V
1
3
150C
INPUT VOLTAGE, +PWM 0 to +11V
INPUT VOLTAGE, PWM 0 to +11V
INPUT VOLTAGE, I
LIM
0 to +10V
CAUTION
C
= 25C, V
S
, V
CC
3. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power
dissipation to achieve high MTTF. For guidance, refer to the heatsink data sheet.
SPECIFICATIONS
2
MIN TYP MAX UNITS
CLOCK (CLK)
CLK OUT, high level
4
I
OUT
1mA 4.8 5.3 V
CLK OUT, low level
4
I
OUT
1mA 0 .4 V
FREQUENCY 392 400 408 kHz
RAMP, center voltage 5 V
RAMP, P-P voltage 4 V
CLK IN, low level
4
0 .9 V
CLK IN, high level
4
3.7 5.4 V
OUTPUT
TOTAL R
ON
4
.4
S
= 200V 97 %
SWITCHING FREQUENCY OSC in 2 196 200 204 kHz
CURRENT, continuous
4
65C case 15 A
CURRENT, peak
4
20 A
POWER SUPPLY
VOLTAGE, V
S
VOLTAGE, V
CC
CURRENT, V
CC
I
OUT
= 0 125 mA
CURRENT, V
CC,
shutdown 80 mA
CURRENT, V
S
No Load 200 mA
I
LIM
/SHUTDOWN
THERMAL
3
RESISTANCE, junction to case Full temperature range, for each die 1 C/W
SA12
148 SA12U
N
O
R
M
A
L
I
Z
E
D

V
c
c

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)
40 200 80 120 160
60
70
80
100
90
20
40
40
60
80
80
100
120 160 200
N
O
R
M
A
L
I
Z
E
D

V
s

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)
0 25 50 75 100 125 150 175200
Vs, (V)
20
40
60
120
100
80
140
N
O
R
M
A
L
I
Z
E
D

V
s

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)
D
U
T
Y

C
Y
C
L
E
,

(
%
)
0
20
40
60
80
100
ANALOG INPUT, (V)
3 5 4 7 6
A OUT
B OUT
1M 100K
95
98
99
100
CLOCK LOADING
96
97
10K
N
O
R
M
A
L
I
Z
E
D

F
R
E
Q
U
E
N
C
Y
,

(
%
)
F NOMINAL = 400kHz
0 75 100
0
POWER DERATING
125
25 50 125
25
50
75
100
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

(
W
)
EACH ACTIVE
OUTPUT RESISTOR
50 25 0 25 50 75 100 125
80
85
90
95
100
105
110
115
CASE TEMPERATURE, ( C)
N
O
R
M
A
L
I
Z
E
D

V
c
c

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

(
%
)
Vcc = 15V
F = 22.5 kHz
NORMAL
OPERATION
SHUTDOWN
OPERATION
NORMALIZED ON RESISTANCE
2.5
2
1.5
1
.5
J
(C)
N
O
R
M
A
L
I
Z
E
D

T
O
T
A
L

R
D
S

O
N
,
(
X
)
50 0 50 100 150
50
N
O
R
M
A
L
I
Z
E
D

F
R
E
Q
U
E
N
C
Y
,

(
%
)
25 0 25 50 75 100 125
98.0
98.5
99.0
99.5
100.0
100.5
101.0
101.5
102.0
0.6
REVERSE DIODE
F
L
Y
B
A
C
K

C
U
R
R
E
N
T
,

I
s
d

(
A
)
0.8 1.0 1.2 1.4
15
12
9
6
3
0
C
O
N
T
I
N
U
O
U
S

A
M
P
S
16
14
12
10
8
CONTINUOUS OUTPUT
25 50 75 100 125
125C
25C
25C
55C
85C
100C
TOTAL VOLTAGE DROP
12
8
10
4
6
2
0
OUTPUT CURRENT, (A)
T
O
T
A
L

V
O
L
T
A
G
E

D
R
O
P
,

(
V
)
0 3 6 9 12 15
60C
SA12
SA12U 149
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
the R
LIMIT
resistors directly to the
GND pin.
Switching noise spikes will in-
variably be found at the I SENSE
pins. The noise spikes could trip
the current limit threshold which
is only 100 mV. R
FILTER
and C
FILTER

should be adjusted so as to reduce
the switching noise well
below 100 mV to prevent
false current limiting.
The sum of the DC level
plus the noise peak will
determine the current
limiting value. As in most
switching circuits it may be difficult to determine the true noise
amplitude without careful attention to grounding of the oscil-
loscope probe. Use the shortest possible ground lead for the
probe and connect exactly at the GND terminal of the amplifer.
Suggested starting values are C
FILTER
= .01uF, R
FILTER
= 5k .
LIMIT
culated by:
R
LIMIT
= .1 V / I
LIMIT
where R
LIMIT
LIMIT
is the
of each R
LIMIT
SHDN
BYPASSING
MODULATION RANGE
The high side of the all N channel H-bridge is driven by a
bootstrap circuit. For the output circuit to switch high, the low
side circuit must have previously been switched on in order to
charge the bootstrap capacitor. Therefore, if the input signal
to the SA12 demands a 100% duty cycle upon start-up the
output will not follow and will be in a tri-state (open) condition.
The ramp signal must cross the input signal at some point to
correctly determine the output state. After the ramp crosses the
input signal one time the output state will be correct thereafter.
In addition, if during normal operation the input signal drives
the SA12 beyond its linear modulation range (approximately
95%) the output will jump to 100% modulation.
GENERAL
proximately 400kHz. The CLK OUT pin will normally be tied
to the CLK IN pin. The clock is divided by two and applied to
an RC network which produces a ramp signal at the PWM/
RAMP pin. An external clock signal can be applied to the CLK
IN pin for synchronization purposes. If a clock frequency lower
than 400kHz is chosen an external capacitor must be tied to
the PWM/RAMP pin. This capacitor, which parallels an internal
capacitor, must be selected so that the ramp oscillates 4 volts
p-p with the lower peak 3 volts above ground.
PWM INPUTS
The full bridge driver may be accessed via the pwm input
comparator. When +PWM > -PWM then A OUT > B OUT. A
motion control processor which generates the pwm signal can
drive these pins with signals referenced to GND.
PROTECTION CIRCUITS
A fxed internal current limit senses the high side current.
Should either of the outputs be shorted to ground the high
side current limit will latch off the output transistors. The tem-
perature of the output transistors is also monitored. Should a
fault condition raise the temperature of the output transistors
to 165C the thermal protection circuit will latch off the output
transistors. The latched condition can be cleared by either
recycling the V
cc
power or by toggling the I LIMIT/SHDN input
with a 10V pulse. See Figures A and B. The outputs will remain
off as long as the shutdown pulse is high (10V).
When supply voltage is over 100V, these circuits may not
protect the FET switches in the case of short circuits directly
at the pins of the amplifer. However, a small inductance be-
tween the amplifer and the short circuit will limit current rise
time and the protection circuits will be effective. A pair of 12
inch wires is adequate inductance.
CURRENT LIMIT
There are two load current
sensing pins, I SENSE A and
I SENSE B. The two pins can
be shorted in the voltage
mode connection but both
must be used in the current
mode connection (see fgures
A and B). It is recommended
that R
LIMIT
resistors be non-
inductive. Load current fows
in the I SENSE pins. To avoid errors due to lead lengths connect
the I LIMIT/SHDN pin directly to the R
LIMIT
resistors (through
the flter network and shutdown divider resistor) and connect
I SENSE A
I SENSE B
I LIMIT/SHDN
R
FILTER
C
FILTER
R
LIMIT
IN4148
SHUTDOWN
SIGNAL
5K
0/10V
I SENSE A
I SENSE B
I LIMIT/SHDN
R
FILTER
C
FILTER
IN4148
0/10V
SHUTDOWN
SIGNAL
5K
5K
R
LIMIT
R
LIMIT
SA50CE
150 SA50CEU
SA50CE
FEATURES
LOW COST COMPLETE H-BRIDGE
SELF-CONTAINED SMART LOWSIDE/HIGHSIDE DRIVE
CIRCUITRY
SINGLE ENDED SUPPLY OPERATION
WIDE SUPPLY RANGE: UP TO 80V
HERMETIC SEALED PACKAGE
HIGH EFFICIENCY: 95% TYPICAL
FOUR QUADRANT OPERATION, TORQUE
CONTROL CAPABILITY
INTERNAL PWM GENERATION
APPLICATIONS
REACTIVE LOADS
DESCRIPTION
The SA50CE is a pulse width modulation amplifer that can
continuously supply 5A to the load. The full bridge amplifer
can be operated over a wide range of supply voltages. All of
the drive/control circuitry for the lowside and high side switches
are internal to the hybrid. The PWM circuitry is internal as well,
leaving the user to only provide an analog signal for the mo-
tor speed and direction, or audio signal for switchmode audio
amplifcation. The SA50CE is packaged in a space efficient
isolated 8-pin TO-3 that can be directly connected to a heatsink.
BLOCK DIAGRAM
TYPICAL APPLICATIONS
+V
S
(LOAD)
(CURRENT)
H-BRIDGE
DRIVE
CIRCUITRY
45KHz
PWM
GENERATOR
RSENSE B
GND
INPUT
V
CC
(+12V)
RSENSE A
B A
Vcc
AUDIO
INPUT
+V
S
+V
S
SPEAKER
GND
SA50CE
SA50CE
DC MOTOR
ANALOG
INPUT
GND
Vcc
TOP VIEW
1
2
3
4
5
6
7
8
Vcc
GND
RSENSE A
A OUT
INPUT
RSENSE B
B OUT
+V
S
8-PIN TO-3
PACKAGE STYLE CE
H-Bridge Motor Driver/Amplifiers
SA50CE P r o d u c t I n n o v a t i o n F r o m
MAY 2009
APEX SA50CEUREVB
SA50CE
SA50CEU 151
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SUPPLY VOLTAGE, +V
S
80V
5
OUTPUT CURRENT, peak 7A
LOGIC SUPPLY VOLTAGE, Vcc 16V
1
3
175C
INPUT VOLTAGE +1V to Vcc 1.5 Vdc
SPECIFICATIONS
2
MIN TYP MAX UNITS
INPUT
ANALOG INPUT VOLTAGES Vcc = 9.5V to 15V
MOTOR A, B = 50% Duty Cycle V
CC
/2 V
MOTOR A = 100% Duty Cycle High
6
2V
CC
/3 V
MOTOR B = 100% Duty Cycle High
6
V
CC
/3 V
OUTPUT
Vds (ON) VOLTAGE, each MOSFET Ids = 5A 1.0 1.3 Vdc
TOTAL Ron, both MOSFETs 0.4
EFFICIENCY, 5A OUTPUT +V
S
= 80V 95 %
SWITCHING FREQUENCY 40 45 50 kHz
CURRENT, peak t = 100 m-sec 7 A
SWITCHING CHARACTERISTICS
4
+V
S
= 28V, Vcc = 12V, Ic =2A
RISE TIME 36 54 ns
FALL TIME 170 250 ns
DEAD TIME 100 ns
POWER SUPPLY
+V
S
VOLTAGE
5
+V
S
I = Load I 80 V
Vcc VOLTAGE 9.5 12 15 V
Vcc CURRENT Vcc = 12Vdc 20 30 mA
THERMAL
3
RESISTANCE, junction to case Full temp range, for each transistor 2.0 C/W
TEMPERATURE RANGE, case 40 +85 C
The SA50CE is constructed from MOSFET transistors. ESD handling procedures must be observed.
CAUTION
NOTES: 1. Each of the two active output transistors can dissipate 36W. This is an output FET rating only; normal operation at worst case
conditions and maximum duty cycle only causes 19 watts internal heat generation in each active output FET. Use 40 watts
maximum to size heatsink.
C
= 25C, Vcc = 12Vdc.
3. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation to
achieve high MTTF. For guidance, refer to the heatsink data sheet.
5. Derate linearly to 70V at 40C from T
C
= +25C.
WARNINGAMPLIFIER PROTECTION
The SA50CE contains an internal logic chip that turns on
and turns off output MOSFET drivers at a certain sequence.
Noises or oscillation caused by external wiring inductance,
lack of proper power supply bypass capacitors, ground, sup-
ply and local internal loops, may be fed back to this logic chip
and cause it to turn on one or more MOSFET drivers at the
wrong time, thus destroying the SA50CE. A well laid out PC
board with low impedance copper ground plane and excellent
bypassing is necessary for the SA50CE to function properly.
A low ESR high frequency bypass capacitor, such as a 0.1 f
100V X7R ceramic, or better, should be mounted as close to
the Vs and ground pins as possible to avoid radiation of high
frequency transients on the power supply wiring. The Apex
Precision Power EK-SA50CE evaluation board is recommended
for fast and easy breadboarding of circuits using the SA50CE.
SA50CE
152 SA50CEU
T
J

=

1
7
5
C
T J

=

1
2
5
C
T J
=
7
5
C
TJ
=
2
5
C
VOLTAGE DROP (V), BOTH FETs
4
0 5 4 3 2 1
5
3
2
1
0
OUTPUT CURRENT, (A)
V
O
L
T
A
G
E

D
R
O
P
,

(
V
)
1 2 5 10 20 50 100
0
100
200
300
400
500
H-BRIDGE FET CAPACITANCE
D
R
A
I
N
-
T
O
-
S
O
U
R
C
E

C
A
P
,

(
p
F
)

DRAIN-TO-SOURCE VOLTAGE, (V)
40 120
0.25
0.35
0.45
0.75
0.85
0.95
1.05
INPUT CURRENT VS TEMP
0.55
0.65
20 0 20 40 60 80 100
I
N
P
U
T

B
I
A
S

C
U
R
R
E
N
T
,

(
A
)

JUNCTION TEMPERATURE (C)
60 180 20 20 60 100 140
OUTPUT RESISTANCE DRIFT
O
U
T
P
U
T

R
E
S
I
S
T
A
N
C
E
,

(
N
O
R
M
A
L
I
Z
E
D
)

0
0.5
1
1.5
2
2.5
MAXIMUM INTERNAL
POWER @ 5A, 80V
POWER DERATING
SINGLE FET POWER CAPABILITY
TEMPERATURE, C
-50 -25 0 25 50 75 100 125 150 175
P
O
W
E
R
,

W
A
T
T
S
50
40
35
30
25
20
15
10
5
0
45
EFFICIENCY vs. LOAD CURRENT
LOAD CURRENT, (A)
E
F
F
I
C
I
E
N
C
Y
,

(
%
)
2 5 4 3 1
96
100
98
96
94
92
90
88
V
S
= 80V
V
S
=

2
0
V
V
S
=
4
0
V
V
S
= 60V
90% DUTY CYCLE
L/R > 75-sec
EFFICIENCY vs. POWER SUPPLY VOLTAGE
SUPPLY VOLTAGE, V
S
(V)
E
F
F
I
C
I
E
N
C
Y
,

(
%
)
I
O
= 1A
80 70 60 50 40 30 20 10 0
100
98
96
94
92
90
88
86
84
I
O
= 5A
I
O
= 4A
I
O
= 3A
I
O
= 2A
90% DUTY CYCLE
L/R > 75-sec
SA50CE
SA50CEU 153
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
Please read Application Note 30 on "PWM Basics".
Refer to Application Note 1 "General Operating Con-
siderations" for helpful information regarding power
supplies, heat sinking and mounting. Visit www.Cirrus.
com for design tools that help automate pwm flter de-
sign and heat sink selection. The "Application Notes"
and "Technical Seminar" sections contain a wealth of
information on specifc types of applications. Information
on package outlines, heat sinks, mounting hardware
and other accessories are located in the "Packages and
Accessories" section. Evaluation Kits are available for
most Apex Precision Power product models, consult
the "Evaluation Kit" section for details. For the most
current version of all Apex Precision Power product
data sheets, visit www.Cirrus.com.
PIN DESCRIPTION
V
CC
- is the low voltage supply for powering internal
logic and drivers for the lowside and highside
MOSFETS. The supplies for the highside drivers
are derived from this voltage.
V
S
- is the higher voltage H-bridge supply. The MOS-
FETS obtain the output current from this supply
pin. Proper by-passing to GND with sufficient
capacitance to suppress any voltage transients,
and to ensure removing any drooping during
switching, should be done as close to the pins
on the hybrid as possible.
A OUT - is the output pin for one half of the bridge. Increas-
ing the input voltage causes increasing duty cycle at
this output.
B OUT - is the output pin for the other half of the bridge.
Decreasing the input voltage causes increasing duty
cycles at this point.
RSENSE A - This is the connection for the bottom of the A
half bridge. This can have a sense resistor connected
to the V
S
return ground for current limit sensing, or can
be connected directly to ground. The maximum voltage
on this pin is 2 volts with respect to GND.
GND - is the return connection for the input logic and V
CC
.
RSENSE B - This is the connection for the bottom of the B
half bridge. This can have a sense resistor connection
to the V
S
return ground for current limit sensing, or can
be connected directly to ground. The maximum voltage
on this pin is 2 volts with respect to GND.
INPUT - is an analog input for controlling the PWM pulse width
of the bridge. A voltage higher than V
CC
/2 will produce
greater than 50% duty cycle pulses out of A OUT. A
voltage lower than V
CC
/2 will produce greater than 50%
duty cycle pulses out of B OUT.
TYPICAL SYSTEM OPERATION
This is a diagram of a typical application of the SA50CE.
The design Vcc voltage is +12 volts. V
CC
is internally bypassed
with a good low ESR ceramic capacitor. A higher ESR bulk
capacitor, such as a tantalum electrolytic, may be used ex-
ternally in parallel. The analog input can be an analog speed
control voltage from a potentiometer, other analog circuitry or
by microprocessor and a D/A converter. This analog input gets
pulled by the current control circuitry in the proper direction
to reduce the current fow in the bridge if it gets too high. The
gain of the current control amplifer will have to be set to obtain
the proper amount of current limiting required by the system.
Current sensing is done in this case by a 0.1 sense resistor
to sense the current from both legs of the bridge separately. It
is important to make the high current traces as big as possible
to keep inductance down. The storage capacitor connected to
the V
S
and the hybrid GND should be large enough to provide
the high energy pulse without the voltage sagging too far. A
low ESR capacitor will be required. Mount capacitor as close
to the hybrid as possible. The connection between GND and
the V
S
return should not be carrying any motor current. The
sense resistor signal is common mode fltered as necessary
to feed the limiting circuitry. This application will allow full four
quadrant torque control for a closed loop servo system.
A snubber network is usually required, due to the inductance
in the power loop. It is important to design the snubber network
to suppress any positive spikes above +V
S
and negative spikes
below 2V with respect to pin 7 (GND).
SA50CE
+12V
Vcc
+V
S
+V
S
CURRENT CONTROL
RSENSE B
RSENSE A
SENSE
RESISTORS
0.1
1000pF
200V
100
2W
SNUBBER NETWORK
6.8F
100V
POLY
MYLAR
GND
GND
R
R
RIN
RIN
Rf
+12V
+12V
RDIVIDE
RDIVIDE
(VCC2)
RDIVIDE = 2X Rf
ANALOG
INPUT
NO OUTPUT
SWITCHING
CURRENT
MOTOR A
3
6
8
7
MOTOR B
MOTOR
5
1
2
4
INPUT
22F
SA53
154 SA53U
SA53
DESCRIPTION
The SA53 is a fully integrated switching amplifer de-
signed primarily to drive DC brush motors. Two inde-
pendent half bridges provide over 10 amperes peak
output current under microcontroller or DSC control.
Thermal and short circuit monitoring is provided, which
generates fault signals for the microcontroller to take
appropriate action. A block diagram is provided in Fig-
ure 1.
Additionally, cycle-by-cycle current limit offers user
programmable hardware protection independent of the
microcontroller. Output current is measured using an
innovative low loss technique. The SA53 is built using
a multi-technology process allowing CMOS logic con-
trol and complementary DMOS output power devices
on the same IC. Use of P-channel high side FETs en-
ables 60V operation without bootstrap or charge pump
circuitry.
The Power Quad surface mount package balances ex-
cellent thermal performance with the advantages of a
low profle surface mount package.
FEATURES
Low Cost Intelligent Switching Amplifer
Directly Connects to Most Embedded Micro-
controllers and Digital Signal Controllers
Integrated Gate Driver Logic with Dead-time
Generation and Shoot-through Prevention
Wide Power Supply Range (8.5 V To 60 V)
Over 10A Peak Output Current per Phase
3A Continuous Output Current per Phase
Independent Current Sensing for each Output
User Programmable Cycle-by-cycle Current
Limit Protection
Over-Current and Over-Temperature Warning
Signals
APPLICATIONS
Bidirectional DC Brush Motors
2 Unidirectional DC Brush Motors
2 Independent Solenoid Actuators
Stepper Motors
Switching Amplifier
FIGURE 1. BLOCK DIAGRAM
SA53 Switching Amplifier
Vs 1
P GND 1
Gate
Control
PWM
Signals
Out 1
Out 2
P GND 2
TEMP
GND
Vs 2
V
S
+
I
LIM
/DIS1
SC
DIS2
SGND
P hase 1
P hase 2
Control
Logic
V
DD
I1' I2'
I1'
I2'
Fault
Logic
I1
I2
1t
1b
2t
2b
V
DD
V
DD
MAY 2009
APEX SA53UREVA
SA53
SA53U 155
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SUPPLY VOLTAGE V
S
60 V
SUPPLY VOLTAGE V
DD
5.5 V
LOGIC INPUT VOLTAGE (-0.5) (V
DD
+0.5) V
OUTPUT CURRENT, peak, 10ms (NOTE 2) I
OUT
10 A
POWER DISSIPATION, avg, 25C (NOTE 2) P
D
100 W
TEMPERATURE, solder, 10sec T
S
260 C
TEMPERATURE, junction (NOTE 2) T
J
150 C
TEMPERATURE RANGE, storage T
STG
55 125 C
OPERATING TEMPERATURE, case T
A
40 125 C
PARAMETER TEST CONDITIONS (Note 1) MIN TYP MAX UNITS
LOGIC
INPUT LOW 1 V
INPUT HIGH 1.8 V
OUTPUT LOW 0.3 V
OUTPUT HIGH 3.7 V
OUTPUT CURRENT
(SC, Temp, I
LIM
/DIS1)
50 mA
POWER SUPPLY
V
S
UVLO 50 60 V
V
S
UNDERVOLTAGE LOCKOUT, (UVLO) 8.3 V
V
DD
4.5 5.5 V
SUPPLY CURRENT, V
S
20 kHz (One phase switching at
50% duty cycle) , V
S
=50V, V
DD
=5V
25 30 mA
SUPPLY CURRENT, V
DD
50% duty cycle) , V
S
=50V, V
DD
=5V
5 6 mA
CURRENT LIMIT
CURRENT LIMIT THRESHOLD (Vth) 3.75 V
Vth HYSTERESIS 100 mV
OUTPUT
CURRENT, CONTINUOUS 25C Case Temperature 3 A
RISING DELAY, TD (RISE) See Figure 10 270 ns
FALLING DELAY, TD (FALL) See Figure 10 270 ns
DISABLE DELAY, TD (DIS) See Figure 10 200 ns
ENABLE DELAY, TD (DIS) See Figure 10 200 ns
RISE TIME, T (RISE) See Figure 11 50 ns
FALL TIME, T (FALL) See Figure 11 50 ns
ON RESISTANCE SOURCING
(P-CHANNEL)
3A Load 400 m
ON RESISTANCE
SINKING (N-CHANNEL)
3A Load 400 m
SPECIFICATIONS
SA53
156 SA53U
NOTES:
1. (All Min/Max characteristics and specifcations are guaranteed over the Specifed Operating Condi-
C
= 25C).
2. Long term operation at elevated temperature will result in reduced product life. De-rate internal power
dissipation to achieve high MTBF.
3. Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any
set of conditions, do not exceed the specifed current rating or a junction temperature of 150C.
PARAMETER TEST CONDITIONS (Note 1) MIN TYP MAX UNITS
THERMAL
THERMAL WARNING 135 C
THERMAL WARNING HYSTERESIS 40 C
RESISTANCE, junction to case Full temperature range 1.25 1.5 C/W
TEMPERATURE RANGE, case Meets Specifcations -40 85 C
FIGURE 2. 64-pin QFP, Package Style HQ
SPECIFICATIONS, continued
SA53
SA53U 157
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
DIODE FORWARD VOLTAGE - TOP FET
(P-Channel)
0
1
2
3
4
5
FORWARD VOLTAGE (V)
C
U
R
R
E
N
T

(
A
)
0.5 1.5 1.3 1.1 0.9 0.7
DIODE FORWARD VOLTAGE - BOTTOM FET
(N-Channel)
0
1
2
3
4
5
FORWARD VOLTAGE (V)
C
U
R
R
E
N
T

(
A
)
0.5 1.5 1.3 1.1 0.9 0.7
ON RESISTANCE - TOP FET
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
I
OUT
,(A)
R
D
S
(
o
n
)
,
(
)
V
S
=11
V
S
=13
V
S
=15
V
S
>17
10 0 9 8 7 6 5 4 3 2 1
(P-Channel)
ON RESISTANCE - BOTTOM FET
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
10
I
OUT
,(A)
R
D
S
(
o
n
)
,
(
)
V
S
=11
V
S
=13
V
S
=15
V
S
=17
V
S
>22
0 9 8 7 6 5 4 3 2 1
(N-Channel)
POWER DERATING
0
20
40
60
80
100
120
CASE TEMPERATURE, T
C
P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
D
-40 120 80 40 0
V
DD
SUPPLY CURRENT
4.5
4.6
4.7
4.8
4.9
5
0 50 100 150 200 250 300
FREQUENCY (kHz)
V
D
D

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
ONE PHASE SWITCHING @
50% DUTY CYCLE; V
S
=50V
V
DD
SUPPLY CURRENT
4
4.5
5
5.5
6
6.5
7
7.5
8
10 20 30 40 50 60
V
S
SUPPLY VOLTAGE (V)
V
D
D

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)ONE PHASE SWITCHING
FREQUENCY =20kHz
50% DUTY CYCLE
25C
125C
CURRENT SENSE
0.1
1
10
0.01 0.1 1 10
SENSE CURRENT (mA)
L
O
A
D

C
U
R
R
E
N
T

(
A
)
V
S
SUPPLY CURRENT
20
40
60
80
100
120
140
160
180
0 50 100 150 200 250 300
FREQUENCY (kHz)
V
S

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
50% DUTY CYCLE; V
S
=50V
0
V
S
SUPPLY CURRENT
0
5
10
15
20
25
V
S
SUPPLY VOLTAGE (V)
V
S

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
125C
25C
ONE PHASE SWITCHING
FREQUENCY =20kHz
50% DUTY CYCLE
10 20 30 40 50 60
SA53
158 SA53U
FIGURE 3. EXTERNAL CONNECTIONS
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
1234567891
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
O
U
T

2
O
U
T

2
N
C
V
S

2
V
S

2
V
S

2
V
S

2
N
C
N
C
N
C
N
C
N
C
P
G
N
D

1
P
G
N
D

1
P
G
N
D

1
P
G
N
D

1
N
C
O
U
T

1
O
U
T

1
O
U
T

1
I
2
N
C
S
C
N
C
S
G
N
D
N
C
I
L
I
M
/
D
I
S
1
N
C
S
G
N
D
N
C
S
G
N
D
N
C
S
G
N
D
N
C
1
b
N
C1
t
N
C
V
D
D
N
C
OUT 2
NC
PGND 2
PGND 2
PGND 2
HS
HS
NC
2b
NC
2t
NC
NC
V
S
1
V
S
1
V
S
1
NC
HS
HS
TEMP
NC
DIS2
NC
I1
TABLE 1. PIN DESCRIPTIONS
Pin # Pin Name Signal Type Simplifed Pin Description
29,30,31 V
S
(phase 1) Power High Voltage Supply (8.5-60V) supplies phase 1 only
51,52,53 OUT 2 Power Output Half Bridge 2 Power Output
55,56,57 PGND (phase 2) Power High Current GND Return Path for Power Output 2
3 SC Logic Output Indication of a short of an output to supply, GND or another phase
61 2b Logic Input Logic high commands 2 phase lower FET to turn on
63 2t Logic Input Logic high commands 2 phase upper FET to turn on
1 I2 Analog Output Phase 2 current sense output
7 I
LIM
/DIS1 Logic Input/Output
As an output, logic high indicates cycle-by-cycle current limit, and
logic low indicates normal operation. As an input, logic high places
all outputs in a high impedance state and logic low disables the
cycle-by-cycle current limit function.
5,9,11,13 SGND Power Analog and digital GND internally connected to PGND
19 V
DD
Power Logic Supply (5V)
23 DIS2 Logic Input Logic high places all outputs in a high impedance state
SA53
SA53U 159
G
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E
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B
A
G
H
I
F
E
D
C
B
A
25 TEMP Logic Output Thermal indication of die temperature above 135C
46,47,48,49 V
S
(phase 2) Power High Voltage Supply phase 2
37,38,39,40 PGND (phase 1) Power High Current GND Return Path for Power Outputs 1&2
26,27,58,59 HS Mechanical Pins connected to the package heat slug
2,4,6,8,10,
12,14,16,18,
20,22,24,28,
32,36,41,42,
43,44,45,50,
54,60,62,64
NC --- Do Not Connect
1.2 Pin Descriptions
V
S
: Supply voltage for the output transistors. These pins require decoupling (1F capacitor with good high fre-
quency characteristics is recommended) to the PGND pins. The decoupling capacitor should be located as
close to the V
S
and PGND pins as possible. Additional capacitance will be required at the V
S
pins to handle load
current peaks and potential motor regeneration. Refer to the applications section of this datasheet for additional
discussion regarding bypass capacitor selection. Note that V
S
pins 29-31 carry only the phase 1 supply current.
Pins 46-49 carry supply current for phase 2. Phase 1 may be operated at a different supply voltage from phase
2. Both V
S
voltages are monitored for undervoltage conditions.
OUT 1, OUT 2: These pins are the power output connections to the load. NOTE: When driving an inductive load, it
is recommended that two Schottky diodes with good switching characteristics (fast t
RR
specs) be connected to
each pin so that they are in parallel with the parasitic back-body diodes of the output FETs. (See Section 2.6)
PGND: Power Ground. This is the ground return connection for the output FETs. Return current from the load fows
through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See section
2.1 of this datasheet for more details.
SC: Short Circuit output. If a condition is detected on any output which is not in accordance with the input com-
mands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approxi-
mately 200ns during switching transitions but in high current applications, short glitches may appear on the
SC pin. A high state on the SC output will not automatically disable the device. The SC pin includes an internal
12k series resistor.
1b, 2b: These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower N-
channel output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low turns the low
side N-channel FET off. If 2b or 2b is high at the same time that a corresponding 1t or 2t input is high, protection
circuitry will turn off both FETs in order to prevent shoot-through on that output phase. Protection circuitry also
includes a dead-time generator, which inserts dead time in the outputs in the case of simultaneous switching of
the top and bottom input signals.
1t, 2t: These Schmitt triggered logic level inputs are responsible for turning the associated top side, or upper P-
channel FET outputs on and off. Logic high turns the top P-channel FET on, and a logic low turns the top P-
channel FET off.
I1, I2: Current sense pins. The SA53 supplies a positive current to these pins which is proportional to the current
fowing through the top side P-channel FET for that phase. Commutating currents fowing through the backbody
diode of the P-channel FET or through external Schottky diodes are not registered on the current sense pins.
Nor do currents fowing through the low side N-channel FET, in either direction, register at the current sense
pins. A resistor connected from a current sense pin to SGND creates a voltage signal representation of the
phase current that can be monitored with ADC inputs of a processor or external circuitry.
SA53
160 SA53U
The current sense pins are also internally compared with the current limit threshold voltage reference, Vth. If
the voltage on any current sense pin exceeds Vth, the cycle by cycle current limit circuit engages. Details of
this functionality are described in the applications section of this datasheet.
I
LIM
/DIS1: This pin is directly connected to the disable circuitry of the SA53. Pulling this pin to logic high places OUT
1 and OUT 2 in a high impedance state. This pin is also connected internally to the output of the current limit
latch through a 12k resistor and can be monitored to observe the function of the cycle-by-cycle current limit
feature. Pulling this pin to a logic low effectively disables the cycle-by-cycle current limit feature.
SGND: This is the ground return connection for the V
DD
logic power supply pin. All internal analog and logic circuitry
is referenced to this pin. PGND is internally connected to GND through a resistance of a few ohms,. However, it
is highly recommended to connect the GND pin to the PGND pins externally as close to the device as possible.
Failure do to this may result in oscillations on the output pins during rising or falling edges.
V
DD
: This is the connection for the 5V power supply, and provides power for the logic and analog circuitry in the
SA53. This pin requires decoupling (at least 0.1F capacitor with good high frequency characteristics is recom-
mended) to the SGND pin.
DIS2: The DIS2 pin is a Schmitt triggered logic level input that places OUT 1 and OUT 2 in a high impedance state
when pulled high. DIS2 has an internal 12k pull-down resistor and may therefore be left unconnected.
TEMP: This logic level output goes high when the die temperature of the SA53 reaches approximately 135C. This
pin WILL NOT automatically disable the device. The TEMP pin includes a 12k series resistor.
HS: These pins are internally connected to the thermal slug on the reverse of the package. They should be con-
nected to GND. Neither the heat slug nor these pins should be used to carry high current.
NC: These no-connect pins should be left unconnected.
2. SA53 OPERATION
The SA53 is designed primar-
ily to drive DC brush motors.
However, it can be used for
any application requiring two
high current outputs. The
signal set of the SA53 is de-
signed specifcally to interface
with a DSP or microcontroller.
A typical system block dia-
gram is shown in the fgure
below. Over-temperature,
Short-Circuit and Current
Limit fault signals provide
important feedback to the
system controller which can
safely disable the output driv-
ers in the presence of a fault
condition. High side current
monitors for both phases pro-
vide performance information
which can be used to regulate
or limit torque.
FIGURE 4. SYSTEM DIAGRAM
DC BRUSH
MOTOR
Vs 1
PGND 1
Current
monitor
Signals
1
2
OUT 1
OUT 2
PGND 2
GND
Vs 2
Vs +
GND
SGND
Gate
Control
Control
Logic
Fault
Logic
TEMP
I
LIM
/DIS1
SC
I1
I2
V
DD
PWM
Signals
DIS2
SGND
1t
1b
2t
2b
Microcontroller
or DSC
SA53
SA53U 161
G
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A
G
H
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B
A
The block diagram in Figure 5 illustrates the features of the input and output structures of the SA53. For simplicity,
a single phase is shown.
FIGURE 5. INPUT AND OUTPUT STRUCTURES FOR A SINGLE PHASE
SGND
Gate
Control
Vs
OUT 1
PGND
1t
1b
SC
TEMP
SC
Logic
Temp
Sense
Ref
I1
DIS2
I
LIM
/DIS1
UVLO
I1'
+
_
Lim 2
+
_
Vdd
Lim 1
Current
Sense
12k
12k
12k
12k
Vth
TABLE 2. TRUTH TABLE
1
t
,

2
t
1
b
,

2
b
I
1
,

I
2
I
L
I
M
/
D
I
S
1
D
I
S
2
O
U
T

1
O
U
T

2
Comments
0 0 X X X High-Z Top and Bottom output FETs for that phase are turned off.
0 1 <V
th
0 0 PGND Bottom output FET for that phase is turned on.
1 0 <V
th
0 0 VS Top output FET for that phase is turned on.
1 1 X X X High-Z Both output FETs for that phase are turned off.
X X >V
th
1 X High-Z
Voltage on I1 or I2 has exceeded Vth, which causes I
LIM
/DIS1 to go high.
This internally disables Top and Bottom output FETs for ALL phases.
X X X X 1 High-Z DIS2 pin pulled high, which disables all outputs.
X X X
Pulled
High
X High-Z
Pulling the I
LIM
/DIS1 pin high externally acts as a second disable input,
which disables ALL output FETs.
X X X
Pulled
Low
0
Determined
by PWM
inputs
Pulling the DIS2 pin low externally disables the cycle-by-cycle current limit
function. The state of the outputs is strictly a function of the PWM inputs.
X X X X X High-Z If V
S
is below the UVLO threshold all output FETs will be disabled.
SA53
162 SA53U
2.1 LAYOUT CONSIDERATIONS
Output traces carry signals with very high dV/dt and dI/dt. Proper routing and adequate power supply bypassing
ensures normal operation. Poor routing and bypassing can cause erratic and low effciency operation as well as
ringing at the outputs.
The V
S
supply should be bypassed with a surface mount ceramic capacitor mounted as close as possible to the V
S

pins. Total inductance of the routing from the capacitor to the V
S
and GND pins must be kept to a minimum to pre-
vent noise from contaminating the logic control signals. A low ESR capacitor of at least 25F per ampere of output
current should be placed near the SA53 as well. Capacitor types rated for switching applications are the only types
that should be considered.
The bypassing requirements of the V
DD
supply are less stringent, but still necessary. A 0.1F to 0.47F surface
mount ceramic capacitor (X7R or NPO) connected directly to the V
DD
pin is suffcient.
SGND and PGND pins are connected internally. However, these pins must be connected externally in such a way
that there is no motor current fowing in the logic and signal ground traces as parasitic resistances in the small
signal routing can develop suffcient voltage drops to erroneously trigger input transitions. Alternatively, a ground
plane may be separated into power and logic sections connected by a pair of back to back Schottky diodes. This
isolates noise between signal and power ground traces and prevents high currents from passing between the plane
sections.
Unused area on the top and bottom PCB planes should be flled with solid or hatched copper to minimize inductive
coupling between signals. The copper fll may be left unconnected, although a ground plane is recommended.
2.2 FAULT INDICATIONS
In the case of either an over-temperature or short cir-
cuit fault, the SA53 will take no action to disable the
outputs. Instead, the SC and TEMP signals are pro-
vided to an external controller, where a determination
can be made regarding the appropriate course of ac-
tion. In most cases, the SC pin would be connected
to a FAULT input on the processor, which would im-
mediately disable its PWM outputs. The TEMP fault
does not require such an immediate response, and
would typically be connected to a GPIO, or Keyboard
Interrupt pin of the processor. In this case, the pro-
cessor would recognize the condition as an external
interrupt, which could be processed in software via an Interrupt Service Routine. The processor could optionally
bring all inputs low, or assert a high level to either of the disable inputs on the SA53.
Figure 6 shows an external SR fip-fop which provides a hard wired shutdown of all outputs in response to a fault
indication. An SC or TEMP fault sets the latch, pulling the disable pin high. The processor clears the latched condi-
tion with a GPIO. This circuit can be used in safety critical applications to remove software from the fault-shutdown
loop, or simply to reduce processor overhead.
In applications which may not have available GPIO, the TEMP pin may be externally connected to the adjacent
DIS1 pin. If the device temperature reaches ~135C all outputs will be disabled, de-energizing the motor. The SA53
will re-energize the motor when the device temperature falls below approximately 95C. The TEMP pin hysteresis is
wide to reduce the likelihood of thermal oscillations which can greatly reduce the life of the device.
2.3 UNDER-VOLTAGE LOCKOUT
The undervoltage lockout condition results in the SA53 unilaterally disabling all output FETs until VS is above the
UVLO threshold indicated in the spec table. There is no external signal indicating that an undervoltage lockout
condition is in progress. The SA53 has two V
S
connections: one for phase 1 and another for phase 2. The supply
voltages on these pins need not be the same, but the UVLO will engage if either is below the threshold. Hysteresis
on the UVLO circuit prevents oscillations with typical power supply variations.
FIGURE 6. EXTERNAL FAULT LATCH CIRCUIT
SA53
PROCESSOR
INTERRUPT
GPIO
PWM
SC
DIS2 TEMP
LATCHED FAULT
FAULT RESET
SA53
SA53U 163
G
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B
A
G
H
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C
B
A
2.4 CURRENT SENSE
External power shunt resistors are not required with the SA53. Forward current in each top, Pchannel output FET is
measured and mirrored to the respective current sense output pin, Ia, Ib and Ic. By connecting a resistor between
each current sense pin and a reference, such as ground, a voltage develops across the resistor that is proportional
to the output current for that phase. An ADC can monitor the voltages on these resistors for protection or for closed
loop torque control in some application confgurations. The current sense pins source current from the V
DD
supply.
Headroom required for the current sense circuit is approximately 0.5V. The nominal scale factor for each propor-
tional output current is shown in the typical performance plot on page 4 of this datasheet.
2.5 CYCLE-BY-CYCLE CURRENT LIMIT
In applications where the current in the motor is not
directly controlled, both the average current rating of
the motor and the inrush current must be considered
when selecting a proper amplifer. For example, a 1A
continuous motor might require a drive amplifer that
can deliver well over 10A peak in order to survive the
inrush condition at startup.
Because the output current of each upper output
FET is measured, the SA53 is able to provide a very
robust current limit scheme. This enables the SA53
to safely and easily drive virtually any DC brush mo-
tor through a startup inrush condition. With limited
current, the starting torque and acceleration are also
limited. The plot in Figure 7 shows starting current
and back EMF with and without current limit enabled.
If the voltage of any of the two current sense pins
exceeds the current limit threshold voltage (Vth), all
outputs are disabled. After all current sense pins fall
below the Vth threshold voltage AND the
offending phases top side input goes low,
the output stage will return to an active
state on the rising edge of ANY top side
input command signal (1t or 2t). With most
commutation schemes, the current limit
will reset each pwm cycle. This scheme
regulates the peak current in each phase
during each pwm cycle as illustrated in the
timing diagram below. The ratio of average
to peak current depends on the inductance
of the motor winding, the back EMF de-
veloped in the motor, and the width of the
pulse.
Figure 8 illustrates the current limit trigger
and reset sequence. Current limit engages
and I
LIM
/DIS1 goes high when any current
sense pin exceeds Vth. Notice that the mo-
ment at which the current sense signal ex-
ceeds the Vth threshold is asynchronous
with respect to the input PWM signal. The
difference between the PWM period and
the motor winding L/R time constant will
often result in an audible beat frequency
sometimes called a sub-cycle oscillation.
TIME
NON-LIMITED BACK EMF
LIMITED BACK EMF
LIMITED MOTOR CURRENT
NON-LIMITED MOTOR CURRENT
FIGURE 7. START-UP VOLTAGE AND CURRENT
It INPUT
OUT 1
I1
V
th
I
LIM
/DIS1
FIGURE 8. CURRENT LIMIT WAVEFORMS
SA53
164 SA53U
This oscillation can be seen on the I
LIM
/DIS1 pin waveform in Figure 8. Input signals commanding 0% or 100% duty
cycle may be incompatible with the current limit feature due to the absence of rising edges of 1t and 2t except when
commutating phases. At high RPM, this may result in poor performance. At low RPM, the motor may stall if the cur-
rent limit trips and the motor current reaches zero without a commutation edge which will typically reset the current
limit latch.
The current limit feature may be disabled by tying the I
LIM
/Dis1 pin to GND. The current sense pins will continue to
provide top FET output current information.
Typically, the current sense pins source current into grounded resistors which provide voltages to the current limit
comparators. If instead the current limit resistors are connected to a voltage output DAC, the current limit can be
controlled dynamically from the system controller. This technique essentially reduces the current limit threshold
voltage to (Vth-VDAC). During expected conditions of high torque demand, such as start-up or reversal, the DAC
can adjust the current limit dynamically to allow periods of high current. In normal operation when low current is
expected, the DAC output voltage can increase, reducing the current limit setting to provide more conservative fault
protection.
2.6 EXTERNAL FLYBACK DIODES
External fy-back diodes will offer superior reverse recovery characteris-
tics and lower forward voltage drop than the internal back-body diodes. In
high current applications, external fyback diodes can reduce power dis-
sipation and heating during commutation of the motor current. Reverse
recovery time and capacitance are the most important parameters to
consider when selecting these diodes. Ultra-fast rectifers offer better re-
verse recovery time and Schottky diodes typically have low capacitance.
Individual application requirements will be the guide when determining
the need for these diodes and for selecting the component which is most
suitable.
FIGURE 10. TIMING DIAGRAMS
3. POWER DISSIPATION
The thermally enhanced package of the SA53 allows several options for managing the power dissipated in the
three output stages. Power dissipation in traditional PWM applications is a combination of output power dissipation
and switching losses. Output power dissipation depends on the quadrant of operation and whether external fyback
diodes are used to carry the reverse or commutating currents. Switching losses are dependent on the frequency of
the PWM cycle as described in the typical performance graphs.
TOP INPUT
BOTTOM INPUT
DELAY TIMING
OUTPUT
DISABLE
td(fall) td(dis) td(rise) td(dis) td(dis) td(dis)
FIGURE 9. SCHOTTKY DIODES
OUT 1
OUT 2
V
S
V
S
SA53
SA53
SA53U 165
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A
G
H
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E
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C
B
A
The size and orientation of the heatsink must be
selected to manage the average power dissipation
of the SA53. Applications vary widely and various
thermal techniques are available to match the re-
quired performance. The patent pending mounting
technique shown in Figure 12, with the SA53 invert-
ed and suspended through a cutout in the PCB is
adequate for power dissipation up to 17W with the
HS33, a 1.5 inch long aluminum extrusion with four
fns. In free air, mounting the PCB perpendicular to
the ground, such that the heated air fows upward
along the channels of the fns can provide a total
J A
of less than 14 C/W (9W max average PD).
Mounting the PCB parallel to the ground impedes
the fow of heated air and provides a
J A
of 16.66
C/W (7.5W max average P
D
). In applications in
which higher power dissipation is expected or lower
junction or case temperatures are required, a larger
heatsink or circulated air can signifcantly improve
the performance.
FIGURE 12. HEATSINK TECHNIQUE
PATENT PENDING
4. ORDERING AND PRODUCT STATUS INFORMATION
MODEL TEMPERATURE PACKAGE PRODUCTION STATUS
SA53-IHZ -25 to 85C 64 pin Power QFP (HQ package drawing) Samples Available 1Q09
TOP INPUT
BOTTOM INPUT
OUTPUT
t(fall) t(rise)
20%
80%
FIGURE 11. OUTPUT RESPONSE
SA57
166 SA57U
SA57 SA57A
DESCRIPTION
The SA57 is a fully integrated switching amplifer de-
signed primarily to drive DC brush motors. Two inde-
pendent half bridges provide over 15 amperes peak
output current under microcontroller or DSC control.
Thermal and short circuit monitoring is provided, which
generates fault signals for the microcontroller to take
appropriate action. A block diagram is provided in Fig-
ure 1.
circuitry.
FEATURES
Low cost intelligent switching amplifer
Directly connects to most embedded Micro-
Integrated gate driver logic with dead-time
generation and shoot-through prevention
Wide power supply range (8.5V to 60V)
Over 15A peak output current per phase
5A continuous output current per phase
8A continuous for A-Grade (SA57A)
Independent current sensing for each output
User programmable cycle-by-cycle current
limit protection
Over-current and over-temperature warning
signals
APPLICATIONS
Bidirectional DC brush motors
2 unidirectional DC brush motors
2 independent solenoid actuators
Stepper motors
Figure 1. BLOCK Diagram
Vs 1
P GND 1
Gate
Control
PWM
Signals
Out 1
Out 2
P GND 2
TEMP
GND
Vs 2
V
S
+
I
LIM
/DIS1
SC
DIS2
SGND
P hase 1
P hase 2
Control
Logic
V
DD
I1' I2'
I1'
I2'
Fault
Logic
I1
I2
1t
1b
2t
2b
V
DD
V
DD
Switching Amplifier
SA57 SA57A P r o d u c t I n n o v a t i o n F r o m
OCT 2008
APEX SA57UREVA
SA57
SA57U 167
G
H
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B
A
G
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B
A
SUPPLY VOLTAGE V
S
60 V
SUPPLY VOLTAGE V
DD
5.5 V
DD
+0.5) V
OUTPUT CURRENT, peak, 10ms
2
I
OUT
17 A
POWER DISSIPATION, avg, 25C
2
P
D
100 W
3
T
J
150 C
STG
55 125 C
A
40 125 C
Parameter Test Conditions
2
SA57 SA57A
Units
Min Typ Max Min Typ Max
LOGIC
INPUT LOW 1 * V
INPUT HIGH 1.8 * V
OUTPUT LOW 0.3 * V
OUTPUT HIGH 3.7 * V
OUTPUT CURRENT
(SC, Temp, I
LIM
/DIS1)
50 * mA
POWER SUPPLY
V
S
UVLO 50 60 55 V
V
S
UNDERVOLTAGE
LOCKOUT, (UVLO)
9 * * V
V
DD
4.5 5.5 * * V
SUPPLY CURRENT, V
S
20 kHz (One phase
switching at 50% duty
cycle) , V
S
=50V, V
DD
=5V
25 30 * * mA
SUPPLY CURRENT, V
DD
20 kHz (One phase
cycle) , V
S
=50V, V
DD
=5V
5 6 * * mA
CURRENT LIMIT
CURRENT LIMIT
THRESHOLD (Vth)
3.95 * V
Vth HYSTERESIS 100 * mV
OUTPUT
CURRENT, CONTINUOUS 25C Case Temperature 5 8 A
RISING DELAY, TD (RISE) See Figure 10 270 * ns
FALLING DELAY, TD (FALL) See Figure 10 270 * ns
DISABLE DELAY, TD (DIS) See Figure 10 200 * ns
ENABLE DELAY, TD (DIS) See Figure 10 200 * ns
RISE TIME, T (RISE) See Figure 11 50 * ns
FALL TIME, T (FALL) See Figure 11 50 * ns
SPECIFICATIONS

SA57
168 SA57U
NOTES:
* The specifcation of SA57A is identical to the specifcation for SA57 in applicable column to the left.
C
= 25C).
2
SA57 SA57A
Units
ON RESISTANCE
SOURCING (P-CHANNEL)
5A Load 300 750 300 600 m
ON RESISTANCE
SINKING (N-CHANNEL)
5A Load 250 750 250 600 m
THERMAL
THERMAL WARNING 135 * C
THERMAL WARNING
HYSTERESIS
40 * C
RESISTANCE, junction to
case
Full temperature range 1.25 1.5 * * C/W
TEMPERATURE RANGE,
case
Meets Specifcations -25 85 -40 125 C
Figure 2. 64-Pin QFP, Package Style HQ
SA57
SA57U 169
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
(P-Channel)
0
1
2
3
4
5
FORWARD VOLTAGE (V)
C
U
R
R
E
N
T

(
A
)
0.5 1.5 1.3 1.1 0.9 0.7
(N-Channel)
0
1
2
3
4
5
FORWARD VOLTAGE (V)
C
U
R
R
E
N
T

(
A
)
0.5 1.5 1.3 1.1 0.9 0.7
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
I
OUT
,(A)
R
D
S
(
o
n
)
,
(
)
V
S
=11
V
S
=13
V
S
=15
V
S
>17
10 0 9 8 7 6 5 4 3 2 1
(P-Channel)
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
10
I
OUT
,(A)
R
D
S
(
o
n
)
,
(
)
V
S
=11
V
S
=13
V
S
=15
V
S
=17
V
S
>22
0 9 8 7 6 5 4 3 2 1
(N-Channel)
POWER DERATING
0
20
40
60
80
100
120
CASE TEMPERATURE, T
C
P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
D
SA57
SA57A
-40 120 80 40 0
V
DD
SUPPLY CURRENT
4.5
4.6
4.7
4.8
4.9
5
0 50 100 150 200 250 300
FREQUENCY (kHz)
V
D
D

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
50% DUTY CYCLE; V
S
=50V
V
DD
SUPPLY CURRENT
4
4.5
5
5.5
6
6.5
7
7.5
8
10 20 30 40 50 60
V
S
SUPPLY VOLTAGE (V)
V
D
D

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
FREQUENCY =20kHz
50% DUTY CYCLE
25C
125C
CURRENT SENSE
0.1
1
10
0.01 0.1 1 10
SENSE CURRENT (mA)
L
O
A
D

C
U
R
R
E
N
T

(
A
)
V
S
SUPPLY CURRENT
20
40
60
80
100
120
140
160
180
0 50 100 150 200 250 300
FREQUENCY (kHz)
V
S

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
50% DUTY CYCLE; V
S
=50V
0
V
S
SUPPLY CURRENT
0
5
10
15
20
25
V
S
SUPPLY VOLTAGE (V)
V
S

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
125C
25C
ONE PHASE SWITCHING
FREQUENCY =20kHz
50% DUTY CYCLE
10 20 30 40 50 60
SA57
170 SA57U
Figure 3. External Connections
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
1234567891
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
O
U
T

2
O
U
T

2
N
C
V
S

2
V
S

2
V
S

2
V
S

2
N
C
N
C
N
C
N
C
N
C
P
G
N
D

1
P
G
N
D

1
P
G
N
D

1
P
G
N
D

1
N
C
O
U
T

1
O
U
T

1
O
U
T

1
I
2
N
C
S
C
N
C
S
G
N
D
N
C
I
L
I
M
/
D
I
S
1
N
C
S
G
N
D
N
C
S
G
N
D
N
C
S
G
N
D
N
C
1
b
N
C1
t
N
C
V
D
D
N
C
OUT 2
NC
PGND 2
PGND 2
PGND 2
HS
HS
NC
2b
NC
2t
NC
NC
V
S
1
V
S
1
V
S
1
NC
HS
HS
TEMP
NC
DIS2
NC
I1
29,30,31 V
S
(phase 1) Power High Voltage Supply (8.5-60V) supplies phase 1 only
55,56,57 PGND (phase 2) Power High Current GND Return Path for Power Output 2
7 I
LIM
5,9,11,13 SGND Power Analog and digital GND internally connected to PGND
19 V
DD
SA57
SA57U 171
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
46,47,48,49 V
S
(phase 2) Power High Voltage Supply phase 2
37,38,39,40 PGND (phase 1) Power High Current GND Return Path for Power Outputs 1&2
2,4,6,8,10,
12,14,16,18,
20,22,24,28,
32,36,41,42,
43,44,45,50,
54,60,62,64
1.2 PIN DESCRIPTIONS
V
S
: Supply voltage for the output transistors. These pins require decoupling (1F capacitor with good high fre-
quency characteristics is recommended) to the PGND pins. The decoupling capacitor should be located as close
to the V
S
S
pins to handle load current
peaks and potential motor regeneration. Refer to the applications section of this datasheet for additional discussion
regarding bypass capacitor selection. Note that Vs pins 29-31 carry only the phase 1 supply current. Pins 46-49
carry supply current for phase2. Phase 1 may be operated at a different supply voltage from phase 2. Only the B &
C supply pins (46-49) are monitored for undervoltage conditions.
OUT 1, OUT 2: These pins are the power output connections to the load. NOTE: When driving an inductive load, it
is recommended that two Schottky diodes with good switching characteristics (fast t
RR
specs) be connected to each
pin so that they are in parallel with the parasitic back-body diodes of the output FETs. (See Section 2.6)
through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See section 2.1 of
this datasheet for more details.
mands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approximately
200ns during switching transitions but in high current applications, short glitches may appear on the SC pin. A high
state on the SC output will not automatically disable the device. The SC pin includes an internal 12k series resistor.
1b, 2b: These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower N-
channel output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low turns the low side
N-channel FET off. If 1b or 2b is high at the same time that a corresponding 1t or 2t input is high, protection circuitry
will turn off both FETs in order to prevent shoot-through current on that output phase. Protection circuitry also in-
cludes a dead-time generator, which inserts dead time in the outputs in the case of simultaneous switching of the
top and bottom input signals.
1t, 2t: These Schmitt triggered logic level inputs are responsible for turning the associated top side, or upper P-
channel FET outputs on and off. Logic high turns the top P-channel FET on, and a logic low turns the top P-channel
FET off.
I1, I2: Current sense pins. The SA57 supplies a positive current to these pins which is proportional to the current
fowing through the top side P-channel FET for that phase. Commutating currents fowing through the back-body
diode of the P-channel FET or through external Schottky diodes are not registered on the current sense pins. Nor do
currents fowing through the low side N-channel FET, in either direction, register at the current sense pins. A resistor
connected from a current sense pin to SGND creates a voltage signal representation of the phase current that can
be monitored with ADC inputs of a processor or external circuitry.
The current sense pins are also internally compared with the current limit threshold voltage reference, Vth. If the
voltage on any current sense pin exceeds Vth, the cycle by cycle current limit circuit engages. Details of this func-
tionality are described in the applications section of this datasheet.
SA57
172 SA57U
I
LIM
1 and OUT 2 in a high impedance state. This pin is also connected internally to the output of the current limit latch
through a 12k resistor and can be monitored to observe the function of the cycle-by-cycle current limit feature.
Pulling this pin to a logic low effectively disables the cycle-by-cycle current limit feature.
DD
is referenced to this pin. PGND is internally connected to GND through a resistance of a few ohms,. However, it is
highly recommended to connect the GND pin to the PGND pins externally as close to the device as possible. Failure
do to this may result in oscillations on the output pins during rising or falling edges.
V
DD
DIS2: The DIS2 pin is a Schmitt triggered logic level input that places OUT 1 and OUT 2 in a high impedance state
when pulled high. DIS2 has an internal 12k pull-down resistor and may therefore be left unconnected.
2. SA57 OPERATION
The SA57 is designed pri-
marily to drive DC brush
motors. However, it can be
used for any application
requiring two high current
outputs. The signal set of
the SA57 is designed spe-
cifcally to interface with a
DSP or microcontroller. A
typical system block dia-
gram is shown in the fgure
below. Over-temperature,
Short-Circuit and Current
Limit fault signals provide
important feedback to the
system controller which
can safely disable the
output drivers in the pres-
ence of a fault condition.
High side current monitors
for both phases provide
performance information
which can be used to regu-
late or limit torque.
DC BRUSH
MOTOR
Vs 1
PGND 1
Current
monitor
Signals
1
2
OUT 1
OUT 2
PGND 2
GND
Vs 2
Vs +
GND
SGND
Gate
Control
Control
Logic
Fault
Logic
TEMP
I
LIM
/DIS1
SC
I1
I2
V
DD
PWM
Signals
DIS2
SGND
1t
1b
2t
2b
Microcontroller
or DSC
Figure 4. System Diagram
SA57
SA57U 173
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SGND
Gate
Control
Vs
OUT 1
PGND
1t
1b
SC
TEMP
SC
Logic
Temp
Sense
Ref
I1
DIS2
I
LIM
/DIS1
UVLO
I1'
+
_
Lim 2
+
_
Vdd
Lim 1
Current
Sense
12k
12k
12k
12k
Vth
1
t
,

2
t
1
b
,

2
b
I
1
,

I
2
I
L
I
M
/
D
I
S
1
D
I
S
2
O
U
T

1
O
U
T

2
Comments
0 1 <V
th
1 0 <V
th
X X >V
th
1 X High-Z
Voltage on I1 or I2 has exceeded Vth, which causes I
LIM
/DIS1 to go high.
X X X
Pulled
High
X High-Z
Pulling the I
LIM
X X X
Pulled
Low
0
Determined
by PWM
inputs
S
Figure 5. Input and output structures for a single phase
SA57
174 SA57U
The V
S
S

S
that should be considered.
DD
DD
pin is suffcient.
sections.
In the case of either an over-temperature or short circuit fault, the SA57 will take no action to disable the outputs.
Instead, the SC and TEMP signals are provided to an external controller, where a determination can be made re-
garding the appropriate course of action. In most cases, the SC pin would be connected to a FAULT input on the
processor, which would immediately disable its PWM outputs. The TEMP fault does not require such an immediate
response, and would typically be connected to a GPIO, or Keyboard Interrupt pin of the processor. In this case,
the processor would recognize the condition as an external interrupt, which could be processed in software via an
Interrupt Service Routine. The processor could optionally bring all inputs low, or assert a high level to either of the
disable inputs on the SA57.
Figure 6 shows an external SR fip-fop which pro-
vides a hard wired shutdown of all outputs in re-
sponse to a fault indication. An SC or TEMP fault sets
the latch, pulling the disable pin high. The processor
clears the latched condition with a GPIO. This circuit
can be used in safety critical applications to remove
software from the fault-shutdown loop, or simply to
reduce processor overhead.
In applications which may not have available GPIO,
the TEMP pin may be externally connected to the
adjacent DIS1 pin. If the device temperature reaches
~135C all outputs will be disabled, de-energizing the
motor. The SA57 will re-energize the motor when
the device temperature falls below approximately 95C. The TEMP pin hysteresis is wide to reduce the likelihood
of thermal oscillations which can greatly reduce the life of the device.
The undervoltage lockout condition results in the SA57 unilaterally disabling all output FETs until V
S
is above the
UVLO threshold indicated in the spec table. There is no external signal indicating that an undervoltage lockout
S
connections: one for phase 1 and another for phase 2. The supply
voltages on these pins need not be the same, but the UVLO will engage if either is below the threshold. Hysteresis
on the UVLO circuit prevents oscillations with typical power supply variations.
Figure 6. External Fault Latch Circuit
SA57
PROCESSOR
INTERRUPT
GPIO
PWM
SC
DIS2 TEMP
LATCHED FAULT
FAULT RESET
SA57
SA57U 175
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
2.4 CURRENT SENSE
External power shunt resistors are not required
with the SA57. Forward current in each top, P-
channel output FET is measured and mirrored to
the respective current sense output pin, I1 and
I2. By connecting a resistor between each cur-
rent sense pin and a reference, such as ground,
a voltage develops across the resistor that is pro-
portional to the output current for that phase. An
ADC can monitor the voltages on these resistors
for protection or for closed loop torque control
in some application confgurations. The current
sense pins source current from the V
DD
supply.
Headroom required for the current sense circuit is
approximately 0.5V. The nominal scale factor for
each proportional output current is shown in the
typical performance plot on page 4 of this data-
sheet.
In applications where the current in the motor is
not directly controlled, both the average current rating of the motor and the inrush current must be considered when
selecting a proper amplifer. For example, a 1A continuous motor might require a drive amplifer that can deliver well
over 10A peak in order to survive the inrush condition at start-up.
Because the output current of each upper output FET is measured, the SA57 is able to provide a very robust current
limit scheme. This enables the SA57 to safely and easily drive virtually any DC brush motor through a start-up inrush
condition. With limited current, the starting torque and acceleration are also limited. The plot in Figure 7 shows
starting current and back EMF with and without current limit enabled.
If the voltage of any of the two current sense pins exceeds the current limit threshold voltage (Vth), all outputs
are disabled. After all current sense pins
fall below the Vth threshold voltage AND
the offending phases top side input goes
low, the output stage will return to an active
state on the rising edge of ANY top side
input command signal (1t or 2t). With most
commutation schemes, the current limit
will reset each PWM cycle. This scheme
regulates the peak current in each phase
during each PWM cycle as illustrated in
the timing diagram below. The ratio of
average to peak current depends on the
inductance of the motor winding, the back
EMF developed in the motor, and the width
of the pulse.
Figure 8 illustrates the current limit trigger
and reset sequence. Current limit engages
and I
LIM
/DIS1 goes high when any current
sense pin exceeds Vth. Notice that the mo-
ment at which the current sense signal ex-
ceeds the Vth threshold is asynchronous
with respect to the input PWM signal. The
difference between the PWM period and
the motor winding L/R time constant will
TIME
LIMITED BACK EMF
Figure 7. Start-up Voltage and Current
It INPUT
OUT 1
I1
V
th
I
LIM
/DIS1
Figure 8. Current Limit Waveforms
SA57
176 SA57U
often result in an audible beat frequency sometimes called a sub-cycle oscillation. This oscillation can be seen on
the I
LIM
/DIS1 pin waveform in Figure 8.
Input signals commanding 0% or 100% duty cycle may be incompatible with the current limit feature due to the
absence of rising edges of 1t and 2t. At high RPM, this may result in poor performance. At low RPM, the motor may
stall if the current limit trips and the motor current reaches zero without a commutation edge which will typically reset
the current limit latch.
LIM
/DIS1 pin to GND. The current sense pins will continue to
can adjust the current limit dynamically to allow periods of high current. In normal operation when low current is
expected, the DAC output voltage can increase, reducing the current limit setting to provide more conservative fault
protection.
External fy-back diodes will offer superior reverse recovery characteristics and
lower forward voltage drop than the internal back-body diodes. In high current
applications, external fyback diodes can reduce power dissipation and heat-
ing during commutation of the motor current. Reverse recovery time and ca-
pacitance are the most important parameters to consider when selecting these
diodes. Ultra-fast rectifers offer better reverse recovery time and Schottky
diodes typically have low capacitance. Individual application requirements will
be the guide when determining the need for these diodes and for selecting the
component which is most suitable.
The thermally enhanced package of the SA57 allows several options for managing the power dissipated in the two
output stages. Power dissipation in traditional PWM applications is a combination of output power dissipation and
switching losses. Output power dissipation depends on the quadrant of operation and whether external fyback di-
odes are used to carry the reverse or commutating currents. Switching losses are dependent on the frequency of
the PWM cycle as described in the typical performance graphs.
The size and orientation of the heatsink must be selected to manage the average power dissipation of the SA57.
Applications vary widely and various thermal techniques are available to match the required performance. The pat-
Figure 9. Schottky Diodes
OUT 1
OUT 2
V
S
V
S
SA57
TOP INPUT
BOTTOM INPUT
DELAY TIMING
OUTPUT
DISABLE
Figure 10. Timing Diagrams
SA57
SA57U 177
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
ent pending mounting technique shown in Figure
12, with the SA57 inverted and suspended through
a cutout in the PCB is adequate for power dissipa-
tion up to 17W with the HS33, a 1.5 inch long alu-
minum extrusion with four fns. In free air, mount-
ing the PCB perpendicular to the ground, such that
the heated air fows upward along the channels of
the fns can provide a total
J A
of less than 14 C/W
(9W max average P
D
). Mounting the PCB parallel
to the ground impedes the fow of heated air and
provides a
J A
of 16.66 C/W (7.5W max average
P
D
). In applications in which higher power dissipa-
tion is expected or lower junction or case tempera-
tures are required, a larger heatsink or circulated
air can signifcantly improve the performance.
SA57-IHZ -25 to 85C 64 pin Power QFP (HQ package drawing) Samples Available
SA57A-FHZ -40 to +125C 64 pin Power QFP (HQ package drawing) Samples Available
TOP INPUT
BOTTOM INPUT
OUTPUT
t(fall) t(rise)
20%
80%
Figure 11. Output Response
Figure 12. Heatsink Technique
PATENT PENDING
SA60
178 SA60U
SA60
FEATURES
LOW COST COMPLETE H-BRIDGE
SELF-CONTAINED SMART LOWSIDE/
HIGHSIDE DRIVE CIRCUITRY
WIDE SUPPLY RANGE: UP TO 80V
ISOLATED CASE ALLOWS DIRECT
HEATSINKING
FOUR QUADRANT OPERATION, TORQUE
CONTROL CAPABILITY
INTERNAL/PROGRAMMABLE PWM
FREQUENCY GENERATION
APPLICATIONS
REACTIVE LOADS
H-Bridge Motor Driver/Amplifiers
H-Bridge
Drive
555
10
11
9
8
12 1
7
6
3
4
2
2.58K
49K
2 6
7 1
4 8
+V
s
B OUT
A OUT
I
sense
A
I
sense
B
POWER
GND
DISABLE
ANALOG IN
Cf/PWM IN
ANALOG GND
V
cc
DESCRIPTION
The SA60 is a pulse width modulation amplifer that
can supply 10A continuous current to the load. The full
bridge amplifer can be operated over a wide range
of supply voltages. All of the drive/control circuitry for
the lowside and highside switches are internal to the
hybrid. The PWM circuitry is internal as well, leaving
the user to only provide an analog signal for the motor
speed/direction, or audio signal for switchmode audio
amplifcation. The internal PWM frequency can be pro-
grammed by an external integrator capacitor. Alterna-
tively, the user may provide an external TTL-compatible
PWM signal for simultaneous amplitude and direction
control for four quadrant mode.
BLOCK DIAGRAM
JUN 2009
APEX SA60UREVL
SA60
SA60U 179
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
The exposed substrate contains beryllia (BeO). Do not crush, machine, or subject to temperatures
in excess of 850C to avoid generating toxic fumes.
1
Min Typ Max Units
INPUT
ANALOG INPUT VOLTAGES V
CC
= 12V
A,B OUT = 50% Duty Cycle 1/2 V
CC
VDC
A OUT = 100% Duty Cycle High 1/3 V
CC
VDC
B OUT = 100% Duty Cycle High 2/3 V
CC
VDC
PWM INPUT
PWM PULSE LOW VOLTAGE 0 0.8 VDC
PWM PULSE HIGH VOLTAGE 2.7 5.0 VDC
PWM FREQUENCY 45 250 KHz
DISABLE ON 2.7 V
CC
VDC
DISABLE OFF 0 0.8 VDC
OUTPUT
V
DS
(ON) VOLTAGE, each MOSFET I
DS
=10A 1.7 2.5 VDC
TOTAL R
ON
, both MOSFETs 0.45
EFFICIENCY, 10A OUTPUT +V
S
=80A 91 %
CURRENT, peak t =100 msec 15 A
SWITCHING FREQUENCY C
F
= 270pF 45 KHz
DEAD TIME 90 nS
POWER SUPPLY
+V
S
VOLTAGE (Note 4) +V
S
Current = Load Current 80 VDC
V
CC
VOLTAGE 9.5 12 15 VDC
V
CC
CURRENT V
CC
= 12VDC 28 36 mA
+V
S
CURRENT Switching, no load, V
S
= 50V 5 mA
SUPPLY VOLTAGE, +V
S
(Note 4) 80 V
OUTPUT CURRENT, peak 15 A
LOGIC SUPPLY VOLTAGE, V
CC
16 V
POWER DISSIPATION, internal (Note 3) 156 W
TEMPERATURE, pin solder, 10s max. 260 C
SPECIFICATIONS
CAUTION
SA60
180 SA60U
NOTES: 1. (All Min/Max characteristics and specifcations are guaranteed over the Specifed Operating Condi-
C
= 25C, V
CC
= 12VDC).
power dissipation to achieve high MTTF.
3. Each of the two active output transistors can dissipate 78W.
4. Derate to 70V below T
C
= +25C.
1
Min Typ Max Units
THERMAL (Note 3)
RESISTANCE, junction to case Full temperature range,
for each transistor
1.6 C/W
TEMPERATURE RANGE, case -25 +85 C
10 100 1000
10
100
1000
PWM FREQ VS EXT INT CAP
C
L
O
C
K

F
R
E
Q
U
E
N
C
Y
,

F
s
w

(
K
H
z
)
0 12 15
0
5
20
25
30
35
TOTAL VOLTAGE DROP
10
15
3 6 9
V
O
L
T
A
G
E

D
R
O
P
,

V
EXTERNAL INTEGRATION CAP, C (pF)
OUTPUT CURRENT, A
0.4
1.8
1.6
1.4
1.2
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S

C
U
R
R
E
N
T

(
X
)
0.8
0.6
1
Vs, (V)
SWITCHING FREQUENCY, Fsw (KHz)
10 70 20 30 40 50 60
0 50 100 150 200 250 9 16 10 11 12 13 14 15
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

(
W
)
0.6 0.8 1.4
SOURCE TO DRAIN VOLTAGE
0.1
REVERSE DIODES
10
1
Vs QUIESCENT VS SWITCH FREQ
V
s

Q
U
I
E
S

C
U
R
R
E
N
T

I
q

(
m
A
)
POWER DERATING
0
20
80
60
40
1.2 1.8 1.6
1
40
60
80
100
120
140
160
F
L
Y
B
A
C
K

C
U
R
R
E
N
T

I
S
D
(
A
)
75
CASE TEMPERATURE, T
C
(C)
100 0 25 50 125
Vcc VOLTAGE (V)
0.7
0.8
0.9
1
1.2
1.1
1.4
1.3
Vcc QUIESCENT VS VOLTAGE
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S

C
U
R
R
E
N
T
,

(
X
)
1/6 5/6
ANALOG INPUT AS PROPORTION OF Vcc
0

D
U
T
Y

C
Y
C
L
E

(
%
)
80
100
1/3
20
40
60
1/2 2/3
Cf (pF) = (1.44E7/Fsw)50
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T
,

I
q

(
X
)
Vcc I
Q
VS SWITCH FREQ
SWITCHING FREQUENCY, Fsw (KHz)
1.6
1.5
1.4
1.3
1.2
1.1
1
25 50 75 100 125
A OUT B OUT
T
C
= 110C
T
C
= 85C
T
C
= 60C
T
C
= 35C
0.9
0.8
0.6
0.2
80
25C
85C
EACH OUTPUT
TRANSISTOR
20
0
SA60
SA60U 181
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
TYPICAL APPLICATION
A wide variety of loads can be driven in either the voltage
mode or the current mode. The most common applications
use three external blocks: a low pass flter converting pulse
width data to an analog output, a difference amplifer to
monitor voltage or current and an error amplifer. Filter in-
ductors must be suitable for square waves at the switching
frequency (laminated steel is generally not acceptable). Fil-
ter capacitors must be low ESR and rated for the expected
ripple current. A difference amplifer with gain of less than
one translates the differential output voltage to a single feedback voltage. Dashed line connections and a higher
gain difference amplifer would be used for current control. The error amplifer integrates the difference between the
input and feedback voltages to close the loop.
GENERAL
Please read Application Note 30 on "PWM Basics". Refer to Application Note 1 "General Operating Considerations"
for helpful information regarding power supplies, heat sinking and mounting. Visit www.Cirrus.com for design tools
that help automate pwm flter design; heat sink selection; Apex Precision Powers complete Application Notes li-
brary; Technical Seminar Workbook; and Evaluation Kits.
PWM OSCILLATOR INTERNAL OR EXTERNAL
The SA60 contains an internal PWM oscillator whose frequency is determined by an external capacitor connected
between pin 1 and pin 2. Maximum frequency is 125 kHz. The user may also disregard the internal PWM oscillator
and supply the SA60 with an external TTL pulse generator up to 250KHZ.
PIN DESCRIPTION
V
CC
- is the low voltage supply for powering internal logic and drivers for the lowside and highside MOSFETS. The
supplies for the highside drivers are derived from this voltage.
V
S
- is the higher voltage H-bridge supply. The MOSFETS obtain the output current from this supply pin. The voltage
on this pin is limited to +80V by the drive IC. The MOSFETS are rated at 100 volts.
ISENSE A & B - These are tied to power gnd directly or through sense resistors.
ANALOG GND - is the reference for the internal PWM oscillator. Connect this pin to pin 6. Connect low side of Vcc
supply and any other supply used to generate analog input signals to ANALOG GND.
ANALOG INPUT - is an analog input for controlling the PWM pulse width of the bridge. A voltage higher than Vcc/2
will produce greater than 50% duty cycle pulses out of B OUT. A voltage lower than Vcc/2 will produce greater
than 50% duty cycle pulses out of A OUT. If using in the digital mode, bias this point at 1/2 the logic high level.
DISABLE - Is the connection for disabling all 4 output switches. DISABLE high overrides all other inputs. When
taken low, everything functions normally. An internal pullup to Vcc will keep DISABLE high if pin left open.
1 2 3 4 5 6 7 8 9 10
ANALOG
GND
CF
NC Vcc
+Vs
ANALOG
INPUT
POWER
GND
11 12
DISABLE
ISENSE A
A OUT B OUT
ISENSE B
PWM
INPUT
* *
* *
Required RC network. See paragraph
on transient shutdown.
* Protection diodes are recommended for
applications where +Vs exceeds 50V.

2
4
12
8
9
11
SA60
LOAD
3
12-pin Power SIP
PACKAGE
STYLE DP
Formed Leads Available
See package style EE
SA60
182 SA60U
PWM INPUT - Is the TTL compatible digital input for controlling the PWM pulse width of the bridge. A duty cycle
greater than 50% will produce greater than 50% duty cycle pulses out of the A out. A duty cycle less than 50%
will produce greater than 50% duty cycle from the B out. For analog inputs, the integration capacitor for the
internal clock must be connected between this pin and analog ground. The internal switching frequency is pro-
grammable up to 125 kHz by selection of the integration capacitor. The formula is:
BYPASSING
Adequate bypassing of the power supplies is required for proper operation. Failure to do so can cause erratic and
low effciency operation as well as excessive ringing at the outputs. The Vs supply should be bypassed with at
least a 1F ceramic capacitor in parallel with another low ESR capacitor of at least 10F per amp of output current.
Capacitor types rated for switching applications are the only types that should be considered. The 1F ceramic
capacitor must be physically connected directly to the Vs and POWER GND pins. Even one inch of lead length will
cause excessive ringing at the outputs. This is due to the very fast switching times and the inductance of the lead
connection. The bypassing requirements of the Vcc supply are less stringent, but still necessary. A .1F to .47F
ceramic capacitor connected directly to the Vcc and ANALOG GND pins will suffce.
PCB LAYOUT
The designer needs to appreciate that the SA60 combines in one circuit both high speed high power switching and
low level analog signals. Certain layout rules of thumb must be considered when a circuit board layout is designed
using the SA60:
1. Bypassing of the power supplies is critical. Capacitors must be connected directly to the power supply pins with
very short lead lengths (well under 1 inch). Ceramic chip capacitors are best.
2. Connect ANALOG GND to POWER GND with a conductor having no intermediate connections. Connect all Vs
power supply, flter and load related ground connections to POWER GND keeping these conductors separate
until reaching pin 6. Connect all Vcc power supply and input signal related ground connections to ANALOG
GND keeping conductors separate until reaching pin 1. Do not allow ground loops to form by making additional
ground connections at the low side of the physical power supplies. If ground plane is used do not allow more
than 1mA to fow through it.
3. Beware of capacitive coupling between output connections and signal inputs through the parasitic capacitance
between layers in multilayer PCB designs.
4. Do not run small signal traces between the pins of the output section (pins 8-12).
CURRENT SENSE
There are two load current sensing pins, I SENSE A and I SENSE B. The two pins can be shorted to POWER GND
in the voltage mode connection but both must be used in the current mode connection. It is recommended that R
SENSE resistors be non-inductive. Load current fows in the I SENSE pins. The SA60 has no internal current limit.
TRANSIENT SUPPRESSION
An RC network of a 100 pF Capacitor and a one ohm resistor is required as shown in the external connection dia-
gram on page 1. This network assures proper operation under various loads. Minimal power is dissipated in the
resistor.
50 C
F
(pF) =
1.44 x10
Fsw
( )
7
SA303
SA303U 183
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SA303
DESCRIPTION
The SA303 is a fully integrated switching amplifer
designed primarily to drive three-phase Brushless
DC (BLDC) motors. Three independent half bridges
provide over 10 amperes peak output current under
microcontroller or DSC control. Thermal and short cir-
cuit monitoring is provided, which generates fault sig-
nals for the microcontroller to take appropriate action.
A block diagram is provided in Figure 1.
circuitry.
FEATURES
Low Cost 3 Phase Intelligent Switching
Amplifer
Directly Connects to Most Embedded Micro-
Integrated Gate Driver Logic with Dead-Time
Generation and Shoot-through Prevention
Wide Power Supply Range (8.5V To 60V)
Over 10A Peak Output Current per Phase
3A Continuous Output Current per Phase
Independent Current Sensing for each Output
User Programmable Cycle-by-cycle Current
Limit Protection
Over-Current and Over-Temperature Warning
Signals
APPLICATIONS
3 phase brushless DC motors
Multiple DC brush motors
3 Phase Switching Amplifier
Figure 1. BLOCK Diagram
Vs (phase A)
P GND(A&B)
Gate
Control
PWM
Signals
A
B
C
Out A
Out B
Out C
P GND(C)
TEMP
GND
Vs (phase B&C)
V
S
+
I
LIM
/DIS1
SC
DIS2
SGND
P hase A
P hase C
P hase B
Control
Logic
V
DD
Ia' Ib' Ic'
Ia'
Ib'
Ic'
Fault
Logic
Ia
Ic
Ib
At
Ab
Bt
Bb
Ct
Cb
V
DD
V
DD
V
DD
MAY 2009
APEX SA303UREVA
SA303
184 SA303U
SUPPLY VOLTAGE V
S
60 V
SUPPLY VOLTAGE V
DD
5.5 V
DD
+0.5) V
OUTPUT CURRENT, peak, 10ms (Note 2) I
OUT
10 A
POWER DISSIPATION, avg, 25C (Note 2) P
D
100 W
TEMPERATURE, solder, 10sec T
S
260 C
TEMPERATURE, junction (Note 2) T
J
150 C
STG
55 125 C
A
40 125 C
LOGIC
INPUT LOW 1 V
INPUT HIGH 1.8 V
OUTPUT LOW 0.3 V
OUTPUT HIGH 3.7 V
OUTPUT CURRENT (SC, Temp, I
LIM
/DIS1) 50 mA
POWER SUPPLY
V
S
UVLO 50 60 V
V
S
UNDERVOLTAGE LOCKOUT, (UVLO) 8.3 V
V
DD
4.5 5.5 V
SUPPLY CURRENT, V
S
50% duty cycle) , V
S
=50V, V
DD
=5V
25 30 mA
SUPPLY CURRENT, V
DD
50% duty cycle) , V
S
=50V, V
DD
=5V
5 6 mA
CURRENT LIMIT
CURRENT LIMIT THRESHOLD (Vth) 3.75 V
Vth HYSTERESIS 100 mV
OUTPUT
CURRENT, CONTINUOUS 25C Case Temperature 3 A
RISING DELAY, TD(RISE) See Figure 10 270 ns
FALLING DELAY, TD(FALL) See Figure 10 270 ns
DISABLE DELAY, TD(DIS) See Figure 10 200 ns
ENABLE DELAY, TD(DIS) See Figure 11 200 ns
RISE TIME, T(RISE) See Figure 11 50 ns
FALL TIME, T(FALL) 50 ns
ON RESISTANCE SOURCING (P-CHANNEL) 3A Load 400 m
ON RESISTANCE
SINKING (N-CHANNEL)
3A Load 400 m
SPECIFICATIONS
SA303
SA303U 185
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
NOTES:
C
= 25C).
THERMAL
THERMAL WARNING 135 C
THERMAL WARNING HYSTERESIS 40 C/W
RESISTANCE, junction to case Full temperature range 1.25 1.5 C/W
TEMPERATURE RANGE, case Meets Specifcations -40 85 C
SA303
186 SA303U
(P-Channel)
0
1
2
3
4
5
FORWARD VOLTAGE (V)
C
U
R
R
E
N
T

(
A
)
0.5 1.5 1.3 1.1 0.9 0.7
(N-Channel)
0
1
2
3
4
5
FORWARD VOLTAGE (V)
C
U
R
R
E
N
T

(
A
)
0.5 1.5 1.3 1.1 0.9 0.7
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
I
OUT
,(A)
R
D
S
(
o
n
)
,
(
)
V
S
=11
V
S
=13
V
S
=15
V
S
>17
10 0 9 8 7 6 5 4 3 2 1
(P-Channel)
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
10
I
OUT
,(A)
R
D
S
(
o
n
)
,
(
)
V
S
=11
V
S
=13
V
S
=15
V
S
=17
V
S
>22
0 9 8 7 6 5 4 3 2 1
(N-Channel)
POWER DERATING
0
20
40
60
80
100
120
CASE TEMPERATURE, T
C
P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
D
-40 120 80 40 0
V
DD
SUPPLY CURRENT
4.5
4.6
4.7
4.8
4.9
5
0 50 100 150 200 250 300
FREQUENCY (kHz)
V
D
D

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
50% DUTY CYCLE; V
S
=50V
V
DD
SUPPLY CURRENT
4
4.5
5
5.5
6
6.5
7
7.5
8
10 20 30 40 50 60
V
S
SUPPLY VOLTAGE (V)
V
D
D

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
FREQUENCY =20kHz
50% DUTY CYCLE
25C
125C
CURRENT SENSE
0.1
1
10
0.01 0.1 1 10
SENSE CURRENT (mA)
L
O
A
D

C
U
R
R
E
N
T

(
A
)
V
S
SUPPLY CURRENT
20
40
60
80
100
120
140
160
180
0 50 100 150 200 250 300
FREQUENCY (kHz)
V
S

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
50% DUTY CYCLE; V
S
=50V
0
V
S
SUPPLY CURRENT
0
5
10
15
20
25
V
S
SUPPLY VOLTAGE (V)
V
S

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
125C
25C
ONE PHASE SWITCHING
FREQUENCY =20kHz
50% DUTY CYCLE
10 20 30 40 50 60
SA303
SA303U 187
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
1234567891
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
O
U
T

C
O
U
T

C
N
C
V
S

B

&

C
V
S

B

&

C
V
S

B

&

C
V
S

B

&

C
N
C
O
U
T

B
O
U
T

B
O
U
T

B
N
C
P
G
N
D

A

&

B
P
G
N
D

A

&

B
P
G
N
D

A

&

B
P
G
N
D

A

&

B
N
C
O
U
T

A
O
U
T

A
O
U
T

A
I
c
N
C
S
C
N
CI
b
N
C
I
L
I
M
/
D
I
S
1
N
C
S
G
N
D
N
C
B
t
N
C
B
b
N
C
A
b
N
C
A
t
N
C
V
D
D
N
C
OUT C
NC
PGND C
PGND C
PGND C
HS
HS
NC
Cb
NC
Ct
NC
NC
V
S
A
V
S
A
V
S
A
NC
HS
HS
TEMP
NC
DIS2
NC
Ia
29,30,31 V
S
(phase A) Power High Voltage Supply (8.5-60V) supplies phase A only
51,52,53 OUT C Power Output Half Bridge C Power Output
55,56,57 PGND (phase C) Power High Current GND Return Path for Power Output C
61 Cb Logic Input Logic high commands C phase lower FET to turn on
63 Ct Logic Input Logic high commands C phase upper FET to turn on
1 Ic Analog Output Phase C current sense output
5 Ib Analog Output Phase B current sense output
7 I
LIM
Table 1. Pin Descriptions
SA303
188 SA303U
9 SGND Power Analog and digital GND internally connected to PGND
11 Bt Logic Input Logic high commands B phase upper FET to turn on
13 Bb Logic Input Logic high commands B phase lower FET to turn on
15 Ab Logic Input Logic high commands A phase lower FET to turn on
17 At Logic Input Logic high commands A phase upper FET to turn on
19 V
DD
21 Ia Analog Output Phase A current sense output
42,43,44 OUT B Power Output Half Bridge B Power Output
46,47,48,49 V
S
(phase B&C) Power High Voltage Supply phase B&C
33,34,35 OUT A Power Output Half Bridge A Power Output
37,38,39,40 PGND (phase A&B) Power High Current GND Return Path for Power Outputs A&B
2,4,6,8,10,
12,14,16,18,
20,22,24,28,
32,36,41,45,
50,54,60,62,
64
V
S
: Supply voltage for the output transistors. These pins require decoupling (1F capacitor with good high frequen-
cy characteristics is recommended) to the PGND pins. The decoupling capacitor should be located as close to
the V
S
S
pins to handle load cur-
rent peaks and potential motor regeneration. Refer to the applications section of this datasheet for additional
discussion regarding bypass capacitor selection. Note that V
S
pins 29-31 carry only the phase A supply current.
Pins 46-49 carry supply current for phases B & C. Phase A may be operated at a different supply voltage from
phases B & C. Both V
S
voltages are monitored for undervoltage conditions.
OUT A, OUT B, OUT C: These pins are the power output connections to the load. NOTE: When driving an induc-
tive load, it is recommended that two Schottky diodes with good switching characteristics (fast t
RR
specs) be
connected to each pin so that they are in parallel with the parasitic back-body diodes of the output FETs. (See
Section 2.6)
through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See section
2.1 of this datasheet for more details.
mands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approxi-
mately 200ns during switching transitions but in high current applications, short glitches may appear on the
SC pin. A high state on the SC output will not automatically disable the device. The SC pin includes an internal
12k series resistor.
Ab, Bb, Cb: These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower
N-channel output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low turns the low
side N-channel FET off. If Ab, Bb, or Cb is high at the same time that a corresponding At, Bt, or Ct input is high,
protection circuitry will turn off both FETs in order to prevent shoot-through on that output phase. Protection
circuitry also includes a dead-time generator, which inserts dead time in the outputs in the case of simultane-
ous switching of the top and bottom input signals.
TABLE 1. PIN DESCRIPTIONS - Cont.
SA303
SA303U 189
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
At, Bt, Ct: These Schmitt triggered logic level inputs are responsible for turning the associated top side, or upper
P-channel FET outputs on and off. Logic high turns the top P-channel FET on, and a logic low turns the top
P-channel FET off.
Ia, Ib, Ic: Current sense pins. The SA303 supplies a positive current to these pins which is proportional to the cur-
rent fowing through the top side P-channel FET for that phase. Commutating currents fowing through the
backbody diode of the P-channel FET or through external Schottky diodes are not registered on the current
sense pins. Nor do currents fowing through the low side N-channel FET, in either direction, register at the cur-
rent sense pins. A resistor connected from a current sense pin to SGND creates a voltage signal representa-
tion of the phase current that can be monitored with ADC inputs of a processor or external circuitry.
The current sense pins are also internally compared with the current limit threshold voltage reference, Vth. If
the voltage on any current sense pin exceeds Vth, the cycle by cycle current limit circuit engages. Details of
this functionality are described in the applications section of this datasheet.
I
LIM
/DIS1: This pin is directly connected to the disable circuitry of the SA303. Pulling this pin to logic high places
OUT A, OUT B, and OUT C in a high impedance state. This pin is also connected internally to the output of the
current limit latch through a 12k resistor and can be monitored to observe the function of the cycle-by-cycle
current limit feature. Pulling this pin to a logic low effectively disables the cycle-by-cycle current limit feature.
DD
is referenced to this pin. PGND is internally connected to GND through a resistance of a few ohms,. However, it
is highly recommended to connect the GND pin to the PGND pins externally as close to the device as possible.
Failure do to this may result in oscillations on the output pins during rising or falling edges.
VDD: This is the connection for the 5V power supply, and provides power for the logic and analog circuitry in the
SA303. This pin requires decoupling (at least 0.1F capacitor with good high frequency characteristics is rec-
ommended) to the SGND pin.
DIS2: The DIS2 pin is a Schmitt triggered logic level input that places OUT A, OUT B, and OUT C in a high imped-
ance state when pulled high. DIS2 has an internal 12k pull-down resistor and may therefore be left uncon-
nected.
2. SA303 OPERATION
The SA303 is designed primarily to drive three phase motors. However, it can be used for any application requir-
ing three high current outputs. The signal set of the SA303 is designed specifcally to interface with a DSP or
microcontroller. A typical system block diagram is shown in the fgure below. Over-temperature, Short-Circuit and
Current Limit fault signals provide important feedback to the system controller which can safely disable the output
drivers in the presence of a fault condition. High side current monitors for all three phases provide performance
information which can be used to regulate or limit torque.
SA303
190 SA303U
BRUSHLESS
MOTOR
Vs (phase A)
PGND (A&B)
Current
monitor
Signals
Sensor Hall Sensors
or
Sensorless Input from Stator leads
A
B
C
OUT A
OUT B
OUT C
PGND (C)
GND
Vs (phase B&C)
Vs +
Sensing
circuits
GND
SGND
Gate
Control
Control
Logic
Fault
Logic
TEMP
I
LIM
/DIS1
SC
Ia
Ic
Ib
V
DD
PWM
Signals
DIS2
SGND
At
Ab
Bt
Bb
Ct
Cb
Microcontroller
or DSC
SA303
SA303U 191
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SGND
Gate
Control
Vs
OUT A
PGND
At
Ab
SC
TEMP
SC
Logic
Temp
Sense
Ref
Ia
DIS2
I
LIM
/DIS1
UVLO
Ia'
+
_
Lim b
Lim c
+
_
Vdd
Lim a
Current
Sense
12k
12k
12k
12k
Vth
A
t
,

B
t
,

C
t
A
b
,

B
b
,

C
b
I
a
,

I
b
,

I
c
I
L
I
M
/
D
I
S
1
D
I
S
2
O
U
T

A
,
O
U
T

B
,
O
U
T

C
Comments
0 1 <V
th
1 0 <V
th
X X >V
th
1 X High-Z
Voltage on Ia, Ib, or Ic has exceeded Vth, which causes I
LIM
/DIS1 to go high.
X X X
Pulled
High
X High-Z
Pulling the I
LIM
X X X
Pulled
Low
0
Determined
by PWM
inputs
S
TABLE 2. Truth Table
SA303
192 SA303U
The V
S
supply should be bypassed with a surface mount ceramic capacitor mounted as close as possible to the VS
S
that should be considered. Note that phases B & C share a V
S
connection and the bypass recommendation should
refect the sum of B & C phase current.
DD
DD
pin is suffcient.
sections.
adjacent DIS1 pin. If the device temperature reach-
es ~135C all outputs will be disabled, de-energizing
the motor. The SA303 will re-energize the motor when the device temperature falls below approximately 95C. The
TEMP pin hysteresis is wide to reduce the likelihood of thermal oscillations which can greatly reduce the life of the
device.
S
is above the
UVLO threshold indicated in the spec table. There is no external signal indicating that an undervoltage lock out
condition is in progress. The SA303 has two VS connections: one for phase A, and another for phases B & C. The
supply voltages on these pins need not be the same, but the UVLO will engage if either is below the threshold.
Hysteresis on the UVLO circuit prevents oscillations with typical power supply variations.
SA303
PROCESSOR
INTERRUPT
GPIO
PWM
SC
DIS2 TEMP
LATCHED FAULT
FAULT RESET
SA303
SA303U 193
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
2.4 CURRENT SENSE
with the SA303. Forward current in each top,
Pchannel output FET is measured and mir-
rored to the respective current sense output pin,
Ia, Ib and Ic. By connecting a resistor between
each current sense pin and a reference, such
as ground, a voltage develops across the resis-
tor that is proportional to the output current for
that phase. An ADC can monitor the voltages on
these resistors for protection or for closed loop
torque control in some application confgurations.
The current sense pins source current from the
VDD supply. Headroom required for the current
sense circuit is approximately .5V. The nominal
scale factor for each proportional output current is
shown in the typical performance plot on page 4
of this datasheet.
2.5 CYCLE-BY-CYCLE CURRENT
LIMIT
In applications where the current in the motor is not directly controlled, both the average current rating of the mo-
tor and the inrush current must be considered when selecting a proper amplifer. For example, a 1A continuous
motor might require a drive amplifer that can deliver well over 10A peak in order to survive the inrush condition at
startup.
Because the output current of each upper output FET is measured, the SA303 is able to provide a very robust cur-
rent limit scheme. This enables the SA303 to safely and easily drive virtually any brushless motor through a startup
inrush condition. With limited current, the starting torque and acceleration are also limited. The plot in Figure 7
shows starting current and back EMF with and without current limit enabled.
If the voltage of any of the three current sense pins exceeds the current limit threshold voltage (Vth), all outputs are
disabled. After all current sense pins fall below the Vth threshold voltage AND the offending phases top side input
goes low, the output stage will return to an active state on the rising edge of ANY top side input command signal (At,
Bt, or Ct). With most commutation schemes, the current limit will reset each pwm cycle. This scheme regulates the
peak current in each phase during each pwm cycle as illustrated in the timing diagram below. The ratio of average
to peak current depends on the inductance of the motor winding, the back EMF developed in the motor, and the
width of the pulse.
Figure 8 illustrates the current limit trigger and reset sequence. Current limit engages and I
LIM
/DIS1 goes high when
any current sense pin exceeds Vth. Notice that the moment at which the current sense signal exceeds the Vth
threshold is asynchronous with respect to the input PWM signal. The difference between the PWM period and the
motor winding L/R time constant will often result in an audible beat frequency sometimes called a sub-cycle oscil-
lation.
This oscillation can be seen on the I
LIM
/DIS1 pin waveform in Figure 8. Input signals commanding 0% or 100% duty
cycle may be incompatible with the current limit feature due to the absence of rising edges of At, Bt, and Ct except
when commutating phases. At high RPM, this may result in poor performance. At low RPM, the motor may stall if
the current limit trips and the motor current reaches zero without a commutation edge which will typically reset the
current limit latch.
LIM
/DIS1 pin to GND. The current sense pins will continue to
TIME
LIMITED BACK EMF
SA303
194 SA303U
can adjust the current limit dynamically to
allow periods of high current. In normal
operation when low current is expected,
the DAC output voltage can increase, re-
ducing the current limit setting to provide
more conservative fault protection.
2.6 EXTERNAL FLYBACK
DIODES
External fy-back diodes will offer superior
reverse recovery characteristics and low-
er forward voltage drop than the internal
back-body diodes. In high current applica-
tions, external fyback diodes can reduce
power dissipation and heating during com-
mutation of the motor current. Reverse re-
covery time and capacitance are the most
important parameters to consider when
selecting these diodes. Ultra-fast rectif-
ers offer better reverse recovery time and
Schottky diodes typically have low capaci-
tance. Individual application requirements
will be the guide when determining the
need for these diodes and for selecting the
component which is most suitable.
The thermally enhanced package of the SA303 allows several op-
tions for managing the power dissipated in the three output stages.
Power dissipation in traditional PWM applications is a combination of
output power dissipation and switching losses. Output power dissipa-
tion depends on the quadrant of operation and whether external fy-
back diodes are used to carry the reverse or commutating currents.
TOP INPUT
BOTTOM INPUT
DELAY TIMING
OUTPUT
DISABLE
A
t
INPUT
OUTA
Ia
V
th
I
LIM
/DIS1
OUTA
OUTC
OUTB
V
S
V
S
V
S
SA303
SA303
SA303U 195
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Switching losses are dependent on the frequency
of the PWM cycle as described in the typical per-
formance graphs.
of the SA303. Applications vary widely and various
thermal techniques are available to match the re-
quired performance. The patent pending mounting
technique shown in Figure 12, with the SA303 in-
verted and suspended through a cutout in the PCB
is adequate for power dissipation up to 17W with
the HS33, a 1.5 inch long aluminum extrusion with
four fns. In free air, mounting the PCB perpendicu-
lar to the ground, such that the heated air fows
upward along the channels of the fns can provide
a total
J A
of less than 14 C/W (9W max average
P
D
). Mounting the PCB parallel to the ground im-
pedes the fow of heated air and provides a
J A
of
16.66 C/W (7.5W max average P
D
). In applications
in which higher power dissipation is expected or
lower junction or case temperatures are required,
a larger heatsink or circulated air can signifcantly
improve the performance.
SA303-IHZ -25 to 85C 64 pin Power QFP (HQ package drawing) Samples Available 1Q09
PATENT PENDING
TOP INPUT
BOTTOM INPUT
OUTPUT
t(fall) t(rise)
20%
80%
SA306
196 SA306U
SA306 SA306A
DESCRIPTION
The SA306 is a fully integrated switching amplifer
designed primarily to drive three-phase Brushless
DC (BLDC) motors. Three independent half bridges
provide over 15 amperes peak output current under
microcontroller or DSC control. Thermal and short cir-
cuit monitoring is provided, which generates fault sig-
nals for the microcontroller to take appropriate action.
A block diagram is provided in Figure 1.
circuitry.
FEATURES
Low cost 3 phase intelligent switching amplifer
Directly connects to most embedded Micro-
Integrated gate driver logic with dead-time
generation and shoot-through prevention
Wide power supply range (8.5V to 60V)
Over 15A peak output current per phase
5A continuous output current per phase
8A continuous for A-Grade (SA306A)
Independent current sensing for each output
User programmable cycle-by-cycle current
limit protection
Over-current and over-temperature warning
signals
APPLICATIONS
3 phase brushless DC motors
Multiple DC brush motors
3 Phase Switching Amplifier
SA306 SA306A
P r o d u c t
I n n o v a t i o n
F r o m
Figure 1. Block Diagram
Vs (phase A)
P GND(A&B)
Gate
Control
PWM
Signals
A
B
C
Out A
Out B
Out C
P GND(C)
TEMP
GND
Vs (phase B&C)
V
S
+
I
LIM
/DIS1
SC
DIS2
SGND
P hase A
P hase C
P hase B
Control
Logic
V
DD
Ia' Ib' Ic'
Ia'
Ib'
Ic'
Fault
Logic
Ia
Ic
Ib
At
Ab
Bt
Bb
Ct
Cb
V
DD
V
DD
V
DD
JUL 2009
APEX - SA306UREVB
SA306
SA306U 197
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SUPPLY VOLTAGE V
S
60 V
SUPPLY VOLTAGE V
DD
5.5 V
DD
+0.5) V
OUTPUT CURRENT, peak, 10ms
2
I
OUT
17 A
POWER DISSIPATION, avg, 25C
2
P
D
100 W
3
T
J
150 C
STG
55 125 C
A
40 125 C
2
SA306 SA306A
Units
LOGIC
INPUT LOW 1 * V
INPUT HIGH 1.8 * V
OUTPUT LOW 0.3 * V
OUTPUT HIGH 3.7 * V
OUTPUT CURRENT
(SC, Temp, I
LIM
/DIS1)
50 * mA
POWER SUPPLY
V
S
UVLO 50 60 55 V
V
S
UNDERVOLTAGE
LOCKOUT, (UVLO)
9 * * V
V
DD
4.5 5.5 * * V
SUPPLY CURRENT, V
S
20 kHz (One phase
cycle) , V
S
=50V, V
DD
=5V
25 30 * * mA
SUPPLY CURRENT, V
DD
20 kHz (One phase
cycle) , V
S
=50V, V
DD
=5V
5 6 * * mA
CURRENT LIMIT
CURRENT LIMIT
THRESHOLD (Vth)
3.95 * V
Vth HYSTERESIS 100 * mV
OUTPUT
CURRENT, CONTINUOUS 25C Case Temperature 5 8 A
RISING DELAY, TD(RISE) See Figure 10 270 * ns
FALLING DELAY, TD(FALL) See Figure 10 270 * ns
DISABLE DELAY, TD(DIS) See Figure 10 200 * ns
ENABLE DELAY, TD(DIS) See Figure 10 200 * ns
RISE TIME, T(RISE) See Figure 11 50 * ns
FALL TIME, T(FALL) See Figure 11 50 * ns
SPECIFICATIONS
SA306
198 SA306U
NOTES:
C
= 25C).
2
SA306 SA306A
Units
ON RESISTANCE
SOURCING (P-CHANNEL)
5A Load 300 750 300 600 m
ON RESISTANCE
SINKING (N-CHANNEL)
5A Load 250 750 250 600 m
THERMAL
THERMAL WARNING 135 * C
THERMAL WARNING
HYSTERESIS
40 * C
RESISTANCE, junction to
case
Full temperature range 1.25 1.5 * * C/W
TEMPERATURE RANGE,
case
Meets Specifcations -25 85 -40 125 C
SA306
SA306U 199
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
(P-Channel)
0
1
2
3
4
5
FORWARD VOLTAGE (V)
C
U
R
R
E
N
T

(
A
)
0.5 1.5 1.3 1.1 0.9 0.7
(N-Channel)
0
1
2
3
4
5
FORWARD VOLTAGE (V)
C
U
R
R
E
N
T

(
A
)
0.5 1.5 1.3 1.1 0.9 0.7
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
I
OUT
,(A)
R
D
S
(
o
n
)
,
(
)
V
S
=11
V
S
=13
V
S
=15
V
S
>17
10 0 9 8 7 6 5 4 3 2 1
(P-Channel)
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
10
I
OUT
,(A)
R
D
S
(
o
n
)
,
(
)
V
S
=11
V
S
=13
V
S
=15
V
S
=17
V
S
>22
0 9 8 7 6 5 4 3 2 1
(N-Channel)
POWER DERATING
0
20
40
60
80
100
120
CASE TEMPERATURE, T
C
P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
D
SA306
SA306A
-40 120 80 40 0
V
DD
SUPPLY CURRENT
4.5
4.6
4.7
4.8
4.9
5
0 50 100 150 200 250 300
FREQUENCY (kHz)
V
D
D

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
50% DUTY CYCLE; V
S
=50V
V
DD
SUPPLY CURRENT
4
4.5
5
5.5
6
6.5
7
7.5
8
10 20 30 40 50 60
V
S
SUPPLY VOLTAGE (V)
V
D
D

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
FREQUENCY =20kHz
50% DUTY CYCLE
25C
125C
CURRENT SENSE
0.1
1
10
0.01 0.1 1 10
SENSE CURRENT (mA)
L
O
A
D

C
U
R
R
E
N
T

(
A
)
V
S
SUPPLY CURRENT
20
40
60
80
100
120
140
160
180
0 50 100 150 200 250 300
FREQUENCY (kHz)
V
S

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
50% DUTY CYCLE; V
S
=50V
0
V
S
SUPPLY CURRENT
0
5
10
15
20
25
V
S
SUPPLY VOLTAGE (V)
V
S

S
U
P
P
L
Y

C
U
R
R
E
N
T

(
m
A
)
125C
25C
ONE PHASE SWITCHING
FREQUENCY =20kHz
50% DUTY CYCLE
10 20 30 40 50 60
SA306
200 SA306U
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
1234567891
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
O
U
T

C
O
U
T

C
N
C
V
S

B

&

C
V
S

B

&

C
V
S

B

&

C
V
S

B

&

C
N
C
O
U
T

B
O
U
T

B
O
U
T

B
N
C
P
G
N
D

A

&

B
P
G
N
D

A

&

B
P
G
N
D

A

&

B
P
G
N
D

A

&

B
N
C
O
U
T

A
O
U
T

A
O
U
T

A
I
c
N
C
S
C
N
CI
b
N
C
I
L
I
M
/
D
I
S
1
N
C
S
G
N
D
N
C
B
t
N
C
B
b
N
C
A
b
N
C
A
t
N
C
V
D
D
N
C
OUT C
NC
PGND C
PGND C
PGND C
HS
HS
NC
Cb
NC
Ct
NC
NC
V
S
A
V
S
A
V
S
A
NC
HS
HS
TEMP
NC
DIS2
NC
Ia
29,30,31 V
S
(phase A) Power High Voltage Supply (8.5-60V) supplies phase A only
51,52,53 OUT C Power Output Half Bridge C Power Output
55,56,57 PGND (phase C) Power High Current GND Return Path for Power Output C
61 Cb Logic Input Logic high commands C phase lower FET to turn on
63 Ct Logic Input Logic high commands C phase upper FET to turn on
1 Ic Analog Output Phase C current sense output
5 Ib Analog Output Phase B current sense output
7 I
LIM
9 SGND Power Analog and digital GND internally connected to PGND
11 Bt Logic Input Logic high commands B phase upper FET to turn on
13 Bb Logic Input Logic high commands B phase lower FET to turn on
SA306
SA306U 201
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
15 Ab Logic Input Logic high commands A phase lower FET to turn on
17 At Logic Input Logic high commands A phase upper FET to turn on
19 V
DD
21 Ia Analog Output Phase A current sense output
42,43,44 OUT B Power Output Half Bridge B Power Output
46,47,48,49 V
S
(phase B&C) Power High Voltage Supply phase B&C
33,34,35 OUT A Power Output Half Bridge A Power Output
37,38,39,40 PGND (phase A&B) Power High Current GND Return Path for Power Outputs A&B
2,4,6,8,10,
12,14,16,18,
20,22,24,28,
32,36,41,45,
50,54,60,62,
64
V
S
: Supply voltage for the output transistors. These pins require decoupling (1F capacitor with good high frequency
characteristics is recommended) to the PGND pins. The decoupling capacitor should be located as close to the V
S

S
pins to handle load current peaks and
potential motor regeneration. Refer to the applications section of this datasheet for additional discussion regarding
bypass capacitor selection. Note that Vs pins 29-31 carry only the phase A supply current. Pins 46-49 carry supply
current for phases B & C. Phase A may be operated at a different supply voltage from phases B & C. Only the B &
C supply pins (46-49) are monitored for undervoltage conditions.
OUT A, OUT B, OUT C: These pins are the power output connections to the load. NOTE: When driving an inductive
load, it is recommended that two Schottky diodes with good switching characteristics (fast t
RR
specs) be connected
to each pin so that they are in parallel with the parasitic back-body diodes of the output FETs. (See Section 2.6)
through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See section 2.1 of
this datasheet for more details.
mands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approximately
200ns during switching transitions but in high current applications, short glitches may appear on the SC pin. A high
state on the SC output will not automatically disable the device. The SC pin includes an internal 12k series resistor.
Ab, Bb, Cb: These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower
N-channel output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low turns the low side
N-channel FET off. If Ab, Bb, or Cb is high at the same time that a corresponding At, Bt, or Ct input is high, protection
circuitry will turn off both FETs in order to prevent shoot-through current on that output phase. Protection circuitry
also includes a dead-time generator, which inserts dead time in the outputs in the case of simultaneous switching
of the top and bottom input signals.
At, Bt, Ct: These Schmitt triggered logic level inputs are responsible for turning the associated top side, or upper P-
channel FET outputs on and off. Logic high turns the top P-channel FET on, and a logic low turns the top P-channel
FET off.
SA306
202 SA306U
Ia, Ib, Ic: Current sense pins. The SA306 supplies a positive current to these pins which is proportional to the cur-
rent fowing through the top side P-channel FET for that phase. Commutating currents fowing through the back-
body diode of the P-channel FET or through external Schottky diodes are not registered on the current sense pins.
Nor do currents fowing through the low side N-channel FET, in either direction, register at the current sense pins. A
resistor connected from a current sense pin to SGND creates a voltage signal representation of the phase current
that can be monitored with ADC inputs of a processor or external circuitry.
The current sense pins are also internally compared with the current limit threshold voltage reference, Vth. If the
voltage on any current sense pin exceeds Vth, the cycle by cycle current limit circuit engages. Details of this func-
tionality are described in the applications section of this datasheet.
I
LIM
A, OUT B, and OUT C in a high impedance state. This pin is also connected internally to the output of the current
limit latch through a 12k resistor and can be monitored to observe the function of the cycle-by-cycle current limit
feature. Pulling this pin to a logic low effectively disables the cycle-by-cycle current limit feature.
DD
is referenced to this pin. PGND is internally connected to GND through a resistance of a few ohms,. However, it is
highly recommended to connect the GND pin to the PGND pins externally as close to the device as possible. Failure
do to this may result in oscillations on the output pins during rising or falling edges.
V
DD
DIS2: The DIS2 pin is a Schmitt triggered logic level input that places OUT A, OUT B, and OUT C in a high imped-
ance state when pulled high. DIS2 has an internal 12k pull-down resistor and may therefore be left unconnected.
2. SA306 OPERATION
The SA306 is designed primarily to drive three phase motors. However, it can be used for any application requir-
ing three high current outputs. The signal set of the SA306 is designed specifcally to interface with a DSP or
microcontroller. A typical system block diagram is shown in the fgure below. Over-temperature, Short-Circuit and
Current Limit fault signals provide important feedback to the system controller which can safely disable the output
drivers in the presence of a fault condition. High side current monitors for all three phases provide performance
information which can be used to regulate or limit torque.
SA306
SA306U 203
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
BRUSHLESS
MOTOR
Vs (phase A)
PGND (A&B)
Current
monitor
Signals
Sensor Hall Sensors
or
A
B
C
OUT A
OUT B
OUT C
PGND (C)
GND
Vs (phase B&C)
Vs +
Sensing
circuits
GND
SGND
Gate
Control
Control
Logic
Fault
Logic
TEMP
I
LIM
/DIS1
SC
Ia
Ic
Ib
V
DD
PWM
Signals
DIS2
SGND
At
Ab
Bt
Bb
Ct
Cb
Microcontroller
or DSC
A
t
,

B
t
,

C
t
A
b
,

B
b
,

C
b
I
a
,

I
b
,

I
c
I
L
I
M
/
D
I
S
1
D
I
S
2
O
U
T

A
,
O
U
T

B
,
O
U
T

C
Comments
0 1 <V
th
1 0 <V
th
X X >V
th
1 X High-Z
Voltage on Ia, Ib, or Ic has exceeded Vth, which causes I
LIM
/DIS1 to go
high. This internally disables Top and Bottom output FETs for ALL phases.
X X X
Pulled
High
X High-Z
Pulling the I
LIM
X X X
Pulled
Low
0
Determined
by PWM
inputs
S
SA306
204 SA306U
SGND
Gate
Control
Vs
OUT A
PGND
At
Ab
SC
TEMP
SC
Logic
Temp
Sense
Ref
Ia
DIS2
I
LIM
/DIS1
UVLO
Ia'
+
_
Lim b
Lim c
+
_
Vdd
Lim a
Current
Sense
12k
12k
12k
12k
Vth
The V
S
S

S
that should be considered. Note that phases B & C share a V
S
connection and the bypass recommendation should
refect the sum of B & C phase current.
DD
DD
pin is suffcient.
sections.
SA306
SA306U 205
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
adjacent DIS1 pin. If the device temperature reaches
~135C all outputs will be disabled, de-energizing the
motor. The SA306 will re-energize the motor when
the device temperature falls below approximately 95C. The TEMP pin hysteresis is wide to reduce the likelihood
of thermal oscillations which can greatly reduce the life of the device.
S
is above the
UVLO threshold indicated in the spec table. There is no external signal indicating that an undervoltage lockout
S
connections: one for phase A, and another for phases B & C. The
supply voltages on these pins need not be the same, but the UVLO will engage if either is below the threshold.
Hysteresis on the UVLO circuit prevents oscillations with typical power supply variations.
2.4 CURRENT SENSE
with the SA306. Forward current in each top, P-
channel output FET is measured and mirrored to
the respective current sense output pin, Ia, Ib and
Ic. By connecting a resistor between each cur-
rent sense pin and a reference, such as ground,
a voltage develops across the resistor that is pro-
portional to the output current for that phase. An
ADC can monitor the voltages on these resistors
for protection or for closed loop torque control
in some application confgurations. The current
sense pins source current from the V
DD
supply.
Headroom required for the current sense circuit is
approximately 0.5V. The nominal scale factor for
each proportional output current is shown in the
typical performance plot on page 4 of this data-
sheet. TIME
LIMITED BACK EMF
SA306
PROCESSOR
INTERRUPT
GPIO
PWM
SC
DIS2 TEMP
LATCHED FAULT
FAULT RESET
SA306
206 SA306U
In applications where the current in the motor is not directly controlled, both the average current rating of the motor
and the inrush current must be considered when selecting a proper amplifer. For example, a 1A continuous motor
might require a drive amplifer that can deliver well over 10A peak in order to survive the inrush condition at start-up.
Because the output current of each upper output FET is measured, the SA306 is able to provide a very robust cur-
rent limit scheme. This enables the SA306 to safely and easily drive virtually any brushless motor through a start-
up inrush condition. With limited current, the starting torque and acceleration are also limited. The plot in Figure 7
shows starting current and back EMF with and without current limit enabled.
If the voltage of any of the three current sense pins exceeds the current limit threshold voltage (Vth), all outputs are
disabled. After all current sense pins fall below the Vth threshold voltage AND the offending phases top side input
goes low, the output stage will return to an active state on the rising edge of ANY top side input command signal (At,
Bt, or Ct). With most commutation schemes, the current limit will reset each PWM cycle. This scheme regulates the
peak current in each phase during each PWM cycle as illustrated in the timing diagram below. The ratio of average
to peak current depends on the inductance of the motor winding, the back EMF developed in the motor, and the
width of the pulse.
Figure 8 illustrates the current limit trig-
ger and reset sequence. Current limit en-
gages and I
LIM
/DIS1 goes high when any
current sense pin exceeds Vth. Notice that
the moment at which the current sense
signal exceeds the Vth threshold is asyn-
chronous with respect to the input PWM
signal. The difference between the PWM
period and the motor winding L/R time
constant will often result in an audible beat
frequency sometimes called a sub-cycle
oscillation. This oscillation can be seen on
the I
LIM
/DIS1 pin waveform in Figure 8.
Input signals commanding 0% or 100%
duty cycle may be incompatible with the
current limit feature due to the absence of
rising edges of At, Bt, and Ct except when
commutating phases. At high RPM, this
may result in poor performance. At low
RPM, the motor may stall if the current
limit trips and the motor current reaches
zero without a commutation edge which
will typically reset the current limit latch.
The current limit feature may be disabled
by tying the I
LIM
/DIS1 pin to GND. The current sense pins will continue to provide top FET output current information.
controlled dynamically from the system controller. This technique essentially reduces the current limit threshold volt-
age to (Vth-VDAC). During expected conditions of high torque demand, such as start-up or reversal, the DAC can
adjust the current limit dynamically to allow periods of high current. In
normal operation when low current is expected, the DAC output voltage
can increase, reducing the current limit setting to provide more conser-
vative fault protection.
External fy-back diodes will offer superior reverse recovery character-
istics and lower forward voltage drop than the internal back-body di-
odes. In high current applications, external fyback diodes can reduce
A
t
INPUT
OUTA
Ia
V
th
I
LIM
/DIS1
OUTA
OUTC
OUTB
V
S
V
S
V
S
SA306
SA306
SA306U 207
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
power dissipation and heating during commutation of the motor current. Reverse recovery time and capacitance
are the most important parameters to consider when selecting these diodes. Ultra-fast rectifers offer better reverse
recovery time and Schottky diodes typically have low capacitance. Individual application requirements will be the
guide when determining the need for these diodes and for selecting the component which is most suitable.
TOP INPUT
BOTTOM INPUT
DELAY TIMING
OUTPUT
DISABLE
The thermally enhanced package of the SA306 al-
lows several options for managing the power dissi-
pated in the three output stages. Power dissipation
in traditional PWM applications is a combination
of output power dissipation and switching losses.
Output power dissipation depends on the quadrant
of operation and whether external fyback diodes
are used to carry the reverse or commutating cur-
rents. Switching losses are dependent on the fre-
quency of the PWM cycle as described in the typi-
cal performance graphs.
of the SA306. Applications vary widely and vari-
ous thermal techniques are available to match the
required performance. The patent pending mount-
ing technique shown in Figure 12, with the SA306
inverted and suspended through a cutout in the
PCB is adequate for power dissipation up to 17W
with the HS33, a 1.5 inch long aluminum extrusion
with four fns. In free air, mounting the PCB per-
pendicular to the ground, such that the heated air fows upward along the channels of the fns can provide a total
J A

of less than 14 C/W (9W max average P
D
). Mounting the PCB parallel to the ground impedes the fow of heated
air and provides a
J A
of 16.66 C/W (7.5W max average P
D
). In applications in which higher power dissipation is
expected or lower junction or case temperatures are required, a larger heatsink or circulated air can signifcantly
improve the performance.
TOP INPUT
BOTTOM INPUT
OUTPUT
t(fall) t(rise)
20%
80%
SA306
208 SA306U
SA306-IHZ -25 to 85C 64 pin Power QFP (HQ package drawing) Samples Available
SA306A-FHZ -40 to +125C 64 pin Power QFP (HQ package drawing) Samples Available
IMPORTANT NOTICE
PATENT PENDING
209
NOTES: ___________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
210
NOTES: ___________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
Op-Amps 211
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Power Operational Ampliers
Product Selector Matrix - Hybrids .....................................212
Product Selector Matrix - ICs............................................213
Product Selector Matrix - Open Frame Modules ..............214
Open Frame Product Design Technology .........................215
Equivalent/Second sources ..............................................216
LINEAR AMPLIFIERS
MP38, MP38A...................................................................217
MP39, MP39A...................................................................221
MP103 ..............................................................................225
MP108, MP108A...............................................................230
MP111, MP111A ................................................................234
MP230 ..............................................................................238
MP240 ..............................................................................244
MP400FC .........................................................................250
PA01, PA73 ......................................................................262
PA73M/883 .......................................................................266
PA02, PA02A ....................................................................267
PA02M/883 .......................................................................271
PA02 Design Ideas ...........................................................272
PA03, PA03A ....................................................................274
PA04, PA04A ....................................................................279
PA05, PA05A ....................................................................283
PA07, PA07A ....................................................................287
PA07M/883 .......................................................................291
PA08, PA08A ....................................................................292
PA08M/883 .......................................................................296
PA08V ...............................................................................297
PA09, PA09A ....................................................................298
PA09M/883 .......................................................................303
PA10, PA10A ....................................................................304
PA10M/883 .......................................................................308
PA12, PA12A ....................................................................309
PA12M/883 .......................................................................313
PA12H ..............................................................................314
PA13, PA13A ....................................................................315
PA15FL, PA15FLA ............................................................322
PA16, PA16A ....................................................................326
PA50, PA50A ....................................................................332
PA51, PA51A ....................................................................336
PA51M/883 .......................................................................340
PA52, PA52A ....................................................................341
PA60EU ............................................................................345
PA61, PA61A ....................................................................349
PA61M/883 .......................................................................353
PA69 .................................................................................354
PA74, PA76, PA74A, PA76A .............................................362
PA74M ..............................................................................366
PA75 .................................................................................367
PA75 Design Ideas ...........................................................371
PA78 .................................................................................372
PA79 .................................................................................382
PA81J , PA82J ...................................................................392
PA83, PA83A ....................................................................396
PA83M/883 .......................................................................400
PA84, PA84A, PA84S .......................................................401
PA84M/883 .......................................................................405
PA85, PA85A ....................................................................406
PA85M ..............................................................................410
PA86 .................................................................................411
PA88, PA88A ....................................................................419
PA89, PA89A ....................................................................423
PA90 .................................................................................427
PA91 .................................................................................432
PA92 .................................................................................437
PA93 .................................................................................442
PA94 .................................................................................447
PA95 .................................................................................453
PA96 .................................................................................458
PA97DR ............................................................................462
PA98, PA98A ....................................................................467
PA107DP ..........................................................................473
PA119CE, PA119CEA .......................................................480
PA162 ...............................................................................485
PA240 ...............................................................................491
PA241 ...............................................................................496
PA241M ............................................................................502
CPA241 ............................................................................503
PA243 ...............................................................................504
POWER BOOSTERS
PB50 .................................................................................509
PB51, PB51A ....................................................................513
PB58, PB58A ....................................................................517
Linear Amplifiers,
Power Boosters
Linear Amplifiers,
Power Boosters
212 Op-Amps
Product Selector Matrix - Hybrids
PRODUCT SELECTOR MATRIX - HYBRIDS
.15
.09
.1
.075
.01
.02
.03
.04
.05
.06
.07
10
1
4
5
8
50
40
30
20
15
.2
.9
6
7
9
3
1.5
2
2.5
3.5
.8
.3
.4
.5
.6
.7
38 50 44 56 700 7280 90 100 200 150 300 350 450 600 900 1200
O
u
t
p
u
t

C
u
r
r
e
n
t
O
u
t
p
u
t

C
u
r
r
e
n
t
Supply Voltage
.015
11
38 50 44 56 700 7280 90 100 200 150 300 350 450 600 900 1200
PA51A
PA16
PA02
PA73
PA01
PA09
PA51
PB50
PA04
PA12A
PA93
PA92
PB51A
PB58A
PA61
PA61A
PA13
PA12
PA13A
PA10
PA05
PA50
PA50A
PA52
PA52A
PA03
PA89
PA94
PA95
PA84
PA90
PA88
PA83
PA08
PA08V
PA81J
PA82J
PA97
PA96
PB51
PB58
PA15
PA15A
PA85
PA91
PA98
PA07
PA10A
PA119
PA12H
PA162
PA107
Op-Amps 213
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Power Operational Ampliers Product Selector Matrix - ICs
PRODUCT SELECTOR MATRIX - ICs
.15
.09
.1
.04
.05
.06
.07
10
1
4
5
8
.2
.9
6
7
9
3
1.5
2
.8
.3
.4
.5
.6
.7
40 50 60 600 70 80 90 100 200 150 300 350 500 700 900
O
u
t
p
u
t

C
u
r
r
e
n
t
Supply Voltage
40 50 60 700 70 80 90 100 200 300 350 500 600 900
.08
SA57
SA306
SA57A
SA306A
SA53
SA303
PA78
PA79
PA60
PA75
PA69
PA86
PA240/PA241/PA243
PA74
PA76
PA74A
PA76A
Linear Switching
214 Op-Amps
Product Selector Matrix - Open Frame
PRODUCT SELECTOR MATRIX - OPEN FRAME MODULES
.15
.1
10
1
4
5
8
50
40
30
20
15
.2
.9
6
7
9
3
2
.8
.3
.4
.5
.6
.7
40 50 60 700 70 80 90 100 200 300 350 450 600 900
O
u
t
p
u
t

C
u
r
r
e
n
t
Supply Voltage
11
40 50 60 700 70 80 90 100 200 300 350 450 600 900
MSA240 MSA260
MP39
MP103
MP108
MP230
MP240
MP111
MP38A
MP39A MP108A
MP38
MP400
Open Frame
Linear
Open Frame
Switching
Op-Amps 215
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Open Frame Product Design Technology
Copper Circuit Layer
Copper provides excellent thermal
management properties
Power Die and Solder
Creates minimal heat
spread angle
BeO Substrate and Solder
Combines excellent thermal
management and electrical
isolation
Insulating Layer
Provides electrical isolation
Aluminum Substrate
Provides mechanical rigidity, better
thermal management properties than steel
D2Pak with Power Die on Copper Slug
Creates a superior heat angle
Steel Metal Package Header
Provides mechanical rigidity, less thermal
management properties than aluminum
Open Frame vs. Hybrid Construction
Apex is driving down the cost of high power analog. For those
applications with slightly more relaxed operating environments,
the new Apex Open Frame product design delivers the power
and thermal performance of a hybrid, but at a cost that is sig-
nifcantly less.
DELIVER THE POWER AT COST SAVINGS OF UP
TO 75%
The open frame concept uses low-cost SMT (surface mount
technology) construction to deliver the power analog performance
you seek at a cost that makes selecting an off-the-shelf power
solution an easy choice over a do-it-yourself discrete. Apexs
open frame design is being integrated into both our linear power
operational amplifer and PWM amplifer product lines to achieve
per unit cost reductions of up to 75%.
THERMAL MANAGEMENT SOLVED
Working with high power in ranges above 5 amps or voltage
supplies greater than 60 volts, comes with a difficult set of thermal
management issues. A watt is a watt no matter how the amplifer
is designed. The one constant is heat dissipation. For example,
a 5 amp, 60 volt amplifer may have to dissipate hundreds of
watts while driving the load. The primary challenge is to get the
heat out of the amplifers package.
For more than 30 years, traditional hybrid designs have
achieved exceptional thermal management by soldering un-
packaged power transistors (die) to a thick flm metalized BeO
(beryllium oxide) substrate. The power transistors take the brunt
of the heat generated while driving the load. The use of BeO
provides the hybrid design with superior heat conductance, while
keeping the temperature of the power transistors under control.
With the open frame approach, thermal management actually
begins with the individually packaged components. The surface
mount power transistors are packaged in an industry-standard
D2Pak with a copper slug on the back (the D2Pak is the surface
mount version of the TO-220 package). The power transistor
inside the D2Pak is soldered to the copper slug to provide a
very low thermal resistance and an exceptionally wide heat
spread angle (see below). When the D2Pak is soldered to the
copper circuit layer of the open frames isolated metal substrate
(IMS), the thermal resistance is actually superior to that of the
hybrid design.
CREATE MORE BOARD SPACE
Although its footprint can be slightly larger than a hybrid design,
an open frame amplifer actually allows you to create a smaller
and less costly system. The open frame design incorporates
the pins and circuitry on the same side of the substrate. When
the open frame is mounted on a PCB, a 1/4 inch of space is
created between the amplifer and the board.
With this mounting arrangement, power supply bypass capaci-
tors can be placed very close to the amplifers power supply pins
while freeing-up valuable board space. This confguration also
makes room for other required system components. Open frame
products save additional board space by allowing the heatsink
to be mounted on top of the device. This is in sharp contrast
to a hybrid design that requires through-hole mounting of the
hybrid and the heatsink, thus occupying valuable board space.
WHY ROLL YOUR OWN?
As designers continue to seek new technology that will de-
crease overall system costs and trim time-to-market, Apexs new
open frame product design deserves serious consideration. An
open frame design achieves the performance of a traditional
power hybrid, but at a signifcantly lower cost. If you have con-
sidered an off-the-shelf power amplifer solution in the past, but
you ended up rolling your own because you couldnt justify the
price tag, a lower-cost option is fnally here.
Open Frame Product Design Technology
Driving Down the Cost of Power
216 Op-Amps
Equivalent/Second sources
Equivalent/Second Sources
Second Sources
Reliable Choices in Power Amplifers
Through a combination of exceptional product performance, manufacturing integrity and long product life cycles,
TM
Products from Cirrus Logic have helped customers manage component obsolescence. Be-
low is a cross reference listing for those industry models for which APEX can be used as a replacement or a second
source. The list indicates the specifc form and function each model can match: pin for pin replacement (P/F), pin
for pin but with major performance differences (P/D) and a functional equivalent (F/E).
Alternative Apex Part Fit Notes
Texas Instruments, Burr-Brown
3571/3572 PA01 P/D
PA07 P/D
PA10 P/D
PA12 P/D
PA61 P/D
3573 PA73 P/F
3573AM PA83 P/F
3573AMQ PA73 P/F
3581/3582/3583 PA83 P/F
3581J PA81J P/F
3582J PA82J P/F
3583J PA83 P/F
3584/3584J PA84 P/D
OPA2541 PA76 P/F
OPA2544 PA60 P/D
OPA501 PA51 P/F
PA61 P/D
OPA502BM PA12 P/D
OPA502SM PA12A P/D
OPA511AM PA01 P/D
PA10 P/D
OPA512 PA12 P/F
PA10 P/D
OPA512SM PA12A P/F
OPA541 PA02 F/E
PA10 P/D
PA07 P/D
PA12 P/D
PA51 P/D
PA61 P/D
OPA548 PA01 F/E
PA73 F/E
(P/F) = Pin for pin compatible - form, ft and functional replacement
(P/D) = Pin for pin compatible - major performance differences noted
(F/E) = Functional equivalent - not pin for pin compatible - major differences noted
MP38 MP38A
MP38U 217
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
P r o d u c t I n n o v a t i o n F r o m MP38, MP38A
R
F
+50V
R
I
ULTRA-
SONIC
DRIVE
-50V
NC
C
C
R
CL
TUNED
TRANSFORMER
1
+V
B
+V
S
-I
LIM
+I
LIM
OUT
-IN
+IN
-V
B
-V
S
I
Q
C
C
1
C
C
2
ULTRA-SONIC AMPLIFIER
30
23
24
15-17
4
6
25
18-20
26
MP38
29
12-14
FEATURES
HIGH INTERNAL DISSIPATION 125 Watts
HIGH VOLTAGE, HIGH CURRENT 200V, 10A
HIGH SLEW RATE 10V/s
4 WIRE CURRENT LIMIT SENSING
OPTIONAL BOOST VOLTAGE INPUTS
APPLICATIONS
LINEAR AND ROTARY MOTOR DRIVES
YOKE/MAGNETIC FIELD EXCITATION
PROGRAMMABLE POWER SUPPLIES TO 95V
INDUSTRIAL AUDIO
PACKAGE OPTION - DIP10 - DUAL-IN-LINE
DESCRIPTION
The MP38 is a cost-effective high voltage MOSFET power
operational amplifer constructed with surface mount com-
ponents on a thermally conductive but electrically isolated
substrate.
While the cost is low the MP38 offers many of the same
features and performance specifcations found in much more
expensive hybrid power amplifers.
The metal substrate allows the MP38 to dissipate power
up to 125 watts and its power supply voltages can range up
to +/- 100 Volts (200V total). Optional boost voltage inputs
allow the small signal portion of the amplifer to operate at
higher supply voltages than the high current output stage.
The amplifer is then biased to achieve close linear swings
to the supply rails at high current for extra efficient operation.
External compensation tailors performance to the user needs.
A four-wire sense technique allows current limiting without
the need to consider internal or external mili-ohm parasitic
resistance in the output line. An Iq pin is available which can
be used to shut off the quiescent current in the output stage.
The output stage then operates class C and lowers quiescent
power dissipation. This is useful in applications where output
crossover distortion is not important.
EQUIVALENT SCHEMATIC
-
I
N
N
C
O
U
T
15
-
V
b
24
-
l
l
i
m
N
C
20
+
I
N
16
G
N
D
28 25 30 21 26
N
C
27 19 17 22 23
I
q
+
I
l
i
m
18 29
Cc
+
V
b
N
C
+
V
s
N
C
7
C
c
1
N
C
11
G
N
D
N
C
+
V
s
N
C
3 6 1 10 5
C
c
2
4 12 14 9 8
N
C
N
C
13 2
COMPONENT SIDE VIEW
+
V
s
*
* *
O
U
T
O
U
T
-
V
s
-
V
s
-
V
s
*
14
13
12
17
16
15
23
24
4
6
30
29
25
26
1
20
19
18
C2 C1
2 GND
28
C3
GND
+Vb
Cc2
Cc1
-IN
+IN
Iq
-Vb
Q1A
D1
Q4
Q5
Q11A
Q14
Q12
Q7
Q1B
Q2
Q6
Q11B
Q15
Q13
Q10
Q3
+Vs
+Ilim
-Ilim
OUT
-Vs
+Vs
OUT
-Vs
+Vs
OUT
-Vs
TYPICAL APPLICATION REF: APPLICATION NOTE 25
The high power bandwidth and high voltage output of the
MP38 allows driving ultra-sonic transducers via a resonant
circuit including the transducer and a matching transformer.
The load circuit appears resistive to the MP38.
* SEE "BYPASSING" PARAGRAPH
Phase Compensation
Gain Cc Rc
1 470pF 100
3 220pF Short
10 100pF Short
Power Operational Amplifier
MP38 MP38A P r o d u c t I n n o v a t i o n F r o m
30-PIN DIP
PACKAGE STYLE CL
JUN 2009
APEX MP38UREVH
MP38 MP38A
218 MP38U
SUPPLY VOLTAGE, +V
S
to V
S
200V
BOOST VOLTAGE V
S
20V
OUTPUT CURRENT, within SOA 25A
INPUT VOLTAGE, differential 20V
INPUT VOLTAGE, common mode V
B
2
175C
SPECIFICATIONS
NOTES: * The specifcation of MP38A is identical to the specifcation for MP38 in applicable column to the left.
C
= 25C, R
C
= 100, C
C
= 470pF. DC input specifcations are value given. Power supply voltage is
typical rating. V
B
= V
S
.
3. Rating applies if the output current alternates between both output transistors at a rate faster than 60 Hz.
4. The MP38 must be used with a heat sink or the quiescent power may drive the unit to junction temperatures higher than 175C.
The MP38 is constructed from MOSFET transistors. ESD handling procedures must be observed.
MP38 MP38A
1
INPUT
OFFSET VOLTAGE, initial 5 10 3 mV
OFFSET VOLTAGE, vs. temperature Full temperature range 30 50 * * V/C
OFFSET VOLTAGE, vs. supply 15 * V/V
OFFSET VOLTAGE, vs. power Full temperature range 30 * V/W
BIAS CURRENT, initial 10 200 * 100 pA
BIAS CURRENT, vs. supply .01 * pA/V
OFFSET CURRENT, initial 10 50 * 30 pA
INPUT IMPEDANCE, DC 10
10
*
INPUT CAPACITANCE 20 * pF
COMMON MODE VOLTAGE RANGE Full temperature range V
B
15

V
B
12 * * V
COMMON MODE REJECTION, DC Full temp, range, V
CM
= 20V 86 98 * * dB
INPUT NOISE 100kHz BW, R
S
= 1K 10 * Vrms
GAIN
OPEN LOOP, @15Hz Full temperature range, C
C
= 100pF 94 113 * * db
GAIN BANDWIDTH PRODUCT I
O
=10A 2 * MHz
POWER BANDWIDTH R
L
=20, V
O
=

180V p-p 20 * kHz
C
C
= 100pF
PHASE MARGIN Full temperature range 60 *
OUTPUT
VOLTAGE SWING I
O
=10A V
S

8.8 V
S

6.6 * * V
VOLTAGE SWING V
B
= V
S
10V, I
O
=10A V
S
6.8 V
S
4 * * V
SETTLING TIME to .1% A
V
=+1,10V step, R
L
=4 2.5 * s
SLEW RATE A
V
= 10, C
C
= 100pF 10 * V/s
CAPACITIVE LOAD Full temperature range, A
V
=+1 10 * nF
RESISTANCE 4 *
CURRENT, CONTINUOUS 10 11 A
POWER SUPPLY
VOLTAGE Full temperature range 15 75 100 * * * V
CURRENT, quiescent, boost supply 22 * mA
CURRENT, quiescent, total 26 * mA
THERMAL
RESISTANCE, AC, junction to case
3
Ful
l
temperature range, F>60Hz .9 * C/W
RESISTANCE, DC, junction to case Full temperature range, F<60Hz 1.2 * C/W
RESISTANCE
4
, junction to air Full temperature range 12 * C/W
TEMPERATURE RANGE, case Meets full range specifcation -40 85 * * C
CAUTION
MP38 MP38A
MP38U 219
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PULSE RESPONSE PULSE RESPONSE
OUTPUT VOLTAGE SWING
0
1
2
3
4
5
6
7
8
9
10
OUTPUT CURRENT, I
O
(A)
O
U
T
P
U
T

V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S
-
V
O

(
V
)
+V
B
= +V
S
0 10 8 6 4 2
+V
B
= +V
S
+10V
-
VB

=
-
VS
-
1
0
V
-V
B
=
-V
S
SLEW RATE vs. COMP.
0
10
20
30
40
50
60
70
COMPENSATION CAPACITOR, (pF)
S
L
E
W

R
A
T
E

(
V
/
s
)
0 100 200 300 400 500
POWER RESPONSE
1
10
100
1K
FREQUENCY (KHz)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
47pF
100pF
470pF
220pF
100 1K 10
SMALL SIGNAL PHASE
FREQUENCY, F (Hz)
O
P
E
N

L
O
O
P

P
H
A
S
E
,

)
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
47pF
100pF
220pF
470pF
47pF
100pF
220pF
470pF
100 100M 1M 10K 1
SMALL SIGNAL RESPONSE
FREQUENCY, F (Hz)
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
-20
0
20
40
60
80
100
120
140
470pF
100pF
47pF
220pF
1 100 10K 1M 100M
SOA
SUPPLY TO OUTPUT DIFFERENTIAL, V
S
-V
O
(V)
O
U
T
P
U
T

C
U
R
R
E
N
T
,

I
O

(
A
)
1
0.2
10
20
10s
100s 1ms 10ms
25C
85C
5 200 100 10
HARMONIC DISTORTION
0.001
0.01
0.1
1
10
FREQUENCY, F(Hz)
P
E
R
C
E
N
T

D
I
S
T
O
R
T
I
O
N

+

N
O
I
S
E
A
V
= 10
V
S
= 96V
R
L
= 24
0.5W
5W
100 100K 10K 1K
150W
50W
0 20 40 60 80
CASE TEMPERATURE, T
C
(C)
40
60
80
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
100
20
0
100
120
140
GENERAL
Please read Application Note 1 "General Operating Con-
siderations" which covers stability, supplies, heat sinking,
mounting, current limit, SOA interpretation, and specifcation
interpretation. Visit www.apexmicrotech.com for design tools
that help automate tasks such as calculations for stability,
internal power dissipation, current limit; heat sink selection;
Apexs complete Application Notes library; Technical Seminar
CURRENT LIMIT
The two current limit sense lines are to be connected directly
across the current limit sense resistor. For the current limit to
work correctly pin 24 must be connected to the amplifer
output side and pin 23 connected to the load side of the
current limit resistor, R
CL
, as shown in Figure 1. This con-
nection will bypass any parasitic resistances, Rp, formed by
sockets and solder joints as well as internal amplifer losses.
The current limiting resistor may not be placed anywhere in
the output circuit except where shown in Figure 1.
The value of the current limit resistor can be calculated as
follows:
.7
R
CL
=
I
LIMIT
BOOST OPERATION
With the V
B
feature the small signal stages of the amplifer
are operated at higher supply voltages than the amplifer's high
current output stage. +V
S
(pins 12-14) and V
S
(pins 18-20)
are connected to the high current output stage. An additional
10V on the V
B
pins is sufficient to allow the small signal stages
to drive the output transistors into saturation and improve the
output voltage swing for extra efficient operation when required.
When close swing to the supply rails is not required the +V
B
and +V
S
pins must be strapped together as well as the V
B

and V
S
pins. The boost voltage pins must not be at a voltage
lower than the V
S
pins.
BYPASSING
Proper bypassing of the power supply pins is crucial for proper
operation. Bypass the Vs pins with a aluminum electrolytic
capacitor with a value of at least 10F per amp of expected
output current. In addition a .47F to 1F ceramic capacitor
should be placed in parallel with each aluminum electrolytic
capacitor. Both of these capacitors have to be placed as close
to the power supply pins as physically possible. If not connected
to the Vs pins (See BOOST OPERATION) the V
B
pins should
also be bypassed with a .47F to 1F ceramic capacitor.
USING THE IQ PIN FUNCTION
Pin 25 (Iq) can be tied to pin 6 (Cc1) to eliminate the class
AB biasing current from the output stage. Typically this would
remove 1-4 mA of quiescent current. The resulting decrease
in quiescent power dissipation may be important in some
applications. Note that implementing this option will raise
the output impedance of the amplifer and increase crossover
distortion as well.
COMPENSATION
The external compensation components C
C
and R
C
are con-
nected to pins 4 and 6. Unity gain stability can be achieved
at any compensation capacitance greater than 470 pF with at
least 60 degrees of phase margin. At higher gains more phase
shift can be tolerated in most designs and the compensation
capacitance can accordingly be reduced, resulting in higher
bandwidth and slew rate.
APPLICATION REFERENCES
For additional technical information please refer to the fol-
lowing application notes.
AN 1 General Operating Considerations
AN 11 Thermal Techniques
AN 38 Loop Stability with Reactive Loads
MP38 MP38A
220 MP38U
R
F
R
I
30
29
23
24
R
CL
MP38
R
P
R
L
INPUT
1517
FIGURE 1. CURRENT LIMIT
MP39 MP39A
MP39U 221
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
MP39, MP39A
R
F
+50V
R
I
ULTRA-
SONIC
DRIVE
-50V
NC
R
C
C
C
R
CL
TUNED
TRANSFORMER
1
+V
B
+V
S
-I
LIM
+I
LIM
OUT
-IN
+IN
-V
B
-V
S
I
Q
C
C
1
C
C
2
ULTRA-SONIC AMPLIFIER
30
23
24
15-17
4
6
25
18-20
26
MP39
29
12-14
FEATURES
APPLICATIONS
INDUSTRIAL AUDIO
PACKAGE OPTION - DIP10 - DUAL-IN-LINE
DESCRIPTION
The MP39 is a cost-effective high voltage MOSFET power
operational amplifer constructed with surface mount com-
ponents on a thermally conductive but electrically isolated
substrate.
While the cost is low the MP39 offers many of the same
features and performance specifcations found in much more
expensive hybrid power amplifers.
The metal substrate allows the MP39 to dissipate power
up to 125 watts and its power supply voltages can range up
to +/- 50 Volts (100V total). Optional boost voltage inputs
allow the small signal portion of the amplifer to operate at
higher supply voltages than the high current output stage.
The amplifer is then biased to achieve close linear swings
to the supply rails at high current for extra efficient operation.
External compensation tailors performance to the user needs.
A four-wire sense technique allows current limiting without
the need to consider internal or external mili-ohm parasitic
resistance in the output line. An Iq pin is available which can
be used to shut off the quiescent current in the output stage.
The output stage then operates class C and lowers quiescent
power dissipation. This is useful in applications where output
crossover distortion is not important.
* SEE "BYPASSING" PARAGRAPH
Phase Compensation
Gain Cc Rc
1 470pF 100
3 220pF Short
10 100pF Short
-
I
N
N
C
O
U
T
15
-
V
b
24
-
l
l
i
m
N
C
20
+
I
N
16
G
N
D
28 25 30 21 26
N
C
27 19 17 22 23
I
q
+
I
l
i
m
18 29
Cc
Rc
+
V
b
N
C
+
V
s
N
C
7
C
c
1
N
C
11
G
N
D
N
C
+
V
s
N
C
3 6 1 10 5
C
c
2
4 12 14 9 8
N
C
N
C
13 2
COMPONENT SIDE VIEW
+
V
s
*
* *
O
U
T
O
U
T
-
V
s
-
V
s
-
V
s
*
14
13
12
17
16
15
23
24
4
6
30
29
25
26
1
20
19
18
C2 C1
2 GND
28
C3
GND
+Vb
Cc2
Cc1
-IN
+IN
Iq
-Vb
R1
Q1A
D1
Q5
Q6
Q10A
Q13
R12
R3
R8
R9
Q11
Q9
R2
Q1B
Q3
Q7
Q10B
R6 R7
Q14
R13
Q12
Q8
Q4
R10
R11
R4
R5
+Vs
+Ilim
-Ilim
OUT
-Vs
+Vs
OUT
-Vs
+Vs
OUT
-Vs
TYPICAL APPLICATION REF: APPLICATION NOTE 25
MP39 allows driving ultra-sonic transducers via a resonant
circuit including the transducer and a matching transformer.
The load circuit appears resistive to the MP39.
30-pin DIP
PACKAGE STYLE CL
MAY 2009
APEX MP39UREVH
MP39 MP39A
222 MP39U
SUPPLY VOLTAGE, +V
S
to V
S
100V
BOOST VOLTAGE V
S
20V
B
2
175C
SPECIFICATIONS
NOTES: * The specifcation of MP39A is identical to the specifcation for MP39 in applicable column to the left.
C
= 25C, R
C
= 100, C
C
= 470pF. DC input specifcations are value given. Power supply voltage is
typical rating. V
B
= V
S
.
4. The MP39 must be used with a heat sink or the quiescent power may drive the unit to junction temperatures higher than 175C.
The MP39 is constructed from MOSFET transistors. ESD handling procedures must be observed.
CAUTION
MP39 MP39A
1
INPUT
OFFSET VOLTAGE, initial 5 10 * 3 mV
OFFSET VOLTAGE, vs. power Full temperature range 30 * V/W
BIAS CURRENT, initial 10 200 * 100 pA
OFFSET CURRENT, initial 10 50 * 30 pA
10
*
B
15 V
B
12 * * V
COMMON MODE REJECTION, DC Full temp, range, V
CM
= 20V 86 98 * * dB
S
= 1K 10 * Vrms
GAIN
OPEN LOOP, @15Hz Full temperature range, C
C
= 100pF 94 113 * * db
O
=10A 2 * MHz
POWER BANDWIDTH R
L
=10, V
O
=

90V p-p 40 * kHz
C
C
= 100pF
OUTPUT
VOLTAGE SWING I
O
=10A V
S
8.8 V
S
6.0 * * V
VOLTAGE SWING V
B
= V
S
10V, I
O
=10A V
S
6.8 V
S
1.1 * * V
V
=+1,10V step, R
L
=4 2.5 * s
SLEW RATE A
V
= 10, C
C
= 100pF 10 * V/s
V
=+1 10 * nF
RESISTANCE 4 *
CURRENT, CONTINUOUS 10 11 A
POWER SUPPLY
CURRENT, quiescent, boost supply 22 * mA
CURRENT, quiescent, total 26 * mA
THERMAL
3
Ful
l
temperature range, F>60Hz .9 * C/W
RESISTANCE, DC, junction to case Full temperature range, F<60Hz 1.2 * C/W
RESISTANCE
4
MP39 MP39A
MP39U 223
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
HARMONIC DISTORTION
100
10
1
0.1
0.01
0.001
%

D
I
S
T
R
I
B
U
T
I
O
N

+

N
O
I
S
E
100 1K 10K 100K
FREQUENCY, F (Hz)
220pF
100pF
470pF
220pF
100pF
PHASE RESPONSE
FREQUENCY, F (Hz)
P
H
A
S
E

(
D
E
G
R
E
E
S
)
1 10 100 1K 10K 100K 1M 10M
0
-30
-60
-120
-150
-180
-210
-90
O
P
E
N

L
O
O
P

G
A
I
N
,

A
O
L

(
d
B
)
140
120
100
80
60
40
20
0
-20
-40
FREQUENCY, F (Hz)
1 10 100 1K 10K 100K 1M 10M
470pF
50W
10 LOAD
50mW
A
V
= 10
V
S
= +/-36
R
LOAD
= 8
470pF
220pF
100pF
25C
85C
125C
1mS
10mS
100 200 300 400 500
EXT. COMPENSATION CAPACITOR (pF)
10
40
S
L
E
W

R
A
T
E

(
V
/
F
)
50
30
20
0
SLEW RATE VS. COMP.
0 20 40 60 80
CASE TEMPERATURE, T
C
(C)
40
60
80
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
100
20
0
100
120
140
1
POWER RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
P
)
100
10 100 1000
10
1
FREQUENCY (kHz)
1 100
SUPPLY to OUTPUT DIFFERENTIAL, V
S
-V
O
(V)
SOA
O
U
T
P
U
T

C
U
R
R
E
N
T
,

I
O

(
A
)
100
10
0.1
1
10
9
6
3
0
0 2 4 6 8 10
O
U
T
P
U
T

V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

-
V
O
(
V
)
OUTPUT CURRENT, I
O
(A)
+
VB
=
+
VS
-
V B

=

-
V S

-

1
0
V
7
4
1
8
5
2
-VS
=
-VB
+
VB
=
+
VS
+
1
0
V
MP39 MP39A
224 MP39U
GENERAL
interpretation. Visit www.cirrus.com for design tools that help
automate tasks such as calculations for stability, internal power
dissipation, current limit; heat sink selection; Apex Precision
CURRENT LIMIT
work correctly pin 24 must be connected to the amplifer output
side and pin 23 connected to the load side of the current limit
resistor, R
CL
, as shown in Figure 1. This connection will bypass
any parasitic resistances, Rp, formed by sockets and solder
joints as well as internal amplifer losses. The current limiting
resistor may not be placed anywhere in the output circuit except
where shown in Figure 1.
follows:
.7
R
CL
=
I
LIMIT
BOOST OPERATION
With the V
B
feature the small signal stages of the amplifer
are operated at higher supply voltages than the amplifer's high
current output stage. +V
S
(pins 12-14) and V
S
(pins 18-20)
are connected to the high current output stage. An additional
10V on the V
B
pins is sufficient to allow the small signal stages
to drive the output transistors into saturation and improve the
output voltage swing for extra efficient operation when required.
When close swing to the supply rails is not required the +V
B
and +V
S
B

and V
S
pins. The boost voltage pins must not be at a voltage
lower than the V
S
pins.
BYPASSING
Proper bypassing of the power supply pins is crucial for proper
operation. Bypass the Vs pins with a aluminum electrolytic
capacitor with a value of at least 10F per amp of expected
output current. In addition a .47F to 1F ceramic capacitor
should be placed in parallel with each aluminum electrolytic
capacitor. Both of these capacitors have to be placed as close
to the power supply pins as physically possible. If not connected
to the Vs pins (See BOOST OPERATION) the V
B
pins should
also be bypassed with a .47F to 1F ceramic capacitor.
USING THE IQ PIN FUNCTION
Pin 25 (Iq) can be tied to pin 6 (Cc1) to eliminate the class
AB biasing current from the output stage. Typically this would
remove 1-4 mA of quiescent current. The resulting decrease
in quiescent power dissipation may be important in some
applications. Note that implementing this option will raise
the output impedance of the amplifer and increase crossover
distortion as well.
COMPENSATION
C
and R
C
are con-
bandwidth and slew rate.
APPLICATION REFERENCES
lowing application notes.
AN01 General Operating Considerations
AN11 Thermal Techniques
AN38 Loop Stability with Reactive Loads
R
F
R
I
30
29
23
24
R
CL
MP39
R
P
R
L
INPUT
1517
MP103
MP103U 225
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
MP103
GENERAL DESCRIPTION
The MP103 is a high voltage, high output current
dual channel operational amplifer for driving capaci-
tive loads such as piezo devices use in ink jet print-
ing applications. The MP103 utilizes proprietary ICs
combined with discrete semiconductor and passive
elements on a thermally conductive insulated metal
substrate, delivering very high power from a compact
module. The amplifer gain is fxed at 65 V/V when
the feedback pin is connected to the V
OUT
pin. Internal
compensation provides optimum slew rate and insures
stability. The only external components required are
the current limit resistors R
LIM
, a series isolation resis-
tor R
S
and the power supply bypass capacitors.
FEATURES
Low Cost Integrated Solution
Output Current >10A Within SOA
Internal Power Dissipation 35 W Per Channel
167V/S Slew Rate
APPLICATIONS
Piezoelectric Actuation For Ink Jet Printer
Nozzles
Power Operational Amplifiers
MP103 P r o d u c t I n n o v a t i o n F r o m
Feedback A
-Vs
IN_A
+Vaux
+Vs
Out B
IL
Out A
Feedback B
-Vs
+Vs
IL
-Vs
+Vs
IL
-Vs
+Vs
IL
-Vs
+Vs
IL
-Vs
+Vs
IL
IN_B
GND
-5V
SEP 2009
APEX MP103UREVA
42-Pin DIP
Package Style FC
MP103
226 MP103U
SUPPLY VOLTAGE, +V
S
to V
S
+V
S
to V
S
200 V
SUPPLY VOLTAGE, V
S
V
S
-30 V
SUPPLY VOLTAGE, +V
AUX
+V
AUX
30 V
OUTPUT CURRENT, pk, per Channel (Within SOA) I
O(PK)
15 A
POWER DISSIPATION, internal, Each Channel P
D
35 W
INPUT VOLTAGE V
IN
-5 V
AUX
V
TEMPERATURE, junction (Note 2) T
J
150 C
S
40 105 C
Parameter Test Conditions Min Typ Max Units
INPUT (Each Channel)
OFFSET VOLTAGE -6.7 2 6.7 mV
OFFSET VOLTAGE vs. temperature Full temperature range 2 V/C
BIAS CURRENT, initial (Note 3) -6.6 3.3 6.6 A
INPUT RESISTANCE, DC 300 K
INPUT CAPACITANCE 1.5 pF
INPUT VOLTAGE RANGE -3.4 +V
AUX
- 2 V
NOISE f = 10KHz 600 nV/Hz
GAIN (Each Channel)
FIXED GAIN Feedback connected to V
OUT
63.5 65 66.5 V/V
GAIN BANDWIDTH, -3db C
L
= 47nF 230 KHz
POWER BANDWIDTH, 130V
P-P
+V
S
= 145V, -V
S
= -15V 230 KHz
OUTPUT (Each Channel)
VOLTAGE SWING I
O
= 10A +V
S
- 15 +V
S
- 9 V
VOLTAGE SWING I
O
= -5A -V
S
+ 15 -V
S
+ 14 V
CURRENT, Peak, Source 12 A
SLEW RATE R
S
=1.0, C
L
=47nF, V
IN
8V
P-P
167 V/S
POWER SUPPLY (Note 4)
VOLTAGE, -V
S
-7 -15 -20 V
VOLTAGE, +V
AUX
24 25 V
VOLTAGE, +V
S
-V
S
+ 20 145 -V
S
+ 200 V
CURRENT, quiescent, -V
S
19 26 mA
CURRENT, quiescent, +V
AUX
13.5 15 mA
CURRENT, quiescent, +V
S
1 5 mA
THERMAL
RESISTANCE, AC, junction to case (Note 5) Full temperature range, f 60Hz 1.5 1.75 C/W
RESISTANCE, DC, junction to case Full temperature range, f < 60Hz 3.1 3.6 C/W
RESISTANCE, junction to air Full temperature range 12.5 14 C/W
TEMPERATURE RANGE, case 0 70 C
SPECIFICATIONS
MP103
MP103U 227
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
NOTES:
tions. Typical performance characteristics and specifcations are derived from measurements taken at
typical supply voltages and T
C
= 25C).
3. Doubles for every 10C of case temperature increase.
4. +V
S
and V
S
denote the positive and negative supply voltages to the output stages. +V
AUX
denotes the
positive supply voltage to the input stages.
5. Rating applies if the output current alternates between both output transistors at a rate faster than
60Hz.
TOTAL SUPPLY VOLTAGE, V
AUX
(V)
INPUT BIAS CURRENT vs. V
AUX
SUPPLY
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
5 25 20 15 10
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
AUX
(V)
OFFSET VOLTAGE vs. V
AUX
SUPPLY
N
O
R
M
A
L
I
Z
E
D

O
F
S
E
T

V
O
L
T
A
G
E
,

V
O
S

(
X
)
5 25 20 15 10
0
1.2
1.0
0.8
0.6
0.4
0.2
SS
(V)
S
SUPPLY
N
O
R
M
A
L
I
Z
E
D

O
F
S
E
T

V
O
L
T
A
G
E
,

V
C
S

(
X
)
5 205 180 155 130 105 80 55 30
0.995
1.035
1.030
1.025
1.020
1.015
1.010
1.005
1.000
CASE TEMPERATURE, T
C
(C)
INPUT BIAS CURRENT vs. TEMPERATURE
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
0 20 40 60 80 -20 -40
0.7
1.2
1.1
1.0
0.9
0.8
0.6
1.6
1.5
1.4
1.3
MAX. OUTPUT PULSE DUTY CYCLE
10
100
OUTPUT VOLTAGE, V
O
(V)
M
A
X
I
M
U
M

D
U
T
Y

C
Y
C
L
E
,

D
C

(
%
)
T
C
=25C
T
C
=70C
100 180 160 140 120
MAX. DC OUTPUT VOLTAGE
100
110
120
130
140
150
CASE TEMPERATURE, T
C
(C)
D
C

O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
d
c
)
0 75 50 25
CASE TEMPERATURE, T
C
(C)
OFFSET VOLTAGE vs. TEMPERATURE
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
0 20 40 60 80 -20 -40
0.7
1.2
1.1
1.0
0.9
0.8
0.6
QUIESCENT CURRENT
0.96
0.98
1
1.02
1.04
1.06
1.08
1.1
CASE TEMPERATURE, T
C
(C)
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
+V
S
V
AUX
-V
S
0 75 50 25 -25
FREQUENCY RESPONSE
-20
-10
0
10
20
30
40
50
1K 10K 1M
FREQUENCY, F (Hz)
G
A
I
N
,

A

V

(
D
B
)
-180
-150
-120
-90
-60
-30
0
30
P
H
A
S
E
,

(
)
100K
C
LOAD
=50nF
LEFT SCALE
RIGHT SCALE
0
2
4
6
8
10
12
14
16
OUTPUT CURRENT, I
O
(A)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y

(
V
)
SOURCE
SINK
0 10 7.5 5 2.5
SOA
S
- V
O
(V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

-
V
S

(
A
)
10 100 1
1
10
1mS
10mS
SINK DC
SOURCE
DC
POWER DERATING
CASE TEMPERATURE, T
C
(C)
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
P
E
R

C
H
A
N
N
E
L
,

P
D

(
W
)
EACH CHANNEL
0 100 75 50 25
0
40
35
30
25
20
15
10
5
MP103
228 MP103U
Pin # Pin name Description
1,2,3 +V
S
_A Positive high voltage power supply pins for channel A.
4,5,6 I
L
_A
High current output pins for channel A. A current limit resistor must be placed between these pins
and the output pin 8.
8 Out_A Output pin for channel A.
15 Out_B Output pin for channel B.
18,19,20 +V
S
_B Positive high voltage power supply pins for channel B.
21,22,23 -V
S
_B Negative power supply pins for channel B.
24,25,26 I
L
_B
High current output pins for channel B. A current limit resistor must be placed between these pins
and the output pin 15.
28 IN_B Input pin for channel B.
30 Feedback_B
Feed back pin for channel B. This pin must be connected to output B pin 15 to close the feedback
loop. When connected directly to pin 15 the closed loop voltage gain of channel B is 65 V/V. The
gain can be increased by inserting a 1/4 W resistor between pins 30 and 15.
32 GND Ground
34 +V
AUX
+24V voltage power supply pin. A 24 V power supply is required for operation of front end small
signal circuitry of each channel.
36 Feedback_A
Feed back pin for channel A. This pin must be connected to output A pin 8 to close the feedback
loop. When connected directly to pin 8 the closed loop voltage gain of channel A is 65 V/V. The
gain can be increased by inserting a 1/4 W resistor between pins 36 and 8.
38 IN_A Input pin for channel A.
40,41,42 -V
S
_A Negative power supply pins for channel A.
PIN DESCRIPTIONS
AUX
(V)
AUX
SUPPLY
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
5 25 20 15 10
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
AUX
(V)
AUX
SUPPLY
N
O
R
M
A
L
I
Z
E
D

O
F
S
E
T

V
O
L
T
A
G
E
,

V
O
S

(
X
)
5 25 20 15 10
0
1.2
1.0
0.8
0.6
0.4
0.2
SS
(V)
S
SUPPLY
N
O
R
M
A
L
I
Z
E
D

O
F
S
E
T

V
O
L
T
A
G
E
,

V
C
S

(
X
)
5 205 180 155 130 105 80 55 30
0.995
1.035
1.030
1.025
1.020
1.015
1.010
1.005
1.000
CASE TEMPERATURE, T
C
(C)
INPUT BIAS CURRENT vs. TEMPERATURE
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
0 20 40 60 80 -20 -40
0.7
1.2
1.1
1.0
0.9
0.8
0.6
1.6
1.5
1.4
1.3
MAX. OUTPUT PULSE DUTY CYCLE
10
100
OUTPUT VOLTAGE, V
O
(V)
M
A
X
I
M
U
M

D
U
T
Y

C
Y
C
L
E
,

D
C

(
%
)
T
C
=25C
T
C
=70C
100 180 160 140 120
MAX. DC OUTPUT VOLTAGE
100
110
120
130
140
150
CASE TEMPERATURE, T
C
(C)
D
C

O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
d
c
)
0 75 50 25
CASE TEMPERATURE, T
C
(C)
OFFSET VOLTAGE vs. TEMPERATURE
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
0 20 40 60 80 -20 -40
0.7
1.2
1.1
1.0
0.9
0.8
0.6
QUIESCENT CURRENT
0.96
0.98
1
1.02
1.04
1.06
1.08
1.1
CASE TEMPERATURE, T
C
(C)
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
+V
S
V
AUX
-V
S
0 75 50 25 -25
FREQUENCY RESPONSE
-20
-10
0
10
20
30
40
50
1K 10K 1M
FREQUENCY, F (Hz)
G
A
I
N
,

A

V

(
D
B
)
-180
-150
-120
-90
-60
-30
0
30
P
H
A
S
E
,

(
)
100K
C
LOAD
=50nF
LEFT SCALE
RIGHT SCALE
0
2
4
6
8
10
12
14
16
OUTPUT CURRENT, I
O
(A)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y

(
V
)
SOURCE
SINK
0 10 7.5 5 2.5
SOA
S
- V
O
(V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

-
V
S

(
A
)
10 100 1
1
10
1mS
10mS
SINK DC
SOURCE
DC
POWER DERATING
CASE TEMPERATURE, T
C
(C)
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
P
E
R

C
H
A
N
N
E
L
,

P
D

(
W
)
EACH CHANNEL
0 100 75 50 25
0
40
35
30
25
20
15
10
5
40 80 60
450
-SLR
+SLR
CASE TEMPERATURE, TC (C)
SLEW RATE vs. TEMPERATURE
S
L
E
W

R
A
T
E
,

S
L
R

(
V
/
s
)
-20 20 0 -40
150
400
350
300
250
200
EXTERNAL FEEDBACK RESISTOR, R
FDBK
()
AMPLIFIER GAIN vs. R
FDBK
A
M
P
L
I
F
I
E
R

G
A
I
N
,

A
V

(
V
/
V
)
500 1500 1000 0
65
105
100
95
90
85
80
75
70
SS
(V)
SS
SUPPLY
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
5 205 155 105 55
0
0.2
0.4
0.6
0.8
1.0
1.2
180 130 80 30
MP103
MP103U 229
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
Please read Application Note 1 General Operating Considerations which covers stability, power supplies, heat
sinking, mounting, current limit, SOA interpretation, and specifcation interpretation. Visit www.Cirrus.com for design
tools that help automate tasks such as calculations for stability, internal power dissipation, current limit, heat sink
selection, Apex Precision Powers complete Application Notes library, Technical Seminar Workbook and Evaluation
Kits.
AMPLIFIER GAIN
When the feedback pin for each channel is connected to the corresponding OUT pin, the gain of the amplifer is
internally set to 65 V/V. The amplifer gain can be increased by connecting a resistor between the feedback and Out
pin. The amplifer gain will be increased approximately 1 V/V for each additional 49.9 added between the feedback
and OUT pin.
SAFE OPERATING AREA
The MOSFET output stage of the MP103 is not limited by second breakdown considerations as in bipolar output
stages. Only thermal considerations and current handling capabilities limit the SOA (see Safe Operating Area
graph). The output stage is protected against transient fyback by the parasitic body diodes of the output stage
MOSFET structure. However, for protection against sustained high energy fyback external fast-recovery diodes
must be used.
S
and -V
S
must be connected physically close to the pins to prevent
local parasitic oscillation in the output stage of the MP103. Use electrolytic capacitors at least 10F per output amp
required. Bypass the electrolytic capacitors with high quality ceramic capacitors (X7R) 0.1F or greater. Duplicate
the supply bypass for the supply terminals of each amplifer channel. A bypass capacitor of 0.1F or greater is rec-
ommended for the +V
AUX
terminal.
CURRENT LIMIT
For proper operation, the current limit resistor (R
LIM
) must be connected as shown in the external connection dia-
gram. For optimum reliability the resistor value should be set as high as possible. The value is calculated as follows;
with the maximum practical value of 30. The current limit function can be disabled by shorting the I
L
pin to the OUT
pin.
R
LIM
= 0.7/I
LIM
POWER SUPPLY PROTECTION
Unidirectional zener diode transient suppressors are recommended as protection on the supply pins. The zeners
clamp transients to voltages within the power supply rating and also clamp power supply reversals to ground.
Whether the zeners are used or not, the system power supply should be evaluated for transient performance in-
cluding power-on overshoot and power-off polarity reversal as well as line regulation. Conditions which can cause
open circuits or polarity reversals on either power supply rail should be avoided or protected against. Reversals or
opens on the negative supply rail is known to induce input stage failure. Unidirectional transzorbs prevent this, and
it is desirable that they be both electrically and physically as close to the amplifer as possible.
SERIES ISOLATION RESISTOR, R
S
To insure stability with all capacitive loads a series isolation resistor should be included between the output and the
load as shown in the external connections drawing. A 1 resistor works well for capacitive loads between 135pF
and 44nF. The resistor will affect the rise and fall time of the output pulse at the capacitive load. This can be com-
pensated for on the input signal.
BACKPLATE GROUNDING
The substrate of the MP103 is an insulated metal substrate. It is required that it be connected to signal ground. This
is accomplished when the ground pin (Pin 32) is properly connected signal ground.
MP108 MP108A
230 MP108U
MP108, MP108A
FEATURES
LOW COST
100 WATT DISSIPATION CAPABILITY
300kHz POWER BANDWIDTH
APPLICATIONS
INKJET PRINTER HEAD DRIVE
PIEZO TRANSDUCER DRIVE
INDUSTRIAL INSTRUMENTATION
REFLECTOMETERS
ULTRA-SOUND TRANSDUCER DRIVE
DESCRIPTION
The MP108 operational amplifer is a surface mount constructed
component that provides a cost effective solution in many indus-
trial applications. The MP108 offers outstanding performance
that rivals much more expensive hybrid components yet has a
footprint of only 4 sq in. The MP108 has many optional features
such as four-wire current limit sensing and external compensation.
The 300 kHz power bandwidth and 10 amp output of the MP108
makes it a good choice for piezo transducer drive applications.
The MP108 is built on a thermally conductive but electrically
insulating substrate that can be mounted to a heat sink.
34-PIN DIP
PACKAGE STYLE FD
TYPICAL APPLICATION
INKJET NOZZLE DRIVE
The MP108's fast slew rate and wide power bandwith make
it an ideal nozzle driver for industrial inkjet printers. The 10 amp
output capability can drive hundreds of nozzles simultaneously.
R1
R12
R9
R10
Q1A Q1B
Q15A Q15B
R2
R11
R8
Q14
Q24
R20
+Vs
-IN
+IN
-Vs
+Vb
R7
Q2
R3
R19
Q23
-Vb
Q3
Q22
R17
R5
Q12 Q13
Q4
Cc2
Cc1
C1
C3
GND
GND
R15
Q17
IC1
+Ilim
-Ilim
D2
Q11
Q16
OUT
-Vb
+Vb
C5
SUBSTRATE
BACKPLATE
+Vs
+Vs
-Vs
-Vs
OUT
OUT
OUT
OUT
OUT
BACK
PLATE
TP
D1
Q8
Q7
Q9
Q6
Q20
Q19
Q21
Q18
8
4
3
2
1
34
5
6
25
33
32
30
11
14
15
16
27
12
13
28
20
21
22
17
18
19
C
C
+V
S
-V
S
OUT
C
C
2
C
C
1
GND
GND
+V
B
+V
S
-V
B
-V
S
-I
LIM
+I
LIM
R
LIM
R
F
R
I
PIEZO
TRANSDUCER
PRINT
NOZZLE
COMMAND
VOLTAGE
-IN +IN
+V
B
-V
B
C
C
2
GND
GND
1 2 3 4 5 6 7 8
31 32 29 30 28 27 26 25 33 34
C
C
1
-I
LIM
+I
LIM
C
C
NOTES:
C
C
IS NPO (COG) RATED FOR FULL SUPPLY VOLTAGE +V
S
TO -V
S
BOTH PINS 3 AND 32 REQUIRED CONNECTED TO SIGNAL GROUND
C2 AND C3 ELECTROLYTIC 10F PER AMP OUTPUT CURRENT
C1,C4,C5-8 HIGH QUALITY CERAMIC 0.1F
ALL OUTPUT PINS MUST BE TIED TOGETHER
VIEW FROM COMPONENT SIDE
PHASE COMPENSATION
GAIN W/O BOOST
1
4
10
C
C
100pF
33pF
10pF
+
C1
C2
C4
+ C3
R
LIM
9 10 11 12
22 24 23 21
+V
S +V
S
+V
S
OUT
NC
13 14 15 16
17 18 19 20
OUT OUT
-V
S
-V
S
-V
S
LOAD &
FEEDBACK
-V
B NC NC
+V
B
TYP. SLEW RATE
55 V/S
135 V/S
170 V/S
OUT OUT OUT
BACK
PLT
TP NC NC NC
NC NC
C5
C6
C7 C8
GAIN W BOOST
1
3
10
C
C
470pF
220pF
33pF
TYP. SLEW RATE
12 V/S
35 V/S
135 V/S
MAY 2009
APEX MP108UREVD
MP108 MP108A
MP108U 231
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SPECIFICATIONS
MP108 MP108A
1
INPUT
OFFSET VOLTAGE 1 5 * 3 mV
OFFSET VOLTAGE vs. temperature Full temperature range 20 50 * * V/C
OFFSET VOLTAGE vs. supply 20 * V/V
BIAS CURRENT, initial
3
100 70 pA
BIAS CURRENT vs. supply 0.1 * pA/V
OFFSET CURRENT, initial 50 30 pA
INPUT RESISTANCE, DC 10
11
*
COMMON MODE VOLTAGE RANGE +V
B
- 15 * V
COMMON MODE VOLTAGE RANGE -V
B
+ 15 * V
COMMON MODE REJECTION, DC 92 * dB
NOISE 1MHz bandwidth, 1k R
S
10 * V RMS
GAIN
OPEN LOOP @ 15Hz R
L
= 10K, C
C
= 10pF 96 * dB
GAIN BANDWIDTH PRODUCT @ 1MHz C
C
= 10pF 10 * MHz
PHASE MARGIN Full temperature range 45 * degrees
OUTPUT
VOLTAGE SWING I
O
= 10A +V
S
- 10 +V
S
- 8.6 * * V
VOLTAGE SWING I
O
= -10A -V
S
+ 10 -V
S
+ 7 * * V
VOLTAGE SWING I
O
= 10A, +V
B
= +V
S
+10V +V
S
- 1.6 * V
VOLTAGE SWING I
O
= -10A, -V
B
= -V
S
-10V -V
S
+ 5.1 * V
CURRENT, continuous, DC 10 11 A
SLEW RATE, A
V
= -20 C
C
= 10pF 150 170 * * V/S
SETTLING TIME, to 0.1% 2V Step 1 * S
RESISTANCE No load, DC 5 *
POWER BANDWIDTH 180V
P-P
C
C
= 10pF, +V
S
= 100V, -V
S
= -100V 300 * kHz
POWER SUPPLY
VOLTAGE 15 75 100 * * * V
CURRENT, quiescent 50 65 * * mA
THERMAL
5
Full temperature range, f 60Hz 1 * C/W
RESISTANCE, DC, junction to case Full temperature range, f < 60Hz 1.25 * C/W
RESISTANCE, junction to air Full temperature range 13 * C/W
TEMPERATURE RANGE, case -40 85 * * C
SUPPLY VOLTAGE, +V
S
to -V
S
200V
SUPPLY VOLTAGE, +V
B
+V
S
+ 15V
6
SUPPLY VOLTAGE, -V
B
-V
S
15V
6
INPUT VOLTAGE +V
B
to -V
B
2
150C.
C
=25C, compensation C
C
=100pF, DC input specifcations are value given, power supply voltage
is typical rating.
to achieve high MTBF.
4. +V
S
and -V
S
denote the positive and negative supply voltages to the output stage. +V
B
and -V
B
denote the positive and negative
supply voltages to the input stages.
5. Rating applies if the output current alternates between both output transistors at a rate faster than 60Hz.
6. Power supply voltages +V
B
and -V
B
must not be less than +V
S
and -V
S
respectively.
MP108 MP108A
232 MP108U
-40 -20 0 20 40 60 80 100
0
20
40
60
80
100
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
POWER DERATING
CASE TEMPERATURE, T
C
(C)
1 10 100
S
-V
O
(V)
1
10
200
0.2
20
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

-
V
S

(
A
)
SAFE OPERATING AREA
1
0
m
S
,

T
C =
2
5
C
D
C
,

T
C =
2
5
C
1
0
0
m
S
,

T
C =
2
5
C
D
C
,

T
C =
8
5
C
-50 -25 0 25 50 75 100
70
80
90
100
110
120
130
N
O
R
M
A
L
I
Z
E
D

C
U
R
R
E
N
T

L
I
M
I
T
,

(
%
)
CASE TEMPERATURE, T
C
(C)
CURRENT LIMIT QUIESCENT CURRENT vs. TEMPERATURE
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
O

(
%
)
0 20 40 60 -20 -40
105
100
95
90
115
80 100
110
QUIESCENT CURRENT vs. SUPPLY
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
O

(
%
)
S
(V)
80 120 160 200 40 0
100
80
60
40
120
T
C
= 85C
T
C
= -40C
T
C
= 25C
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

T
H
D

(
%
)
FREQUENCY, F (Hz)
30 30K 10K 1K 100
A
V
= 20
C
C
= 10pF
V
S
= 52V
R
L
= 4
P
O

=

2
0
0
W
P
O
= 10W
P
O

=

1
0
0
W
1
0.1
0.01
0.001
SMALL SIGNAL RESPONSE W/O BOOST
FREQUENCY, F (Hz)
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
10 1M 100K 10K 1K 100 10M
120
100
80
60
40
20
0
C
C
= 10pF
C
C
= 33pF
C
C
= 100pF
R
L
= 4
I
O
= 1A DC
SMALL SIGNAL RESPONSE W/ BOOST
FREQUENCY, F (Hz)
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
10 1M 100K 10K 1K 100 10M
120
100
80
60
40
20
0
C
C
= 33pF
C
C
= 220pF
C
C
= 470pF
R
L
= 4
I
O
= 1A
1
FREQUENCY, F (Hz)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
200
20
100
10K 100K 1M 5M
POWER RESPONSE
C
C
=

1
0
p
F
C
C
=

3
3
p
F
C
C
=

1
0
0
p
F
C
C
=

2
2
0
p
F
C
C
=

4
7
0
p
F
2
3
2
1
1
PHASE RESPONSE W/ BOOST
FREQUENCY, F (Hz)
P
H
A
S
E
,

)
100K 5M 1M
90
120
150
180
210
1 C
C
= 10pF
2 C
C
= 33pF
3 C
C
= 100pF
R
L
= 4
I
O
= 1A
2
3
2
1
1
PHASE RESPONSE W/O BOOST
FREQUENCY, F (Hz)
P
H
A
S
E
,

)
300K 10M 1M
90
120
150
180
1 C
C
= 10pF
2 C
C
= 33pF
3 C
C
= 100pF
R
L
= 4
I
O
= 1A
OUTPUT CURRENT, I
O
(A)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

(
V
)
9
8
7
6
5
4
3
2
1
0
0 2 4 6 8 10
W/O BOOST FROM +V
S
W
/O
B
O
O
S
T FR
O
M
-V
S
W
ITH BOOST FROM +V
S W
IT
H
B
O
O
S
T
F
R
O
M
-
VS
T
C
= 25C
50mS PULSE
MP108 MP108A
MP108U 233
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
Please read Application Note 1 "General Operating Consid-
erations" which covers stability, power supplies, heat sinking,
dissipation, current limit, heat sink selection, Apex Precision
Power's complete Application Notes library, Technical Seminar
Workbook and Evaluation Kits.
GROUND PINS
The MP108 has two ground pins (pins 3, 32). These pins
provide a return for the internal capacitive bypassing of the
small signal portions of the MP108. The two ground pins are
not connected together on the substrate. Both of these pins
are required to be connected to the system signal ground.
SAFE OPERATING AREA
The MOSFET output stage of the MP108 is not limited by
second breakdown considerations as in bipolar output stages.
Only thermal considerations and current handling capabilities
limit the SOA (see Safe Operating Area graph on previous page).
The output stage is protected against transient fyback by the
parasitic body diodes of the output stage MOSFET structure.
However, for protection against sustained high energy fyback
external fast-recovery diodes must be used.
COMPENSATION
The external compensation capacitor C
C
is connected
between pins 5 and 6. Unity gain stability can be achieved with
any capacitor value larger than 100pF for a minimum phase
margin of 45 degrees. At higher gains more phase shift can
usually be tolerated in most designs and the compensation
capacitor value can be reduced resulting in higher bandwidth
and slew rate. Use the typical operating curves as a guide to
select C
C
for the application. An NPO (COG) type capacitor is
required rated for the full supply voltage (200V).
OVERVOLTAGE PROTECTION
Although the MP108 can withstand differential input voltages
up to 25V, additional external protection is recommended. In
most applications 1N4148 signal diodes connected anti-parallel
across the input pins is sufficient. In more demanding applica-
tions where bias current is important diode connected JFETs
such as 2N4416 will be required. See Q1 and Q2 in Figure 1.
In either case the differential input voltage will be clamped to
0.7V. This is usually sufficient overdrive to produce the maxi-
mum power bandwidth. Some applications will also need over
voltage protection devices connected to the power supply rails.
Unidirectional zener diode transient suppressors are recom-
mended. The zeners clamp transients to voltages within the
power supply rating and also clamp power supply reversals to
ground. Whether the zeners are used or not the system power
supply should be evaluated for transient performance including
power-on overshoot and power-off polarity reversals as well as
line regulation. See Z1 and Z2 in Figure 1.
S
and -V
S

must be connected physically close to the pins to prevent local
parasitic oscillation in the output stage of the MP108. Use
electrolytic capacitors at least 10F per output amp required.
Bypass the electrolytic capacitors with high quality ceramic
capacitors (X7R) 0.1F or greater. In most applications power
supply terminals +V
B
and -V
B
will be connected to +V
S
and
-V
S
respectively. Supply voltages +V
B
and -V
B
are bypassed
internally but both ground pins 3 and 32 must be connected to
the system signal ground to be effective. In all cases power to
the buffer amplifer stage of the MP108 at pins 8 and 25 must
be connected to +V
B
and -V
B
at pins 4 and 30 respectively.
Provide local bypass capacitors at pins 8 and 25. See the
external connections diagram on page 1.
34
33
+Vs
-Vs
OUT
3
32
GND
GND
+Vb
+Vs
-Vb
-Vs
Z1
Z2
-IN
+IN
Q1
Q2
34
OUT
11-13
20-22
33
I
LIM-
I
LIM+
27
28
R
P
R
L
IN
R
F
R
LIM
R
IN
FIGURE 1
FIGURE 2
4 WIRE CURRENT LIMIT
CURRENT LIMIT
resistor R
LIM
as shown in Figure 2. This connection will bypass
any parasitic resistances RP, formed by socket and solder joints
as well as internal amplifer losses. The current limiting resistor
may not be placed anywhere in the output circuit except where
shown in Figure 2. The value of the current limit resistor can
be calculated as follows: R
LIM
= .65/I
LIMIT
BOOST OPERATION
With the boost feature the small signal stages of the amplifer
are operated at a higher supply voltages than the amplifers
high current output stage. +V
B
(pins 4,8) and -V
B
(pins 25,30)
are connected to the small signal stages and +V
S
(pins 14-16)
and -V
S
(pins 17-19) are connected to the high current output
stage. An additional 10V on the +V
B
and -V
B
pins is sufficient
to allow the small signal stages to drive the output stage into
the triode region and improve the output voltage swing for extra
efficient operation when required. When the boost feature is
not needed +V
S
and -V
S
are connected to the +V
B
and -V
B

pins respectively. The +V
B
and -V
B
pins must not be operated
at supply voltages less than +V
S
and -V
S
respectively.
BACKPLATE GROUNDING
The substrate of the MP108 is an insulated metal substrate.
It is required that it be connected to signal ground. Connect pin
2 (back plate) to signal ground. The back plate will then be AC
grounded to signal ground through a 1F capacitor.
MP111
234 MP111U
MP111, MP111A
FEATURES
LOW COST
HIGH OUTPUT CURRENT- 50 AMP PULSE OUTPUT, 15
AMP CONTINUOUS
130 V/uS SLEW RATE
500kHz POWER BANDWIDTH
APPLICATIONS
INKJET PRINTER HEAD DRIVE
PIEZO TRANSDUCER DRIVE
INDUSTRIAL INSTRUMENTATION
REFLECTOMETERS
ULTRA-SOUND TRANSDUCER DRIVE
DESCRIPTION
The MP111 operational amplifer is a surface mount constructed
component that provides a cost-effective solution in many indus-
trial applications. The MP111 offers outstanding performance
that rivals much more expensive hybrid components yet has a
footprint of only 4 sq in. The MP111 has many optional features
such as four-wire current limit sensing and external compensa-
tion. The 500 kHz power bandwidth and 15 amp continuous
and 50A pulse output of the MP111 makes it a good choice
for piezo transducer drive applications. The MP111 is built on
a thermally conductive but electrically insulating substrate that
can be mounted to a heat sink.
34-PIN DIP
PACKAGE STYLE FD
TYPICAL APPLICATION
INKJET NOZZLE DRIVE
The MP111's fast slew rate and wide power bandwith make it
an ideal nozzle driver for industrial inkjet printers. The 50 amp
pulse output capability can drive hundreds of inkjet nozzles
simultaneously.
R1
R12
R9
R10
Q1A Q1B
Q15A Q15B
R2
R11
R8
Q14
Q24
R20
+Vs
-IN
+IN
-Vs
+Vb
R7
Q2
R3
R19
Q23
-Vb
Q3
Q22
R17
R5
Q12 Q13
Q4
Cc2
Cc1
C1
C3
GND
GND
R15
Q17
IC1
+Ilim
-Ilim
D2
Q11
Q16
OUT
-Vb
+Vb
C5
SUBSTRATE
BACKPLATE
+Vs
+Vs
-Vs
-Vs
OUT
OUT
OUT
OUT
OUT
BACK
PLATE
TP
D1
Q8
Q7
Q9
Q6
Q20
Q19
Q21
Q18
8
4
3
2
1
34
5
6
25
33
32
30
11
14
15
16
27
12
13
28
20
21
22
17
18
19
C
C
+V
S
-V
S
OUT
C
C
2
C
C
1
GND
GND
+V
B
+V
S
-V
B
-V
S
-I
LIM
+I
LIM
R
LIM
R
F
R
I
PIEZO
TRANSDUCER
PRINT
NOZZLE
COMMAND
VOLTAGE
-IN +IN
+V
B
-V
B
C
C
2
GND
GND
1 2 3 4 5 6 7 8
31 32 29 30 28 27 26 25 33 34
C
C
1
-I
LIM
+I
LIM
C
C
NOTES:
C
C
S
TO -V
S.
BOTH PINS 3 AND 32 REQUIRED CONNECTED TO SIGNAL GROUND.
C2 AND C3 ELECTROLYTIC 10F PER AMP OUTPUT CURRENT.
C1, C4, C5-8 HIGH QUALITY CERAMIC 0.1F.
ALL OUTPUT PINS MUST BE TIED TOGETHER.
SEE PACKAGE OUTLINE FD IN THE OUTLINE DIMENSIONS DATASHEET.
PHASE COMPENSATION
GAIN W/O BOOST
1
4
10
C
C
100pF
68pF
33pF
R
LIM
9 10 11 12
22 24 23 21
+V
S +V
S
+V
S
OUT
NC
13 14 15 16
17 18 19 20
OUT OUT
-V
S
-V
S
-V
S
LOAD &
FEEDBACK
-V
B NC NC
+V
B
TYP. SLEW RATE
55 V/S
60 V/S
130 V/S
OUT OUT OUT
BACK
PLT
TP NC NC NC
NC NC
C5
C6
C7 C8
GAIN W BOOST
3
6
10
C
C
470pF
220pF
100pF
TYP. SLEW RATE
12 V/S
27 V/S
55 V/S
+
C1
C2
C4
+ C3
MAY 2009
APEX MP111UREVC
MP111
MP111U 235
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SPECIFICATIONS
1
MIN TYP MAX UNITS
INPUT
OFFSET VOLTAGE 1 5 mV
OFFSET VOLTAGE vs. temperature Full temperature range 20 50 V/C
OFFSET VOLTAGE vs. supply 20 V/V
3
100 pA
BIAS CURRENT vs. supply 0.1 pA/V
OFFSET CURRENT, initial 50 pA
11

INPUT CAPACITANCE 4 pF
B
- 15 V
B
+ 15 V
COMMON MODE REJECTION, DC 92 dB
S
10 V RMS
GAIN
OPEN LOOP @ 15Hz R
L
= 10K, C
C
= 33pF 96 dB
C
= 33pF 6 MHz
PHASE MARGIN Full temperature range 45 degrees
OUTPUT
VOLTAGE SWING I
O
= 15A +V
S
- 10 +V
S
- 8.4 V
VOLTAGE SWING I
O
= -15A -V
S
+ 10 -V
S
+ 5.8 V
VOLTAGE SWING I
O
= 15A, +V
B
= +V
S
+10V +V
S
- 0.8 V
VOLTAGE SWING I
O
= -15A, -V
B
= -V
S
-10V -V
S
+ 1.0 V
CURRENT, continuous, DC 15 A
SLEW RATE, A
V
= -20 C
C
= 33pF 100 130 V/S
SETTLING TIME, to 0.1% 2V Step 1 S
RESISTANCE No load, DC 3
POWER BANDWIDTH 80V
P-P
C
C
= 33pF, +V
S
= 50V, -V
S
= -50V 500 kHz
POWER SUPPLY
VOLTAGE 15 45 50 V
CURRENT, quiescent 142 157 mA
THERMAL
5
Full temperature range, f 60Hz .65 C/W
RESISTANCE, DC, junction to case Full temperature range, f < 60Hz .88 C/W
SUPPLY VOLTAGE, +V
S
to -V
S
100V
SUPPLY VOLTAGE, +V
B
+V
S
+ 15V
6
SUPPLY VOLTAGE, -V
B
-V
S
15V
6
INPUT VOLTAGE +V
B
to -V
B
DIFFERENTIAL INPUT VOLTAGE 25V
2
175C.
MP111
236 MP111U
30 100 1K 10K 30K
0.001
0.01
0.1
D
I
S
T
O
R
T
I
O
N
,

T
H
D

(
%
)
FREQUENCY, F (Hz)
HARMONIC DISTORTION
A
V
= 10
C
C
= 33pF
V
S
= 50V
R
L
= 4
P
O

=

1
5
0
W
P
O

=

1
0
W
P
O

=

7
5
W
0 3 6 9 12 15
0
1
2
3
4
5
6
7
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

(
V
)
OUTPUT CURRENT, I
O
(A)
W/O BOOST FROM +V
S
W/O BOOST FROM -V
S
WITH BOOST FROM +V
S
WITH BOOST FROM -V
S
T
C
=25C
50mS PULSE
8
9
1 10
S
-V
O
(V)
10
100
1
50
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

-
V
S

(
A
)
SAFE OPERATING AREA
DC, T
C
=85C
DC, T
C
=25C
10mS, T
C
=25C
1mS, T
C
=25C
100S, T
C
=25C
-40 -20 0 20 40
80
90
100
110
120
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
%
)
CASE TEMPERATURE T
C
(C)
QUIESCENT CURRENT vs. TEMP.
V
S
130
V
B
TOTAL
60 80 100 20 40 60 80 100
84
88
92
96
100
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
%
)
S
(V)
QUIESCENT CURRENT vs. SUPPLY
T
C
= 25C
104
T
C
= 85C
T
C
= -40C
-50 -25 0 25 50 75 100
70
80
90
100
110
120
130
N
O
R
M
A
L
I
Z
E
D

C
U
R
R
E
N
T

L
I
M
I
T
,

(
%
)
CASE TEMPERATURE, T
C
(C)
CURRENT LIMIT
10 100 1K 10K
0
20
40
60
80
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
SMALL SIGNAL RESPONSE W/ BOOST
FREQUENCY, F (Hz)
100K 1M 10M
100
120
1
2
1
3
10 100 1K 10K
0
20
40
60
80
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
SMALL SIGNAL RESPONSE W/O BOOST
FREQUENCY, F (Hz)
100K 1M 10M
100
120
2
3
1
FREQUENCY, F(Hz)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
100
10
10K 100K 1M 5M
POWER RESPONSE
C
C
=
3
3
p
F
C
C
=
6
8
p
F
C
C
=
1
0
0
p
F
C
C
=
2
2
0
p
F
C
C
=
4
7
0
p
F
100K 1M 10M
-180
-150
-120
-90
-60
P
H
A
S
E
,

)
FREQUENCY, F (Hz)
1 C
C
= 33pF
2 C
C
= 68pF
3 C
C
= 100pF
R
L
= 4
I
O
= 1A
2
3
1
10K 100K 1M 10M
-180
-150
-120
-90
-60
P
H
A
S
E
,

)
PHASE RESPONSE W/ BOOST
FREQUENCY, F (Hz)
1
2
3
-40 -20 0 20 40 60 80 100
0
40
80
120
160
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
POWER DERATING
CASE TEMPERATURE, T
C
(C)
180
20
60
100
140
1 C
C
= 33pF
2 C
C
= 68pF
3 C
C
= 100pF
R
L
= 4
I
O
= 1A
1 C
C
= 100pF
2 C
C
= 220pF
3 C
C
= 470pF
R
L
= 4
I
O
= 1A DC
1 C
C
= 33pF
2 C
C
= 68pF
3 C
C
= 100pF
R
L
= 4
I
O
= 1A DC
MP111
MP111U 237
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
GROUND PINS
The MP111 has two ground pins (pins 3, 32). These pins
provide a return for the internal capacitive bypassing of the
small signal portions of the MP111. The two ground pins are
not connected together on the substrate. Both of these pins
are required to be connected to the system signal ground.
SAFE OPERATING AREA
The MOSFET output stage of the MP111 is not limited by
Only thermal considerations and current handling capabilities
limit the SOA (see Safe Operating Area graph on previous page).
The output stage is protected against transient fyback by the
parasitic body diodes of the output stage MOSFET structure.
However, for protection against sustained high energy fyback
external fast-recovery diodes must be used.
COMPENSATION
C
is connected
between pins 5 and 6. Unity gain stability can be achieved with
any capacitor value larger than 100pF for a minimum phase
margin of 45 degrees. At higher gains more phase shift can
usually be tolerated in most designs and the compensation
capacitor value can be reduced resulting in higher bandwidth
and slew rate. Use the typical operating curves as a guide to
select C
C
for the application. An NPO (COG) type capacitor is
required rated for the full supply voltage (100V).
Although the MP111 can withstand differential input voltages
most applications 1N4148 signal diodes connected anti-parallel
across the input pins is sufficient. In more demanding applica-
tions where bias current is important diode connected JFETs
such as 2N4416 will be required. See Q1 and Q2 in Figure 1.
In either case the differential input voltage will be clamped to
0.7V. This is usually sufficient overdrive to produce the maxi-
mum power bandwidth. Some applications will also need over
voltage protection devices connected to the power supply rails.
mended. The zeners clamp transients to voltages within the
power supply rating and also clamp power supply reversals to
ground. Whether the zeners are used or not the system power
S
and -V
S

must be connected physically close to the pins to prevent
local parasitic oscillation in the output stage of the MP111. Use
electrolytic capacitors at least 10F per output amp required.
Bypass the electrolytic capacitors with high quality ceramic
capacitors (X7R) 0.1F or greater. In most applications power
supply terminals +Vb and -Vb will be connected to +V
S
and
-V
S
respectively. Supply voltages +Vb and -Vb are bypassed
internally but both ground pins 3 and 32 must be connected to
the system signal ground to be effective. In all cases power to
the buffer amplifer stage of the MP111 at pins 8 and 25 must
be connected to +Vb and
-Vb at pins 4 and 30 respectively. Provide local bypass
capacitors at pins 8 and 25. See the external connections
diagram on page 1.
CURRENT LIMIT
resistor R
LIM
as shown in Figure 2. This connection will bypass
any parasitic resistances R
P
, formed by socket and solder joints
as well as internal amplifer losses. The current limiting resistor
may not be placed anywhere in the output circuit except where
shown in Figure 2. The value of the current limit resistor can
be calculated as follows: R
LIM
= .65/I
LIMIT
BOOST OPERATION
With the boost feature the small signal stages of the amplifer
are operated at a higher supply voltages than the amplifer's
high current output stage. +Vb (pins 4,8) and -Vb (pins 25,30)
are connected to the small signal stages and +V
S
(pins 14-16)
and -V
S
(pins 17-19) are connected to the high current output
stage. An additional 10V on the +Vb and -Vb pins is sufficient
to allow the small signal stages to drive the output stage into
the triode region and improve the output voltage swing for extra
efficient operation when required. When the boost feature is
not needed +V
S
and -V
S
are connected to the +Vb and -Vb
pins respectively. The +Vb and -Vb pins must not be operated
at supply voltages less than +V
S
and -V
S
respectively.
BACKPLATE GROUNDING
The substrate of the MP111 is an insulated metal substrate.
It is required that it be connected to signal ground. Connect pin
2 (back plate) to signal ground. The back plate will then be AC
grounded to signal ground through a 1F capacitor.
34
33
+Vs
-Vs
OUT
3
32
GND
GND
+Vb
+Vs
-Vb
-Vs
Z1
Z2
-IN
+IN
Q1
Q2
34
OUT
11-13
20-22
33
I
LIM-
I
LIM+
27
28
R
P
R
L
IN
R
F
R
LIM
R
IN
FIGURE 1
FIGURE 2
4 WIRE CURRENT LIMIT
MP230
238 MP230U
MP230
GENERAL DESCRIPTION
The MP230 operational amplifer is a surface mount
constructed component that provides a cost effective
solution in many industrial applications. The MP230
offers outstanding performance that rivals many much
more expensive hybrid components yet has a footprint
of only 4.7 sq in. The MP230 has many optional fea-
tures such as four-wire current limit sensing, a shut-
down control and external compensation. In addition,
the class A/B output stage biasing can be turned off
for lower quiescent current with class C operation in
applications where crossover distortion is less impor-
tant such as when driving motors, for example. A boost
voltage feature biases the output stage for close linear
swings to the supply rail for extra effcient operation.
The MP230 is built on a thermally conductive but elec-
trically insulating substrate that can be mounted to a
heat sink.
FEATURES
LOW COST
APPLICATIONS
MOTOR DRIVE
MAGNETIC DEFLECTION
PROGRAMMABLE POWER SUPPLIES
INDUSTRIAL AUDIO AMPLIFIER
R1
41
42
R11
R7
R9
Q1A Q1B
Q11A Q11B
R2
R10
R8
Q10
Q15
R14
+Vs
-IN
+IN
-Vs
+Vb
R6
Q2
C2
R3
R13
Q14
-Vb
Q3
Q13 R12
R5
Q5 Q6
D1
Q4
Cc1
Cc2
1
4
6
38
C1
C3
40 GND
2 GND
R4
Q17
D2
+I
LIM
36
35
-I
LIM
D3
Q18
Q19 OUT
OUT
12-14
9-11
24-26
27-29
LEVEL
SHIFT
3.9k
R13
R15
Q20
Q21
R16
Q16
7
8
LSD
HSD
Iq 5
Q3A
Q13A
R12A
R5A
+Vs
18-20
OUT
15-17
OUT
30-32
-Vs
21-23
SEP 2009
APEX MP230UREVH
MP230
MP230U 239
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SUPPLY VOLTAGE, +V
S
to -V
S
100 V
SUPPLY VOLTAGE, +V
B
(BOOST) (Note 6) +V
S
+ 15 V
SUPPLY VOLTAGE, -V
B
(BOOST) (Note 6) -V
S
15V V
POWER DISSIPATION, internal, DC 210 W
INPUT VOLTAGE +V
B
to -V
B
V
INPUT
OFFSET VOLTAGE vs. temperature
20 50 V/C
BIAS CURRENT, initial (Note 3) 100 pA
INPUT IMPEDANCE, DC 100 G
S
- 13 V
S
+ 13 V
NOISE 100kHz bandwidth, 1k R
S
5 V RMS
SHUTDOWN, active HSD - LSD 4.5 5 5.5 V
SHUTDOWN, inactive HSD - LSD -0.5 0 0.25 V
GAIN
OPEN LOOP @ 15Hz R
L
= 1K, C
C
= 100pF 96 dB
C
= 100pF 2 MHz
PHASE MARGIN Full temperature range 60
OUTPUT
VOLTAGE SWING I
O
= 30A +V
S
- 10 +V
S
- 7 V
VOLTAGE SWING I
O
= -30A -V
S
+ 10 -V
S
+ 8 V
VOLTAGE SWING I
O
= 30A, +V
B
= +V
S
+10V +V
S
- 1.5 V
VOLTAGE SWING I
O
= -30A, -V
B
= -V
S
-10V -V
S
+ 3.0 V
SLEW RATE, A
V
= -10 C
C
= 100pF 12 15 V/S
SPECIFICATIONS
MP230
240 MP230U
NOTES:
C
= 25C, compensation C
C
= 470pF, DC input specifcations are value
given, power supply voltage is typical rating. Amplifer operated without boost feature.
4. +V
S
and -V
S
denote the + and - output stage supply voltages. +V
B
and -V
B
denote the + and - input
stage supply voltages (boost voltages).
60Hz.
B
and -V
B
S
and -V
S
respectively.
SETTLING TIME, to 0.1% A
V
= -1, 10V Step, C
C
= 470pF 2.5 S
RESISTANCE, open loop DC, 10A Load 0.1
POWER SUPPLY
VOLTAGE 15 45 50 V
CURRENT, quiescent, total 27 35 mA
CURRENT, boost supply 17 mA
CURRENT, shutdown or class C quiescent 17 mA
THERMAL
RESISTANCE, AC, junction to case (Note 5) Full temp range, f 60Hz 0.6 C/W
RESISTANCE, DC, junction to case Full temp range, f < 60Hz 0.7 C/W
RESISTANCE, junction to air Full temp range 14 C/W
-IN +IN
+Vb
-Vb
Cc2
OUT GND
GND
1 2 3 4 5 6 7 8
39 40 37 38 36 35 34 33 41 42
-Vs OUT
Cc1 NC
-Vs -I
LIM
+I
LIM
Cc
NOTES:
C
C
S
TO -V
S
.
C1 AND C4 HIGH QUALITY CERAMIC 0.1F.
SEE TEXT FOR SELECTION OF VALUES FOR Rs1 - Rs4.
PHASE COMPENSATION
GAIN W/O BOOST C
C
1 470pF
220pF 4
100pF 10
+
C1
C2
C4
+
C3
R
LIM
9 10 11 12
30 32 31 29
+Vs +Vs +Vs
-Vs OUT
OUT OUT OUT
NC
20 13 14 15 16 17 18 19
24 23 22 25 26 27 28 21
+Vs +Vs +Vs OUT OUT OUT
-Vs -Vs -Vs OUT OUT OUT
LOAD &
NC NC NC
LSD HSD
FEEDBACK
GAIN W/BOOST TYP. SLEW RATE
8 8V/S
12V/S 15
15V/S 30
Iq
Rs1
Rs4 Rs3
Rs2
42-Pin DIP
Package Style FC
MP230
MP230U 241
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
FREQUENCY, F(Hz)
0
20
40
60
80
100
120
10 100 1K 10K 100K 1M 2M
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
1 - C
C
= 100pF
2 - C
C
= 220pF
3 - C
C
= 470pF
R
L
= 2.5
1
2
3
SMALL SIGNAL RESPONSE W/ BOOST SMALL SIGNAL RESPONSE W/O BOOST
FREQUENCY, F(Hz)
0
20
40
60
80
100
120
10 100 1K 10K 100K 1M 2M
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
1
2
3
1 - C
C
= 100pF
2 - C
C
= 220pF
3 - C
C
= 470pF
R
L
= 2.5
TC
=
2
5
C
TC

=

-
4
0
C
T
C

=

8
5
C
S
(V)
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
%
)
QUIESCENT CURRENT VS SUPPLY
96
97
98
99
100
101
20 40 60 80 100
W
/O
B
O
O
S
T
F
R
O
M
-VS
W/O BOOST FROM +V
S
W
IT
H
B
O
O
S
T
F
R
O
M
-VS
WITH BOOST FROM +V
S
0 5 10 15 20 25 30
0
2
4
6
8
OUTPUT CURRENT, I
O
(A)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

(
V
)
PHASE RESPONSE W/BOOST
P
H
A
S
E

,

(
)
FREQUENCY, F(Hz)
100K 1M 2M
180
150
120
90
C
C
= 470pF
C
C
= 220pF
C
C
= 100pF
R
L
= 2.5
-40 -20 0 20 40 60 80 100
0
50
100
150
200
250
POWER DERATING
CASE TEMPERATURE. T
C
(C)
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
-50 -25 0 25 50 75 100
70
80
90
100
110
120
130
CASE TEMPERATURE. T
C
(
C)
N
O
R
M
A
L
I
Z
E
D

C
U
R
R
E
N
T

L
I
M
I
T
,

(
%
)
CURRENT LIMIT
P
H
A
S
E

,

(
)
FREQUENCY, F(Hz)
100K 1M 2M
180
150
120
90
C
C
= 470pF
C
C
= 220pF
C
C
= 100pF
R
L
= 2.5
POWER RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O
(
V
P
-
P
)
10
100
FREQUENCY, F(Hz)
10K 100K 500K
C
C

=

1
0
0
p
F
C
C

=

2
2
0
p
F
C
C

=

4
7
0
p
F
-40 -20 0 20 40 60 80 100
96
100
104
108
112
116
QUIESCENT CURRENT vs TEMPERATURE
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
%
)
30 100 1K 10K 30K
FREQUENCY, F (Hz)
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

T
H
D

(
%
)
A
V
= 10
C
C
= 100pF
+/-V
S
= 50V
R
L
= 4
P
O
= 1W
P
O
= 10W
P
O
= 200W
0.001
0.01
0.1
1
SAFE OPERATING AREA
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

-
V
S
,

(
A
)
S
- V
O
(V)
1 100 10
5
40
10
1
DC, T
C
= 85C
100mS, T
C
= 25C
DC, T
C
= 25C
200mS, T
C
= 25C
10mS, T
C
= 25C
MP230
242 MP230U
TYPICAL APPLICATION
MOTOR POSITION CONTROL
The MOSFET output stage of the MP230 provides
superior SOA performance compared to bipolar
output stages where secondary breakdown is a
concern. The extended SOA is ideal in motor drive
applications where the back EMF of the motor may
impose simultaneously both high voltage and high
current across the output stage transistors. In the
fgure above a mechanical to electrical feedback po-
sition converter allows the MP230 to drive the motor
in either direction to a set point determined by the
DAC voltage.
GENERAL
Please read Application Note 1 General Operating
Considerations which covers stability, power sup-
plies, heat sinking, mounting, current limit, SOA interpretation, and specifcation interpretation. Visit www.cirrus.
com for design tools that help automate tasks such as calculations for stability, internal power dissipation, current
limit, heat sink selection, Apex Precision Powers complete Application Notes library, Technical Seminar Workbook
GROUND PINS
The MP230 has two ground pins (pins 2, 40). These pins provide a return for the internal capacitive bypassing of
the small signal stages of the MP230. The two ground pins are not connected together on the substrate. Both of
these pins are required to be connected to the system signal ground.
BALANCING RESISTOR SELECTION (R
S1
-R
S4
)
The MP230 uses parallel sets of output transistors. To ensure that the load current is evenly shared among the
transistors external balancing resistors R
S1
-R
S4
are required. To calculate the required value for each of the resistors
use: R = 4.5 / I
2
,where I is the maximum expected output current. For example, with a maximum output current of
10A each balancing resistor should be 0.045 ohms. Each resistor dissipates 1.125W at the maximum current. Use
a non-inductive 2W rated resistor. A ready source for such resistors is the IRC resistor series LR available from
Mouser Electronics.
SAFE OPERATING AREA
stages. Only thermal considerations and current handling capabilities limit the SOA (see Safe Operating Area graph
on previous page). The output stage is protected against transient fyback by the parasitic diodes of the output stage
must be used.
COMPENSATION
C
is connected to pins 4 and 6. Unity gain stability can be achieved with
C
C
= 470pF for a minimum phase margin of 60 degrees. At higher gains more phase shift can usually be tolerated
and C
C
can be reduced resulting in higher bandwidth and slew rate. Use the typical operating curves as a guide to
select C
C
. A 100V NPO (COG) type capacitor is required. Boost operation requires more compensation or higher
gains than with normal operation due to the increased capacitance of the output transistors when the output signal
swings close to the supply rails.
Although the MP230 can withstand differential input voltages up to 25V, in some applications additional external
protection may be needed. 1N4148 signal diodes connected anti-parallel across the input pins is usually suffcient.
In more demanding applications where bias current is important diode connected JFETs such as 2N4416 will be
Cc
42
41
+Vs
-Vs
6
OUT
38
1
DAC OUTPUT
POSITION
COMMAND
2
21-23
27-29
40
36
Cc2
Cc1
GND
GND
+Vb
+Vs
-Vb
-Vs
MOTOR
DRIVE
4
POSITION
FEEDBACK
-I
LIM
+I
LIM
R
LIM
35
*OUT
9-11
15-17
24-26
30-32
*
12-14
18-20
Rs1
Rs2
Rs3
Rs4
MP230
MP230U 243
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
required. See Q1 and Q2 in Figure 1. In either case the differential
input voltage will be clamped to 0.7V. This is suffcient overdrive
to produce the maximum power bandwidth. Some applications will
also need over-voltage protection devices connected to the power
supply rails. Unidirectional zener diode transient suppressors are
recommended. The zeners clamp transients to voltages within
the power supply rating and also clamp power supply reversals
to ground. Whether the zeners are used or not the system power
S
and -V
S
must
be connected physically close to the pins to prevent local para-
sitic oscillation in the output stage of the MP230. Use electrolytic
capacitors at least 10F per output amp required. Bypass the
electrolytic capacitors with high quality ceramic capacitors 0.1F
or greater. In most applications power supply terminals +V
B
and
-V
B
S
and -V
S
respectively. Although +V
B

and -V
B
are bypassed internally it is recommended to bypass +V
B
and -V
B
with 0.1F externally. Additionally, ground
pins 2 and 40 must be connected to the system signal ground.
CURRENT LIMIT
across the current limit sense resistor. For the current limit to work
correctly pin 36 must be connected to the amplifer output side and
pin 35 connected to the load side of the current limit resistor R
LIM

as shown in Figure 2. This connection will bypass any parasitic re-
sistances RP, formed by socket and solder joints as well as internal
amplif er losses.The current limiting resistor may not be placed
anywhere in the output circuit except where shown in Figure 2.
The value of the current limit resistor can be calculated as follows:
R
LIM
= .65/I
LIMIT
BOOST OPERATION
With the boost feature the small signal stages of the amplifer are operated at a higher supply voltages than the
amplifers high current output stage. +V
B
(pin 1) and -V
B
(pin 38) are connected to the small signal stages. An addi-
tional 10V on the +V
B
and -V
B
pin is suffcient to allow the small signal stages to drive the output stage into the triode
region and improve the output voltage swing for extra effcient operation when required. When the boost feature
is not needed +V
S
and -V
S
are connected to +V
B
and -V
B
respectively. +V
B
and -V
B
must not be operated at supply
voltages less than +V
S
and -V
S
respectively.
SHUTDOWN
The output stage is turned off by applying a 5V level to HSD (pin 8) relative to LSD (pin 7). This is a non-latching
circuit. As long as HSD remains high relative to LSD the output stage will be turned off. LSD will normally be tied to
signal ground but LSD may foat from -V
B
to +V
B
- 15V. Shutdown can be used to lower quiescent current for standby
operation or as part of a load protection circuit.
BIAS CLASS OPTION
Normally pin 5 (Iq) is left open. But when pin 5 is connected to pin 6 (Cc1) the quiescent current in the output stage
is disabled. This results in lower quiescent power, but also class C operation of the output stage and the resulting
crossover distortion. In many applications, such as driving motors, the distortion may be unimportant and lower
standby power dissipation is an advantage.
42
41
+Vs
-Vs
OUT
38
1
2
40
GND
GND
+Vb
+Vs
-Vb
-Vs
Z1
Z2
-IN
+IN
Q1
Q2
FIGURE 1: OVERVOLTAGE PROTECTION
42
OUT
41
-I
LIM
+I
LIM
35
36
R
P
R
LIM
R
L
IN
R
F
R
IN
FIGURE 2: 4 WIRE CURRENT LIMIT
MP240
244 MP240U
MP240
GENERAL DESCRIPTION
The MP240 operational amplifer is a surface mount
constructed component that provides a cost effective
solution in many industrial applications. The MP240
offers outstanding performance that rivals much more
expensive hybrid components yet has a footprint of
only 4.7 sq in. The MP240 has many optional fea-
tures such as four-wire current limit sensing, a shut-
down control and external compensation. In addition,
the class A/B output stage biasing can be turned off
for lower quiescent current with class C operation in
applications where crossover distortion is less impor-
tant such as when driving motors, for example. A boost
voltage feature biases the output stage for close linear
swings to the supply rail for extra effcient operation.
The MP240 is built on a thermally conductive but elec-
trically insulating substrate that can be mounted to a
heat sink.
FEATURES
LOW COST
APPLICATIONS
MOTOR DRIVE
MAGNETIC DEFLECTION
INDUSTRIAL AUDIO AMPLIFIER
R1
41
42
R11
R7
R9
Q1A Q1B
Q11A Q11B
R2
R10
R8
Q10
Q15
R14
+Vs
-IN
+IN
-Vs
+Vb
R6
Q2
C2
R3
R13
Q14
-Vb
Q3
Q13 R12
R5
Q5 Q6
D1
Q4
Cc1
Cc2
1
4
6
38
C1
C3
40 GND
2 GND
R4
Q17
D2
+I
LIM
36
35
-I
LIM
D3
Q18
Q19 OUT
OUT
12-14
9-11
24-26
27-29
LEVEL
SHIFT
3.9k
R13
R15
Q20
Q21
R16
Q16
7
8
LSD
HSD
Iq 5
Q3A
Q13A
R12A
R5A
+Vs
18-20
OUT
15-17
OUT
30-32
-Vs
21-23
SEP 2009
APEX MP240UREVH
MP240
MP240U 245
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SUPPLY VOLTAGE, +V
S
to -V
S
200 V
OUTPUT CURRENT, +V
B
(Note 6) +V
S
+ 15V V
POWER DISSIPATION, -V
B
(Note 6) -V
S
- 15V V
INPUT VOLTAGE +V
B
to -V
B
V
INPUT
20 50 V/C
INPUT IMPEDANCE, DC 100 G
B
- 15 V
B
+ 15 V
DIFFERENTIAL INPUT VOLTAGE 25 V
S
5 V RMS
SHUTDOWN, active HSD - LSD 4.5 5 5.5 V
SHUTDOWN, inactive HSD - LSD -0.5 0 0.25 V
GAIN
OPEN LOOP @ 15Hz R
L
= 1K, C
C
= 100pF 96 dB
C
= 100pF 1.8 MHz
OUTPUT
VOLTAGE SWING I
O
= 20A +V
S
- 10 +V
S
- 7 V
VOLTAGE SWING I
O
= -20A -V
S
+ 10 -V
S
+ 8 V
VOLTAGE SWING I
O
= 20A, +V
B
= +V
S
+10V +V
S
- 3.0 +V
S
- 2.0 V
VOLTAGE SWING I
O
= -20A, -V
B
= -V
S
-10V -V
S
+ 6.0 -V
S
+ 5.0 V
SLEW RATE, A
V
= -10 C
C
= 100pF 12 14 V/S
SPECIFICATIONS
MP240
246 MP240U
NOTES:
C
= 25C, compensation C
C
= 680pF, DC input specifcations are value
given, power supply voltage is typical rating. Amplifer operated without boost feature.
4. +V
S
and -V
S
denote the + and - output stage supply voltages. +V
B
and -V
B
denote the + and - input
stage supply voltages (boost voltages).
60Hz.
B
and -V
B
S
and -V
S
respectively.
V
= -1, 10V Step, C
C
= 680pF 5 S
RESISTANCE, open loop DC, 10A Load 0.2
POWER SUPPLY
VOLTAGE 15 75 100 V
CURRENT, quiescent, total 16.5 25 mA
CURRENT, shutdown or class C quiescent 8.5 mA
CURRENT, boost supply 8.5 mA
THERMAL
RESISTANCE, AC, junction to case (Note 5) Full temp range, f 60Hz 0.58 C/W
RESISTANCE, DC, junction to case Full temp range, f < 60Hz 0.73 C/W
-IN +IN
+Vb
-Vb
Cc2
OUT GND
GND
1 2 3 4 5 6 7 8
39 40 37 38 36 35 34 33 41 42
-Vs OUT
Cc1 NC
-Vs -I
LIM
+I
LIM
Cc
NOTES:
C
C
S
TO -V
S
.
C1 AND C4 HIGH QUALITY CERAMIC 0.1F.
SEE TEXT FOR SELECTION OF VALUES FOR Rs1 - Rs4.
PHASE COMPENSATION
GAIN W/O BOOST C
C
1 680pF
330pF 3
100pF 10
+
C1
C2
C4
+
C3
R
LIM
9 10 11 12
30 32 31 29
+Vs +Vs +Vs
-Vs OUT
OUT OUT OUT
NC
20 13 14 15 16 17 18 19
24 23 22 25 26 27 28 21
+Vs +Vs +Vs OUT OUT OUT
-Vs -Vs -Vs OUT OUT OUT
LOAD &
NC NC NC
LSD HSD
FEEDBACK
GAIN W/BOOST TYP. SLEW RATE
3 3V/S
6V/S 6
14V/S 13
Iq
Rs1
Rs4 Rs3
Rs2
42-Pin DIP
Package Style FC
MP240
MP240U 247
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
FREQUENCY
0
20
40
60
80
100
120
10 100 1K 10K 100K 1M 2M
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)1 - C
C
= 100pF
2 - C
C
= 330pF
3 - C
C
= 680pF
R
L
= 2.5
1
2
3
SMALL SIGNAL RESPONSE W/ BOOST SMALL SIGNAL RESPONSE W/O BOOST
FREQUENCY, F(Hz)
0
20
40
60
80
100
120
10 100 1K 10K 100K 1M 2M
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
1
2
3
1 - C
C
= 100pF
2 - C
C
= 330pF
3 - C
C
= 680pF
R
L
= 2.5
W
/O
B
O
O
S
T
F
R
O
M
-VS
W/O BOOST FROM +V
S
W
IT
H
B
O
O
S
T
F
R
O
M
-
VS
W
IT
H
B
O
O
S
T
F
R
O
M
+
VS
0 5 10 15 20
0
2
4
6
OUTPUT CURRENT, I
O
(A)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

(
V
)
T
C
= 25C
50mS PULSE
1
3
5
7
-40 -20 0 20 40 60 80 100
0
50
100
150
POWER DERATING
CASE TEMPERATURE. T
C
(C)
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
-50 -25 0 25 50 75 100
70
80
90
100
110
120
130
CASE TEMPERATURE. T
C
(C)
N
O
R
M
A
L
I
Z
E
D

C
U
R
R
E
N
T

L
I
M
I
T
,

(
%
)
CURRENT LIMIT
-40 -20 0 20 40 60 80 100
90
100
110
120
130
QUIESCENT CURRENT vs TEMPERATURE
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
%
)
30 100 1K 10K 30K
FREQUENCY, F (Hz)
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

T
H
D

(
%
)
A
V
= 16
C
C
= 100pF
+/-V
S
= 60V
R
L
= 8
P
O
= 1W
P
O
= 10W
P
O
= 150W
0.001
0.01
0.1
1
10
10mS, TC = 25C
100mS, TC = 25C
DC, TC = 25C
DC, TC = 85C
P
H
A
S
E

,

(
)
FREQUENCY, F(Hz)
100K 1M 2M
180
150
120
90
C
C
= 680pF
C
C
= 100pF
R
L
= 2.5
C
C
= 330pF
50K
PHASE RESPONSE W/BOOST
P
H
A
S
E

,

(
)
FREQUENCY, F(Hz)
100K 1M 2M
180
150
120
90
C
C
= 680pF
C
C
= 330pF
C
C
= 100pF
R
L
= 2.5
50K
POWER RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O
(
V
P
-
P
)
20
200
FREQUENCY, F(Hz)
1K 100K 500K
C
C

=

1
0
0
p
F
C
C

=

3
3
0
p
F
C
C

=

6
8
0
p
F
10K
100
TC
=
2
5
C
T
C

=

-
4
0
C
TC
=
8
5
C
S
(V)
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
%
)
QUIESCENT CURRENT VS SUPPLY
40
80
120
160
200
0 40 80 120 160 200
SAFE OPERATING AREA
S
- V
O
(V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

-
V
S

(
A
)
1 10 100 200
30
10
1
0.5
200
5
MP240
248 MP240U
TYPICAL APPLICATION
MOTOR POSITION CONTROL
The MOSFET output stage of the MP240 provides supe-
rior SOA performance compared to bipolar output stages
where secondary breakdown is a concern. The extended
SOA is ideal in motor drive applications where the back
EMF of the motor may impose simultaneously both high
voltage and high current across the output stage transis-
tors. In the fgure above a mechanical to electrical feed-
back position converter allows the MP240 to drive the mo-
tor in either direction to a set point determined by the DAC
voltage.
The MP400 is ideally suited to driving both piezo actua-
tion and defection applications off of a single low voltage
supply. The circuit above boosts a system 24V buss to 350V to drive an ink jet print head. The MP400s high speed
defection amplifer is biased for single supply operation by external resistors R2 R6, so that a 0 to 5V DAC can
be used as the input to the amplifer to drive the print head from 0 to >300V.
GENERAL
sinking, mounting, current limit, SOA interpretation, and specifcation interpretation. Visit www.cirrus.com for design
selection, Apex Precision Powers complete Application Notes library, Technical Seminar Workbook and Evaluation
Kits.
GROUND PINS
The MP240 has two ground pins (pins 2, 40). These pins provide a return for the internal capacitive bypassing of
the small signal stages of the MP240. The two ground pins are not connected together on the substrate. Both of
these pins are required to be connected to the system signal ground.
BALANCING RESISTOR SELECTION (R
S1
-R
S4
)
The MP240 uses parallel sets of output transistors. To ensure that the load current is evenly shared among the
transistors external balancing resistors R
S1
-R
S4
are required. To calculate the required value for each of the resistors
use: R = 4.5/I
2
,where I is the maximum expected output current. For example, with a maximum output current of
10A each balancing resistor should be 0.045 ohms. Each resistor dissipates 1.125W at the maximum current. Use
a non-inductive 2W rated resistor. A ready source for such resistors is the IRC resistor series LR available from
Mouser Electronics.
SAFE OPERATING AREA
stages. Only thermal considerations and current handling capabilities limit the SOA (see Safe Operating Area graph
on previous page). The output stage is protected against transient fyback by the parasitic diodes of the output stage
must be used.
COMPENSATION
C
is connected to pins 4 and 6. Unity gain stability can be achieved with
C
C
= 680pF for a minimum phase margin of 60 degrees. At higher gains more phase shift can usually be tolerated
and C
C
can be reduced resulting in higher bandwidth and slew rate. Use the typical operating curves as a guide to
select C
C
. A 200V NPO (COG) type capacitor is required. Boost operation requires more compensation or higher
gains than with normal operation due to the increased capacitance of the output transistors when the output signal
swings close to the supply rails.
Cc
42
41
+Vs
-Vs
6
OUT
38
1
DAC OUTPUT
POSITION
COMMAND
2
21-23
27-29
40
36
Cc2
Cc1
GND
GND
+Vb
+Vs
-Vb
-Vs
MOTOR
DRIVE
4
POSITION
FEEDBACK
-I
LIM
+I
LIM R
LIM
35
*OUT
9-11
15-17
24-26
30-32
*
12-14
18-20
Rs1
Rs2
Rs3
Rs4
MP240
MP240U 249
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Although the MP240 can withstand differential input voltages up to 25V, in
some applications additional external protection may be needed. 1N4148
signal diodes connected anti-parallel across the input pins is usually suf-
fcient. In more demanding applications where bias current is important
diode connected JFETs such as 2N4416 will be required. See Q1 and Q2
in Figure 1. In either case the differential input voltage will be clamped to
0.7V. This is suffcient overdrive to produce the maximum power band-
width. Some applications will also need over-voltage protection devices
connected to the power supply rails. Unidirectional zener diode transient
suppressors are recommended. The zeners clamp transients to voltages
within the power supply rating and also clamp power supply reversals to
ground. Whether the zeners are used or not the system power supply
should be evaluated for transient performance including power-on over-
shoot and power-off polarity reversals as well as line regulation. See Z1
and Z2 in Figure 1.
S
and -V
S
must be connected physically close to the pins to prevent local para-
sitic oscillation in the output stage of the MP240. Use electrolytic capacitors at least 10F per output amp required. Bypass
the electrolytic capacitors with high quality ceramic capacitors 0.1F or greater. In most applications power supply terminals
+V
B
and -V
B
S
and -V
S
respectively. Although +V
B
and -V
B
are bypassed internally it is recommended to
bypass +V
B
and -V
B
with 0.1F externally. Additionally ground pins 2 and 40 must be connected to the system signal ground.
CURRENT LIMIT
The two current limit sense lines are to be connected directly across the cur-
rent limit sense resistor. For the current limit to work correctly pin 36 must
be connected to the amplifer output side and pin 35 connected to the load
side of the current limit resistor R
LIM
as shown in Figure 2. This connection
will bypass any parasitic resistances R
P
, formed by socket and solder joints
as well as internal amplifer losses. The current limiting resistor may not be
placed anywhere in the output circuit except where shown in Figure 2. The
value of the current limit resistor can be calculated as follows: R
LIM
= .65/I
LIMIT
BOOST OPERATION
With the boost feature the small signal stages of the amplifer are operated at a higher supply voltages than the amplifers
B
(pin 1) and -V
B
(pin 38) are connected to the small signal stages. An additional 10V on the +V
B

and -V
B
pin is suffcient to allow the small signal stages to drive the output stage into the triode region and improve the output
voltage swing for extra effcient operation when required. When the boost feature is not needed +V
S
and -V
S
are connected
to +V
B
and -V
B
respectively. +V
B
and -V
B
must not be operated at supply voltages less than +V
S
and -V
S
respectively.
SHUTDOWN
The output stage is turned off by applying a 5V level to HSD (pin 8) relative to LSD (pin 7). This is a non-latching circuit. As
long as HSD remains high relative to LSD the output stage will be turned off. LSD will normally be tied to signal ground but
LSD may foat from -V
B
to +V
B
- 15V. Shutdown can be used to lower quiescent current for standby operation or as part of a
load protection circuit.
BIAS CLASS OPTION
Normally pin 5 (Iq) is left open. But when pin 5 is connected to pin 6 (Cc1) the quiescent current in the output stage is disabled.
This results in lower quiescent power, but also class C operation of the output stage and the resulting crossover distortion.
In many applications, such as driving motors, the distortion may be unimportant and lower standby power dissipation is an
advantage.
42
41
+Vs
-Vs
OUT
38
1
2
40
GND
GND
+Vb
+Vs
-Vb
-Vs
Z1
Z2
-IN
+IN
Q1
Q2
FIGURE 1: OVERVOLTAGE PROTECTION
42
OUT
41
-I
LIM
+I
LIM
35
36
R
P
R
LIM
R
L
IN
R
F
R
IN
FIGURE 2: 4 WIRE CURRENT LIMIT
MP400
250 MP400U
MP400FC
GENERAL DESCRIPTION
The MP400FC combines a high voltage, high speed
precision power op amp with a supply voltage boost
function in an integrated thermally conductive mod-
ule. The voltage boost function uses a switch mode
power supply (SMPS) to boost the input power supply
voltage. This allows the user the benefts of using his
standard 12 V or 24 V buss without the need to de-
sign a high voltage supply to power the op amp. The
SMPS voltage is adjustable from 50-350 V, allowing for
op amp output voltages up to 340 V. External phase
compensation provides the user with the fexibility to
tailor gain, slew rate and bandwidth for a specifc ap-
plication. The unique design of this amplifer provides
extremely high slew rates in pulse applications while
maintaining low quiescent current. The output stage is
well protected with a user defned current limit. Safe
Operating Area (SOA) must be observed for reliable
operation.
FEATURES
Low Cost
Wide Common Mode Range
Standard Supply Voltage
Single Supply: 10 V to 50 V
Output Current - 150 mA Continuous
Output Voltage 50-350 V
350 V/S Slew Rate
200 kHz Power Bandwidth
Applications
Piezoelectric positioning and Actuation
Electrostatic Defection
Deformable Mirror Actuators
Chemical and Biological Stimulators
15 12 13 14 21
24
25
23
22
28 29 30 31 32 33 27 26 34 40 39 41
36
1
2
42
38
37
4
8
C8
AMP
R19
C6
R15
R14
R8
D1
Q2
L1
SMPS
CONTROLLER
R17
R7
Rset Power GND
35
L2
6
Vbias
Vin (10V to 50V)
Analog
GND
-Vs +IN -IN
Vboost
LFin
+Vs
Cr+
Cc+
Out
Ilim
Cc-
Cr-
MP400FC P r o d u c t I n n o v a t i o n F r o m
AUG 2009
APEX MP400UREVE
MP400
MP400U 251
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SUPPLY VOLTAGE, +V
CC
to GND 50 V
OUTPUT CURRENT, peak within SOA 200 mA
POWER DISSIPATION, internal, DC, Amplifer 14.2 W
OUTPUT POWER, SMPS 67 W
INPUT VOLTAGE, Differential -16 16 V
INPUT VOLTAGE, Common Mode -16 16 V
AMPLIFIER INPUT
0 to 85C (Case)
-63 V/C
BIAS CURRENT, initial (Note 3) 8.5 200 pA
6
COMMON MODE VOLTAGE RANGE, pos. +V

S
- 2 V
COMMON MODE VOLTAGE RANGE, neg. -V
S
+ 5.5 V
COMMON MODE REJECTION, DC 90 118 dB
NOISE 700KHz bandwidth 418 V RMS
AMPLIFIER GAIN
OPEN LOOP @ 15 Hz 89 120 dB
GAIN BANDWIDTH PRODUCT @ 1 MHz 1 MHz
AMPLIFIER OUTPUT
VOLTAGE SWING I
O
= 10 mA |V
S
| - 2 V
VOLTAGE SWING I
O
= 100 mA |V
S
| - 8.6 |V
S
| - 12 V
VOLTAGE SWING I
O
= 150 mA |V
S
| - 10 V
CURRENT, continuous, DC 150 mA
SLEW RATE 100 350 V/S
SETTLING TIME, to 0.1% 2 V Step 1 S
RESISTANCE, No load R
LIM
= 6.2 44
POWER BANDWIDTH, 300 V
P-P
+V
S
= 160 V, V
S
= -160 V 200 kHz
CURRENT, quiescent, amplifer only 0.2 0.7 2.5 mA
SPECIFICATIONS
MP400
252 MP400U
NOTES:
C
= 25C).
3. Doubles for every 10
o
C of temperature increase.
4. +V
S
and V
S
denote the positive and negative supply voltages to the output stage.
SMPS
INPUT VOLTAGE, V
IN
10 50 V
SMPS OUTPUT VOLTAGE, V
B
46.75 365 V
SMPS OUTPUT CURRENT, I
S
V
B
= 10x V
IN
150 mA
OUTPUT VOLTAGE TOLERANCE V
B
10x V
IN
, I
S
150 mA,
R
SET
= 1%
+/-2 6.5 %
VOLTAGE BOOST 10 x input V
THERMAL
RESISTANCE, DC, junction to case Full temperature range, f<60Hz 7.7 8.8 C/W
TEMPERATURE RANGE, case 0 70 C
SPECIFICATIONS, (cont).
6 7 8 9 10 5 4 3 2 1 16 17 18 19 20 15 14 13 12 11
37 36 35 34 33 38 39 40 41 42 27 26 25 24 23 28 29 30 31 32 22 21
C
C
- C
C
+
Power GND
C
IN 10V-50V
C1
R
LIM
TO LOAD
AND
FEEDBACK
+
V
B
I
A
S
V
I
N
A
G
N
D
R
S
E
T
C
C
-
-
V
S
-
I
N
+
I
N
C
R
-
C
R
+
C
C
+
P
G
N
D
P
G
N
D
P
G
N
D
P
G
N
D
P
G
N
D
P
G
N
D
P
G
N
D
P
G
N
D
V
I
N
V
I
N
V
I
N
V
B
+
V
S

I
L
I
M

O
U
T

+
Cboost
L
F
I
N
Q
2
D
Q
2
D
Q
2
D
Q
2
D
Analog GND
42-Pin DIP
Package Style FC
MP400
MP400U 253
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
21 - 23, 25 V
IN
Input voltage pins for the on board high voltage switch mode power supply.
24 V
BIAS
Input voltage pin for the boost controller circuitry. This pin is typically tied to V
IN
12 15 Q2D Drain node of the SMPS MOSFET switch. An external RC snubber may be connect from this
node to power ground to reduce or eliminate overshoot and ringing at switch turn off, reducing
switching noise on the SMPS.
8 V
B
This is the output of the high voltage SMPS and typically is tied to pin 6, L
FIN
. Other loads can
be added to this pin as long as the maximum output power of the SMPS is not exceeded. For
proper operation, an external high voltage, low ESR capacitor must be connected to this pin.
Refer to the paragraph titled SMPS Output Capacitor.
6 L
FIN
The high voltage SMPS, V
B
, is connected to this pin to power the MP400FC amplifer through a
47 H flter inductor. The supply current in to this pin can not exceed 200 mA.
4 +V
S
MP400FC amplifer high voltage supply pin. This pin is used for external supply bypass. A high
quality ceramic capacitor of at least 1uF should be used. The high voltage SMPS, V
B
, can be
connected directly to this pin, bypassing the 47 H flter inductor.
34 R
SET
SMPS voltage set resistor. A resistor is connected from this pin to power ground to set the SMPS
voltage.
26 33 PGND Power ground. SMPS switching circuits are referenced to ground through these pins.
35 AGND Analog ground for MP400FC amplifer circuits. AGND and PGND are connected at one point on
the MP400FC. Avoid external connections between AGND and PGND.
41 -V
S
This pin is typically connected to AGND. However, an external negative supply voltage can be
connected to this pin.
39 +IN Amplifer non-inverting input
40 -IN Amplifer inverting input
1 V
OUT
Amplifer output
2 I
LIM
Amplifer current limit. A current limit resistor must be connected between I
LIM
and V
OUT
. R
LIM
=
0.7/I
LIM
.
36 C
R
+ + side compensation capacitor connection one.
37 C
C
+ + side compensation capacitor connection two.
38 C
R
- - side compensation capacitor connection one.
42 C
C
- - side compensation capacitor connection two.
Unused pins should be left open. This is mandatory for pins 3, 5, 7, 9, 11 and 16.
TYPICAL APPLICATION
The MP400FC is ideally suited to driv-
ing both piezo actuation and defection
applications off of a single low volt-
age supply. The circuit above boosts a
system 24 V buss to 350 V to drive an
ink jet print head. The MP400FCs high
speed defection amplifer is biased for
single supply operation by external re-
sistors R2 R6, so that a 0 to 5 V DAC
can be used as the input to the amplifer
to drive the print head from 0 to >300 V.
R1
402K
R
CL
DEFLECTION
PLATE
INK
DROPLETS
SMPS
CIRCUIT
Vin = 24V
0-5V
DAC
MP400
C
C
C
C
+350V
R2
124K
1W
R3
124K
1W
R6
402K
R5
5.62K
R4
5.62K
0.0
470F
100F
Rset PGND
Vboost
PIN DESCRIPTIONS
MP400
254 MP400U
COMMON MODE REJECTION
0
20
40
60
80
100
120
140
FREQUENCY (Hz)
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N

(
d
B
)
1 10 100 1K 10K 100K
0
2
4
6
8
10
12
0 50 100 150 200
PEAK TO PEAK LOAD CURRENT (mA)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y

(
V
)
+V
S
SIDE DROP
-V
S
SIDE DROP
0 50 75 100
CASE TEMPERATURE, T
C
(C)
4
2
0
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
D

(
W
)
25
6
AMPLIFIER INTERNAL POWER DERATING
8
16
10
12
14
+V
S
100 1K 10K
FREQUENCY, (Hz)
40
20
0
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N

(
d
B
)
60
POWER SUPPLY REJECTION
100
80
-V
S
0 4 6 8 10
RESISTOR ()
80
40
0
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
m
A
)
2
120
CURRENT LIMIT
160
-V
S
+V
S
12 14
GAIN = -100
1 100 1000
FREQUENCY, (KHz)
200
150
100
50
0
O
U
T
P
U
T

V
O
L
T
A
G
E
,

(
V
)300
250
POWER RESPONSE
350
GAIN = -50
10
NO COMPENSATION
0 50 75 100
CASE TEMPERATURE, T
C
(C)
20
10
0
S
M
P
S

O
U
T
P
U
T

P
O
W
E
R
,

P
O

(
W
)
25
30
SMPS POWER DERATING
40
70
50
60
SMPS CURRENT VS. SMPS VOLTAGE
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
BOOST SUPPLY VOLTAGE, V
B
(V)
S
M
P
S

C
U
R
R
E
N
T
,

I
S

(
A
)
Limit of L
FIN
filter inductor,
and MP400 amplifier.
V
I
N

=
1
2
V
V
IN
=
2
4
V
V
IN
=
4
8
V
C
BOOST
= 470uF
50 300 250 200 150 100 350
EFFICIENCY Vs. SMPS CURRENT
55
60
65
70
0.05 0.1 0.15 0.2
I
O
E
F
F
I
C
I
E
N
C
Y

(
%
)
V
IN
= 48V
V
B
= 350V
50
55
60
65
70
0.05 0.1 0.15 0.2
I
O
E
F
F
I
C
I
E
N
C
Y

(
%
)
V
IN
= 24V
V
B
= 240V
55
60
65
70
0.05 0.1 0.15 0.2
E
F
F
I
C
I
E
N
C
Y

(
%
)
V
IN
= 12V
V
B
= 120V
I
O
MP400
MP400U 255
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
-35
-25
-15
-5
5
15
25
35
G
A
I
N
,
d
B
C
C
=0pF
C
C
=1pF
C
C
=2.2pF
C
C
=10pF
C
C
=22pF
C
C
=5pF
LARGE SIGNAL GAIN vs. COMPENSATION, V
O
= 50V
P-P
A
V
=+26
R
BIAS
=100K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
V
S
=50V
FREQUENCY, KHz
10 1K 100 10K
-35
-25
-15
-5
5
15
25
35
G
A
I
N
,
d
B
C
C
=0pF
C
C
=1pF
C
C
=2.2pF
C
C
=10pF
C
C
=22pF
C
C
=5pF
SMALL SIGNAL GAIN vs. COMPENSATION, V
O
= 5V
P-P
A
V
=+26
R
BIAS
=100K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
V
S
=50V
FREQUENCY, KHz
10 1K 100 10K
FREQUENCY, KHz
10 1K 100
-35
-25
-15
-5
5
15
25
35
45
G
A
I
N
,
d
B
C
C
=0pF
C
C
=1pF
C
C
=2.2pF
C
C
=10pF
C
C
=22pF
C
C
=5pF
O
= 500mV
P-P
A
V
=+26
R
BIAS
=100K
R
C
=3.3K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
V
S
=50V
10K
GAIN vs. INPUT/OUTPUT SIGNAL LEVEL
-25
-15
-5
5
15
25
35
45
G
A
I
N
,

d
B
500 mV
P-P
50 V
P-P
5 V
P-P
A
V
=+51
R
BIAS
=100K
R
C
=OPEN
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=50V
FREQUENCY, KHz
10 1K 100 10K
SMALL SIGNAL OPEN LOOP PHASE
-90
-60
-30
0
30
60
90
120
150
180
P
H
A
S
E
,

C
S
=68pF
P
IN
=-40dBm
R
BIAS
=100K
R
S
= 48.7
V
S
=50V
FREQUENCY, KHz
100 1000 10 1
R
C
=OPEN, C
C
=0pF
R
C
=3.3K, C
C
=1pF
R
C
=3.3K, C
C
=2.2pF
R
C
=3.3K, C
C
=5pF
R
C
=3.3K, C
C
=10pF
R
C
=3.3K, C
C
=22pF
SMALL SIGNAL OPEN LOOP PHASE, V
O
= 250mV
P-P
-90
-60
-30
0
30
60
90
120
150
180
P
H
A
S
E
,

C
S
=68pF
P
IN
=-40dBm
R
BIAS
=OPEN
R
S
= 48.7
FREQUENCY, KHz
100 1000 10 1
R
C
=OPEN, C
C
=0pF
R
C
=3.3K, C
C
=1pF
R
C
=3.3K, C
C
=2.2pF
R
C
=3.3K, C
C
=5pF
R
C
=3.3K, C
C
=10pF
R
C
=3.3K, C
C
=22pF
SMALL SIGNAL OPEN LOOP GAIN
-20
0
20
40
60
80
100
FREQUENCY, KHz
100
G
A
I
N
,

D
b
C
S
=68pF
P
IN
=-40dBm
R
BIAS
=OPEN
R
S
= 48.7
V
S
=50V
1000 10 1
R
C
=OPEN, C
C
=0pF
R
C
=3.3K, C
C
=1pF
R
C
=3.3K, C
C
=2.2pF
R
C
=3.3K, C
C
=5pF
R
C
=3.3K, C
C
=10pF
R
C
=3.3K, C
C
=22pF
MP400
256 MP400U
RISE AND FALL TIME (10% - 90%)
0
0.2
0.4
0.6
0.8
1
T
i
m
e
,

s
TR
TF
A
V
=+51
C
L
=8pF
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
0 2 4 6 8 10 12 14 16
PEAK-TO-PEAK INPUT VOLTAGE
SR+/SR- (25% - 75%)
SR+
SR-
A
V
=+26
C
L
=8pF
R
F
=35.6K
R
G
=1.5K
R
L
=50K
V
S
=150V
0 2 4 6 8 10 12 14 16
0
200
400
600
800
1000
S
R
,

V
/
s
SR+/SR- (25% -75%)
SR+
SR-
A
V
=+51
C
L
=8pF
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
0 2 4 6 8 10 12 14 16
0
200
400
600
800
1000
S
R
,

V
/
s
SR+/SR- (25% - 75%)
0
200
400
600
800
1000
SR+
SR-
S
R
,

V
/
s
A
V
=+101
C
L
=8pF
R
F
=25K
R
G
= 250
R
L
=50K
V
S
=150V
0 2 4 6 8 10 12 14 16
PULSE RESPONSE vs. C
C
AND R
C
-150
-120
-90
-60
-30
0
30
60
90
120
150
-2.4
-1.8
-1.2
-0.6
0
0.6
1.2
1.8
2.4
3.0
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
I
N
P
U
T

V
O
L
T
A
G
E
,

V
TIME, s
0 1 2 3 4 5 6 -1 -2 7 8
A
V
=+51
C
C
=68pF
C
L
=330pF
R
C
= 48
R
F
=75K
R
G
=1.5K
R
L
=OPEN
V
S
=150V
Out - 0pF
Out - 1pF & 3.3K
Out - 5pF & 3.3K
input
-3.0
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
I
N
P
U
T

V
O
L
T
A
G
E
,

V
TIME, s
-150
-100
-50
0
50
100
150
TRANSIENT RESPONSE
-8
-6
-4
-2
0
2
4
6
8
A
V
=+26
C
C
=2.2pF
C
L
=8pF
R
C
=3.3K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
10V
P-P
input10
-2 0 2 4 6 8 10 12 -4
2V
P-P
input2
TIME, s
-30
-20
-10
0
10
20
30
-1.5
-1
-0.5
0
0.5
1
1.5
TRANSIENT RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
I
N
P
U
T

V
O
L
T
A
G
E
,

V
A
V
=+26
C
C
=2.2pF
C
L
=8pF
R
C
=3.3K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
-2 0 2 4 6 8 10 12 -4
1V
P-P
input1
-15
-10
-5
0
5
10
15
TIME, s
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
I
N
P
U
T

V
O
L
T
A
G
E
,

V
-2 0 2 4 6 8 10 12 -4
TRANSIENT RESPONSE
A
V
=+26
C
C
=2.2pF
C
L
=8pF
R
C
=3.3K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
MP400
MP400U 257
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
TIME, s
0 30 10 8 6 4 2 -2 -6 -4 28 26 24 22 20 18 16 14 12
PULSE RESPONSE vs. CAP LOAD
A
V
=-50
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
300pF, 1V
P-P
200pF, 1V
P-P
100pF, 1V
P-P
-80
-60
-40
-20
0
20
40
60
80
100
120
140
O
U
T
P
U
T
,

V
-80
-60
-40
-20
0
20
40
60
80
100
120
140
O
U
T
P
U
T
,

V
300pF, 2V
P-P
200pF, 2V
P-P
100pF, 2V
P-P
A
V
=-50
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
C
L
=8pF
TIME, s
0 30 10 8 6 4 2 -2 -6 -4 28 26 24 22 20 18 16 14 12
A
V
=-50
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
-80
-60
-40
-20
0
20
40
60
80
100
120
140
TIME, s
O
U
T
P
U
T
,

V
300pf, 3V
P-P
200pf, 3V
P-P
100pf, 3V
P-P
0 30 10 8 6 4 2 -2 -6 -4 28 26 24 22 20 18 16 14 12
SUPPLY CURRENT vs. FREQUENCY
0
5
10
15
20
25
30
1000 100 10
Frequency, (KHz sine wave)
V
IN
=3V
P
A
V
=+51
C
L
=8pF
C
S
=68pF
R
F
=75K
R
G
=1.5K
R
L
=50K
R
S
= 48.7
V
S
=150V
I
S
,

m
A
V
IN
=6V
P
I
S
vs. V
IN
0
2
4
6
8
10
12
14
16
18
V
IN
, V
P-P
(100KHz sine wave)
A
V
=+51
C
L
=8pF
C
S
=68pF
R
F
=75K
R
G
=1.5K
R
L
=50K
R
S
= 48.7
V
S
=150V
I
S
,

m
A
1 9 8 7 6 5 4 3 2 0
OVERDRIVE RECOVERY
-300
-200
-100
0
100
200
300
TIME, s
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
-6
-4
-2
0
2
4
6
I
N
P
U
T

V
O
L
T
A
G
E
,

V
OUTPUT
INPUT
A
V
=+51
C
C
=OPEN
C
L
=8pF
R
C
=OPEN
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
-4 12 10 8 6 4 2 0 -2 -6
PULSE RESPONSE
-0.05
0
0.05
0.1
0.15
0.2
TIME,s
I
S
,

A
6 0 -1
A
V
=+51
C
L
=8pF
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
5 4 3 2 1
SR+/SR- (25%-75%)
0
200
400
600
800
1000
1200
1400
1600
INPUT VOLTAGE, VOLTS PEAK-TO-PEAK
V
/
s
SR+(A
V
=-50)
SR-(A
V
=-50)
SR+(A
V
=+51)
SR-(A
V
=+51)
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
C
L
=8pF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SR+/SR- (25%-75%)
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
C
L
=8pF
0
200
400
600
800
1000
1200
PEAK TO PEAK INPUT VOLTAGE
S
R
+
/
S
R
-

V
/
s
SR+(A
V
=-25)
SR-(A
V
=-25)
SR+(A
V
=+26)
SR-(A
V
=+26)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MP400
258 MP400U
0
5
10
15
20
25
30
1000 100 10
V
IN
=3V
P
A
V
=+51
C
L
=8pF
C
S
=68pF
R
F
=75K
R
G
=1.5K
R
L
=50K
R
S
= 48.7
V
S
=150V
I
S
,

m
A
V
IN
=6V
P
I
S
vs. V
IN
0
2
4
6
8
10
12
14
16
18
V
IN
, V
P-P
(100KHz sine wave)
A
V
=+51
C
L
=8pF
C
S
=68pF
R
F
=75K
R
G
=1.5K
R
L
=50K
R
S
= 48.7
V
S
=150V
I
S
,

m
A
1 9 8 7 6 5 4 3 2 0
OVERDRIVE RECOVERY
-300
-200
-100
0
100
200
300
TIME, s
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
-6
-4
-2
0
2
4
6
I
N
P
U
T

V
O
L
T
A
G
E
,

V
OUTPUT
INPUT
A
V
=+51
C
C
=OPEN
C
L
=8pF
R
C
=OPEN
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
-4 12 10 8 6 4 2 0 -2 -6
PULSE RESPONSE
-0.05
0
0.05
0.1
0.15
0.2
TIME,s
I
S
,

A
6 0 -1
A
V
=+51
C
L
=8pF
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
5 4 3 2 1
SR+/SR- (25%-75%)
0
200
400
600
800
1000
1200
1400
1600
V
/
s
SR+(A
V
=-50)
SR-(A
V
=-50)
SR+(A
V
=+51)
SR-(A
V
=+51)
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
C
L
=8pF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SR+/SR- (25%-75%)
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
C
L
=8pF
0
200
400
600
800
1000
1200
S
R
+
/
S
R
-

V
/
s
SR+(A
V
=-25)
SR-(A
V
=-25)
SR+(A
V
=+26)
SR-(A
V
=+26)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
GENERAL
Please read Application note 1 General operating considerations which covers stability, power supplies,
heat sinking, mounting, current limit, SOA interpretation, and specifcation interpretation. Visit www.cirrus.com for
design tools that help automate tasks such as calculations for stability, internal power dissipation, and current limit.
There you will also fnd a complete application notes library, technical seminar workbook, and evaluation kits.
THEORY OF OPERATION
The PA78 is designed specifcally as a high speed pulse amplifer. In order to achieve high slew rates with low idle
current, the internal design is quite different from traditional voltage feedback amplifers. Basic op amp behaviors
like high input impedance and high open loop gain still apply. But there are some notable differences, such as signal
dependent supply current, bandwidth and output impedance, among others. The impact of these differences varies
depending on application performance requirements and circumstances. These different behaviors are ideal for
some applications but can make designs more challenging in other circumstances.
SUPPLY CURRENT AND BYPASS CAPACITANCE
A traditional voltage feedback amplifer relies on fxed current sources in each stage to drive the parasitic capaci-
tances of the next stage. These currents combine to defne the idle or quiescent current of the amplifer. By design,
these fxed currents are often the limiting parameter for slew rate and bandwidth of the amplifer. Amplifers which
are high voltage and have fast slew rates typically have high idle currents and dissipate notable power with no sig-
nal applied to the load. At the heart of the PA78 design is a signal dependent current source which strikes a new
balance between supply current and dynamic performance. With small input signals, the supply current of the PA78
is very low, idling at less than 1 mA. With large transient input signals, the supply currents increase dramatically to
allow the amplifer stages to respond quickly. The Pulse Response plot in the typical performance section of this
datasheet describes the dynamic nature of the supply current with various input transients.
Choosing proper bypass capacitance requires careful consideration of the dynamic supply currents. High frequency
ceramic capacitors of 0.1 F or more should be placed as close as possible to the amplifer supply pins. The in-
ductance of the routing from the supply pins to these ceramic capacitors will limit the supply of peak current during
transients, thus reducing the slew rate of the PA78. The high frequency capacitance should be supplemented by
additional bypass capacitance not more than a few centimeters from the amplifer. This additional bypass can be
a slower capacitor technology, such as electrolytic, and is necessary to keep the supplies stable during sustained
output currents. Generally, a few microfarad is suffcient.
SMALL SIGNAL PERFORMANCE
The small signal performance plots in the typical performance section of this datasheet describe the behavior when
the dynamic current sources described previously are near the idle state. The selection of compensation capacitor
directly affects the open loop gain and phase performance.
Depending on the confguration of the amplifer, these plots show that the phase margin can diminish to very low
levels when left uncompensated. This is due to the amount of bias current in the input stage when the part is in
standby. An increase in the idle current in the output stage of the amplifer will improve phase margin for small sig-
nals although will increase the overall supply current.
MP400
MP400U 259
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Current can be injected into the output stage by adding a resistor, R
BIAS
, between C
C
- and V
S
+. The size of R
BIAS
will
depend upon the application but 500 A (50 V V+ supply/100K) of added bias current shows signifcant improve-
ment in the small signal phase plots. Adding this resistor has little to no impact on small signal gain or large signal
performance as under these conditions the current in the input stage is elevated over its idle value. It should also
be noted that connecting a resistor to the upper supply only injects a fxed current and if the upper supply is fxed
and well bypassed. If the application includes variable or adjustable supplies, a current source diode could also be
used. These two terminal components combine a JFET and resistor connected within the package to behave like
a current source.
As a second stability measure, the PA78 is externally compensated and performance can be optimized to the ap-
plication. Unlike the R
BIAS
technique, external phase compensation maintains the low idle current but does affect
the large signal response of the amplifer. Refer to the small and large signal response plots as a guide in making
the tradeoffs between bandwidth and stability. Due to the unique design of the PA78, two symmetric compensation
networks are required. The compensation capacitor C
C
must be rated for a working voltage of the full operating
supply voltage (+V
S
to V
S
). NPO capacitors are recommended to maintain the desired level of compensation over
temperature.
The PA78 requires an external 33 pF capacitor between C
C
- and -V
S
to prevent oscillations in the falling edge of the
output. This capacitor should be rated for the full supply voltage (+V
S
to -V
S
).
LARGE SIGNAL PERFORMANCE
As the amplitude of the input signal increases, the internal dynamic current sources increase the operation band-
width of the amplifer. This unique performance is apparent in its slew rate, pulse response, and large signal perfor-
mance plots. Recall the previous discussion about the relationships between signal amplitude, supply current, and
slew rate. As the amplitude of the input amplitude increases from 1 V
P-P
to 15 V
P-P
, the slew rate increases from 50
V/s to well over 350 V/s.
Notice the knee in the Rise and Fall times plot, at approximately 6 V
P-P
input voltage. Beyond this point the output
becomes clipped by the supply rails and the amplifer is no longer operating in a closed loop fashion. The rise and
fall times become faster as the dynamic current sources are providing maximum current for slewing. The result of
this amplifer architecture is that it slews fast, but allows good control of overshoot for large input signals. This can
be seen clearly in the large signal Transient Response plots.
HEATSINKING AND SAFE OPERATING AREA
The MOSFET output stage of the PA78 is not limited by second break-
down considerations as in bipolar output stages. Only thermal con-
siderations of the package and current handling capabilities limit the
Safe Operating Area. The SOA plots include power dissipation limita-
tions which are dependent upon case temperature. Keep in mind that
the dynamic current sources which drive high slew rates can increase
the operating temperature of the amplifer during periods of repeated
slewing. The plot of supply current vs. input signal amplitude for a 100
kHz signal provides an indication of the supply current with repeated
slewing conditions. This application dependent condition must be con-
sidered carefully.
The output stage is self-protected against transient fyback by the para-
sitic body diodes of the output stage. However, for protection against
sustained high energy fyback, external, fast recovery diodes must be
used.
CURRENT LIMIT
For proper operation, the current limit resistor, R
LIM
, must be connected as shown in the external connections dia-
gram. For maximum reliability and protection, the largest resistor value should be used. The maximum practical
value for R
LIM
is about 12 . However, refer to the SOA curves for each package type to assist in selecting the op-
timum value for Rlim in the intended application. Current limit may not protect against short circuit conditions with
supply voltages over 200 V.
SOA
0
20
40
60
80
100
120
140
160
10 100 1000
O
U
T
P
U
T

C
U
R
R
E
N
T

(
m
A
)
S
-V
O
(V)
25C
125C
75C
MP400
260 MP400U
LAYOUT CONSIDERATIONS
The PA78 is built on a dielectrically isolated process and the package tab is therefore not electrically connected
to the amplifer. For high speed operation, the package tab should be connected to a stable reference to reduce
capacitive coupling between amplifer nodes and the foating tab. It is often convenient to directly connect the tab
to GND or one of the supply rails, but an AC connection through a 1F capacitor to GND is also suffcient if a DC
connection is undesirable
Care should be taken to position the R
C
/ C
C
compensation networks close
to the amplifer compensation pins. Long loops in these paths pick up noise
and increase the likelihood of LC interactions and oscillations.
SMPS OPERATION
The MP400FC is designed to operate off of a standard voltage rail. Typi-
cal values include 12 V, 24 V, or 48 V. The addition of the on-board SMPS
eliminates the need to design or purchase a high voltage power supply. The
only inputs required by the SMPS are the V
IN
source. Input and output flter
capacitor, and boost voltage set resistor (R
SET
).
The SMPS output can be adjusted between a minimum of 50 V to a max-
imum of 350 V. The voltage boost adjustment is independent of V
IN
. Ad-
justment to the boost level is made through a resistor from the R
SET
pin to
ground. The resistor value is:
Where V
BOOST
= desired SMPS voltage.
Example: 1) Desired V
BOOST
= 160 V
2) R
SET
= 1K (1066 by equation)
If R
SET
is open, V
BOOST
will be 50 V. If R
SET
is shorted to ground V
BOOST
will be limited to 350 V.
Note that while the MP400 SMPS generates a positive voltage from 50 V to 350 V, the amplifer may operate from
a variety of supply voltages. Symmetric, asymmetrical and single supply confgurations can be used so long as the
total supply voltage from +V
S
to -V
S
does not exceed 350 V. The amplifer performance graphs in this datasheet
include some plots taken with symmetrical supplies, but those plots generally apply to all supply confgurations.
SMPS OUTPUT CAPACITOR
An external SMPS output flter capacitor is required for proper operation. ESR considerations prevail in the choice
of the output flter capacitor. Select the highest value capacitor that meets the following ESR requirement. The
minimum value for C
BOOST
is 100 F.
ESR = dVo/I
LPK
Where,
dVo = The maximum acceptable output ripple voltage
I
LPK
= Peak inductor current = (1/L) V
IN
ton
L = 10
-6
if the internal inductor is used.
V
IN
= Input voltage of the application.
ton = (2 Io L ((Vo + 0.6 - V
IN
)/(F
SW
V
IN
2
)))
V
BOOST
= The boost supply voltage of the application.
I
O
= The maximum continuous output current for the application.
F
SW
= 100 KHz switching frequency of the MP400FC boost supply.
SMPS Output vs. RSET
1
10
100
1000
10000
100000
VBoost (V)
R
S
E
T

(
)
50 100 150 200 250 300 350
R
SET
= - 615
1.85 10
5
V
BOOST
- 49.95
MP400
MP400U 261
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SMPS INPUT CAPACITOR
An external input capacitor is required. This capacitor should be at least 100 F.
THERMAL CONSIDERATIONS
For reliable operation the MP400FC will require a heatsink for most applications. When choosing the heatsink the
power dissipation in the op amp and the SMPS MOSFET switch (Q2) are both considered. The power dissipation of
the op amp is determined in the same manner as any power op amp. The power dissipation of the MOSFET switch
(Q2) is the sum of the power dissipation due to conduction and the switching power.
P
D(Q2)
= (I
IN(pk)
2
R
DS(ON)
D) + (I
IN(pk)
V
IN
t
r
F
SW
)
Where:
V
IN
= SMPS input voltage
V
B
= SMPS output voltage
I
O
= Total SMPS output current
F
SW
= 100 KHz
R
DS(ON)
= 0.621
t
r
= 82 x 10
-9
s
D = t
1
F
SW
t
1
= 2 I
O
10 x 10
-6

(

)
V
B
- V
IN
F
SW
V
IN
2
I
IN(pk)
=
V
B
t
d
10 x 10
-6
t
d
=t
1

(

)
- t
1
V
B
V
B
- V
IN
IMPORTANT NOTICE
PA01 PA73
262 PA01-73U
PA01, PA73
FEATURES
LOW COST, ECONOMY MODEL PA01
HIGH OUTPUT CURRENT Up to 5A PEAK
EXCELLENT LINEARITY PA01
HIGH SUPPLY VOLTAGE Up to 30V
ISOLATED CASE 300V
APPLICATIONS
MOTOR, VALVE AND ACTUATOR CONTROL
MAGNETIC DEFLECTION CIRCUITS UP TO 4A
POWER TRANSDUCERS UP TO 20kHz
TEMPERATURE CONTROL UP TO 180W
PROGRAMMABLE POWER SUPPLIES UP TO 48V
AUDIO AMPLIFIERS UP TO 50W RMS
DESCRIPTION
The PA01 and PA73 are high voltage, high output current
operational amplifers designed to drive resistive, inductive
and capacitive loads. For optimum linearity, the PA01 has a
class A/B output stage. The PA73 has a simple class C output
stage (see Note 1) to reduce cost for motor control and other
applications where crossover distortion is not critical and
to provide interchangeability with type 3573 amplifers. The
safe operating area (SOA) can be observed for all operating
conditions by selection of user programmable current limit
resistors. These amplifers are internally compensated for all
gain settings. For continuous operation under load, a heatsink
of proper rating is recommended.
This hybrid integrated circuit utilizes thick flm (cermet)
resistors, ceramic capacitors and semiconductor chips to
maximize reliability, minimize size and give top performance.
Ultrasonically bonded aluminum wires provide reliable inter-
connections at all operating temperatures. The 8-pin TO-3
package is hermetically sealed and electrically isolated. The
use of compressible thermal washers and/or improper mount-
ing torque will void the product warranty. Please see General
Operating Considerations.
CL+
+V
+IN
IN
V
N.C.
CL
OUT
S
S
TOP VIEW
R
CL+
R
CL
OUTPUT
1
2
3
4
5
6
7
8
NOTE 1: * Indicates not used in PA73. Open base of Q2A
connected to output of A1.
TYPICAL APPLICATION
Unidirectional Optical Speed Control
The pulse output of a non-contact optical sensor drives a
voltage-to-frequency converter which generates feedback for
the op amp. With the loop closed in this manner, the op amp
corrects for any variations in the speed due to changing load.
Because of operation in only one direction, an unsymmetrical
supply is used to maximize efficiency of both power op amp
and power supply. High speed diodes at the input protect the
op amp from commutator noise which may be generated by
the motor.
24V
.33
3W
30V
+6V
C
F
R
IN
PA01
R
F
F/V
OPTO
PULSE
GEN.
R
CL
.33
3W
R
CL+
V
IN
0/5V
M
0/+5V
1N4148
UNSYMMETRICAL SUPPLIES FOR EFFICIENCY
3
4
5
6
2
1
8
A1
D1
Q1
Q4
Q3
Q5
C1
Q2A
Q2B
Q6B
Q6A
*
*
*
*
*
*
8-PIN TO-3
PACKAGE STYLE CE
PA01 PA73 P r o d u c t I n n o v a t i o n F r o m
MAY 2009
APEX PA01-73UREVU
PA01 PA73
PA01-73U 263
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SPECIFICATIONS
PA01 PA73
2
INPUT
C
= 25C 5 12 * 10 mV
OFFSET VOLTAGE, vs. supply T
C
= 25C 35 * 200 V/V
OFFSET VOLTAGE, vs. power T
C
= 25C 20 * V/W
C
= 25C 15 50 * 40 nA
BIAS CURRENT, vs. temperature Full temperature range .05 .4 * * nA/C
BIAS CURRENT, vs. supply T
C
= 25C .02 * nA/V
C
= 25C 12 30 * * nA
OFFSET CURRENT, vs. temperature Full temperature range .05 * nA/C
INPUT IMPEDANCE, common-mode T
C
= 25C 200 * M
INPUT IMPEDANCE, differential T
C
= 25C 10 * M
INPUT CAPACITANCE T
C
= 25C 3 * pF
3
Full temperature range V
S
6 V
S
3 * * V
3
T
C
= 25C, V
CM
= V
S
6V 70 110 * * dB
GAIN
OPEN LOOP GAIN at 10Hz Full temp. range, full load 91 113 * * dB
GAIN BANDWIDTH PRODUCT @ 1MHz T
C
= 25C, full load 1 * MHz
POWER BANDWIDTH T
C
= 25C, I
O
= 4A, V
O
= 40V
PP
15 23 * * kHz
OUTPUT
VOLTAGE SWING
3
T
C
= 25C, I
O
= 5A V
S
10 V
S
5 V
S
8 * V
VOLTAGE SWING
3
Full temp. range, I
O
= 2A V
S
6 V
S
5 * * V
VOLTAGE SWING
3
Full temp. range, I
O
= 46mA V
S
5 * V
CURRENT, peak T
C
= 25C 5 * A
SETTLING TIME to .1% T
C
= 25C, 2V step 2 * s
SLEW RATE T
C
= 25C, R
L
= 2.5 1.0 2.6 * * V/s
CAPACITIVE LOAD, unity gain Full temperature range 1 * nF
CAPACITIVE LOAD, gain > 4 Full temperature range SOA *
POWER SUPPLY
VOLTAGE Full temperature range 10 28 28 * * 30 V
CURRENT, quiescent T
C
= 25C 20 50 2.6 5 mA
THERMAL
4
F > 60Hz 1.9 2.1 * * C/W
RESISTANCE, DC, junction to case F < 60Hz 2.4 2.6 * * C/W
RESISTANCE, junction to air 30 * C/W
TEMPERATURE RANGE, case Meets full range specifcations 25 25 +85 * * * C
PA01 PA73
SUPPLY VOLTAGE, +V
S
to V
S
60V 68V
OUTPUT CURRENT, within SOA 5A 5A
POWER DISSIPATION, internal 67W 67W
INPUT VOLTAGE, differential 37V 37V
INPUT VOLTAGE, common-mode V
S
V
S
1
200C 200C
TEMPERATURE, pin solder -10s 300C 300C
TEMPERATURE RANGE, storage 65 to +150C 65 to +150C
OPERATING TEMPERATURE RANGE, case 25 to +85C 25 to +85C
NOTES: * The specifcation of PA73 is identical to the specifcation for PA01 in applicable column to the left.
achieve high MTTF.
2. The power supply voltage specifed under the TYP rating applies unless otherwise noted as a test condition.
3. +V
S
and V
S
denote the positive and negative supply rail respectively. Total V
S
is measured from +V
S
to V
S
.
CAUTION
PA01 PA73
264 PA01-73U
10K 20K 50K .1M
FREQUENCY, F (Hz)
4.6
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
P
)
POWER RESPONSE
30K 70K
6.8
10
15
22
32
46
68
100
|+V
S
| + |-V
S
| = 60V
1 100 10M
FREQUENCY, F (Hz)
20
0
60
120
O
P
E
N

L
O
O
P

G
A
I
N
,

A
O
L

(
d
B
)
20
40
80
100
10 1K 10K .1M 1M
1 10K
FREQUENCY, F (Hz)
0
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
120
.1M 10 100 1K 1M
20
60
100
1 100 .1M 10M
140
100
40
0
PHASE RESPONSE
60
20
1K 10 10K 1M
FREQUENCY, F (Hz)
P
H
A
S
E
,

)
120
80
180
160
10 100 10K .1M
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/

H
z
)
INPUT NOISE
1K
10
20
30
40
50
70
100
0 20 40 60 80 100 120
TEMPERATURE, T(C)
0
10
30
50
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
20
70
140
40
60
C
T = T
A
T = T
50 0 100
1.0
2.2
2.5
BIAS CURRENT
1.6
.7
25 25 50 75
1.9
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
125
1.3
CASE TEMPERATURE, T
C
(C)
.4
50 25 50 100
CASE TEMPERATURE, T
C
(C)
0
3.0
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
2.5
0 25 75
1.0
1.5
.5
2.0
125
3.5
R
CL
= 0.3
R
CL
= 0.6
0
TIME, t (s)
PULSE RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
8
2 4 6 8 10 12
6
4
2
0
2
4
6
8
V
IN
= 5V, t
R
= 100ns
PA01
for PA73
100 1K 3K .1M
FREQUENCY, F (Hz)
.003
.3
3
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N

(
%
)
.01
.1
1
300 10K 30K
.03
P
A
7
3

@

P
O

=

3
2
W
P
A
7
3

@

P
O

=

5
0
m
W
P
A
0
1

@

P
O

=

5
0
m
W
P
A
0
1

@

P
O

=

3
2
W
V
S
= 28V
R
L
= 8
A
V
= 10
20 80
S
(V)
.7
.8
1.3
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D
,

I
Q

(
X
)
.9
1.2
30 40 50 60 70
1.1
1.0
PA01 @
25 to +25C
PA73 @
25 to +85C
PA01 @
85C
PA01 PA73
PA01-73U 265
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
Please read Application Note 1 "General Operating Consider-
ations" which covers stability, supplies, heat sinking, mounting,
current limit, SOA interpretation, and specifcation interpretation.
Visit www.cirrus.com for design tools that help automate tasks
current limit and heat sink selection. The "Application Notes"
and "Technical Seminar" sections contain a wealth of informa-
tion on specifc types of applications. Package outlines, heat
sinks, mounting hardware and other accessories are located
in the "Packages and Accessories" section. Evaluation Kits
are available for most Apex Precision Power product models,
consult the "Evaluation Kit" section for details. For the most
current version of all Apex Precision Power product data sheets,
visit www.cirrus.com.
SAFE OPERATING AREA (SOA)
The output stage of most power amplifers has three distinct
limitations:
1. The current handling capability of the transistor geometry
and the wire bonds.
2. The second breakdown effect which occurs whenever the
simultaneous collector current and collector-emitter voltage
exceeds specifed limits.
3. The junction temperature of the output transistors.
The SOA curves combine the effect of these limits. For a
given application, the direction and magnitude of the output
current should be calculated or measured and checked against
the SOA curves. This is simple for resistive loads but more
complex for reactive and EMF generating loads.
1. For sine wave outputs, use Power Design
1
to plot a load
line. Make sure the load line does not cross the 0.5ms limit
and that excursions beyond any other second breakdown
line do not exceed the time label, and have a duty cycle of
no more than 10%.
For other waveform outputs, manual load line plotting
is recommended. Applications Note 22, SOA AND LOAD
LINES, will be helpful. A Spice type analysis can be very
useful in that a hardware setup often calls for instruments
or amplifers with wide common mode rejection ranges.
2. EMF generating or reactive load and short circuits to the
supply rail or shorts to common are safe if the current limits
are set as follows at T
C
= 85C.
SHORT TO V
S
SHORT TO
V
S
C, L, OR EMF LOAD COMMON
34V .58A 1.1A
30V .46A 1.4A
25V .61A 1.7A
20V .86A 2.1A
15V 1.3A 2.9A
3. The output stage is protected against occaisional transient
fyback. However, for protection against sustained, high
energy fyback, external fast-recovery diodes should be
used.
CURRENT LIMIT
Proper operation requires the use of two current limit resis-
tors, connected as shown, in the external connection diagram.
The minimum value for R
CL
is 0.12 ohm; however, for optimum
reliability it should be set as high as possible. Refer to the
General Operating Considerations section of the handbook
for current limit adjust details.
10 15 20 25 30 35 40 50 60
.3
.4
.6
.8
1.0
1.5
2.0
3.0
4.0
5.0
T
c

=

8
5
C
T
c

=

1
2
5
C T
H
E
R
M
A
L
s
t
e
a
d
y

s
t
a
t
e

S
E
C
O
N
D

B
R
E
A
K
D
O
W
N
t

=

1
m
s
t

=

5
m
s
t

=

0
.
5
m
s
PA01 LIMIT
1
Note 1. Power Design is a self-extracting Excel spreadsheet
available free from www.cirrus.com
PA73M
266 PA73MU
PA73M/883
SG PARAMETER SYMBOL TEMP. POWER TEST CONDITIONS MIN MAX UNITS
1 Quiescent Current I
Q
25C 28V V
IN
= 0, A
V
= 100 5 mA
1 Input Offset Voltage V
OS
25C 28V V
IN
= 0, A
V
= 100 10 mV
OS
25C 10V V
IN
= 0, A
V
= 100 17.2 mV
OS
25C 30V V
IN
= 0, A
V
= 100 10.8 mV
1 Input Bias Current, +IN +I
B
25C 28V V
IN
= 0 40 nA
1 Input Bias Current, IN I
B
25C 28V V
IN
= 0 40 nA
1 Input Offset Current I
OS
25C 28V V
IN
= 0 25 nA
Q
55C 28V V
IN
= 0, A
V
= 100 5 mA
OS
55C 28V V
IN
= 0, A
V
= 100 15.2 mV
OS
55C 10V V
IN
= 0, A
V
= 100 22.4 mV
OS
55C 30V V
IN
= 0, A
V
= 100 16 mV
B
55C 28V V
IN
= 0 72 nA
3 Input BiasCurrent, IN I
B
55C 28V V
IN
= 0 72 nA
OS
55C 28V V
IN
= 0 60 nA
Q
125C 28V V
IN
= 0, A
V
= 100 7 mA
OS
125C 28V V
IN
= 0, A
V
= 100 16.5 mV
OS
125C 10V V
IN
= 0, A
V
= 100 23.7 mV
OS
125C 30V V
IN
= 0, A
V
= 100 17.3 mV
B
125C 28V V
IN
= 0 80 nA
B
125C 28V V
IN
= 0 80 nA
OS
125C 28V V
IN
= 0 80 nA
4 Output Voltage, I
O
= 5A V
O
25C 18.3V R
L
= 2.07 10.3 V
4 Output Voltage, I
O
= 50mA V
O
25C 30V R
L
= 500 25 V
4 Output Voltage, I
O
= 2A V
O
25C 30V R
L
= 12 24 V
4 Current Limits I
CL
25C 18V R
L
= 12, R
CL
= 1 .54 .86 A
4 Stability/Noise E
N
25C 28V R
L
= 500, A
V
= 1, C
L
= 10nF 1 mV
4 Slew Rate SR 25C 28V R
L
= 500 1 10 V/s
4 Open Loop Gain A
OL
25C 28V R
L
= 500, F = 10Hz 91 dB
4 Common Mode Rejection CMR 25C 15V R
L
= 500, F = DC, V
CM
= 9V 70 dB
6 Output Voltage, I
O
= 5A V
O
55C 18.3V R
L
= 2.07 10.3 V
6 Output Voltage, I
O
= 50mA V
O
55C 30V R
L
= 500 25 V
6 Output Voltage, I
O
= 2A V
O
55C 30V R
L
= 12 24 V
6 Stability/Noise E
N
55C 30V R
L
= 500, A
V
= 1, C
L
= 10nF 1 mV
L
= 500 1 10 V/s
6 Open Loop Gain A
OL
55C 28V R
L
= 500, F = 10Hz 91 dB
L
= 500, F = DC, V
CM
= 9V 70 dB
5 Output Voltage, I
O
= 3A V
O
125C 11.3V R
L
= 2.07 6.3 V
5 Output Voltage, I
O
= 50mA V
O
125C 30V R
L
= 500 25 V
5 Output Voltage, I
O
= 2A V
O
125C 30V R
L
= 12 24 V
5 Stability/Noise E
N
125C 28V R
L
= 500, A
V
= 1, C
L
= 10nF 1 mV
L
= 500 1 10 V/s
5 Open Loop Gain A
OL
125C 28V R
L
= 500, F = 10Hz 91 dB
L
= 500, F = DC, V
CM
= 9V 70 dB
BURN IN CIRCUIT
* These components are used to stabilize device
due to poor high frequency characteristics of burn
in board.
** Input signals are calculated to result in internal
power dissipation of approximately 2.1W at case
temperature = 125C.
100K
1
1
100K
+15V
15V
5
6
2
1
8
3
20
**
*
U.U.T
4
*
Table 4 Group A Inspection
PA73M/883 P r o d u c t I n n o v a t i o n F r o m
SEP 2009
APEX PA73MUREVI
PA02 PA02A
PA02U 267
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA02, PA02A
FEATURES
HIGH POWER BANDWIDTH 350kHz
FAST SETTLING TIME 600ns
LOW CROSSOVER DISTORTION Class A/B
LOW INTERNAL LOSSES 1.2V at 2A
HIGH OUTPUT CURRENT 5A PEAK
LOW INPUT BIAS CURRENT FET Input
ISOLATED CASE 300 VDC
APPLICATIONS
POWER TRANSDUCERS UP TO 350 kHz
DESCRIPTION
The PA02 and PA02A are wideband, high output current
and capacitive loads. Their complementary collector output
stage can swing close to the supply rails and is protected
against inductive kickback. For optimum linearity, the output
stage is biased for class A/B operation. The safe operating
area (SOA) can be observed for all operating conditions by
selection of user programmable, current limiting resistors
(down to 10mA). Both amplifers are internally compensated
but are not recommended for use as unity gain followers. For
continuous operation under load, mounting on a heatsink of
proper rating is recommended.
These hybrid integrated circuits utilize thick flm (cermet)
package is hermetically sealed and electrically isolated. Iso-
lation washers are not recommended. The use of compress-
ible thermal washers and/or improper mounting torque will
void the product warranty. Please see General Operating
Considerations.
TYPICAL APPLICATION
Vehicular Sound System Power Stage
LOW INTERNAL LOSS MAXIMIZES EFFICIENCY
When system voltages are low and power is at a premium,
the PA02 is a natural choice. The circuit above utilizes not only
the feature of low internal loss of the PA02, but also its very
low distortion level to implement a crystal clear audio amplifer
suitable even for airborne applications. This circuit uses AC
coupling of both the input signal and the gain circuit to render
DC voltage across the speaker insignifcant. The resistor and
capacitor across the inputs form a stability enhancement net-
work. The 0.27 ohm current limit resistors provide protection
in the event of an output short circuit.
16K
100K
R
CL+
R
CL
.27
.27
3.2
16W
12
+12
.47F
.47F
16K
.001F
PA02
IN
1K
R
CL+
R
CL
TOP VIEW
1
2
3
4
5
6
7
8
CL
V
S
+IN
IN
OUT
OUT
+V
S
CL+
2
6
5
7
1
3
4
8
R2 R3
R1
R5
R4
R8
R9 R10
R11
R12
R13
R14
R15
R6
R7
Q1
Q8
Q5
Q4
Q3
Q6
Q2
Q7
A1
D1
D2
8-PIN TO-3
PACKAGE STYLE CE
PA02 PA02A P r o d u c t I n n o v a t i o n F r o m
MAY 2009
APEX PA02UREVO
PA02 PA02A
268 PA02U
SUPPLY VOLTAGE, +V
S
to V
S
38V
1
48W
S
+2V to +V
S
2V
1
150C
TEMPERATURE RANGE, storage 65 to +150C
CAUTION
SPECIFICATIONS
PA02 PA02A
2, 6
INPUT
C
= 25C 5 10 1 3 mV
OFFSET VOLTAGE, vs. temperature Full temperature range 10 50 * 25 V/C
C
= 25C 10 * V/V
C
= 25C 6 * V/W
C
= 25C 50 200 25 100 pA
BIAS CURRENT, vs. temperature T
C
= 85C 200 * pA/C
C
= 25C .01 * pA/V
C
= 25C 25 100 15 50 pA
OFFSET CURRENT, vs. temperature T
C
= 85C 100 * pA/C
INPUT IMPEDANCE, DC T
C
= 25C 1000 * G
INPUT CAPACITANCE T
C
= 25C 3 * pF
COMMON MODE VOLT. RANGE
5
, Pos. Full temperature range +V
S
6 +V
S
3 * * V
COMMON MODE VOLT. RANGE
5
, Neg. Full temperature range V
S
+6 V
S
+5 * * V
COMMON MODE REJECTION, DC Full temperature range 70 100 * * dB
GAIN
OPEN LOOP GAIN at 10Hz T
C
= 25C, 1k load 103 * dB
OPEN LOOP GAIN at 10Hz Full temp. range, 10k load 86 100 * * dB
GAIN BANDWIDTH PRODUCT at 1MHz T
C
= 25C, 10 load 4.5 * MHz
POWER BANDWIDTH T
C
= 25C, 10 load 350 * kHz
PHASE MARGIN Full temp. range, 10 load 30 *
OUTPUT
VOLTAGE SWING
3
T
C
= 25C, I
O
= 5A, R
CL
= .08 V
S
4 V
S
3 * * V
VOLTAGE SWING
3
Full temp. range, I
O
= 2A V
S
2 V
S
1.2 * * V
CURRENT, peak T
C
= 25C 5 * A
C
= 25C, 2V step .6 * s
SLEW RATE T
C
= 25C 13 20 * * V/s
CAPACITIVE LOAD Full temp. range, A
V
> 10 SOA *
HARMONIC DISTORTION P
O
= .5W, F = 1kHz, R
L
= 10 .004 * %
SMALL SIGNAL rise/fall time R
L
= 10, A
V
= 1 100 * ns
SMALL SIGNAL overshoot R
L
= 10, A
V
= 1 10 * %
POWER SUPPLY
C
= 25C 27 40 * * mA
THERMAL
RESISTANCE, AC junction to case
4
F > 60Hz 1.9 2.1 * * C/W
RESISTANCE, DC junction to case F < 60Hz 2.4 2.6 * * C/W
TEMPERATURE RANGE, case Meets full range specifcations 25 +85 55 +125 C
NOTES: * The specifcation of PA02A is identical to the specifcation for PA02 in applicable column to the left.
achieve high MTTF.
2. The power supply voltage for all specifcations is the TYP rating unless otherwise noted as a test condition.
3. +V
S
and V
S
S
is measured from +V
S
to V
S
.
5. Exceeding CMV range can cause the output to latch.
6. Full temperature specifcations are guaranteed but not 100% tested.
7. The absolute maximum negative input voltage is equal to the negative power supply voltage plus 1V (-Vs + 1V).
PA02 PA02A
PA02U 269
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
0 25 50 75 100 125
TEMPERATURE, T (C)
0
10
30
50
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
10 100 10K .1M
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,
e
n

(
n
V
/
H
z
)
1 100 10M
FREQUENCY, F (Hz)
20
0
60
120
O
P
E
N

L
O
O
P

G
A
I
N
,

A
O
L

(
d
B
)
20
40
80
100
1 100 .1M 10M
210
150
60
0
PHASE RESPONSE
90
30
.1M .2M .5M 1M
FREQUENCY, F (Hz)
6
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
1 3 4 7
OUTPUT CHANGE FROM ZERO, VOLTS
0
2
3
SETTLING TIME
T
I
M
E
,

t

(
S
)
.5
1.5
2.5
25 125
CASE TEMPERATURE, T
C
(C)
1.0
1.1
1.6
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
1.2
1.5
0
OUTPUT CURRENT, I
O
(A)
S
A
T
U
R
A
T
I
O
N

V
O
L
T
A
G
E
,

V
S

V
O

(
V
)
25 50 100
CASE TEMPERATURE, T
C
(C)
0
2.5
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
2.0
2 5 6
1.0
INPUT NOISE
1K
10
15
20
1K
20
POWER RESPONSE
.3M
0 25 50 75 100
1.4
0 25 75
.5
1.0
10 1K 10K .1M 1M
150
40
10 10K 1M
FREQUENCY, F (Hz)
P
H
A
S
E
,

)
1.5
.7M
7.8
10
13
18
23
30
1
1.3
125
3.0
180
120
25
30
35
40
1 2 3 4 5
1.5
2.0
2.5
3.0
3.5
8
1
m
V

N
O

L
O
A
D
1
0
m
V
N
O
L
O
A
D
.5
.9
| +V
S
| + | V
S
| = 36V
| +V
S
| + | V
S
| = 30V
T=T
C
T=T
A
T
C
= 25 to 85C
V
O
R
CL
= 0.3
R
CL
= 0.62
10mV 10 LOAD
10
FREQUENCY, F(Hz)
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)
100 1K 10K .1M 1M 10M
0
20
40
60
80
100
120
140
+V
S
V
S
1 10K
FREQUENCY, F (Hz)
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
120
.1M 10 100 1K 1M
20
60
100
10M
15 105
.25
64
256
BIAS CURRENT
4
.06
5 45 65 85
16
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
1
CASE TEMPERATURE, T
C
(C)
25
PA02 PA02A
270 PA02U
GENERAL
Please read Application Note 1 "General Operating Considerations" which cov-
ers stability, supplies, heat sinking, mounting, current limit, SOA interpretation, and
specifcation interpretation. Visit www.Cirrus.com for design tools that help automate
tasks such as calculations for stability, internal power dissipation, current limit; heat
sink selection; Apex Precision Powers complete Application Notes library; Technical
Seminar Workbook; and Evaluation Kits.
SAFE OPERATING AREA
The SOA curves combine the
effect of all limits for this Power
Op Amp. For a given application,
the direction and magnitude of
the output current should be cal-
culated or measured and checked
against the SOA curves. This is
simple for resistive loads but more
complex for reactive and EMF
generating loads. The following
guidelines may save extensive
analytical efforts:
1. Under transient conditions,
capacitive and dynamic* loads
up to the following maximums
are safe:
CAPACITIVE LOAD INDUCTIVE LOAD
V
S
I
LIM
= 2A I
LIM
= 5A I
LIM
= 2A I
LIM
= 5A
18V 2mF 0.7mF .2H 10mH
15V 10mF 2.2mF .7H 25mH
10V 25mF 10mF 5H 50mH
* If the inductive load is driven near steady state conditions, allowing the output
voltage to drop more than 8V below the supply rail with I
LIM
= 5A, or 17V below the
supply rail with I
LIM
= 2A while the amplifer is current limiting, the inductor should
be capacitively coupled or the current limit must be lowered to meet SOA criteria.
2. The amplifer can handle any EMF generating or reactive load and short circuits
to the supply rails or shorts to common if the current limits are set as follows at
T
C
= 85C.
SHORT TO V
S
SHORT TO
V
S
C, L OR EMF LOAD COMMON
18V .5A 1.7A
15V .7A 2.8A
10V 1.6A 4.2A
These simplifed limits may be exceeded with further analysis using the operating
conditions for a specifc application.
CURRENT LIMIT
Proper operation requires the use of two current limit resistors, connected as shown
in the external connection diagram. The minimum value for R
CL
is 0.12 ohm, however for
optimum reliability it should be set as high as possible. Refer to the General Operating
Considerations section of the handbook for current limit adjust details.
DEVICE MOUNTING
The case (mounting fange) is electrically isolated and should be mounted directly
to a heatsink with thermal compound. Screws with Belville spring washers are recom-
mended to maintain positive clamping pressure on heatsink mounting surfaces. Long
periods of thermal cycling can loosen mounting screws and increase thermal resistance.
Since the case is electrically isolated (foating) with respect to the internal circuits
it is recommended to connect it to common or other convenient AC ground potential.
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V

O
R

V
S

(
A
)
2 3 5 7 10 15 20 25 30 40
0.2
0.3
0.5
0.7
1.0
1.5
2.0
3.0
4.0
5.0
SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE V
S
V
O
(V)
T
H
E
R
M
A
L
S
E
C
O
N
D
B
R
E
A
K
D
O
W
N
t

=

5
m
s
T
C
=

1
2
5
C
T
C =
2
5
C
T
C
=

7
0
C
T
C
=

1
0
0
C
S
T
E
A
D
Y

S
T
A
T
E
SOA
100 1K 3K .1M
FREQUENCY, F (Hz)
.001
.1
1
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

T
H
D

(
%
)
.003
.03
.3
300 10K 30K
.01
.3M
1 3 4
TIME, t (S)
15
5
15
PULSE RESPONSE
10
0
10
2 5
5
PULSE RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
.2
.1
0
.1
.2
.3
.3
10K
FREQUENCY, F (Hz)
LOADING EFFECTS
D
E
L
T
A

G
A
I
N

W
I
T
H

L
O
A
D
,

A

(
d
B
)
1.2
.6
0
.1M 100 1K
1.5
.9
.3
TIME, t (S)
0 .5 1.0 1.5
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
0
GAIN = 1
LOAD = 10
PO
=
5
W
P
O
=

5
0
m
W
P
O
=

.
5
W
V
IN
= .2V, tr = 50ns
V
IN
= 1V, tr = 100ns
LOAD = 10
I
O
= 150mA
I
O
= 400mA
PA02M
PA02MU 271
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
P r o d u c t I n n o v a t i o n F r o m PA02M/883
BURN IN CIRCUIT
* These components are used to stabilize device due to poor
high frequency characteristics of burn in board.
** Input signals are calculated to result in internal power dissipa-
tion of approximately 2.1W at case temperature = 125C.
1 Quiescent current I
Q
25C 15V V
IN
= 0, A
V
= 100, R
CL
= .2 40 mA
1 Input offset voltage V
OS
25C 15V V
IN
= 0, A
V
= 100 10 mV
OS
25C 7V V
IN
= 0, A
V
= 100 11.6 mV
OS
25C 19V V
IN
= 0, A
V
= 100 10.8 mV
1 Input bias current, +IN +I
B
25C 15V V
IN
= 0 200 pA
1 Input bias current, IN I
B
25C 15V V
IN
= 0 200 pA
1 Input offset current I
OS
25C 15V V
IN
= 0 100 pA
Q
55C 15V V
IN
= 0, A
V
= 100, R
CL
= .2 60 mA
OS
55C 15V V
IN
= 0, A
V
= 100 14 mV
OS
55C 7V V
IN
= 0, A
V
= 100 15.6 mV
OS
55C 19V V
IN
= 0, A
V
= 100 14.8 mV
B
55C 15V V
IN
= 0 200 pA
B
55C 15V V
IN
= 0 200 pA
OS
55C 15V V
IN
= 0 100 pA
Q
125C 15V V
IN
= 0, A
V
= 100, R
CL
= .2 60 mA
OS
125C 15V V
IN
= 0, A
V
= 100 15 mV
OS
125C 7V V
IN
= 0, A
V
= 100 16.6 mV
OS
125C 19V V
IN
= 0, A
V
= 100 15.8 mV
B
125C 15V V
IN
= 0 30 nA
B
125C 15V V
IN
= 0 30 nA
OS
125C 15V V
IN
= 0 10 nA
4 Output voltage, I
O
= 5A V
O
25C 9V R
L
= 1, R
CL
= 0 5 V
4 Output voltage, I
O
= 36mA V
O
25C 19V R
L
= 500 18 V
4 Output voltage, I
O
= 2A V
O
25C 12V R
L
= 5, R
CL
= 0 10 V
4 Current limits I
CL
25C 9V R
L
= 5, R
CL
= 1 .54 .86 A
4 Stability/noise E
N
25C 15V R
L
= 500, A
V
= 1, C
L
= 1.5nF 1 mV
4 Slew rate SR 25C 18V R
L
= 500 13 100 V/s
4 Open loop gain A
OL
25C 15V R
L
= 500, F = 10Hz 86 dB
4 Common mode rejection CMR 25C 8.25V R
L
= 500, F = DC, V
CM
= 2.25V 70 dB
6 Output voltage, I
O
= 5A V
O
55C 9V R
L
= 1, R
CL
= 0 5 V
6 Output voltage, I
O
= 36mA V
O
55C 19V R
L
= 500 18 V
6 Output voltage, I
O
= 2A V
O
55C 12V R
L
= 5, R
CL
= 0 10 V
6 Stability/noise E
N
55C 15V R
L
= 500, A
V
= 1, C
L
= 1.5nF 1 mV
L
= 500 13 100 V/s
6 Open loop gain A
OL
55C 15V R
L
= 500, F = 10Hz 86 dB
L
= 500, F = DC, V
CM
= 2.25V 70 dB
5 Output voltage, I
O
= 3A V
O
125C 7V R
L
= 1, R
CL
= 0 3 V
5 Output voltage, I
O
= 36mA V
O
125C 19V R
L
= 500 18 V
5 Output voltage, I
O
= 2A V
O
125C 12V R
L
= 5, R
CL
= 0 10 V
5 Stability/noise E
N
125C 15V R
L
= 500, A
V
= 1, C
L
= 1.5nF 1 mV
L
= 500 8.5 100 V/s
5 Open loop gain A
OL
125C 15V R
L
= 500, F = 10Hz 86 dB
L
= 500, F = DC, V
CM
= 2.25V 70 dB
100K
1
1
100K
+15V
15V
5
6
2
7
1
8
3,4
20
* *
*
*
U.U.T
SEP 2009
APEX PA02MUREVK
PA02DI
272 PA02DIU
P r o d u c t I n n o v a t i o n F r o m PA02 Design Ideas
BACKGROUND
In 1985, Apex Precision Power frst addressed inquiries on how the PA02 could be used to second source the LH0101. Now,
because of Apex Precision Powers commitment to continue production of the PA02, it is the part of choice for most new designs.
For retroft situations, the PA02 can be substituted for the LH0101 without requiring a PC layout change.
COMPARING THE LH0101 AND THE PA02
The PA02 can satisfy the majority of applications now using the 0101, and can often do it with improved frequency response,
linearity and distortion. The table below and the notes that follow compare the two devices.
KEY SPECIFICATION COMPARISON
LH0101 LH0101 LH0101 LH0101
K AK CK ACK PA02 PA02A PA02M Units
V
OS
, Initial 10 3 10 3 10 3 10 mV
V
OS
, vs. Temp 15 7 15 7 13 5.5 15 mV
Bias Current, Initial 1000 300 1000 300 200 100 200 pA
Offset Current, Initial 250 75 250 75 100 50 100 pA
Temp Range 55/+125 55/+125 25/+85 25/+85 25/+85 55/+125 55/+125 C
Power Bandwidth 300 300 300 300 350 350 350 kHz
Slew Rate (minimum) N/A 7.5 N/A 7.5 13 13 13 V/s
Distortion @ 0.5w, 0.008 0.008 0.008 0.008 0.004 0.004 0.004 %
1 kHz, 10 ohms (typical)
Note: The LH0101 is rated from 5V to 22V. The PA02 is rated from 7V to 19V. Do not use the PA02 below 7V
(14V total) or above 19V (38V total).
PIN-OUT COMPARISON
LH0101 Function Pin No. PA02 Function
SC+ 1 RCL+
V+ 2 +V
S
Feedback 3 Out
(Note 1) 4 Out
IN 5 IN
+IN 6 +IN
V 7 V
S
SC 8 RCL
Out Case Isolated
NOTE 1: MAY BE OUT OR N/C, DEPENDING ON DATA SHEET REVISION
The PA02 can often drop into the LH0101 socket and improve performance in the areas noted above. This drop in status ap-
plies when the LH0101 does not employ the swing enhancement network. More simply stated, where Pin No. 3 is tied directly to
the output (i.e., the case), the 0101 and PA02 are often interchangeable. For circuits which do employ the swing enhancement,
one resistor should be removed and another replaced with a jumper. This retroft saves parts and assembly cost and improves
circuit efficiency by eliminating the drop across each of the two resistors. In both cases, the case of the PA02 is tied to the output.
This is acceptable.
Replacing the LH0101 with the APEX PA02
PA02 Design Ideas
P r o d u c t
I n n o v a t i o n
F r o m
MAY 2009
APEX PA02DIUREV1
PA02DI
PA02DIU 273
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QUESTIONS?
If you have questions, or would like further assistance converting your design
to the PA02, please call the Apex Precision Power Applications Design Support
Request at (800) 625-4084.
+V
S
V
S
CASE
R
L
3
5
+V
S
V
S
CASE
R
L
3
5
+V
S
V
S
CASE
R
L
3
5
51
100
+V
S
V
S
CASE
R
L
3
5
J1
REMOVE
LH0101 PA02
LH0101 PA02
DROP IN EXAMPLE
MODIFICATION EXAMPLE
PA03 PA03A
274 PA02U
P r o d u c t I n n o v a t i o n F r o m PA03, PA03A
FEATURES
MO-127 COPPER POWER DIP PACKAGE
HIGH INTERNAL POWER DISSIPATION
500 watts
HIGH VOLTAGE OPERATION 75V
VERY HIGH CURRENT 30 amps
INTERNAL SOA PROTECTION
OUTPUT SWINGS CLOSE TO SUPPLY RAILS
EXTERNAL SHUTDOWN CONTROL
APPLICATIONS
YOKE/MAGNETIC FIELD DEFLECTION
PROGRAMMABLE POWER SUPPLIES to 68V
TRANSDUCER/AUDIO TO 1000W
DESCRIPTION
The super power PA03 advances the state of the art in both
brute force power and self protection against abnormal oper-
ating conditions. Its features start with a copper dip package
developed by Apex Precision Power to extend power capabilities
well beyond those attainable with the familiar TO-3 package.
The increased pin count of the new package provides addi-
tional control features, while the superior thermal conductivity
of copper allows substantially higher power ratings.
The PA03 incorporates innovative current limiting circuits
limiting internal power dissipation to a curve approximating
the safe operating area of the power transistors. The internal
current limit of 35A is supplemented with thermal sensing
which reduces the current limit as the substrate temperature
rises. Furthermore, a subcircuit monitors actual junction
temperatures and with a response time of less than ten mil-
liseconds reduces the current limit further to keep the junction
temperature at 175C.
The PA03 also features a laser trimmed high performance
FET input stage providing superior DC accuracies both initially
and over the full temperature range.
EQUIVALENT
SCHEMATIC
3
4
5
2
1
12
11
8
7
6
9
10
V
+
BAL
BAL
+V
Q31
Q20
A
Q17
Q2
Q3
Q5
Q20
B
Q18
+SHUT
DOWN
SHUT
DOWN
Q14
Q22
COMP
Q12
D1
Q1
Q6
Q7
Q19
Q29
Q30
Q34
Q32
Q26
D3
OUT
Q9 D2
Q16
Q4
D4
+
Q24
The PA03 output power stages contain fast reverse recovery
diodes for sustained high energy fyback protection.
This hybrid integrated circuit utilizes thick flm resistors,
ceramic capacitors and silicon semiconductors to maximize
reliability, minimize size and give top performance. Ultra-
sonically bonded aluminum wires provide reliable intercon-
nections at all operating temperatures. The MO-127 Copper,
12-pin Power Dip package (see Package Outlines), is
hermetically sealed and isolated from the internal circuits.
Insulating washers are not recommended.
IMPORTANT: Observe mounting precautions.
TYPICAL APPLICATION
POSITION
FEEDBACK
OBJECT
TOOL
SHUT DOWN
+5V
+
+S
S
V
S
C
1
R2
R
BAL
+V
S
0/10V
R1
PA03
DESIRED
POSITION
DAC
12-PIN DIP
PACKAGE STYLE CU
MAY 2009
APEX PA03UREVJ
PA03 PA03A
PA02U 275
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PA03 PA03A
2
INPUT
C
= 25C .5 2 .25 .5 mV
OFFSET VOLTAGE, vs. temperature Full temperature range 10 30 5 10 V/C
C
= 25C 8 * V/V
OFFSET VOLTAGE, vs. power Full temperature range 20 10 V/W
C
= 25C 5 50 3 10 pA
C
= 25C .01 * pA/V
C
= 25C 2.5 50 1.5 10 pA
C
= 25C 10
11
*
INPUT CAPACITANCE T
C
= 25C 6 * pF
3
S
10V * V
COMMON MODE REJECTION, DC Full temp. range, V
CM
= 20V 86 108 * * dB
SHUTDOWN CURRENT
4
Full temperature range 100 * A
SHUTDOWN VOLTAGE Full temp. range, amp enabled .85 * V
SHUTDOWN VOLTAGE Full temp. range, amp disabled 3.5 * V
GAIN
C
POWER BANDWIDTH T
C
= 25C, I
O
= 15A, V
O
= 88V
PP
30 * kHz
PHASE MARGIN Full temp. range, C
C
= 1.8nF 65 *
OUTPUT
VOLTAGE SWING
3
T
C
= 25C, I
O
= 30A V
S
7 6.2 * * V
VOLTAGE SWING
3
Full temp. range, I
O
= 12A V
S
5 4.2 * * V
VOLTAGE SWING
3
Full temp. range, I
O
= 146mA V
S
4 3.5 * * V
CURRENT, peak T
C
= 25C 30 * A
C
= 25C, 10V step 8 * s
SLEW RATE T
C
= 25C, C
C
- open 8 * V/s
CAPACITIVE LOAD Full temp. range, A
V
= 1 2 * nF
SHUTDOWN DELAY T
C
= 25C, disable 10 * s
T
C
= 25C, operate 20 * s
POWER SUPPLY
CURRENT, quiescent
6
T
C
= 25C 125 300 * * mA
CURRENT, disable mode Full temperature range 25 40 * * mA
THERMAL
5
Full temp. range, F>60Hz .22 .28 * * C/W
RESISTANCE, DC junction to case Full temp. range, F<60Hz .25 .3 * * C/W
RESISTANCE, junction to ambient Full temperature range 14 * C/W
TEMPERATURE, junction Sustained operation 150 * C
TEMPERATURE RANGE, case Meets full range specifcation 25 85 * * C
SPECIFICATIONS
SUPPLY VOLTAGE, +V
S
to V
S
150V
OUTPUT CURRENT, within SOA Internally limited
S
TEMPERATURE, pin solder-10s 300C
1
175C
OPERATING TEMP. RANGE, case 55 to +125C
SHUTDOWN VOLTAGE, differential 5V
SHUTDOWN VOLTAGE, common mode V
S
1. Long term operation at the maximum junction temperature will result in reduced product life. Derate power dissipation to achieve
high MTTF.
2. The power supply voltage for all specifcations is the TYP rating unless noted as a test condition.
3. +V
S
and V
S
S
is measured from +V
S
to V
S
.
4. Rating applies if both shutdown inputs are least 1V inside supply rails. If one of the shutdown inputs is tied to a supply rail, the
current in that pin may increase to 2.4mA.
6. The PA03 must be used with a heatsink or the quiescent power may drive the unit into thermal shutdown.
PA03 PA03A
276 PA02U
0
0
100
300
500
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
15 105
.25
64
256
BIAS CURRENT
4
.06
10 100 10K .1M
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/
H
z
)
1 100 10M
FREQUENCY, F (Hz)
20
0
60
120
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
20
40
80
100
1 100 .1M 10M
210
150
60
0
PHASE RESPONSE
90
30
0 5 20 25
OUTPUT CURRENT, I
O
(A)
1
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
HARMONIC DISTORTION
TIME, t (S)
40
S
(V)
.4
1.4
N
O
R
M
A
L
I
Z
E
D
,

I
Q

(
X
)
.6
1.2
1 10K
FREQUENCY, F (Hz)
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
120
.1M 10 100 0
PULSE RESPONSE
V
O
L
T
S
50 100
CASE TEMPERATURE, T
C
(C)
0
40
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
30
INPUT NOISE
1K
1K
5 45 65 85
16
200
POWER RESPONSE
10
60 80 100 120 140
1.0
25 75
10
10 1K 10K .1M 1M
400
10 10K 1M
FREQUENCY, F (Hz)
P
H
A
S
E
,

)
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
1K 1M
20
60
100
5 10 15 20 25 30
7.5
5.0
2.5
0
2.5
5.0
7.5
2
3
4
5
6
7
.8
1
125
50
CASE TEMPERATURE, T
C
(C)
180
120
25
FREQUENCY, F (Hz)
D
I
S
T
O
R
T
I
O
N
,

(
%
)

V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y

(
V
)
FREQUENCY, F (Hz)
40 80 120 160 200
20
50 25 0
2
4
6
10
20
5K 10K 50K 100K 300K
150
10
20
30
40
50
100
3K
QUIESCENT CURRENT
30 100 300 1K 3K 10K 30K
1.0
0.3
0.1
.03
.01
.003
30 15
C
C
= 470pF
C
C
=

O
P
E
N
C
C
=

1
8
0
0
p
F
C
C

=

O
P
E
N
C
C

=

1
8
0
0
p
F
T C
=

5
5
C
TC
=
2
5
C
T C

=

1
2
5
C
V
IN
= .5V, A
V
= 10
R
L
=.5
C
C

=

O
P
E
N
C
C

=

1
8
0
0
p
F
C
C

=

4
7
0
p
F
T
C
= 85C
TC
=
2
5
C
TC
=
1
2
5
C
TC
=

2
5
C
V
S
= 50V
A
V
= 10
P
O
= 200W
R
L
= 4
0
CASE TEMPERATURE, T
C
(C)
PA03 PA03A
PA02U 277
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GENERAL
MOUNTING PRECAUTIONS
The PA03 copper base is very soft and easily bent. Do not
put any stress on the mounting ears of this package. This calls
for caution when pushing the amplifer into certain types of
packaging foam and particularly when inserting the device into
a socket. Insert the amplifer into the socket only by pushing
on the perimeter of the package lid. Pushing the unit into the
socket by applying pressure to the mounting tabs will bend
the base due to the high insertion force required. The base
will then not contact the heatsink evenly resulting in very poor
heat transfer. To remove a unit from a socket, pry the socket
away from the heatsink so that the heatsink will support the
amplifer base evenly. Recommended mounting torque is 810
in.-lbs. (.91.13 Nm).
Due to the internal (non-adjustable) current limit of the PA03,
worst case power dissipation calculations must assume cur-
rent capability of 46 amps. Application specifc circuits should
be checked against the SOA curve when relying upon current
limit for fault protection.
SAFE OPERATING AREA CURVES
Second breakdown limitations do apply to the PA03 but are
less severe, since junction temperature limiting responds within
10ms. Stress levels shown as being safe for more than 10ms
duration will merely cause thermal shutdown.
Under normal operating conditions, activation of the thermal
shutdown is a sign that the internal junction temperatures have
reached approximately 175C. Thermal shutdown is a short
term safety feature. If the conditions remain that cause thermal
shutdown, the amplifer will oscillate in and out of shutdown,
creating peak high power stresses, destroying useful signals,
and reducing the reliability of the device.
BALANCE CONTROL
The voltage offset of the PA03 may be externally adjusted
to zero. To implement this adjustment install a 100 to 200 ohm
potentiometer between pins 11 and 12 and connect the wiper
arm to the positive supply. Bypass pins 11 and 12 each with
at least a .01F ceramic capacitor.
If the optional adjust provision is not used, connect both
pins 11 and 12 to the positive supply.
OUTPUT STAGE SHUTDOWN
The entire power stage of the PA03 may be disabled us-
ing one of the circuits shown in Figure 1. There are many
applications for this function. One is a load protection based
on power delivered to the load or thermal rise. Another one is
conservation of power when using batteries. The control volt-
age requirements accommodate a wide variety logic drivers.
1. CMOS operating at +5V can drive the control pins di-
rectly.
2. CMOS operating at greater than 5V supplies need a voltage
divider.
3. TTL logic needs a pull up resistor to +5V to provide a swing
to the fully disabled voltage (3.5V). When not using the
shutdown feature, connect both pins 3 and 4 to common.
PHASE COMPENSATION
At low gain settings an external compensation capacitor
is required to insure stability. In addition to the resistive feed-
back network, roll off or integrating capacitors must also be
considered. A frequency of 1 MHz is most appropriate to cal-
culate gain. Operation at gains below 10, without the external
compensation capacitor opens the possibility of oscillations
near output saturation regions when under load, the improper
operation of the thermal shutdown circuit. This can result in
amplifer destruction.
At gains of 10 or more:
1. No external components are required.
2. Typical slew rate will be 8V/s.
3. Typical phase margin will be 70.
1
10 20 50 100 150
5
10
30
40
SUPPLY TO OUTPUT DIFFERENTIAL V
S
V
O
(V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S

(
A
)
CURRENT LIMIT ZONE
1
.0
m
S
1
0
m
S
1
0
0
m
S
T
H
E
R
M
A
L
S
E
C
O
N
D

B
R
E
A
K
D
O
W
N
T
C
= 25C
dc
SOA
1
2
3
4
5
6
12
11
10
9
8
7
TOP
VIEW
BALANCE CONTROL
BALANCE CONTROL
PHASE COMP.
PHASE COMP.
+SUPPLY
+OUTPUT
INPUT
+INPUT
SHUT DN
+SHUT DN
SUPPLY
OUTPUT
Pins 6 & 7 must be
connected together.
If unused, tie Pins
11 & 12 to +SUPPLY.
IMPORTANT: OBSERVE
MOUNTING PRECAUTIONS.
REVERSE INSERTION
WILL DESTROY UNIT.
The internal substrate contains beryllia (BeO).
Do not break the seal. If accidentally broken, do
not crush, machine, or subject to temperatures
in excess of 850C to avoid generating toxic
fumes.
CAUTION
PA03 PA03A
278 PA02U
4
3
0 = OPERATE
1 = SHUT DN
500
Q14
Q22
1K 1K
*
+5V
500
PA03
* NOT REQUIRED
WHEN USING
CMOS LOGIC
FIGURE 1a.
DIRECT DRIVE
OF SHUTDOWN
3
0 = SHUT DN
1 = OPERATE
500
Q14
Q22
1K R
+15V
500
PA03
FIGURE 1b.
HIGH VOLTAGE
LOGIC INTERFACE
CMOS 4
4
3
500
Q14
Q22
1K
R1
**
500 PA03
FIGURE 1c.
THERMALLY
ACTIVATED
SHUTDOWN R2
4.7K
LOAD
R4
30K
R3
360
360
400mV
THERMAL SENSE
TRANSISTOR
+V
S
2R
** SELECT SHUTOFF
TEMPERATURE
SELECT R4 FOR 5V
DROP ON R2
At a gain of 3:
1. Connect a 470pF compensation capacitor between
pins 9 and 10.
2. Typical slew rate will be 5V/s.
At unity gain:
1. Connect a 1.8nF compensation capacitor between
pins 9 and 10.
2. Typical slew rate will be 1.8V/s.
IMPORTANT NOTICE
PA04 PA04A
PA04U 279
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C
B
A
G
H
I
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D
C
B
A
12
9
1
5
6
8
10
11
7
2
4
3
SLEEP
+V
BOOST
Q10
IN
Q14 Q15
Q21
V
BOOST
COMP
Q22
+IN
Q20
COMP
Q17
D1
Q5
Q12
Q19
Q26
Q18
Q13
+Vs
Q6
I
LIM
I
LIM
OUT
Q7
Vs
D5 D6
D2
D3
D7
D9
D8
D4
TYPICAL APPLICATION
PA04 allows driving sonar transducers via a resonant circuit
including the transducer and a matching transformer. The load
circuit appears resistive to the PA04. Control logic turns off the
amplifer in sleep mode.
Sonar Transducer Driver
PHASE COMPENSATION
Gain C
C
R
C
1 470pF 120
>3 220pF 120
10 100pF 120
C
C
RATED FOR FULL SUPPLY VOLTAGE
*See BOOST OPERATION paragraph.
CONTROL
LOGIC
ULTRA-
SONIC
DRIVE
R
f
R
i 1
12
2
7
10
11
R
CL
TUNED
TRANSFORMER
PA04
TOPVIEW
-INPUT
+INPUT
SLEEP
CURRENT LIMIT
CURRENT LIMIT
C
C
R
C
1
2
3
4
5
6
12
11
10
9
8
7
TOPVIEW
COMP
-V
BOOST
-SUPPLY
+SUPPLY
OUTPUT *
*
COMP
+V
BOOST
FEATURES
HIGH INTERNAL DISSIPATION 200 WATTS
HIGH SLEW RATE 50V/S
LOW DISTORTION
EXTERNAL SLEEP MODE CONTROL
EVALUATION KIT SEE EK09
APPLICATIONS
SONAR TRANSDUCER DRIVER
AUDIO UP TO 400W
DESCRIPTION
The PA04 is a high voltage MOSFET power operational
amplifer that extends the performance limits of power ampli-
fers in slew rate and power bandwidth, while maintaining high
current and power dissipation ratings.
The PA04 is a highly fexible amplifer. The sleep mode
feature allows ultra-low quiescent current for standby opera-
tion or load protection by disabling the entire amplifer. Boost
voltage inputs allow the small signal portion of the amplifer to
operate at a higher voltage than the high current output stage.
The amplifer is then biased to achieve close linear swings to
the supply rails at high currents for extra efficient operation.
External compensation tailors performance to user needs.
A four wire sense technique allows precision current limiting
without the need to consider internal or external milliohm
parasitic resistance in the output line.
The JEDEC MO-127 12-pin Power Dip package (see
Package Outlines) is hermetically sealed and isolated from
the internal circuits. The use of compressible thermal washers
will void product warranty.
12-PIN DIP
PACKAGE STYLE CR
MAY 2009
APEX PA04UREVL
PA04 PA04A
280 PA04U
SUPPLY VOLTAGE, +V
S
to V
S
200V
BOOST VOLTAGE SUPPLY VOLTAGE +20V
S

2
150C
SPECIFICATIONS
PA04 PA04A
1
INPUT
OFFSET VOLTAGE, initial 5 10 2 5 mV
BIAS CURRENT, initial 10 50 5 20 pA
OFFSET CURRENT, initial 10 50 5 20 pA
11
*
B
-8 * V
CM
= 20V 86 98 * * dB
S
= 1K 10 * Vrms
GAIN
OPEN LOOP, @ 15Hz Full temperature range, C
C
= 100pF 94 102 * * dB
O
= 10A 2 * MHz
POWER BANDWIDTH R
L
= 4.5, V
O
= 180V p-p 90 * kHz
C
C
= 100pF, R
C
= 120
OUTPUT
VOLTAGE SWING I
O
= 15A V
S
-8.8 V
S
-7.5 * * V
VOLTAGE SWING V
BOOST
= Vs + 5V, I
O
= 20A V
S
-6.8 V
S
-5.5 * * V
CURRENT, peak 20 * A
V
= 1, 10V step, R
L
= 4 2.5 * s
SLEW RATE A
V
= 10, C
C
= 100pF, R
C
= 120 40 50 * V/s
V
= +1 10 * nF
RESISTANCE 2 *
POWER SUPPLY
CURRENT, quiescent, boost supply 30 40 * * mA
CURRENT, quiescent, total 70 90 * * mA
CURRENT, quiescent, total, sleep mode Full temperature range 3 5 * * mA
THERMAL
3
Full temperature range, F>60Hz .3 .4 * * C/W
RESISTANCE, DC, junction to case Full temperature range, F<60Hz .5 .6 * * C/W
RESISTANCE
4
C
= 25C, C
C
= 470pF, R
C
= 120 ohms. DC input specifcations are value given. Power supply volt-
age is typical rating. V
BOOST
= V
S
.
4. The PA04 must be used with a heatsink or the quiescent power may drive the unit to junction temperatures higher than 150C.
The PA04 is constructed from MOSFET transistors. ESD handling procedures must be observed.
CAUTION
PA04 PA04A
PA04U 281
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
0 25 50 75 100 125 150
TEMPERATURE, T
C
(C)
0
50
150
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
100 1K 10M
FREQUENCY F (Hz)
0
50 0 75 125
CASE TEMPERATURE, T
C
(C)
N
O
R
M
A
L
I
Z
E
D

C
U
R
R
E
N
T

L
I
M
I
T
,

(
%
)
10 10M
FREQUENCY,Ff (Hz)
0
120
SMALL SIGNAL GAIN
O
P
E
N

L
O
O
P

G
A
I
N

R
E
S
P
O
N
S
E
,

A

(
d
B
)
40
80
FREQUENCY, F (Hz)
SMALL SIGNAL PHASE
0 5 15 20
2
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S
V
O

(
V
)
30 300 30K
FREQUENCY, F (Hz)
.001
.02
.2
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

T
H
D

(
%
)
.002
.01
.1
30 200
S
(V)
.8
.9
1.2
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
1.0
1.1
10K 50K 1M
FREQUENCY, F (Hz)
20
60
180
200
POWER RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
80
100
10
FREQUENCY, F (Hz)
0
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
100
1M 100 1K 0 10 15
TIME, t (s)
5
0
PULSE RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
30 5 20
100 200
EXT. COMPENSATION CAPACITOR C
C
(pF)
0
60
SLEW RATE
S
L
E
W

R
A
T
E
,

S
R

(
V
/
s
)
40
100 1K 3K 10K 20K .6M
40
25
CURRENT LIMIT
50
60
70
10 10K 100K 1M
100
200
10
50 100 150
20
7.5
1 100 1K 10K 100K 1M
20
40
60
80
100
300 400 500
O
P
E
N

L
O
O
P

P
H
A
S
E
,

)
100 10M 1 10 1K 10K 100K 1M
180
135
90
45
0
4
6
8
10
12
OUTPUT CURRENT, I
O
(A)
10K 100K
2.5
2.5
5
7.5
25 25 100
80
90
100
110
120
130
.005
.05
.2M
120
150
20
60
T = T
C
T = T
A
R
C
= 120
R
L
= 4
VB
O
O
S
T
=
VS
VBOOST
=
VS
+
5
V
A
V
= +1
A
V
= 10
R
L
= 4
C
C
= 100pF, R
C
= 120
V
S
= 62V
R
C
=120
R
L
= 4.0
C
C
= 470pF
C
C

=

2
2
0
p
F
C
C

=

1
0
0
p
F
C
C

=

4
7
0
p
F
P
O

=

2
0
0
W
P
O
= 1W
P
O

=

3
0
0
W
R
C
= 120
R
L
= 4
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)
4 LOAD
R
C
= 120
C
C
=

4
7
0
p
F
C
C
=

1
0
0
p
F
C
C
=

2
2
0
p
F
C
C
= 470pF
C
C
= 220pF
C
C
= 100pF
PA04 PA04A
282 PA04U
GENERAL
CURRENT LIMIT
resistor, R
CL
any parasitic resistances, Rp, formed by sockets and solder
where shown in Figure 1.
follows:
.76
R
CL
=
I
LIMIT
Figure 1.
Current Limit.
The MOSFET output stage of this power operational ampli-
fer has two distinct limitations:
1. The current handling capability of the MOSFET geometry
and the wire bonds.
2. The junction temperature of the output MOSFETs.
NOTE: The output stage is protected against transient fy-
back. However, for protection against sustained, high
energy fyback, external fast-recovery diodes should
be used.
SLEEP MODE OPERATION
In the sleep mode, pin 12 (sleep) is tied to pin 9 (+V
BOOST
).
This disables the amplifers internal reference and the am-
plifer shuts down except for a trickle current of 3 mA which
fows into pin 12. Pin 12 should be left open if the sleep mode
is not required.
Several possible circuits can be built to take advantage of
this mode. In Figure 2A a small signal relay is driven by a logic
gate. This removes the requirement to deal with the common
mode voltage that exists on the shutoff circuitry since the sleep
mode is referenced to the +V
BOOST
voltage.
In Figure 2B, circuitry is used to level translate the sleep
mode input signal. The differential input activates sleep mode
with a differential logic level signal and allows common mode
voltages to V
BOOST
.
BOOST OPERATION
With the V
BOOST
feature the small signal stages of the
amplifer are operated at higher supply voltages than the
BOOST
(pin 9) and
V
BOOST
(pin 5) are connected to the small signal circuitry of
the amplifer. +V
S
(pin 8) and V
S
(pin 6) are connected to the
high current output stage. An additional 5V on the V
BOOST
pins
is sufficient to allow the small signal stages to drive the output
transistors into saturation and improve the output voltage
swing for extra efficient operation when required. When close
swings to the supply rails is not required the +V
BOOST
and +V
S

BOOST
and V
S

pins. The boost voltage pins must not be at a voltage lower
than the V
S
pins.
COMPENSATION
C
and R
C
are con-
bandwidth and slew rate. Use the typical operating curves as
a guide to select C
C
and R
C
for the application.
FIGURE 2A. SLEEP MODE CIRCUIT.
LOGIC K1 9
12
9
12
+V
BOOST
SLEEP
+V
BOOST
SLEEP
560
470
Q1
1K
Q2
V
BOOST
470
LOGIC
INPUT
+
-
FIGURE 2B. SLEEP MODE CIRCUIT.
R
f
R
i 1
2
10
11
R
CL
PA04
R
P
R
L
CL
CL INPUT
7
SOA
5.0
2.0
.5
.2
2
SUPPLY TO OUTPUT DIFFERENTIAL (V)
O
U
T
P
U
T

C
U
R
R
E
N
T

(
A
)
5 10 20 50 200
20
D
C

T
C
=

1
2
5
C
D
C

T
C
=

8
5
C
D
C

T
C
=

2
5
C
t

=

1
0
m
s
t

=

1
m
s
10
100
1.0
PA05 PA05A
PA05U 283
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
and/or improper mounting torque will void the product warranty.
Please see General Operating Considerations.
TYPICAL APPLICATION
The high power bandwidth of the PA05 allows driving sonar
transducers via a resonant circuit including the transducer and
a matching transformer. The load circuit appears resistive to
the PA05. Control logic turns off the amplifer's output during
shutdown.
PHASE COMPENSATION
Gain C
C
R
C
1 470pF 120
>3 220pF 120
10 82pF 120
C
C
*See BOOST OPERATION paragraph.
FEATURES
HIGH INTERNAL DISSIPATION 250 WATTS
LOW DISTORTION
EXTERNAL SHUTDOWN CONTROL
EVALUATION KIT SEE EK09
APPLICATIONS
sonar transducer driver
AUDIO UP TO 500W
DESCRIPTION
The PA05 is a high voltage MOSFET power operational
amplifer that extends the performance limits of power ampli-
fers in slew rate and power bandwidth, while maintaining high
current and power dissipation ratings.
The PA05 is a highly fexible amplifer. The shutdown control
feature allows the output stage to be turned off for standby
operation or load protection during fault conditions. Boost
voltage inputs allow the small signal portion of the amplifer to
operate at a higher voltage than the high current output stage.
The amplifer is then biased to achieve close linear swings to
the supply rails at high currents for extra efficient operation.
External compensation tailors slew rate and bandwidth per-
formance to user needs. A four wire sense technique allows
precision current limiting without the need to consider internal
or external milliohm parasitic resistance in the output line. The
output stage is protected by thermal limiting circuits above
junction temperatures of 175C.
12
9
5
6
8
10
SHUTDOWN
+V
BOOST
IN
V
BOOST
+IN
+Vs
I
LIM
I
LIM
OUT
Vs
BIAS
7
4
3
COMP
2
1
11
Q12 Q13
Q1
Q8
Q4
Q5
Q10
Q16 Q17
Q22
Q14
Q18
Q24
Q21
Q25
Q29
Q30 Q33
D1
D6
D9
D5
D19
D20
D27
D31
D4
CONTROL
LOGIC
ULTRA-
SONIC
DRIVE
R
f
R
i 1
12
2
10
11
R
CL
TUNED
TRANSFORMER
PA05
7
TOP
VIEW
INPUT
+INPUT
SHUTDOWN
CURRENT LIMIT
CURRENT LIMIT
C
C
R
C
1
2
3
4
5
6
12
11
10
9
8
7
TOP
VIEW
COMP
V
BOOST
SUPPLY
+V
BOOST
+SUPPLY
OUTPUT *
*
COMP
12-PIN POWER DIP
PACKAGE STYLE CR
MAY 2009
APEX PA05UREVJ
PA05 PA05A
284 PA05U
SUPPLY VOLTAGE, +V
S
to V
S
100V
BOOST VOLTAGE SUPPLY VOLTAGE +20V
OUTPUT CURRENT, continuous within SOA 30A
B

2
175C
SPECIFICATIONS
CAUTION
C
= 25C, C
C
= 470pF, R
C
= 120 ohms. DC input specifcations are value given. Power supply volt-
age is typical rating. V
BOOST
= V
S
.
4. The PA05 must be used with a heatsink or the quiescent power may drive the unit to junction temperatures higher than 150C.
PA05 PA05A
1
INPUT
OFFSET VOLTAGE, vs. supply 10 30 * * V/V
11
*
B
8 * V
CM
= 20V 90 100 * * dB
INPUT NOISE 100KHz BW, R
S
= 1K 10 * Vrms
GAIN
OPEN LOOP, @ 15Hz Full temperature range, C
C
= 82pF 94 102 * * dB
GAIN BANDWIDTH PRODUCT R
L
= 10 3 * MHz
POWER BANDWIDTH R
L
= 4, V
O
= 80V
P-P
, A
V
= 10 400 * kHz
C
C
= 82pF, R
C
= 120
PHASE MARGIN Full temperature range, C
C
= 470pF 60 *
OUTPUT
VOLTAGE SWING I
O
= 20A V
S
9.5 V
S
8.7 * * V
VOLTAGE SWING V
BOOST
= Vs + 5V, I
O
= 30A V
S
5.8 V
S
5.0 * * V
CURRENT, peak 30 * A
V
= +1, 10V step, R
L
= 4 2.5 * s
SLEW RATE A
V
= 10, C
C
= 82pF, R
C
= 120 80 100 * V/s
V
= +1 2.2 * nF
RESISTANCE I
O
= 0, No load, 2MHz 5 *
I
O
= 1A, 2MHz 2 *
POWER SUPPLY
CURRENT, quiescent, boost supply 46 56 * * mA
CURRENT, quiescent, total, shutdown 46 56 * * mA
THERMAL
3
Full temperature range, F>60Hz .3 .4 * * C/W
RESISTANCE, DC, junction to case Full temperature range, F<60Hz .4 .5 * * C/W
4
PA05 PA05A
PA05U 285
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
0 25 50 75 100 125 150
CASE TEMPERATURE, T
C
(C)
0
100
200
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
100 1K 10M
FREQUENCY F (Hz)
0
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)
50 0 75 125
CASE TEMPERATURE, T
C
(C)
N
O
R
M
A
L
I
Z
E
D

C
U
R
R
E
N
T

L
I
M
I
T
,

(
%
)
100 10M
FREQUENCY, F (Hz)
0
20
60
100
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
40
80
FREQUENCY, F (Hz)
225
PHASE RESPONSE
0 5 20 30
2
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

V
O

(
V
)
30 300 30K
FREQUENCY, f (Hz)
.001
.02
.2
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

T
H
D

(
%
)
.002
.01
.1
20 100
S
(V)
.8
.9
1.2
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
1.0
1.1
40K .4M 4M
FREQUENCY, F (Hz)
2
POWER RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
10
FREQUENCY, F (Hz)
0
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
60
80
100
1M 100 1K 0 10 15
TIME, t (s)
5
0
PULSE RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
30 5 20
100 1K 3K 10K
25
CURRENT LIMIT
50
60
70
10 10K 100K 1M
150
250
15
40 60 80
7.5
10 1K 10K 100K 1M
20
40
60
80
100
P
H
A
S
E
,

)
100 10M 10 1K 10K 100K 1M
180
135
90
45
0
4
6
8
10
12
OUTPUT CURRENT, I
O
(A)
10K 100K
2.5
2.5
5
7.5
A
V
= +1
25 25 100
80
90
100
110
120
130
.005
.05
A
V
= 10
R
L
= 2
C
C
= 82pF, R
C
= 120
V
S
= 31V
C
C
= 470pF
P
O

=

2
0
0
W
P
O
= 1W
P
O

=

3
0
0
W
40
20
50
R
L
= 8
R
C
= 120
C
C
= 82pf
C
C
= 220pf
C
C
= 470pf
C
C
= 470pf
C
C
= 220pf
C
C
= 82pf
4
6
10
20
40
60
100
C
C
=

8
2
p
F
C
C
=

4
7
0
p
F
C
C
=

2
2
0
p
F
VB
O
O
S
T
=
VS
VBOOST
=
VS
+
5
V
10 25
100K 1M
20
60
40
EXT. COMPENSATION CAPACITOR C
C
(pF)
100 200 300 400 500
80
100
SLEW RATE vs. COMP
S
L
E
W

R
A
T
E

S
R

(
V
/
S
)
C
C
= 82pf
C
C
= 220pf
C
C
= 470pf
R
L
= 8
R
C
= 120
PA05 PA05A
286 PA05U
GENERAL
CURRENT LIMIT
work correctly, pin 11 must be connected to the amplifer output
resistor, R
CL
any parasitic resistances, R
P
formed by sockets and solder
where shown in Figure 1. If current limiting is not used, pins 10
and 11 must be tied to pin 7.
follows:
and the wire bonds.
NOTE: The output stage is protected against transient fy-
back. However, for protection against sustained, high energy
fyback, external fast-recovery diodes should be used.
The output stage thermal protection circuit engages when
junction temperatures reach approximately 175C. If the condition
remains that caused the shutdown, the amplifer may oscillate
in and out of shutdown, creating high peak power stresses
reducing the reliability of the device.
SHUTDOWN OPERATION
To disable the output stage, pin 12 is connected to ground
via relay contacts or via an electronic switch. The switching
device must be capable of sinking 2mA to complete shutdown
and capable of standing off the supply voltage +V
S
. See Figure
2 for suggested circuits.
From an internal circuitry standpoint, shutdown is just a
special case of current limit where the allowed output current
is zero. As with current limit, however, a small current does
fow in the output during shutdown. A load impedance of 100
ohms or less is required to insure the output transistors are
turned off. Note that even though the output transistors are off
the output pin is not open circuited because of the shutdown
operating current.
BOOST OPERATION
With the V
BOOST
feature, the small signal stages of the ampli-
fer are operated at higher supply voltages than the amplifers
BOOST
(pin 9), and V
BOOST
(pin
5) are connected to the small signal circuitry of the amplifer.
+V
S
(pin 8) and V
S
(pin 6) are connected to the high current
output stage. An additional 5V on the V
BOOST
pins is sufficient
to allow the small signal stages to drive the output transistors
into saturation and improve the output voltage swing for extra
efficient operation when required. When close swings to the
supply rails is not required the +V
BOOST
and +V
S
pins must be
strapped together as well as the V
BOOST
and V
S
pins. The boost
voltage pins must not be at a voltage lower than the V
S
pins.
COMPENSATION
C
and R
C
are con-
least 60 degrees of phase margin. At higher gains, more phase
bandwidth and slew rate. Use the typical operating curves as
a guide to select C
C
and R
C
for the application.
1
SUPPLY TO OUTPUT DIFFERENTIAL (V)
O
U
T
P
U
T

C
U
R
R
E
N
T

(
A
)
2 5 10 30 100
.3
.6
.9
1.2
1.5
3
6
9
12
15
30
D
C

T
C
=

1
2
5
C
D
C

T
C
=

8
5
C
D
C

T
C
=

2
5
C
t

=

2
0
0
m
s
3 4 20 40 50
SOA
I
LIMIT
= .7/R
CL
R
i
1
2
10
11
R
CL
PA05
R
P
R
L
CL
CL INPUT
7
R
f
LOGIC
K1
SHUTDOWN
470
Q1
FIGURE 2. SHUTDOWN OPERATION
12
12
SHUTDOWN
LOGIC
A
B
PA07 PA07A
PA07U 287
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA07, PA07A
TYPICAL APPLICATION
Negates optoelectronic instabilities
Lead network minimizes overshoot
SEQUENTIAL POSITION CONTROL
Position is sensed by the differentially connected photo
diodes, a method that negates the time and temperature
variations of the optical components. Off center positions
produce an error current which is integrated by the op amp
circuit, driving the system back to center position. A momen-
tary switch contact forces the system out of lock and then the
integrating capacitor holds drive level while both diodes are
in a dark state. When the next index point arrives, the lead
network of C1 and R1 optimize system response by reducing
overshoot. The very low bias current of the PA07 augments
performance of the integrator circuit.
NOTE: Input offset voltage trim optional. R
T
= 10K MAX
FEATURES
LOW BIAS CURRENT FET Input
PROTECTED OUTPUT STAGE Thermal Shutoff
EXCELLENT LINEARITY Class A/B Output
WIDE SUPPLY RANGE 12V TO 50V
HIGH OUTPUT CURRENT 5A Peak
APPLICATIONS
DESCRIPTION
The PA07 is a high voltage, high output current operational
amplifer designed to drive resistive, inductive and capacitive
loads. For optimum linearity, especially at low levels, the out-
put stage is biased for class A/B operation using a thermistor
compensated base-emitter voltage multiplier circuit. A thermal
shutoff circuit protects against overheating and minimizes
heatsink requirements for abnormal operating conditions. The
safe operating area (SOA) can be observed for all operating
conditions by selection of user programmable current limiting
resistors. Both amplifers are internally compensated for all
gain settings. For continuous operation under load, a heatsink
of proper rating is recommended.
This hybrid circuit utilizes thick flm (cermet) resistors, ceramic
capacitors and semiconductor chips to maximize reliability,
minimize size and give top performance. Ultrasonically bonded
aluminum wires provide reliable interconnections at all operating
temperatures. The 8-pin TO-3 package is hermetically sealed
and electrically isolated. The use of compressible washers
CL+
+V
+IN
IN
V
BAL
CL
OUT
S
S
TOP VIEW
R
CL+
R
CL
R
T
R
S
OUTPUT
R
S
= ( V
S
+ + V
S
) R
T
/1.6
1
2
3
4
5
6
7
8
MOTOR
R
CL+
R
CL
C
L C
F
R
L
R
F2
R
F1
+32V
.68
.68
32V
+V
V
PD1 PD2
LIGHT
V = 28
EMF = 14V
R = 14
PA07
W
3
7
5
4
6
2
1
8
Q1 Q2
Q5
Q4
Q3
Q8 Q9
C3
Q12A Q12B
Q10
Q15
Q18
D2
D3
D1
C2
C4
Q11
Q16
Q19
C1
Q7
Q6A
Q6B
Q17A
Q17B
8-PIN TO-3
PACKAGE STYLE CE
FET Input Power Operational Amplifier
MAY 2009
APEX PA07UREVP
PA07 PA07A
288 PA07U
SPECIFICATIONS
SUPPLY VOLTAGE, +V
S
to V
S
100V
1
67W
S

1
200C
PA07 PA07A
2
INPUT
C
= 25C .5 2 .25 .5 mV
C
= 25C 8 * V/V
3
T
C
= 25C 5 50 3 10 pA
BIAS CURRENT,vs. supply T
C
= 25C .01 * pA/V
OFFSET CURRENT, initial
3
T
C
= 25C 2.5 50 1.5 10 pA
C
= 25C 10
11
*
INPUT CAPACITANCE T
C
= 25C 4 * pF
4
S
10 * V
COMMON MODE REJECTION, DC Full temperature range, V
CM
= 20V 120 * dB
GAIN
C
= 25C, R
L
= 15 89 95 * * dB
C
= 25C, R
L
= 15 1.3 * MHz
POWER BANDWIDTH T
C
= 25C, R
L
= 15 18 * kHz
PHASE MARGIN Full temperature range, R
L
= 15 70 *
OUTPUT
VOLTAGE SWING
4
Full temp. range, I
O
= 5A V
S
5 * V
VOLTAGE SWING
4
Full temp. range, I
O
= 2A V
S
5 * V
VOLTAGE SWING
4
Full temp. range, I
O
= 90mA V
S
5 * V
CURRENT, peak T
C
= 25C 5 * A
C
= 25C, 2V step 1.5 * s
SLEW RATE T
C
= 25C 5 * V/s
CAPACITIVE LOAD, gain>4 Full temperature range SOA *
POWER SUPPLY
C
= 25C 18 30 * * mA
THERMAL
5
F>60Hz 1.9 2.1 * * C/W
RESISTANCE, DC, junction to case F<60Hz 2.4 2.6 * * C/W
TEMPERATURE RANGE, case Meets full range specifcations 25 25 +85 * * * C
achieve high MTTF.
2. The power supply voltage for all specifcations is the TYP rating unless otherwise noted as a test condition.
3. Doubles for every 10C of temperature increase.
4. +V
S
and V
S
S
is measured from +V
S
to V
S
.
CAUTION
PA07 PA07A
PA07U 289
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
40 100
S
(V)
.4
.6
1.6
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
.8
1.4
50 60 70 80 90
1.2
1.0
T
C
= 25C
T
C
= 25C
T
C
= 85C
T
C
= 125C
0 2 3 6
OUTPUT CURRENT, I
O
(A)
0
2
6
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S
A
T

(
V
)
3
5
1 5
1
4
4
TC
=
2
5
C
T
C
=
8
5
C
TC
=

2
5
C
15 25 105
.06
1
64
256
BIAS CURRENT
4
.25
5 45 65 85
16
TEMPERATURE, T
C
(C)
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
0 20 40 60 80 100 120
0
10
30
50
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
20
70
140
40
60
T = T
C
T = T
A
TEMPERATURE, T
C
(C)
1 100 10M
FREQUENCY, F (Hz)
20
0
60
120
O
P
E
N

L
O
O
P

G
A
I
N
,

A
O
L

(
d
B
)
20
40
80
100
10 1K 10K .1M 1M 1 100 .1M 10M
180
150
60
0
PHASE RESPONSE
90
30
1K 10 10K 1M
FREQUENCY, F (Hz)
P
H
A
S
E
,

)
120
210
50 25 50 100
CASE TEMPERATURE, T
C
(C)
0
3.0
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
2.5
0 25 75
1.0
1.5
.5
2.0
R
CL
= 0.6
R
CL
= 0.3
1 10K
FREQUENCY, F (Hz)
0
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
120
.1M 10 100 1K 1M
20
60
100
0
TIME, t (s)
PULSE RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
8
2 4 6 8 10 12
6
4
2
0
2
4
6
8
V
IN
= 5V, t
r
= 100ns
10K 20K 50K .1M
FREQUENCY, F (Hz)
4.6
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
POWER RESPONSE
30K 70K
6.8
10
15
22
32
46
68
100
|+V
S
| + |-V
S
| = 100V
|+V
S
| + |-V
S
| = 70V
10 100 10K .1M
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/
H
z
)
INPUT NOISE
1K
2
10
20
4
6
100 1K 3K .1M
FREQUENCY, F (Hz)
.3
3
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

T
H
D

(
%
)
.01
.1
1
300 10K 30K
.03
P
O

=

5
0
W
,

V
S

=

2
5
V
,

R
L

=

4
P
O

=

5
0
m
W
,

R
L

=

8
G =10
10
P
O

=

6
0
W
,

V
S

=

3
6
V
,

R
L

=

8
PA07 PA07A
290 PA07U
GENERAL
interpretation. Visit www.Cirrus.com for design tools that help
limitations:
1. The current handling capability of the wire bonds.
exceed specifed limits.
complex for reactive and EMF generating loads. However,
the following guidelines may save extensive analytical efforts.
1. For DC outputs, especially those resulting from fault condi-
tions, check worst case stress levels against the new SOA
graph.
For sine wave outputs, use Power Design
1
to plot a load
no more than 10%.
For other waveform outputs, manual load line plotting is
recommended. Applications Note 22, SOA AND LOAD
T
c
=
1
2
5
C T
H
E
R
M
A
L
s
t
e
a
d
y

s
t
a
t
e

S
E
C
O
N
D

B
R
E
A
K
D
O
W
N
t

=

1
m
s
t

=

5
m
s
t

=

0
.
5
m
s
.2
.3
.4
.6
.8
1.0
1.5
2.0
3.0
4.0
5.0
10 15 20 25 30 35 40 50 60 70 80 100
T
c
=
8
5
C
S
V
O
(V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S

(
A
)
2. The amplifer can handle any reactive or EMF generating
load and short circuits to the supply rail or common if the
current limits are set as follows at T
C
= 85C:
SHORT TO V
S
SHORT TO
V
S
50V .21A .61A
40V .3A .87A
30V .46A 1.4A
20V .87A 2.5A
15V 1.4A 4.0A
These simplifed limits may be exceeded with further analysis
using the operating conditions for a specifc application.
3. The output stage is protected against transient fyback.
However, for protection against sustained, high energy
THERMAL SHUTDOWN PROTECTION
The thermal protection circuit shuts off the amplifer when
the substrate temperature exceeds approximately 150C. This
allows heatsink selection to be based on normal operating
conditions while protecting the amplifer against excessive
junction temperature during temporary fault conditions.
Thermal protection is a fairly slow-acting circuit and therefore
does not protect the amplifer against transient SOA violations
(areas outside of the T
C
= 25C boundary). It is designed to
protect against short-term fault conditions that result in high
power dissipation within the amplifer. If the conditions that
cause thermal shutdown are not removed, the amplifer will
oscillate in and out of shutdown. This will result in high peak
power stresses, will destroy signal integrity and reduce the
reliability of the device.
CURRENT LIMIT
tors, connected as shown in the external connections diagram.
CL
is .12, however, for optimum
1
available free from www.Cirrus.com
PA07M/883
PA07MU 291
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA07M/883
Q
25C 35V V
IN
= 0, A
V
= 100 30 mA
OS
25C 35V V
IN
= 0, A
V
= 100 2 mV
OS
25C 12V V
IN
= 0, A
V
= 100 4.3 mV
OS
25C 50V V
IN
= 0, A
V
= 100 3.5 mV
B
25C 35V V
IN
= 0 50 pA
B
25C 35V V
IN
= 0 50 pA
OS
25C 35V V
IN
= 0 50 pA
Q
55C 35V V
IN
= 0, A
V
= 100 46 mA
OS
55C 35V V
IN
= 0, A
V
= 100 4.4 mV
OS
55C 12V V
IN
= 0, A
V
= 100 6.7 mV
OS
55C 50V V
IN
= 0, A
V
= 100 5.9 mV
B
55C 35V V
IN
= 0 50 pA
B
55C 35V V
IN
= 0 50 pA
OS
55C 35V V
IN
= 0 50 pA
Q
125C 35V V
IN
= 0, A
V
= 100 30 mA
OS
125C 35V V
IN
= 0, A
V
= 100 5 mV
OS
125C 12V V
IN
= 0, A
V
= 100 7.3 mV
OS
125C 50V V
IN
= 0, A
V
= 100 6.5 mV
B
125C 35V V
IN
= 0 10 nA
B
125C 35V V
IN
= 0 10 nA
OS
125C 35V V
IN
= 0 10 nA
4 Output Voltage, I
O
= 5A V
O
25C 15.3V R
L
= 2.07 10.3 V
4 Output Voltage, I
O
= 90mA V
O
25C 50V R
L
= 500 45 V
4 Output Voltage, I
O
= 2A V
O
25C 29V R
L
= 12 24 V
4 Current Limits I
CL
25C 19V R
L
= 12, R
CL
= 1 .54 .86 A
4 Stability/Noise E
N
25C 35V R
L
= 100, A
V
= 1, C
L
= 1nF 1 mV
L
= 500 2.5 10 V/s
4 Open Loop Gain A
OL
25C 35V R
L
= 500, F = 15Hz 89 dB
4 Common Mode Rejection CMR 25C 34.5V R
L
= 500, F = DC, V
CM
= 24.5V 80 dB
6 Output Voltage, I
O
= 5A V
O
55C 15.3V R
L
= 2.07 10.3 V
6 Output Voltage, I
O
= 90mA V
O
55C 50V R
L
= 500 45 V
6 Output Voltage, I
O
= 2A V
O
55C 29V R
L
= 12 24 V
6 Stability/Noise EN 55C 35V R
L
= 100, A
V
= 1, C
L
= 1nF 1 mV
L
= 500 2.5 10 V/s
6 Open Loop Gain A
OL
55C 35V R
L
= 500, F = 15Hz 89 dB
L
= 500, F = DC, V
CM
= 24.5V 80 dB
5 Output Voltage, I
O
= 3A V
O
125C 11.3V R
L
= 2.07 6.3 V
5 Output Voltage, I
O
= 90mA V
O
125C 50V R
L
= 500 45 V
5 Output Voltage, I
O
= 2A V
O
125C 29V R
L
= 12 24 V
5 Stability/Noise E
N
125C 35V R
L
= 100, A
V
= 1, C
L
= 1nF 1 mV
L
= 500 1.25 10 V/s
5 Open Loop Gain A
OL
125C 35V R
L
= 500, F = 15Hz 89 dB
L
= 500, F = DC, V
CM
= 24.5V 80 dB
BURN IN CIRCUIT
* These components are used to stabilize device due
to poor high frequency characteristics of burn in
board.
** Input signals are calculated to result in internal power
dissipation of approximately 2.1W at case tempera-
ture = 125C.
100K
1
1
100K
+15V
15V
5
6
2
1
8
3
20
**
*
U.U.T
4
*
SEP 2009
APEX - PA07MUREVL
PA08 PA08A
292 PA08U
FEATURES
WIDE SUPPLY RANGE 15V to 150V
PROGRAMMABLE OUTPUT CURRENT LIMIT
HIGH OUTPUT CURRENT Up to 150mA
APPLICATIONS
HIGH VOLTAGE INSTRUMENTATION
ELECTROSTATIC TRANSDUCERS & DEFLECTION
ANALOG SIMULATORS
DESCRIPTION
The PA08 is a high voltage operational amplifer designed
for output voltage swings of up to 145V with a dual () sup-
ply or 290V with a single supply. High accuracy is achieved
with a cascode input circuit confguration. All internal biasing
is referenced to a zener diode fed by a FET constant current
source. As a result, the PA08 features an unprecedented sup-
ply range and excellent supply rejection. The output stage is
biased-on for linear operation. Internal phase compensation
assures stability at all gain settings. The safe operating area
(SOA) can be observed with all types of loads by choosing
the appropriate current limiting resistors. For operation into
inductive loads, two external fyback pulse protection diodes
are recommended. A heatsink may be necessary to maintain
the proper case temperature under normal operating conditions.
This hybrid integrated circuit utilizes beryllia (BeO) substrate,
thick flm resistors, ceramic capacitors and semiconductor chips
to maximize reliability, minimize size and give top performance.
use of compressible thermal isolation washers and/or improper
mounting torque will void the product warranty. Please see
General Operating Considerations.
TYPICAL APPLICATION
ATE PIN DRIVER
The PA08 as a pin driver is capable of supplying high test
voltages to a device under test (DUT). Due to the possibility
of short circuits to any terminal of the DUT, current limit must
be set to be safe when limiting with a supply to output volt-
age differential equal to the amplifer supply plus the largest
magnitude voltage applied to any other pin of the DUT. In
addition, fyback diodes are recommended when the output of
the amplifer exits any equipment enclosure to prevent damage
due to electrostatic discharges. Refer to Application Note 7
for details on accuracy considerations of this circuit.
CL+
+V
+IN
IN
V
BAL
CL
OUT
S
S
TOP VIEW
R
CL+
R
CL
OUTPUT
1
2
3
4
5
6
7
8
R
S
R
T
T
= 10K MAX
R
S
= ( +V
S
+ -V
S
) R
T
/1.6
PA08
-132V
+132V
110K
+V
S
-V
S
+132V
-132V
8.2
8.2
1mA
D.U.T.
DAC
3
5
6
2
7
8
D1
Q1
Q3
Q5
Q2
D2
C4
Q12A Q12B
4
Q15
Q4
C3
Q11
Q16
Q6
C1
Q7
Q19
Q17
1
Q10
Q9 C2 Q8
8-PIN TO-3
PACKAGE STYLE CE
MAY 2009
APEX PA08UREVM
PA08 PA08A
PA08U 293
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SPECIFICATIONS
SUPPLY VOLTAGE, +V
S
to V
S
300V
OUTPUT CURRENT, within SOA 200mA
POWER DISSIPATION, internal at T
C
= 25C 17.5W
S

TEMPERATURE, pin solder - 10s max 300C
1
175C
PA08 PA08A
2
INPUT
C
= 25C .5 2 .25 .5 mV
OFFSET VOLTAGE, vs. temperature T
C
= 25C to +85C 15 30 5 10 V/C
C
= 25C .5 * 2 V/V
OFFSET VOLTAGE, vs. time T
C
= 25C 75 * V/kh
3
T
C
= 25C 5 50 3 10 pA
C
= 25C .01 * pA/V
3
T
C
= 25C 2.5 50 1.5 10 pA
C
= 25C 10
5
* M
INPUT CAPACITANCE T
C
= 25C 4 * pF
4
T
C
= 25C to +85C V
S
10 * V
COMMON MODE REJECTION, DC T
C
= 25C to +85C, V
CM
= 90V 130 * dB

GAIN
C
= 25C, R
L
= 118 * dB
C
= 25C, R
L
= 1.2K 96 111 * * dB
C
= 25C, R
L
= 1.2K 5 * MHz
POWER BANDWIDTH T
C
= 25C, R
L
= 1.2K 90 * kHz
PHASE MARGIN T
C
= 25 to +85C 60 *
OUTPUT
VOLTAGE SWING
4
T
C
= 25C, I
O
= 150mA V
S
15 V
S
8 * * V
VOLTAGE SWING
4
T
C
= 25
o
C to +85
o
C, I
O
= 75mA V
S
10 V
S
5 * * V
VOLTAGE SWING
4
T
C
= 25
o
C to +85
o
C, I
O
= 20mA V
S
5 V
S
3 * * V
CURRENT, peak T
C
= 85C 150 * mA
SLEW RATE T
C
= 25C 30 20 * V/s
CAPACITIVE LOAD, A
V
= 1 T
C
= 25 to +85C 10 * nF
CAPACITIVE LOAD, A
V
> 4 T
C
= 25 to +85C SOA *
C
= 25C, R
L
= 1.2K, 2V step 1 * s
POWER SUPPLY
VOLTAGE T
C
= 55 to +125C 15 100 150 * * * V
C
= 25C 6 8.5 * * mA
THERMAL
5
T
C
= 55 to +125C, F > 60Hz 4.26 * C/W
RESISTANCE, DC junction to case T
C
= 55 to +125C, F < 60Hz 6.22 8.57 * * C/W
RESISTANCE, junction to air T
C
= 55 to +125C 30 * C/W
high MTTF.
2. The power supply voltage specifed under typical (TYP) applies unless otherwise noted.
3. Doubles for every 10
o
C of temperature increase.
4. +V
S
and V
S
denote the positive and negative supply rail respectively.
5. Rating applies only if output current alternates between both output transistors at a rate faster than 60Hz.

CAUTION
PA08 PA08A
294 PA08U
0 25 50 75 100 125
TEMPERATURE, T (C)
0
5
10
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
D

(
W
)
-55 0 100
0
200
250
100
10 100 10K .1M
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/
H
z
)
1 100 10M
FREQUENCY, F (Hz)
-20
0
60
120
O
P
E
N

L
O
O
P

G
A
I
N
,

A
O
L

(
d
B
)
20
40
80
100
0 100 .1M 10M
210
150
60
0
PHASE RESPONSE
90
30
50K .1M .3M .7M
FREQUENCY, F (Hz)
15
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
1 100 1K 1M
FREQUENCY, F (Hz)
0
100
140
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N

C
M
R

(
d
B
)
20
60
120
1 1M
FREQUENCY, F (Hz)
0
40
140
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)
60
120
10K 50K .2M
FREQUENCY, F (Hz)
30
300
COMMON MODE VOLTAGE
C
O
M
M
O
N

M
O
D
E

V
O
L
T
A
G
E
,

V
C
M

(
V
P
-
P
)
60
200
1.5
6
2
2
6
2.0 0 .5 30
PULSE RESPONSE
N
O
R
M
A
L
I
Z
E
D

S
L
E
W

R
A
T
E

(
X
)
50 250
S
(V)
4
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
m
A
)
2
10 10K .1M 20K 1M
15
INPUT NOISE
1K
2
4
1K
-25 25 50 75
150
2.5
15
POWER RESPONSE
.2M
10 100 1K 10K .1M
20
30
.4
10 1K 10K .1M 1M
150
7.5
12.5
10 10K 1M
FREQUENCY, F (Hz)
P
H
A
S
E
,

)
R
E
L
A
T
I
V
E

O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
0
1 2.5
4
0
4
50 100 150 200 250 300
.6
.8
1.0
1.2
1.4
1.6
.5M
30
60
100
200
300
40
.5M
100
125
50
300
6
CASE TEMPERATURE, T
C
(C)
180
120
6
10
15
20
100
OPEN LOOP GAIN
SLEW RATE
2
4
6
100 150 200
T
C =
-
2
5
C
T
C
=
8
5
C
T
C
= -25C
R
CL
= 4.7
R
CL
= 10
R
L
=1.2K
R
L
=1.2K
R
L
=1.2K
1M
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
V
IN
= 5V, t
r
= 100ns
TIME, t (s)
R
L
=1.2K
S
(V)
80
80
.1M
|+V
S
| + |V
S
| = 300V
|+V
S
| + |V
S
| = 100V
|+V
S
| + |V
S
| = 100V
|+V
S
| + |V
S
| = 300V
+V
S
V
S
20
17.5
PA08 PA08A
PA08U 295
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
such as calculations for stability, internal power dissipation, cur-
rent limit and heat sink selection. The "Application Notes" and
"Technical Seminar" sections contain a wealth of information
on specifc types of applications. Package outlines, heat sinks,
mounting hardware and other accessories are located in the
"Packages and Accessories" section. Evaluation Kits are avail-
able for most Apex Precision Power product models, consult
the "Evaluation Kit" section for details. For the most current
version of all Apex Precision Power product data sheets, visit
www.Cirrus.com.
The output stage of most power amplifers has two distinct
limitations:
and the wire bonds.
complex for reactive and EMF generating loads. However, the
following guidelines may save extensive analytical efforts.
1. Under transient conditions, the following capacitive and
inductive loads are safe with the current limits set to the
maximum:
V
S
C(MAX) L(MAX)
150V .4F 280mH
125V .9F 380mH
100V 2F 500mH
75V 10F 1200mH
50V 100F 13H
2. The amplifer can handle any EMF generating or reactive
load and short circuits to the supply rails or simple shorts
to common if the current limits are set as follows:
200
150
100
80
50
40
30
20
80 100 120 150 170 200 250 300
SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE (V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S

(
m
A
)
s
t
e
a
d
y

s
t
a
t
e
t

=

5
m
s
t

=

1
m
s
t

=

0
.
5
m
s
t

=

2
0
0
s
SHORT TO V
SC,
SHORT TO
V
S
150V 20mA 67mA
125V 27mA 90mA
100V 42mA 130mA
75V 67mA 200mA
50V 130mA 200mA
INDUCTIVE LOADS
Two external diodes as shown in Figure 1, are required
to protect these amplifers from fyback (kickback) pulses
exceeding the supply voltages of the amplifer when driving
inductive loads. For component selection, these external diodes
must be very quick, such as ultra fast recovery diodes with no
more than 200 nanoseconds of reverse recovery time. The
diode will turn on to divert the fyback energy into the supply
rails thus protecting the output transistors from destruction due
to reverse bias.
A note of caution about the supply. The energy of the fyback
pulse must be absorbed by the power supply. As a result, a tran-
sient will be superimposed on the supply voltage, the magnitude
of the transient being a function of its transient impedance and
current sinking capability. If the supply voltage plus transient
exceeds the maximum supply rating or if the AC impedance of
the supply is unknown, it is best to clamp the output and the
supply with a zener diode to absorb the transient.
INPUT PROTECTION
The input is protected against common mode voltages up to
the supply rails and differential voltages up to 50V. Increased
protection against differential input voltages can be obtained by
adding 2 resistors, 2 capacitors and 4 diode connected FETs
as shown in Figure 2.
CURRENT LIMITING
tors, connected as shown in the external connection diagram.
CL
is 3.24. However, for optimum
PROTECTION, INDUCTIVE LOAD PROTECTION, OVERVOLTAGE
IN4936 OR
UES1106
+V
S
V
S
100pf/200V
100pf/200V
150K
150K
+IN
IN
Fig. 1 Fig. 2
+
_
Q1
Q2
Q3
Q4
PA08M
296 PA08MU
PA08M/883
Q
25C 100V V
IN
= 0, A
V
= 100 8.5 mA
OS
25C 100V V
IN
= 0, A
V
= 100 2 mV
OS
25C 15V V
IN
= 0, A
V
= 100 3.7 mV
OS
25C 150V V
IN
= 0, A
V
= 100 3 mV
B
25C 100V V
IN
= 0 50 pA
B
25C 100V V
IN
= 0 50 pA
OS
25C 100V V
IN
= 0 50 pA
Q
55C 100V V
IN
= 0, A
V
= 100 9.5 mA
OS
55C 100V V
IN
= 0, A
V
= 100 4.4 mV
OS
55C 15V V
IN
= 0, A
V
= 100 6.1 mV
OS
55C 150V V
IN
= 0, A
V
= 100 5.4 mV
B
55C 100V V
IN
= 0 50 pA
B
55C 100V V
IN
= 0 50 pA
OS
55C 100V V
IN
= 0 50 pA
Q
125C 100V V
IN
= 0, A
V
= 100 12 mA
OS
125C 100V V
IN
= 0, A
V
= 100 5 mV
OS
125C 15V V
IN
= 0, A
V
= 100 6.7 mV
OS
125C 150V V
IN
= 0, A
V
= 100 6 mV
B
125C 100V V
IN
= 0 10 nA
B
125C 100V V
IN
= 0 10 nA
OS
125C 100V V
IN
= 0 10 nA
4 Output Voltage, I
O
= 150mA V
O
25C 31V R
L
= 100 15 V
4 Output Voltage, I
O
= 29mA V
O
25C 150V R
L
= 5K 145 V
4 Output Voltage, I
O
= 80mA V
O
25C 90V R
L
= 1K 80 V
4 Current Limits I
CL
25C 30V R
L
= 100 75 125 mA
4 Stability/Noise E
N
25C 100V R
L
= 5K, A
V
= 1, C
L
= 1nF 1 mV
L
= 5K 20 100 V/s
4 Open Loop Gain A
OL
25C 100V R
L
= 5K, F = 10Hz 96 dB
L
= 5K, F = DC, V
CM
= 22.5V 90 dB
6 Output Voltage, I
O
= 100mA V
O
55C 31V R
L
=100 10 V
6 Output Voltage, I
O
= 29mA V
O
55C 150V R
L
= 5K 145 V
6 Output Voltage, I
O
= 70mA V
O
55C 90V R
L
= 1K 70 V
6 Stability/Noise E
N
55C 100V R
L
= 5K, A
V
= 1, C
L
= 1nF 1 mV
L
= 5K 20 100 V/s
6 Open Loop Gain A
OL
55C 100V R
L
= 5K, F = 10Hz 96 dB
L
= 5K, F = DC, V
CM
= 22.5V 90 dB
5 Output Voltage, I
O
= 150mA V
O
125C 31V R
L
= 100 15 V
5 Output Voltage, I
O
= 29mA V
O
125C 150V R
L
= 5K 145 V
5 Output Voltage, I
O
= 80mA V
O
125C 90V R
L
= 1K 80 V
5 Stability/Noise E
N
125C 100V R
L
= 5K, A
V
= 1, C
L
= 1nF 1 mV
L
= 5K 20 100 V/s
5 Open Loop Gain A
OL
125C 100V R
L
= 5K, F = 10Hz 96 dB
L
= 5K, F = DC, V
CM
= 22.5V 90 dB
100K
5
100K
+50V
50V
5
6
2
1
8
3
60
**
*
U.U.T
4
*
5
BURN IN CIRCUIT
* These components are used to stabilize device due to poor
high frequency characteristics of burn in board.
** Input signals are calculated to result in internal power dis-
sipation of approximately 2.1W at case temperature = 125C.
SEP 2009
APEX PA08MUREVL
PA08V
PA08VU 297
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA08V
FEATURES
EXTENDED SUPPLY RANGE
UP TO 175V or
350V TOTAL
PROVIDES PA08 PERFORMANCE
UP TO 150mA
LOW DRIFT FET INPUT
APPLICATIONS
PIEZO ELECTRIC TRANSDUCERS
DESCRIPTION
The PA08V is an extended supply range operational amplifer
capable of output voltage swings of 170V with dual supplies or
340V total supply voltage on single or non-symmetric supplies.
High accuracy is achieved with a cascode input circuit con-
fguration. All internal biasing is referenced to a zener diode
fed by a FET constant current source. As a result, the PA08
features an unprecedented supply range and excellent sup-
ply rejection. The output stage is biased class A-B for linear
operation. Internal phase compensation assures stability at all
gain settings. The safe operating area (SOA) can be observed
with all types of loads by choosing the appropriate current limit-
ing resistors. For operation into inductive loads, two external
fyback pulse protection diodes are recommended. A heatsink
may be necessary to maintain the proper case temperature
under normal operating conditions.
This hybrid integrated circuit utilizes a beryllia (BeO) sub-
strate, thick flm resistors, ceramic capacitors, and semicon-
ductor chips to maximize reliability, minimize size and give top
performance. Ultrasonically bonded aluminum wires provide
reliable interconnections at all operating temperatures. The
8-pin to TO-3 package is hermetically sealed and electrically
isolated. The use of compressible thermal isolation washers
SPECIFICATIONS
Specifcations of the standard PA08 apply with the beneft
of supply ratings being extended to 175V. Design changes
enabling the total supply rating of 350V have no effect on the
shape of the typical performance graphs.
GENERAL CONSIDERATIONS
SAFE OPERATING AREA
The extended safe operating area is as follows:
When operating on 175V, maximum safe values of capaci-
tive and inductive loading are .2F and 200mH. Maximum safe
current limit for a short to common is 50mA, and for a short to
supply rails, the maximum is 15mA.
3
5
6
2
7
8
D1
Q1
Q3
Q5
Q2
D2
C4
Q12A Q12B
4
Q15
Q4
C3
Q11
Q16
Q6
C1
Q7
Q19
Q17
1
Q10
Q9 C2 Q8
100 300 200
20
30
40
50
100
150
15
250 150 125 175 350 90
80
SAFE OPERATING AREA CURVE (SOA)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S

(
m
A
)
t

=

2
0
0
s t

=

0
.
5
m
s t

=

1
m
s
t

=

5
m
s
s
t
e
a
d
y

s
t
a
t
e
Please consult the PA08 data sheet for basic information
on this amplifer, plus the application notes in this Apex Preci-
sion Power DATA BOOK, for recommendations on stability,
current limiting, heatsinks, bypassing, and suggestions for
circuit functions.
8-PIN TO-3
PACKAGE STYLE CE
PA08V P r o d u c t I n n o v a t i o n F r o m
MAY 2009
APEX PA08VUREVH
PA09 PA09A
298 PA09U
+37V
37V
470pF
R
F
100
R
S

.5

R
D
3.9K
C
F
PA09
V
I
4
3
7
8
1
C
C
5pF
di
dt
= 2A/s
i = V
i
/R
S
L
Y
13H
1
5
6
FIGURE 1. PA09 AS DEFLECTION AMPLIFIER
PA09, PA09A
FEATURES
POWER MOS TECHNOLOGY 2A peak rating
HIGH GAIN BANDWIDTH PRODUCT 150MHz
VERY FAST SLEW RATE 200V/s
PROTECTED OUTPUT STAGE Thermal shutoff
EXCELLENT LINEARITY Class A/B output
LOW BIAS CURRENT, LOW NOISE FET input
APPLICATIONS
VIDEO DISTRIBUTION AND AND AMPLIFICATION
HIGH SPEED DEFLECTION CIRCUITS
POWER TRANSDUCERS TO 2MHz
COAXIAL LINE DRIVERS
POWER LED OR LASER DIODE EXCITATION
DESCRIPTION
The PA09 is a high voltage, high output current operational
amplifer optimized to drive a variety of loads from DC through
the video frequency range. Excellent input accuracy is achieved
with a dual monolithic FET input transistor which is cascoded
by two high voltage transistors to provide outstanding common
mode characteristics. All internal current and voltage levels are
referenced to a zener diode biased on by a current source. As
a result, the PA09 exhibits superior DC and AC stability over
a wide supply and temperature range.
High speed and freedom from second breakdown is assured
by a complementary Power MOS output stage. For optimum
linearity, especially at low levels, the Power MOS transistors
are biased in the class A/B mode. Thermal shutoff provides
full protection against overheating and limits the heatsink
requirements to dissipate the internal power losses under
normal operating conditions. A built-in current limit protects the
amplifer against overloading. Transient inductive load kickback
protection is provided by two internal clamping diodes. External
phase compensation allows the user maximum fexibility in
obtaining the optimum slew rate and gain bandwidth product
at all gain settings. For continuous operation under load, a
heatsink of proper rating is recommended.
This hybrid integrated circuit utilizes thick flm (cermet) resis-
tors, ceramic capacitors and silicon semiconductor chips to
connections at all operating temperatures. The CE, 8-pin TO-3
package is hermeti-
cally sealed and elec-
trically isolated. The
use of compressible
thermal washers and/
or improper mount-
ing torque will void
the product warranty.
Please see General
Operating Consider-
ations.
DEFLECTION AMPLIFIER (FIGURE 1)
The defection amplifer circuit of Figure 1 achieves arbi-
trary beam positioning for a fast heads-up display. Maximum
transition times are 4s while delivering 2A pk currents to the
13mH coil. The key to this circuit is the sense resistor (R
S
)
which converts yoke current to voltage for op amp feedback.
This negative feedback forces the coil current to stay exactly
proportional to the control voltage. The network consisting of
R
D
, R
F
and C
F
serves to shift from a current feedback via R
S

to a direct voltage feedback at high frequencies. This removes
the extra phase shift caused by the inductor thus preventing
oscillation. See Application Note 5 for details of this and other
precision magnetic defection circuits.
3
6
2
7
8
5
4
1
Q1
Q5
Q2
D1
D2
Q18
Q15
Q10
Q12B
Q9
C2
Q8
Q12A
Q4
Q3
C1
Q6
Q13
Q11
Q14
D3
Q16
Q17
Q7
Q19
TOP VIEW
1
2
3
4
5
6
7
8
C
C
V
S
+IN
IN
+V
S
OUT
BAL
C
C R
C
R
S
= (|+V
S
| + |V
S
|) R
T
/1.6
T
= 10K MAX
R
T
R
S
8-PIN TO-3
PACKAGE STYLE CE
MAY 2009
APEX PA09UREVM
PA09 PA09A
PA09U 299
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SPECIFICATIONS
SUPPLY VOLTAGE, +V
S
to V
S
80V
1
78W
S
1
150C
PA09 PA09A
2
INPUT
OFFSET VOLTAGE, initial .5 3 .25 .5 mV
OFFSET CURRENT, initial 2.5 50 1.5 10 pA
11
*
3
S
10 V
S
8 * * V
CM
= 20V 104 * dB
GAIN
OPEN LOOP GAIN at 15Hz R
L
= 1k 80 98 * dB
GAIN BANDWIDTH PRODUCT at 1MHz C
C
= 5pF 150 * MHz
POWER BANDWIDTH R
L
= 15, C
C
= 5pF 750 * KHz
POWER BANDWIDTH R
L
= 15, C
C
= 100pF 150 * KHz
OUTPUT
VOLTAGE SWING
3
Full temperature range, I
O
= 2A V
S
8 V
S
7 * * V
CURRENT, PEAK 4.5 * A
SETTLING TIME to 1% 4V step, C
C
= 100pF .75 * s
SETTLING TIME to .1% 4V step, C
C
= 100pF 1.3 * s
SLEW RATE C
C
= 5pF 220 * V/s
SLEW RATE C
C
= 100pF 25 * V/s
RESISTANCE 7.5 *
POWER SUPPLY
THERMAL
4
Full temperature range, F > 60Hz 1.2 1.3 * * C/W
RESISTANCE, DC junction to case Full temperature range, F < 60Hz 1.6 1.8 * * C/W
TEMPERATURE RANGE, case Meets full range specifcations 25 25 + 85 * * * C
CAUTION
high MTTF.
C
= 25C, supply voltage = 35V.
3. +V
S
and -V
S
S
is measured from +V
S
to V
S
.
PA09 PA09A
300 PA09U
0 25 50 75 100 125
CASE TEMPERATURE, T
C
(C)
10
40
60
80
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
55 100
4
8
9
CURRENT LIMIT
6
3
10 100 10K 1M
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/
H
z
)
1
3
5
8
10
7
9
100K
COMMON MODE VOLTAGE
C
O
M
M
O
N

M
O
D
E

V
O
L
T
A
G
E
,

V
C
M

(
V
P
P
)
1K 10M
FREQUENCY, F (Hz)
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
120
10K 100K 1K
FREQUENCY, F(Hz)
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
15
INPUT NOISE
1K
10
15
20
25 25 50 75
7
50
150
70
OUTPUT CURRENT, I
O
(A)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y

(
V
)
1M
20
60
100
10K 100K 1M 100M
0
20
40
60
80
100
5
J
(C)
4
6
30
300K 1M 3M 10M 30M
20
30
40
50
70
0
100M
10
2
1
125
2 3 4 5
10M
7
5
3
100K
7
30
20
0
| +V
S
| + | V
S
| = 80V
C
C
= 100pF
FREQUENCY, F (Hz)
0
V/s
GAIN
HIGH
300
100
30
10
3
1
1K 300 100 3 1 30 10
G
A
I
N

A
N
D

S
L
E
W

R
A
T
E
,

(
V
/
s
)
SLEW RATE vs. COMP.
1000
COMPENSATION CAPACITOR, C
C
(pF)
LOW
100
80
60
40
20
0
-20
100M 10M 1M 100K 100 10 10K 1K
5pF
33pF
100pF
15pF
FREQUENCY, F (Hz)
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
0
-40
-80
-120
-160
-200
100M 10M 1M 100K 100 10 10K 1K
FREQUENCY, F (Hz)
O
P
E
N

L
O
O
P

P
H
A
S
E
,

)
PHASE RESPONSE
5pF
33pF
100pF
330pF
15pF
ALL
OTHERS
330pF
6.2pF
33pF
100pF
330pF
15pF
60
50
40
30
20
10
1M 3K 1K 30 10 300 100
FREQUENCY, F (KHz)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
P
)
POWER RESPONSE
90
80
70
100
330pF
30 60 80
S
(V)
1.4
QUIESCENT CURRENT
1.2
40 50 70
.6
.8
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
1.0
1.6
PA09 PA09A
PA09U 301
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
SUPPLY VOLTAGE
The specifed voltage (V
S
) applies for a dual () supply
having equal voltages. A nonsymmetrical (ie. +70/10V) or a
single supply (ie. 80V) may be used as long as the total volt-
age between the +V
S
and V
S
rails does not exceed the sum
of the voltages of the specifed dual supply.
and the wire bonds.
The SOA curves combine the effect of these limits and allow
for internal thermal delays. For a given application, the direc-
tion and magnitude of the output current should be calculated
or measured and checked against the SOA curves. This is
simple for resistive loads but more complex for reactive and
EMF generating loads. The following guidelines may save
extensive analytical efforts:
1. Capacitive and inductive loads up to the following maximums
are safe:
V
S
40V .1F 11mH
30V 500F 24mH
20V 2500F 75mH
15V 100mH
2. Short circuits to ground are safe with dual supplies up to
20V.
BYPASSING OF SUPPLIES
Each supply rail must be bypassed to common with a tanta-
lum capacitor of at least 47F in parallel with a .47F ceramic
capacitor directly connected from the power supply pins to the
ground plane.
OUTPUT LEADS
Keep the output leads as short as possible. In the video
frequency range, even a few inches of wire have signifcant
inductance, raising the interconnection impedance and limit-
ing the output current slew rate. Furthermore, the skin effect
increases the resistance of heavy wires at high frequencies.
Multistrand Litz Wire is recommended to carry large video
currents with low losses.
GROUNDING
Single point grounding of the input resistors and the input
signal to a common ground plane will prevent undesired cur-
rent feedback, which can cause large errors and/or instabilities.
"Single point" is a key phrase here; a ground plane should be
used as shielding rather than a current path. Leaving the case
of the PA09 foating will cause oscillations in some applications.
COMPENSATION
The PA09 is extremely fexible in terms of choice of compen-
sation capacitor for any given gain. The most common ranges
are shown in the COMPENSATION typical performance graph.
Swinging closer to the supply rails, heavier loads, faster input
signal rise and fall times and higher supply voltages all tend to
demand larger values of compensation capacitor. This capaci-
tor must be rated at least as high as the total voltage applied
to the amplifer. In making specifc value choices, use the
square wave stability test presented in APPLICATION NOTE
19, Figures 40 and 41.
In addition to small signal testing, if the application includes
step functions in the input signal, use this circuit to measure
large signal response. By increasing square wave amplitude to
the maximum of the application, this test may show signifcant
distortion of the output waveform following the square wave
transitions. In this case the faster input stages of the PA09
are out-running the output stage and overload recovery time
creates the distortion. This speed relationship is also why
slew rate does not increase for compensation values below
about 27pF.
SUPPLY CURRENT
When swinging large signals, the output stage of the PA09
demands extra supply current. The following graphs illustrate
this current for several conditions for both sine and square
wave signals. Current is exclusive of any load current and will
affect both supply rating and thermal ratings. When calculat-
ing internal power dissipation, multiply this current times total
supply voltage.
Note that swinging closer to the supply rail demands more
30 50 80 20 40
2.0
5.0
15
3.0
4.0
1.5
2.5
3.5
60 70 25 35
INTERNAL VOLTAGE DROP SUPPLY TO OUTPUT V
S
V
O
(V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S

(
A
)
T
C
= 25C
t

=

1
0
0
m
s
s
t
e
a
d
y

s
t
a
t
e
t

=

3
0
0
m
s
SOA
PA09 PA09A
302 PA09U
current. Output voltage is given as peak. Currents are aver-
age responding supply readings, but AC monitoring will reveal
current pulses corresponding to periods of high slew rate. For
example, driving 30V outputs at 500KHz on 40V supplies
produces a .8A pulse during negative slew and a 1.2A pulse
during positive slew. If the input signal is over driven by several
times the output swing capability, pulses up to 4A may be seen.

THERMAL SHUTDOWN PROTECTION
allows heatsink selection to be based on normal operating
15V
O
/23V
S
32V
O
/40V
S
15V
O
/40V
S
7.0
5.5
4.0
2.5
1.0
1M 10K 100K
N
O
R
M
A
L
I
Z
E
D

I
Q
,

(
X
)
QUIESCENT vs. SQUARE DRIVE
FREQUENCY, F (KHz)
1
5
V
O

/
2
3
V
S
3
2
V
O

/
4
0
V
S
1
5
V
O

/
4
0
V
S
1.5
1.4
1.3
1.2
1.1
1.0
1000 100 300
N
O
R
M
A
L
I
Z
E
D

I
Q
,

(
X
)
QUIESCENT vs. SINE DRIVE
FREQUENCY, F (KHz)
(areas outside of the T
C
= 25C boundary). It is designed to
power dissipation within the amplifer, If the conditions that
power stresses, destroy signal integrity, and reduce the reli-
ability of the device.
STABILITY
Due to its large bandwidth the PA09 is more likely to oscillate
than lower bandwidth Power Operational Amplifers. To prevent
oscillations a reasonable phase margin must be maintained by:
1. Pay very careful attention to supply bypassing and circuit
grounding. This is very important when step functions are
driven and the PA09 shares supplies with more active
devices.
2. Keeping the external sumpoint stray capacitance to ground
at a minimum and the sumpoint load resistance (input and
feedback resistors in parallel) below 500. Larger sumpoint
load resistances can be used with increased phase com-
pensation and/or bypassing of the feedback resistor.
3. Connect the case to a local AC ground potential.
CURRENT LIMIT
Internal current limiting is provided in the PA09. Note the
current limit curve given under typical performance graphs is
based on junction temperature. If the amplifer is operated at
cold junction temperatures, current limit could be as high as 8
amps. This is above the maximum allowed current on the SOA
curve of 5 amps. Systems using this part must be designed to
keep the maximum output current to less than 5 amps under all
conditions. The internal current limit only provides this protec-
tion for junction temperatures of 80C and above.
PA09M
PA08MU 303
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA09M/883
Q
25C 35V V
IN
= 0, A
V
= 100 85 mA
OS
25C 35V V
IN
= 0, A
V
= 100 3 mV
OS
25C 12V V
IN
= 0, A
V
= 100 5.3 mV
OS
25C 40V V
IN
= 0, A
V
= 100 3.5 mV
B
25C 35V V
IN
= 0 100 pA
1 Inout Bias Current, IN I
B
25C 35V V
IN
= 0 100 pA
OS
25C 35V V
IN
= 0 50 pA
Q
55C 35V V
IN
= 0, A
V
= 100 165 mA
OS
55C 35V V
IN
= 0, A
V
= 100 5.4 mV
OS
55C 12V V
IN
= 0, A
V
= 100 7.7 mV
OS
55C 40V V
IN
= 0, A
V
= 100 5.9 mV
B
55C 35V V
IN
= 0 100 pA
B
55C 35V V
IN
= 0 100 pA
OS
55C 35V V
IN
= 0 50 pA
Q
125C 35V V
IN
= 0, A
V
= 100 140 mA
OS
125C 35V V
IN
= 0, A
V
= 100 6 mV
OS
125C 12V V
IN
= 0, A
V
= 100 8.3 mV
OS
125C 40V V
IN
= 0, A
V
= 100 6.5 mV
B
125C 35V V
IN
= 0 10 nA
B
125C 35V V
IN
= 0 10 nA
OS
125C 35V V
IN
= 0 10 nA
4 Output Voltage, I
O
= 3A V
O
25C 21.3V R
L
= 3.75 11.3 V
4 Output Voltage, I
O
= 66mA V
O
25C 40V R
L
= 500 33 V
4 Output Voltage, I
O
= 2A V
O
25C 38V R
L
= 15 30 V
4 Current Limits I
CL
25C 32.2V R
L
= 3.75 3.4 6 A
4 Stability/Noise E
N
25C 35V R
L
= 500, A
V
= 1, C
L
= 1.5nF 1 mV
L
= 500 25 500 V/s
4 Open Loop Gain A
OL
25C 35V R
L
= 500, F = 10Hz 80 dB
L
= 500, F = DC, V
CM
= 22.5V 64 dB
6 Output Voltage, I
O
= 3A V
O
55C 21.3V R
L
= 3.75 11.3 V
6 Output Voltage, I
O
= 66mA V
O
55C 40V R
L
= 500 33 V
6 Output Voltage, I
O
= 2A V
O
55C 38V R
L
= 15 30 V
6 Stability/Noise E
N
55C 35V R
L
= 500, A
V
= 1, C
L
= 1.5nF 1 mV
L
= 500 25 500 V/s
6 Open Loop Gain A
OL
55C 35V R
L
= 500, F = 10Hz 80 dB
L
= 500, F = DC, V
CM
= 22.5V 64 dB
5 Output Voltage, I
O
= 66mA V
O
125C 40V R
L
= 500 33 V
5 Output Voltage, I
O
= 1A V
O
125C 23.5V R
L
= 15 15 V
5 Stability/Noise E
N
125C 35V R
L
= 500, A
V
= 1, C
L
= 1.5nF 1 mV
L
= 500, 20 500 V/s
5 Open Loop Gain A
OL
125C 35V R
L
= 500, F = 10Hz 80 dB
L
= 500, F = DC, V
CM
= 22.5V 64 dB
BURN IN CIRCUIT
due to poor high frequency characteristics of burn
in board.
temperature = 125C.
100K
100K
+15V
15V
5
1
8
3
20
**
*
U.U.T
4
*
220
100pF
7
SEP 2009
APEX PA09MUREVK
PA10 PA10A
304 PA10U
PA10, PA10A
3
4
5
6
2
1
7
8
A1
D1
Q1
Q4
Q3
Q5
C1
Q2A
Q2B
Q6B
Q6A
TYPICAL APPLICATION
FIGURE 1. VOLTAGE-TO-CURRENT CONVERSION
DC and low distortion AC current waveforms are delivered
to a grounded load by using matched resistors (A and B
sections) and taking advantage of the high common mode
rejection of the PA10.
Foldover current limit is used to modify current limits based
on output voltage. When load resistance drops to 0, the current
is limited based on output voltage. When load resistance drops
to 0, the current limit is 0.79A resulting in an internal dissipa-
tion of 33.3 W. When output voltage increases to 36V, the
current limit is 1.69A. Refer to Application Note 9 on foldover
limiting for details.
S
R
R2B
.82
.82
42V
+42V
R2A
R1A
PA10
R1B
LOAD
0-24
CONTROL
FEATURES
GAIN BANDWIDTH PRODUCT 4MHz
TEMPERATURE RANGE 55 to +125C (PA10A)
APPLICATIONS
DESCRIPTION
The PA10 and PA10A are high voltage, high output current
and capacitive loads. For optimum linearity, the output stage
is biased for class A/B operation. The safe operating area
(SOA) can be observed for all operating conditions by selec-
tion of user programmable current limiting resistors. Both
amplifers are internally compensated for all gain settings. For
continuous operation under load, a heatsink of proper rating
is recommended.
use of compressible isolation washers voids the warranty.
CL+
+V
+IN
IN
V
FO
CL
OUT
S
S
TOP VIEW
R
CL+
R
CL
OUTPUT
1
2
3
4
5
6
7
8
8-PIN TO-3
PACKAGE STYLE CE
MAY 2009
APEX PA10UREVR
PA10 PA10A
PA10U 305
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SPECIFICATIONS
SUPPLY VOLTAGE, +V
S
to V
S
100V
S

1
200C
PA10 PA10A
2, 5
INPUT
C
= 25C 2 6 1 4 mV
C
= 25C 30 200 * * V/V
C
= 25C 20 * VW
C
= 25C 12 30 10 20 nA
BIAS CURRENT, vs. temperature Full temperature range 50 500 * * pA/C
C
= 25C .10 * pA/V
C
= 25C 12 30 5 10 nA
OFFSET CURRENT, vs. temperature Full temperature range 50 * pA/C
C
= 25C 200 * M
INPUT CAPACITANCE T
C
= 25C 3 * pF
3
S
5 V
S
3 * * V
3
Full temp. range, V
CM
= V
S
6V 74 100 * * dB
GAIN
C
= 25C, 1K load 110 * dB
OPEN LOOP GAIN at 10Hz Full temp. range, 15 load 96 108 * * dB
C
= 25C, 15 load 4 * MHz
POWER BANDWIDTH T
C
= 25C, 15 load 10 15 * * kHz
PHASE MARGIN Full temp. range, 15 load 35 *
OUTPUT
VOLTAGE SWING
3
T
C
= 25C, I
O
= 5A V
S
8 V
S
5 V
S
6 * V
VOLTAGE SWING
3
Full temp. range, I
O
= 2A V
S
6 * V
VOLTAGE SWING
3
Full temp. range, I
O
= 80mA V
S
5 * V
CURRENT, peak T
C
= 25C 5 * A
C
= 25C, 2V step 2 * s
SLEW RATE T
C
= 25C 2 3 * * V/s
V
= 1 .68 * nF
V
= 2.5 10 * nF
V
> 10 SOA * nF
POWER SUPPLY
C
= 25C 8 15 30 * * * mA
THERMAL
4
T
C
= 55 to +125C, F > 60Hz 1.9 2.1 * * C/W
RESISTANCE, DC, junction to case T
C
= 55 to +125C 2.4 2.6 * * C/W
C
= 55 to +125C 30 * C/W
CAUTION
to achieve high MTTF.
2. The power supply voltage for all tests is 40, unless otherwise noted as a test condition.
3. +V
S
and V
S
S
is measured from +V
S
to V
S
.
5. Full temperature range specifcations are guaranteed but not tested.
PA10 PA10A
306 PA10U
0 10K
FREQUENCY, F (Hz)
0
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
120
.1M 10 100 1K 1M
20
60
100
0
TIME, t (s)
PULSE RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
8
2 4 6 8 10 12
6
4
2
0
2
4
6
8
V
IN
= 5V, t
r
= 100ns
0 20 40 60 80 100 120
TEMPERATURE, T (C)
0
10
30
50
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
20
70
140
40
60
PA10 PA10A
T = T
C
T = T
A
50 25 50 100
CASE TEMPERATURE, T
C
(C)
0
3.0
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
2.5
0 25 75
1.0
1.5
.5
2.0
R
CL
= 0.6
R
CL
= 0.3
125
3.5
50 0 100
.4
1.0
2.2
2.5
BIAS CURRENT
1.6
.7
25 25 50 75
1.9
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
125
1.3
CASE TEMPERATURE, T
C
( C)
10K 20K 50K .1M
FREQUENCY, F (Hz)
4.6
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
P
)
POWER RESPONSE
30K 70K
6.8
10
15
22
32
46
68
100
|+V
S
| + |V
S
| = 30V
S S
|+V
S
| + |V
S
| = 80V
|+V
S
| + |V
S
| = 100V
10 100 10K .1M
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/

H
z
)
INPUT NOISE
1K
10
20
30
40
50
70
100
100 1K 3K .1M
FREQUENCY, F (Hz)
.003
.3
3
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N

(
%
)
.01
.1
1
300 10K 30K
.03
A
V
= 10
V
S
= 38V
R
L
= 8
P
O

=

5
0
m
W
P O

=

2
W
P
O

=

6
0
W
40 100
S
(V)
.4
.6
1.6
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
.8
1.4
50 60 70 80 90
1.2
1.0
T
C
= -25C
T
C
= 25C
T
C
= 85C
T
C
= 125C
0 2 3
OUTPUT CURRENT, I
O
(A)
2
6
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

(
V
)
3
5
1 5
1
4
TC
=
2
5
C
TC
=
2
5
to
8
5
C
TC
=
2
5
C
TC
=
2
5
to
8
5
C
4
VO
+
VO
1 100 10M
FREQUENCY, F (Hz)
20
0
60
120
O
P
E
N

L
O
O
P

G
A
I
N
,

A
O
L

(
d
B
)
20
40
80
100
10 1K 10K .1M 1M 1 100 .1M 10M
140
100
40
0
PHASE RESPONSE
60
20
1K 10 10K 1M
FREQUENCY, F (Hz)
P
H
A
S
E
,

)
120
80
180
160
PA10 PA10A
PA10U 307
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
limitations:
and the wire bonds.
complex for reactive and EMF generating loads.
1. For DC outputs, especially those resulting from fault condi-
tions, check worst case stress levels against the new SOA
graph.
For sine wave outputs, use Power Design
1
to plot a load
no more than 10%.
1
Note 1. Power Design is a self-extracting Excel spread-
sheet available free from www.Cirrus.com
For other waveform outputs, manual load line plotting
is recommended. Applications Note 22, SOA AND LOAD
load and short circuits to the supply rail or shorts to com-
mon if the current limits are set as follows at T
C
= 85C:
T
C =
1
2
5
C
T
H
E
R
M
A
L
s
t
e
a
d
y

s
t
a
t
e

S
E
C
O
N
D

B
R
E
A
K
D
O
W
N
t

=

1
m
s
t

=

5
m
s
t

=

0
.
5
m
s
.2
.3
.4
.6
.8
1.0
1.5
2.0
3.0
4.0
5.0
10 15 20 25 30 35 40 50 60 70 80 100
T
C =
8
5
C
S
V
O
(V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S

(
A
)
SHORT TO V
S
SHORT TO
V
S
50V .21A .61A
40V .3A .87A
35V .36A 1.0A
30V .46A 1.4A
25V .61A 1.7A
20V .87A 2.2A
15V 1.4A 2.9A
CURRENT LIMITING
Refer to Application Note 9, "Current Limiting", for details of
both fxed and foldover current limit operation. Visit the Apex
Precision Power web site at www.Cirrus.com for a copy of the
Power Design spreadsheet (Excel) which plots current limits vs.
steady state SOA. Beware that current limit should be thought
of as a +/20% function initially and varies about 2:1 over the
range of 55C to 125C.
For fxed current limit, leave pin 7 open and use equations
1 and 2.
R
CL
= 0.65/L
CL
(1)
I
CL
= 0.65/R
CL
(2)
Where:
I
CL
is the current limit in amperes.
R
CL
is the current limit resistor in ohms.
For certain applications, foldover current limit adds a slope
to the current limit which allows more power to be delivered
to the load without violating the SOA. For maximum foldover
slope, ground pin 7 and use equations 3 and 4.
0.65 + (Vo * 0.014)
I
CL
= (3)
R
CL
0.65 + (Vo * 0.014)
R
CL
= (4)
I
CL
Where:
Vo is the output voltage in volts.
Most designers start with either equation 1 to set R
CL
for the
desired current at 0v out, or with equation 4 to set R
CL
at the
maximum output voltage. Equation 3 should then be used to
plot the resulting foldover limits on the SOA graph. If equa-
tion 3 results in a negative current limit, foldover slope must
be reduced. This can happen when the output voltage is the
opposite polarity of the supply conducting the current.
In applications where a reduced foldover slope is desired,
this can be achieved by adding a resistor (R
FO
) between pin
7 and ground. Use equations 4 and 5 with this new resistor
in the circuit.

0.65 + Vo
*
0.14
10.14 + R
FO
I
CL
= (5)
R
CL

0.65 + Vo
*
0.14
10.14 + R
FO
R
CL
= (6)
I
CL
Where:
R
FO
is in K ohms.
PA10M/883
308 PA10MU
PA10M/883
BURN IN CIRCUIT
* These components are used to stabilize device due to
poor high frequency characteristics of burn in board.
dissipation of approximately 2.1W at case temperature
= 125C.
Q
25C 40V V
IN
= 0, A
V
= 100, R
CL
= .1 30 mA
OS
25C 40V V
IN
= 0, A
V
= 100 6 mV
OS
25C 10V V
IN
= 0, A
V
= 100 12 mV
OS
25C 45V V
IN
= 0, A
V
= 100 7 mV
B
25C 40V V
IN
= 0 30 nA
B
25C 40V V
IN
= 0 30 nA
OS
25C 40V V
IN
= 0 30 nA
Q
55C 40V V
IN
= 0, A
V
= 100, R
CL
= .1 75 mA
OS
55C 40V V
IN
= 0, A
V
= 100 11.2 mV
OS
55C 10V V
IN
= 0, A
V
= 100 17.2 mV
OS
55C 45V V
IN
= 0, A
V
= 100 12.2 mV
B
55C 40V V
IN
= 0 115 nA
B
55C 40V V
IN
= 0 115 nA
OS
55C 40V V
IN
= 0 115 nA
Q
125C 40V V
IN
= 0, A
V
= 100, R
CL
= .1 30 mA
OS
125C 40V V
IN
= 0, A
V
= 100 12.5 mV
OS
125C 10V V
IN
= 0, A
V
= 100 18.5 mV
OS
125C 45V V
IN
= 0, A
V
= 100 13.5 mV
B
125C 40V V
IN
= 0 70 nA
B
125C 40V V
IN
= 0 70 nA
OS
125C 40V V
IN
= 0 70 nA
4 Output voltage, I
O
= 5A V
O
25C 18V R
L
= 2.07 10 V
4 Output voltage, I
O
= 80mA V
O
25C 45V R
L
= 500 40 V
4 Output voltage, I
O
= 2A V
O
25C 30V R
L
= 12 24 V
4 Current limits I
CL
25C 17V R
L
= 12, R
CL
= 1 .6 .89 A
4 Stability/noise E
N
25C 40V R
L
= 100, A
V
= 1, C
L
= .33nF 1 mV
L
= 500 2 10 V/s
4 Open loop gain A
OL
25C 40V R
L
= 500, F = 10Hz 96 dB
4 Common mode rejection CMR 25C 15V R
L
= 500, F = DC, V
CM
= 9V 74 dB
6 Output voltage, I
O
= 5A V
O
55C 18V R
L
= 2.07 10 V
6 Output voltage, I
O
= 80mA V
O
55C 45V R
L
= 500 40 V
6 Output voltage, I
O
= 2A V
O
55C 30V R
L
= 12 24 V
6 Stability/noise E
N
55C 40V R
L
= 100, A
V
= 1, C
L
= .33nF 1 mV
L
= 500 2 10 V/s
6 Open loop gain A
OL
55C 40V R
L
= 500, F = 10Hz 96 db
L
= 500, F = DC, V
CM
= 9V 74 dB
5 Output voltage, I
O
= 3A V
O
125C 14.3V R
L
= 2.07 6.3 V
5 Output voltage, I
O
= 80mA V
O
125C 45V R
L
= 500 40 V
5 Output voltage, I
O
= 2A V
O
125C 30V R
L
= 12 24 V
5 Stability/noise E
N
125C 40V R
L
= 100, A
V
= 1, C
L
= .33nF 1 mV
L
= 500 2 10 V/s
5 Open loop gain A
OL
125C 40V R
L
= 500, F = 10Hz 96 dB
L
= 500, F = DC, V
CM
= 9V 74 dB
100K
1
1
100K
+15V
15V
5
6
2
1
8
3
20
* *
*
*
U.U.T
4
SEP 2009
APEX PA10MUREVM
PA12 PA12A
PA12U 309
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA12, PA12A
FEATURES
LOW THERMAL RESISTANCE 1.4C/W
CURRENT FOLDOVER PROTECTION NEW
HIGH TEMPERATURE VERSION PA12H
HIGH OUTPUT CURRENT Up to 15A Peak
APPLICATIONS
DESCRIPTION
The PA12 is a state of the art high voltage, very high output
current operational amplifer designed to drive resistive, induc-
tive and capacitive loads. For optimum linearity, especially at low
levels, the output stage is biased for class A/B operation using
a thermistor compensated base-emitter voltage multiplier circuit.
The safe operating area (SOA) can be observed for all operating
conditions by selection of user programmable current limiting
resistors. For continuous operation under load, a heatsink of
proper rating is recommended. The PA12 is not recommended
for gains below 3 (inverting) or +4 (non-inverting).
3
4
5
6
2
1
8
A1
D1
Q1
Q4
Q3
Q5
C1
Q2A
Q2B
Q6B
Q6A
7
POWER RATING
Not all vendors use the same method to rate the power
handling capability of a Power Op Amp. Apex Precision Power
rates the internal dissipation, which is consistent with rating
methods used by transistor manufacturers and gives conser-
vative results. Rating delivered power is highly application
dependent and therefore can be misleading. For example, the
125W internal dissipation rating of the PA12 could be expressed
as an output rating of 250W for audio (sine wave) or as 440W
if using a single ended DC load. Please note that all vendors
rate maximum power using an infnite heatsink.
THERMAL STABILITY
Apex Precision Power has eliminated the tendency of class
A/B output stages toward thermal runaway and thus has vastly
increased amplifer reliability. This feature, not found in most
other Power Op Amps, was pioneered by Apex Precision
Power in 1981 using thermistors which assure a negative
temperature coefficient in the quiescent current. The reliability
benefts of this added circuitry far outweigh the slight increase
in component count.
CL+
+V
S

+IN
IN
V
S

F.O.
CL
OUT
TOP VIEW
R
CL+
R
CL-
OUTPUT
1
2
3
4
5
6
7
8
8-PIN TO-3
PACKAGE STYLE CE
MAY 2009
APEX PA12UREVS
PA12 PA12A
310 PA12U
SPECIFICATIONS
PA12 PA12A
2, 5
INPUT
C
= 25C 2 6 1 4 mV
C
= 25C 30 200 * * V/V
C
= 25C 20 * V/W
C
= 25C 12 30 10 20 nA
BIAS CURRENT, vs. temperature Full temperature range 50 500 * * pA/C
C
= 25C 10 * pA/V
C
= 25C 12 30 5 20 nA
OFFSET CURRENT, vs. temperature Full temperature range 50 * pA/C
C
= 25C 200 * M
INPUT CAPACITANCE T
C
= 25C 3 * pF
3
S
5 V
S
3 * * V
CM
= V
S
6V 74 100 * * dB

GAIN
C
= 25C, 1K load 110 * dB
OPEN LOOP GAIN at 10Hz Full temp. range, 8 load 96 108 * * dB
C
= 25C, 8 load 4 * MHz
POWER BANDWIDTH T
C
= 25C, 8 load 13 20 * * kHz
PHASE MARGIN, A
V
= +4 Full temp. range, 8 load 20 *
OUTPUT
VOLTAGE SWING
3
T
C
= 25C, PA12 = 10A, PA12A = 15A V
S
6 * V
VOLTAGE SWING
3
T
C
= 25C, I
O
= 5A V
S
5 * V
VOLTAGE SWING
3
Full temp. range, I
O
= 80mA V
S
5 * V
CURRENT, peak T
C
= 25C 10 15 A
C
= 25C, 2V step 2 * s
SLEW RATE T
C
= 25C 2.5 4 * * V/s
V
= 4 1.5 * nF
V
> 10 SOA *
POWER SUPPLY
C
= 25C 25 50 * * mA
THERMAL
4
T
C
= 55 to +125C, F > 60Hz .8 .9 * * C/W
C
= 55 to +125C 1.25 1.4 * * C/W
C
= 55 to +125C 30 * C/W
TEMPERATURE RANGE, case Meets full range specifcation 25 +85 55 +125 C
achieve high MTTF.
3. +V
S
and V
S
S
is measured from +V
S
to V
S
.
5. Full temperature range specifcations are guaranteed but not 100% tested.
PA12/PA12A
SUPPLY VOLTAGE, +Vs to Vs 100V
S
TEMPERATURE, pin solder -10s 300C
1
200C
CAUTION
PA12 PA12A
PA12U 311
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
0 20 40 60 80 100 120
CASE TEMPERATURE, TC (C)
0
20
60
100
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
50 0 100
.7
1.9
2.2
BIAS CURRENT
1.3
.4
10 100 10K .1M
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/
H
z
)
1 100 10M
FREQUENCY, F (Hz)
20
0
60
120
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
20
40
80
100
1 100 .1M 10M
210
150
60
0
PHASE RESPONSE
90
30
10K 20K 50K .1M
FREQUENCY, F (Hz)
4.6
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
100 1K 3K .1M
FREQUENCY, F (Hz)
.003
.3
3
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

(
%
)
.01
.1
1
40 100
S
(V)
.4
.6
1.6
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D
,

I
Q

(
X
)
.8
1.4
0
OUTPUT CURRENT, I
O
(A)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y

(
V
)
1 10K
FREQUENCY, F (Hz)
0
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
120
.1M 10 100 0
TIME, t (s)
PULSE RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
50 25 50 100
CASE TEMPERATURE, T
C
(C)
0
15.0
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
12.5
300 10K 30K
1
INPUT NOISE
1K
10
20
30
1K
25 25 50 75
1.6
40
140
POWER RESPONSE
30K
50 60 70 80 90
1.2
0 25 75
5.0
7.5
-8
10 1K 10K .1M 1M
140
80
120
10 10K 1M
FREQUENCY, F (Hz)
P
H
A
S
E
,

)
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
2.5
10.0
1K 1M
20
60
100
2 4 6 8 10 12
-6
-4
-2
0
2
4
6
8
70K
6.8
10
15
22
32
46
68
100
.03
1.0
125
1.0
125
17.5
CASE TEMPERATURE, T
C
(C)
180
120
40
50
70
100
2.5
3 6 9 12 15
2
3
4
5
6
PA12 PA12A
R
CL
= .18 ,R
FO
= 0
R
CL
= .06 ,R
FO
=
V
O =
0
V
O
= 24V
V
O
= 0
V
O
= 24V
| +V
S
| + | V
S
| = 100V
| +V
S
| | V
S
| = 80V
| +V
S
| + | V
S
| = 30V
V
IN
= 5V, t
r
= 100ns
P
O

=

1
0
0
m
W
T
C
= 25C
P O

=

4
W
A
V
=10
V
S
= 37V
R
L
= 4
P
O

=

1
2
0
W
T
C
= 25C
T
C
= 85C
T
C
= 125C
V
O
+V
O
PA12 PA12A
312 PA12U
load and short circuits to the supply rail or common if the
current limits are set as follows at T
C
= 25C:
SHORT TO V
S
SHORT TO
V
S
50V .30A 2.4A
40V .58A 2.9A
35V .87A 3.7A
30V 1.5A 4.1A
25V 2.4A 4.9A
20V 2.9A 6.3A
15V 4.2A 8.0A
CURRENT LIMITING
Refer to Application Note 9, "Current Limiting", for details of
both fxed and foldover current limit operation. Visit the Apex
Precision Power web site at www.Cirrus.com for a copy of the
Power Design spreadsheet (Excel) which plots current limits vs.
steady state SOA. Beware that current limit should be thought
of as a +/20% function initially and varies about 2:1 over the
range of 55C to 125C.
For fxed current limit, leave pin 7 open and use equations
1 and 2.
R
CL
= 0.65/L
CL
(1)
I
CL
= 0.65/R
CL
(2)
Where:
I
CL
R
CL
For certain applications, foldover current limit adds a slope
to the current limit which allows more power to be delivered
to the load without violating the SOA. For maximum foldover
slope, ground pin 7 and use equations 3 and 4.
0.65 + (Vo * 0.014)
I
CL
= (3)
R
CL
0.65 + (Vo * 0.014)
R
CL
= (4)
I
CL
Where:
Vo is the output voltage in volts.
CL
for the
desired current at 0v out, or with equation 4 to set R
CL
at the
maximum output voltage. Equation 3 should then be used to
plot the resulting foldover limits on the SOA graph. If equa-
tion 3 results in a negative current limit, foldover slope must
be reduced. This can happen when the output voltage is the
opposite polarity of the supply conducting the current.
In applications where a reduced foldover slope is desired,
this can be achieved by adding a resistor (R
FO
) between pin
7 and ground. Use equations 4 and 5 with this new resistor
in the circuit.

Vo
*
0.14
0.65 +
10.14 + R
FO
I
CL
= (5)
R
CL

Vo
*
0.14
0.65 +
10.14 + R
FO
R
CL
= (6)
I
CL
Where:
R
FO
is in K ohms.
GENERAL
limitations:
and the wire bonds.
The SOA curves combine the effect of all limits for this Power
Op Amp. For a given application, the direction and magnitude
of the output current should be calculated or measured and
checked against the SOA curves. This is simple for resistive
loads but more complex for reactive and EMF generating
loads. However, the following guidelines may save extensive
analytical efforts.
1. Capacitive and dynamic* inductive loads up to the following
maximum are safe with the current limits set as specifed.
V
S
I
LIM
= 5A I
LIM
= 10A I
LIM
= 5A I
LIM
= 10A
50V 200F 125F 5mH 2.0mH
40V 500F 350F 15mH 3.0mH
35V 2.0mF 850F 50mH 5.0mH
30V 7.0mF 2.5mF 150mH 10mH
25V 25mF 10mF 500mH 20mH
20V 60mF 20mF 1,000mH 30mH
15V 150mF 60mF 2,500mH 50mH
*If the inductive load is driven near steady state conditions,
allowing the output voltage to drop more than 8V below the
supply rail with I
LIM
= 15A or 25V below the supply rail with I
LIM

= 5A while the amplifer is current limiting, the inductor must
be capacitively coupled or the current limit must be lowered
to meet SOA criteria.
T
C =
2
5
C
T
C =
1
2
5
C
T
C =
8
5
C
t

=

0
.
5
m
s
t

=

5
m
s
t

=

1
m
s
T
H
E
R
M
A
L
s
t
e
a
d
y

s
t
a
t
e
SECOND BREAKDOWN
SOA
20 50 70 100 40 30 10
SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE, V
S
- V
O
(V)
15
.6
.4
10
6.0
4.0
2.0
3.0
.3
1.0
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

-
V
S

(
A
)
PA12M/883
PA12MU 313
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA12M/883
Q
25C 40V V
IN
= 0, A
V
= 100, R
CL
= .1 50 mA
OS
25C 40V V
IN
= 0, A
V
= 100 6 mV
OS
25C 10V V
IN
= 0, A
V
= 100 12 mV
OS
25C 45V V
IN
= 0, A
V
= 100 7 mV
B
25C 40V V
IN
= 0 30 nA
1 Inout bias current,IN I
B
25C 40V V
IN
= 0 30 nA
OS
25C 40V V
IN
= 0 30 nA
Q
55C 40V V
IN
= 0, A
V
= 100, R
CL
= .1 100 mA
OS
55C 40V V
IN
= 0, A
V
= 100 11.2 mV
OS
55C 10V V
IN
= 0, A
V
= 100 17.2 mV
OS
55C 45V V
IN
= 0, A
V
= 100 12.2 mV
B
55C 40V V
IN
= 0 115 nA
3 Input bias current,IN I
B
55C 40V V
IN
= 0 115 nA
OS
55C 40V V
IN
= 0 115 nA
Q
125C 40V V
IN
= 0, A
V
= 100, R
CL
= .1 50 mA
OS
125C 40V V
IN
= 0, A
V
= 100 12.5 mV
OS
125C 10V V
IN
= 0, A
V
= 100 18.5 mV
OS
125C 45V V
IN
= 0, A
V
= 100 13.5 mV
B
125C 40V V
IN
= 0 70 nA
B
125C 40V V
IN
= 0 70 nA
OS
125C 40V V
IN
= 0 70 nA
4 Output voltage, I
O
= 10A V
O
25C 16V R
L
= 1 10 V
4 Output voltage, I
O
= 80mA V
O
25C 45V R
L
= 500 40 V
4 Output voltage, I
O
= 5A V
O
25C 35V R
L
= 6 30 V
4 Current limits I
CL
25C 14V R
L
= 6, R
CL
= 1 .6 .89 A
4 Stability/noise E
N
25C 40V R
L
= 500, C
L
= 1.5nF, / 1 1 mV
L
= 500 2.5 10 V/s
4 Open loop gain A
OL
25C 40V R
L
= 500, F = 10Hz 96 dB
L
= 500, F = DC, V
CM
= 9V 74 dB
6 Output voltage, I
O
= 8A V
O
55C 14V R
L
= 1 8 V
6 Output voltage, I
O
= 80mA V
O
55C 45V R
L
= 500 40 V
6 Stability/noise E
N
55C 40V R
L
= 500, C
L
= 1.5nF, / 1 1 mV
L
= 500 2.5 10 V/s
6 Open loop gain A
OL
55C 40V R
L
= 500, F = 10Hz 96 dB
L
= 500, F = DC, V
CM
= 9V 74 dB
5 Output voltage, I
O
= 8A V
O
125C 14V R
L
= 1 8 V
5 Output voltage, I
O
= 80mA V
O
125C 45V R
L
= 500 40 V
5 Stability/noise E
N
125C 40V R
L
= 500, C
L
= 1.5nF, / 1 1 mV
L
= 500 2.5 10 V/s
5 Open loop gain A
OL
125C 40V R
L
= 500, F = 10Hz 96 dB
L
= 500, F = DC, V
CM
= 9V 74 dB
BURN IN CIRCUIT
/ 1 Minimum gain recommendation is either G = +4 (non-
inverting) or G = 3 (inverting).

/ 2 Input signals are calculated to result in internal power
dissipation of approximately 2.1W at case temperature =
125C.

/ 3 These components are used to stabilize device due to
poor hgh frequency characteristics of burn in board.
100K
1
1
100K
+15V
15V
5
6
2
1
8
3
20
/3
/3
/2
U.U.T
4
SEP 2009
APEX PA12MUREVL
PA12H
314 PA12HU
PA12H
FEATURES
LOW COST 200C VERSION OF PA12
OUTPUT CURRENT at 200C 1A
FULL SPECIFICATIONS 25C to +125C
WIDE SUPPLY RANGE 10 to 45V
CURRENT FOLDOVER PROTECTION
APPLICATIONS
TRANSMISSION LINE DRIVER
DESCRIPTION
The PA12H is a low cost, high temperature Power Op Amp
made especially for short term use in extreme environmental
situations such as down hole instrumentation. The amplifer
can power mechanical or electronic transducers and can drive
the long transmission lines associated with these applications.
The PA12H, based on the standard PA12s very high
power level, leaves a six watt capability after being derated
for operation at a case temperature of 200C. To meet the
high temperature requirements for up to 200 hours, polyimid
has replaced the standard epoxy for attaching the small signal
devices.
These hybrid integrated circuits utilize thick flm conductors,
ceramic capacitors and silicon semiconductors to maximize
reliability, minimize size and give top performance. Ultrasoni-
cally bonded aluminum wires provide reliable interconnections
at all operating temperatures. The 8-pin TO-3 package (see
Package Outlines) is hermetically sealed and isolated. The use
of compressible thermal washers and/or improper mounting
torque will void the product warranty. Please see General
Operating Considerations.
CL+
+V
S
+IN
IN
V
S
F.O.
CL
OUT
TOP VIEW
R
CL+
R
CL-
OUTPUT
1
2
3
4
5
6
7
8
CALCULATED LIFE EXPECTANCY
1000
100
10
E
X
P
E
C
T
E
D

L
I
F
E
,

H
O
U
R
S
188 192 196 200
8-PIN TO-3
PACKAGE STYLE CE
SPECIFICATIONS
Specifcations of the standard PA12 apply to the PA12H with
the exception of the temperature range extensions
1. The operating and storage temperature ABSOLUTE MAXI-
MUM RATINGS extend to +200C.
2. Static and dynamic tests are performed at +125C as shown
in SG 2 and SG 5 of the military PA12M data sheet.
3. Additional tests at T
C
= 200C:
A. Quiescent current = 100mA max at V
S
= 45.
B. Voltage swing = V
S
4 (I
O
= 1A, V
S
= 15)
GENERAL CONSIDERATIONS
The primary aim of the PA12H is to provide a reasonable
level of power output at a minimum cost. To achieve this end,
full dynamic tests are performed up to 125C, with only minimal
100% testing at 200C. This approach saves nearly an order
of magnitude over the cost of a fully tested long life product,
but does require recognition of two limitations.
First, input parameters such as voltage offset and bias cur-
rent are not tested above 125C. This could lead to accuracy
problems if the PA12H is used as a precision computational
element. Solutions to this limitation include contacting the
factory regarding additional testing at higher temperatures or
using high temperature small signal amplifers for computa-
tional tasks.
The second limitation of life span requires the PA12H to
be used in short term applications. This requirement is man-
dated by the low cost design concept. At 200C component
degradation is nearly as severe during storage as during actual
operation. This must be taken into account when scheduling
actual implementation of the fnished package.
Please consult the PA12 data sheet for basic information
on this amplifer; the PA12M data sheet for details on +125C
tests, and Power Operational Amplifer handbook section
General Operating Considerations, for recommendations
on supplies, stability, heatsinks and bypassing.
PA12H P r o d u c t I n n o v a t i o n F r o m
MAY 2009
APEX PA12HUREVJ
PA13 PA13A
PA13U 315
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA13, PA13A
FEATURES
LOW THERMAL RESISTANCE 1.1C/W
CURRENT FOLDOVER PROTECTION
HIGH OUTPUT CURRENT Up to 15A Peak
APPLICATIONS
MAGNETIC DEFLECTION CIRCUITS
UP TO 10A
UP TO 90V
12
2
1
5
9
3
7
A1
D1
Q1
Q4
Q3
Q5
C1
Q2A
Q2B
Q6B
Q6A
4
11
10
6
8
DESCRIPTION
The PA13 is a state of the art high voltage, very high
output current operational amplifer designed to drive
resistive, inductive and capacitive loads. For optimum
linearity, especially at low levels, the output stage is
biased for class A/B operation using a thermistor com-
pensated base-emitter voltage multiplier circuit. The
safe operating area (SOA) can be observed for all op-
erating conditions by selection of user programmable
current limiting resistors. For continuous operation un-
der load, a heatsink of proper rating is recommended.
The PA13 is not recommended for gains below 3 (in-
verting) or +4 (non-inverting).
resistors, ceramic capacitors and semiconductor chips
to maximize reliability, minimize size and give top per-
formance. Ultrasonically bonded aluminum wires pro-
vide reliable interconnections at all operating temper-
atures. The 12-pin power SIP package is electrically
isolated.
AUG 2008
APEX PA13REVN
1 2 3 4 5 6 7 8 9 10 11 12
IN +IN
OUTPUT
F.O.
V
+V
C
L
+C
L
R
CL
+R
CL
S
S
12-pin SIP
PACKAGE
STYLE DP
Formed leads avaliable
PA13 PA13A
316 PA13U
CAUTION
SUPPLY VOLTAGE, +V
S
to -V
S
100 V
OUTPUT CURRENT, within SOA 15 A
POWER DISSIPATION, internal 135 W
INPUT VOLTAGE, differential -37 37 V
INPUT VOLTAGE, common mode -V
S
V
S
V
ABSOLUTE MAXIMUM RATINGS PA13/PA13A
Parameter
Test Condi-
tions
2,5
PA13 PA13A
Units Min Typ Max Min Typ Max
INPUT
OFFSET VOLTAGE vs. temp
Full temp range
10 65 * 40 V/C
OFFSET VOLTAGE vs. supply 30 200 * * V/V
OFFSET VOLTAGE vs. power 20 * V/W
BIAS CURRENT, initial 12 30 10 20 nA
BIAS CURRENT, vs. temp Full temp range 50 500 * * pA/C
BIAS CURRENT, vs. supply 10 * pA/V
OFFSET CURRENT, initial 12 30 5 10 nA
OFFSET CURRENT, vs. temp Full temp range 50 * pA/C
INPUT IMPEDANCE, DC 200 * M
COMMON MODE VOLTAGE
RANGE (Note 4)
Full temp range V
S
- 5 V
S
- 3 * * V
COMMON MODE REJECTION,
DC
Full temp range,
V
CM
= V
S
6V
74 100 * * dB
GAIN
OPEN LOOP GAIN @ 10Hz 1K load 110 * dB
OPEN LOOP GAIN @ 10Hz Full temp range,
8 load
96 108 * * dB
GAIN BANDWIDTH PRODUCT
@ 1MHz
8 load 4 * MHz
POWER BANDWIDTH 8 load 13 20 * * kHz
PHASE MARGIN, A
V
= +4 Full temp range,
8 load
20 *
SPECIFICATIONS
PA13 PA13A
PA13U 317
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Parameter
Test Condi-
tions
2,5
PA13 PA13A
OUTPUT
VOLTAGE SWING (Note 4) PA13 = 10A,
PA13A = 15A
V
S
- 6 * V
VOLTAGE SWING (Note 4) I
O
= 5A V
S
- 5 * V
VOLTAGE SWING (Note 4) Full temp range,
I
O
= 80mA
V
S
- 5 * V
CURRENT, peak 10 15 A
SETTLING TIME to 0.1% 2V step 2 * S
SLEW RATE 2.5 4 * * V/S
CAPACITIVE LOAD Full temp range,
A
V
= 4
1.5 * nF
A
V
> 10
SOA *
POWER SUPPLY
VOLTAGE Full temp range 10 40 45 * * * V
THERMAL
RESISTANCE, AC,
junction to case (Note 5)
T
C
= 55 to
+125C, F >
60Hz
0.6 0.7 * * C/W
RESISTANCE, DC,
junction to case
T
C
= 55 to
+125C
0.9 1.1 * * C/W
RESISTANCE, DC,
junction to air
T
C
= 55 to
+125C
30 * C/W
TEMPERATURE RANGE, case Meets full range
specifcation
-25 +85 * * C
tions. Typical performance characteristics and specifcations are derived from measurements taken at
typical supply voltages and T
C
= 25C).
* The specifcation of PA13A is identical to the specifcation for PA13 in the applicable column to the left
4. +V
S
and V
S
S
is measured from +V
S

to V
S
.
60Hz.
PA13 PA13A
318 PA13U
POWER RATING
Not all vendors use the same method to rate the power han-
dling capability of a Power Op Amp. Apex Precision Power
rates the internal dissipation, which is consistent with rating
methods used by transistor manufacturers and gives conser-
vative results. Rating delivered power is highly application
dependent and therefore can be misleading. For example,
the 135W internal dissipation rating of the PA13 could be ex-
pressed as an output rating of 260W for audio (sine wave) or
as 440W if using a single ended DC load. Please note that all
vendors rate maximum power using an infnite heatsink.
THERMAL STABILITY
Apex Precision Power has eliminated the tendency of class
A/B output stages toward thermal runaway and thus has
vastly increased amplifer reliability. This feature, not found in
most other Power Op Amps, was pioneered by Apex Preci-
sion Power in 1981 using thermistors which assure a negative
temperature coeffcient in the quiescent current. The reliability
benefts of this added circuitry far outweigh the slight increase
in component count.
V =
L
*
1
t
YOKE DRIVER:
47F .1F
.1F
47F
22V
+73V
R

1K
R
.2

C

50pF
2.5V
P-P
R
2K
11,12
2
1
5,6
3
R
.5
7.8mH
4
5Ap-p
D
F
CL+
F
S
HIGH CURRENT ASYMMETRICAL SUPPLY
7,8
9,10
R
.2

CL
PA13
TYPICAL APPLICATION
50 0 100
.7
1.9
2.2
BIAS CURRENT
1.3
.4
10 100 10K .1M
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/
H
z
)
1 100 10M
FREQUENCY, F (Hz)
20
0
60
120
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
20
40
80
100
1 100 .1M 10M
210
150
60
0
PHASE RESPONSE
90
30
10K 20K 50K .1M
FREQUENCY, F (Hz)
4.6
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
100 1K 3K .1M
FREQUENCY, F (Hz)
.003
.3
3
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

(
%
)
.01
.1
1
40 100
S
(V)
.4
.6
1.6
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D
,

I
Q

(
X
)
.8
1.4
0
OUTPUT CURRENT, I
O
(A)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y

(
V
)
1 10K
FREQUENCY, F (Hz)
0
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
120
.1M 10 100 0
TIME, t (s)
PULSE RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
50 25 50 100
CASE TEMPERATURE, T
C
(C)
0
15.0
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
12.5
300 10K 30K
1
INPUT NOISE
1K
10
20
30
1K
25 25 50 75
1.6
POWER RESPONSE
30K
50 60 70 80 90
1.2
0 25 75
5.0
7.5
-8
10 1K 10K .1M 1M 10 10K 1M
FREQUENCY, F (Hz)
P
H
A
S
E
,

)
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
2.5
10.0
1K 1M
20
60
100
2 4 6 8 10 12
-6
-4
-2
0
2
4
6
8
70K
6.8
10
15
22
32
46
68
100
.03
1.0
125
1.0
125
17.5
CASE TEMPERATURE, T
C
(C)
180
120
40
50
70
100
2.5
3 6 9 12 15
2
3
4
5
6
R
CL
= .18, R
FO
= 0
R
CL
= .06, R
FO
=
V
O =
0
V
O
= 24V
V
O
= 0
V
O
= 24V
| +V
S
| + | V
S
| = 100V
| +V
S
| | V
S
| = 80V
| +V
S
| + | V
S
| = 30V
V
IN
= 5V, t
r
= 100ns
P
O

=

1
0
0
m
W
T
C
= 25C
P O

=

4
W
A
V
=10
V
S
= 37V
R
L
= 4
P
O

=

1
2
0
W
T
C
= 25C
T
C
= 85C
T
C
= 125C
V
O
+V
O
0 20 40 60 80 100 120
CASE TEMPERATURE, T
C
(C)
0
20
60
100
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
40
140
140
80
120
PA13
PA13 PA13A
PA13U 319
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
50 0 100
.7
1.9
2.2
BIAS CURRENT
1.3
.4
10 100 10K .1M
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/
H
z
)
1 100 10M
FREQUENCY, F (Hz)
20
0
60
120
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
20
40
80
100
1 100 .1M 10M
210
150
60
0
PHASE RESPONSE
90
30
10K 20K 50K .1M
FREQUENCY, F (Hz)
4.6
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
100 1K 3K .1M
FREQUENCY, F (Hz)
.003
.3
3
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

(
%
)
.01
.1
1
40 100
S
(V)
.4
.6
1.6
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D
,

I
Q

(
X
)
.8
1.4
0
OUTPUT CURRENT, I
O
(A)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y

(
V
)
1 10K
FREQUENCY, F (Hz)
0
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
120
.1M 10 100 0
TIME, t (s)
PULSE RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
50 25 50 100
CASE TEMPERATURE, T
C
(C)
0
15.0
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
12.5
300 10K 30K
1
INPUT NOISE
1K
10
20
30
1K
25 25 50 75
1.6
POWER RESPONSE
30K
50 60 70 80 90
1.2
0 25 75
5.0
7.5
-8
10 1K 10K .1M 1M 10 10K 1M
FREQUENCY, F (Hz)
P
H
A
S
E
,

)
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
2.5
10.0
1K 1M
20
60
100
2 4 6 8 10 12
-6
-4
-2
0
2
4
6
8
70K
6.8
10
15
22
32
46
68
100
.03
1.0
125
1.0
125
17.5
CASE TEMPERATURE, T
C
(C)
180
120
40
50
70
100
2.5
3 6 9 12 15
2
3
4
5
6
R
CL
= .18, R
FO
= 0
R
CL
= .06, R
FO
=
V
O =
0
V
O
= 24V
V
O
= 0
V
O
= 24V
| +V
S
| + | V
S
| = 100V
| +V
S
| | V
S
| = 80V
| +V
S
| + | V
S
| = 30V
V
IN
= 5V, t
r
= 100ns
P
O

=

1
0
0
m
W
T
C
= 25C
P O

=

4
W
A
V
=10
V
S
= 37V
R
L
= 4
P
O

=

1
2
0
W
T
C
= 25C
T
C
= 85C
T
C
= 125C
V
O
+V
O
0 20 40 60 80 100 120
CASE TEMPERATURE, T
C
(C)
0
20
60
100
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
40
140
140
80
120
PA13
GENERAL
Please read Application Note 1 "General Operating Considerations" which covers stability, supplies, heat sinking,
mounting, current limit, SOA interpretation, and specifcation interpretation. Visit www.Cirrus.com for design tools
that help automate tasks such as calculations for stability, internal power dissipation, current limit; heat sink selec-
tion; Apex Precision Powers complete Application Notes library; Technical Seminar Workbook; and Evaluation Kits.
limitations:
and the wire bonds.
simultaneous collector current and collector-emitter volt-
age exceeds specifed limits.
loads but more complex for reactive and EMF generating
loads. However, the following guidelines may save extensive
analytical efforts.
T
C
=
2
5
C
T
C
=
8
5
C
t

=

0
.
5
m
s
t

=

5
m
s
t

=

1
m
s
T
H
E
R
M
A
L
s
t
e
a
d
y

s
t
a
t
e
SOA
20 50 70 90 40 30 10
S
- V
O
(V)
15
.6
.4
10
6.0
4.0
2.0
3.0
1.0
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

-
V
S

(
A
)
S
E
C
O
N
D

B
R
E
A
K
D
O
W
N
PA13 PA13A
320 PA13U
1. Capacitive and dynamic* inductive loads up to the following maximum are safe with the current limits set as
specifed.
V
S
I
LIM
= 5A I
LIM
= 10A I
LIM
= 5A I
LIM
= 10A
50V 200F 125F 5mH 2.0mH
40V 500F 350F 15mH 3.0mH
35V 2.0mF 850F 50mH 5.0mH
30V 7.0mF 2.5mF 150mH 10mH
25V 25mF 10mF 500mH 20mH
20V 60mF 20mF 1,000mH 30mH
15V 150mF 60mF 2,500mH 50mH
*If the inductive load is driven near steady state conditions, allowing the output voltage to drop more than 12.5V be-
low the supply rail with ILIM = 10A or 27V below the supply rail with ILIM = 5A while the amplifer is current limiting,
the inductor must be capacitively coupled or the current limit must be lowered to meet SOA criteria.
2. The amplifer can handle any EMF generating or reactive load and short circuits to the supply rail or common if
the current limits are set as follows at TC = 25C:
SHORT TO V
S
SHORT TO
V
S
45V .43A 3.0A
40V .65A 3.4A
35V 1.0A 3.9A
30V 1.7A 4.5A
25V 2.7A 5.4A
20V 3.4A 6.7A
15V 4.5A 9.0A
These simplifed limits may be exceeded with further analysis using the operating conditions for a specifc applica-
tion.
CURRENT LIMITING
Refer to Application Note 9, "Current Limiting", for details of both fxed and foldover current limit operation. Visit the
Apex Precision Power web site at www.cirrus.com for a copy of Power_design.exe which plots current limits vs.
steady state SOA. Beware that current limit should be thought of as a 20% function initially and varies about 2:1
over the range of 55C to 125C.
For fxed current limit, leave pin 4 open and use equations 1 and 2.

R
CL
=
0.65
I
CL
(1)

I
CL
=
0.65
R
CL
(2)
Where:
I
CL
R
CL
PA13 PA13A
PA13U 321
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
For certain applications, foldover current limit adds a slope to the current limit which allows more power to be deliv-
ered to the load without violating the SOA. For maximum foldover slope, ground pin 4 and use equations 3 and 4.

0.65 +(V
O
* 0.014)
I
CL
=
R
CL

(3)

0.65 +(V
O
* 0.014)
R
CL
=
I
CL

(4)
Where:
V
O
is the output voltage in volts.
CL
for the desired current at 0v out, or with equation 4 to set R
CL
at
the maximum output voltage. Equation 3 should then be used to plot the resulting foldover limits on the SOA graph.
If equation 3 results in a negative current limit, foldover slope must be reduced. This can happen when the output
voltage is the opposite polarity of the supply conducting the current.
In applications where a reduced foldover slope is desired, this can be achieved by adding a resistor (R
FO
) between
pin 4 and ground. Use equations 4 and 5 with this new resistor in the circuit.

V
O

*
0.14
I
CL
=
R
CL
0.65 +
10.14 +R
FO (5)

V
O

*
0.14
R
CL
=
I
CL
0.65 +
10.14 +R
FO (6)
Where:
R
FO
is in K ohms.
IMPORTANT NOTICE
PA15FL PA15FLA
322 PA15FLU
PA15FL, PA15FLA
TYPICAL APPLICATION
LOW POWER, PIEZOELECTRIC POSITIONING
Piezo positioning may be applied to the focusing of segment-
ed mirror systems. The composite mirror may be composed of
hundreds of elements, each requiring focusing under computer
control. In such complex systems the PA15FL reduces the
costs of power supplies and cooling with its advantages of low
cost and low quiescent power consumption while increasing
circuit density with the SIP package.
PHASE COMPENSATION
GAIN C
C
R
C
1 33pf 1K
10 OPEN OPEN
.6
R
CL

I
CL
FEATURES
HIGH VOLTAGE 450V (225V)
LOW COST
LOW QUIESCENT CURRENT 3.0mA MAX
HIGH OUTPUT CURRENT 200mA
APPLICATIONS
PIEZOELECTRIC POSITIONING
ELECTROSTATIC TRANSDUCERS
DESCRIPTION
The PA15FL is a high voltage, low quiescent current MOSFET
operational amplifer designed as a low cost solution for driving
continuous output currents up to 200mA and pulse currents up
to 350mA into capacitive loads. The safe operating area (SOA)
has no second breakdown limitations and can be observed for
all type loads by choosing an appropriate current limiting resistor.
The MOSFET input stage has integrated static and differential
mode protection. The MOSFET output stage is biased AB for
linear operation. External compensation provides fexibility
in choosing bandwidth and slew rate for the application. The
10-pin power SIP package is electrically isolated.
Q1 Q2
6
1
2
5
9
8
10
7
R1 R2 C1 R3
Q3
CC1
CC2
Q6
Q5
R5
R8 R9
Q15
R11 R12
Q16
Q12
Q8
R4
R7
Q4
ILIM
OUT
Q14
R10
Q13
Q11
+V
S
IN
+IN
V
S
R6
COMPUTER
FOCUS
COMMAND
VOLTAGE
R
F
R
IN
+V
S
-V
S
1
2
5
7
6
10
PA15FL
V
OUT
PIEZO DRIVE
R
CL
R
CL
C
C
1 2 3 4 5 6 7 8 9 10
IN +IN
NC V +V C
C1
I
LIM
C
C2
R
C
OUT NC
S S
10-PIN SIP
PACKAGE STYLE FL
Formed leads available
See package style FU
High Voltage Power Operational Amplifiers
PA15FL PA15FLA
P r o d u c t
I n n o v a t i o n
F r o m
MAY 2009
APEX PA15FLUREVC
PA15FL PA15FLA
PA15FLU 323
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SUPPLY VOLTAGE, +V
S
to V
S
450V
OUTPUT CURRENT, source, sink See SOA
POWER DISSIPATION, continuous @ T
C
= 25C 30W
S

2
150C
SPECIFICATIONS
PA15FL PA15FLA
1
INPUT
OFFSET VOLTAGE, initial 2 10 .5 3 mV
OFFSET VOLTAGE, vs. time 75 * V/kh
BIAS CURRENT, initial 200 2000 * * pA
BIAS CURRENT, vs. supply 4 * pA/V
11
*
3
V
S
15 * V
COMMON MODE REJECTION, DC V
CM
= 90V 80 98 * * dB
NOISE 10KHz BW, R
S
= 1K, C
C
= OPEN 2 * Vrms
GAIN
OPEN LOOP, @ 15Hz R
L
= 2K, C
C
= OPEN 94 111 * * dB
GAIN BANDWIDTH PRODUCT at 1MHz R
L
= 2K, C
C
= OPEN 5.8 * MHz
POWER BANDWIDTH R
L
= 2K, C
C
= OPEN 24 * kHz
OUTPUT
VOLTAGE SWING
3
I
O
= 200mA V
S
15 V
S
10 * * V
CURRENT, continuous 200 * mA
SLEW RATE, A
V
= 100 C
C
= OPEN 20 20 30 V/s
CAPACITIVE LOAD, A
V
= +1 Full temperature range 100 * pf
SETTLING TIME to .1% C
C
= OPEN, 2V step 2 * s
RESISTANCE, no load 50 *
POWER SUPPLY
VOLTAGE
5
See note 5 50 150 225 * * * V
CURRENT, quiescent, 2.0 3.0 * * mA
THERMAL
4
Full temperature range, F > 60Hz 2.5 * C/W
RESISTANCE, DC, junction to case Full temperature range, F < 60Hz 4.2 * C/W
TEMPERATURE RANGE , Case Meets full range specifcations 25 +85 * * C
NOTES: * The specifcation of PA15FLA is identical to the specifcation for PA15FL in applicable column to the left.
C
= 25C, compensation = C
C
= 33pF, R
C
= 1K, R
CL
= 0. DC input specifcations are value given.
Power supply voltage is typical rating.
achieve high MTTF.
3. +V
S
and V
S
denote the positive and negative power supply rail respectively.
5. Derate max supply rating .625 V/C below 25C case. No derating needed above 25C case.
CAUTION
The PA15FL is constructed from MOSFET transistors. ESD handling procedures must be observed.
The exposed substrate contains beryllia (BeO). Do not crush, machine, or subject to temperatures in excess of 850C to
avoid generating toxic fumes.
PA15FL PA15FLA
324 PA15FLU
100K 1M
FREQUENCY, F (Hz)
270
45
PHASE RESPONSE
P
H
A
S
E
,

)

100K 10M
FREQUENCY, F (Hz)
10
0
30
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)

10
20
40
50
10 1M
FREQUENCY, F (Hz)
20
80
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)

40
60
100
1 1M
FREQUENCY, F (Hz)
0
20
120
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)

40
80
O
U
T
P
U
T

I
M
P
E
D
A
N
C
E
,

R

(
)

3M 10K 100K
FREQUENCY, F (Hz)
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

(
%
)

.1
.3
30K 100 1K 10K
100 300
S
(V)
2.0
OPEN LOOP OUTPUT IMPEDANCE
Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
m
A
)

2.4
1K 10K
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

+
V
S

V
O

(
V
)

10 100 1K 10K .1M
60
2.2
.001
1M
225
180
450
2.6
2.8
1M
.01
100
135
100 .1M
10M
200 400
T
C
= 85C
T
C
= 25C
T
C
= 125C
C
C
= Open
QUIESCENT CURRENT
0
50
100
150
200
250
300
350
400
10M
SWING FROM V
S
0 40 200
LOAD CURRENT, I (mA)
80 120 160
0
16
24
8
20
4
12
125C
85C
25C
55C
125C
85C
55C
25C
SWING FROM +V
S
0 40 160 200
LOAD CURRENT, I (mA)
80 120
R
L
= 1K
C
C
= Open
A

= 30
5 watt
50 mW
2K 100K
FREQUENCY, F (Hz)
20
500
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)

POWER RESPONSE
10K
100
C
C

=

O
p
e
n

C
C

=

1
5
p
f

2
10
4
8
6
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

+
V
S

V
O

(
V
)

200K
30
FREQUENCY, F (Hz)
C
C
= Open
C
C
= 33pF
C
C
= Open
10 10M
FREQUENCY, F (Hz)
20
0
60
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)

20
40
80
120
10K
100
C
C
= 33pF
C
C
= Open
C
C
= 33pF
C
C
= Open
90
100 1K .1M 1M
C
C

=

3
3
p
f

0 25 50 75 100 125 150
CASE TEMPERATURE, T
C
(C)
0
8
24
32
POWER DERATING
O
U
T
P
U
T

S
T
A
G
E

I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)

16
40
T
C
= -55C
PA15FL PA15FLA
PA15FLU 325
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
CURRENT LIMIT
CL
) must be
connected as shown in the external connection diagram. The
minimum value is 2 ohm, however for optimum reliability the
resistor value should be set as high as possible. The value
is calculated as follows; with the maximum practical value of
150 ohms.
.6
R
CL
=
I
LIM
and the wire bonds.
INPUT PROTECTION
Although the PA15FL can withstand differential input voltages
most applications 1N4148 or 1N914 signal diodes are sufficient
(D1-D4 in Figure 2a). In more demanding applications where
low leakage or low capacitance are of concern 2N4416 or
2N5457-2N5459 JFETs connected as diodes will be required
(Q1-Q4 in Figure 2b). In either case the input differential voltage
will be clamped to 1.4V. This is sufficient overdrive to produce
maximum power bandwidth.
mended as protection on the supply pins. The zeners clamp
transients to voltages within the power supply rating and also
clamp power supply reversals to ground. Whether the zeners
are used or not, the system power supply should be evaluated
for transient performance including power-on overshoot and
power-off polarity reversals as well as line regulation.
Conditions which can cause open circuits or polarity reversals
on either power supply rail should be avoided or protected
against. Reversals or opens on the negative supply rail are
known to induce input stage failure. Unidirectional transzorbs
prevent this, and it is desirable that they be both electrically
and physically as close to the amplifer as possible.
STABILITY
The PA15FL has sufficient phase margin to be stable with
most capacitive loads at a gain of 10 or more, using the recom-
mended phase compensation.
The PA15FL is externally compensated and performance can
be tailored to the application. Use the graphs of small signal
response and power response as a guide. The compensation
capacitor C
C
must be rated at 500V working voltage. An NPO
capacitor is recommended. The compensation network C
C
R
C

must be mounted closely to the amplifer pins 8 and 9 to avoid
spurious oscillation.
FIGURE 2. OVERVOLTAGE PROTECTION
PA15FL
+V
S
IN
+IN
Z1
Z2
D4 D3
6
5
1
2
+V
S
Z1
Z2
6
5
PA15FL
a.
b.
V
S
V
S
D2 D1
IN
+IN
1
2
Q1 Q2
Q3 Q4
SOA
S
V
O
(V)
25 50 75 100 250 500
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S
,

(
m
A
)
10
20
30
50
100
200
300
500
D
C
,

T
C
=

1
2
5
C
D
C
,

T
C
=

8
5
C
2
0
0
m
S
PULSE CURVES @ 10% DUTY CYCLE MAX
D
C
,

T
C
=

2
5
C
1
0
0
m
S
125
PA16 PA16A
326 PA16U
PA16, PA16A
FEATURES
HIGH POWER BANDWIDTH 350kHz
FAST SETTLING TIME 600ns
LOW CROSSOVER DISTORTION Class A/B
HIGH OUTPUT CURRENT 5A PEAK
LOW INPUT BIAS CURRENT FET Input
ISOLATED CASE 300 VDC
APPLICATIONS
MAGNETIC DEFLECTION CIRCUITS UP TO
5A
POWER TRANSDUCERS UP TO 350 kHz
R2 R3
R1
R5
R4
R8
R9 R10
R11
R12
R13
R14
R15
R6
R7
Q1
Q8
Q5
Q4
Q3
Q6
Q2
Q7
A1
D1
D2
4
2
1
6
8
12
10
DESCRIPTION
The PA16 and PA16A are wideband, high output cur-
rent operational amplifers designed to drive resistive,
inductive and capacitive loads. Their complementary
collector output stage can swing close to the supply
rails and is protected against inductive kickback. For
optimum linearity, the output stage is biased for class
A/B operation. The safe operating area (SOA) can be
observed for all operating conditions by selection of
user programmable, current limiting resistors (down to
10mA). Both amplifers are internally compensated but
are not recommended for use as unity gain followers.
For continuous operation under load, mounting on a
These hybrid integrated circuits utilize thick flm (cer-
met) resistors, ceramic capacitors and semiconductor
chips to maximize reliability, minimize size and give
top performance. Ultrasonically bonded aluminum
wires provide reliable interconnections at all operating
temperatures. The Power SIP package is electrically
isolated.
AUG 2008
APEX PA16REVH
PA16 PA16A
PA16U 327
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SUPPLY VOLTAGE, +V
S
to -V
S
38 V
OUTPUT CURRENT, within SOA 5 A
POWER DISSIPATION, internal (Note 2) 62.5 W
S
+ 2 +V
S
- 2 V
ABSOLUTE MAXIMUM RATINGS PA16/PA16A
SPECIFICATIONS
Parameter
Test Condi-
tions
3,7
PA16 PA16A
INPUT
Full temp range
10 50 * 25 V/C
OFFSET VOLTAGE vs. supply 10 * V/V
OFFSET VOLTAGE vs. power 6 * V/W
BIAS CURRENT, vs. temp 200 * pA/C
BIAS CURRENT, vs. supply 0.01 * pA/V
OFFSET CURRENT, vs. temp 100 * pA/C
INPUT IMPEDANCE, DC 1000 * G
CAUTION
IN +IN
OUT
+V
R
CL
+R
CL
S
V
S
1 2 3 4 5 6 7 8 9 10 11 12
12-pin SIP
PACKAGE
STYLE DP
PA16 PA16A
328 PA16U
Parameter
Test Condi-
tions
3,7
PA16 PA16A
COMMON MODE VOLTAGE
RANGE, Pos. (Note 6)
Full temp range +V
S
- 6 +V
S
- 3 * * V
COMMON MODE VOLTAGE
RANGE, Neg. (Note 6)
Full temp range -V
S
+ 6 -V
S
+ 5 * * V
DC
Full temp range 70 100 * * dB
GAIN
OPEN LOOP GAIN @ 10Hz 1K load 103 * dB
OPEN LOOP GAIN @ 10Hz Full temp range,
10K load
86 100 * * dB
@ 1MHz
10 load 4.5 * MHz
POWER BANDWIDTH 10 load 350 * kHz
PHASE MARGIN Full temp range,
10 load
30 *
OUTPUT
O
= 5A,
R
CL
= 0.08
V
S
- 4 V
S
- 3 V
S
- 3 * V
O
= 2A V
S
- 2 V
S
- 1.2 V
S
- 1.2 * V
CURRENT, peak 5 * A
SETTLING TIME to 0.1% 2V step 0.6 * S
SLEW RATE 13 20 * * V/S
A
V
> 10
SOA *
HARMONIC DISTORTION P
O
= 5W, F =
1kHz, R
L
= 4
0.028 * %
SMALL SIGNAL rise/fall time R
L
= 10,
A
V
= 1
100 * nS
SMALL SIGNAL overshoot R
L
= 10,
A
V
= 1
10 * %
POWER SUPPLY
VOLTAGE Full temp range 7 15 19 * * * V
THERMAL
RESISTANCE, AC,
F > 60Hz 1.4 1.63 * * C/W
RESISTANCE, DC,
junction to case
F < 60Hz 1.8 2.0 * * C/W
RESISTANCE, DC,
junction to air
30 * C/W
specifcation
-25 +85 * * C
PA16 PA16A
PA16U 329
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
0 25 50 75 100 125
CASE TEMPERATURE, T
C
(C)
0
30
50
70
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
D

(
W
)
10 100 10K .1M
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

e
N

(
n
V
/
H
z
)
1 100 10M
FREQUENCY, F (Hz)
20
0
60
120
O
P
E
N

L
O
O
P

G
A
I
N
,

A
O
L

(
d
B
)
20
40
80
100
1 100 .1M 10M
210
150
60
0
PHASE RESPONSE
90
30
.1M .2M .5M 1M
FREQUENCY, F (Hz)
6
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
1 3 4 7
0
2
3
SETTLING TIME
T
I
M
E
,

t

(
s
)
.5
1.5
2.5
0
OUTPUT CURRENT, I
O
(A)
S
A
T
U
R
A
T
I
O
N

V
O
L
T
A
G
E
,

V
S

V
O

(
V
)
25 50 100
CASE TEMPERATURE, T
C
(C)
0
2.5
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
2.0
2 5 6
1.0
INPUT NOISE
1K
10
15
20
1K
40
POWER RESPONSE
.3M
0 25 75
.5
1.0
10 1K 10K .1M 1M
60
10 10K 1M
FREQUENCY, F (Hz)
P
H
A
S
E
,

)
1.5
.7M
7.8
10
13
18
23
30
1
125
3.0
180
120
25
30
35
40
1 2 3 4 5
1.5
2.0
2.5
3.0
3.5
8
1
m
V

N
O

L
O
A
D
1
0
m
V
N
O
L
O
A
D
.5
| +V
S
| + | V
S
| = 36V
| +V
S
| + | V
S
| = 30V
T
C
= 25 to 85C
V
O
R
CL
= 0.3
R
CL
= 0.62
10mV 10 LOAD
10
FREQUENCY, F(Hz)
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)
100 1K 10K .1M 1M 10M
0
20
40
60
80
100
120
140
+V
S
V
S
25
CASE TEMPERATURE, T
C
(C)
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T

I
Q

(
X
)
0 25 50 75 100 125
.94
.92
.96
.98
1
1.02
1.04
1.06
1.08
1 10K
FREQUENCY, F (Hz)
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
120
.1M 10 100 1K 1M
20
60
100
10M
15 105
.25
64
256
BIAS CURRENT
4
.06
5 45 65 85
16
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
1
CASE TEMPERATURE, T
C
(C)
25
10
20
TYPICAL APPLICATION
Vehicular Sound System Power Stage
When system voltages are low and power is at a pre-
mium, the PA16 is a natural choice. The circuit above
utilizes not only the feature of low internal loss of the
PA16, but also its very low distortion level to imple-
ment a crystal clear audio amplifer suitable even for
airborne applications. This circuit uses AC coupling
of both the input signal and the gain circuit to render
DC voltage across the speaker insignifcant. The re-
sistor and capacitor across the inputs form a stabil-
ity enhancement network. The 0.27 ohm current limit
resistors provide protection in the event of an output
short circuit.
16K
100K
R
CL+
R
CL
.27
.27
3.2
16W
12
+12
.47F
.47F
16K
.001F
PA16
IN
1K
LOW INTERNAL LOSS MAXIMIZES EFFICIENCY
NOTES:
C
= 25C).
* The specifcation of PA16A is identical to the specifcation for PA16 in applicable column to the left.
3. The power supply voltage for all specifcations is the TYP rating unless otherwise noted as a test
condition.
4. +V
S
and V
S
S
is measured from +V
S

to V
S
.
60Hz.
6. Exceeding CMV range can cause the output to latch.
7. Full temperature specifcations are guaranteed but not 100% tested.
8. The absolute maximum negative input voltage is equal to the negative power supply voltage plus 1V
(-V
S
+ 1V).
PA16 PA16A
330 PA16U
0 25 50 75 100 125
CASE TEMPERATURE, T
C
(C)
0
30
50
70
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
D

(
W
)
10 100 10K .1M
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

e
N

(
n
V
/
H
z
)
1 100 10M
FREQUENCY, F (Hz)
20
0
60
120
O
P
E
N

L
O
O
P

G
A
I
N
,

A
O
L

(
d
B
)
20
40
80
100
1 100 .1M 10M
210
150
60
0
PHASE RESPONSE
90
30
.1M .2M .5M 1M
FREQUENCY, F (Hz)
6
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
1 3 4 7
0
2
3
SETTLING TIME
T
I
M
E
,

t

(
s
)
.5
1.5
2.5
0
OUTPUT CURRENT, I
O
(A)
S
A
T
U
R
A
T
I
O
N

V
O
L
T
A
G
E
,

V
S

V
O

(
V
)
25 50 100
CASE TEMPERATURE, T
C
(C)
0
2.5
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
2.0
2 5 6
1.0
INPUT NOISE
1K
10
15
20
1K
40
POWER RESPONSE
.3M
0 25 75
.5
1.0
10 1K 10K .1M 1M
60
10 10K 1M
FREQUENCY, F (Hz)
P
H
A
S
E
,

)
1.5
.7M
7.8
10
13
18
23
30
1
125
3.0
180
120
25
30
35
40
1 2 3 4 5
1.5
2.0
2.5
3.0
3.5
8
1
m
V

N
O

L
O
A
D
1
0
m
V
N
O
L
O
A
D
.5
| +V
S
| + | V
S
| = 36V
| +V
S
| + | V
S
| = 30V
T
C
= 25 to 85C
V
O
R
CL
= 0.3
R
CL
= 0.62
10mV 10 LOAD
10
FREQUENCY, F(Hz)
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)
100 1K 10K .1M 1M 10M
0
20
40
60
80
100
120
140
+V
S
V
S
25
CASE TEMPERATURE, T
C
(C)
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T

I
Q

(
X
)
0 25 50 75 100 125
.94
.92
.96
.98
1
1.02
1.04
1.06
1.08
1 10K
FREQUENCY, F (Hz)
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
120
.1M 10 100 1K 1M
20
60
100
10M
15 105
.25
64
256
BIAS CURRENT
4
.06
5 45 65 85
16
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
1
CASE TEMPERATURE, T
C
(C)
25
10
20
10K
FREQUENCY, F (Hz)
LOADING EFFECTS
D
E
L
T
A

G
A
I
N

W
I
T
H

L
O
A
D
,

A

(
d
B
)
1.2
.6
0
.1M 100 1K
1.5
.9
.3
I
O
=150mA
I
O
=400mA
PULSE RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
.2
.1
0
.1
.2
.3
.3
TIME, t (s)
0 .5 1.0 1.5
V
IN
=.2V, t
r
=50ns
1 3 4
TIME, t (s)
15
5
15
PULSE RESPONSE
10
0
10
2 5
5
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
0
V
IN
=1V, t
r
=100ns
LOAD = 10
.1K 1.0K
FREQUENCY, F (Hz)
0.001
0.1
1
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

T
H
D

(
%
)
10K
0.01
100K
A
V
=10
V
PS
=15V
P
O
=.5W
R
L
= 4
P
O
=5W
R
L
= 4
P
O
=25W
R
L
= 2
PA16 PA16A
PA16U 331
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
Please read Application Note 1 "General Operating Considerations" which
covers stability, supplies, heat sinking, mounting, current limit, SOA interpre-
tation, and specifcation interpretation. Visit www.cirrus.com for design tools
that help automate tasks such as calculations for stability, internal power dis-
sipation, current limit; heat sink selection; Apex Precision Powers complete
Application Notes library; Technical Seminar Workbook; and Evaluation Kits.
The SOA curves combine the effect of all limits for this Pow-
er Op Amp. For a given application, the direction and magni-
tude of the output current should be calculated or measured
and checked against the SOA curves. This is simple for re-
sistive loads but more complex for reactive and EMF gen-
erating loads. The following guidelines may save extensive
analytical efforts:
The amplifer can handle any EMF generating or reactive
load and short circuits to the supply rails or shorts to com-
mon if the current limits are set as follows at T
C
= 85C.
SHORT TO V
S
SHORT TO
V
S
C, L OR EMF LOAD COMMON
18V .9A 1.8A
15V 1.0A 2.1A
10V 1.6A 3.2A
These simplifed limits may be exceeded with further analy-
sis using the operating conditions for a specifc application.
CURRENT LIMIT
Proper operation requires the use of two current limit resistors, connected as shown in the external connection dia-
gram. The minimum value for R
CL
is 0.12 ohm, however for optimum reliability it should be set as high as possible.
Refer to the General Operating Considerations section of the handbook for current limit adjust details.

R
CL
= - 0.01
0.65
I
LIM
(A)
DEVICE MOUNTING
The case (mounting fange) is electrically isolated and should be mounted directly to a heatsink with thermal com-
pound. Screws with Belville spring washers are recommended to maintain positive clamping pressure on heatsink
mounting surfaces. Long periods of thermal cycling can loosen mounting screws and increase thermal resistance.
Since the case is electrically isolated (foating) with respect to the internal circuits it is recommended to connect it
to common or other convenient AC ground potential.
10K
FREQUENCY, F (Hz)
LOADING EFFECTS
D
E
L
T
A

G
A
I
N

W
I
T
H

L
O
A
D
,

A

(
d
B
)
1.2
.6
0
.1M 100 1K
1.5
.9
.3
I
O
=150mA
I
O
=400mA
PULSE RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
.2
.1
0
.1
.2
.3
.3
TIME, t (s)
0 .5 1.0 1.5
V
IN
=.2V, t
r
=50ns
1 3 4
TIME, t (s)
15
5
15
PULSE RESPONSE
10
0
10
2 5
5
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
0
V
IN
=1V, t
r
=100ns
LOAD = 10
.1K 1.0K
FREQUENCY, F (Hz)
0.001
0.1
1
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

T
H
D

(
%
)
10K
0.01
100K
A
V
=10
V
PS
=15V
P
O
=.5W
R
L
= 4
P
O
=5W
R
L
= 4
P
O
=25W
R
L
= 2
t

=

5
m
s
s
t
e
a
d
y

s
t
a
t
e

s
e
c
o
n
d

b
r
e
a
k
d
o
w
n
T
C
=

6
0
C T
C
=

8
5
C
5.0
4.0
3.0
2.0
1.5
1.0
0.8
0.6
0.5
6 7 8 10 9 15 20 25 30 38
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S

(
A
)
S
V
O
(V)
SOA
PA50 PA50A
332 PA50U
PA50, PA50A
FEATURES
HIGH CURRENT 40A Continuous, 100A PEAK
APPLICATIONS
SEMI-CONDUCTOR TESTING
DESCRIPTION
The PA50 is a MOSFET power operational amplifer that
extends the performance limits of power amplifers in slew
rate and power bandwidth, while maintaining high current and
power dissipation ratings.
Boost voltage inputs allow the small signal portion of the
amplifer to operate at a higher voltage than the high current
output stage. The amplifer is then biased to achieve close
linear swings to the supply rails at high currents for extra ef-
fcient operation.
TOP
VIEW
1
2
3
4
5
6
12
11
10
9
8
7
TOP
VIEW
IN
+IN
-OUT
-OUT
-V
s
-V
s
+OUT
+OUT
+Vb
-Vb
+V
s
+V
s
12-PIN DIP
PACKAGE STYLE CR
MAY 2009
APEX PA50UREVG
PA50 PA50A
PA50U 333
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA50 PA50A
1
INPUT
OFFSET VOLTAGE, vs. temperature Full temperature range 20 50 * * V/V
BIAS CURRENT vs. supply .01 * pA/V
OFFSET CURRENT, initial 10 50 * * pA
INPUT IMPEDANCE, DC 10" *
IMPUT CAPACITANCE 13 * pF
COMMON MODE VOLTAGE RANGE Full temperature range -V
B
+12
+V
B
-14 * V
COMMON MODE REJECTION,DC Full temp, range, V
CM
= 20V 90 100 * * dB
INPUT NOISE 100KHZ BW, Rs=1K 10 * Vrms
GAIN
OPEN LOOP,@ 15Hz Full temperature range 94 102 * * dB
L
=10 3 * MHz
POWER BANDWIDTH R
L
=4, V
o
=80V
P-P
, Av=-10 200 * kHz
OUTPUT
VOLTAGE SWING I
o
=40A V
S
9.5 V
S
8.0 * * V
VOLTAGE SWING, PA50 V
BOOST
=V
S
10V, I
o
=40A V
S
5.8 V
S
4.0 V
VOLTAGE SWING, PA50A V
BOOST
=V
S
10V, I
o
=50A V
S
5.8 V
S
5.0 V
CURRENT, peak 3ms 10% Duty Cycle 100 * A
SETTLING TIME TO.1% A
V
= -10,10V STEP,R
L
=4 1 * s
SLEW RATE A
V
=-10 50 * V/s
RESISTANCE I
O
=0, NO LOAD, 2MHZ 2.5 *
POWER SUPPLY
VOLTAGE, V
BOOST
Full temperature range +14, -12 15 65 * * * V
VOLTAGE, V
S
Full temperature range 3 50 * * V
CURRENT,quiescent, boost supply 26 32 * * mA
THERMAL
RESISTANCE,AC,junction to case
3
Full temperature range, F>60HZ .2 .25 * * C/W
RESISTANCE,DC,junction to case Full temperature range, F>60HZ .25 .31 * * C/W
SUPPLY VOLTAGE, +V
S
to V
S
100V
BOOST VOLTAGE, +V
b
to -V
b
130V
b

2
150C
SPECIFICATIONS
NOTES: * The specifcation of PA50A is identical to the specifcation for PA50 in applicable column to the left
C
= 25C, DC input specifcations are value given. Power supply voltage is typical rating.
V
BOOST
= V
S
.
CAUTION

PA50 PA50A
334 PA50U
0 25 50 75 100
TEMPERATURE, T (C)
0
200
300
400
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
100 1K 10M
FREQUENCY F (Hz)
0
10K 100K 1M
100
500
20
40
60
80
100
V
S
= V
B
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)
T = T
C
10
10 10M
FREQUENCY, Ff (Hz)
0
120
SMALL SIGNAL GAIN
O
P
E
N

L
O
O
P

G
A
I
N

R
E
S
P
O
N
S
E
,

A

(
d
B
)
40
80
FREQUENCY, F (Hz)
SMALL SIGNAL PHASE
0 10 30 40 50
0
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

V
O

(
V
)OUTPUT VOLTAGE SWING
20
1 100 1K 10K 100K 1M
O
P
E
N

L
O
O
P

P
H
A
S
E
,

)
100 10M 1 10 1K 10K 100K 1M
180
135
90
45
0
2
4
6
8
10
OUTPUT CURRENT, I
O
(A)
R
L
= 4
R
L
= 4
VBO
O
ST
=
VS
VB
O
O
S
T
=
V
S +
1
0
V
FREQUENCY, F (Hz)
0
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
100
1M 100 1K 10K 100K
20
60
10 20 100
S
(V)
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
1M
FREQUENCY, F (Hz)
100K
40 60 80
1
1.025
1.05
1.125
QUIESCENT CURRENT
1.075
1.1
20
40
90
100
POWER RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
50
60
30
70
80
100 1
SUPPLY TO OUTPUT DIFFERENTIAL, (V)
10
0.1
10
100
SAFE OPERATING AREA
O
U
T
P
U
T

C
U
R
R
E
N
T
,

(
A
)
1
D
C

T
C
=

1
2
5
C
D
C

T
C
=

8
5
C
D
C

T
C
=

2
5
C
t

=

1
0
m
s
t

=

1
m
s
PA50 PA50A
PA50U 335
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
CURRENT LIMIT
There is no internal circuit provision for current limit in the
PA50. However, the PA50 circuit board in the PA50 evaluation
kit does provide a means whereby the output current can be
sensed. An external circuit current limit can thereby be imple-
mented if needed.
BOOST OPERATION
With the V
BOOST
BOOST
(pin 11) and
V
BOOST
the amplifer. +V
S
(pin 9,10) and V
S
(pin 3,4) are connected to
the high current output stage. An additional 10V on the V
BOOST

pins is sufficient to allow the small signal stages to drive the
output transistors into saturation and improve the output voltage
BOOST
and +V
S

BOOST
and V
S

than the V
S
pins.
COMPENSATION
Compensation is internally fxed for a gain of 3 or more and
is not adjustable by the user. The PA50 therefore is not unity
gain stable.
Proper and sufficient power supply bypassing is crucial to
proper operation of the PA50. Bypass the +Vb and -Vb supply
pins with a minimum .1F ceramic capacitors directly at the
supply pins. On the +Vs and -Vs pins use a combination of
ceramic and electrolytic capacitors. Use 1F ceramic capaci-
tors and an electrolytic capacitor at least 10F for each amp
of output current required.
IMPORTANT NOTICE
PA51 PA51A
336 PA51U
PA51, PA51A
FEATURES
CLASS C OUTPUT Low Cost
LOW QUIESCENT CURRENT 2.6mA
APPLICATIONS
DC SERVO AMPLIFIER
MOTOR/SYNCHRO DRIVER
VALVE AND ACTUATOR CONTROL
DC OR AC POWER REGULATOR
DESCRIPTION
The PA51 and PA51A are high voltage, high output current
operational amplifers designed to drive resistive, inductive and
capacitive loads. Their complementary common emitter output
stage is the simple class C type optimized for low frequency
applications where crossover distortion is not critical. These
amplifers are not recommended for audio, transducer or defec-
tion coil drive circuits. The safe operating area (SOA) is fully
specifed and can be observed for all operating conditions by
selection of user programmable current limiting resistors. Both
amplifers are internally compensated for all gain settings. For
continuous operation under load, mounting on a heatsink of
proper rating is recommended. Do not use isolation washers!
This hybrid integrated circuit utilizes thick flm conductors,
ceramic capacitors and semiconductor chips to maximize reli-
ability, minimize size and give top performance. Ultrasonically
bonded aluminum wires provide reliable interconnections at
all operating temperatures. The 8-pin TO-3 package is electri-
cally isolated and hermetically sealed. The use of compress-
Considerations.
TYPICAL APPLICATION
The linear relationship of torque output to current input of
the modern torque motor makes this simple control circuit
ideal for many material processing and testing applications.
The sense resistor develops a feedback voltage proportional
to motor current and the small signal properties of the Power
Op Amp insure accuracy. With this closed loop operation, tem-
perature induced impedance variations of the motor winding
are automatically compensated.
.1

28V
+10V
C1
R1
PA51
R4
0/+5V
MOTOR CURRENT IS A FUNCTION OF V
IN
PROGRAMMABLE TORQUE CIRCUIT
.1

R3
R5
.5

R2
2.5K
4.16K
DAC
M
0/6A
CL+
+V
+IN
IN
V
N.C.
CL
OUT
S
S
TOP VIEW
R
CL+
R
CL
OUTPUT
1
2
3
4
5
6
7
8
A1
4
5
6
3
2
1
8
C1
Q4
Q6A
Q6B
Q3
Q1A
Q1B
8-PIN TO-3
PACKAGE STYLE CE
MAY 2009
APEX PA51UREVR
PA51 PA51A
PA51U 337
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SPECIFICATIONS
PA51 PA51A
2, 5
INPUT
C
= 25C 5 10 2 8 mV
C
= 25C 35 * V/V
C
= 25C 20 * V/W
C
= 25C 15 40 * 30 nA
BIAS CURRENT, vs. temperature Full temperature range .05 * nA/C
C
= 25C .02 * nA/V
C
= 25C 12 30 5 10 nA
OFFSET CURRENT, vs. temperature Full temperature range .05 * nA/C
INPUT IMPEDANCE, common mode T
C
= 25C 250 * M
INPUT IMPEDANCE, differential T
C
= 25C 10 * M
INPUT CAPACITANCE T
C
= 25C 3 * pF
3
S
6 V
S
3 * * V
3
T
C
= 25C, V
CM
= V
S
6V 70 110 80 * dB

GAIN
C
POWER BANDWIDTH T
C
= 25C, I
O
= 8A, V
O
= 40V
PP
10 16 * * kHz
OUTPUT
VOLTAGE SWING
3
T
C
= 25C, I
O
= 10A V
S
8 V
S
5 * * V
VOLTAGE SWING
3
Full temp. range, I
O
= 4A V
S
6 V
S
4 * * V
VOLTAGE SWING
3
Full temp. range, I
O
= 68mA V
S
6 * V
CURRENT T
C
= 25C 10 * A
C
= 25C, 2V step 2 * s
SLEW RATE T
C
= 25C, R
L
= 6 1.0 2.6 * * V/s
CAPACITIVE LOAD, unity gain Full temperature range 1.5 * nF
CAPACITIVE LOAD, gain > 4 Full temperature range SOA *
POWER SUPPLY
VOLTAGE Full temperature range 10 28 36 * 34 40 V
C
= 25C 2.6 10 * * mA
THERMAL
4
F > 60Hz 1.0 1.2 * * C/W
SUPPLY VOLTAGE, +V
S
to V
S
80V
S
1
200C
TEMPERATURE, pin solder -10s 300C
CAUTION
achieve high MTTF.
2. The power supply voltage specifed under the TYP rating applies unless otherwise noted as a test condition.
3. +V
S
and V
S
S
is measured from +V
S
to V
S
.
PA51 PA51A
338 PA51U
0 25 50 75 100 125
TEMPERATURE, T (C)
0
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
1 100 10M
FREQUENCY, F (Hz)
20
0
60
120
O
P
E
N

L
O
O
P

G
A
I
N
,

A
O
L

(
d
B
)
20
40
80
100
10K 20K 50K .1M
FREQUENCY, F (Hz)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
30 300 1K 30K
FREQUENCY, F (Hz)
.3
3
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N

(
%
)
.01
.1
1
6
TIME, (s)
8
PULSE RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
4
0
8
8 0 2 1
FREQUENCY, F (Hz)
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
-25 50 100
CASE TEMPERATURE, T
C
(C)
0
6
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
5
100 3K 10K
20
100
POWER RESPONSE
30K
0 25 75
2
3
0
10 1K 10K .1M 1M
150
40
60
1
4
4 10
6
2
2
10 100 1K 10K .1M 1M
20
40
60
80
100
120
70K
70
.03
125
7
80
PA51
R
CL
= 0.3
R
CL
= .12
50
36
26
19
13
9.7
7
V
S
= 40V
R
L
= 3
R
L
= 8
12
4
6
GAIN = +1 R
L
= 5
10
P O

=

.
1
W
P
O

=

5
W
P
O

=

5
0
W
V
S
= 36V
R
L
= 4
GAIN = 10
PA51A
1 100 .1M 10M
210
150
60
0
PHASE RESPONSE
90
30
1K 10 10K 1M
FREQUENCY, F (Hz)
P
H
A
S
E
,

)
180
120
0
OUTPUT CURRENT, I
O
(A)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y

(
V
)
3.0
2 4 6 8 10
3.5
4.0
4.5
5.0
5.5
2.5
TC
=
2
5
to
8
5
C
TC
=

2
5
C
50 0 100
.7
1.9
2.2
BIAS CURRENT
1.3
.4
10 100 10K .1M
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/
H
z
)
INPUT NOISE
1K
10
20
30
25 25 50 75
1.6
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
125
1.0
CASE TEMPERATURE, T
C
(C)
40
50
70
100
2.5
40
S
(V)
.4
.6
1.6
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
.8
1.4
50 60 70 80 90
1.2
1.0
30 20
T C
=

5
5
C T
C
= 25C
T
C
= 125C
PA51 PA51A
PA51U 339
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
automate tasks such as calculations for stability, internal
power dissipation, current limit and heat sink selection. The
"Application Notes" and "Technical Seminar" sections con-
tain a wealth of information on specifc types of applications.
Package outlines, heat sinks, mounting hardware and other
accessories are located in the "Packages and Accessories"
section. Evaluation Kits are available for most Apex Precision
Power product models, consult the "Evaluation Kit" section
for details. For the most current version of all Apex Precision
Power product data sheets, visit www.Cirrus.com.

limitations:
and the wire bonds.
The SOA curves combine the effect of of all limits for this
Power Op Amp. For a given application, the direction and
magnitude of the output current should be calculated or mea-
sured and checked against the SOA curves. This is simple
for resistive loads but more complex for reactive and EMF
generating loads. The following guidelines may save extensive
analytical efforts.
1. Under transient conditions, capacitive and dynamic* induc-
tive loads up to the following maximums are safe:
V
S
I
LIM
= 5A I
LIM
= 10A I
LIM
= 5A I
LIM
= 10A
40V 400F 200F 11mH 4.3mH
35V 800F 400F 20mH 5.0mH
30V 1,600F 800F 35mH 6.2mH
25V 5.0mF 2.5mF 50mH 15mH
20V 10mF 5.0mF 400mH 20mH
15V 20mF 10mF ** 100mH
* If the inductive load is driven near steady state conditions,
supply rail with I
LIM
= 10A or 15V below the supply rail with
I
LIM
= 5A while the amplifer is current limiting, the inductor
should be capacitively coupled or the current limit must be
lowered to meet SOA criteria.
** Second breakdown effect imposes no limitation but thermal
limitations must still be observed.
load and short circuits to the supply rail or shorts to common
if the current limits are set as follows at T
C
= 85C.
SHORT TO V
S
SHORT TO
V
S
45V 0.1A 1.3A
40V 0.2A 1.5A
35V 0.3A 1.6A
30V 0.5A 2.0A
25V 1.2A 2.4A
20V 1.5A 3.0A
15V 2.0A 4.0A
3.The output stage is protected against transient fyback. How-
ever, for protection against sustained, high energy fyback,
external fast-recovery diodes should be used.
CURRENT LIMIT
tors, connected as shown in the external connection diagram.
CL
is .06 ohm, however for optimum
10
5.0
3.0
1.5
1.0
0.7
0.2
5 15 20 30 40 50 70 80
S
V
O
(V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S

(
A
)
0.3
0.5
7.0
7 10
2.0
s
t
e
a
d
y

s
t
a
t
e
t

=

5
m
s
t

=

1
m
s
T
C =
8
5
C
T
C =
2
5
C
T
C =
1
2
5
C
T
H
E
R
M
A
L
SOA
PA51M/883
340 PA51MU
PA51M/883
Q
25C 34V V
IN
= 0, A
V
= 100, R
CL
= .1 10 mA
OS
25C 34V V
IN
= 0, A
V
= 100 10 mV
OS
25C 10V V
IN
= 0, A
V
= 100 16 mV
OS
25C 40V V
IN
= 0, A
V
= 100 11.2 mV
B
25C 34V V
IN
= 0 40 nA
B
25C 34V V
IN
= 0 40 nA
OS
25C 34V V
IN
= 0 10 nA
Q
55C 34V V
IN
= 0, A
V
= 100, R
CL
= .1 10 mA
OS
55C 34V V
IN
= 0, A
V
= 100 15.2 mV
OS
55C 10V V
IN
= 0, A
V
= 100 21.2 mV
OS
55C 40V V
IN
= 0, A
V
= 100 16.4 mV
B
55C 34V V
IN
= 0 72 nA
B
55C 34V V
IN
= 0 72 nA
OS
55C 34V V
IN
= 0 26 nA
Q
125C 34V V
IN
= 0, A
V
= 100, R
CL
= .1 13 mA
OS
125C 34V V
IN
= 0, A
V
= 100 16.5 mV
OS
125C 10V V
IN
= 0, A
V
= 100 22.5 mV
OS
125C 40V V
IN
= 0, A
V
= 100 17.7 mV
B
125C 34V V
IN
= 0 80 nA
B
125C 34V V
IN
= 0 80 nA
OS
125C 34V V
IN
= 0 30 nA
4 Output voltage, I
O
=10A V
O
25C 18V R
L
= 1 10 V
4 Output voltage, I
O
= 68mA V
O
25C 40V R
L
= 500 34 V
4 Output voltage, I
O
= 4A V
O
25C 30V R
L
= 6 24 V
4 Current limits I
CL
25C 16V R
L
= 1, R
CL
= .1 5 7.9 A
4 Stability/noise E
N
25C 34V R
L
= 500, A
V
= +1, C
L
= 1.5nF 1 mV
L
= 500 1.0 10 V/s
4 Open loop gain A
OL
25C 34V R
L
= 500, F = 10Hz 94 dB
4 Common-mode rejection CMR 25C 15V R
L
= 500, F = DC, V
CM
= 9V 70 dB
6 Output voltage, I
O
=10A V
O
55C 18V R
L
= 1 10 V
6 Output voltage, I
O
= 68mA V
O
55C 40V R
L
= 500 34 V
6 Output voltage, I
O
= 4A V
O
55C 30V R
L
= 6 24 V
6 Stability/noise E
N
55C 34V R
L
= 500, A
V
= +1, C
L
= 1.5nF 1 mV
L
= 500 1.0 10 V/s
6 Open loop gain A
OL
55C 34V R
L
= 500, F = 10Hz 94 dB
L
= 500, F = DC, V
CM
= 9V 70 dB
5 Output voltage, I
O
= 8A V
O
125C 16V R
L
= 1 8 V
5 Output voltage, I
O
= 68mA V
O
125C 40V R
L
= 500 34 V
5 Output voltage, I
O
= 4A V
O
125C 30V R
L
= 6 24 V
5 Stability/noise E
N
125C 34V R
L
= 500, A
V
= +1, C
L
= 1.5nF 1 mV
L
= 500 1.0 10 V/s
5 Open loop gain A
OL
125C 34V R
L
= 500, F = 10Hz 94 dB
L
= 500, F = DC, V
CM
= 9V 70 dB
BURN IN CIRCUIT
board.
= 125C.
100K
1
1
100K
+15V
15V
5
6
2
7
1
8
3
20
* *
*
*
U.U.T
4
SEP 2009
APEX PA51MUREVJ
PA52 PA52A
PA52U 341
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA52, PA52A
FEATURES
HIGH CURRENT 40A Continuous, 80A PEAK
APPLICATIONS
SEMI-CONDUCTOR TESTING
DESCRIPTION
The PA52 is a MOSFET power operational amplifer that
extends the performance limits of power amplifers in slew
rate and power bandwidth, while maintaining high current and
power dissipation ratings.
Boost voltage inputs allow the small signal portion of the
amplifer to operate at a higher voltage than the high current
output stage. The amplifer is then biased to achieve close
linear swings to the supply rails at high currents for extra ef-
fcient operation.
TOP
VIEW
1
2
3
4
5
6
12
11
10
9
8
7
TOP
VIEW
IN
+IN
-OUT
-OUT
-V
s
-V
s
+OUT
+OUT
+Vb
-Vb
+V
s
+V
s
12-PIN DIP
PACKAGE STYLE CR
MAY 2009
APEX PA52UREVG
PA52 PA52A
342 PA52U
SUPPLY VOLTAGE, +V
S
to V
S
200V
BOOST VOLTAGE, +V
b
to -V
b
230V
b

2
150C
SPECIFICATIONS
NOTES: * The specifcation of PA52A is identical to the specifcation for PA52 in applicable column to the left
C
= 25C, DC input specifcations are value given. Power supply voltage is typical rating.
V
BOOST
= V
S
.
CAUTION
PA52 PA52A
1
INPUT
OFFSET VOLTAGE, vs. temperature Full temperature range 20 50 * * V/V
BIAS CURRENT vs. supply .01 * pA/V
INPUT IMPEDANCE, DC 10" *
IMPUT CAPACITANCE 13 * pF
COMMON MODE VOLTAGE RANGE Full temperature range -V
B
+12
+V
B
-14 * V
COMMON MODE REJECTION,DC Full temp, range, V
CM
= 20V 90 100 * * dB
INPUT NOISE 100KHZ BW, Rs=1K 10 * Vrms
GAIN
OPEN LOOP,@ 15Hz Full temperature range 94 102 * * dB
L
=10 3 * MHz
POWER BANDWIDTH R
L
=4, V
o
=180V
P-P
, Av=-10 90 * kHz

OUTPUT
VOLTAGE SWING I
o
=40A V
S
9.5 V
S
8.0 * * V
VOLTAGE SWING, PA52 V
BOOST
=V
S
10V, I
o
=40A V
S
5.8 V
S
4.0 V
VOLTAGE SWING, PA52A V
BOOST
=V
S
10V, I
o
=50A V
S
5.8 V
S
5.0 V
CURRENT, peak 3ms 10% Duty Cycle 80 * A
SETTLING TIME TO.1% A
V
= -10,10V STEP,R
L
=4 1 * s
SLEW RATE A
V
=-10 50 * V/s
RESISTANCE I
O
=0, NO LOAD, 2MHZ 2.5 *

POWER SUPPLY
VOLTAGE, V
BOOST
Full temperature range +14, -12 30 115 * * * V
VOLTAGE, V
S
Full temperature range 3 100 * * V
CURRENT,quiescent, boost supply 26 32 * * mA

THERMAL
RESISTANCE,AC,junction to case
3
Full temperature range, F>60HZ .2 .25 * * C/W
RESISTANCE,DC,junction to case Full temperature range, F>60HZ .25 .31 * * C/W
PA52 PA52A
PA52U 343
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
0 25 50 75 100
TEMPERATURE, T (C)
0
200
300
400
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
100 1K 10M
FREQUENCY F (Hz)
0
10K 100K 1M
100
20
40
60
80
100
T = T
C
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)
10
10 10M
FREQUENCY,Ff (Hz)
0
120
SMALL SIGNAL GAIN
O
P
E
N

L
O
O
P

G
A
I
N

R
E
S
P
O
N
S
E
,

A

(
d
B
)
40
80
FREQUENCY, F (Hz)
SMALL SIGNAL PHASE
0 10 30 40 50
0
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

V
O

(
V
)
20
1 100 1K 10K 100K 1M
O
P
E
N

L
O
O
P

P
H
A
S
E
,

)
100 10M 1 10 1K 10K 100K 1M
180
135
90
45
0
2
4
6
8
10
OUTPUT CURRENT, I
O
(A)
R
L
= 4
R
L
= 4
VBO
O
ST
=
VS
VB
O
O
S
T
=
VS
+
1
0
V
FREQUENCY, F (Hz)
0
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
100
1M 100 1K 10K 100K
20
60
10 0 200
SS
(V)
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q
(
X
)
1M
FREQUENCY, F (Hz)
100K
50 100 150
1
1.04
1.08
1.18
QUIESCENT CURRENT
1.12
1.16
10
POWER RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
100
200
100 1
SUPPLY TO OUTPUT DIFFERENTIAL, (V)
10
0.1
10
80
SAFE OPERATING AREA
O
U
T
P
U
T

C
U
R
R
E
N
T
,

(
A
)
1
D
C

T
C
=

1
2
5
C
D
C

T
C
=

8
5
C
D
C

T
C
=

2
5
C
t

=

1
0
m
s
t

=

1
m
s
1.02
1.06
1.10
1.14
PA52 PA52A
344 PA52U
GENERAL
CURRENT LIMIT
There is no internal circuit provision for current limit in the
PA52. However, the PA52 circuit board in the PA52 evaluation
kit does provide a means whereby the output current can be
sensed. An external circuit current limit can thereby be imple-
mented if needed.
BOOST OPERATION
With the V
BOOST
BOOST
(pin 11) and
V
BOOST
the amplifer. +V
S
(pin 9,10) and V
S
(pin 3,4) are connected to
the high current output stage. An additional 10V on the V
BOOST

pins is sufficient to allow the small signal stages to drive the
output transistors into saturation and improve the output voltage
BOOST
and +V
S

BOOST
and V
S

than the V
S
pins.
COMPENSATION
Compensation is internally fxed for a gain of 3 or more and
is not adjustable by the user. The PA52 therefore is not unity
gain stable.
Proper and sufficient power supply bypassing is crucial to
proper operation of the PA52. Bypass the +Vb and -Vb supply
pins with a minimum .1F ceramic capacitors directly at the
supply pins. On the +Vs and -Vs pins use a combination of
ceramic and electrolytic capacitors. Use 1F ceramic capaci-
tors and an electrolytic capacitor at least 10F for each amp
of output current required.
IMPORTANT NOTICE
PA60
PA60U 345
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA60EU
FEATURES
RoHS COMPLIANT
LOW COST
WIDE BANDWIDTH - 1.1 Mhz
HIGH OUTPUT CURRENT - 1A per amplifer
WIDE COMMON MODE RANGE Includes negative supply
WIDE SUPPLY VOLTAGE RANGE
Single supply: 5V to 40V
Split supplies: 2.5V to 20V
LOW QUIESCIENT CURRENT
VERY LOW DISTORTION
APPLICATIONS
HALF AND FULL BRIDGE MOTOR DRIVERS
AUDIO POWER AMPLIFIER
Stereo - 15.91W RMS per channel
Bridge - 31.82W RMS per 2 channels
IDEAL FOR SINGLE SUPPLY SYSTEMS
5V - Peripherals
12V - Automotive
28V - Avionic
DESCRIPTION
The amplifer design is a dual power op amp on a single
monolithic die. This approach provides a cost-effective solu-
tion to applications where multiple amplifers are required or a
bridge confguration is needed. Very low harmonic distortion
of 0.02% THD and low I
Q
makes the PA60 a good solution for
low power audio applications such as laptops and computer
speakers.
FIGURE 1. Equivalent schematic (one channel)
The dual output PA60EU, is available in a 12-Pin Molded
Plastic SIP with standard 100 mil spacing. The heat tab of EU
package is tied to -V
S
.
FIGURE 2. Bi-directional speed control from a single supply
TYPICAL APPLICATION
R1 and R2 set up Amplifer A as non-inverting. Amplifer
B is set up as a unity gain inverter driven from the output of
Amplifer A. Note that Amplifer B inverts the signals about the
reference node, which is set at mid-supply by R5 and R6. When
the command input is midrange, so is the output of Amplifer
A. Since this is also equivalent to the reference node voltage,
the output of Amplifer B is the same resulting in 0V across
the motor. Inputs more positive than 5V result in motor current
fow from left to right (see Figure 2). Inputs less than 5V drive
the motor in the opposite direction.
The amplifers are especially well-suited for applications such
as this. The extended common mode range allows command
inputs as low as 0V. The output swing lets it drive within 2V
of the supply at an output of 1A. This means that a command
input that ranges from 0 to 10V will drive a 24V motor from
full scale CCW to full scale CW at 1A.
FIGURE 3. External Connections.
High VoltagePower Operational Amplifiers
PA60EU P r o d u c t I n n o v a t i o n F r o m
OUT
+Vs
-IN +IN
-Vs
I BIAS
MONITOR
THERMAL
PROTECT
JUL 2009
APEX - PA60UREVH
12-PIN SIP
PACKAGE STYLE EU
INPUT
0-10V
A
M
B
R2 R3
R4
R5
R6
R1
1/2 PA60 1/2 PA60
+28V
+
_
+
_
+
I
N
(
A
)

-
I
N
(
A
)

N
C

-
V
S

O
U
T
(
A
)

-
V
S

+
V
S

O
U
T
(
B
)

-
V
S

N
C

-
I
N
(
B
)

+
I
N
(
B
)

PA60EU
+
- A -
+
B
SUB
SUB SUB
1 2 3 4 5 6 7 8 9 10 11 12
PA60
346 PA60U
SUPPLY VOLTAGE, total 5V to 40V
OUTPUT CURRENT SOA
POWER DISSIPATION, internal (PA60EU, 1 amplifer) 19.89W
POWER DISSIPATION, internal (PA60EU, 2 amplifers)
4
31.82W
INPUT VOLTAGE, differential Vs
INPUT VOLTAGE, common mode +Vs,-Vs-.5V
JUNCTION TEMPERATURE, max.
1
150C
TEMPERATURE, pin solder - 10 secs max. 220C
TEMP RANGE STORAGE -55C to 150C
OPERATING TEMP RANGE, case
1
-40C to 125C
SPECIFICATIONS (PER AMPLIFIER)
1,2
MIN TYP MAX UNITS
INPUT
OFFSET VOLTAGE, initial 1 15 mV
OFFSET VOLTAGE, vs. temperature Full temp range 20 V/C
BIAS CURRENT, initial 100 500 nA
COMMON MODE RANGE Full temp range -Vs +Vs - 1.3 V
POWER SUPPLY REJECTION Full temp range 60 90 dB
CHANNEL SEPARATION I
OUT
= 500mA, = 1kHz 50 68 dB
INPUT NOISE VOLTAGE R
S
= 100, = 1 to 100kHz 22 nV/Hz
GAIN
OPEN LOOP GAIN V
O
= 10V, R
L
= 2.0K 89 100 dB
GAIN BANDWIDTH PRODUCT = 100kHz, C
L
= 100pF, R
L
= 2.0K 0.9 1.4 MHz
PHASE MARGIN Full temp range, C
L
= 100pF, R
L
= 2K 65 C
POWER BANDWIDTH V
O(P-P)
= 28V 13.6 kHz
OUTPUT
CURRENT, peak 1.5 A
SLEW RATE 1.0 1.4 V/S
VOLTAGE SWING Full temp range, I
O
= 100mA |Vs| -1.1 |Vs| -0.8 V
O
= 1A |Vs| -1.8 |Vs| -1.4 V
HARMONIC DISTORTION A
V
= 1, R
L
= 50, .02 %
V
O
= .5VRMS, = 1kHz
POWER SUPPLY
VOLTAGE, V
SS
3
5 30 40 V
CURRENT, quiescent total 8 10 mA
THERMAL
DC, 1 amplifer 5.71 6.29 C/W
DC, 2 amplifers
4
3.57 3.93 C/W
AC, 1 amplifer 4.29 4.71 C/W
AC, 2 amplifers
4
2.68 2.95 C/W
RESISTANCE, junction to air 30 C/W
Notes: 1. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation to
achieve high MTTF.
2. Unless otherwise noted, the following conditions apply: V
S
= 15V, T
C
=25C.
3. +V
S
and -V
S
denote the positive and negative rail respectively. V
SS
denotes total rail-to-rail supply.
4. Rating applies when power dissipation is equal in each of the amplifers.
5. If -V
S
is disconnected before +V
S
, a diode between -V
S
and ground is recommended to avoid damage.
PA60
PA60U 347
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
-50 0 50 100 150
-0.5
0.5
1.5
2.5
CASE TEMPERATURE, T
C
(C)
A
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
m
A
)
BIAS CURRENT
-50 0 50 100 150
0
1
2
3
CASE TEMPERATURE, T
C
(C)
N
O
R
M
A
L
I
Z
W
D

O
F
F
S
E
T

V
O
L
T
A
G
E
,

V
O
S

(
m
V
)
OFFSET VOLTAGE
00 04 08 12 16
35
45
55
65
OUTPUT LOAD CAPACITANCE, C
L
(nF)
P
H
A
S
E

M
A
R
G
I
N
,

)
PHASE MARGIN vs. OUTPUT LOAD CAPACITANCE
20
25
0
-20
20
40
60
1 10 100 1K 10K
90
100
110
120
130
VOLTAGE GAIN & PHASE vs. FREQUENCY
FREQUENCY, (KHz)
G
A
I
N
,

A

(
d
B
)
P
H
A
S
E
,

)
PULSE RESPONSE
TIME, t (s)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
0 10 20 30 40 50
-4
8
4
0
-8
-2
10
6
2
-6
-10
60 70
+V
S
= +15V
A
V
= +1
V
IN
= 10Vp
-V
S
= -15V
R
L
= 20
f
IN
= 20kHz
QUIESCENT CURRENT
0.5 0.7 0.9 1.1 1.3
NORMALIZED QUIESCENT CURRENT, I
Q
(mA)
T
O
T
A
L

S
U
P
P
L
Y

V
O
L
T
A
G
E
,

V
S

(
V
)
20
16
12
0
4
8
-80
-40
0
40
80
120
C
A
S
E

T
E
M
P
E
R
A
T
U
R
E
,

T
C

(
C
)
OUTPUT CURRENT, I
O
(A)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

(
V
)
0.1 0.2 0.3 0.4 0.5 0.6
0.6
1.8
1.4
1
0.2
0.8
2
1.6
1.2
0.4
0
0.7 1.0 0.9 0.8
PULSE RESPONSE
TIME, t (s)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
0 200 400 600 800 1000
0
1200 1400
+V
S
= +15V
A
V
= +1
V
IN
= 10Vp
-V
S
= -15V
f
IN
= 1kHz
-4
8
4
-8
-2
10
6
2
-6
-10
-100
0.5
1.5
2.5
-100
0
1
2
1.5 1.7 1.9
160 24
PA60
348 PA60U
GENERAL
ations" which covers stability, supplies, heatsinking, mounting,
SOA interpretation, and specifcation interpretation. Visit www.
Cirrus.com for design tools that help automate tasks such as
calculations for stability, internal power dissipation, heatsink
selection; Apex's complete Application Notes library; Technical
Seminar Workbook; and Evaluation Kits.
STABILITY CONSIDERATIONS
All monolithic power
op amps use output
stage topologies that
present special sta-
bility problems. This
is primarily due to
non-complementary
(both devices are NPN)
output stages with a
mismatch in gain and
phase response for
different polarities of
output current. It is dif-
fcult for the op amp manufacturer to optimize compensation
for all operating conditions. For applications with load current
exceeding 300mA, oscillation may appear. The oscillation may
occur only with the output voltage swing at the negative or
positive half cycle. Under most operating and load conditions
acceptable stability can be achieved by providing a series RC
snubber network connected from the output to ground (see
Figure 4). The recommended component values of the of the
network are,R
SN
= 10 and C
SN
= 0.01F. Please refer to Ap-
plication Note 1 for further details.
The SOA curves combine the effect of all limits for this power
op amp. For a given application, the direction and magnitude
loads but more complex for reactive and EMF generating loads.
The following guidelines may save extensive analytical efforts.
The PA60EU has a large exposed copper heat tab to which
the monolithic is directly attached. The PA60EU may require a
thermal washer, which is electrically insulating since the tab
is directly tied to -V
S
. This can result in a thermal impedance
R
CS
of up to 1C/W or greater.
FIGURE 4. R-C Snubber
1 10 100
S
- V
O
, (V)
0.1
1
10
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

o
r

-
V
S
,

(
A
)
SOA PA60EU
DC, T
C
= 25C
DC, T
C
= 85C
(A) AMPLIFIER LOADED
(A+B) AMPLIFIERS LOADED
+
C
SN
0.01F
R
SN
10
POWER DERATING
CASE TEMPERATURE, T
C
(C)
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)

0 25 50 75 100 125
25
20
15
10
5
(A) AMPLIFIER
30
(A+B) AMPLIFIERS
0
35
1. Always use a heat sink. Even unloaded the PA60EU can
dissipate up to .4 watts.
2. Avoid bending the leads. Such action can lead to internal
damage.
3. Always fasten the tab of the EU package to the heat sink
before the leads are soldered to fxed terminals.
4. Strain relief must be provided if there is any probability of
axial stress to the leads.
PA61 PA61A
PA61U 349
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA61, PA61A
FEATURES
LOW COST Class C output stage
LOW QUIESCENT CURRENT 3mA
APPLICATIONS
PROGRAMMABLE POWER SUPPLY
MOTOR/SYNCRO DRIVER
VALVE AND ACTUATOR CONTROL
DC OR AC POWER REGULATOR
FIXED FREQUENCY POWER OSCILLATOR
DESCRIPTION
The PA61 and PA61A are high output current operational
amplifers designed to drive resistive, inductive and capaci-
tive loads. Their complementary emitter follower output stage
is the simple class C type and optimized for low frequency
applications where crossover distortion is not critical. These
amplifers are not recommended for audio, transducer or
defection coil drive circuits above 1kHz or when distortion is
critical. The safe operating area (SOA) is fully specifed and
can be observed for all operating conditions by selection of
user programmable current limiting resistors. Both amplifers
are internally compensated for all gain settings. For continu-
ous operation under load, mounting on a heatsink of proper
rating is recommended.
This hybrid circuit utilizes thick flm conductors, ceramic
capacitors, and semiconductor chips to maximize reliabil-
ity, minimize size, and give top performance. Ultrasonically
bonded aluminum wires provide reliable interconnections at
all operating temperatures. The 8-pin TO-3 package is electri-
cally isolated and hermetically sealed. The use of compres-
sible thermal washers and/or improper mounting torque
voids the product warranty. Please see General Operating
Considerations.
TOP VIEW
1
2
3
4
5
6
7
8
C
L
V
S
+IN
IN
+V
S
OUT
N.C.
C
L+
R
CL+
R
CL
OUTPUT
+42V
42V
R
F1

PA61
R
CL+

R
CL

R
F2

R
W

RTN

SENSE LO
R
W

10V
SENSE HI
LOAD
DAC
R
IN1
R
IN2
OUT
FIGURE 1. PROGRAMMABLE POWER SUPPLY
WITH REMOTE SENSING
2
8
1
3
6
4
5
A1
Q3
Q4
C1
Q1A
Q1B
Q6B
Q6A
TYPICAL APPLICATION
Due to its high current drive capability, PA61 applications
often utilize remote sensing to compensate IR drops in the
wiring. The importance of remote sensing increases as ac-
curacy requirements, output currents, and distance between
amplifer and load go up. The circuit above shows wire resis-
tance from the PA61 to the load and back to the local ground
via the power return line. Without remote sensing, a 7.5A load
current across only 0.05 ohm in each line would produce a
0.75V error at the load.
With the addition of the second ratio matched R
F
/R
IN
pair
and two low current sense wires, IR drops in the power return
line become common mode voltages for which the op amp
has a very high rejection ratio. Voltage drops in the output and
power return wires are inside the feedback loop. Therefore, as
long as the Power Op Amp has the voltage drive capability to
overcome the IR losses, accuracy remains the same. Applica-
tion Note 7 presents a general discussion of PPS circuits.
8-PIN TO-3
PACKAGE STYLE CE
MAY 2009
APEX PA61UREVL
PA61 PA61A
350 PA61U
PA61 PA61A
2
INPUT
C
= 25C 2 6 1 4 mV
OFFSET VOLTAGE, vs. temperature Specifed temperature range 10 65 * 40 V/C
C
= 25C 30 200 * * V/V
C
= 25C 20 * V/W
C
= 25C 12 30 10 20 nA
BIAS CURRENT, vs. temperature Specifed temperature range 50 500 * * pA/C
C
= 25C 10 * pA/V
C
= 25C 12 30 5 10 nA
OFFSET CURRENT, vs. temperature Specifed temperature range 50 * pA/C
C
= 25C 200 * M
INPUT CAPACITANCE T
C
= 25C 3 * pF
3
Specifed temperature range V
S
5 V
S
3 * * V
3
Specifed temperature range 74 100 * * dB

GAIN
C
POWER BANDWIDTH T
C
= 25C, I
O
= 8A, V
O
= 40V
PP
10 16 * * kHz
OUTPUT
VOLTAGE SWING
3
T
C
= 25C, I
O
= 10A V
S
7 V
S
5 V
S
6 * V
VOLTAGE SWING
3
Full temp. range, I
O
= 4A V
S
6 V
S
4 * * V
VOLTAGE SWING
3
Full temp. range, I
O
= 68mA V
S
5 * V
CURRENT T
C
= 25C 10 * A
C
= 25C, 2V step 2 * s
SLEW RATE T
C
= 25C, R
L
= 6 1.0 2.8 * * V/s
CAPACITIVE LOAD, unit gain Full temperature range 1.5 * nF
CAPACITIVE LOAD, gain>4 Full temperature range SOA *
POWER SUPPLY
C
= 25C 3 10 * * mA
THERMAL
4
F > 60Hz 1.0 1.2 * * C/W
TEMPERATURE RANGE, case Meets full range specifcation 25 25 +85 * * * C
SPECIFICATIONS
SUPPLY VOLTAGE, +V
S
to V
S
90V
S

TEMPERATURE, pin solder-10s 300C
1
200C
achieve high MTTF.
3. +V
S
and V
S
S
is measured from +V
S
to V
S
.
CAUTION
PA61 PA61A
PA61U 351
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
0 25 50 75 100 125 150
TEMPERATURE, T
C
(C)
0
20
60
100
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
50 0 100
.7
1.9
2.2
BIAS CURRENT
1.3
.4
10 100 10K .1M
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V

(
n
V
/
H
z
)
1 100 10M
FREQUENCY, F (Hz)
20
0
60
120
O
P
E
N

L
O
O
P

G
A
I
N
,

A
O
L

(
d
B
)
20
40
80
100
1 100 .1M 10M
210
150
60
0
PHASE RESPONSE
90
30
FREQUENCY, F (Hz)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
FREQUENCY, F (Hz)
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

(
%
)
40
S
(V)
.4
.6
1.6
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
.8
1.4
1 10K
FREQUENCY, F (Hz)
0
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
120
.1M 10 100
25 50 100
CASE TEMPERATURE, T
C
(C)
0
6
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
5
INPUT NOISE
1K
10
20
30
1K
25 25 50 75
1.6
40
POWER RESPONSE
50 60 70 80 90
1.2
0 25 75
2
3
10 1K 10K .1M 1M
80
10 10K 1M
FREQUENCY, F (Hz)
P
H
A
S
E
,

)
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
1
4
1K 1M
20
60
100
1.0
125
1.0
125
7
CASE TEMPERATURE, T
C
(C)
180
120
40
50
70
100
2.5
30 20
0
OUTPUT CURRENT, I
O
(A)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y

(
V
)
3.0
2 4 6 8 10
3.5
4.0
4.5
5.0
5.5
2.5
0
TIME, t (s)
PULSE RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
8
2 4 6 8 10 12
6
4
2
0
2
4
6
8
14
R
C
L
=
.1
2

R
CL
= 0.3 TC
=
2
5
to
8
5
C
TC
=

2
5
C
T = T
C
21
30
41
58
15
80
11
10K .1M 20K 30K 50K 70K
8
R
L
= 8
R
L
= 3
V
S
= 40V
R
L
= 5 A
V
= +1
1
3
10
.3
.1
30 300 1K 10K 100 30K
.03
.01
3K
V
S
= 36
R
L
= 4
A
V
= 10
P
O

=

5
W
P O

=

.
1
W
P
O

=

5
0
W
T C
=

5
5
C T
C
= 25C
T
C
= 125C
PA61 PA61A
352 PA61U
GENERAL
visit www.Cirrus.com.
The output stage of most power amplifers has 3 distinct
limitations:
and the wire bonds.
The following guidelines may save extensive analytical efforts.
1. Under transient conditions, capacitive and dynamic* induc-
tive loads up to the following maximum are safe:
V
S
I
LIM
= 5A I
LIM
= 10A I
LIM
= 5A I
LIM
= 10A
45V 200 F 150 F 8mH 2.8mH
40V 400 F 200 F 11mH 4.3mH
35V 800 F 400 F 20mH 5.0mH
30V 1600 F 800 F 35mH 6.2mH
25V 5.0mF 2.5mF 50mH 15mH
20V 10mF 5.0mF 400mH 20mH
15V 20mF 10mF ** 100mH
* If the inductive load is driven near steady state conditions,
supply rail with I
LIM
= 10A or 15V below the supply rail with
I
LIM
= 5A while the amplifer is current limiting, the inductor
should be capacitively coupled or the current limit must be
lowered to meet SOA criteria.
** Second breakdown effect imposes no limitation but thermal
limitations must still be observed.
load and short circuits to the supply rail or shorts to common
if the current limits are set as follows at T
C
=85C.
SHORT TO V
S
SHORT TO
V
S
45V 0.1A 1.3A
40V 0.2A 1.5A
35V 0.3A 1.6A
30V 0.5A 2.0A
25V 1.2A 2.4A
20V 1.5A 3.0A
15V 2.0A 4.0A
However, for protection against sustained, high energy fyback,
T
C
=
1
2
5
C
T
C
=
8
5
C
S
t
e
a
d
y

S
t
a
t
e
t

=

5
m
s
t

=

1
m
s
t

=

0
.
5
m
s
10 20 30
S
V
O
(V)
I
N
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S

(
A
)
40 50 60 70 90 80
.1
.2
.3
.4
.6
.8
1.0
2.0
3.0
4.0
6.0
8.0
10
1.5
T
C
=
2
5
C
25 15
PA61M/883
PA61MU 353
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
P r o d u c t I n n o v a t i o n F r o m PA61M/883
Q
25C 32V V
IN
= 0, A
V
= 100 10 mA
OS
25C 32V V
IN
= 0, A
V
= 100 6 mV
OS
25C 10V V
IN
= 0, A
V
= 100 10.4 mV
OS
25C 45V V
IN
= 0, A
V
= 100 8.6 mV
B
25C 32V V
IN
= 0 30 nA
B
25C 32V V
IN
= 0 30 nA
OS
25C 32V V
IN
= 0 30 nA
Q
55C 32V V
IN
= 0, A
V
= 100 10 mA
OS
55C 32V V
IN
= 0, A
V
= 100 11.2 mV
OS
55C 10V V
IN
= 0, A
V
= 100 15.6 mV
OS
55C 45V V
IN
= 0, A
V
= 100 13.8 mV
B
55C 32V V
IN
= 0 115 nA
B
55C 32V V
IN
= 0 115 nA
OS
55C 32V V
IN
= 0 115 nA
Q
125C 32V V
IN
= 0, A
V
= 100 15 mA
OS
125C 32V V
IN
= 0, A
V
= 100 12.5 mV
OS
125C 10V V
IN
= 0, A
V
= 100 16.9 mV
OS
125C 45V V
IN
= 0, A
V
= 100 15.1 mV
B
125C 32V V
IN
= 0 70 nA
B
125C 32V V
IN
= 0 70 nA
OS
125C 32V V
IN
= 0 70 nA
4 Output Voltage, I
O
= 10A V
O
25C 17V R
L
= 1 10 V
4 Output Voltage, I
O
= 80mA V
O
25C 45V R
L
= 500 40 V
4 Output Voltage, I
O
= 4A V
O
25C 30V R
L
= 6 24 V
4 Current Limits I
CL
25C 15V R
L
= 6, R
CL
= 1 .56 .88 A
4 Stability/Noise E
N
25C 32V R
L
= 500, A
V
= 1, C
L
= 10nF 1 mV
L
= 500 1 10 V/s
4 Open Loop Gain A
OL
25C 32V R
L
= 500, F = 10Hz 96 dB
L
= 500, F = DC, V
CM
= 9V 74 dB
6 Output Voltage, I
O
= 10A V
O
55C 17V R
L
= 1 10 V
6 Output Voltage, I
O
= 80mA V
O
55C 45V R
L
= 500 40 V
6 Output Voltage, I
O
= 4A V
O
55C 30V R
L
= 6 24 V
6 Stability/Noise E
N
55C 32V R
L
= 500, A
V
= 1, C
L
= 10nF 1 mV
L
= 500 1 10 V/s
6 Open Loop Gain A
OL
55C 32V R
L
= 500, F = 10Hz 96 dB
6 CommonMode Rejection CMR 55C 15V R
L
= 500, F = DC, V
CM
= 9V 74 dB
5 Output Voltage, I
O
= 8A V
O
125C 15V R
L
= 1 8 V
5 Output Voltage, I
O
= 80mA V
O
125C 45V R
L
= 500 40 V
5 Output Voltage, I
O
= 4A V
O
125C 30V R
L
= 6 24 V
5 Stability/Noise E
N
125C 32V R
L
= 500, A
V
= 1, C
L
= 10nF 1 mV
L
= 500 1 10 V/s
5 Open Loop Gain A
OL
125C 32V R
L
= 500, F = 10Hz 96 dB
L
= 500, F = DC, V
CM
= 9V 74 dB
+15V
15V
100
1
U.U.T.
4
3
5
6
2
1
100
20
1
**
*
*
BURN IN CIRCUIT
due to poor high frequency characteristics of
burn in board.
temperature = 125C.
SEP 2009
APEX PA61MUREVG
PA69
354 PA69U
PA69
DESCRIPTION
The PA69 is a high voltage, high speed, low idle cur-
rent op-amp capable of delivering up to 100mA peak
output current. Due to the dynamic biasing of the input
stage, it can achieve slew rates over 350V/s, while
only consuming less than 1mA of idle current. External
phase compensation allows great fexibility for the user
to optimize bandwidth and stability.
The output stage is protected with user selected cur-
rent limit resistor. For the selection of this current limit-
ing resistor, pay close attention to the SOA curves for
each package type. Proper heatsinking is required for
maximum reliability.
FEATURES
A Unique (Patent Pending) Technique for Very
Low Quiescent Current
Over 350 V/s Slew Rate
Wide Supply Voltage
Single Supply: 20V To 200V
Split Supplies: 10V To 100V
Output Current 75mA Cont.; 100mA Pk
Up to 23 Watt Dissipation Capability
Over 200 kHz Power Bandwidth
APPLICATIONS
Piezoelectric Positioning and Actuation
12Pin SIP
PACKAGE STYLE EU
LEAD FORM EW
ACTIVE LOAD
ACTIVE LOAD
CLASS AB INPUT STAGE
BUFFER
CURRENT
LIMIT
VOUT
VOUT+
VOUT
V+
V
PA69 P r o d u c t I n n o v a t i o n F r o m
BLOCK DIAGRAM
JUL 2009
APEX PA69UREVB
PA69EU
12-pin SIP
I
LIM
V
OUT
C
C
- -V
S
-IN +IN C
R
+ C
C
+ +V
S
C
R
-
+V
S
C
C
+
R
C
+
R
F
R
IN
R
C
-
TO LOAD
_V
S
R
LIM
1 12 11 10 9 8 7 6 5 4 3 2
C
C
-
33pF
PA69
PA69U 355
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SUPPLY VOLTAGE, +V
S
to V
S
200 V
OUTPUT CURRENT, peak (200ms), within SOA 200 mA
INPUT VOLTAGE, differential 15 15 V
S
+V
S
V
INPUT
OFFSET VOLTAGE -25 8 25 mV
0 to 125C (Case Temperature)
-63 V/C
BIAS CURRENT, initial 8.5 200 pA
8

S
- 2 V
S
+ 5.5 V
NOISE 700KHz 418 V RMS
NOISE, V
O
NOISE 500 nV/Hz
GAIN
OPEN LOOP @ 1Hz 89 120 dB
GAIN BANDWIDTH PRODUCT @ 1MHz 1 MHz
OUTPUT
VOLTAGE SWING I
O
= 10mA |V
S
| - 2 V
VOLTAGE SWING I
O
= 75mA |V
S
| - 8.6 |V
S
| - 12 V
SLEW RATE Package Tab connected to GND 100 350 V/S
SETTLING TIME, to 0.1% 5V Step (No Compensation) 1 S
P-P
+V
S
= 160V, V
S
= -160V 200 kHz
OUTPUT RESISTANCE, No load R
CL
= 6.2 44
POWER SUPPLY
VOLTAGE 10 50 100 V
CURRENT, quiescent (Note 5) 100V Supply 0.2 0.7 2.5 mA
SPECIFICATIONS
PA69
356 PA69U
THERMAL
RESISTANCE, DC, junction to air Full temperature range 12.21 C/W
C
= 25C, DC input specifcations are value given, power supply voltage
is typical rating.
3. +V
S
and V
S
denote the positive and negative supply voltages of the output stage.
4. Rating applies if output current alternates between both output transistors at a rate faster than 60Hz.
5. Supply current increases with signal frequency. See graph on page 4.
TYPICAL APPLICATION CIRCUIT
The PA69 is ideally suited for driving continuous drop
ink jet printers, in both piezo actuation and defection
applications. The high voltage of the amplifer creates
an electrostatic feld on the defection plates to con-
trol the position of the ink droplets. The rate at which
droplets can be printed is directly related to the rate
at which the amplifer can drive the plate to a different
electrostatic feld strength.
100K
0-5V
DAC
1.6K
-15V
R
C
C
C
R
CL
C
C
R
C
+335V
DEFLECTION
PLATE INK
DROPLETS
PA69
PA69U 357
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
-35
-25
-15
-5
5
15
25
35
G
A
I
N
,
d
B
C
C
=0pF
C
C
=1pF
C
C
=2.2pF
C
C
=10pF
C
C
=22pF
C
C
=5pF
O
= 50V
P-P
A
V
=+26
R
BIAS
=100K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
V
S
=50V
FREQUENCY, KHz
10 1K 100 10K
-35
-25
-15
-5
5
15
25
35
G
A
I
N
,
d
B
C
C
=0pF
C
C
=1pF
C
C
=2.2pF
C
C
=10pF
C
C
=22pF
C
C
=5pF
O
= 5V
P-P
A
V
=+26
R
BIAS
=100K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
V
S
=50V
FREQUENCY, KHz
10 1K 100 10K
FREQUENCY, KHz
10 1K 100
-35
-25
-15
-5
5
15
25
35
45
G
A
I
N
,
d
B
C
C
=0pF
C
C
=1pF
C
C
=2.2pF
C
C
=10pF
C
C
=22pF
C
C
=5pF
O
= 500mV
P-P
A
V
=+26
R
BIAS
=100K
R
C
=3.3K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
V
S
=50V
10K
-25
-15
-5
5
15
25
35
45
G
A
I
N
,

d
B
500 mV
P-P
50 V
P-P
5 V
P-P
A
V
=+51
R
BIAS
=100K
R
C
=OPEN
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=50V
FREQUENCY, KHz
10 1K 100 10K
-90
-60
-30
0
30
60
90
120
150
180
P
H
A
S
E
,

C
S
=68pF
P
IN
=-40dBm
R
BIAS
=100K
R
S
= 48.7
V
S
=50V
FREQUENCY, KHz
100 1000 10 1
R
C
=OPEN, C
C
=0pF
R
C
=3.3K, C
C
=1pF
R
C
=3.3K, C
C
=2.2pF
R
C
=3.3K, C
C
=5pF
R
C
=3.3K, C
C
=10pF
R
C
=3.3K, C
C
=22pF
O
= 250mV
P-P
-90
-60
-30
0
30
60
90
120
150
180
P
H
A
S
E
,

C
S
=68pF
P
IN
=-40dBm
R
BIAS
=OPEN
R
S
= 48.7
FREQUENCY, KHz
100 1000 10 1
R
C
=OPEN, C
C
=0pF
R
C
=3.3K, C
C
=1pF
R
C
=3.3K, C
C
=2.2pF
R
C
=3.3K, C
C
=5pF
R
C
=3.3K, C
C
=10pF
R
C
=3.3K, C
C
=22pF
-20
0
20
40
60
80
100
FREQUENCY, KHz
100
G
A
I
N
,

D
b
C
S
=68pF
P
IN
=-40dBm
R
BIAS
=OPEN
R
S
= 48.7
V
S
=50V
1000 10 1
R
C
=OPEN, C
C
=0pF
R
C
=3.3K, C
C
=1pF
R
C
=3.3K, C
C
=2.2pF
R
C
=3.3K, C
C
=5pF
R
C
=3.3K, C
C
=10pF
R
C
=3.3K, C
C
=22pF
PA69
358 PA69U
C
AND R
C
-150
-120
-90
-60
-30
0
30
60
90
120
150
-2.4
-1.8
-1.2
-0.6
0
0.6
1.2
1.8
2.4
3.0
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
I
N
P
U
T

V
O
L
T
A
G
E
,

V
TIME, s
0 1 2 3 4 5 6 -1 -2 7 8
A
V
=+51
C
C
=68pF
C
L
=330pF
R
C
= 48
R
F
=75K
R
G
=1.5K
R
L
=OPEN
V
S
=150V
Out - 0pF
Out - 1pF & 3.3K
Out - 5pF & 3.3K
input
-3.0
2V
P-P
input2
TIME, s
-30
-20
-10
0
10
20
30
-1.5
-1
-0.5
0
0.5
1
1.5
TRANSIENT RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
I
N
P
U
T

V
O
L
T
A
G
E
,

V
A
V
=+26
C
C
=2.2pF
C
L
=8pF
R
C
=3.3K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
-2 0 2 4 6 8 10 12 -4
1V
P-P
input1
-15
-10
-5
0
5
10
15
TIME, s
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
I
N
P
U
T

V
O
L
T
A
G
E
,

V
-2 0 2 4 6 8 10 12 -4
TRANSIENT RESPONSE
A
V
=+26
C
C
=2.2pF
C
L
=8pF
R
C
=3.3K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
SR+/SR- (25% - 75%)
SR+
SR-
A
V
=+26
C
L
=8pF
R
F
=35.6K
R
G
=1.5K
R
L
=50K
V
S
=150V
0 2 4 6 8 10 12 14 16
0
200
400
600
800
1000
S
R
,

V
/
s
SR+/SR- (25% -75%)
SR+
SR-
A
V
=+51
C
L
=8pF
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
0 2 4 6 8 10 12 14 16
0
200
400
600
800
1000
S
R
,

V
/
s
SR+/SR- (25% - 75%)
0
200
400
600
800
1000
SR+
SR-
S
R
,

V
/
s
A
V
=+101
C
L
=8pF
R
F
=25K
R
G
= 250
R
L
=50K
V
S
=150V
0 2 4 6 8 10 12 14 16
PA69
PA69U 359
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
0
5
10
15
20
25
30
1000 100 10
V
IN
=3V
P
A
V
=+51
C
L
=8pF
C
S
=68pF
R
F
=75K
R
G
=1.5K
R
L
=50K
R
S
= 48.7
V
S
=150V
I
S
,

m
A
V
IN
=6V
P
I
S
vs. V
IN
0
2
4
6
8
10
12
14
16
18
V
IN
, V
P-P
(100KHz sine wave)
A
V
=+51
C
L
=8pF
C
S
=68pF
R
F
=75K
R
G
=1.5K
R
L
=50K
R
S
= 48.7
V
S
=150V
I
S
,

m
A
1 9 8 7 6 5 4 3 2 0
PULSE RESPONSE
-0.05
0
0.05
0.1
0.15
0.2
TIME,s
I
S
,

A
6 0 -1
A
V
=+51
C
L
=8pF
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
5 4 3 2 1
TIME, s
0 30 10 8 6 4 2 -2 -6 -4 28 26 24 22 20 18 16 14 12
A
V
=-50
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
300pF, 1V
P-P
200pF, 1V
P-P
100pF, 1V
P-P
-80
-60
-40
-20
0
20
40
60
80
100
120
140
O
U
T
P
U
T
,

V
-80
-60
-40
-20
0
20
40
60
80
100
120
140
O
U
T
P
U
T
,

V
300pF, 2V
P-P
200pF, 2V
P-P
100pF, 2V
P-P
A
V
=-50
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
C
L
=8pF
TIME, s
0 30 10 8 6 4 2 -2 -6 -4 28 26 24 22 20 18 16 14 12
A
V
=-50
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
-80
-60
-40
-20
0
20
40
60
80
100
120
140
TIME, s
O
U
T
P
U
T
,

V
300pf, 3V
P-P
200pf, 3V
P-P
100pf, 3V
P-P
0 30 10 8 6 4 2 -2 -6 -4 28 26 24 22 20 18 16 14 12
SR+/SR- (25%-75%)
0
200
400
600
800
1000
1200
1400
1600
V
/
s
SR+(A
V
=-50)
SR-(A
V
=-50)
SR+(A
V
=+51)
SR-(A
V
=+51)
R
F
=75K
R
G
=1.5K
R
L
=50K
C
L
=8pF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SR+/SR- (25%-75%)
R
F
=75K
R
G
=1.5K
R
L
=50K
C
L
=8pF
0
200
400
600
800
1000
1200
S
R
+
/
S
R
-

V
/
s
SR+(A
V
=-25)
SR-(A
V
=-25)
SR+(A
V
=+26)
SR-(A
V
=+26)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PA69
360 PA69U
GENERAL
Please read Application note 1 General operating considerations which covers stability, power supplies, heat
tools that help automate tasks such as calculations for stability, internal power dissipation, and current limit. There
you will also fnd a complete application notes library, technical seminar workbook, and evaluation kits.
THEORY OF OPERATION
ceramic capacitors of 0.1F or more should be placed as close as possible to the amplifer supply pins. The in-
Current can be injected into the output stage by adding a resistor, Rbias, between C
C
- and V
S
+. The size of Rbias
will depend upon the application but 500A of added bias current shows signifcant improvement in the small signal
phase plots. Adding this resistor has little to no impact on small signal gain or large signal performance as under
these conditions the current in the input stage is elevated over its idle value. It should also be noted that connecting
a resistor to the upper supply only injects a fxed current and if the upper supply is fxed and well bypassed. If the
application includes variable or adjustable supplies, a current source diode could also be used. These two terminal
components combine a JFET and resistor connected within the package to behave like a current source.
plication. Unlike the Rbias technique, external phase compensation maintains the low idle current but does affect
networks are required. The compensation capacitor C
C
must be rated for a working voltage of the full operating
PA69
PA69U 361
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
supply voltage (+V
S
to V
S
temperature..
The PA69 requires an external 33pF capacitor between C
C
- and Vs to prevent oscillations in the falling edge of the
S
to V
S
).
slew rate. As the amplitude of the input amplitude increases from 1V
P-P
to 15V
P-P
, the slew rate increases from 50V/
s to well over 350V/s.
The output becomes clipped by the supply rails and the amplifer is no longer operating in a closed loop fashion. The
rise and fall times become faster as the dynamic current sources are providing maximum current for slewing. The
result of this amplifer architecture is that it slews fast, but allows good control of overshoot for large input signals.
This can be seen clearly in the large signal Transient Response plots.
The MOSFET output stage of the PA69 is not limited by second breakdown
considerations as in bipolar output stages. Only thermal considerations
of the package and current handling capabilities limit the Safe Operating
Area. The SOA plots include power dissipation limitations which are de-
pendent upon case temperature. Keep in mind that the dynamic current
sources which drive high slew rates can increase the operating tempera-
ture of the amplifer during periods of repeated slewing. The plot of supply
current V
S
. input signal amplitude for a 100 kHz signal provides an indica-
tion of the supply current with repeated slewing conditions. This applica-
tion dependent condition must be considered carefully.
The output stage is self-protected against transient fyback by the parasitic
body diodes of the output stage. However, for protection against sustained
high energy fyback, external, fast recovery diodes must be used.
CURRENT LIMIT
For proper operation, the current limit resistor, Rlim, must be connected as shown in the external connections
diagram. For maximum reliability and protection, the largest resistor value should be used. The minimum practical
value for R
LIM
is about 12. However, refer to the SOA curves for each package type to assist in selecting the opti-
mum value for R
LIM
in the intended application.
to GND or one of the supply rails, but an AC connection through a 1uF capacitor to GND is also suffcient if a DC
C
/ C
C
compensation networks close to the amplifer compensation pins. Long
loops in these paths pick up noise and increase the likelihood of L
C
interactions and oscillations.
ELECTROSTATIC DISCHARGE
Like many high performance MOSFET amplifers, the PA69 very sensitive to damage due to electrostatic discharge
(ESD). Failure to follow proper ESD handling procedures could have results ranging from reduced operating per-
formance to catastrophic damage. Minimum proper handling includes the use of grounded wrist or shoe straps,
grounded work surfaces. Ionizers directed at the work in progress can neutralize the charge build up in the work
environment and are strongly recommended.
PA74/76 PA74A/76A
362 PA74-76U
P r o d u c t I n n o v a t i o n F r o m PA74, PA76, PA74A, PA76A
Power Dual Operational Amplifiers
PA74/PA76 PA74A/76A
P r o d u c t
I n n o v a t i o n
F r o m
COMMAND
INPUT
0/10V
A M B
R2
9K
R3
10K
R4
10K
R5
10K
R6
10K
R1
5K
1/2 PA74 1/2 PA74
+28V
+
_
+
_
+28V
FEATURES
LOW COST
WIDE COMMON MODE RANGE
Includes negative supply
WIDE SUPPLY VOLTAGE RANGE
Single supply: 5V to 40V
HIGH EFFICIENCY |Vs2.2V| at 2.5A typ
HIGH OUTPUT CURRENT 3A
LOW DISTORTION
APPLICATIONS
HALF & FULL BRIDGE MOTOR DRIVERS
STEREO 30W RMS per channel
BRIDGE 60W RMS per package
5V Peripherals, 12V Automotive
28V Avionic
DESCRIPTION
The amplifer design consists of dual monolithic input and output
stages to achieve the desired input and output characteristics
of the PA74 and PA76. The input stage utilizes a dual power op
amp on a single chip monolithic that drives the output stages.
The output stages are confgured in a non inverting unity gain
buffer confguration. The output stages of the amplifer are also
compensated for stability. The PA74 and PA76 dual amplifers are
designed with both monolithic and hybrid technologies providing
a cost effective solution for applications requiring multiple ampli-
fers per board or bridge mode confgurations. Both amplifers
are internally compensated but are not recommended for use
as unity gain followers.
This dual hybrid circuit utilizes a beryllia (BeO) substrate, thick
flm resistors, ceramic capacitors and monolithic amplifers to
maximize reliability and power handling capability, minimize size
and give top performance. Ultrasonically bonded aluminum wires
provide reliable interconnections at all operating temperatures.
The 8-Pin TO-3 package is hermetically sealed and electrically
isolated. The use of compressible isolation washers voids the
warranty.
EQUIVALENT SCHEMATIC ONE CHANNEL
A
1
2
3
4
5
6
7
8
+V
S
IN, A
+IN, A
+IN, B
IN, B
V
S
OUT, B
OUT, A
B
A B
1
2
3
4
5
6
7
8
+V
S
+IN, A
IN, A
OUT, A
V
S
+IN, B
IN, B
OUT, B
+
+
TYPICAL APPLICATION
R1 and R2 set up amplifer A in a non-inverting gain of 2.8.
Amp B is set up as a unity gain inverter driven from the output
of amp A. Note that amp B inverts signals about the reference
node, which is set at mid-supply (14V) by R5 and R6. When
the command input is 5V, the output of amp A is 14V. Since
this is equal to the reference node voltage, the output of amp
B is also 14V, resulting in 0V across the motor. Inputs more
positive than 5V result in motor current fow from left to right
(see Figure 1). Inputs less positive than 5V drive the motor in
the opposite direction.
The amplifers are especially well-suited for this application.
The extended common mode range allows command inputs
as low as 0V. Its superior output swing abilities let it drive
within 2V of supply at an output current of 2A. This means
that a command input that ranges from 0.714V to 9.286V will
drive a 24V motor from full scale CCW to full scale CW at up
to 2A. A single power op amp with an output swing capability
of Vs 6 would require 30V supplies and would be required to
swing 48V p-p at twice the speed to deliver an equivalent drive.
EXTERNAL CONNECTIONS (TOP VIEWS)
PA74 PA76
FIGURE 1: BIDIRECTIONAL
SPEED CONTROL FROM A
SINGLE SUPPLY.
8-PIN TO-3
PACKAGE STYLE CE
+V
S
-IN
-V
S
+IN
I BIAS
MONITOR
THERMAL
PROTECT
CURRENT
GAIN
CURRENT
GAIN
OUT
MAY 2009
APEX PA74-76UREVE
PA74/76 PA74A/76A
PA74-76U 363
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
OUTPUT CURRENT SOA
POWER DISSIPATION, internal (per amplifer) 36W
POWER DISSIPATION, internal (both amplifers) 60W
INPUT VOLTAGE, differential V
S
INPUT VOLTAGE, common mode +V
S
, -V
S
0.5V
JUNCTION TEMPERATURE, max
1
150C
TEMPERATURE, pin solder10 sec max 300C
TEMPERATURE RANGE, storage 65C to 150C
OPERATING TEMPERATURE RANGE, case 55C to 125C
SPECIFICATIONS
PA74/76 PA74A/PA76A
2
INPUT
OFFSET VOLTAGE, initial 1.5 10 .5 7 mV
OFFSET VOLTAGE, vs. temperature Full temperature range 20 10 V/C
BIAS CURRENT, initial 100 500 * 250 nA
COMMON MODE RANGE Full temperature range V
S
+V
S
1.3 * * V
COMMON MODE REJECTION, DC Full temperature range 60 70 * * dB
POWER SUPPLY REJECTION Full temperature range 60 90 * * dB
OUT
= 1A, F = 1kHz 50 70 * * dB
S
= 100, f = 1 to 100KHz

GAIN
OPEN LOOP GAIN Full temperature range 89 100 * * * dB
GAIN BANDWIDTH PRODUCT A
V
= 40dB 0.9 1.4 * * MHz
POWER BANDWIDTH V
O(P-P)
= 28V 13.6 * kHz
OUTPUT
CURRENT, peak 2.5 3 A
SLEW RATE 0.5 1.4 * * V/s
VOLTAGE SWING Full temp. range, I
O
= 100mA |V
S
| 1.1 |V
S
| 0.9 * * V
VOLTAGE SWING Full temp. range, I
O
= 1A |V
S
| 2.0 |V
S
| 1.7 * * V
VOLTAGE SWING I
O
= 2.5A (PA74, 76) |V
S
| 3.5 |V
S
| 2.9 * * V
VOLTAGE SWING I
O
= 3.0A (PA74A, PA76A) |V
S
| 4.0 |V
S
| 3.3 V
POWER SUPPLY
VOLTAGE, VSS
3
30 40 * * * V
THERMAL
DC, single amplifer 3.2 3.5 * * C/W
DC, both amplifers
4
1.9 2.1 * * C/W
AC, single amplifer 2.4 2.6 * * C/W
AC, both amplifers
4
1.4 1.6 * * C/W
RESISTANCE, junction to air 30 * * C/W
TEMPERATURE RANGE, case Meets full range specifcations 25 85 25 85 C
NOTES: * The specifcation of PA74A/PA76A is identical to the specifcation for PA74/PA76 in applicable column to the left.
achieve high MTTF.
2. Unless otherwise noted, the following conditions apply: VS = 15V, TC = 25C.
3. +VS and VS denote the positive and negative supply rail respectively. VSS denotes the total rail-to-rail supply voltage.
4. Rating applies when power dissipation is equal in the two amplifers.
CAUTION
PA74/76 PA74A/76A
364 PA74-76U
-80 140 100 60 20 -20
0.4
1.2
1.0
0.8
0.6
2.0
1.8
1.5
1.4
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
CASE TEMPERATURE, T
C
(C)
NORMALIZED QUIESCENT CURRENT
vs. CASE TEMPERATURE
vs. SUPPLY VOTAGE
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
SUPPLY VOLTAGE, V
S
(V)
20 0 15 10 5
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
OUTPUT CURRENT, I
O
(A)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
D
R
O
P

(
V
)
0.0 3.5 0.5 1.0 1.5 2.0 2.5 3.0
1.5
1.0
0.5
0.0
2.0
2.5
3.0
3.5
4.0
PULSE RESPONSE
TIME, t (s)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
400 1.4K 1.2K 1.0K 800 600 200 0
-10
15
10
5
0
-5
-15
+V
S
= +15V
A
V
= +1
V
IN
= 10Vp
-V
S
= -15V
R
L
= 10
f
IN
= 1KHz
PULSE RESPONSE
TIME, t (s)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
20 70 60 50 40 30 10 0
-10
15
10
5
0
-5
-15
+V
S
= +15V
A
V
= +1
V
IN
= 10Vp
-V
S
= -15V
R
L
= 10
f
IN
= 20KHz
0 40 80 120 160 -40 -80
1.0
0.9
0.8
0.7
0.6
1.1
1.2
1.3
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
TEMPERATURE, (C)
I
B
FREQUENCY, f (Hz)
80
120
160
200
240
280
1K 10K 100K 1M 10M
P
H
A
S
E
,

)
PHASE vs. FREQUENCY
FREQUENCY, f (Hz)
60
40
20
0
-20
-40
1K 10K 100K 1M 10M
G
A
I
N
,

A

(
d
B
)
VOLTAGE GAIN vs. FREQUENCY
80
V
OS
N
O
R
M
A
L
I
Z
E
D

O
F
F
S
E
T

V
O
L
T
A
G
E
,

V
O
S

(
X
)
120 80 40 0 -40
-4
8
4
0
TEMPERATURE, (C)
PA74/76 PA74A/76A
PA74-76U 365
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
ations" which covers stability, supplies, heatsinking, mounting,
selection; Apex Precision Power's complete Application Notes
library; Technical Seminar Workbook; and Evaluation Kits.
All monolithic power op amps use output stage topologies
that present special stability problems. This is primarily due to
non-complementary (both devices are NPN) output stages with
a mismatch in gain and phase response for different polarities
of output current. It is difficult for the opamp manufacturer to
optimize compensation for all operating conditions.
Thermal grease or a Apex Precision Power TW03 thermal
washer, RCS = .1 to .2C/W, is the only recommended interface
for the PA74/76. Internal power dissipation increases directly
with frequency therefore it is critical to sufficiently heat sink
the PA74 and PA76. Even unloaded the PA74 and PA76 can
dissipate up to 3 watts while running at higher frequencies.
SOA
TWO AMPLIFIERS LOADED
ONE AMPLIFIER
LOADED
100 1.0 10
0.1
1.0
10
S
- V
O
(V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

o
r

-
V
S
,

(
A
)
DC, T
C
= 85C
DC, T
C
= 25C
PARALLEL CONFIGURATION CONSIDERATIONS
LOSSES
The PA74 and PA76 utilize a parallel confguration to achieve
the desired current output requirements. The parallel confgura-
tion inherently creates internal losses due to circulating currents.
The circulating currents generate power losses through the
current sharing resistors when delivering current to the load.
SUPPLY CURRENT
The parallel confguration used in the PA74 and PA76 also
generates supply currents while high voltage sign waves are
seen at the output. Listed below are the supply currents expected
while running at a particular frequency and when VO 15Vpp,
note that the outputs are not loaded.
Frequency Supply Current
100Hz 18mA
1KHz 20mA
5KHz 32mA
10KHz 50mA
15KHz 75mA
SATURATION OPERATION
The parallel confguration used in the PA74 and PA76 is
sensitive to operation in the saturation region. The PA74 and
PA76 may exhibit large peak currents; this is mainly due to
thermal protection limitations.
0
10
20
30
40
50
60
70
POWER DERATING
0 25 50 75 100 125
TWO AMPLIFIERS LOADED
ONE AMPLIFIER LOADED
CASE TEMPERATURE, T
C
(C)
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
PA74M
366 PA74MU
PA74M
1 Quiesent Current I
Q
25C 15 V
IN
= 0, A
V
= 100 30 mA
OS
25C 2.5 V
IN
= 0, A
V
= 100 10 mV
OS
25C 15 V
IN
= 0, A
V
= 100 10 mV
OS
25C 20 V
IN
= 0, A
V
= 100 14 mV
1 Input Bias Current + IN + I
B
25C 15 V
IN
= 0 1000 nA
1 Input Bias Current IN I
B
25C 15 V
IN
= 0 1000 nA
OS
25C 15 V
IN
= 0 500 nA
Q
55C 15 V
IN
= 0, A
V
= 100 30 mA
OS
55C 2.5 V
IN
= 0, A
V
= 100 14 mV
OS
55C 15 V
IN
= 0, A
V
= 100 14 mV
OS
55C 20 V
IN
= 0, A
V
= 100 18 mV
B
55C 15 V
IN
= 0 1000 nA
B
55C 15 V
IN
= 0 1000 nA
OS
55C 15 V
IN
= 0 500 nA
Q
125C 15 V
IN
= 0, A
V
= 100 40 mA
OS
125C 2.5 V
IN
= 0, A
V
= 100 15 mV
OS
125C 15 V
IN
= 0, A
V
= 100 15 mV
OS
125C 20 V
IN
= 0, A
V
= 100 19 mV
B
125C 15 V
IN
= 0 1000 nA
B
125C 15 V
IN
= 0 1000 nA
OS
125C 15 V
IN
= 0 500 nA
4 Output Voltage I
O
= 2A V
O
25C 9.5 R
L
= 3 6.0 V
4 Output Voltage I
O
= 100mA V
O
25C 11 R
L
= 100 9.9 V
4 Output Voltage I
O
= 1A V
O
25C 4.8 R
L
= 3 2.8 V
4 Stability/Noise E
N
25C 15 R
L
= 500, A
V
= 1 C
L
= 1.5nF 1.0 mV
4 Crosstalk XTLK 25C 15 R
L
= 3 50 dB
4 Slew Rate SR 25C 15 R
L
= 500 .5 V/S
4 Open Loop Gain A
OL
25C 15 R
L
= 500, F =10Hz 75 dB
4 Common-mode Rejection CMR 25C 17 R
L
= 500, V
CM
= 14V 60 dB
6 Output Voltage I
O
= 2A V
O
55C 9.5 R
L
= 3 6.0 V
6 Output Voltage I
O
= 100mA V
O
55C 11 R
L
= 100 9.9 V
6 Output Voltage I
O
= 1A V
O
55C 4.8 R
L
= 3 2.8 V
6 Stability/Noise E
N
55C 15 R
L
= 500, A
V
= 1, C
L
= 1.5nF 1.0 mV
L
= 500 .5 V/S
6 Open Loop Gain A
OL
55C 15 R
L
= 500, F = 10Hz 75 dB
L
= 500, V
CM
= 14V 60 dB
5 Output Voltage I
O
= 1A V
O
125C 4.8 R
L
= 3 2.8 V
5 Output Voltage I
O
= 100mA V
O
125C 11 R
L
= 100 9.9 V
5 Output Voltage I
O
= 750mA V
O
125C 4.0 R
L
= 3 2.25 V
5 Stability/Noise E
N
125C 15 R
L
= 500, A
V
= 1, C
L
= 1.5nF 1.0 mV
L
= 500 .5 V/S
5 Open Loop Gain A
OL
125C 15 R
L
= 500, F = 10Hz 75 dB
L
= 500, V
CM
= 14V 60 dB
burn in board.
temperature = 125C.
BURN IN CIRCUIT
**
A B
10K
10K
*
*
4
3 2
U.U.T.
1
10K
10K
6
5
*
*
+15V
15V
200
200
8
7
PA74M P r o d u c t I n n o v a t i o n F r o m
SEP 2009
APEX PA74MUREVB
PA75
PA75U 367
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA75
Dual Power Operational Amplifiers
PARALLEL CONNECTION
yields a single 2.5A amplifier
R
I
R
F
R
S
R
S
1/2
PA75
1/2
PA75
A
B
V
IN
V
O
+V
S
V
S
I 2I
I
LOAD
7 PIN DDPAK
PACKAGE STYLE CC
7 PIN TO220 7 PIN TO220
STAGGERED LEADS PACKAGE STYLE CD
PACKAGE STYLE CX
TYPICAL APPLICATION
Ref: APPLICATION NOTES 8, 20, 26
SUB
A B
SUB
A B
SUB
A B
PA75CC
PA75CD PA75CX
O
U
T

A
M
P

A
-
I
N

A
M
P

A
+
I
N

A
M
P

A
-
V
S
+
I
N

A
M
P

B
+
V
S
O
U
T

A
M
P

B
O
U
T

A
M
P

A
-
I
N

A
M
P

A
+
I
N

A
M
P

A
-
V
S
+
I
N

A
M
P

B
+
V
S
O
U
T

A
M
P

B
O
U
T

A
M
P

A
-
I
N

A
M
P

A
+
I
N

A
M
P

A
-
V
S
+
I
N

A
M
P

B
+
V
S
O
U
T

A
M
P

B
Combining the power op amp (master channel A) and the
unity gain buffer (slave channel B) in a parallel connection
yields a single 2.5A amplifer. RI and RF can set up channel A
for the required gain for the overall circuit. Small values of R
S

(sense resistors) are used on the outputs to improve current
sharing characteristics. The master amplifer can be confgured
in inverting or non-inverting gain confgurations.
EXTERNAL
CONNECTIONS
FEATURES
RoHS COMPLIANT
LOW COST
HIGH OUTPUT CURRENT - 2.5A (Combined)
WIDE COMMON MODE RANGE Includes negative supply
WIDE SUPPLY VOLTAGE RANGE Single supply: 5V to 40V
VERY LOW DISTORTION
APPLICATIONS
5V Peripherals, 12V Automotive, 28V Avionic
PACKAGING OPTIONS
7 TO-220 Plastic Package (PA75CD)
7 TO-220 with Staggered Lead Form (PA75CX)
7 DDPAK Surface Mount Package (PA75CC)
DESCRIPTION
The amplifer design consists of dual power op amp on a single
monolithic die. Side B of the dual monolithic is confgured as a
unity gain buffer to increase the current capability of the master
side A. The use of two PA75 amplifers provides a cost-effective
solution to applications where multiple amplifers are required or
a bridge confguration is needed. Very low harmonic distortion
of .02% THD and low I
Q
makes the PA75 a good solution for
power audio applications.
The PA75 is available in three standard package designs. The
surface mount version of the PA75, the PA75CC, is an industry
standard non-hermetic plastic 7-pin DDPAK. The through hole
version of the PA75, the PA75CD and PA75CX, are industry
standard non-hermetic plastic 7-pin TO-220 packages. The
PA75CX is staggered lead formed and offers standard 100 mil
spacing. This allows for easier PC board layout. (Please refer to
the CX lead form package drawing for dimension of the PA75CX).
The monolithic amplifer is directly attached to the metal tabs
of the PA75CC, PA75CD, and PA75CX. The metal tabs of the
packages are directly tied to -Vs.
EQUIVALENT SCHEMATIC ONE CHANNEL
OUT
+Vs
-IN +IN
-Vs
I BIAS
MONITOR
THERMAL
PROTECT
CHANNEL A
CHANNEL B
MAY 2009
APEX PA75UREVF
PA75
368 PA75U
2
MIN TYP MAX UNITS
INPUT
OFFSET VOLTAGE, vs. temperature Full temperature range 20 V/C
COMMON MODE RANGE Full temperature range V
S
+V
S
1.3 V
COMMON MODE REJECTION, DC Full temperature range 60 90 dB
POWER SUPPLY REJECTION Full temperature range 60 90 dB
OUT
= 500mA, = 1kHz 50 68 dB
S
= 100, = 1 to 100kHz 22 nV/Hz
GAIN
OPEN LOOP GAIN Full temperature range 89 100 dB
GAIN BANDWIDTH PRODUCT A
V
= 40dB 0.9 1.4 MHz
PHASE MARGIN Full temperature range, R
L
= 2K, C
L
= 100pF 65
POWER BANDWIDTH V
O(P-P)
= 28V 13.6 kHz
OUTPUT
CURRENT, peak 1.5 A
SLEW RATE 1 1.4 V/s
VOLTAGE SWING Full Temperature Range, I
O
= 100mA |V
S
| - 1.1 |V
S
| - .8 V
VOLTAGE SWING Full Temperature Range, I
O
= 1A |V
S
| - 1.8 |V
S
| - 1.4 V
V
= 1, R
2
= 50, V
O
= .5V
RMS
, = 1kHz .02 %
POWER SUPPLY
VOLTAGE, V
SS
3
5 30 40 V
CURRENT, quiescent, total 8 10 mA
THERMAL
RESISTANCE,DC junction to case (single) 5.84 6.42 C/W
RESISTANCE,AC junction to case (single) 4.38 4.81 C/W
RESISTANCE,DC junction to case (both) 3.97 4.36 C/W
RESISTANCE,AC junction to case (both) 2.98 3.27 C/W
RESISTANCE,junction to air (CD,CX) 60 C/W
RESISTANCE,junction to air (CC)
4
27 C/W
TEMPERATURE RANGE,case Meets full range specifcations 25 85 C
SPECIFICATIONS
OUTPUT CURRENT SOA
POWER DISSIPATION, internal, (per amplifer) 19.5W
POWER DISSIPATION, internal (both amplifers) 28.6W
INPUT VOLTAGE, differential V
S
S
, -V
S
0.5V
1
150C
TEMPERATURE RANGE, storage 55C to 150C
OPERATING TEMPERATURE RANGE, case 40C to 125C
NOTES: 1. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation to
achieve high MTTF.
S
= 15V, T
C
= 25C.
3. +V
S
and V
S
denote the positive and negative supply rail respectively. V
SS
denotes the total rail-to-rail supply voltage.
4. Heat tab attached to 3/32" FR-4 board with 2oz. copper. Topside copper area (heat tab directly attached) = 1000 sq. mm, back-
side copper area = 2500 sq. mm, board area = 2500 sq. mm.
PA75
PA75U 369
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
0.0 0.4 0.8 1.2 1.6
35
45
55
65
L
(nF)
P
H
A
S
E

M
A
R
G
I
N
,

)
2.0
25
+V
S
= +15V
-V
S
= -15V
R
L
= 2K
A
V
= -100
0
-20
20
40
60
1 10 100 1K 10K
90
100
110
120
130
FREQUENCY, f (KHz)
G
A
I
N
,

A

(
d
B
)
P
H
A
S
E
,

)
+V
S
= +15V
-V
S
= -15V
R
L
= 2K
PULSE RESPONSE
TIME, t (s)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
0 10 20 30 40 50
-4
8
4
0
-8
-2
10
6
2
-6
-10
60 70
+V
S
= +15V
A
V
= +1
V
IN
= 10Vp
-V
S
= -15V
R
L
= 20
f
IN
= 20kHz
OUTPUT CURRENT, I
O
(A)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

(
V
)
0.1 0.3 0.5
0.6
1.8
1.4
1
0.2
0.8
2
1.6
1.2
0.4
0
0.7 0.9
PULSE RESPONSE
TIME, t (s)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
0 200 400 600 800 1000
0
1200 1400
+V
S
= +15V
A
V
= +1
V
IN
= 10Vp
-V
S
= -15V
f
IN
= 1kHz
-4
8
4
-8
-2
10
6
2
-6
-10
QUIESCENT CURRENT
NORMALIZED QUIESCENT CURRENT, I
Q
(mA)
0.9 1.9 1.1 1.3 1.5 1.7 0.7 1.5
0
24
20
16
12
8
4
T
O
T
A
L

S
U
P
P
L
Y

V
O
L
T
A
G
E
,

V
S

(
V
)
C
A
S
E

T
E
M
P
E
R
A
T
U
R
E
,

T
C

(
C
)
-80
160
120
80
40
0
-40
0 150 -100 50 -50 -100
-0.5
2.5
2
1.5
1
0.5
0
BIAS CURRENT
CASE TEMPERATURE, T
C
(C)
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
m
A
)
OFFSET VOLTAGE
TEMPERATURE, T
C
(C)
0 150 100 50 -50 -100
0
0.5
1
1.5
2
2.5
3
N
O
R
M
A
L
I
Z
E
D

O
F
F
S
E
T

V
O
L
T
A
G
E
,

V
O
S

(
m
V
)
PA75
370 PA75U
GENERAL
Please read Application Note 1 General Operating Consider-
ations which covers stability, supplies, heatsinking, mounting,
selection; Apex Precision Powers complete Application Notes
library; Technical Seminar Workbook; and Evaluation Kits.
All monolithic power
op amps use output
stage topologies that
present special stabil-
ity problems. This is
primarily due to non-
complementary (both
devi ces are NPN)
output stages with a
mismatch in gain and
phase response for
different polarities of
output current. It is dif-
fcult for the op amp manufacturer to optimize compensation
for all operating conditions. For applications with load current
exceeding 300ma, oscillation may appear. The oscillation may
occur only with the output voltage swing at the negative or
positive half cycle. Under most operating and load conditions
acceptable stability can be achieved by providing a series
RC snubber network connected from the output to ground.
The recommended component values of the of the network
are,R
SN
= 10 and C
SN
= 0.01F. Please refer to Application
Note 1 for further details.
The PA75CD and CX have a large exposed copper heat
tab to which the monolithic is directly attached. The PA75CD
and CX may require a thermal washer, which is electrically
insulating since the tab is directly tied to -VS. This can result
in a thermal impedance RCS of up to 1C/W or greater.
The PA75CC has a large exposed integrated copper heatslug
to which the monolithic is directly attached. The solder connec-
tion of the heatslug to a minimum of 1 square inch foil area of
the printed circuit board will result in thermal performance of
25C/W junction to air rating of the PA75CC. Solder connection
to an area of 1 to 2 square inches of foil is required for minimal
power applications
Where the PA75CC is used in higher power applications,
it is necessary to use surface mount techniques of heatsink-
ing. Surface mount techniques include the use of a surface
mount fan in combination with a surface mount heatsink on
the backside of the FR4/ PC board with through hole thermal
vias. Other highly thermal conductive substrate board materials
are available for maximum heat sinking.
1. Always use a heat sink. Even unloaded the PA75 can dis-
sipate up to .4 watts.
2. Avoid bending the leads. Such action can lead to internal
damage.
3. Always fasten the tab of the CD and CX package to the
heat sink before the leads are soldered to fxed terminals.
4. Strain relief must be provided if there is any probability of
axial stress to the leads.
SOA
TWO AMPLIFIERS
LOADED
ONE AMPLIFIER
LOADED
100.0 10.0
0.1
1.0
10.0
S
- V
O
(V)
DC, T
C
= 85C
1.0
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

o
r

-
V
S

(
A
)
DC, T
C
= 25C
0
5
10
15
20
25
30
35
0 125 100 75 50 25
CASE TEMPERATURE, T
C
(C)
TWO AMPLIFIERS
LOADED
ONE AMPLIFIER
LOADED
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
+
C
SN
0.01F
R
SN
10
PA75 Design Ideas
PA75DIU 371
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA75 Design Ideas
The function of the discontinued PA26 can be replaced with
a pair of PA75 amplifers. The basic technique is to connect
the op amp and the buffer sections of the PA75 in parallel to
perform as one op amp of the PA26 did. A second PA75 then
takes on the duties of the second op amp of the PA26. A new
printed circuit layout will be required. While the thermal rating
of existing PA26 heatsinking will be adequate for the pair of
PA75 amplifers, and most applications will need modifcation
to heatsink mounting design.
BASIC PARALLEL OPERATION NOT UTILIZING
VBOOST OR ISENSE FUNCTIONS.
This substitution requires for each half of the PA26 circuit:
1. Increase the wattage rating of the original snubber resistor
to 1.25W or more (the recommended value is still 1) to
become a sharing resistor.
2. Tie the buffer input directly to the op amp output.
3. Add a second 1 ohm 1.25W sharing resistor for the PA75
buffer section.
4. To the junction of the sharing resistors and original snubber
capacitor, connect the output and feedback.
5. If desired, the original snubber capacitor may be reduced
to 10nF (this will possibly save space).
Figure 1. Basic substitution
When this circuit was tested, a single 0.47F supply bypass
capacitor from +Vs to -Vs proved satisfactory for the second
PA75 amplifer, even for dual supplies. With 1 share resistors,
quiescent current was less than the typical for a PA26 and the
output voltage swing at 2.5A was equal to PA26.
1/2 PA26
-Vs
PA75
OP AMP
-Vs
PA75
BUFFER
FOR APPLICATIONS WHERE THE ISENSE FUNCTION
WAS IMPLEMENTED
Very nearly equal performance can be obtained because
the total quiescent current of the PA75 is roughly equal to the
output stage current only of the PA26.
Figure 2. Substitution with Isense
FOR APPLICATIONS WHERE VBOOST WAS IMPLE-
MENTED
As the PA75 actually swings closer to the rail at 1.25A than
the PA26 does at 2.5A, the advantage of the original Vboost
circuit can be obtained with PA75 even without Vboost pins.
The Vboost capacitors and diodes can be eliminated, the old
Vboost pin tied to +Vs and the sharing resistors reduced to
0.5 (0.75 W is adequate) in the basic substitution of Figure
1. With the phase shift of the current buffer amplifer generat-
ing circulating currents through the two 0.5 share resistors,
no load supply current will increase as high voltage and high
frequency output signals are driven. The test circuit with two
PA75 amplifers drew 215mA while driving 19Vpeak sine
waves at 15KHz. This current will be less as frequency or peak
output swing is reduced: Half the frequency will reduce it by
almost 2:1; half the amplitude will also reduce it by almost 2:1.
1/2 PA26
PA75
OP AMP
PA75
BUFFER
High Voltage Power Operational Amplifier
PA75 Design Ideas
P r o d u c t
I n n o v a t i o n
F r o m
MAY 2009
APEX PA75DIUREVA
PA78
372 PA78U
PA78
DESCRIPTION
FEATURES
Wide Supply Voltage
APPLICATIONS
12Pin SIP
PACKAGE STYLE EU
LEAD FORM EW
20Pin PSOP
PACKAGE STYLE DK
ACTIVE LOAD
ACTIVE LOAD
BUFFER
CURRENT
LIMIT
VOUT
VOUT+
VOUT
V+
V
BLOCK DIAGRAM
JUL 2009
APEX PA78UREVB
PA78
PA78U 373
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SUPPLY VOLTAGE, +V
S
to V
S
350 V
POWER DISSIPATION, internal, DC DK Pkg. 14 W
POWER DISSIPATION, internal, DC EU Pkg. 23 W
S
+V
S
V
TEMPERATURE, pin solder, 10s EU Pkg. 260 C
INPUT
OFFSET VOLTAGE EU Pkg. -25 8 25 mV
OFFSET VOLTAGE DK Pkg. -40 8 40 mV
-63 V/C
8

S
- 2 V
S
+ 5.5 V
NOISE, V
O
NOISE 500 nV/Hz
GAIN
OUTPUT
VOLTAGE SWING I
O
= 10mA |V
S
| - 2 V
VOLTAGE SWING I
O
= 100mA |V
S
| - 8.6 |V
S
| - 12 V
VOLTAGE SWING I
O
= 150mA |V
S
| - 10 V
P-P
+V
S
= 160V, V
S
= -160V 200 kHz
CL
= 6.2 44
SPECIFICATIONS
PA78
374 PA78U
PA78EU
12-pin SIP
I
LIM
V
OUT
C
C
- -V
S
-IN +IN C
R
+ C
C
+ +V
S
C
R
-
+V
S
C
C
+
R
C
+
R
F
R
IN
R
C
-
TO LOAD
_V
S
R
LIM
1 12 11 10 9 8 7 6 5 4 3 2
C
C
-
33pF
-V
S
C
C
V
OUT
I
L
+V
S
-IN
+IN
C
R
C
R
+
C
C
+
PA78DK
20 PIN PSOP
1
11 10
20
+
DK Package
EU Package
POWER SUPPLY
VOLTAGE 10 150 175 V
THERMAL
RESISTANCE, DC, junction to case
(PA78EU)
Full temperature range 5.5 C/W
RESISTANCE, DC, junction to air
(PA78EU)
(PA78DK)
Full temperature range 8.3 9.1 C/W
(PA78DK) (Note 6)
Full temperature range 25 C/W
(PA78DK) (Note 7)
C
is typical rating.
3. +V
S
and V
S
6. Rating applies when the heatslug of the DK package is soldered to a minimum of 1 square inch foil
area of a printed circuit board.
7. Rating applies with the JEDEC conditions outlined in the Heatsinksing section of this datasheet.
PA78
PA78U 375
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
The PA78 is ideally suited for driving continuous drop ink
jet printers, in both piezo actuation and defection applica-
tions. The high voltage of the amplifer creates an electro-
static feld on the defection plates to control the position of
the ink droplets. The rate at which droplets can be printed
is directly related to the rate at which the amplifer can drive
the plate to a different electrostatic feld strength.
PA78EU SOA
0.01
0.1
1
S
- V
O
(V)
C
U
R
R
E
N
T
,

A
M
P
S

(
A
)
10 100 1000
D
C
,

T
C
=

8
5
C
D
C
,

T
C
=

2
5
C
3
0
0
m
S
2
0
0
m
S
PULSE CURVES
@ 10% DUTY CYCLE MAX
PA78DK SOA
0.01
0.1
1
10 100 1000
S
- V
O
(V)
C
U
R
R
E
N
T
,

A
M
P
S

(
A
)
D
C
,

T
C
=

8
5
C
D
C
,

T
C
=

2
5
C
3
0
0
m
S
2
0
0
m
S
PULSE CURVES
0
20
40
60
80
100
120
140
FREQUENCY (Hz)
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N

(
d
B
)
1 10 100 1K 10K 100K
0
2
4
6
8
10
12
0 50 100 150 200
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y

(
V
)
+V
S
SIDE DROP
-V
S
SIDE DROP
+V
S
100 1K 10K
FREQUENCY, (Hz)
40
20
0
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N

(
d
B
)
60
100
80
-V
S
POWER DERATING
0
5
10
15
20
25
CASE TEMPERATURE, T
C
(C)
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
25 125 100 75 50 0
P
A
7
8
D
K
P
A
7
8
E
U
CURRENT LIMIT
0
20
40
60
80
100
120
140
160
0 50
RESISTOR VALUE ()
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
m
A
)
V
S

+V
S
100
GAIN = -100
1 100 1000
FREQUENCY, (KHz)
200
150
100
50
0
O
U
T
P
U
T

V
O
L
T
A
G
E
,

(
V
)300
250
POWER RESPONSE
350
GAIN = -50
10
NO COMPENSATION
100K
0-5V
DAC
1.6K
-15V
R
C
C
C
R
CL
C
C
R
C
+335V
DEFLECTION
PLATE INK
DROPLETS
PA78
376 PA78U
-35
-25
-15
-5
5
15
25
35
G
A
I
N
,
d
B
C
C
=0pF
C
C
=1pF
C
C
=2.2pF
C
C
=10pF
C
C
=22pF
C
C
=5pF
O
= 50V
P-P
A
V
=+26
R
BIAS
=100K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
V
S
=50V
FREQUENCY, KHz
10 1K 100 10K
-35
-25
-15
-5
5
15
25
35
G
A
I
N
,
d
B
C
C
=0pF
C
C
=1pF
C
C
=2.2pF
C
C
=10pF
C
C
=22pF
C
C
=5pF
O
= 5V
P-P
A
V
=+26
R
BIAS
=100K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
V
S
=50V
FREQUENCY, KHz
10 1K 100 10K
FREQUENCY, KHz
10 1K 100
-35
-25
-15
-5
5
15
25
35
45
G
A
I
N
,
d
B
C
C
=0pF
C
C
=1pF
C
C
=2.2pF
C
C
=10pF
C
C
=22pF
C
C
=5pF
O
= 500mV
P-P
A
V
=+26
R
BIAS
=100K
R
C
=3.3K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
V
S
=50V
10K
-25
-15
-5
5
15
25
35
45
G
A
I
N
,

d
B
500 mV
P-P
50 V
P-P
5 V
P-P
A
V
=+51
R
BIAS
=100K
R
C
=OPEN
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=50V
FREQUENCY, KHz
10 1K 100 10K
-90
-60
-30
0
30
60
90
120
150
180
P
H
A
S
E
,

C
S
=68pF
P
IN
=-40dBm
R
BIAS
=100K
R
S
= 48.7
V
S
=50V
FREQUENCY, KHz
100 1000 10 1
R
C
=OPEN, C
C
=0pF
R
C
=3.3K, C
C
=1pF
R
C
=3.3K, C
C
=2.2pF
R
C
=3.3K, C
C
=5pF
R
C
=3.3K, C
C
=10pF
R
C
=3.3K, C
C
=22pF
O
= 250mV
P-P
-90
-60
-30
0
30
60
90
120
150
180
P
H
A
S
E
,

C
S
=68pF
P
IN
=-40dBm
R
BIAS
=OPEN
R
S
= 48.7
FREQUENCY, KHz
100 1000 10 1
R
C
=OPEN, C
C
=0pF
R
C
=3.3K, C
C
=1pF
R
C
=3.3K, C
C
=2.2pF
R
C
=3.3K, C
C
=5pF
R
C
=3.3K, C
C
=10pF
R
C
=3.3K, C
C
=22pF
-20
0
20
40
60
80
100
FREQUENCY, KHz
100
G
A
I
N
,

D
b
C
S
=68pF
P
IN
=-40dBm
R
BIAS
=OPEN
R
S
= 48.7
V
S
=50V
1000 10 1
R
C
=OPEN, C
C
=0pF
R
C
=3.3K, C
C
=1pF
R
C
=3.3K, C
C
=2.2pF
R
C
=3.3K, C
C
=5pF
R
C
=3.3K, C
C
=10pF
R
C
=3.3K, C
C
=22pF
PA78
PA78U 377
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
C
AND R
C
-150
-120
-90
-60
-30
0
30
60
90
120
150
-2.4
-1.8
-1.2
-0.6
0
0.6
1.2
1.8
2.4
3.0
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
I
N
P
U
T

V
O
L
T
A
G
E
,

V
TIME, s
0 1 2 3 4 5 6 -1 -2 7 8
A
V
=+51
C
C
=68pF
C
L
=330pF
R
C
= 48
R
F
=75K
R
G
=1.5K
R
L
=OPEN
V
S
=150V
Out - 0pF
Out - 1pF & 3.3K
Out - 5pF & 3.3K
input
-3.0
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
I
N
P
U
T

V
O
L
T
A
G
E
,

V
TIME, s
-150
-100
-50
0
50
100
150
TRANSIENT RESPONSE
-8
-6
-4
-2
0
2
4
6
8
A
V
=+26
C
C
=2.2pF
C
L
=8pF
R
C
=3.3K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
10V
P-P
input10
-2 0 2 4 6 8 10 12 -4
2V
P-P
input2
TIME, s
-30
-20
-10
0
10
20
30
-1.5
-1
-0.5
0
0.5
1
1.5
TRANSIENT RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
I
N
P
U
T

V
O
L
T
A
G
E
,

V
A
V
=+26
C
C
=2.2pF
C
L
=8pF
R
C
=3.3K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
-2 0 2 4 6 8 10 12 -4
1V
P-P
input1
-15
-10
-5
0
5
10
15
TIME, s
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
I
N
P
U
T

V
O
L
T
A
G
E
,

V
-2 0 2 4 6 8 10 12 -4
TRANSIENT RESPONSE
A
V
=+26
C
C
=2.2pF
C
L
=8pF
R
C
=3.3K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
0
0.2
0.4
0.6
0.8
1
T
i
m
e
,

s
TR
TF
A
V
=+51
C
L
=8pF
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
0 2 4 6 8 10 12 14 16
SR+/SR- (25% - 75%)
SR+
SR-
A
V
=+26
C
L
=8pF
R
F
=35.6K
R
G
=1.5K
R
L
=50K
V
S
=150V
0 2 4 6 8 10 12 14 16
0
200
400
600
800
1000
S
R
,

V
/
s
SR+/SR- (25% -75%)
SR+
SR-
A
V
=+51
C
L
=8pF
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
0 2 4 6 8 10 12 14 16
0
200
400
600
800
1000
S
R
,

V
/
s
SR+/SR- (25% - 75%)
0
200
400
600
800
1000
SR+
SR-
S
R
,

V
/
s
A
V
=+101
C
L
=8pF
R
F
=25K
R
G
= 250
R
L
=50K
V
S
=150V
0 2 4 6 8 10 12 14 16
PA78
378 PA78U
0
5
10
15
20
25
30
1000 100 10
V
IN
=3V
P
A
V
=+51
C
L
=8pF
C
S
=68pF
R
F
=75K
R
G
=1.5K
R
L
=50K
R
S
= 48.7
V
S
=150V
I
S
,

m
A
V
IN
=6V
P
I
S
vs. V
IN
0
2
4
6
8
10
12
14
16
18
V
IN
, V
P-P
(100KHz sine wave)
A
V
=+51
C
L
=8pF
C
S
=68pF
R
F
=75K
R
G
=1.5K
R
L
=50K
R
S
= 48.7
V
S
=150V
I
S
,

m
A
1 9 8 7 6 5 4 3 2 0
OVERDRIVE RECOVERY
-300
-200
-100
0
100
200
300
TIME, s
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
-6
-4
-2
0
2
4
6
I
N
P
U
T

V
O
L
T
A
G
E
,

V
OUTPUT
INPUT
A
V
=+51
C
C
=OPEN
C
L
=8pF
R
C
=OPEN
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
-4 12 10 8 6 4 2 0 -2 -6
PULSE RESPONSE
-0.05
0
0.05
0.1
0.15
0.2
TIME,s
I
S
,

A
6 0 -1
A
V
=+51
C
L
=8pF
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
5 4 3 2 1
TIME, s
0 30 10 8 6 4 2 -2 -6 -4 28 26 24 22 20 18 16 14 12
A
V
=-50
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
300pF, 1V
P-P
200pF, 1V
P-P
100pF, 1V
P-P
-80
-60
-40
-20
0
20
40
60
80
100
120
140
O
U
T
P
U
T
,

V
-80
-60
-40
-20
0
20
40
60
80
100
120
140
O
U
T
P
U
T
,

V
300pF, 2V
P-P
200pF, 2V
P-P
100pF, 2V
P-P
A
V
=-50
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
C
L
=8pF
TIME, s
0 30 10 8 6 4 2 -2 -6 -4 28 26 24 22 20 18 16 14 12
A
V
=-50
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
-80
-60
-40
-20
0
20
40
60
80
100
120
140
TIME, s
O
U
T
P
U
T
,

V
300pf, 3V
P-P
200pf, 3V
P-P
100pf, 3V
P-P
0 30 10 8 6 4 2 -2 -6 -4 28 26 24 22 20 18 16 14 12
PA78
PA78U 379
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
Please read Application note 1 General operating
considerations which covers stability, power sup-
plies, heat sinking, mounting, current limit, SOA inter-
pretation, and specifcation interpretation. Visit www.
cirrus.com for design tools that help automate tasks
such as calculations for stability, internal power dis-
sipation, and current limit. There you will also fnd a
complete application notes library, technical seminar
workbook, and evaluation kits.
THEORY OF OPERATION
The PA78 is designed specifcally as a high speed
pulse amplifer. In order to achieve high slew rates
with low idle current, the internal design is quite dif-
ferent from traditional voltage feedback amplifers.
Basic op amp behaviors like high input impedance
and high open loop gain still apply. But there are
some notable differences, such as signal dependent
supply current, bandwidth and output impedance,
among others. The impact of these differences var-
ies depending on application performance require-
ments and circumstances. These different behaviors
are ideal for some applications but can make designs
more challenging in other circumstances.
SR+/SR- (25%-75%)
0
200
400
600
800
1000
1200
1400
1600
V
/
s
SR+(A
V
=-50)
SR-(A
V
=-50)
SR+(A
V
=+51)
SR-(A
V
=+51)
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
C
L
=8pF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SR+/SR- (25%-75%)
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
C
L
=8pF
0
200
400
600
800
1000
1200
S
R
+
/
S
R
-

V
/
s
SR+(A
V
=-25)
SR-(A
V
=-25)
SR+(A
V
=+26)
SR-(A
V
=+26)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PA78
380 PA78U
BIAS
, between C
C
- and V
S
+. The size of R
BIAS

will depend upon the application but 500A (50V V+ supply/100K) of added bias current shows signifcant improve-
a current source.
BIAS
networks are required. The compensation capacitor Cc must be rated for a working voltage of the full operating
supply voltage (+V
S
to V
S
temperature.
C
- and V
S
S
to V
S
).
P-P
to 15V
P-P
Notice the knee in the Rise and Fall times plot, at approximately 6V
P-P
The MOSFET output stage of the PA78 is not limited by second breakdown considerations as in bipolar output
stages. Only thermal considerations of the package and current handling capabilities limit the Safe Operating Area.
The SOA plots include power dissipation limitations which are dependent upon case temperature. Keep in mind
that the dynamic current sources which drive high slew rates can increase the operating temperature of the ampli-
fer during periods of repeated slewing. The plot of supply current vs. input signal amplitude for a 100 kHz signal
provides an indication of the supply current with repeated slewing conditions. This application dependent condition
must be considered carefully.
The output stage is self-protected against transient fyback by the parasitic body diodes of the output stage. How-
ever, for protection against sustained high energy fyback, external, fast recovery diodes must be used.
CURRENT LIMIT
LIM
, must be connected as shown in the external connec-
tions diagram. For maximum reliability and protection, the largest resistor value should be used. The minimum
practical value for R
LIM
is about 12. However, refer to the SOA curves for each package type to assist in selecting
the optimum value for R
LIM
in the intended application. Current limit may not protect against short circuit conditions
with supply voltages over 200V.
PA78
PA78U 381
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
C
/ C
C
loops in these paths pick up noise and increase the likelihood of LC interactions and oscillations.
The PA78DK package has a large exposed integrated copper heatslug to which the monolithic amplifer is directly
attached. The solder connection of the heat slug to a 1 square inch foil area on the printed circuit board will result
in improved thermal performance of 25C/W. In order to improve the thermal performance, multiple metal layers in
the printed circuit board are recommended. This may be adequate heatsinking but the large number of variables
involved suggest temperature measurements be made on the top of the package. Do not allow the temperature to
exceed 85C.
The junction to ambient thermal resistance of the DK package can achieve a 19.1C/W rating by using the PCB
conditions outlined in JEDEC standard: (JESD515):
PCB Conditions:
PCB Layers = 4L, Copper, FR4
PCB Dimensions = 101.6 x 114.3mm
PCB Thickness = 1.6mm
Conditions:
Power dissipation = 2 watt
Ambient Temperature = 55C
IMPORTANT NOTICE
PA79
382 PA79U
PA79
DESCRIPTION
FEATURES
Wide Supply Voltage
Output Current Per Amplifer
150mA Cont.; 200mA Pk
Up to 26 Watt Dissipation Capability (Dual)
APPLICATIONS
20Pin PSOP
PACKAGE STYLE DK
ACTIVE LOAD
ACTIVE LOAD
BUFFER
CURRENT
LIMIT
VOUT
VOUT+
VOUT
V+
V
BLOCK DIAGRAM
JJUL 2009
APEX PA79UREVB
PA79
PA79U 383
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SUPPLY VOLTAGE, +V
S
to V
S
350 V
POWER DISSIPATION, internal, DC Single 14 W
POWER DISSIPATION, internal, DC Dual 26 W
S
+V
S
V
INPUT
-63 V/C
8

S
- 2 V
S
+ 5.5 V
NOISE, V
O
NOISE 500 nV/Hz
GAIN
OUTPUT
VOLTAGE SWING I
O
= 10mA |V
S
| - 2 V
VOLTAGE SWING I
O
= 100mA |V
S
| - 8.6 |V
S
| - 12 V
VOLTAGE SWING I
O
= 150mA |V
S
| - 10 V
P-P
+V
S
= 160V, V
S
= -160V 200 kHz
CL
= 6.2 44
POWER SUPPLY
SPECIFICATIONS
PA79
384 PA79U
-V
S
(A)
C
C
- (A)
V
OUT
(A)
I
L
(A)
+V
S
(A)
V
OUT
(B)
I
L
(B)
C
C
- (B)
+V
S
(B)
C
C
+ (B)
-IN (A)
+IN (A)
C
R
- (A)
C
R
+ (A)
C
C
+ (A)
-V
S
(B)
-IN (B)
+IN (B)
C
R
+ (B)
C
R
- (B)
PA79DK
20 PIN PSOP
1
11 10
20
+
A
+
B
THERMAL
RESISTANCE, DC, junction to case, Dual
(Note 8)
RESISTANCE, DC, junction to case, Single Full temperature range 8.3 9.1 C/W
RESISTANCE, DC, junction to air, Dual Full temperature range 25 C/W
RESISTANCE, DC, junction to air, Single Full temperature range 19.1 C/W
C
is typical rating.
3. +V
S
and V
S
5. Supply current increases with signal frequency. See graph on page 4. Applies to each amplifer.
7. Rating applies with the JEDEC conditions outlined in the Heatsinksing section of this datasheet.
8. Rating applies when power dissipation is equal in two amplifers.
The PA79 is ideally suited for driving continu-
ous drop ink jet printers, in both piezo actuation
and defection applications. The high voltage of
the amplifer creates an electrostatic feld on the
defection plates to control the position of the
ink droplets. The rate at which droplets can be
printed is directly related to the rate at which the
amplifer can drive the plate to a different elec-
trostatic feld strength.
-175V
+175V
-175V
+175V
R
C
R
L
R
CL
R
CL
RFS
CFS
RIS
RF
CF
C
C
C
N
R
N
R
C
C
C
R
C
C
C
R
C
C
C
CL
V
IN
V
OUT
660V
PP
OUT
+IN
-V
S
C
C
-
C
R
-
-IN
+V
S
C
C
+
C
R
+
I
LIM PA79 (B)
OUT
+IN
-V
S
C
C
-
C
R
-
-IN
+V
S
C
C
+
C
R
+
I
LIM PA79 (A)
NOTES:
1. The package heat slug needs to be connected to a stable refer-
ence such as gnd for high slew rates. Please refer to special
considerations section for details.
2. Supply bypassing required for V
S
and +V
S
.
3. For C
C
and R
C
values refer to power supply biasing section.
4. Dimple and ESD triangle denotes pin 1.
PA79
PA79U 385
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
25 125 100 75 50 0
0
30
25
20
15
10
5
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
ONE
AMPLIFIER
LOADED
TWO
AMPLIFIERS
LOADED
POWER DERATING
CASE TEMPERATURE, T
C
(C)
0
20
40
60
80
100
120
140
FREQUENCY (Hz)
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N

(
d
B
)
1 10 100 1K 10K 100K
0
2
4
6
8
10
12
0 50 100 150 200
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y

(
V
)
+V
S
SIDE DROP
-V
S
SIDE DROP
+V
S
100 1K 10K
FREQUENCY, (Hz)
40
20
0
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N

(
d
B
)
60
100
80
-V
S
CURRENT LIMIT
0
20
40
60
80
100
120
140
160
0 50
RESISTOR VALUE ()
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
m
A
)
V
S

+V
S
100
GAIN = -100
1 100 1000
FREQUENCY, (KHz)
200
150
100
50
0
O
U
T
P
U
T

V
O
L
T
A
G
E
,

(
V
)300
250
POWER RESPONSE
350
GAIN = -50
10
NO COMPENSATION
PHASE RESPONSE
-80
-60
-40
-20
0
20
40
60
80
100
120
10K 100K 1M 10M
FREQUENCY (Hz)
P
H
A
S
E

(
)
NO
COMPENSATION
C
C
= 2.7pF
C
C
= 10pF
C
C
= 22pF
33pF PIN 3 TO GND
100K +V
S
TO PIN 3
R
c
= 3.3K
OPEN LOOP GAIN
-40
-20
0
20
40
60
80
10K 100K 1M 10M
FREQUENCY (Hz)
G
A
I
N

(
d
B
)
NO COMPENSATION
C
C
= 2.7pF
C
C
= 10pF
C
C
= 22pF
33pF PIN 3 TO GND
100K +V
S
TO PIN 3
R
C
=3.3K
PA79
386 PA79U
-35
-25
-15
-5
5
15
25
35
G
A
I
N
,
d
B
C
C
=0pF
C
C
=1pF
C
C
=2.2pF
C
C
=10pF
C
C
=22pF
C
C
=5pF
O
= 50V
P-P
A
V
=+26
R
BIAS
=100K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
V
S
=50V
FREQUENCY, KHz
10 1K 100 10K
-35
-25
-15
-5
5
15
25
35
G
A
I
N
,
d
B
C
C
=0pF
C
C
=1pF
C
C
=2.2pF
C
C
=10pF
C
C
=22pF
C
C
=5pF
O
= 5V
P-P
A
V
=+26
R
BIAS
=100K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
V
S
=50V
FREQUENCY, KHz
10 1K 100 10K
FREQUENCY, KHz
10 1K 100
-35
-25
-15
-5
5
15
25
35
45
G
A
I
N
,
d
B
C
C
=0pF
C
C
=1pF
C
C
=2.2pF
C
C
=10pF
C
C
=22pF
C
C
=5pF
O
= 500mV
P-P
A
V
=+26
R
BIAS
=100K
R
C
=3.3K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
V
S
=50V
10K
-25
-15
-5
5
15
25
35
45
G
A
I
N
,

d
B
500 mV
P-P
50 V
P-P
5 V
P-P
A
V
=+51
R
BIAS
=100K
R
C
=OPEN
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=50V
FREQUENCY, KHz
10 1K 100 10K
-90
-60
-30
0
30
60
90
120
150
180
P
H
A
S
E
,

C
S
=68pF
P
IN
=-40dBm
R
BIAS
=100K
R
S
= 48.7
V
S
=50V
FREQUENCY, KHz
100 1000 10 1
R
C
=OPEN, C
C
=0pF
R
C
=3.3K, C
C
=1pF
R
C
=3.3K, C
C
=2.2pF
R
C
=3.3K, C
C
=5pF
R
C
=3.3K, C
C
=10pF
R
C
=3.3K, C
C
=22pF
O
= 250mV
P-P
-90
-60
-30
0
30
60
90
120
150
180
P
H
A
S
E
,

C
S
=68pF
P
IN
=-40dBm
R
BIAS
=OPEN
R
S
= 48.7
FREQUENCY, KHz
100 1000 10 1
R
C
=OPEN, C
C
=0pF
R
C
=3.3K, C
C
=1pF
R
C
=3.3K, C
C
=2.2pF
R
C
=3.3K, C
C
=5pF
R
C
=3.3K, C
C
=10pF
R
C
=3.3K, C
C
=22pF
-20
0
20
40
60
80
100
FREQUENCY, KHz
100
G
A
I
N
,

D
b
C
S
=68pF
P
IN
=-40dBm
R
BIAS
=OPEN
R
S
= 48.7
V
S
=50V
1000 10 1
R
C
=OPEN, C
C
=0pF
R
C
=3.3K, C
C
=1pF
R
C
=3.3K, C
C
=2.2pF
R
C
=3.3K, C
C
=5pF
R
C
=3.3K, C
C
=10pF
R
C
=3.3K, C
C
=22pF
PA79
PA79U 387
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
C
AND R
C
-150
-120
-90
-60
-30
0
30
60
90
120
150
-2.4
-1.8
-1.2
-0.6
0
0.6
1.2
1.8
2.4
3.0
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
I
N
P
U
T

V
O
L
T
A
G
E
,

V
TIME, s
0 1 2 3 4 5 6 -1 -2 7 8
A
V
=+51
C
C
=68pF
C
L
=330pF
R
C
= 48
R
F
=75K
R
G
=1.5K
R
L
=OPEN
V
S
=150V
Out - 0pF
Out - 1pF & 3.3K
Out - 5pF & 3.3K
input
-3.0
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
I
N
P
U
T

V
O
L
T
A
G
E
,

V
TIME, s
-150
-100
-50
0
50
100
150
TRANSIENT RESPONSE
-8
-6
-4
-2
0
2
4
6
8
A
V
=+26
C
C
=2.2pF
C
L
=8pF
R
C
=3.3K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
10V
P-P
input10
-2 0 2 4 6 8 10 12 -4
2V
P-P
input2
TIME, s
-30
-20
-10
0
10
20
30
-1.5
-1
-0.5
0
0.5
1
1.5
TRANSIENT RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
I
N
P
U
T

V
O
L
T
A
G
E
,

V
A
V
=+26
C
C
=2.2pF
C
L
=8pF
R
C
=3.3K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
-2 0 2 4 6 8 10 12 -4
1V
P-P
input1
-15
-10
-5
0
5
10
15
TIME, s
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
I
N
P
U
T

V
O
L
T
A
G
E
,

V
-2 0 2 4 6 8 10 12 -4
TRANSIENT RESPONSE
A
V
=+26
C
C
=2.2pF
C
L
=8pF
R
C
=3.3K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
0
0.2
0.4
0.6
0.8
1
T
i
m
e
,

s
TR
TF
A
V
=+51
C
L
=8pF
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
0 2 4 6 8 10 12 14 16
SR+/SR- (25% - 75%)
SR+
SR-
A
V
=+26
C
L
=8pF
R
F
=35.6K
R
G
=1.5K
R
L
=50K
V
S
=150V
0 2 4 6 8 10 12 14 16
0
200
400
600
800
1000
S
R
,

V
/
s
SR+/SR- (25% -75%)
SR+
SR-
A
V
=+51
C
L
=8pF
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
0 2 4 6 8 10 12 14 16
0
200
400
600
800
1000
S
R
,

V
/
s
SR+/SR- (25% - 75%)
0
200
400
600
800
1000
SR+
SR-
S
R
,

V
/
s
A
V
=+101
C
L
=8pF
R
F
=25K
R
G
= 250
R
L
=50K
V
S
=150V
0 2 4 6 8 10 12 14 16
PA79
388 PA79U
0
5
10
15
20
25
30
1000 100 10
V
IN
=3V
P
A
V
=+51
C
L
=8pF
C
S
=68pF
R
F
=75K
R
G
=1.5K
R
L
=50K
R
S
= 48.7
V
S
=150V
I
S
,

m
A
V
IN
=6V
P
I
S
vs. V
IN
0
2
4
6
8
10
12
14
16
18
V
IN
, V
P-P
(100KHz sine wave)
A
V
=+51
C
L
=8pF
C
S
=68pF
R
F
=75K
R
G
=1.5K
R
L
=50K
R
S
= 48.7
V
S
=150V
I
S
,

m
A
1 9 8 7 6 5 4 3 2 0
OVERDRIVE RECOVERY
-300
-200
-100
0
100
200
300
TIME, s
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
-6
-4
-2
0
2
4
6
I
N
P
U
T

V
O
L
T
A
G
E
,

V
OUTPUT
INPUT
A
V
=+51
C
C
=OPEN
C
L
=8pF
R
C
=OPEN
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
-4 12 10 8 6 4 2 0 -2 -6
PULSE RESPONSE
-0.05
0
0.05
0.1
0.15
0.2
TIME,s
I
S
,

A
6 0 -1
A
V
=+51
C
L
=8pF
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
5 4 3 2 1
TIME, s
0 30 10 8 6 4 2 -2 -6 -4 28 26 24 22 20 18 16 14 12
A
V
=-50
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
300pF, 1V
P-P
200pF, 1V
P-P
100pF, 1V
P-P
-80
-60
-40
-20
0
20
40
60
80
100
120
140
O
U
T
P
U
T
,

V
-80
-60
-40
-20
0
20
40
60
80
100
120
140
O
U
T
P
U
T
,

V
300pF, 2V
P-P
200pF, 2V
P-P
100pF, 2V
P-P
A
V
=-50
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
C
L
=8pF
TIME, s
0 30 10 8 6 4 2 -2 -6 -4 28 26 24 22 20 18 16 14 12
A
V
=-50
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
-80
-60
-40
-20
0
20
40
60
80
100
120
140
TIME, s
O
U
T
P
U
T
,

V
300pf, 3V
P-P
200pf, 3V
P-P
100pf, 3V
P-P
0 30 10 8 6 4 2 -2 -6 -4 28 26 24 22 20 18 16 14 12
PA79
PA79U 389
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
Please read Application note 1 General operating
considerations which covers stability, power sup-
plies, heat sinking, mounting, current limit, SOA inter-
pretation, and specifcation interpretation. Visit www.
cirrus.com for design tools that help automate tasks
such as calculations for stability, internal power dis-
sipation, and current limit. There you will also fnd a
complete application notes library, technical seminar
workbook, and evaluation kits.
THEORY OF OPERATION
The PA79 is designed specifcally as a high speed
pulse amplifer. In order to achieve high slew rates
with low idle current, the internal design is quite dif-
ferent from traditional voltage feedback amplifers.
Basic op amp behaviors like high input impedance
and high open loop gain still apply. But there are
some notable differences, such as signal dependent
supply current, bandwidth and output impedance,
among others. The impact of these differences var-
ies depending on application performance require-
ments and circumstances. These different behaviors
are ideal for some applications but can make designs
more challenging in other circumstances.
SR+/SR- (25%-75%)
0
200
400
600
800
1000
1200
1400
1600
V
/
s
SR+(A
V
=-50)
SR-(A
V
=-50)
SR+(A
V
=+51)
SR-(A
V
=+51)
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
C
L
=8pF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SR+/SR- (25%-75%)
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
C
L
=8pF
0
200
400
600
800
1000
1200
S
R
+
/
S
R
-

V
/
s
SR+(A
V
=-25)
SR-(A
V
=-25)
SR+(A
V
=+26)
SR-(A
V
=+26)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PA79
390 PA79U
BIAS
, between C
C
- and V
S
+. The size of R
BIAS

will depend upon the application but 500A (50V V+ supply/100K) of added bias current shows signifcant improve-
a current source.
BIAS
supply voltage (+V
S
to V
S
temperature.
C
- and V
S
S
to V
S
).
P-P
to 15V
P-P
Notice the knee in the Rise and Fall times plot, at approximately 6V
P-P
The MOSFET output stage of the PA79 is not limited by second breakdown considerations as in bipolar output
stages. Only thermal considerations of the package and current handling capabilities limit the Safe Operating Area.
The SOA plots include power dissipation limitations which are dependent upon case temperature. Keep in mind
that the dynamic current sources which drive high slew rates can increase the operating temperature of the ampli-
fer during periods of repeated slewing. The plot of supply current vs. input signal amplitude for a 100 kHz signal
provides an indication of the supply current with repeated slewing conditions. This application dependent condition
must be considered carefully.
The output stage is self-protected against transient fyback by the parasitic body diodes of the output stage. How-
ever, for protection against sustained high energy fyback, external, fast recovery diodes must be used.
CURRENT LIMIT
LIM
, must be connected as shown in the external connections
diagram. For maximum reliability and protection, the largest resistor value should be used. The minimum practi-
cal value for R
LIM
is about 12. However, refer to the SOA curves for each package type to assist in selecting the
optimum value for R
LIM
in the intended application. Current limit may not protect against short circuit conditions with
supply voltages over 200V.
PA79
PA79U 391
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
C
/ C
C
loops in these paths pick up noise and increase the likelihood of L
C
interactions and oscillations.
The PA79DK package has a large exposed integrated copper heatslug to which the monolithic amplifer is directly
attached. The solder connection of the heat slug to a 1 square inch foil area on the printed circuit board will result
in improved thermal performance of 25C/W. In order to improve the thermal performance, multiple metal layers in
the printed circuit board are recommended. This may be adequate heatsinking but the large number of variables
involved suggest temperature measurements be made on the top of the package. Do not allow the temperature to
exceed 85C.
The junction to ambient thermal resistance of the DK package can achieve a 19.1C/W rating by using the PCB
conditions outlined in JEDEC standard: (JESD515):
PCB Conditions:
PCB Layers = 4L, Copper, FR4
PCB Dimensions = 101.6 x 114.3mm
PCB Thickness = 1.6mm
Conditions:
Power dissipation = 2 watts
Ambient Temperature = 55C
MOISTURE SENSITIVITY
The PA79DK has been qualifed according to JEDEC 22-A-113-D, MSL 3. The following conditions were used: IR
refow for Pb-free assembly profle where: package thickness is greater than 2.5mm, package volume is greater
than 350mm
2
, TP = 245C.
PA81J PA82J
392 PA81-82U
PA81J, PA82J
FEATURES
HIGH VOLTAGE OPERATION 150V (PA82J)
HIGH OUTPUT CURRENT 30mA (PA81J)
LOW BIAS CURRENT, LOW NOISE FET Input
APPLICATIONS
HIGH IMPEDANCE BUFFERS UP TO 140V
ELECTROSTATIC TRANSDUCER & DEFLECTION
BIOCHEMISTRY STIMULATORS
COMPUTER TO VACUUM TUBE INTERFACE
DESCRIPTION
The PA80 series of high voltage operation amplifers provides
an extremely wide range of supply capability with two over-
lapping products. High accuracy is achieved with a cascode
input circuit confguration. All internal biasing is referenced
to a zener diode. As a result, these models offer outstanding
common mode and power supply rejection. The output stage
operates in the class A/B mode for best linearity. Internal phase
compensation assures stability at all gain settings without ex-
ternal components. Fixed internal current limits protect these
amplifers against a short circuit to common at most supply
voltages. For sustained high energy fyback, external fast
recovery diodes should be used. However, a heatsink may
be necessary to maintain the proper case temperature under
normal operating conditions.
This hybrid circuit utilizes thick flm resistors, ceramic
capacitors and silicon semiconductors to maximize reliabil-
ity, minimize size and give top performance. Ultrasonically
bonded aluminum wires provide reliable interconnections
at all operating temperatures. The 8-pin TO-3 package (see
voids the warranty.
TOP VIEW
1
2
3
4
5
6
7
8
V
S
+IN
IN
BAL
N.C.
OUTPUT
BAL
+V
S
NOTE: Input offset trimpot optional.
Recommended value of 100K
TYPICAL APPLICATION
The PA81 and 70K ohm resistor form a current to voltage
converter, accepting 1mA from a 12 bit current output digital
to analog converter. The power op amp contribution to the er-
ror budget is insignifcant. At a case temperature of 70C, the
combination of voltage offset and bias errors amounts to less
than 31ppm of full scale range. Incorporation of the optional
offset trim can further reduce these errors to under 9ppm.
+75V
75V
70K
PA81J
HIGH VOLTAGE PROGRAMMABLE POWER SUPPLY
1mA
D/A
.47
.47
70V
2
7
4
3
5
6
1
Q1 Q2
D1
D2
Q15
Q12B
Q9
C4
Q8
Q13
Q4
Q3
C1
Q16
Q17
Q5
C5
Q12A
Q14
C6
C2
C3
Q11
Q6
Q7
8-PIN TO-3
PACKAGE STYLE CE
PA81J PA82J P r o d u c t I n n o v a t i o n F r o m
MAY 2009
APEX PA81-82JUREVJ
PA81J PA82J
PA81-82U 393
G
H
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E
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C
B
A
G
H
I
F
E
D
C
B
A
SPECIFICATIONS
PA81J PA82J
SUPPLY VOLTAGE, +V
S
to V
S
200V 300V
OUTPUT CURRENT, within SOA Internally Limited
POWER DISSIPATION, internal 11.5W 11.5W
INPUT VOLTAGE, differential 150V 300V
S
V
S
TEMPERATURE, pin solder - 10 sec 300C 300C
TEMPERATURE, junction 150C 150C
TEMPERATURE RANGE, storage 65 to +125C 65 to +125C
OPERATING TEMPERATURE RANGE, case 55 to +125C 55 to +125C
PA81J PA82J
2
INPUT
C
= 25C 1.5 3 * * mV
C
= 25C 20 * V/V
C
= 25C 75 * V/kh
C
= 25C 5 50 * * pA
C
= 25C .2 * pA/V
C
= 25C 2.5 50 * * pA
C
= 25C 10
11
*
INPUT CAPACITANCE T
C
= 25C 10 * pF
2
S
10 * V
CM
= 20V 110 * dB

GAIN
OPEN LOOP GAIN at 10Hz Full load 94 116 100 118 dB
UNITY GAIN BANDWIDTH T
C
= 25C 5 * MHz
POWER BANDWIDTH T
C
= 25C, full load 60 30 kHz
OUTPUT
VOLTAGE SWING
2
T
C
= 25C, I
PK
V
S
5 * V
CURRENT, peak T
C
= 25C 30 15 mA
CURRENT, limit T
C
= 25C 50 25 mA
C
= 25C, 10V step 12 * s
SLEW RATE
4
T
C
= 25C 20 * V/s
CAPACITIVE LOAD A
V
= 1 10 * nF
POWER SUPPLY
VOLTAGE Full temperature range 32 75 75 70 150 150 V
C
= 25C 6.5 8.5 6.5 8.5 mA
THERMAL
3
F > 60Hz 6 * C/W
3
F < 60Hz 9 10 * * C/W
TEMPERATURE RANGE, shutdown 150 * C
NOTES: * The specifcation of PA82J is identical to the specifcation for PA81J in applicable column to the left.
2. +V
S
and V
S
S
is measured from +V
S
to V
S
.
4. On the PA81J and PA82J, signal slew rates at pins 5 and 6 must be limited to less than 1V/ns to avoid damage. When faster
waveforms are unavoidable, resistors in series with those pins, limiting current to 150mA will protect the amplifer from damage.
CAUTION
PA81J PA82J
394 PA81-82U
0 25 50 75 100 125
TEMPERATURE, T
C
(C)
2
6
8
12
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
50 100
80
120
130
CURRENT LIMIT
100
70
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/
H
z
)
1
FREQUENCY, F (Hz)
20
0
60
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
20
40
80
100
10
210
150
60
0
PHASE RESPONSE
90
30
FREQUENCY, F (Hz)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
P
)
HARM0NIC DISTORTION
D
I
S
T
O
R
T
I
O
N

(
%
)
90
POWER SUPPLY (% OF MAX)
0.7
SLEW RATE
N
O
R
M
A
L
I
Z
E
D

S
L
E
W

R
A
T
E
0.8
1.0
COMMON MODE VOLTAGE
C
O
M
M
O
N

M
O
D
E

V
O
L
T
A
G
E
,

V
C
M

(
V
P
P
)
1
FREQUENCY, F (Hz)
C
O
M
M
O
M

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
120
10 100 1
FREQUENCY, F (Hz)
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)
15 45 85
64
BIAS CURRENT
N
O
R
M
A
L
I
Z
E
D

C
U
R
R
E
N
T

L
I
M
I
T
,

(
%
)
4
INPUT NOISE
25 25 50 75
110
POWER RESPONSE
40 50 60 70 80
5 25 65
.06
.25
1K 100K
10
P
H
A
S
E
,

)
N
O
R
M
A
L
I
Z
E
D

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
X
)
1
20
60
100
10 100
0
20
40
60
80
100
0.9
90
256
180
120
0
60
125
100 1K 10K .1M
100 110
4
0
10K 1M 10M 1
105
120
100 10 1M 10M
FREQUENCY, F (Hz)
140
0
1K 10K 1M 1K 10K 1M
120
140
100
.1M 50K .5M
15
30
60
200
300
25K .15M .25M.35M
3
.1
.01
.003
.03
1
.3
1K 10K 100K 3K 100 300 30K
.1M .1M
30
60
100
200
300
15
1M 10K .1M 20K 50K .2M .5M
2
4
6
10
20
10 1K 10K .1M 100
T = T
A
T = T
C
V
S
+V
S
P
A
8
1
J
/
P
A
8
2
J
PA82J
R
L
= 10K
100VRMS
PA81J
R
L
= 2K
40VRMS
+
2
5
C

T
O

+
8
5
2
5
C
PA82J
PA81J
CASE TEMPERATURE, T
C
C
(C)
FREQUENCY, F (Hz)
PA82J
PA81J
16
FREQUENCY, F (Hz)
PA81J PA82J
PA81-82U 395
G
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F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SINGLE SUPPLY OPERATION
These amplifers are suitable for operation from a single sup-
ply voltage. The operating requirements do however, impose
the limitation that the input voltages do not approach closer
than 10 volts to either supply rail. This is due to the operating
voltage requirements of the current sources, the half-dynamic
loads and the cascode stage. Refer to the simplifed schemat-
ics.Thus, single supply operation requires the input signals
to be biased at least 10 volts from either supply rail. Figure 3
illustrates one bias technique to achieve this.
Figure 4 illustrates a very common deviation from true single
supply operation. The availibility of two supplies still allows
ground (common) referenced signals, but also maximizes the
high voltage capability of the unipolar output. This technique
can utilize an existing low voltage system power supply and
does not place large current demands on that supply. The 12
volt supply in this case must supply only the quiescent current
of the PA81J, which is 8.5mA maximum. If the load is reactive
or EMF producing, the low voltage supply must also be able
to absorb the reverse currents generated by the load.
GENERAL
For the PA80J and PA81J, the combination of voltage capa-
bility and internal current limits mandate that the devices are
safe for all combinations of supply voltage and load. On the
PA82J, any load combination is safe up to a total supply of 250
volts. When total supply voltage equals 300 volts, the device
will be safe if the output current is limited to 10 milliamps or
less. This means that the PA82J used on supplies up to 125
volts will sustain a short to common or either supply without
danger. When using supplies above 125 volts, a short to
one of the supplies will be potentially destructive. When us-
ing single supply above 250 volts, a short to common will be
potentially destructive.
Safe supply voltages do not imply disregard for heatsinking.
The thermal calculations and the use of a heatsink are required
in many applications to maintain the case temperature within
the specifed operating range of 0 to 70C. Exceeding this case
temperature range can result in an inoperative circuit due to
excessive input errors or activation of the thermal shutdown.
INDUCTIVE LOADS
to protect these amplifers against fyback (kickback) pulses
exceeding the supply voltage of the amplifer when driving in-
ductive loads. For component selection, these external diodes
must be very quick, such as ultra fast recovery diodes with
no more than 200 nanoseconds of reverse recovery time. Be
sure the diode voltage rating is greater than the total of both
supplies. The diode will turn on to divert the fyback energy
into the supply rails thus protecting the output transistors from
destruction due to reverse bias.
pulse must be absorbed by the power supply. As a result, a
transient will be superimposed on the supply voltage, the
magnitude of the transient being a function of its transient
impedance and current sinking capability. If the supply voltage
plus transient exceeds the maximum supply rating, or if the AC
impedance of the supply is unknown, it is best to clamp the
output and the supply with a zener diode to absorb the transient.
+V
S
V
S
FIGURE 2.
PROTECTION,
INDUCTIVE LOAD
+210V
50K
PA82J
FIGURE 3.
TRUE SINGLE
SUPPLY OPERATION
D/A
+50/+200V
+210V
50K 2.5K
2.5K
2.5/10V
50K
+210V
50K
+12V
130V
50K
PA81J
FIGURE 4.
NON-SYMMETRIC
SUPPLIES
0/5V
D/A
0/125V
2K
PA83 PA83A
396 PA83U
PA83, PA83A
FEATURES
FULLY PROTECTED INPUT Up to 150V
APPLICATIONS
ANALOG SIMULATORS
DESCRIPTION
for output voltage swings up to 145V with a dual () supply or
290V with a single supply. Its input stage is protected against
transient and steady state overvoltages up to and including
the supply rails. High accuracy is achieved with a cascode
input circuit confguration. All internal biasing is referenced
to a zener diode fed by a FET constant current source. As
a result, the PA83 features an unprecedented supply range
and excellent supply rejection. The output stage is biased in
the class A/B mode for linear operation. Internal phase com-
pensation assures stability at all gain settings without need
for external components. Fixed current limits protect these
amplifers against shorts to common at supply voltages up to
120V. For operation into inductive loads, two external fyback
pulse protection diodes are recommended. However, a heatsink
may be necessary to maintain the proper case temperature
under normal operating conditions.
This hybrid circuit utilizes beryllia (BeO) substrates, thick
(cermet) flm resistors, ceramic capacitors and silicon semicon-
ductor chips to maximize reliability, minimize size and give top
8-pin TO-3 package is hermetically sealed and electrically iso-
lated. The use of compressible thermal isolation washers and/or
improper mounting torque voids product warranty. Please see
Application Note 1 General Operating Considerations.
TYPICAL APPLICATION
While piezo electric transducers present a complex imped-
ance, they are often primarily capacitive at useful frequen-
cies. Due to this capacitance, the speed limitation for a given
transducer/amplifer combination may well stem from limited
current drive rather than power bandwidth restrictions. With
its drive capability of 75mA, the PA83 can drive transducers
having up to 2nF of capacitance at 40kHz at maximum output
voltage. In the event the transducer may be subject to shock
or vibration, fyback diodes, voltage clamps or other protection
networks must be added to protect the amplifer from high
voltages which may be generated.
+150V
150V
100K
A1
PA83
SIMPLE PIEZO ELECTRIC TRANSDUCER DRIVE
5V
3.57K
GATED
OSCILLATOR
I =
V
*
C
t
2
7
4
3
5
6
1
Q1 Q2
D1
D2
Q15
Q12B
Q9
C4
Q8
Q13
Q4
Q3
C1
Q16
Q17
Q5
C5
Q12A
Q14
C6
C2
C3
Q10
Q6
Q7
Q11
TOP VIEW
1
2
3
4
5
6
7
8
V
S
+IN
IN
BAL
N.C.
OUTPUT
BAL
+V
S
NOTE:
1. Pin 8 not internally connected.
2. Input offset trimpot optional.
Recommended value of 100K.
8-PIN TO-3
PACKAGE STYLE CE
MAY 2009
APEX PA83UREVQ
PA83 PA83A
PA83U 397
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A
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A
SPECIFICATIONS
SUPPLY VOLTAGE, +V
S
to V
S
300V
C
= 25C
1
17.5W
INPUT VOLTAGE, common mode 300V
TEMPERATURE, pin solder - 10s max (solder) 300C
TEMPERATURE, junction 175C
PA83 PA83A
2
INPUT
C
= 25C 1.5 3 .5 1 mV
C
= 25C .5 .2 V/V
C
= 25C 75 * V/kh
3
T
C
= 25C 5 50 3 10 pA
C
= 25C .01 * pA/V
3
T
C
= 25C 2.5 50 1.5 10 pA
OFFSET CURRENT, vs. supply T
C
= 25C .01 * pA/V
C
= 25C 10
11
*
INPUT CAPACITANCE Full temperature range 6 * pF
4
S
10 * V
COMMON MODE REJECTION, DC Full temperature range 130 * dB

GAIN
C
= 25C, R
L
= 2K 96 116 * * dB
UNITY GAIN CROSSOVER FREQ. T
C
= 25C, R
L
= 2K 5 3 * MHz
POWER BANDWIDTH T
C
= 25C, R
L
= 10K 60 40 * kHz
OUTPUT
VOLTAGE SWING
4
, full load Full temp. range, I
O
= 75mA V
S
10 V
S
5 * * V
VOLTAGE SWING
4
Full temp. range, I
O
= 15mA V
S
5 V
S
3 * * V
CURRENT, peak T
C
= 25C 75 * mA
CURRENT, short circuit T
C
= 25C 100 * mA
SLEW RATE
6
T
C
= 25C, R
L
= 2K 20 30 * * V/s
CAPACITIVE LOAD, gain > 4 Full temperature range SOA * F
C
= 25C, R
L
= 2K, 10V step 12 * s
POWER SUPPLY
VOLTAGE T
C
= 55C to +125C 15 150 150 * * * V
C
= 25C 6 8.5 * * mA
THERMAL
5
F > 60Hz 4.26 * C/W
RESISTANCE, case to air 30 * C/W
TEMP. RANGE, case (PA83/PA83A) Meets full range specifcation 25 +85 * * C
achieve high MTTF.
2. The power supply voltage for all tests is the TYP rating, unless otherwise noted as a test condition.
4. +V
S
and V
S
S
is measured from +V
S
to V
S
.
6. Signal slew rates at pins 5 and 6 must be limited to less than 1V/ns to avoid damage. When faster waveforms are unavoidable,
resistors in series with those pins, limiting current to 150mA will protect the amplifer from damage.
CAUTION
PA83 PA83A
398 PA83U
55 100
0
200
250
CURRENT LIMIT
100
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/
H
z
)
1
FREQUENCY, F (Hz)
20
0
60
O
P
E
N

L
O
O
P

G
A
I
N
,

A
O
L

(
d
B
)
20
40
80
100
10
210
150
60
0
PHASE RESPONSE
90
30
FREQUENCY, F (Hz)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
P
)
PULSE RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
)
200
S
(V)
.4
.6
1.6
SLEW RATE VS. SUPPLY
N
O
R
M
A
L
I
Z
E
D

S
L
E
W

R
A
T
E

(
X
)
.8
1.4
COMMON MODE VOLTAGE
C
O
M
M
O
N

M
O
D
E

V
O
L
T
A
G
E
,

V
C
M

(
V
P
P
)
1
FREQUENCY, F (Hz)
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
120
10 100 1
FREQUENCY, F (Hz)
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)
0 60 100
7

C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
6
INPUT NOISE
25 25 50 75
150
POWER RESPONSE
30 50 100 150
1.2
20 40 80
2
3
1K 100K
P
H
A
S
E
,

)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

V
O

(
V
)
4
20
60
100
10 100
0
20
40
60
80
100
1.0
50
8
180
120
0 125
100 1K 10K .1M
250 300
10K 1M 10M
FREQUENCY, F (Hz)
1
120
120
100 10 1M 10M
FREQUENCY, F (Hz)
140
0
1K 10K 1M 1K 10K 1M
120
140
6
0
4
6
2
4
2
.5 1.5 2.5 1 .5 0 2.0
.1M .1M
30
60
100
200
300
15
1M 10K .1M 20K 50K .2M .5M
2
4
6
10
20
15
10 1K 10K .1M 100
CASE TEMPERATURE, T
C
(C) OUTPUT CURRENT I
O
(mA)
TIME, t (s)
3.0
5
15
100
1M .1M 50K .2M .5M
30
60
200
300
.3M .7M
T
C

=

2
5
C
T
C

=

8
5
C T
C

=

2
5
C
| +V
S
| + | V
S
| = 100V
| +V
S
| + | V
S
| = 300V
| +V
S
| + | V
S
| = 300V
| +V
S
| + | V
S
| = 100V
R
L
= 2K
R
L
= 2K R
L
= 2K
R
L
= 2K R
L
= 2K
V
IN
= 5V, t
r
=100ns
+V
S
V
S
0 25 50 75 100 125
TEMPERATURE, T (C)
0
5
10
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
D

(
W
)
2.5
15
150
7.5
12.5
20
17.5
PA83 PA83A
PA83U 399
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GENERAL
The bipolar output stage of this high voltage amplifer has
two distinct limitations.
1. The internal current limit, which limits maximum available
output current.
2. The second breakdown effect, which occurs whenever the
exceed specifed limits.
the following guidelines may save extensive analytical efforts:
+V
S
V
S
FIGURE 1. PROTECTION, INDUCTIVE LOAD
100 300 200
20
30
40
50
100
200
150
250 150 120 80
70
INTERNAL VOLTAGE DROP, SUPPLY TO OUTPUT (V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

-
V
S

(
m
A
)
INTERNAL CURRENT LIMIT
t

=

0
.
5
m
s
t

=

1
m
s
S
E
C
O
N
D

B
R
E
A
K
D
O
W
N
t

=

5
m
s
s
t
e
a
d
y

s
t
a
t
e
SOA
1. The following capacitive and inductive loads are safe:
V
S
C(MAX) L(MAX)
150V .7 F 1.5H
125V 2.0F 2.5H
100V 5.F 6.0H
75V 60F 30H
50V ALL ALL
120V or single supplies up to 120V.
3. Short circuits to the supply rails are safe with total supply
voltages up to 120V, e.g. 60V.
INDUCTIVE LOADS
pulse must be absorbed by the power supply. As a result, a tran-
sient will be superimposed on the supply voltage, the magnitude
of the transient being a function of its transient impedance and
current sinking capability. If the supply voltage plus transient
exceeds the maximum supply rating or if the AC impedance
of the supply is unknown, it is best to clamp the output and the
supply with a zener diode to absorb the transient.
PA83M/883
400 PA83MU
PA83M/883
Q
25C 150V V
IN
= 0, A
V
= 100 8.5 mA
OS
25C 150V V
IN
= 0, A
V
= 100 3 mV
OS
25C 15V V
IN
= 0, A
V
= 100 5.7 mV
B
25C 150V V
IN
= 0 50 pA
B
25C 150V V
IN
= 0 50 pA
OS
25C 150V V
IN
= 0 50 pA
Q
55C 150V V
IN
= 0, A
V
= 100 10 mA
OS
55C 150V V
IN
= 0, A
V
=100 5 mV
OS
55C 15V V
IN
= 0, A
V
= 100 7.7 mV
B
55C 150V V
IN
= 0 50 pA
B
55C 150V V
IN
= 0 50 pA
OS
55C 150V V
IN
= 0 50 pA
Q
125C 150V V
IN
= 0, A
V
= 100 10 mA
OS
125C 150V V
IN
= 0, A
V
= 100 5.5 mV
OS
125C 15V V
IN
= 0, A
V
= 100 8.2 mV
B
125C 150V V
IN
= 0 10 nA
B
125C 150V V
IN
= 0 10 nA
OS
125C 150V V
IN
= 0 10 nA
4 Output Voltage, I
O
= 75mA V
O
25C 85V R
L
= 1K 75 V
4 Output Voltage, I
O
= 29mA V
O
25C 150V R
L
= 5K 145 V
4 Current Limits I
CL
25C 30V R
L
= 100 75 125 mA
4 Stability/Noise E
N
25C 150V R
L
= 5K, A
V
= 1, C
L
= 10nF 1 mV
L
= 5K 20 80 V/s
4 Open Loop Gain A
OL
25C 150V R
L
= 5K, F = 10Hz 96 dB
L
= 5K, F = DC, V
CM
= 22.5V 90 dB
6 Output Voltage, I
O
= 40mA V
O
55C 45V R
L
= 1K 40 V
6 Output Voltage, I
O
= 29mA V
O
55C 150V R
L
= 5K 145 V
6 Stability/Noise E
N
55C 150V R
L
= 5K, A
V
= 1, C
L
= 10nF 1 mV
L
= 5K 20 80 V/s
6 Open Loop Gain A
OL
55C 150V R
L
= 5K, F = 10Hz 96 dB
L
= 5K, F = DC, V
CM
= 22.5V 90 dB
5 Output Voltage, I
O
= 40mA V
O
125C 45V R
L
= 1K 40 V
5 Output Voltage, I
O
= 29mA V
O
125C 150V R
L
= 5K 145 V
5 Stability/Noise E
N
125C 150V R
L
= 5K, A
V
= 1, C
L
= 10nF 1 mV
L
= 5K 20 80 V/s
5 Open Loop Gain A
OL
125C 150V R
L
= 5K, F = 10Hz 96 dB
L
= 5K, F = DC, V
CM
= 22.5V 90 dB
BURN IN CIRCUIT
100K
100K
+50V
50V
5
6
2
1
7 60
**
*
U.U.T
*
board.
= 125C.
SEP 2009
APEX PA83MUREVH
PA84 PA84A PA84S
PA84U 401
G
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B
A
G
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E
D
C
B
A
P r o d u c t I n n o v a t i o n F r o m PA84, PA84A, PA84S
FEATURES
FAST SETTLING TIME .1% in 1s (PA84S)
FULLY PROTECTED INPUT Up to 150v
APPLICATIONS
ANALOG SIMULATORS
DESCRIPTION
for output voltage swings up to 145V with a dual supply or
290V with a single supply. Two versions are available. The
new PA84S, fast settling amplifer can absorb differential input
overvoltages up to 50V while the established PA84 and PA84A
can handle differential input overvoltages of up to 300V. Both
versions are protected against common mode transients and
overvoltages up to the supply rails. High accuracy is achieved
with a cascode input circuit confguration. All internal biasing
is referenced to a zener diode fed by a FET constant current
source. As a result, the PA84 features an unprecedented sup-
ply range and excellent supply rejection. The output stage is
biased-on for linear operation. External phase compensation
allows for user fexibility in obtaining the maximum slew rate.
Fixed current limits protect these amplifers against shorts
to common at supply voltages up to 150V. For operation into
inductive loads, two external fyback pulse protection diodes
are recommended. However, a heatsink may be necessary to
maintain the proper case temperature under normal operating
conditions.
strate, thick flm resistors, ceramic capacitors and semiconduc-
tor chips to maximize reliability, minimize size and give top
8-pin TO-3 package is hermetically sealed and electrically
isolated. The use of compressible thermal isolation washers
EXTERNAL CONNECTION
TOP VIEW
1
2
3
4
5
6
7
8
V
S
+IN
IN
BAL
COMP
OUT
BAL
+V
S
NOTES:
1. Phase Compensation required
for safe operation.
2. Input offset trimpot optional.
Recommended value 100K.
R
C
C
C
PHASE COMPENSATION
GAIN
1
10
100
1000
C
C
10nF
500pF
50pF
none
R
C
200
2K
20K
none
TYPICAL APPLICATION
The PA84 is ideally suited to driving ink jet control units (often
a piezo electric device) which require precise pulse shape
control to deposit crisp clear date or lot code information on
product containers. The external compensation network has
been optimized to match the gain setting of the circuit and the
complex impedance of the ink jet control unit. The combination
of speed and high voltage capabilities of the PA84 form ink
droplets of uniform volume at high production rates to enhance
the value of the printer.
*Not included in PA84S.
+150V
150V
100K
PA84
10V
50K
INK JET
CONTROL
10K
DAC

4.7K
390pF
2
7
4
3
5
6
1
Q1 Q2
D1
D2
Q15
Q12B
Q9
C4
Q8
Q13
Q4
Q3
C1
Q16
Q17
Q5
C5
Q12A
Q14
C6
Q10
Q6
Q7
Q11
8
*
*
*
*
*
*
8-PIN TO-3
PACKAGE STYLE CE
PA84 PA84A PA84S
P r o d u c t
I n n o v a t i o n
F r o m
MAY 2009
APEX PA84UREVP
PA84 PA84A PA84S
402 PA84U
NOTES: * The specifcation of PA84A is identical to the specifcation for PA84/PA84S in applicable column to the left.
1. Signal slew rates at pins 5 and 6 must be limited to less than 1V/ns to avoid damage. When faster waveforms are unavoidable,
resistors in series with those pins, limiting current to 150mA will protect the amplifer from damage.
achieve high MTTF.
3. The power supply voltage for all tests is 150V, unless otherwise noted as a test condition.
5. +V
S
and V
S
SUPPLY VOLTAGE, +V
S
to V
S
300V
C
= 25C
2
17.5W
INPUT VOLTAGE, differential PA84/PA84A
1
300V
INPUT VOLTAGE, differential PA84S 50V
INPUT VOLTAGE, common mode
1
V
S

TEMPERATURE, pins for 10s max (solder) 300C
2
175C
CAUTION
PA84/PA84S PA84A
3
INPUT
C
= 25C 1.5 3 .5 1 mV
C
= 25 to +85C 10 25 5 10 V/C
C
= 25C .5 .2 V/V
C
= 25C 75 * V/kh
4
T
C
= 25C 5 50 3 10 pA
C
= 25C .01 * pA/V
4
T
C
= 25C 2.5 50 1.5 10 pA
OFFSET CURRENT, vs. supply T
C
= 25C .01 * pA/V
C
= 25C 10
11
*
INPUT CAPACITANCE T
C
= 25 to +85C 6 * pF
5
T
C
= 25 to +85C V
S
10 V
S
8.5 * * V
C
= 25 to +85C 130 * dB

GAIN
C
= 25C, R
L
= 120 * dB
OPEN LOOP GAIN at 10Hz. T
C
= 25C, R
L
= 3.5K 100 118 * * dB
GAIN BANDWIDTH PRODUCT@ 1MHz T
C
= 25C, R
L
= 3.5K, R
C
= 20K 75 * MHz
POWER BANDWIDTH, high gain T
C
= 25C, R
L
= 3.5K, R
C
= 20K 250 180 * kHz
POWER BANDWIDTH, low gain T
C
= 25C, R
L
= 3.5K, R
C
= 20K 120 * kHz
OUTPUT
VOLTAGE SWING
5
T
C
= 25C, I
O
= 40mA V
S
7 V
S
3 * * V
VOLTAGE SWING
5
T
C
= 25 to +85C, I
O
= 15mA V
S
5 V
S
2 * * V
CURRENT, peak T
C
= 25C 40 * mA
CURRENT, short circuit T
C
= 25C 50 * mA
SLEW RATE, high gain T
C
= 25C, R
L
= 3.5K, R
C
= 20K 200 150 * V/s
SLEW RATE, low gain T
C
= 25C, R
L
= 3.5K, R
C
= 2K 125 * V/s
SETTLING TIME .01% at gain = 100 T
C
= 25C, R
L
= 3.5K PA84S 2 s
SETTLING TIME .1% at gain = 100 R
C
= 20K, V
IN
= 2V step ONLY 1 s
SETTLING TIME .01% at gain = 100 T
C
= 25C, R
L
= 3.5K PA84/84A 20 20 s
SETTLING TIME .1% at gain = 100 R
C
= 20K, V
IN
= 2V step 12 12 s
POWER SUPPLY
VOLTAGE T
C
= 55C to +125C 15 150 * * V
C
= 25C 5.5 7.5 * * mA
THERMAL
6
T
C
= 55C to +125C, F > 60Hz 4.26 * C/W
C
= 55C to +125C, F < 60Hz 6.22 8.57 * * C/W
RESISTANCE, case to air T
C
= 55C to +125C 30 * C/W
TEMPERATURE RANGE, case Meets full range specifcations 25 +85 * * C
SPECIFICATIONS
PA84 PA84A PA84S
PA84U 403
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
55 100
30
70
80
CURRENT LIMIT
50
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/
H
z
)
1
FREQUENCY, F (Hz)
20
0
60
O
P
E
N

L
O
O
P

G
A
I
N
,

A
O
L

(
d
B
)
20
40
80
100
10
1.5
2.5
4.0
5.0
3.5
4.5
FREQUENCY, F (Hz)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
P
)
SLEW RATE VS. COMP
S
L
E
W

R
A
T
E

(
V
/
S
)
200
S
(V)
.4
.6
1.6
SLEW RATE VS. SUPPLY
N
O
R
M
A
L
I
Z
E
D

S
L
E
W

R
A
T
E

(
X
)
.8
1.4
COMMON MODE VOLTAGE
C
O
M
M
O
N

M
O
D
E

V
O
L
T
A
G
E
,

V
C
M

(
V
P
P
)
1
FREQUENCY, F (Hz)
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
120
10 100 1
FREQUENCY, F (Hz)
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)
0 150 250
2
OPEN LOOP GAIN

C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
m
A
)
0
INPUT NOISE
25 25 50 75
60
POWER RESPONSE
30 50 100 150
1.2
50 100 200
8
6
1K .1M
V
O
L
T
A
G
E

D
R
O
P

S
U
P
P
L
Y
,

V
S

V
O

(
V
)
R
E
L
A
T
I
V
E

O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
4
20
60
100
10 100
20
40
60
80
100
1.0
40
4
2.0
3.0
0 125
20 30 40 50
250 300
10K 1M 10M
FREQUENCY, F (Hz)
0
300
120
100 10 60 70
OUTPUT CURRENT, I
O
(mA)
140
1K 10K 1M 1K 10K 1M
120
140
200
70
30
20
50
150
100
1K 5K 20K 2K 200 500 10K
.1M .1M
30
50
100
200
300
15
1M 10K .1M 20K 50K .2M .5M
2
3
5
10
20
15
7
10 1K 10K .1M 100
CASE TEMPERATURE, T
C
(C) TOTAL SUPPLY VOLTAGE, V
S
(V)
2
15
100
1M .1M 50K .2M .5M
30
60
200
300
.3M .7M
20
150
150
EXT. COMPENSATION RESISTANCE, R
C
()
T
C
= 85C
T
C
= 25C
T
C
= 25C
R
L
= 3.5K
R
C
/
C
C

=

2
0
K
/
5
0
p
F
R
C
/
C
C

=

2
K
/
5
0
0
p
F
R
C
/
C
C
=

2
0
0
/
1
0
n
F
R
L
= 3.5K
T C

=

8
5
C
T C

=

2
5
C
T C

=

2
5
C
R
L
= 3.5K R
L
= 3.5K
R
C /
C
C
=

2
0
0
/
1
0
n
F
V
S
= 150V
V
S
= 150V
R
C

/C
C
=

2
0
K
/
5
0
p
F

R
C
/
C
C
=

2
K
/
5
0
0
p
F

0 25 50 75 100 125
TEMPERATURE, T (C)
0
5
10
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
D

(
W
)
2.5
15
150
7.5
12.5
20
17.5
PA84 PA84A PA84S
404 PA84U
OUTPUT PROTECTION
pulse must be absorbed by the power supply. As a result, a
transient will be superimposed on the supply voltage, the
magnitude of the transient being a function of its transient
impedance and current sinking capability. If the supply voltage
plus transient exceeds the maximum supply rating or if the AC
impedance of the supply is unknown, it is best to clamp the
output and the supply with a zener diode to absorb the transient.
STABILITY
Due to its large bandwidth the PA84 is more likely to oscillate
than lower bandwidth Power Operational Amplifers such as
the PA83 or PA08. To prevent oscillations, a reasonable phase
margin must be maintained by:
1. Selection of the proper phase compensation capacitor and
resistor. Use the values given in the table under external
connections and interpolate if necessary. The phase margin
can be increased by using a large capacitor and a smaller
resistor than the slew rate optimized values listed in the
table. The compensation capacitor may be connected to
common (in lieu of +V
S
) if the positive supply is properly
bypassed to common. Because the voltage at pin 8 is only a
few volts below the positive supply, this ground connection
requires the use of a high voltage capacitor.
2. Keeping the external sumpoint stray capacitance to ground
load resistance can be used with increased phase compen-
sation (see 1 above).
3. Connecting the amplifer case to a local AC common thus
preventing it from acting as an antenna.
GENERAL
The bipolar output stage of this high voltage operational
amplifer has two output limitations:
1. The internal current limit which limits maximum available
output current.
2. The second breakdown effect, which occurs whenever the
the following guidelines may save extensive analytical efforts:
1. The following capacitive and inductive loads are safe:
V
S
C(MAX) L(MAX)
150V 1.2F .7H
125V 6.0F 25H
100V 12F 90H
75V ALL ALL
150V or single supplies up to 150V.
3. Short circuits to the supply rails are safe with total supply
voltages up to 150V (i.e. 75V).
+V
S
V
S
FIGURE 1. PROTECTIVE,
INDUCTIVE LOAD
20
30
40
50
25
35
300 200 250 150 170
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S

(
m
A
)
t

=

5
m
s
t

=

1
m
s
S
T
E
A
D
Y

S
T
A
T
E
SOA
PA84M/883
PA84MU 405
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA84M/883
Q
25C 150V V
IN
= 0, A
V
= 100 7.5 mA
OS
25C 150V V
IN
= 0, A
V
= 100 3 mV
OS
25C 15V V
IN
= 0, A
V
= 100 5.7 mV
B
25C 150V V
IN
= 0 50 pA
B
25C 150V V
IN
= 0 50 pA
OS
25C 150V V
IN
= 0 50 pA
Q
55C 150V V
IN
= 0, A
V
= 100 9.5 mA
OS
55C 150V V
IN
= 0, A
V
= 100 5 mV
OS
55C 15V V
IN
= 0, A
V
= 100 7.7 mV
B
55C 150V V
IN
= 0 50 pA
B
55C 150V V
IN
= 0 50 pA
OS
55C 150V V
IN
= 0 50 pA
Q
125C 150V V
IN
= 0, A
V
= 100 9.5 mA
OS
125C 150V V
IN
= 0, A
V
= 100 5.5 mV
OS
125C 15V V
IN
= 0, A
V
= 100 8.2 mV
B
125C 150V V
IN
= 0 10 nA
B
125C 150V V
IN
= 0 10 nA
OS
125C 150V V
IN
= 0 10 nA
4 Output Voltage, I
O
= 40mA V
O
25C 47V R
L
= 1K 40 V
4 Output Voltage, I
O
= 28.6mA V
O
25C 150V R
L
= 5K 143 V
4 Output Voltage, I
O
= 15mA V
O
25C 80V R
L
= 5K 75 V
4 Current Limits I
CL
25C 20V R
L
= 100 36 70 mA
4 Stability/Noise E
N
25C 150V R
L
= 5K, A
V
= 1, C
L
= 10nF 1 mV
L
= 5K, C
C
= 50pF 100 600 V/s
4 Open Loop Gain A
OL
25C 150V R
L
= 5k, F = 10Hz 100 dB
L
= 5k, F = DC, V
CM
= 22.5V 90 dB
6 Output Voltage, I
O
= 40mA V
O
55C 47V R
L
= 1K 40 V
6 Output Voltage, I
O
= 28.6mA V
O
55C 150V R
L
= 5K 143 V
6 Output Voltage, I
O
= 15mA V
O
55C 80V R
L
= 5K 75 V
6 Stability/Noise E
N
55C 150V R
L
= 5K, A
V
= 1, C
L
= 10nF 1 mV
L
= 5K, C
C
= 50pF 100 600 V/s
6 Open Loop Gain A
OL
55C 150V R
L
= 5K, F = 10Hz 100 dB
6 Common Mode Rejection CMR -55C 32.5V R
L
= 5k, F = DC, V
CM
= 22.5V 90 dB
5 Output Voltage, I
O
= 30mA V
O
125C 37V R
L
= 1K 30 V
5 Output Voltage, I
O
= 28.6mA V
O
125C 150V R
L
= 5K 143 V
5 Output Voltage, I
O
= 15mA V
O
125C 80V R
L
= 5K 75 V
5 Stability/Noise E
N
125C 150V R
L
= 5, A
V
= 1, C
L
= 10nF 1 mV
L
= 5K, C
C
= 50pF 100 600 V/s
5 Open Loop Gain A
OL
125C 150V R
L
= 5K, F = 10Hz 100 dB
L
= 5k, F = DC, V
CM
= 22.5V 90 dB
BURN IN CIRCUIT
100K
100K
+50V
50V
5
6
2
1
7 60
**
*
U.U.T
*
board.
= 125C.
SEP 2009
APEX PA84MUREVH
PA85 PA85A
406 PA85U
PA85, PA85A
FEATURES
APPLICATIONS
PIEZO TRANSDUCER EXCITATION
DESCRIPTION
The PA85 is a high voltage, high power bandwidth MOSFET
operational amplifer designed for output currents up to 200mA.
Output voltages can swing up to 215V with a dual supply
and up to +440 volts with a single supply. The safe operating
area (SOA) has no second breakdown limitations and can be
observed with all types of loads by choosing an appropriate cur-
rent limiting resistor. High accuracy is achieved with a cascode
input circuit confguration. All internal biasing is referenced to a
bootstrapped zener-MOSFET current source. As a result, the
PA85 features an unprecedented supply range and excellent
supply rejection. The MOSFET output stage is biased on for
linear operation. External compensation provides user fexibility.
capacitors and silicon semiconductor chips to maximize reli-
ability, minimize size and give top performance. Ultrasonically
bonded aluminum wires provide reliable interconnections at all
operating temperatures. The 8-pin TO-3 package is hermeti-
cally sealed and electrically isolated. The use of compressible
isolation washers voids the warranty.
2
1
3
6
4 5
8 7
COMP C
OUT
+V
S
V
S
L
Q1 Q2
Q4
Q8
Q9
Q6 Q7
Q12
Q10A
Q10B
Q11
Q17
Q13
Q16
Q18
D1
D23
D2
IN +IN
PATENTED
TYPICAL APPLICATION
Dynamic focusing is the active correction of focusing voltage
as a beam traverses the face of a CRT. This is necessary in
high resolution fat face monitors since the distance between
cathode and screen varies as the beam moves from the center
of the screen to the edges. PA85 lends itself well to this function
since it can be connected as a summing amplifer with inputs
from the nominal focus potential and the dynamic correction.
The nominal might be derived from a potentiometer, or per-
haps automatic focusing circuitry might be used to generate
this potential. The dynamic correction is generated from the
sweep voltages by calculating the distance of the beam from
the center of the display.
z = x
2
+ y
2
R
IN1
R
F
R
CL
+225V
-225V
PA85
R
IN2
DC
FOCUS
X SWEEP
SAMPLE
Y SWEEP
SAMPLE
TO
FOCUS
GRID
1
2
3
4
5
6
7
8
TOP VIEW
CL
+Vs
+IN
Vs
COMP
OUT
R
CL
IN
C
C
COMP
R
C
PHASE COMPENSATION
Gain C
C
R
C
1 68pF 100
20 10pF 330
100 3.3pF 0
C
C
RATED FOR FULL
SUPPLY VOLTAGE
8-PIN TO-3
PACKAGE STYLE CE
MAY 2009
APEX PA85UREVO
PA85 PA85A
PA85U 407
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SUPPLY VOLTAGE, +V
S
to V
S
450V
OUTPUT CURRENT, continuous within SOA 200mA
C
= 25C
2
30W
S
2
150C
SPECIFICATIONS
PA85 PA85A
1
INPUT
3
5 50 3 10 pA
3
10 100 3 30 pA
11
*
4
V
S
15 * V
CM
= 90V 90 110 * * dB
NOISE 100kHz BW, R
S
= 1K, C
C
= 10pf 1 * Vrms
GAIN
OPEN LOOP, @ 15Hz R
L
= 2K, C
C
= OPEN 96 111 * * dB
L
= 2K, C
C
= 3.3pf 100 * MHz
POWER BANDWIDTH C
C
= 10pf 300 * kHz
C
C
= 3.3pf 500 * kHz
OUTPUT
VOLTAGE SWING
4
I
O
= 200mA Vs10 Vs6.5 * * V
VOLTAGE SWING
4
I
O
= 75mA V8.5 Vs6.0 * * V
VOLTAGE SWING
4
I
O
= 20mA V8.0 Vs5.5 * * V
CURRENT, continuous T
C
= 85C 200 * mA
SLEW RATE, A
V
= 20 C
C
= 10pf 400 * V/s
SLEW RATE, A
V
= 100 C
C
= OPEN 1000 700 * V/s
CAPACITIVE LOAD, A
V
= +1 Full temperature range 470 * * pf
C
= 10pf, 2V step 1 * s
RESISTANCE, no load R
CL
= 0 50 *
POWER SUPPLY
VOLTAGE
6
Full temperature range 15 150 225 * * * V
THERMAL
5
C
C
= 68pF, R
C
= 100. DC input specifcations are value given. Power
supply voltage is typical rating.
achieve high MTTF. Ratings apply only to output transistors. An additional 10W may be dissipated due to quiescent power.
4. +V
S
and V
S
CAUTION
PA85 PA85A
408 PA85U
0 25 50 75 100 125 150
CASE TEMPERATURE, T
C
(C)
0
8
24
32
POWER DERATING
O
U
T
P
U
T

S
T
A
G
E
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
.2M
FREQUENCY F (Hz)
225
45
0
PHASE RESPONSE
P
H
A
S
E
,

)
270
10 100 10K 100K
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/

H
z
)
10 10M
FREQUENCY, F (Hz)
20
0
60
120
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
20
40
80
100
0 250
OUTPUT CURRENT, I
O
(mA)
4
5
8
10
7
9
500K 5M
FREQUENCY, F (Hz)
25
125
500
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
P
)
100
250
1K 10K 10M
FREQUENCY, F (Hz)
20
80
140
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
60
100
1 1M
FREQUENCY, F (Hz)
20
40
140
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)
60
100
1 5 10 30
RESISTOR VALUE, R
CL
()
20
100
500
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
m
A
)
200
300
0 60
EXT. COMPENSATION CAPACITOR, C
C
(pF)
100
SLEW RATE
S
L
E
W

R
A
T
E
,

(
V
/
S
)
200
1000
90 15 45 10
FREQUENCY, F (Hz)
.003
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

(
%
)
.03
.05
100K 100 1K 10K
0 100 300 400
S
(V)
.90
1.10
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
1.05
100K 1M 2 20
50
INPUT NOISE VOLTAGE
1K
2
7
10
20
5
3
15
100 V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

V
O

(
V
)
135
16
40
POWER RESPONSE
10 100 1K 10K .1M
80
200
.95
1.00
.001
100 1K 10K .1M 1M
180
90
450
1.15
1.20
C
C
= 10pF
200
6
TC
=
1
2
5
C
T
C

=

1
2
5
C
T
C
= 25C
T
C
= 25C
T
C
= 55C
T
C
= 55C
75
50
1M
500
30 75
.005
.01
A
V
= 30
P
O
= 15W
C
C
= 10pf
R
L
= 1K
120
C
C
= 10pF
120
C
C

=

3
.
3
p
f
C
C

=

1
0
p
f
C
C

=

6
8
p
f
R
L
= 2K
2M 50K 100K 200K
C
C
= 68pF
C
C
= 10pF
C
C
= 3.3pF
20M
1M 10M 40M
C
C
= 68pF
C
C
= 3.3pF
PA85 PA85A
PA85U 409
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
CURRENT LIMIT
CL
) must be
minimum value is 1.4 ohm, however for optimum reliability the
30 ohms.
.7
R
CL
=
I
LIM
- .016
and the wire bonds.
NOTE: The output stage is protected against transient fyback.
S
V
O
(V)
25 50 75 100 250 500
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S
,

(
m
A
)
10
20
30
50
100
200
300
500
D
C
,

T
C
=

1
2
5
C
D
C
,

T
C
=

8
5
C
2
0
0
m
S
D
C
,

T
C
=

2
5
C
1
0
0
m
S
125
SOA
SAFE OPERATING CURVES
The safe operating area curves defne the maximum ad-
ditional internal power dissipation the amplifer can tolerate
when it produces the necessary output to drive an external
load. This is not the same as the absolute maximum internal
power dissipation listed elsewhere in the specifcation since the
quiescent power dissipation is signifcant compared to the total.
INPUT PROTECTION
Although the PA85 can withstand differential voltages up to
25V, additional external protection is recommended. Since
the PA85 is a high speed amplifer, low leakage, low capaci-
tance JFETs connected as diodes are recommended (e.g.
2N4416, Q1-Q4 in Figure 2). The differential input voltage will
be clamped to 1.4V. This is sufficient overdrive to produce
against. Reversals or opens on the negative supply rail is
STABILITY
The PA85 is externally compensated and performance can
be tailored to the application. Use the graphs of small signal
response and power response as a guide. The compensation
capacitor C
C
must be rated at 500V working voltage. An NPO
capacitor is recommended. The compensation network C
C
R
C

+V
S
IN
+IN
Z1
Z2
3
6
5
4
PA85
Q1 Q3
V
S
Q2
Q4
FIGURE 2.
PA85M
410 PA85MU
PA85M
SG PARAMETER*** SYMBOL TEMP. POWER TEST CONDITIONS MIN MAX UNITS
Q
25C 150V V
IN
= 0, A
V
= 100 25 mA
OS
25C 15V V
IN
= 0, A
V
= 100 4 mV
OS
25C 150V V
IN
= 0, A
V
= 100 2 mV
B
25C 150V V
IN
= 0 50 pA
B
25C 150V V
IN
= 0 50 pA
OS
25C 150V V
IN
= 0 100 pA
Q
55C 150V V
IN
= 0, A
V
= 100 28 mA
OS
55C 15V V
IN
= 0, A
V
= 100 6.4 mV
OS
55C 150V V
IN
= 0, A
V
= 100 4.4 mV
B
55C 150V V
IN
= 0 50 pA
B
55C 150V V
IN
= 0 50 pA
OS
55C 150V V
IN
= 0 50 pA
Q
125C 150V V
IN
= 0, A
V
= 100 28 mA
OS
125C 15V V
IN
= 0, A
V
= 100 7 mV
OS
125C 150V V
IN
= 0, A
V
= 100 5 mV
B
125C 150V V
IN
= 0 10 nA
B
125C 150V V
IN
= 0 10 nA
OS
125C 150V V
IN
= 0 10 nA
4 Output voltage, I
O
= 200mA V
O
25C 50V R
L
= 200 40 V
4 Output voltage, I
O
= 70mA V
O
25C 150V R
L
= 2K 141 V
4 Output voltage, I
O
= 20mA V
O
25C 48V R
L
= 2K 40 V
4 Current limits I
CL
25C 50V R
CL
= 10, R
L
= 200 60 112 mA
4 Stability/noise E
N
25C 150V C
C
= 68pF, R
C
= 100, A
V
= +1, C
L
= 470pF 1 mV
L
= 2K, A
V
= 100, C
C
= OPEN 400 V/s
4 Open loop gain A
OL
25C 150V R
L
= 2K, F = 15Hz, C
C
= OPEN 96 dB
4 Common-mode rejection CMR 25C 150V F = DC, V
CM
= 90V 90 dB
6 Output voltage, I
O
= 200mA V
O
55C 50V R
L
= 200 40 V
6 Output voltage, I
O
= 70mA V
O
55C 150V R
L
= 2K 141 V
6 Output voltage, I
O
= 20mA V
O
55C 48V R
L
= 2K 40 V
6 Stability/noise E
N
55C 150V C
C
= 68pF, R
C
= 100, A
V
= +1, C
L
= 470pF 1 mV
L
= 2K, A
V
= 100, C
C
= OPEN 400 V/s
6 Open loop gain A
OL
55C 150V R
L
= 2K, F = 15Hz, C
C
= OPEN 96 dB
CM
= 90V 90 dB
5 Output voltage, I
O
= 150mA V
O
125C 40V R
L
= 200 30 V
5 Output voltage, I
O
= 70mA V
O
125C 150V R
L
= 2K 141 V
5 Output voltage, I
O
= 20mA V
O
125C 48V R
L
= 2K 40 V
5 Stability/noise E
N
125C 150V C
C
= 68pF, R
C
= 100, A
V
= +1, C
L
= 470pF 1 mV
L
= 2K, A
V
= 100, C
C
= OPEN 400 V/s
5 Open loop gain A
OL
125C 150V R
L
= 2K, F = 15Hz, C
C
= OPEN 96 dB
CM
= 90V 90 dB
BURN IN CIRCUIT * These components are used to stabilize device due to
poor high frequency characteristics of burn in board.
= 125C.
*** An additional test is performed manually at
T
C
= 25C which stresses power supply, common mode
range and output swing to 225V (450V total).
100K
2.7
100
100K
+15V
15V
5
6
2
7
1
8
3
20
* *
*
*
U.U.T
4
68pF
SEP 2009
APEX PA85MUREVB
PA86
PA86U 411
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA86
DESCRIPTION
FEATURES
Wide Supply Voltage
APPLICATIONS
12Pin SIP
PACKAGE STYLE EU
LEAD FORM EW
ACTIVE LOAD
ACTIVE LOAD
BUFFER
CURRENT
LIMIT
VOUT
VOUT+
VOUT
V+
V
BLOCK DIAGRAM
JUL 2009
APEX PA86UREVB
PA78EU
12-pin SIP
I
LIM
V
OUT
C
C
- -V
S
-IN +IN C
R
+ C
C
+ +V
S
C
R
-
+V
S
C
C
+
R
C
+
R
F
R
IN
R
C
-
TO LOAD
_V
S
R
LIM
1 12 11 10 9 8 7 6 5 4 3 2
C
C
-
33pF
PA86
412 PA86U
SUPPLY VOLTAGE, +V
S
to V
S
250 V
S
+V
S
V
INPUT
-63 V/C
8

S
- 2 V
S
+ 5.5 V
NOISE, V
O
NOISE 500 nV/Hz
GAIN
OUTPUT
VOLTAGE SWING I
O
= 10mA |V
S
| - 2 V
VOLTAGE SWING I
O
= 100mA |V
S
| - 8.6 |V
S
| - 12 V
VOLTAGE SWING I
O
= 150mA |V
S
| - 10 V
P-P
+V
S
= 160V, V
S
= -160V 200 kHz
CL
= 6.2 44
POWER SUPPLY
VOLTAGE 10 50 125 V
SPECIFICATIONS
PA86
PA86U 413
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
THERMAL
RESISTANCE, DC, junction to air Full temperature range 12.21 C/W
C
is typical rating.
3. +V
S
and V
S
The PA86 is ideally suited for driving continuous drop
ink jet printers, in both piezo actuation and defection
applications. The high voltage of the amplifer creates
an electrostatic feld on the defection plates to con-
trol the position of the ink droplets. The rate at which
droplets can be printed is directly related to the rate
at which the amplifer can drive the plate to a different
electrostatic feld strength.
100K
0-5V
DAC
1.6K
-15V
R
C
C
C
R
CL
C
C
R
C
+335V
DEFLECTION
PLATE INK
DROPLETS
POWER DERATING
0
5
10
15
20
25
CASE TEMPERATURE, T
C
(C)
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
25 125 100 75 50 0
0
20
40
60
80
100
120
140
FREQUENCY (Hz)
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N

(
d
B
)
1 10 100 1K 10K 100K
0
2
4
6
8
10
12
0 50 100 150 200
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y

(
V
)
+V
S
SIDE DROP
-V
S
SIDE DROP
+V
S
100 1K 10K
FREQUENCY, (Hz)
40
20
0
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N

(
d
B
)
60
100
80
-V
S
CURRENT LIMIT
0
20
40
60
80
100
120
140
160
0 50
RESISTOR VALUE ()
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
m
A
)
V
S

+V
S
100
GAIN = -100
1 100 1000
FREQUENCY, (KHz)
200
150
100
50
0
O
U
T
P
U
T

V
O
L
T
A
G
E
,

(
V
)300
250
POWER RESPONSE
350
GAIN = -50
10
NO COMPENSATION
SOA
0.01
0.1
1
S
- V
O
(V)
C
U
R
R
E
N
T
,

A
M
P
S

(
A
)
10 100 1000
D
C
,

T
C
=

8
5
C
D
C
,

T
C
=

2
5
C
3
0
0
m
S
2
0
0
m
S
PULSE CURVES
PA86
414 PA86U
-35
-25
-15
-5
5
15
25
35
G
A
I
N
,
d
B
C
C
=0pF
C
C
=1pF
C
C
=2.2pF
C
C
=10pF
C
C
=22pF
C
C
=5pF
O
= 50V
P-P
A
V
=+26
R
BIAS
=100K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
V
S
=50V
FREQUENCY, KHz
10 1K 100 10K
-35
-25
-15
-5
5
15
25
35
G
A
I
N
,
d
B
C
C
=0pF
C
C
=1pF
C
C
=2.2pF
C
C
=10pF
C
C
=22pF
C
C
=5pF
O
= 5V
P-P
A
V
=+26
R
BIAS
=100K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
V
S
=50V
FREQUENCY, KHz
10 1K 100 10K
FREQUENCY, KHz
10 1K 100
-35
-25
-15
-5
5
15
25
35
45
G
A
I
N
,
d
B
C
C
=0pF
C
C
=1pF
C
C
=2.2pF
C
C
=10pF
C
C
=22pF
C
C
=5pF
O
= 500mV
P-P
A
V
=+26
R
BIAS
=100K
R
C
=3.3K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
V
S
=50V
10K
-25
-15
-5
5
15
25
35
45
G
A
I
N
,

d
B
500 mV
P-P
50 V
P-P
5 V
P-P
A
V
=+51
R
BIAS
=100K
R
C
=OPEN
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=50V
FREQUENCY, KHz
10 1K 100 10K
-90
-60
-30
0
30
60
90
120
150
180
P
H
A
S
E
,

C
S
=68pF
P
IN
=-40dBm
R
BIAS
=100K
R
S
= 48.7
V
S
=50V
FREQUENCY, KHz
100 1000 10 1
R
C
=OPEN, C
C
=0pF
R
C
=3.3K, C
C
=1pF
R
C
=3.3K, C
C
=2.2pF
R
C
=3.3K, C
C
=5pF
R
C
=3.3K, C
C
=10pF
R
C
=3.3K, C
C
=22pF
O
= 250mV
P-P
-90
-60
-30
0
30
60
90
120
150
180
P
H
A
S
E
,

C
S
=68pF
P
IN
=-40dBm
R
BIAS
=OPEN
R
S
= 48.7
FREQUENCY, KHz
100 1000 10 1
R
C
=OPEN, C
C
=0pF
R
C
=3.3K, C
C
=1pF
R
C
=3.3K, C
C
=2.2pF
R
C
=3.3K, C
C
=5pF
R
C
=3.3K, C
C
=10pF
R
C
=3.3K, C
C
=22pF
-20
0
20
40
60
80
100
FREQUENCY, KHz
100
G
A
I
N
,

D
b
C
S
=68pF
P
IN
=-40dBm
R
BIAS
=OPEN
R
S
= 48.7
V
S
=50V
1000 10 1
R
C
=OPEN, C
C
=0pF
R
C
=3.3K, C
C
=1pF
R
C
=3.3K, C
C
=2.2pF
R
C
=3.3K, C
C
=5pF
R
C
=3.3K, C
C
=10pF
R
C
=3.3K, C
C
=22pF
PA86
PA86U 415
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
C
AND R
C
-150
-120
-90
-60
-30
0
30
60
90
120
150
-2.4
-1.8
-1.2
-0.6
0
0.6
1.2
1.8
2.4
3.0
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
I
N
P
U
T

V
O
L
T
A
G
E
,

V
TIME, s
0 1 2 3 4 5 6 -1 -2 7 8
A
V
=+51
C
C
=68pF
C
L
=330pF
R
C
= 48
R
F
=75K
R
G
=1.5K
R
L
=OPEN
V
S
=150V
Out - 0pF
Out - 1pF & 3.3K
Out - 5pF & 3.3K
input
-3.0
2V
P-P
input2
TIME, s
-30
-20
-10
0
10
20
30
-1.5
-1
-0.5
0
0.5
1
1.5
TRANSIENT RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
I
N
P
U
T

V
O
L
T
A
G
E
,

V
A
V
=+26
C
C
=2.2pF
C
L
=8pF
R
C
=3.3K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
-2 0 2 4 6 8 10 12 -4
1V
P-P
input1
-15
-10
-5
0
5
10
15
TIME, s
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
I
N
P
U
T

V
O
L
T
A
G
E
,

V
-2 0 2 4 6 8 10 12 -4
TRANSIENT RESPONSE
A
V
=+26
C
C
=2.2pF
C
L
=8pF
R
C
=3.3K
R
F
=35.7K
R
G
=1.5K
R
L
=50K
SR+/SR- (25% - 75%)
SR+
SR-
A
V
=+26
C
L
=8pF
R
F
=35.6K
R
G
=1.5K
R
L
=50K
V
S
=150V
0 2 4 6 8 10 12 14 16
0
200
400
600
800
1000
S
R
,

V
/
s
SR+/SR- (25% -75%)
SR+
SR-
A
V
=+51
C
L
=8pF
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
0 2 4 6 8 10 12 14 16
0
200
400
600
800
1000
S
R
,

V
/
s
SR+/SR- (25% - 75%)
0
200
400
600
800
1000
SR+
SR-
S
R
,

V
/
s
A
V
=+101
C
L
=8pF
R
F
=25K
R
G
= 250
R
L
=50K
V
S
=150V
0 2 4 6 8 10 12 14 16
PA86
416 PA86U
0
5
10
15
20
25
30
1000 100 10
V
IN
=3V
P
A
V
=+51
C
L
=8pF
C
S
=68pF
R
F
=75K
R
G
=1.5K
R
L
=50K
R
S
= 48.7
V
S
=150V
I
S
,

m
A
V
IN
=6V
P
I
S
vs. V
IN
0
2
4
6
8
10
12
14
16
18
V
IN
, V
P-P
(100KHz sine wave)
A
V
=+51
C
L
=8pF
C
S
=68pF
R
F
=75K
R
G
=1.5K
R
L
=50K
R
S
= 48.7
V
S
=150V
I
S
,

m
A
1 9 8 7 6 5 4 3 2 0
PULSE RESPONSE
-0.05
0
0.05
0.1
0.15
0.2
TIME,s
I
S
,

A
6 0 -1
A
V
=+51
C
L
=8pF
R
F
=75K
R
G
=1.5K
R
L
=50K
V
S
=150V
5 4 3 2 1
TIME, s
0 30 10 8 6 4 2 -2 -6 -4 28 26 24 22 20 18 16 14 12
A
V
=-50
R
F
=75K
R
G
=1.5K
R
L
=50K
300pF, 1V
P-P
200pF, 1V
P-P
100pF, 1V
P-P
-80
-60
-40
-20
0
20
40
60
80
100
120
140
O
U
T
P
U
T
,

V
-80
-60
-40
-20
0
20
40
60
80
100
120
140
O
U
T
P
U
T
,

V
300pF, 2V
P-P
200pF, 2V
P-P
100pF, 2V
P-P
A
V
=-50
R
F
=75K
R
G
=1.5K
R
L
=50K
C
L
=8pF
TIME, s
0 30 10 8 6 4 2 -2 -6 -4 28 26 24 22 20 18 16 14 12
A
V
=-50
R
F
=75K
R
G
=1.5K
R
L
=50K
-80
-60
-40
-20
0
20
40
60
80
100
120
140
TIME, s
O
U
T
P
U
T
,

V
300pf, 3V
P-P
200pf, 3V
P-P
100pf, 3V
P-P
0 30 10 8 6 4 2 -2 -6 -4 28 26 24 22 20 18 16 14 12
SR+/SR- (25%-75%)
0
200
400
600
800
1000
1200
1400
1600
V
/
s
SR+(A
V
=-50)
SR-(A
V
=-50)
SR+(A
V
=+51)
SR-(A
V
=+51)
R
F
=75K
R
G
=1.5K
R
L
=50K
C
L
=8pF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SR+/SR- (25%-75%)
R
F
=75K
R
G
=1.5K
R
L
=50K
C
L
=8pF
0
200
400
600
800
1000
1200
S
R
+
/
S
R
-

V
/
s
SR+(A
V
=-25)
SR-(A
V
=-25)
SR+(A
V
=+26)
SR-(A
V
=+26)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PA86
PA86U 417
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
Please read Application note 1 General operating considerations which covers stability, power supplies, heat
tools that help automate tasks such as calculations for stability, internal power dissipation, and current limit. There
you will also fnd a complete application notes library, technical seminar workbook, and evaluation kits.
THEORY OF OPERATION
BIAS
, between C
C
- and V
S
+. The size of R
BIAS

will depend upon the application but 500A of added bias current shows signifcant improvement in the small signal
phase plots. Adding this resistor has little to no impact on small signal gain or large signal performance as under
these conditions the current in the input stage is elevated over its idle value. It should also be noted that connecting
a resistor to the upper supply only injects a fxed current and if the upper supply is fxed and well bypassed. If the
application includes variable or adjustable supplies, a current source diode could also be used. These two terminal
components combine a JFET and resistor connected within the package to behave like a current source.
BIAS
PA86
418 PA86U
supply voltage (+V
S
to V
S
temperature.
C
- and V
S
S
to V
S
).
P-P
to 15V
P-P
The output becomes clipped by the supply rails and the amplifer is no longer operating in a closed loop fashion. The
rise and fall times become faster as the dynamic current sources are providing maximum current for slewing. The
result of this amplifer architecture is that it slews fast, but allows good control of overshoot for large input signals.
This can be seen clearly in the large signal Transient Response plots.
The MOSFET output stage of the PA86 is not limited by second breakdown
considerations as in bipolar output stages. Only thermal considerations of
the package and current handling capabilities limit the Safe Operating Area.
The SOA plots include power dissipation limitations which are dependent
upon case temperature. Keep in mind that the dynamic current sources
which drive high slew rates can increase the operating temperature of the
amplifer during periods of repeated slewing. The plot of supply current vs.
input signal amplitude for a 100 kHz signal provides an indication of the
supply current with repeated slewing conditions. This application depen-
dent condition must be considered carefully.
The output stage is self-protected against transient fyback by the parasitic
body diodes of the output stage. However, for protection against sustained
high energy fyback, external, fast recovery diodes must be used.
CURRENT LIMIT
LIM
, must be connected as shown in the external connections
diagram. For maximum reliability and protection, the largest resistor value should be used. The minimum practi-
cal value for R
LIM
is about 12. However, refer to the SOA curves for each package type to assist in selecting the
optimum value for R
LIM
in the intended application. Current limit may not protect against short circuit conditions with
supply voltages over 200V.
C
/ C
C
loops in these paths pick up noise and increase the likelihood of LC interactions and oscillations.
POWER DERATING
0
5
10
15
20
25
CASE TEMPERATURE, T
C
(C)
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
25 125 100 75 50 0
0
20
40
60
80
100
120
140
FREQUENCY (Hz)
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N

(
d
B
)
1 10 100 1K 10K 100K
0
2
4
6
8
10
12
0 50 100 150 200
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y

(
V
)
+V
S
SIDE DROP
-V
S
SIDE DROP
+V
S
100 1K 10K
FREQUENCY, (Hz)
40
20
0
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N

(
d
B
)
60
100
80
-V
S
CURRENT LIMIT
0
20
40
60
80
100
120
140
160
0 50
RESISTOR VALUE ()
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
m
A
)
V
S

+V
S
100
GAIN = -100
1 100 1000
FREQUENCY, (KHz)
200
150
100
50
0
O
U
T
P
U
T

V
O
L
T
A
G
E
,

(
V
)300
250
POWER RESPONSE
350
GAIN = -50
10
NO COMPENSATION
SOA
0.01
0.1
1
S
- V
O
(V)
C
U
R
R
E
N
T
,

A
M
P
S

(
A
)
10 100 1000
D
C
,

T
C
=

8
5
C
D
C
,

T
C
=

2
5
C
3
0
0
m
S
2
0
0
m
S
PULSE CURVES
PA88 PA88A
PA88U 419
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA88, PA88A
FEATURES
APPLICATIONS
DESCRIPTION
The PA88 is a high voltage, low quiescent current MOSFET
operational amplifer designed for output currents up to 100mA.
Output voltages can swing up to 215V with a dual supply
and up to +440 volts with a single supply. The safe operating
area (SOA) has no second breakdown limitations and can be
observed with all types of loads by choosing an appropriate cur-
rent limiting resistor. High accuracy is achieved with a cascode
input circuit confguration. All internal biasing is referenced to a
bootstrapped zener-MOSFET current source. As a result, the
PA88 features an unprecedented supply range and excellent
supply rejection. The MOSFET output stage is biased on for
This hybrid circuit utilizes beryllia (BeO) substrates, thick
flm resistors, ceramic capacitors and semiconductor chips to
use of compressible thermal isolation washers and/or improper
mounting torque will void the product warranty. Please see
TYPICAL APPLICATION
Piezo positioning may be applied to the focusing of
segmented mirror systems. The composite mirror may be
composed of hundreds of elements, each requiring focusing
under computer control. In such complex systems the PA88s
advantage of low quiescent power consumption reduces
the costs of power supplies and cooling, while providing the
interface between the computer and the high voltage drive to
the piezo positioners.
F
R
PA88
IN
R
PIEZO DRIVE
S
V
S
+V
OUT
V
C
C
COMPUTER
FOCUS
COMMAND
VOLTAGE
1
2 3
4
5
6 7
8
TOP VIEW
CL
+Vs
+IN
Vs
COMP
OUT
R
CL
IN
C
C
PHASE COMPENSATION
GAIN C
C
1
10
20
100
68pf
33pf
15pf
3.3pf
COMP
R
C
100
100
100
W
W
R
C
W
R
CL
=
.7
I
LIM
C
C
RATED FOR FULL
SUPPLY VOLTAGE
PATENTED
2
1
3
6
4 5
8 7
+ IN
COMP
CL
OUT
+V
S
V
S
Q1 Q2
Q4
Q8
Q9
Q6 Q7
Q12
Q10A
Q10B
Q11
Q17
Q13
Q16
Q18
D2
D19
D1
IN
8-PIN TO-3
PACKAGE STYLE CE
MAY 2009
APEX PA88UREVN
PA88 PA88A
420 PA88U
SUPPLY VOLTAGE, +V
S
to V
S
450V
OUTPUT CURRENT, source, sink See SOA
C
= 25C 15W
S

2
150C
SPECIFICATIONS
PA88 PA88A
1
INPUT
3
5 50 3 10 pA
3
2.5 100 3 20 pA
11
*
4
V
S
15 * V
CM
= 90V 90 110 * * dB
NOISE 100kHz BW, R
S
= 1K, C
C
= 15pf 2 * Vrms
GAIN
OPEN LOOP, @ 15Hz R
L
= 2K, C
C
= OPEN 96 111 * * dB
L
= 2K, C
C
= 15pf, R
C
= 100 2.1 * MHz
POWER BANDWIDTH R
L
= 2K, C
C
= 15pf, R
C
= 100 6 * kHz
OUTPUT
VOLTAGE SWING
4
Full temp. range, I
O
= 75mA V
S
16 V
S
14 * * V
VOLTAGE SWING
4
Full temp. range, I
O
= 20mA V
S
10 V
S
5.2 * * V
C
= 85C 100 * mA
SLEW RATE, A
V
= 20 C
C
= 15pf, R
C
= 100 8 * V/s
SLEW RATE, A
V
= 100 C
C
= OPEN 30 * V/s
CAPACITIVE LOAD, A
V
= +1 Full temperature range 470 * pf
C
= 15pf, R
C
= 100, 2V step 10 * s
CL
= 0 100 *
POWER SUPPLY
VOLTAGE
6
See note 6 15 200 225 * * * V
CURRENT, quiescent, 1.7 2 * * mA
THERMAL
5
C
C
= 68pF, R
C
= 100. DC input specifcations are value given. Power
supply voltage is typical rating.
achieve high MTTF.
4. +V
S
and V
S
CAUTION
PA88 PA88A
PA88U 421
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
0 25 50 75 100 125 150
TEMPERATURE, T (C)
0
2.5
7.5
10
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
1 100 1K 1M
FREQUENCY, F (Hz)
210
180
60
0
PHASE RESPONSE
P
H
A
S
E
,

)
10 100 10K 1M
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/
H
z
)
1 10M
FREQUENCY, F (Hz)
20
0
60
120
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
20
40
80
100
1K 2K 100K
FREQUENCY, F (Hz)
25
125
500
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
P
)
75
250
1 10 1M
FREQUENCY, F (Hz)
20
80
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
60
100
1 1M
FREQUENCY, F (Hz)
20
40
140
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)
60
100
3 10 20 100
CURRENT LIMIT RESISTOR, R
CL
()
10
30
200
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
m
A
)
50
70
0 50
C
(pF)
1
SLEW RATE
S
L
E
W

R
A
T
E
,

(
V
/
S
)
2
50
70 10 30 3
FREQUENCY, F (Hz)
.001
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

(
%
)
1
10
30K 30 300 3K
0 100 300
S
(V)
1.0
2.0
QUIESCENT CURRENT
Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
m
A
)
1.75
1K 10K 5 50
20
INPUT NOISE
1K
2
7
10
20
3
5
15
10 10K .1M
120
5
15
POWER RESPONSE
5K
10 100 1K 10K .1M
80
200
1.25
1.5
.0001
100 1K 10K .1M 1M
150
90
450
2.25
2.5
50
20
20 60
.01
.1
120
120
12.5
T
C
= 125C
T
C
= 25C
T
C
= -55C
10
30
10K 20K 50K
R
L
= 2K
P
O
= 2.5W
A
V
= 30
100 .1M
C
C
= 15pF
C
C
= 33pF
C
C
= 68pF
C
C
= 3.3pF
10M
C
C
= 33pF
C
C
= 3.3pF
C
C
= 68pF
C
C
= 3.3pF
C
C
= 68pF
C
C
= 33pF
120
100
150
C
C

=

3
.
3
p
f
C
C

=

1
5
p
f
C
C

=

3
3
p
f
C
C

=

6
8
p
f
3K
100
40
3
5
10
30
T = T
C
T = T
A
2
4
6
8
10
12
14
16
18
20
20 40 60 80 100
OUTPUT CURRENT, I
O
(mA)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
s
-
V
o
,

(
V
)
T
C
=-55C
T
C
=125C
T
C
=85C
Negative
Positive
T
C
=25C
PA88 PA88A
422 PA88U
GENERAL
CURRENT LIMIT
CL
) must be
150 ohms.
.7
R
CL
=
I
LIM
and the wire bonds.
SOA
S
V
O
(V)
25 50 75 100 250 500
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S
,

(
m
A
)
5
10
15
25
50
100
150
250
D
C
,

T
C
=

1
2
5
C
D
C
,

T
C
=

8
5
C
2
0
0
m
S
D
C
,

T
C
=

2
5
C
1
0
0
m
S
125
INPUT PROTECTION
Although the PA88 can withstand differential input voltages
up to 25V, additional external protection is recommended,
and required at total supply voltages above 300 volts. In most
applications 1N4148 or 1N914 signal diodes are sufficient (D1,
D2 in Figure 2a). In more demanding applications where low
leakage or low capacitance are of concern 2N4416 or 2N5457-
2N5459 JFETs connected as diodes will be required (Q1, Q2
in Figure 2b). In either case the input differential voltage will
be clamped to .7V. This is sufficient overdrive to produce
power-off polarity reversal as well as line regulation.
STABILITY
The PA88 has sufficient phase margin to be stable with
most capacitive loads at a gain of 4 or more, using the rec-
ommended phase
compensation.
The PA88 is exter-
nally compensated
and performance can
be tailored to the
application. Use the
graphs of small signal
response and power
response as a guide.
The compensation
capacitor C
C
must
be rated at 500V
working voltage. An
NPO capacitor is
recommended. The
compensation net-
work C
C
R
C
must be
mounted closely to
the amplifer pins 7
and 8 to avoid spuri-
ous oscillation.
PA88
+V
S
IN
+IN
Z1
Z2
D2 D1
3
6
5
4
+V
S
IN
+IN
Z1
Z2
3
6
5
4
PA88
Q1 Q2
a.
b.
V
S
V
S
PA89 PA89A
PA89U 423
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
TYPICAL APPLICATION
Ultra-high voltage capability combined with the bridge am-
plifer confguration makes it possible to develop +/1000 volt
peak swings across a piezo element. A high gain of 50 for
A1 insures stability with the capacitive load, while noise-gain
compensation Rn and Cn on A2 insure the stability of A2 by
operating in a noise gain of 50.
A1
PA89
A2
PA89
R
50R
600V
V
IN
PIEZO
TRANSDUCER
50R
R
+600V
600V
+600V
SINGLE AXIS MICRO-POSITIONING
50R
Cn
PATENTED
PHASE COMPENSATION
Gain C
C
R
C
1 470pF 470
10 68pF 220
15 33pF 220
100 15pF 220
Note: C
C
must be rated for full supply voltage Vs to +Vs.
See details under EXTERNAL COMPONENTS.
TOP
VIEW
IN
+IN
N/C
N/C
V
S

OUT
RESERVED
RESERVED
COMP
COMP
+V
C
S
C
C
R
C
L
R
CL
R =
CL
I
LIM
.7
1
2
3
4
5
6
12
11
10
9
8
7
TOP
VIEW
FEATURES
1140V P-P SIGNAL OUTPUT
75 mA CONTINUOUS OUTPUT CURRENT
HERMETIC SEALED PACKAGE
INPUT PROTECTION
APPLICATIONS
ELECTROSTATIC DEFLECTION
SEMICONDUCTOR TESTING
DESCRIPTION
The PA89 is an ultra high voltage, MOSFET operational ampli-
fer designed for output currents up to 75 mA. Output voltages
can swing over 1000V p-p. The safe operating area (SOA) has
no second breakdown limitations and can be observed with
all types of loads by choosing an appropriate current limiting
resistor. High accuracy is achieved with a cascode input circuit
confguration and 120dB open loop gain. All internal biasing is
referenced to a bootstrapped zener-MOSFET current source,
giving the PA89 a wide supply range and excellent supply
rejection. The MOSFET output stage is biased for class A/B
The PA89 is 100% gross leak tested to military standards for
long term reliability.
strate, thick flm resistors, ceramic capacitors and semiconduc-
tor chips to maximize reliability, minimize size and give top
MO-127 High Voltage, Power Dip package is hermetically
sealed and electrically isolated. The use of compressible
thermal washers will void the product warranty.
SIMPLIFIED SCHEMATIC
7
6
8
5
2 1
10 9
+IN IN
COMP
C
OUT
+V
S
V
S
L
Q1 Q2
Q3
Q19
Q20
Q22 Q23
Q26
Q25A Q25B
Q29
Q36
Q45
Q44
Q42
D1
D57
D30
D35
D34
D31
D5
HIGH VOLTAGE MO-127
PACKAGE STYLE DC
MAY 2009
APEX PA89UREVJ
PA89 PA89A
424 PA89U
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS SUPPLY VOLTAGE, +V
S
to V
S
1200V
OUTPUT CURRENT, within SOA 100mA
C
= 25C 40W
S
25V
2
150C
TEMPERATURE, storage 65 to 125C
OPERATING TEMPERATURE RANGE, case 55 to 125C
PA89 PA89A
1
INPUT
3
5 50 3 10 pA
BIAS CURRENT,vs. supply .01 * pA/V
3
5 50 3 20 pA
5
* M
4
S
50 * V
CM
= 90V 96 110 * * dB
S
= 10K, C
C
= 15pF 4 V RMS
GAIN
OPEN LOOP GAIN at 10Hz R
L
= 10k, C
C
= 15pF 108 120 * * dB
L
= 10k, C
C
= 15pF, A
V
= 100 10 * MHz
POWER BANDWIDTH R
L
= 10k, C
C
= 15pF, V
O
= 500V p-p 5 * kHz
PHASE MARGIN Full temperature range, A
V
= 10 60 *
OUTPUT
VOLTAGE SWING
4
I
O
= 75mA V
S
45 V
S
30 * * V
VOLTAGE SWING
4
Full temperature range, I
O
= 20mA V
S
20 V
S
12 * * V
CURRENT, continuous Full temperature range 75 * mA
SLEW RATE C
C
= 15pF, A
V
= 100 12 16 * * V/s
CAPACITIVE LOAD, Av = 10 Full temperature range 1 * nF
CAPACITIVE LOAD, Av>10 Full temperature range SOA *
SETTLING TIME to .1% R
L
= 10K, 10V step, Av = 10 2 * s
POWER SUPPLY
VOLTAGE, V
S
4
Full temperature range 75 500 600 * * * V
CURRENT, quiescent 4.8 6.0 * * mA
THERMAL
5
Full temperature range, F > 60Hz 2.1 2.3 * * C/W
RESISTANCE, DC, junction to case Full temperature range, F < 60Hz 3.3 3.5 * * C/W
CAUTION
C
= 25C, C
C
= 68pF, R
C
= 220, and V
S
= 500V. Input parameters for bias currents and offset volt-
age are values given.
achieve high MTTF.
4. +V
S
and V
S
5. Rating applies only if the output current alternates between both output transistors at a rate faster than 60Hz.
PA89 PA89A
PA89U 425
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
0 25 50 75 100 125 150
CASE TEMPERATURE, T
C
(C)
0
8
24
32
POWER DERATING
O
U
T
P
U
T

S
T
A
G
E
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
1 100 1K 10M
FREQUENCY F (Hz)
270
180
45
0
PHASE RESPONSE
P
H
A
S
E
,

)
135
225
10 100 10K 100K
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

e
N

(
n
V
/
H
z
)
1 100 10M
FREQUENCY, F (Hz)
20
0
60
120
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
20
40
80
100
1K 3K 30K 100K
FREQUENCY, F (Hz)
100
500
1000
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
300
600
1 100 10K 10M
FREQUENCY, F (Hz)
0
60
100
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
20
40
80
1 10M
FREQUENCY, F (Hz)
0
20
100
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)
40
80
0 40 60 100
RESISTOR VALUE, R
CL
()
0
40
100
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
m
A
)
60
80
0 75
C
(pF)
5
SLEW RATE VS COMP
S
L
E
W

R
A
T
E
,

(
V
/

S
)
10
15
20
100 25 50. 30 300 3K
FREQUENCY, F (Hz)
.01
.1
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

T
H
D

(
%
)
1
10
100K 100 1K 10K
0 200 800 1200
S
(V)
.9
1.10
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
1.05
10 1K 100K 1M 20 80
20
30K
INPUT NOISE VOLTAGE
1K
2
7
10
20
3
5
15
15pf, 220
33pf, 220
68pf, 220
10 10K 100K 1M
90
16
40
POWER RESPONSE
800
1200
10K
C
C
= 68pf
C
C
= 33pf
C
C
= 15pf
10 100 1K 10K 100K 1M
60
400 600 1000
.95
1.00
68pf, 220
33pf, 220
15pf, 220
V
O
= 800Vpp
V
O
= 600Vpp
V
O
= 400Vpp
V
O
= 100Vpp
.001
10 1K 10K 100K 1M
C
C
, R
C
C
C
, R
C R
C
= 220
V
S
= 500V
C
C
= 15pf, R
C
= 220
R
L
= 11K
A
V
= 100
0
5
10
15
20
25
30
35
40
45
OUTPUT CURRENT, I
O
,(mA)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S
-
V
O

(
V
)
25 50 75 100 0
PA89 PA89A
426 PA89U
GENERAL
STABILITY
Although the PA89 can be operated at unity gain, maximum
slew rate and bandwidth performance was designed to be
obtained at gains of 10 or more. Use the small signal response
and phase response graphs as a guide. In applications where
gains of less than 10 are required, use noise gain compensa-
tion to increase the phase margin of the application circuit as
illustrated in the typical application drawing.
and the wire bonds.
ditional internal power dissipation the amplifer can tolerate
when it produces the necessary output to drive an external
load. This is not the same as the absolute maximum internal
power dissipation listed elsewhere in the specifcation since the
quiescent power dissipation is signifcant compared to the total.
EXTERNAL COMPONENTS
The very high operating voltages of the PA89 demand con-
sideration of two component specifcations rarely of concern in
building op amp circuits: voltage rating and voltage coefficient.
The compensation capacitance C
C
must be rated for the
full supply voltage range. For example, with supply voltages
of 500V the possible voltage swing across C
C
is 1000V. In
addition, a voltage coefficient less than 100PPM is recom-
mended to maintain the capacitance variation to less than
5% for this example. It is strongly recommended to use the
highest quality capacitor possible rated at least twice the total
supply voltage range.
Of equal importance are the voltage rating and voltage coef-
fcient of the gain setting resistances. Typical voltage ratings of
low wattage resistors are 150 to 250V. In the above example
1000V could appear across the feedback resistor. This would
require several resistors in series to obtain the proper voltage
rating. Low voltage coefficient resistors will insure good gain
linearity. The wattage rating of the feedback resistor is also of
concern. A 1 megohm feedback resistor could easily develop
1 watt of power dissipation.
Though high voltage rated resistors can be obtained,
a 1 megohm feedback resistor comprised of fve 200Kohm,
1/4 watt metal flm resistors in series will produce the proper
voltage rating, voltage coefficient and wattage rating.
CURRENT LIMIT
For proper operation the current limit resistor (R
CL
) must be
is calculated as follows with the maximum practical value of
150 ohms.
.7
R
CL
=
I
LIM
When setting the value for R
CL
allow for the load current as
well as the current in the feedback resistor. Also allow for the
temperature coefficient of the current limit which is approxi-
mately -0.3% /C of case temperature rise.
CAUTIONS
The operating voltages of the PA89 are potentially lethal.
During circuit design, develop a functioning circuit at the lowest
possible voltages. Clip test leads should be used for hands
off measurements while troubleshooting.
Unidirectional zener diode transient absorbers are recom-
300 500 80010001200
S
V
O
(V)
3
10
30
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S

(
m
A
)
100
200
5
15
50
100mS
25C
85C
125C
T = T
CASE
10mS
100
SOA
PA90
PA90U 427
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA90
FEATURES
APPLICATIONS
PROGRAMMABLE POWER SUPPLIES UP
TO 390V
Q1 Q2
R1 R2 C1 R3
Q3
CC1
12
11
1
4
5
9
6
10
2
7
8
CC2
3
Q6
Q5
R5
R8 R9
Q15
R11 R12
Q16
Q12
Q8
R4
R7
Q4
ILIM
OUT
Q17
R10
Q13
Q11
+V
S
IN
+IN
V
S
I
Q
R6
Q14B Q14A
DESCRIPTION
The PA90 is a high voltage, low quiescent current
MOSFET operational amplifer designed as a low cost
solution for driving continuous output currents up to
200mA and pulse currents up to 350mA. The safe oper-
ating area (SOA) has no second breakdown limitations
and can be observed for all type loads by choosing
an appropriate current limiting resistor. The MOSFET
output stage is biased AB for linear operation. Exter-
nal compensation provides fexibility in choosing band-
width and slew rate for the application. Apex Precision
Powers Power SIP package uses a minimum of board
space allowing for high density circuit boards. The 12-
pin PowerSIP package is electrically isolated.
JUN 2009
APEX PA90UREVJ
1 2 3 4 5 6 7 8 9 10
IN +IN
R
CL
+V
s
V
s
TO LOAD
AND FEEDBACK
11 12
R
c
C
c
*
*
(See text.)
* Bypassing required.
I
Q
12-pin SIP
PACKAGE
STYLE DP
See package EE
PA90
428 PA90U
CAUTION
SUPPLY VOLTAGE, +V
S
to -V
S
400 V
OUTPUT CURRENT, source, sink, peak, within SOA 350 mA
C
= 25C 30 W
S
V
S
V
1
Min Typ Max Units
AMPLIFIER INPUT
OFFSET VOLTAGE, initial 0.5 2 mV
15 50 V/C
OFFSET VOLTAGE vs. supply 10 25 V/V
OFFSET VOLTAGE vs. time 75 V/kHz
BIAS CURRENT, initial 200 2000 pA
BIAS CURRENT vs. supply 4 pA/V
11
(Note 3)
V
S
15 V
CM
= 90V 80 98 dB
NOISE 100KHz bandwidth, R
S
= 1K,
C
C
= OPEN
1 V RMS
GAIN
OPEN LOOP @ 15Hz R
L
= 2K, C
C
= OPEN 94 111 dB
GAIN BANDWIDTH PRODUCT @ 1MHz R
L
= 2K, C
C
= OPEN 100 MHz
POWER BANDWIDTH R
L
= 2K, C
C
= OPEN 470 kHz
OUTPUT
O
= 200mA V
S
12 V
S
10 V
CURRENT, continuous 200 mA
SLEW RATE, A
V
= 100 C
C
= OPEN 240 300 V/S
CAPACITIVE LOAD, A
V
= +1 Full temperature range 470 pF
SPECIFICATIONS
PA90
PA90U 429
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
C
= 25C).
3. +V
S
and V
S
60Hz.
1
Min Typ Max Units
SETTLING TIME to 0.1% C
C
= OPEN, 2V step 1 S
RESISTANCE, no load 50
POWER SUPPLY
VOLTAGE (Note 5) 40 150 200 V
THERMAL
RESISTANCE, AC, junction to case (Note 4) Full temp range, F > 60Hz 2.5 C/W
RESISTANCE, DC, junction to case Full temp range, F < 60Hz 4.2 C/W
TEMPERATURE RANGE, case Meets full range specifcations -25 +85 C
TYPICAL APPLICATION
Piezo positioning may be applied to the focusing of segment-
ed mirror systems. The composite mirror may be composed
of hundreds of elements, each requiring focusing under com-
puter control. In such complex systems the PA90 reduces
the costs of power supplies and cooling with its advantages
of low cost and low quiescent power consumption while in-
creasing circuit density with the SIP package.
F
R
PA90
IN
R
1
2
6
7,8
9,10
11,12
PIEZO DRIVE
S
V
S
+V
OUT
V
COMPUTER
FOCUS
COMMAND
VOLTAGE
CL
R
10
HARMONIC DISTORTION
100K 100 1K 10K
100k
FREQUENCY F (Hz)
135
90
PHASE RESPONSE
P
H
A
S
E
,

)
10 100 10K 100K
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V

(
n
V
H
z
)
100K
FREQUENCY, F (Hz)
10
0
30
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
10
20
40
50
0 0.15 0.2
OUTPUT CURRENT, I
O
(A)
5
6
4.5
4
5.5
1M
FREQUENCY, F (Hz)
50
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
200
100
80
70
60
400
300
0 8 12 20 24
RESISTOR VALUE, R
CL
()
0
.05
.2
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
.1
.15
0.1
C
(pF)
10
SLEW RATE
S
L
E
W

R
A
T
E
,

(
V
/
S
)
50
40
30
20
1K
10 100
FREQUENCY, F (Hz)
D
I
S
T
O
R
T
I
O
N
,

(
%
)
1
25 50 100
CASE TEMPERATURE, T
C
(C)
1.1
NORMALIZED QUIES. CURRENT
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
1.0
4 16
INPUT NOISE VOLTAGE
1K
2
7
10
20
5
3
15
.05
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

V
O

(
V
)
225
POWER RESPONSE
75
.001
1M 10M
270
180
125
1.2
1.3
0.1
3.5
100K
700
300
200
100
70
500
1
.01
.1
10K
1M 10M
C
C
= 68 pF
C
C
= 10 pF
C
C
= 4.7 pF
C
C
= OPEN
C
C
= 68 pF
C
C
= 10 pF
C
C
= 4.7 pF
C
C
= OPEN
C
C

=

O
P
E
N
C
C

=

4
.
7
p
F
C
C

=

1
0
p
F
C
C

=

6
8
p
F
0 25 50 75 100 125 150
CASE TEMPERATURE, T
C
(C)
0
8
24
32
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
16
40
R
L
= 1K
V
S
= 200V
A
V
= 63
P
O
= 5W
P
O
= 1W
P
O
= 17.6W
PA90
430 PA90U
10
HARMONIC DISTORTION
100K 100 1K 10K
100k
FREQUENCY F (Hz)
135
90
PHASE RESPONSE
P
H
A
S
E
,

)
10 100 10K 100K
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V

(
n
V
H
z
)
100K
FREQUENCY, F (Hz)
10
0
30
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
10
20
40
50
0 0.15 0.2
OUTPUT CURRENT, I
O
(A)
5
6
4.5
4
5.5
1M
FREQUENCY, F (Hz)
50
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
200
100
80
70
60
400
300
0 8 12 20 24
RESISTOR VALUE, R
CL
()
0
.05
.2
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
.1
.15
0.1
C
(pF)
10
SLEW RATE
S
L
E
W

R
A
T
E
,

(
V
/
S
)
50
40
30
20
1K
10 100
FREQUENCY, F (Hz)
D
I
S
T
O
R
T
I
O
N
,

(
%
)
1
25 50 100
CASE TEMPERATURE, T
C
(C)
1.1
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
1.0
4 16
INPUT NOISE VOLTAGE
1K
2
7
10
20
5
3
15
.05
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

V
O

(
V
)
225
POWER RESPONSE
75
.001
1M 10M
270
180
125
1.2
1.3
0.1
3.5
100K
700
300
200
100
70
500
1
.01
.1
10K
1M 10M
C
C
= 68 pF
C
C
= 10 pF
C
C
= 4.7 pF
C
C
= OPEN
C
C
= 68 pF
C
C
= 10 pF
C
C
= 4.7 pF
C
C
= OPEN
C
C

=

O
P
E
N
C
C

=

4
.
7
p
F
C
C

=

1
0
p
F
C
C

=

6
8
p
F
0 25 50 75 100 125 150
CASE TEMPERATURE, T
C
(C)
0
8
24
32
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
16
40
R
L
= 1K
V
S
= 200V
A
V
= 63
P
O
= 5W
P
O
= 1W
P
O
= 17.6W
PHASE COMPENSATION
GAIN C
C
* R
C
1 68pF 100
5 10pF 100
10 4.7pF 0
30 NONE 0
*C
C
To be rated for the full supply voltage +V
S
to V
S
.
Use NPO ceramic (COG) type.
GENERAL
mounting, current limit, SOA interpretation, and specifcation interpretation. Visit www.cirrus.com for design tools
CURRENT LIMIT
CL
gram. For optimum reliability the resistor value should be set as high as possible. The value is calculated as fol-
lows; with the maximum practical value of 32 ohms.
.65
R
CL
=
I
LIM
PA90
PA90U 431
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
The MOSFET output stage of this power operational amplifer has two distinct limitations:
1. The current handling capability of the MOSFET geometry and the wire bonds.
NOTE: The output stage is protected against transient fyback. However, for protection against sustained, high en-
ergy fyback, external fast-recovery diodes should be used.
ditional internal power dissipation the amplifer can toler-
ate when it produces the necessary output to drive an
external load.
INPUT PROTECTION
Although the PA90 can withstand differential voltages up
to 20V, additional external protection is recommended.
Low leakage, low capacitance JFETs connected as di-
odes are recommended (e.g. 2N4416, Q1-Q4 in Fig-
ure 2). The differential input voltage will be clamped to
1.4V. This is suffcient overdrive to produce maximum
power bandwidth.
Unidirectional zener diode transient suppressors are
recommended as protection on the supply pins. See
Figure 2. The zeners clamp transients to voltages within
the power supply rating and also clamp power supply
reversals to ground. Whether the zeners are used or not,
the system power supply should be evaluated for transient performance
including power-on overshoot and power-off polarity reversals as well as
line regulation.
Conditions which can cause open circuits or polarity reversals on either
power supply rail should be avoided or protected against. Reversals or
opens on the negative supply rail is known to induce input stage failure.
Unidirectional transzorbs prevent this, and it is desirable that they be
both electrically and physically as close to the amplifer as possible.
STABILITY
The PA90 is externally compensated and performance can be tailored
to the application. Use the graphs of small signal response and power
response as a guide. The compensation capacitor C
C
must be rated at 500V working voltage. An NPO capacitor
is recommended. The compensation network C
C
R
C
QUIESCENT CURRENT REDUCTION
When pin 3 (I
Q
) is shorted to pin 5 (CC2) the AB biasing of the output stage is disabled. This raises distortion since
the output stage is then class C biased, but reduces the quiescent current by 1mA for a power dissipation savings
of 0.4W. Pin 3 may be left open if not used.
SOA
S
- V
O
(V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

-
V
S

(
m
A
)
25 50 75 100 125 250 500
500
300
200
100
50
30
20
10
PULSE CURVES @ 10% DUTY CYCLE MAX.
1
0
0
m
S
2
0
0
m
S
D
C
,

T
C
=

2
5
C
D
C
,

T
C
=

1
2
5
C
D
C
,

T
C
=

8
5
C
+V
S
IN
+IN
Z1
Z2
11, 12
7, 8
1
2
6
PA90
Q1
Q2
V
S
Q3
Q4
FIGURE 2.
OVERVOLTAGE
PROTECTION
PA91
432 PA91U
P r o d u c t I n n o v a t i o n F r o m PA91
FEATURES
APPLICATIONS
TO 440V
Q1 Q2
R1 R2 C1 R3
Q3
CC1
12
11
1
4
5
9
6
10
2
7
8
CC2
3
Q6
Q5
R5
R8 R9
Q15
R11 R12
Q16
Q12
Q8
R4
R7
Q4
ILIM
OUT
Q17
R10
Q13
Q11
+V
S
IN
+IN
V
S
I
Q
R6
Q14B Q14A
DESCRIPTION
solution for driving continuous output currents up to
200mA and pulse currents up to 350mA. The safe oper-
ating area (SOA) has no second breakdown limitations
and can be observed for all type loads by choosing
space allowing for high density circuit boards. The 12-
pin PowerSIP package is electrically isolated.
JUN 2009
APEX PA91UREVH
1 2 3 4 5 6 7 8 9 10
IN +IN
R
CL
+V
s
V
s
TO LOAD
AND FEEDBACK
11 12
R
c
C
c
*
*
(See text.)
I
Q
12-pin SIP
PACKAGE
STYLE DP
PA91
PA91U 433
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
CAUTION
SUPPLY VOLTAGE, +V
S
to -V
S
450 V
OUTPUT CURRENT, source, sink, peak, within SOA 350 mA
C
= 25C 30 W
S
V
S
V
1
Min Typ Max Units
INPUT
15 50 V/C
OFFSET VOLTAGE vs. time 75 V/KHz
11
(Note 3)
V
S
15 V
CM
= 90V 80 98 dB
NOISE 100KHz bandwidth,
R
S
= 1K, C
C
= OPEN
1 V RMS
GAIN
OPEN LOOP @ 15Hz R
L
= 2K, C
C
= OPEN 94 111 dB
L
= 2K, C
C
= OPEN 100 MHz
POWER BANDWIDTH R
L
= 2K, C
C
= OPEN 470 KHz
OUTPUT
O
= 200mA V
S
12 V
S
10 V
SLEW RATE, A
V
= 100 C
C
= OPEN 240 300 V/S
CAPACITIVE LOAD, A
V
= +1 Full temperature range 470 pF
SPECIFICATIONS
PA91
434 PA91U
C
= 25C).
3. +V
S
and V
S
60Hz.
5. Derate max supply rating 0.625 V/C below 25C case. No derating needed above 25C case.
1
Min Typ Max Units
C
= OPEN, 2V step 1 S
POWER SUPPLY
THERMAL
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
10
HARMONIC DISTORTION
100K 100 1K 10K
100k
FREQUENCY F (Hz)
135
90
PHASE RESPONSE
P
H
A
S
E
,

)
10 100 10K 100K
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V

(
n
V
H
z
)
100K
FREQUENCY, F (Hz)
10
0
30
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
10
20
40
50
0 0.15 0.2
OUTPUT CURRENT, I
O
(A)
5
6
4.5
4
5.5
0 8 12 20 24
RESISTOR VALUE, R
CL
()
0
.05
.2
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
.1
.15
0.1
C
(pF)
10
SLEW RATE
S
L
E
W

R
A
T
E
,

(
V
/
S
)
50
40
30
20
1K
10 100
FREQUENCY, F (Hz)
D
I
S
T
O
R
T
I
O
N
,

(
%
)
1
25 50 100
CASE TEMPERATURE, T
C
(C)
1.1
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
1.0
4 16
INPUT NOISE VOLTAGE
1K
2
7
10
20
5
3
15
.05
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

V
O

(
V
)
225
75
.001
1M 10M
270
180
125
1.2
1.3
0.1
3.5
700
300
200
100
70
500
1
.01
.1
1M 10M
C
C
= 68 pF
C
C
= 10 pF
C
C
= 4.7 pF
C
C
= OPEN
C
C
= 68 pF
C
C
= 10 pF
C
C
= 4.7 pF
C
C
= OPEN
0 25 50 75 100 125 150
CASE TEMPERATURE, T
C
(C)
0
8
24
32
POWER DERATING
16
40
R
L
= 1K
V
S
= 200V
A
V
= 63
P
O
= 5W
P
O
= 1W
P
O
= 17.6W
OUTPUT STAGE
POWER RESPONSE
FREQUENCY, F (Hz)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O
(
V
P
-
P
)
10K 100K 1M
50
60
70
80
90
100
200
300
500
400
C
C

=

O
P
E
N
C
C

=

4
.
7
p
F
C
C

=

1
0
p
F
C
C

=

6
8
p
F
PA91
PA91U 435
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
TYPICAL APPLICATION
Piezo positioning may be applied to the focusing of seg-
mented mirror systems. The composite mirror may be
composed of hundreds of elements, each requiring focus-
ing under computer control. In such complex systems the
PA91 reduces the costs of power supplies and cooling
with its advantages of low cost and low quiescent power
consumption while increasing circuit density with the SIP
package.
GENERAL
CURRENT LIMIT
CL
with the maximum practical value of 32 ohms.
.65
R
CL
=
I
LIM
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
10
HARMONIC DISTORTION
100K 100 1K 10K
100k
FREQUENCY F (Hz)
135
90
PHASE RESPONSE
P
H
A
S
E
,

)
10 100 10K 100K
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V

(
n
V
H
z
)
100K
FREQUENCY, F (Hz)
10
0
30
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
10
20
40
50
0 0.15 0.2
OUTPUT CURRENT, I
O
(A)
5
6
4.5
4
5.5
0 8 12 20 24
RESISTOR VALUE, R
CL
()
0
.05
.2
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
.1
.15
0.1
C
(pF)
10
SLEW RATE
S
L
E
W

R
A
T
E
,

(
V
/
S
)
50
40
30
20
1K
10 100
FREQUENCY, F (Hz)
D
I
S
T
O
R
T
I
O
N
,

(
%
)
1
25 50 100
CASE TEMPERATURE, T
C
(C)
1.1
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
1.0
4 16
INPUT NOISE VOLTAGE
1K
2
7
10
20
5
3
15
.05
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

V
O

(
V
)
225
75
.001
1M 10M
270
180
125
1.2
1.3
0.1
3.5
700
300
200
100
70
500
1
.01
.1
1M 10M
C
C
= 68 pF
C
C
= 10 pF
C
C
= 4.7 pF
C
C
= OPEN
C
C
= 68 pF
C
C
= 10 pF
C
C
= 4.7 pF
C
C
= OPEN
0 25 50 75 100 125 150
CASE TEMPERATURE, T
C
(C)
0
8
24
32
POWER DERATING
16
40
R
L
= 1K
V
S
= 200V
A
V
= 63
P
O
= 5W
P
O
= 1W
P
O
= 17.6W
OUTPUT STAGE
POWER RESPONSE
FREQUENCY, F (Hz)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O
(
V
P
-
P
)
10K 100K 1M
50
60
70
80
90
100
200
300
500
400
C
C

=

O
P
E
N
C
C

=

4
.
7
p
F
C
C

=

1
0
p
F
C
C

=

6
8
p
F
F
R
PA91
IN
R
1
2
6
7,8
9,10
11,12
PIEZO DRIVE
S
V
S
+V
OUT
V
COMPUTER
FOCUS
COMMAND
VOLTAGE
CL
R
PHASE COMPENSATION
GAIN C
C
* R
C

1 68pF 100
5 10pF 100
10 4.7pF 0
30 NONE 0
*C
C
To be rated for the full supply voltage +V
S
to V
S
.
Use NPO ceramic (COG) type.
PA91
436 PA91U
The MOSFET output stage of this power operational
amplifer has two distinct limitations:
1. The current handling capability of the MOSFET ge-
ometry and the wire bonds.
NOTE: The output stage is protected against transient
used.
The safe operating area curves defne the maximum
additional internal power dissipation the amplifer can
tolerate when it produces the necessary output to drive
an external load.
INPUT PROTECTION
Although the PA91 can withstand differential voltages
up to 20V, additional external protection is recom-
mended. Low leakage, low capacitance JFETs con-
nected as diodes are recommended (e.g. 2N4416, Q1-Q4 in Figure
2). The differential input voltage will be clamped to 1.4V. This is
suffcient overdrive to produce maximum power bandwidth.
Unidirectional zener diode transient suppressors are recommended
as protection on the supply pins. See Figure 2. The zeners clamp
transients to voltages within the power supply rating and also clamp
power supply reversals to ground. Whether the zeners are used or
not, the system power supply should be evaluated for transient per-
formance including power-on overshoot and power-off polarity rever-
sals as well as line regulation.
Conditions which can cause open circuits or polarity reversals on
either power supply rail should be avoided or protected against. Re-
versals or opens on the negative supply rail is known to induce input stage failure. Unidirectional transzorbs prevent
this, and it is desirable that they be both electrically and physically as close to the amplifer as possible.
STABILITY
The PA91 is externally compensated and performance can be tailored to the application. Use the graphs of small
signal response and power response as a guide. The compensation capacitor CC must be rated at 500V working
voltage. An NPO capacitor is recommended. The compensation network CCRC must be mounted closely to the
amplifer pins 4 and 5 to avoid spurious oscillation.
When pin 3 (IQ) is shorted to pin 5 (CC2) the AB biasing of the output stage is disabled. This raises distortion since
the output stage is then class C biased, but reduces the quiescent current by 1mA for a power dissipation savings
of 0.4W. Pin 3 may be left open if not used.
SOA
S
- V
O
(V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

-
V
S

(
m
A
)
25 50 75 100 125 250 500
500
300
200
100
50
30
20
10
1
0
0
m
S
2
0
0
m
S
D
C
,

T
C
=

2
5
C
D
C
,

T
C
=

1
2
5
C
D
C
,

T
C
=

8
5
C
+V
S
IN
+IN
Z1
Z2
11, 12
7, 8
1
2
6
PA91
Q1
Q2
V
S
Q3
Q4
FIGURE 2.
OVERVOLTAGE
PROTECTION
PA92
PA92U 437
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA92
FEATURES
APPLICATIONS
TO 390V
Q1 Q2
R1 R2 C1 R3
Q3
CC1
12
11
1
4
5
9
6
10
2
7
8
CC2
3
Q6
Q5
R5
R8 R9
Q15
R11 R12
Q16
Q12
Q8
R4
R7
Q4
ILIM
OUT
Q17
R10
Q13
Q11
+V
S
IN
+IN
V
S
I
Q
R6
Q14B Q14A
DESCRIPTION
solution for driving continuous output currents up to 4A
and pulse currents up to 7A. The safe operating area
(SOA) has no second breakdown limitations and can
be observed for all type loads by choosing an appropri-
ate current limiting resistor. The MOSFET output stage
is biased AB for linear operation. External compensa-
tion provides fexibility in choosing bandwidth and slew
rate for the application. Apex Precision Powers Power
SIP package uses a minimum of board space allowing
for high density circuit boards. The Power SIP package
is electrically isolated.
JUN 2009
APEX PA92UREVK
1 2 3 4 5 6 7 8 9 10
IN +IN
R
CL
+V
s
V
s
TO LOAD
AND FEEDBACK
11 12
R
c
C
c
*
*
(See text.)
I
Q
PATENTED
12-pin SIP
PACKAGE
STYLE DP
PA92
438 PA92U
CAUTION
INPUT
15 50 V/C
OFFSET VOLTAGE vs. time 75 V/kh
11
(Note 3)
V
S
15 V
CM
= 90V 80 98 dB
NOISE 100KHz bandwidth,
R
S
= 1K, C
C
= 10pF
1 V RMS
GAIN
OPEN LOOP @ 15Hz R
L
= 2K, C
C
= 10pF 94 111 dB
L
= 2K, C
C
= 10pF 18 MHz
POWER BANDWIDTH R
L
= 2K, C
C
= 10pF 30 kHz
OUTPUT
O
= 4A V
S
12 V
S
10 V
SLEW RATE, A
V
= 100 C
C
= 10pF 50 V/S
CAPACITIVE LOAD, A
V
= +1 Full temperature range 1 nF
SUPPLY VOLTAGE, +V
S
to -V
S
400 V
OUTPUT CURRENT, source, sink, peak, within SOA 7 A
C
= 25C 80 W
S
V
S
V
SPECIFICATIONS
PA92
PA92U 439
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
C
= 25C).
3. +V
S
and V
S
60Hz.
C
= 10pF, 2V step 1 S
POWER SUPPLY
THERMAL
(Note 4)
Full temp range, F > 60Hz 1 C/W
HARMONIC DISTORTION
100 1K 10K
100k
FREQUENCY F (Hz)
135
90
PHASE RESPONSE
P
H
A
S
E
,

)
10 100 10K 100K
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V

(
n
V
H
z
)
100K
FREQUENCY, F (Hz)
10
0
30
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
10
20
40
50
0 3 4
OUTPUT CURRENT, I
O
(A)
8.0
7.5
7.0
8.5
0.0 0.4 0.6 1.0 1.2
RESISTOR VALUE, R
CL
()
0
1
4
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
2
3
10
C
(pF)
1
SLEW RATE
S
L
E
W

R
A
T
E
,

(
V
/
S
)
6
4
3
2
100 300
FREQUENCY, F (Hz)
D
I
S
T
O
R
T
I
O
N
,

(
%
)
25 50 100
CASE TEMPERATURE, T
C
(C)
1.2
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
1.0
0.2 0.8
INPUT NOISE VOLTAGE
1K
2
7
10
20
5
3
15
1
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

V
O

(
V
)
225
75
.001
1M 10M
270
180
125
1.4
1.6
2
6.5
60
30
20
10
8
40
30
.01
.1
1M 10M
C
C
= 150pF
C
C
= 100pF
C
C
= 47pF
C
C
= 10pF
C
C
= 150pF
C
C
= 100pF
C
C
= 47pF
C
C
= 10pF
0 25 50 75 100 125
CASE TEMPERATURE, T
C
(C)
0
20
60
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
40
80
P
O
= 62W
P
O
= 20W
P
O
= 1W
POWER RESPONSE
FREQUENCY, F (Hz)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O
(
V
P
-
P
)
10K 100K 1M
10
100
400
C
C
= 10pF
C
C
= 47pF
C
C
= 100pF
C
C
= 150pF
1K
200 60
PA92
440 PA92U
GENERAL
CURRENT LIMIT
CL
) must
be connected as shown in the external connection dia-
gram. For optimum reliability the resistor value should be
set as high as possible. The value is calculated as fol-
lows; with the maximum practical value of 16 ohms.
.65
R
CL
=
I
LIM
The MOSFET output stage of this power operational am-
plifer has two distinct limitations:
1. The current handling capability of the MOSFET geom-
etry and the wire bonds.
used.
S
V
O
(V)
10 20 30 40 80 100 200 300 500
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S
,

(
A
)
.04
.2
.1
.08
.06
.3
.8
.6
.4
1
2
4
8
6

T
C
=

1
2
5
C
T
C
=

8
5
C
1
0
0
m
S
60
200mS
DC, T
C
= 25C
SOA
HARMONIC DISTORTION
100 1K 10K
100k
FREQUENCY F (Hz)
135
90
PHASE RESPONSE
P
H
A
S
E
,

)
10 100 10K 100K
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V

(
n
V
H
z
)
100K
FREQUENCY, F (Hz)
10
0
30
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
10
20
40
50
0 3 4
OUTPUT CURRENT, I
O
(A)
8.0
7.5
7.0
8.5
0.0 0.4 0.6 1.0 1.2
RESISTOR VALUE, R
CL
()
0
1
4
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
2
3
10
C
(pF)
1
SLEW RATE
S
L
E
W

R
A
T
E
,

(
V
/
S
)
6
4
3
2
100 300
FREQUENCY, F (Hz)
D
I
S
T
O
R
T
I
O
N
,

(
%
)
25 50 100
CASE TEMPERATURE, T
C
(C)
1.2
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
1.0
0.2 0.8
INPUT NOISE VOLTAGE
1K
2
7
10
20
5
3
15
1
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

V
O

(
V
)
225
75
.001
1M 10M
270
180
125
1.4
1.6
2
6.5
60
30
20
10
8
40
30
.01
.1
1M 10M
C
C
= 150pF
C
C
= 100pF
C
C
= 47pF
C
C
= 10pF
C
C
= 150pF
C
C
= 100pF
C
C
= 47pF
C
C
= 10pF
0 25 50 75 100 125
CASE TEMPERATURE, T
C
(C)
0
20
60
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
40
80
P
O
= 62W
P
O
= 20W
P
O
= 1W
POWER RESPONSE
FREQUENCY, F (Hz)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O
(
V
P
-
P
)
10K 100K 1M
10
100
400
C
C
= 10pF
C
C
= 47pF
C
C
= 100pF
C
C
= 150pF
1K
200 60
PHASE COMPENSATION
GAIN C
C
* R
C
1 150pF 100
2 100pF 100
3 47pF 0
12 10pF 0
*C
C
Never to be <10pF. C
C
to be rated for the full supply
voltage +V to -Vs. Use ceramic NPO (COG) type.
PA92
PA92U 441
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
The safe operating area curves defne the maximum additional internal power dissipation the amplifer can tolerate
when it produces the necessary output to drive an external load.
INPUT PROTECTION
Although the PA92 can withstand differential voltages up to 20V, ad-
ditional external protection is recommended. Low leakage, low capaci-
tance JFETs connected as diodes are recommended (e.g. 2N4416, Q1-
Q4 in Figure 2). The differential input voltage will be clamped to 1.4V.
This is suffcient overdrive to produce maximum power bandwidth.
Unidirectional zener diode transient suppressors are recommended as
protection on the supply pins. See Figure 2. The zeners clamp transients
to voltages within the power supply rating and also clamp power supply
reversals to ground. Whether the zeners are used or not, the system
power supply should be evaluated for transient performance including
power-on overshoot and power-off polarity reversals as well as line regulation.
Conditions which can cause open circuits or polarity reversals on either power supply rail should be avoided or pro-
tected against. Reversals or opens on the negative supply rail is known to induce input stage failure. Unidirectional
transzorbs prevent this, and it is desirable that they be both electrically and physically as close to the amplifer as
possible.
STABILITY
signal response and power response as a guide. The compensation capacitor C
C
must be rated at 500V working
voltage. An NPO capacitor is recommended. The compensation network C
C
R
C
must be mounted closely to the am-
plifer pins 4 and 5 to avoid spurious oscillation.
When pin 3 (I
Q
) is shorted to pin 5 (CC2) the AB biasing of the output stage is disabled. This lowers quiescent power
but also raises distortion since the output stage is then class C biased. The output stage bias current is nominally
set at 1mA. Pin 3 may be left open if not used.
+V
S
IN
+IN
Z1
Z2
11, 12
7, 8
1
2
6
PA90
Q1
Q2
V
S
Q3
Q4
FIGURE 2.
OVERVOLTAGE
PROTECTION
PA93
442 PA93U
PA93
FEATURES
APPLICATIONS
TO 390V
Q1 Q2
R1A
R1B C1 R3
Q3
CC1
CC2
Q6
Q5
R5
R8 R9
Q15
R11 R12
Q16
Q12
Q8
R4
R7
Q4
ILIM
OUT
Q18
R15
Q13
Q11
+V
S
IN
+IN
V
S
R6
Q14A Q14B
DESCRIPTION
solution for driving continuous output currents up to 8A
and pulse currents up to 14A. The safe operating area
(SOA) has no second breakdown limitations and can
be observed for all type loads by choosing an appropri-
ate current limiting resistor. The MOSFET output stage
is biased AB for linear operation. External compensa-
tion provides fexibility in choosing bandwidth and slew
rate for the application. Apex Precision Powers Power
SIP package uses a minimum of board space allowing
for high density circuit boards. The Power SIP package
is electrically isolated.
AUG 2008
APEX PA93UREVH
1 2 3 4 5 6 7 8 9 10
IN +IN
R
CL
+V
s
V
s
TO LOAD
AND FEEDBACK
(See text.)
11 12
R
c
C
c
*
*
I
Q
PATENTED
12-pin SIP
PACKAGE
STYLE DP
PA93
PA93U 443
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SPECIFICATIONS
CAUTION
SUPPLY VOLTAGE, +V
S
to -V
S
400 V
OUTPUT CURRENT, source, sink, peak, within SOA 14 A
C
= 25C 125 W
S
V
S
V
1
Min Typ Max Units
INPUT
15 50 V/C
11
(Note 3)
Vs 15 V
CM
= 90V 80 98 dB
NOISE 100KHz BW, R
S
= 1K,
C
C
= 10pF
1 V RMS
GAIN
OPEN LOOP @ 15Hz R
L
= 2K, C
C
= 10pF 94 111 dB
L
= 2K, C
C
= 10pF 12 MHz
POWER BANDWIDTH R
L
= 2K, C
C
= 10pF 30 KHz
PHASE MARGIN Full temp range 60
OUTPUT
O
= 8mA V
S
12 V
S
10 V
SLEW RATE, A
V
= 100 C
C
= 10pF 50 V/S
CAPACITIVE LOAD, A
V
= +1 Full temp range 1 nF
PA93
444 PA93U
C
= 25C, DC input specifcations are value given. Power supply voltage
is typical rating. R
C
= 100 C
C
= 220pF.
internal power dissipation to achieve high MTTF.
3. +V
S
and V
S
60Hz.
1
Min Typ Max Units
C
= 10pF, 2V step 1 S
POWER SUPPLY
THERMAL
(Note 4)
Full temp range, F > 60Hz 0.7 C/W
RESISTANCE, DC, junction to case Full temp range, F < 60Hz 1 C/W
TYPICAL APPLICATION
Piezo positioning may be applied to the focusing of segmented
mirror systems. The composite mirror may be composed of
hundreds of elements, each requiring focusing under computer
control. In such complex systems the PA93 reduces the costs
of power supplies and cooling with its advantages of low cost
and low quiescent power consumption while increasing circuit
density with the SIP package.
F
R
PA93
IN
R
1
2
6
7,8
9,10
11,12
PIEZO DRIVE
S
V
S
+V
OUT
V
COMPUTER
FOCUS
COMMAND
VOLTAGE
CL
R
0 25 50 75 100 125
CASE TEMPERATURE, T
C
(C)
0
75
100
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
100k
FREQUENCY F (Hz)
135
90
PHASE RESPONSE
P
H
A
S
E
,

)
100K
FREQUENCY, F (Hz)
10
0
30
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
10
20
40
50
0 6 8
OUTPUT CURRENT, I
O
(A)
7
9
6
8
1M
FREQUENCY, F (Hz)
10
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
100
400
0 .2 .3 .5 .6
RESISTOR VALUE, R
CL
()
0
2
8
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
4
6
10 60
C
(pF)
1
SLEW RATE
S
L
E
W

R
A
T
E
,

(
V
/
S
)
4
3
2
60
100 200 300 20 40
25 50 100
CASE TEMPERATURE, T
C
(C)
1.2
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
1.0
.1 .4
2
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

V
O

(
V
)
225
50
25
125
POWER RESPONSE
75
1M 10M
270
180
125
1.4
1.8
1.6
4
5
100K
40
20
10
8
6
30
30
1K 10K
1M 10M
C
C
= 220pF
C
C
= 100pF
C
C
= 47pF
C
C
= 10pF
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
H
z
)
FREQUENCY, F (Hz)
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

(
%
)
.01
.1
10K 100 1K
INPUT NOISE VOLTAGE
2
7
10
20
5
3
15
.001
P
O
= 1W
P
O
= 20W
P
O
= 62W
C
C
= 220pF
C
C
= 100pF
C
C
= 47pF
C
C
= 10pF
C
C
= 220pF
C
C
= 100pF
C
C
= 47pF
C
C
= 10pF
10 100K 10K 1K 100
PA93
PA93U 445
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
0 25 50 75 100 125
CASE TEMPERATURE, T
C
(C)
0
75
100
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
100k
FREQUENCY F (Hz)
135
90
PHASE RESPONSE
P
H
A
S
E
,

)
100K
FREQUENCY, F (Hz)
10
0
30
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
10
20
40
50
0 6 8
OUTPUT CURRENT, I
O
(A)
7
9
6
8
1M
FREQUENCY, F (Hz)
10
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
100
400
0 .2 .3 .5 .6
RESISTOR VALUE, R
CL
()
0
2
8
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
4
6
10 60
C
(pF)
1
SLEW RATE
S
L
E
W

R
A
T
E
,

(
V
/
S
)
4
3
2
60
100 200 300 20 40
25 50 100
CASE TEMPERATURE, T
C
(C)
1.2
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
1.0
.1 .4
2
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

V
O

(
V
)
225
50
25
125
POWER RESPONSE
75
1M 10M
270
180
125
1.4
1.8
1.6
4
5
100K
40
20
10
8
6
30
30
1K 10K
1M 10M
C
C
= 220pF
C
C
= 100pF
C
C
= 47pF
C
C
= 10pF
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
H
z
)
FREQUENCY, F (Hz)
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

(
%
)
.01
.1
10K 100 1K
INPUT NOISE VOLTAGE
2
7
10
20
5
3
15
.001
P
O
= 1W
P
O
= 20W
P
O
= 62W
C
C
= 220pF
C
C
= 100pF
C
C
= 47pF
C
C
= 10pF
C
C
= 220pF
C
C
= 100pF
C
C
= 47pF
C
C
= 10pF
10 100K 10K 1K 100
PHASE COMPENSATION
GAIN C
C
* R
C
1 220pF 100
2 100pF 100
4 47pF 0
17 10pF 0
*C
C
Never to be <10pF. C
C
to be rated for the full supply
voltage +V
S
to -V
S
. Use ceramic NPO (COG) type.
GENERAL
mounting, current limit, SOA interpretation, and specifcation interpretation. Visit www.Cirrus.com for design tools
CURRENT LIMIT
CL
with the maximum practical value of 16 ohms.
.65
R
CL
=
I
LIM
PA93
446 PA93U
The MOSFET output stage of this power operational am-
plifer has two distinct limitations:
1. The current handling capability of the MOSFET geom-
etry and the wire bonds.
used.
ditional internal power dissipation the amplifer can toler-
ate when it produces the necessary output to drive an
external load.
INPUT PROTECTION
Although the PA93 can withstand differential voltages up
to 20V, additional external protection is recommended.
Low leakage, low capacitance JFETs connected as di-
odes are recommended (e.g. 2N4416, Q1-Q4 in Figure 2). The differen-
tial input voltage will be clamped to 1.4V. This is suffcient overdrive to
produce maximum power bandwidth.
protection on the supply pins. See Figure 2. The zeners clamp transients
to voltages within the power supply rating and also clamp power supply
reversals to ground. Whether the zeners are used or not, the system
power supply should be evaluated for transient performance including
power-on overshoot and power-off polarity reversals as well as line regu-
lation.
power supply rail should be avoided or protected against. Reversals or opens on the negative supply rail is known
to induce input stage failure. Unidirectional transzorbs prevent this, and it is desirable that they be both electrically
STABILITY
C
C
R
C
When pin 3 (I
Q
) is shorted to pin 5 (CC2) the AB biasing of the output stage is disabled. This lowers quiescent power
but also raises distortion since the output stage is then class C biased. The output stage bias current is nominally
set at 1mA. Pin 3 may be left open if not used.
S
V
O
(V)
10 20 30 40 100 200 300 500
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S
,

(
A
)
.1
.08
.06
.6
.4
.3
.2
.8
3
2
1
4
6
8
20
10

D
C
,
T
C
=

1
2
5
C
1
0
0
m
S
60 80
200mS
DC, T
C
= 25C

D
C
,
T
C
=

8
5
C
SOA
+V
S
IN
+IN
Z1
Z2
11, 12
7, 8
1
2
6
PA93
Q1
Q2
V
S
Q3
Q4
FIGURE 2.
OVERVOLTAGE
PROTECTION
PA94
PA94U 447
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
P r o d u c t I n n o v a t i o n F r o m PA94
FEATURES
APPLICATIONS
TO 430V
MASS SPECTROMETERS
SEMICONDUCTOR MEASUREMENT EQUIP-
MENT
Q1 Q2
R1A
R1B C2 R3
Q3
CC1
CC2
Q6
Q5
R9
R11 R12
Q29
R20 R27
Q30
Q29
Q8
R4
R7
Q4
ILIM
OUT
Q14
R19
Q21
Q14
+V
S
IN
+IN
V
S
R10
Q15A Q15B
4
6
7
8
10
2
1
12
DESCRIPTION
The PA94 is a high voltage, MOSFET operational am-
plifer designed as a low cost solution for driving contin-
uous output currents up to 100mA and pulse currents
up to 200mA into capacitive loads. The safe operat-
ing area (SOA) has no second breakdown limitations
and can be observed for all load types by choosing
space allowing for high density circuit boards.. The
Power SIP package is electrically isolated. Isolating
thermal washers (TW13) prevent arcing from pins to
heatsink.
JUN 2009
APEX PA94UREVM
PA94
448 PA94U
CAUTION
in excess of 850C to avoid toxic fumes.
SUPPLY VOLTAGE, +V
S
to V
S
900 V
OUTPUT CURRENT, source, sink, within SOA 200 mA
C
= 25C 30 W
INPUT VOLTAGE, common mode (Note 3) -V
S
V
S
V
1
Min Typ Max Units
INPUT
15 50 V/C
11
(Note 3)
V
S
= 450V V
S
30 V
CM
= 90V 80 98 dB
S
= 1K 2 V RMS
GAIN
OPEN LOOP @ 15Hz R
L
= 5K 94 115 dB
L
= 5K 140 MHz
POWER BANDWIDTH R
L
= 5K 300 kHz
PHASE MARGIN, A
V
= 100 Full temp range 60
OUTPUT
VOLTAGE SWING I
O
= 70mA V
S
24 V
S
20 V
SLEW RATE, A
V
= 100 C
C
=2.2pF 500 700 V/S
RESISTANCE no load 100
SPECIFICATIONS
PA94
PA94U 449
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
C
is typical rating. C
c
= 4.7pF.
3. Although supply voltages can range up to 450V the input pins cannot swing over this range. The
input pins must be at least 30V from either supply rail but not more than 450V from either supply rail.
See text for a more complete description of the common mode voltage range.
60Hz.
1 2 4 6 7 8 10 12
* *
* 0.01F or greater ceramic power supply bypassing required.
IN +IN C
C
1 C
C
2 OUT I
LIM
Vs +Vs
C
C
R
LIM
PATENTED
8-pin SIP
PACKAGE
STYLE DQ
See package style EC
1
Min Typ Max Units
POWER SUPPLY
CURRENT, quiescent output stage only 120 A
THERMAL
(Note 4)
Full temp range, F > 60Hz 2.5 C/W
PHASE COMPENSATION
GAIN C
C
100 2.2pF
50 4.7pF
10 22pF
C
C
rated for full supply voltage.
.7
R
LIM
=
I
LIM
PA94
450 PA94U
0 25 50 75 100 125 150
TEMPERATURE, T (C)
0
5
15
20
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
10 100 10K 1M
FREQUENCY, F (Hz)
0 100
OUTPUT CURRENT, I
O
(mA)
4
8
24
40
16
32
3 10 20 100
CL
()
10
30
200
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
m
A
)
50
70
5 50
20
INPUT NOISE
1K
2
7
10
20
3
5
15
20
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

V
O

(
V
)
10
30
60
25
40
120
100
150
TC
=
2
5
C
T
C
=

5
5
C
T
C

=

1
2
5
C
T
C

=

8
5
C
80
T = T
C
T = T
A
SAFE OPERATING AREA
S
V
O
(V)
50
50
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S
,

(
m
A
)
5
10
15
25
D
C
,

T
C
=

1
2
5
C
D
C
,

T
C
=

8
5
C
2
0
0
m
S
PULSE CURVES @
10% DUTY CYCLE MAX
D
C
,

T
C
=

2
5
C
1
0
0
m
S
100
100
150
200
250
500 1K
0 200 600 800 1000
S
(V)
1.08
1.04
1.00
.96
.92
.88
QUIESCENT CURRENT
Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I

(
X
)
400
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/
H
z
)
1M 20M 10M
FREQUENCY, F (Hz)
-90
-120
-150
-180
-210
-240
PHASE RESPONSE
P
H
A
S
E
,

)
POWER RESPONSE
100K 1M 2M
FREQUENCY, F (Hz)
10K
50
1K
500
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
100
200
FREQUENCY, F (Hz)
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
0
60
120
20
40
80
100
10 100 1K 10K 1M 100K 20M 10M
C
C
= 22 pF
C
C
= 2.2pF
C
C
= 4.7pF
C
C
= 22 pF
C
C
= 4.7pF
C
C
= 2.2pF
C
C

=

2
2

p
F
C
C

=

4
.
7
p
F
C
C

=

2
.
2
p
F
TYPICAL APPLICATION
package.
F
R
PA94
IN
R
PIEZO DRIVE
S
V
S
+V
OUT
V
COMPUTER
FOCUS
COMMAND
VOLTAGE
CL
R
1
2
10
8
7
12
PA94
PA94U 451
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
CURRENT LIMIT
LIM
) must be connected as shown in the external con-
nection diagram. The minimum value is 3.5 ohm, however for optimum reliability the resistor value
should be set as high as possible. The value is calculated as follows; with the maximum practical value
of 30 ohms.
.7
R
LIM
=
I
LIM
COMMON MODE INPUT RANGE
Operational amplifers are usually designed to have a common mode input voltage range that approximates the
power supply voltage range. However, to keep the cost as low as possible and still meet the requirements of most
applications the common mode input voltage range of the PA94 is restricted. The input pins must always be a least
30V from either supply voltage but never more than 450V. This means that the PA94 cannot be used in applications
where the supply voltages are extremely unbalanced. For example, supply voltages of +800V and 100V would not
be allowed in an application where the non-inverting pin is grounded because in normal operation both input pins
would be at 0V and the difference voltage between the positive supply and the input pins would be 800V. In this
kind of application, however, supply voltages +450V and -100V does meet the input common mode voltage range
requirements since the maximum difference voltage between the inputs pins and the supply voltage is 450V (the
maximum allowed). The output has no such restrictions on its voltage swing. The output can swing within 24V of
either supply voltage regardless of value so long as the total supply voltage does not exceed 900V.
INTERNAL POWER DISSIPATION AND HEATSINK SELECTION
With the unique combination of high voltage and speed of the PA94, traditional formulas for heatsink selection will
falsely lower the apparent power handling capability of this amplifer. To more accurately predict operating tempera-
tures use Power Design
1
revision 10 or higher, or use the following procedure:
Find internal dissipation (PD) resulting from driving the load. Use Power Design or refer to Apex Precision Power
Applications Note 1, General Operating Considertaions, paragraph 7. Find total quiescent power (PD
Q
) by multiply-
ing 0.024A by V
SS
(total supply voltage). Find output stage quiescent power (PD
QOUT
) by multiplying 0.00012 by V
SS
.
Calculate a heatsink rating which will maintain the case at 85C or lower.

T
C
- T
A
PD + PD
Q
R
SA
= -0.1C/W
Where: T
C
= maximum case temperature allowed
T
A
= maximum ambient temperature encountered
Calculate a heatsink rating which will maintain output transistor junctions at 150C or lower.

T
J
- T
A
- (PD + PD
QOUT
)
*
R
JC
PD + PD
Q
R
SA
=

-0.1C/W

Where: T
J
= maximum junction temperature allowed.
R
JC
= AC or DC thermal resistance from the specifcation table.
Use the larger heatsink of these two calculations.
Power Design is an Excel spreadsheet available free from www.cirrus.com
PA94
452 PA94U
INPUT PROTECTION
Although the PA94 can withstand differential input voltages up to
20V, additional external protection is recommended. In most ap-
plications 1N4148 or 1N914 signal diodes are suffcient (D1, D2 in
Figure 1a). In more demanding applications where low leakage or
low capacitance are of concern 2N4416 or 2N5457-2N5459 JFETs
connected as diodes will be required (Q1, Q2 in Figure 1b). In ei-
ther case the input differential voltage will be clamped to .7V. This
is suffcient overdrive to produce maximum power bandwidth. Note
that this protection does not automatically protect the amplifer from
excessive common mode input voltages.
Unidirectional zener diode transient suppressors are recommended
as protection on the supply pins. The zeners clamp transients to
voltages within the power supply rating and also clamp power sup-
ply reversals to ground. Whether the zeners are used or not, the
system power supply should be evaluated for transient performance
including power-on overshoot and power-off polarity reversal as well
as line regulation.
possible.
STABILITY
The PA94 is stable at gains of 100 or more with a NPO (COG) compensation capacitor of 2.2pF. The compensation
capacitor, Cc, in the external connections diagram must be rated at 1000V working voltage and mounted closely to
pins 4 and 6 to prevent spurious oscillation. A compensation capacitor less than 2.2pF is not recommended.
EXTERNAL COMPONENTS
The compensation capacitor Cc must be rated for the total supply voltage. An NPO (COG) capacitor rated a 1kV is
recommended.
Of equal importance are the voltage rating and voltage coeffcient of the gain setting feedback resistor. Typical volt-
age ratings of low wattage resistors are 150 to 250V. Up to 500 V can appear across the feedback resistor. High
voltage rated resistors can be obtained. However a 1 megohm feedback resistor composed of fve 200k resistors in
series will produce the proper voltage rating.
CAUTIONS
The operating voltages of the PA94 are potentially lethal. During circuit design develop a functioning circuit at the
lowest possible voltages. Clip test leads should be used for "hands off" measurements while troubleshooting.
PA94
+V
S
IN
+IN
Z1
Z2
D2 D1
12
10
1
2
+V
S
IN
+IN
Z1
Z2
12
10
1
2
PA94
Q1 Q2
A.
B.
V
S
V
S
PA95
PA95U 453
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA95
FEATURES
LOW QUIESCENT CURRENT 1.6mA
APPLICATIONS
TO 430V
MASS SPECTROMETERS
SEMICONDUCTOR MEASUREMENT
EQUIPMENT
Q1 Q2
R1A R1B C2
12
R3
Q3
CC1
CC2
Q6
Q5
R9
R11
2
1
R12
Q29
R20
10
R27
Q30
Q29
Q8
R4
R7
7
8
6
4
Q4
ILIM
OUT
Q14
R19
Q21
Q14
+V
S
IN
+IN
V
S
R10
Q5A Q5B
DESCRIPTION
The PA95 is a high voltage, MOSFET operational am-
plifer designed as a low cost solution for driving contin-
uous output currents up to 100mA and pulse currents
up to 200mA into capacitive loads. The safe operat-
ing area (SOA) has no second breakdown limitations
and can be observed for all load types by choosing
space allowing for high density circuit boards. The
Power SIP package is electrically isolated. Isolating
thermal washers (TW13) are recommended to prevent
arcing from pins to heatsink.
JUN 2009
APEX PA95UREVK
1 2 4 6 7 8 10 12
* *
* 0.01F or greater ceramic power supply bypassing required.
IN +IN C
C
1 C
C
2 OUT I
LIM
Vs +Vs
C
C
R
LIM
PATENTED
8-pin SIP
PACKAGE
STYLE DQ
See package style EC
PA95
454 PA95U
CAUTION
SUPPLY VOLTAGE, +V
S
to -V
S
900 V
C
= 25C 30 W
INPUT VOLTAGE, common mode (Note 3) -V
S
V
S
V
1
Min Typ Max Units
INPUT
15 50 V/C
11
(Note 3)
V
S
=250V V
S
30 V
CM
= 90V 80 98 dB
S
= 1K 2 V RMS
GAIN
OPEN LOOP @ 15Hz R
L
= 5K 94 118 dB
L
= 5K 10 MHz
POWER BANDWIDTH R
L
= 5K 20 kHz
PHASE MARGIN, A
V
= 10 Full temp range 60
OUTPUT
VOLTAGE SWING I
O
= 70mA V
S
24 V
S
20 V
SLEW RATE, A
V
= 100 C
C
=4.7pF 30 V/S
RESISTANCE no load 100
SPECIFICATIONS
PA95
PA95U 455
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
C
c
= 4.7pF.
60Hz.
1
Min Typ Max Units
POWER SUPPLY
CURRENT, quiescent 1.6 2.2 mA
THERMAL
TEMPERATURE RANGE, case -25 +85 C
0 25 50 75 100 125 150
TEMPERATURE, T (C)
0
5
15
20
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
10 100 10K 1M
FREQUENCY, F (Hz)
OUTPUT CURRENT, I
O
(mA)
3 10 20 100
CL
()
10
30
200
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
m
A
)
50
70
5 50
20
INPUT NOISE
1K
2
7
10
20
3
5
15
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

V
O

(
V
)
10
30
25
120
100
150
T = T
C
T = T
A
SAFE OPERATING AREA
S
V
O
(V)
50
50
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S
,

(
m
A
)
5
10
15
25
D
C
,

T
C
=

1
2
5
C
D
C
,

T
C
=

8
5
C
2
0
0
m
S
PULSE CURVES @
10% DUTY CYCLE MAX
D
C
,

T
C
=

2
5
C
1
0
0
m
S
100
100
150
200
250
500 1K
1M 2M 3M 4M 5M
FREQUENCY, F (Hz)
-90
-135
-180
-225
-270
-315
-360
PHASE RESPONSE
P
H
A
S
E
,

)
C
C
= 4.7pF
100K 300K
FREQUENCY, F (Hz)
50
1K
500
POWER RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
100
10K
C
C
= 4.7pF
200
0 200 600 800 1000
S
(V)
1.08
1.04
1.00
.96
.92
.88
QUIESCENT CURRENT
Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I

(
X
)
400
FREQUENCY, F (Hz)
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
0
60
120
20
40
80
100
100 1K 10K 100K 1M 10M 10
C
C
= 4.7pF
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/
H
z
)
0 100
4
8
24
40
16
32
20 60 40
TC
=
2
5
C
T
C
=

5
5
C
T
C

=

1
2
5
C
T
C

=

8
5
C
80
PA95
456 PA95U
TYPICAL APPLICATION
package.
PHASE COMPENSATION
C
C
rated for full supply voltage.
GAIN C
C
100 4.7pF
GENERAL
CURRENT LIMIT
LIM
gram. The minimum value is 3.5 ohm, however for optimum reliability the resistor value should be set as high as
possible. The value is calculated as follows; with the maximum practical value of 150 ohms.
.7
R
LIM
=
I
LIM
applications the common mode input voltage range of the PA95 is restricted. The input pins must always be a least
30V from either supply voltage but never more than 500V. This means that the PA95 cannot be used in applications
where the supply voltages are extremely unbalanced. For example, supply voltages of +800V and 100V would not
be allowed in an application where the non-inverting pin is grounded because in normal operation both input pins
would be at 0V and the difference voltage between the positive supply and the input pins would be 800V. In this
kind of application, however, supply voltages +500V and -100V does meet the input common mode voltage range
0 25 50 75 100 125 150
TEMPERATURE, T (C)
0
5
15
20
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
10 100 10K 1M
FREQUENCY, F (Hz)
OUTPUT CURRENT, I
O
(mA)
3 10 20 100
CL
()
10
30
200
CURRENT LIMIT
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
m
A
)
50
70
5 50
20
INPUT NOISE
1K
2
7
10
20
3
5
15
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

V
O

(
V
)
10
30
25
120
100
150
T = T
C
T = T
A
SAFE OPERATING AREA
S
V
O
(V)
50
50
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S
,

(
m
A
)
5
10
15
25
D
C
,

T
C
=

1
2
5
C
D
C
,

T
C
=

8
5
C
2
0
0
m
S
PULSE CURVES @
10% DUTY CYCLE MAX
D
C
,

T
C
=

2
5
C
1
0
0
m
S
100
100
150
200
250
500 1K
1M 2M 3M 4M 5M
FREQUENCY, F (Hz)
-90
-135
-180
-225
-270
-315
-360
PHASE RESPONSE
P
H
A
S
E
,

)
C
C
= 4.7pF
100K 300K
FREQUENCY, F (Hz)
50
1K
500
POWER RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
100
10K
C
C
= 4.7pF
200
0 200 600 800 1000
S
(V)
1.08
1.04
1.00
.96
.92
.88
QUIESCENT CURRENT
Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I

(
X
)
400
FREQUENCY, F (Hz)
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
0
60
120
20
40
80
100
100 1K 10K 100K 1M 10M 10
C
C
= 4.7pF
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/
H
z
)
0 100
4
8
24
40
16
32
20 60 40
TC
=
2
5
C
T
C
=

5
5
C
T
C

=

1
2
5
C
T
C

=

8
5
C
80
F
R
PA95
IN
R
PIEZO DRIVE
S
V
S
+V
OUT
V
COMPUTER
FOCUS
COMMAND
VOLTAGE
CL
R
1
2
10
8
7
12
PA95
PA95U 457
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
requirements since the maximum difference voltage between the inputs pins and the supply voltage is 500V (the
maximum allowed). The output has no such restrictions on its voltage swing. The output can swing within 24V of
either supply voltage regardless of value so long as the total supply voltage does not exceed 900V.
INPUT PROTECTION
Although the PA95 can withstand differential input voltages up to
20V, additional external protection is recommended. In most ap-
plications 1N4148 or 1N914 signal diodes are suffcient (D1, D2 in
Figure 1a). In more demanding applications where low leakage or
low capacitance are of concern 2N4416 or 2N5457-2N5459 JFETs
connected as diodes will be required (Q1, Q2 in Figure 1b). In
either case the input differential voltage will be clamped to .7V.
This is suffcient overdrive to produce maximum power bandwidth.
Note that this protection does not automatically protect the ampli-
fer from excessive common mode input voltages.
Unidirectional zener diode transient suppressors are recommend-
ed as protection on the supply pins. The zeners clamp transients
to voltages within the power supply rating and also clamp power
supply reversals to ground. Whether the zeners are used or not,
the system power supply should be evaluated for transient perfor-
mance including power-on overshoot and power-off polarity rever-
sal as well as line regulation.
possible.
STABILITY
The PA95 is stable at gains of 10 or more with a NPO (COG) compensation capacitor of 4.7pF. The compensation
pins 4 and 6 to prevent spurious oscillation. A compensation capacitor less than 4.7pF is not recommended.
EXTERNAL COMPONENTS
The compensation capacitor Cc must be rated for the total supply voltage. An NPO (COG)capacitor rated a 1kV is
recommended.
Of equal importance are the voltage rating and voltage coeffcient of the gain setting feedback resistor. Typical volt-
age ratings of low wattage resistors are 150 to 250V. Up to 500 V can appear across the feedback resistor. High
voltage rated resistors can be obtained. However a 1 megohm feedback resistor composed of fve 200k resistors in
series will produce the proper voltage rating.
CAUTIONS
The operating voltages of the PA95 are potentially lethal. During circuit design develop a functioning circuit at the
lowest possible voltages. Clip test leads should be used for "hands off" measurements while troubleshooting.
PA95
+V
S
IN
+IN
Z1
Z2
D2 D1
12
10
1
2
+V
S
IN
+IN
Z1
Z2
12
10
1
2
PA95
Q1 Q2
A.
B.
V
S
V
S
PA96
458 PA96U
PA96
FEATURES
HIGH OUTPUT CURRENT 1.5 AMPS
175 MHz GAIN BANDWIDTH
250 V/-SECOND SLEW RATE
APPLICATIONS
PZT DRIVE
MAGNETIC DEFLECTION
70V LINE AUDIO to 70W
DESCRIPTION
The PA96 is a state of the art high voltage, high current
operational amplifer designed to drive resistive, capacitive
and inductive loads. For optimum linearity, the output stage
is biased for class A/B operation. External compensation
provides user fexibility in maximizing bandwidth at any gain
setting. The safe operating area (SOA) can be observed for
all operating conditions by selection of user programmable
current limit. For continuous operation under load, a heatsink
of proper rating is required.
The hybrid integrated circuit utilizes thick flm (cermet)
TYPICAL APPLICATION
PZT POSITION CONTROL
The MOSFET output stage of the PA96 provides superior
SOA performance compared to bipolar output stages where
secondary breakdown is a concern. The extended SOA is
ideal in applications where the load is highly reactive and
may impose simultaneously both high voltage and high cur-
rent across the output stage transistors. In the fgure above
a piezo-electric transducer is driven to high currents and high
voltages by the PA96.
8
7
6
5
4
3
2
1
TOP VIEW
C
L
+V
S
+IN
-IN
-V
S
COMP
COMP
OUT
R
CL
C
C
+275V
-15V
PA96
_
+
-
+
C
C
R
CL
R
I
R
F
3
5
4
6
8
7
1
2
+Vs
COMP
COMP
-Vs
+IN
-IN
OUT
CL
8-PIN TO-3
PACKAGE STYLE CE
MAY 2009
APEX PA96UREVE
PA96
PA96U 459
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SPECIFICATIONS
SUPPLY VOLTAGE, +V
S
to V
S
300V
OUTPUT CURRENT, continuous 1.5A,
S
to V
S
TEMPERATURE, pin solder, 10s 300C
1
150C
TEMPERATURE RANGE, storage 65 to 150C
OPERATING TEMPERATURE, case 55 to 125C
2
MIN TYP MAX UNITS
INPUT
BIAS CURRENT, initial 200 pA
INPUT RESISTANCE, DC 100 G
3
+V
S
13 V
3
V
S
+ 13 V
NOISE 100KHz bandwidth, 1k R
s
6 V RMS
GAIN
OPEN LOOP @ 15Hz R
L
= 1k, C
C
=100pF 96 114 dB
GAIN BANDWIDTH PRODUCT @ 1MHz VS = 150V, -VS = 150V, 100 175 MHz
A = -100, RF = 100K
PHASE MARGIN Full temperature range, using 60
recommended C
C
for gain.
PBW 250V p-p output, 100, 100 KHz
+150V Supplies, Cc = 0pf
OUTPUT
VOLTAGE SWING
3
I
O
= 1.5A +V
S
12 +V
S
5.6 V
VOLTAGE SWING
3
I
O
= 1.5A V
S
+ 12 V
S
+ 10 V
VOLTAGE SWING
3
I
O
= 0.1A +V
S
8 V
VOLTAGE SWING
3
I
O
= 0.1A V
S
+ 8 V
CURRENT, continuous, DC 1.5 A
SLEW RATE A
V
= 100, 150V Supplies, 250 load 200 250 V/S
negative slope, Positiveslope much
faster
V
= 100, 1V Step, C
C
= 0pF 2 S
RESISTANCE, open loop DC, 1A Load 7 10
THERMAL
RESISTANCE, AC Junction to Case
4
Full temperature range. f > 60Hz 1.2 1.3 C/W
RESISTANCE, DC Junction to Case Full temperature range. f < 60Hz 1.6 1.8 C/W
RESISTANCE, Junction to Ambient 30 C/W
TEMPERATURE RANGE, case Meets full range specifcations -25 85 C
POWER SUPPLY
CURRENT, Quiescent total 25 30 35 mA
CURRENT, Quiescent output stage only 10 mA
NOTES: 1. Long term operation at the maximum junction temperature will result in reduced product life. Derate power dissipation to achieve
high MTTF.
2. The power supply voltage specifed under typical (TYP) applies unless noted as a test condition.
3. +V
S
and V
S
S
is measured from +V
S
to V
S
.
CAUTION
PA96
460 PA96U
3
2
1
.2
.3
.4
.5
10 20 30 4050 100 200 300
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

o
r

V
S

(
A
)
S
V
O
(V)
.1
SOA
T

=

1
0
0
m
s
s
t
e
a
d
y

s
t
a
t
e

T
C
=

1
2
5
C
s
t
e
a
d
y

s
t
a
t
e

T
C
=

8
5
C
s
t
e
a
d
y

s
t
a
t
e

T
C
=

2
5
C
CASE TEMPERATURE, C
100
90
80
70
60
50
40
30
20
10
0
-35 125 105 85 65 45 25 5 -15 -55
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

W
POWER DERATING
POWER SUPPLY RAIL to RAIL
270 210 150 90 30
Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

m
A
30.0
30.1
30.2
30.3
30.4
30.5
30.6
30.7
30.8
30.9
31.0
QUIESCENT CURRENT vs. POWER SUPPLY
TEMPERATURE, C
50
45
40
35
30
25
20
15
10
5
0
-35 125 105 85 65 45 25 5 -15 -55
Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

m
A
QUIESCENT CURRENT vs. TEMP.
POWER SUPPLY, RAIL to RAIL
2.5
2
1.5
1
.5
0
-.5
-1
-1.5
-2
-2.5
270 210 150 90 30
D
C

O
F
F
S
E
T

R
T
I
,

m
V
DC OFFSET vs. POWER SUPPLY
OUTPUT CURRENT, A
15
12
9
6
3
0
0.0 2.0 1.6 1.2 0.8 0.4
V
S

-

V
O
,

(
V
)
V
O
- (-V
S
)
V
S
- V
O
LARGE SIGNAL PULSE RESPONSE
TIME, (sec)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
125
-120
-75
-25
25
75
10 25 20 15 5 0
+V
S
= 150V
-V
S
= 150V
A = -100
C
C
= 0
SMALL SIGNAL PULSE RESPONSE
TIME, (sec)
10
-10
-6
-2
2
6
10 25 20 15 5 0
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
+V
S
= 150V
-V
S
= 150V
A = -100
C
C
= 0
RAIL TO RAIL PULSE RESPONSE
TIME, (sec)
250
-250
-150
-50
50
150
10 25 20 15 5 0
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
+V
S
= 150V
-V
S
= 150V
A = -100
C
C
= 0
-V
S
= -15V
-V
S
= -150V
0 20 40 60 80 100 120 140 160
+V
S
VOLTAGE
200
180
160
140
120
100
80
60
40
20
0 G
A
I
N

B
A
N
D
W
I
D
T
H

P
R
O
D
U
C
T

@

1
M
H
z
GAIN BANDWIDTH vs. +SUPPLY VOLTAGE OPEN LOOP PHASE RESPONSE
FREQUENCY, (Hz)
P
H
A
S
E
,

)
90
-360
-270
-180
-90
0
1K 100M 10M 1M 100K 10K 100 10
330pF
22pF
0pF
330pF
22pF
0pF
OPEN LOOP FREQUENCY RESPONSE
FREQUENCY, (Hz)
G
A
I
N
,

d
b
160
-40
0
40
80
120
1K 100M 10M 1M 100K 10K 100 10
330pF
22pF
0pF
PA96
PA96U 461
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
Please read Application Note 1 General Operating Con-
siderations which covers stability, supplies, heat sinking,
Powers Application Notes library, Technical Seminar Workbook,
SPECIAL PRECAUTIONS
The PA96 operates with up 300V rail to rail voltage, and
delivers amperes of current. Precautions should be taken for
the safety of the user and the amplifer.
Although the non-operating common mode input range is rail
to rail, the differential input voltage must not exceed 15 V.
Therefore; if the feedback ratio is less than 10, even if
caused by disconnecting a signal source , typical power turn
on transients can destroy the amplifer.
Similarly in a voltage follower application a large differential
transient can be generated if the slew rate of the input is greater
than that of the voltage follower.
Therefore it is prudent to clamp the input with series back
to back diodes as shown below.
If experimentally optimizing the compensation capacitor,
turn off the supplies and let them bleed to low voltage before
installing each new value. Otherwise internal current pulses of
up to 3 amps can be induced. Also, do you want your fngers
around 300V?
Essentially the full rail to rail power supply voltage may be
applied to the compensation capacitor. A 400V COG or Mica
capacitor is recommended.
POWER BANDWIDTH
The power bandwidth is 1/( x the negative edge slew time).
The slew time is determined by the compensation capacitor,
load, and internal device capacitance; it is independent of
closed loop gain. The uncompensated power bandwidth is
typically 100kHz for a 250Vp-p output signal into 100. It typi-
cally increases to above 300KHz with no load.
COMPENSATION TABLE
The following table tabulates recommended compensation
capacitor values vs. gain. These values will typically result in
less than 2% overshoot and a -3db small signal bandwidth of
greater than 1MHz, except under operating conditions where
uncompensated gain bandwidth is too low to support a 1MHz
bandwidth. (See gain bandwidth vs. Plus power supply curves).
Note that other factors such as capacitance in parallel with
the feedback resistor may reduce circuit bandwidth from that
determined from the gain bandwidth curve.
Cc Inverting Gain
From To
150pf 1 2
51pf 2 5
33pf 5 10
22pf 10 20
10pf 20 50
5pf 50 100
None 100 up
Cc Non-Inverting Gain
From To
330 pf 1 2
150pf 2 3
51pf 3 6
33pf 6 10
22pf 10 20
10pf 20 50
5pf 50 100
None 100 up
CURRENT LIMIT
For proper operation the current limit resistor, Rcl, must
be connected as shown in the external connections diagram.
The minimum value is 0.2, with a maximum practical value
of 100. For optimum reliability the resistor should be set as
high as possible. The value is calculated as I
L
= 0.68V/Rcl. Note
that the 0.68V is reduced by 2mV every C rise in temperature.
Also note that the current limit can be set such that the SOA
is exceeded on a continuous basis. As an example if the current
limit was set at 1.5A and the supply was at 150V, a short to
ground would produce 225 watts internal dissipation, greatly
exceeding the 83 watt steady state SOA rating.
Under some conditions of load and compensation the am-
plifer may oscillate at a low level when current limit is active,
even though the amplifer is stable otherwise. The current
will be limited to the programmed value in this situation. To
minimize such occurrences, use a non-reactive resistor to
program current limit.
1N4148
1N4148 1N4148
1N4148
PA96
PA97DR
462 PA97DRU
PA97DR
FEATURES
LOW QUIESCENT CURRENT 600A
APPLICATIONS
MASS SPECTROMETERS
SCANNING COILS
TO 880V
SEMICONDUCTOR MEASUREMENT EQUIP-
MENT
PA97DR P r o d u c t I n n o v a t i o n F r o m
Q1 Q2
R1 R2 C1
12
R4
Q3
CC1
CC2
Q6
Q5
R7
R8
2
1
R9
Q14
R16
10
R18
Q15
R5
8
6
4
Q4
OUT
Q12
R14
+V
S
IN
+IN
V
S
R10
Q10A Q10B
DESCRIPTION
The PA97DR is a high voltage MOSFET operational
amplifer designed as a low cost solution for driving
continuous output currents up to 10mA and pulse cur-
rents to 15mA into capacitive loads. The safe operating
area (SOA) has no second breakdown limitations. The
MOSFET output stage is biased class C for low qui-
escent current operation. External compensation pro-
vides fexibility in choosing bandwidth and slew rate for
the application. Apex Precision Powers SIP05 pack-
age uses a minimum of board space allowing for high
density circuit boards.
JAN 2009
APEX PA97DRUREVG
PA97DR
PA97DRU 463
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
SUPPLY VOLTAGE, +V
S
to -V
S
900 V
POWER DISSIPATION,continuous @ TC = 25C 5 W
INPUT VOLTAGE, differential (Note 3) -20 20 V
INPUT VOLTAGE, common mode (See Text) -V
S
V
S
V
INPUT
11
(Note 3)
V
S
=250V V
S
30 V
CM
= 90V 80 98 dB
NOISE
10KHz BW, R
S
= 1K,
C
C
= 10pF
2 VRMS
GAIN
OPEN LOOP @ 15Hz R
L
= 5K, C
C
= 10pF 94 111 dB
L
= 5K, C
C
= 10pF 1 MHz
POWER BANDWIDTH R
L
= 5K, C
C
= 10pF 2 kHz
PHASE MARGIN, A
V
= 100 Full temperature range 60
OUTPUT
O
= 10mA V
S
24 V
S
20 V
SLEW RATE, A
V
= 100 C
C
= 10pF 8 V/S
SETTLING TIME, to 0.1% C
C
= 10pF, 2V step 2 S
RESISTANCE 10mA Load 100
SPECIFICATIONS
PA97DR
464 PA97DRU
C
C
= 10pF.
60Hz.
CAUTION
The PA97DR is constructed from MOSFET transistors. ESD handling procedures must be ob-
served.
POWER SUPPLY
CURRENT, quiescent, amplifer only 0.6 1 mA
THERMAL
RESISTANCE, AC, junction to case (Note 4) Full temp range, F > 60Hz 20 C/W
RESISTANCE, DC, junction to case Full temp range, F < 60Hz 25 C/W
TEMPERATURE RANGE, case 25 +85 C
TEMPERATURE, T (C)
1M .6M 2M 3M
FREQUENCY, F (Hz)
PHASE RESPONSE
P
H
A
S
E
,

)
10 100 10K 1M
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/
H
z
)
-120
-140
-160
-180
-200
-220
OUTPUT CURRENT, I
O
(mA)
INPUT NOISE
1K
2
7
10
20
3
5
15
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

V
O

(
V
)
SAFE OPERATING AREA
20
10
8
6
5
4
3
2
1
100 200 300 400 600 1000
C
C
=10pF
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S
,

(
m
A
)
1
0
0
S
D
C
,
T
C =
2
5
C
D
C
,
T
C =
8
5
C
D
C
,
T
C =
1
2
5

C
S
V
O
(V)
1 10M
FREQUENCY, F (Hz)
0
60
120
140
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
20
40
80
100
100 1K 10K .1M 1M 10
C
C
=

1
0
p
F
1.08
1.04
1.00
0.96
0.92
0.88
100 200 300 400 500 600 700 800 900 N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I

(
X
)
S
(V)
QUIESCENT CURRENT
14
13
12
11
10
9
0 2 4 6 8 10
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
5
4
3
2
1
0
0 25 50 75 100 125 150
SWING FROM +V
S
SWING FROM -V
S
10K 30K
FREQUENCY, F (Hz)
50
1K
500
POWER RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
100
1K
C
C
= 10pF
200
T = T
C
T = T
A
PA97DR
PA97DRU 465
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
* 0.01F or greater ceramic power supply bypassing
required. CC = 10pF minimum, 1kV NPO (COG).
PHASE COMPENSATION
GAIN C
C
10 10pF
TEMPERATURE, T (C)
1M .6M 2M 3M
FREQUENCY, F (Hz)
PHASE RESPONSE
P
H
A
S
E
,

)
10 100 10K 1M
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/
H
z
)
-120
-140
-160
-180
-200
-220
OUTPUT CURRENT, I
O
(mA)
INPUT NOISE
1K
2
7
10
20
3
5
15
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

V
O

(
V
)
SAFE OPERATING AREA
20
10
8
6
5
4
3
2
1
100 200 300 400 600 1000
C
C
=10pF
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S
,

(
m
A
)
1
0
0
S
D
C
,
T
C =
2
5
C
D
C
,
T
C =
8
5
C
D
C
,
T
C =
1
2
5

C
S
V
O
(V)
1 10M
FREQUENCY, F (Hz)
0
60
120
140
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
20
40
80
100
100 1K 10K .1M 1M 10
C
C
=

1
0
p
F
1.08
1.04
1.00
0.96
0.92
0.88
100 200 300 400 500 600 700 800 900 N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I

(
X
)
S
(V)
QUIESCENT CURRENT
14
13
12
11
10
9
0 2 4 6 8 10
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
5
4
3
2
1
0
0 25 50 75 100 125 150
SWING FROM +V
S
SWING FROM -V
S
10K 30K
FREQUENCY, F (Hz)
50
1K
500
POWER RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
-
P
)
100
1K
C
C
= 10pF
200
T = T
C
T = T
A
TYPICAL APPLICATION
mented mirror systems. The composite mirror may be com-
posed of hundreds of elements, each requiring focusing un-
der computer control. In such complex systems the PA97DR
reduces the costs of power supplies and cooling with its ad-
vantages of low cost and low quiescent power consumption
while increasing circuit density with the SIP package.
F
R
PA97DR
IN
R
PIEZO DRIVE
S
V
S
+V
OUT
V
COMPUTER
FOCUS
COMMAND
VOLTAGE
C
C
1
2
10
4
8
12
6
1 2 4 6 8 10 12
* *
IN +IN CC1 CC2 OUT Vs +Vs
C
C
*
PATENTED
7-pin SIP
PACKAGE STYLE DR
GENERAL
Please read the General Operating Considerations section, which covers stability, supplies, heatsinking, mount-
ing, current limit, SOA interpretation, and specifcation interpretation. Additional information can be found in the ap-
plication notes. For information on the package outline, heatsinks, and mounting hardware, consult the Accessory
and Package Mechanical Data section of the handbook.
CURRENT LIMIT
The PA97DR has no provision for current limiting the output.
PA97DR
466 PA97DRU
applications the common mode input voltage range of the PA97DR is restricted. The input pins must always be a
least 30V from either supply voltage but never more than 500V. This means that the PA97 cannot be used in ap-
plications where the supply voltages are extremely unbalanced. For example, supply voltages of +800V and 100V
would not be allowed in an application where the non-inverting pin is grounded because in normal operation both
input pins would be at 0V and the difference voltage between the positive supply and the input pins would be 800V.
In this kind of application, however, supply voltages +500V and -100V does meet the input common mode voltage
range requirements since the maximum difference voltage between the inputs pins and the supply voltage is 500V
(the maximum allowed). The output has no such restrictions on its voltage swing. The output can swing within 24V
of either supply voltage regardless of value so long as the total supply voltage does not exceed 900V.
INPUT PROTECTION
Although the PA97DR can withstand differential input voltages up to 20V, additional external protection is recom-
mended. In most applications 1N4148 or 1N914 signal diodes are suffcient (D1, D2 in Figure 2a). In more demand-
ing applications where low leakage or low capacitance are of concern 2N4416 or 2N5457-2N5459 JFETs connected
as diodes will be required (Q1, Q2 in Figure 2b). In either case the input differential voltage will be clamped to .7V.
This is suffcient overdrive to produce maximum power bandwidth. Note that this protection does not automatically
protect the amplifer from excessive common mode input voltages.
Unidirectional zener diode transient suppressors are recommended as pro-
tection on the supply pins. The zeners clamp transients to voltages within
the power supply rating and also clamp power supply reversals to ground.
Whether the zeners are used or not, the system power supply should be
evaluated for transient performance including power-on overshoot and pow-
er-off polarity reversal as well as line regulation.
Conditions which can cause open circuits or polarity reversals on either pow-
er supply rail should be avoided or protected against. Reversals or opens on
the negative supply rail is known to induce input stage failure. Unidirectional
transzorbs prevent this, and it is desirable that they be both electrically and
physically as close to the amplifer as possible.
EXTERNAL COMPONENTS
The compensation capacitor Cc must be rated for the total supply voltage.
10pF NPO (COG)capacitor rated at 1kV is recommended.
Of equal importance is the voltage rating and voltage coeffcient of the gain
setting feedback resistor. Typical voltage ratings of low wattage resistors are
150 to 250V. Up to 900 V can appear across the feedback resistor. High
voltage rated resistors can be obtained. However a 1 megohm feedback
resistor composed of fve 200k resistors in series will produce the proper
voltage rating.
CAUTIONS
The operating voltages of the PA97DR are potentially lethal. During circuit design develop a functioning circuit at
the lowest possible voltages. Clip test leads should be used for "hands off" measurements while troubleshooting.
With no internal current limit, proper choice of load impedance and supply voltage is required to meed SOA limitia-
tions. An output short circuit will destroy the amplifer within milliseconds.
STABILITY
The PA97DR is stable at gains of 10 or more with a NPO (COG) compensation capacitor of 10pF. The compensation
pins 4 and 6 to prevent spurious oscillation. A compensation capacitor less than 10pF is not recommended.
PA97DR
+V
S
IN
+IN
Z1
Z2
D2 D1
12
10
1
2
+V
S
IN
+IN
Z1
Z2
12
10
1
2
PA97DR
Q1 Q2
A.
B.
V
S
V
S
FIGURE 2.
PA98 PA98A
PA98U 467
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA98, PA98A
FEATURES
APPLICATIONS
PIEZO TRANSDUCER EXCITATION
TO 430V
ELECTROSTATIC TRANSDUCERS &
DEFLECTION
9
6
12
11
7
2 1
5 4
COMP
OUT
+V
S
+V
S
V
S
V
S
C
10
C
L
L
8
Q1 Q2
Q3
Q8
Q9
Q6 Q7
Q12
Q10A
Q10B
Q11
Q17
Q13
Q15
Q18
D1
D23
D2
IN +IN
DESCRIPTION
The PA98 is a high voltage, high power bandwidth
MOSFET operational amplifer designed for output
currents up to 200mA. Output voltages can swing up
to 215V with a dual supply and up to +440 volts with
a single supply. The safe operating area (SOA) has
no second breakdown limitations and can be observed
with all types of loads by choosing an appropriate cur-
rent limiting resistor. High accuracy is achieved with a
cascode input circuit confguration. All internal biasing
is referenced to a bootstrapped zener-MOSFET cur-
rent source. As a result, the PA98 features an unprec-
edented supply range and excellent supply rejection.
The MOSFET output stage is biased on for linear oper-
ation. External compensation provides user fexibility.
This hybrid circuit utilizes thick flm (cermet) resistors,
ceramic capacitors and silicon semiconductor chips to
maximize reliability, minimize size and give top perfor-
mance. Ultrasonically bonded aluminum wires provide
reliable interconnections at all operating temperatures.
The Power SIP package is electrically isolated.
AUG 2008
APEX PA98REVJ
PA98 PA98A
468 PA98U
CAUTION
1 2 3 4 5 6 7 8 9 10
IN +IN
R
CL
+V
s
V
s
TO LOAD
AND FEEDBACK
11 12
R
c
C
c
*
*
NC
PATENTED
12-pin SIP
PACKAGE
STYLE DP
Package style EE
SUPPLY VOLTAGE, +V
S
to -V
S
450 V
OUTPUT CURRENT, continuous within SOA 200 mA
C
= 25C (Note 2) 30 W
S
V
S
V
SPECIFICATIONS
Parameter
Test Condi-
tions
1
PA98 PA98A
INPUT
OFFSET VOLTAGE, initial 0.5 2 0.25 0.5 mV
Full temp range
10 30 5 10 V/C
OFFSET VOLTAGE vs. supply 3 10 * * V/V
OFFSET VOLTAGE vs. time 75 * V/kHz
BIAS CURRENT, initial (Note 3) 5 50 3 10 pA
BIAS CURRENT, vs. supply 0.01 * pA/V
(Note 3)
10 100 3 30 pA
11
*
COMMON MODE VOLTAGE
RANGE (Note 4)
V
S
- 15 * V
DC
V
CM
= 90V 90 110 * * dB
PA98 PA98A
PA98U 469
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
C
C
= 68pF, R
C
= 100. DC input specifcations
are value given. Power supply voltage is typical rating.
internal power dissipation to achieve high MTTF. Ratings apply only to output transistors. An addi-
tional 10W may be dissipated due to quiescent power.
4. +V
S
and V
S
60Hz.
Parameter
Test Condi-
tions
1
PA98 PA98A
NOISE 100kHz BW,
R
S
= 1K,
C
C
= 10pf
1 * V RMS
GAIN
OPEN LOOP GAIN @ 15Hz R
L
= 2K,
C
C
= OPEN
96 111 * * dB
@ 1MHz
R
L
= 2K,
C
C
= 3.3pf
100 * MHz
POWER BANDWIDTH C
C
= 10pf 300 * kHz
C
C
= 3.3pf 500 * kHz
PHASE MARGIN Full temp range 60 *
OUTPUT
O
= 200mA V
S
- 10 V
S
- 6.5 * * V
O
= 75mA V
S
- 8.5 V
S
- 6.0 * * V
O
= 20mA V
S
- 8.0 V
S
- 5.5 * * V
C
= 85C 200 * mA
SLEW RATE, A
V
= 20 C
C
= 10pf 400 * V/S
SLEW RATE, A
V
= 100 C
C
= OPEN 1000 700 * V/S
CAPACITIVE LOAD, A
V
= +1 Full temp range 470 * pF
C
= 10pf,
2V step
1 * S
CL
= 0 50 *
POWER SUPPLY
VOLTAGE (Note 6) Full temp range 15 150 225 * * * V
THERMAL
RESISTANCE, AC,
Full temp range,
F > 60Hz
2.5 * C/W
RESISTANCE, DC,
junction to case
Full temp range,
F < 60Hz
4.2 * C/W
RESISTANCE, junction to air Full temp range 30 * C/W
specifcations
-25 +85 * * C
PA98 PA98A
470 PA98U
CURRENT LIMIT
RESISTOR VALUE, R
CL
()
2 10 5 1
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
m
A
)
300
50
20
20
500
100
200
30
FREQUENCY, F (Hz)
10 1K 100 1
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)
100
40
20
10K
120
60
80
140
1M 100K
FREQUENCY, F (Hz)
10K 1M 100K 1K
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
100
40
20
10M
120
60
80
140
C
C
= 10pF
INPUT NOISE VOLTAGE
FREQUENCY, F (Hz)
100 10K 1K 10 I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
H
z
)
10
3
2
100K
15
5
7
20
HARMONIC DISTORTION
FREQUENCY, F (Hz)
100 10K 1K 10
D
I
S
T
O
R
T
I
O
N
,

(
%
)
.03
.003
.001
100K
.05
.005
.01
A
V
= 30
P
O
= 15W
C
C
= 10pF
R
L
= 1K
SLEW RATE
C
(pF)
15 45 30 0
S
L
E
W

R
A
T
E
,

(
V
/
S
)
500
200
100
60
1000
75 90
FREQUENCY, F (Hz)
200K 2M 500K 50K
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
P
P
)
250
125
100
75
50
25
5M
500
C
C

=

6
8
p
F
C
C

=

3
.
3
p
F
C
C

=

1
0
p
F
R
L
= 2K
OUTPUT CURRENT, I
O
(mA)
50 200 150 100 0
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

-

V
O

(
V
)
9
8
7
6
5
4
250
10
T
C

=

1
2
5
C
T
C
= -55C
T
C
=
2
5
C
FREQUENCY, F (Hz)
100 1K 1M 100K 10K 10M 10
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
80
60
40
20
0
-20
C
C
= 3.3pF
C
C
= 10pF
C
C
= 68pF
20M
120
100
QUIESCENT CURRENT
S
(V)
100 200 450 400 300 0
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
1.15
1.10
1.05
1.00
.95
.90
TC
=
1
2
5
C
T
C
= -55C
T
C
= 25C
1.20
PHASE RESPONSE
FREQUENCY, F (Hz)
1M 10M 40M .2M
P
H
A
S
E
,

)
0
-45
-90
-135
-180
-225
-270
C
C
= 68pF
C
C
= 3.3pF
C
C
= 10pF
POWER DERATING
CASE TEMPERATURE, T
C
(C)
25 50 125 100 75 150 0
O
U
T
P
U
T

S
T
A
G
E
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
40
32
24
16
8
0
PA98 PA98A
PA98U 471
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
CURRENT LIMIT
CL
gram. The minimum value is 1.4 ohm, however for optimum reliability the resistor value should be set as high as
possible. The value is calculated as follows; with the maximum practical value of 30 ohms.
.7
R
CL
=
I
LIM
- .016
The MOSFET output stage of this power operational
amplifer has two distinct limitations:
1. The current handling capability of the MOSFET ge-
ometry and the wire bonds.
used.
The safe operating area curves defne the maximum
additional internal power dissipation the amplifer can
tolerate when it produces the necessary output to drive
an external load. This is not the same as the absolute
maximum internal power dissipation listed elsewhere in
the specifcation since the quiescent power dissipation
is signifcant compared to the total.
SOA
S
- V
O
(V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

-
V
S

(
m
A
)
25 50 75 100 125 250 500
500
300
200
100
50
30
20
10
1
0
0
m
S
2
0
0
m
S
D
C
,

T
C
=

2
5
C
D
C
,

T
C
=

1
2
5
C
D
C
,

T
C
=

8
5
C
TYPICAL APPLICATION
DYNAMIC FOCUSING
Dynamic focusing is the active correction of focusing voltage
as a beam traverses the face of a CRT. This is necessary in
high resolution fat face monitors since the distance between
cathode and screen varies as the beam moves from the center
of the screen to the edges. PA98 lends itself well to this func-
tion since it can be connected as a summing amplifer with
inputs from the nominal focus potential and the dynamic cor-
rection. The nominal might be derived from a potentiometer, or
perhaps automatic focusing circuitry might be used to generate this potential. The dynamic correction is generated
from the sweep voltages by calculating the distance of the beam from the center of the display.
PHASE COMPENSATION
Gain C
C
R
C

1 68pF 100
20 10pF 330
100 3.3pF 0
C
C
2
z = x + y
2
IN1
R
F
R
CL
R
+225V
225V
PA98
IN2
R
DC
FOCUS
X SWEEP
SAMPLE
Y SWEEP
SAMPLE
TO
FOCUS
GRID
PA98 PA98A
472 PA98U
INPUT PROTECTION
Although the PA98 can withstand differential voltages up to 25V, additional external protection is recommended.
Since the PA98 is a high speed amplifer, low leakage, low capacitance JFETs connected as diodes are recom-
mended (e.g. 2N4416, Q1-Q4 in Figure 1). The differential input voltage will be clamped to 1.4V. This is suffcient
overdrive to produce maximum power bandwidth.
protection on the supply pins. The zeners clamp transients to voltages
within the power supply rating and also clamp power supply reversals to
ground. Whether the zeners are used or not, the system power supply
should be evaluated for transient performance including power-on over-
shoot and power-off polarity reversals as well as line regulation.
power supply rail should be avoided or protected against. Reversals or
opens on the negative supply rail is known to induce input stage failure.
Unidirectional transzorbs prevent this, and it is desirable that they be
both electrically and physically as close to the amplifer as possible.
STABILITY
C
C
R
C
INTERNAL POWER DISSIPATION AND HEATSINK SELECTION
tures use Power Design
1
revision 10 or higher, or use the following procedure:
Find internal dissipation (PD) resulting from driving the load. Use Power Design or refer to Apex Precision Power
Applications Note 1, General Operating Considertaions, paragraph 7. Find total quiescent power (PD
Q
) by multiply-
ing 0.025A by V
SS
(total supply voltage). Find output stage quiescent power (PD
QOUT
) by multiplying 0.001 by V
SS
.
T
C
- T
A
PD + PD
Q
R
SA
= -0.1C/W
Where: T
C
T
A
T
J
- T
A
- (PD + PD
QOUT
)
*
R
JC
PD + PD
Q
R
SA
=

-0.1C/W
Where: T
J
R
JC
+V
S
IN
+IN
Z1
Z2
11, 12
7, 8
1
2
6
PA98
Q1
Q2
V
S
Q3
Q4
FIGURE 1.
OVERVOLTAGE
PROTECTION
PA107DP
PA107DPU 473
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA107DP
GENERAL DESCRIPTION
The PA107DP is a state of the art wideband high pow-
er operational amplifer designed to drive resistive, ca-
pacitive or inductive loads. For optimum linearity the
output stage is biased for class A/B operation. Feed
forward technology is used to obtain wide bandwidth
and excellent DC performance, but constricts use to
inverting mode only. External compensation allows the
user to obtain both high gain and wide bandwidth. Use
of a heatsink is required to realize the SOA.
This hybrid integrated circuit uses thick flm resistors,
ceramic capacitors, and semiconductors to maximize
reliability, minimize size, and give top performance.
Ultrasonically bonded aluminum wires provide reliable
interconnections at all operating temperatures. The 12
pin SIP package occupies only 2 square inches. The
use of compressible insulation washers voids the war-
ranty.
FEATURES
High Voltage 180 Vp-p
High Slew Rate 2500 V/s Minimum
with A
CL
= 20
High Gain Bandwidth 180 MHz
High Output Current 1.5 A Steady State
Within SOA
High Peak Output Current 5 A
APPLICATIONS
Piezo Drive
CRT Beam Intensity Control
ATE Applications
Line Driver
PA107DP P r o d u c t I n n o v a t i o n F r o m
VEE
GND
4
+V
AUX
2
9
-V
AUX
3
+V
AUX
R3
D
S
G
Q1:2
C2
D1
Q13
R5
Q7
Q6
D5
Q5
Q10
D10
D8
D7
R18
R13
R8 R11
R7 R10
Q22 R17
Q18
Q20
Q17
10
OUT
11
+Vsp
12
IN
1
R2
D2
D3
D
S
G Q1:1
D6
Q4
R4
D9 R12
Q21
Q16
Q19 R16
C1
+
-
U1
C3
Q3
Q2
R9
Q12
Q15
C5
R15
C4
Q8
Q14
+V
S
D4
R1
R19 Q9
R14
Q11
8
R6
+V
AUX
-V
AUX
-V
AUX
+V
AUX
+V
AUX
-V
AUX
+V
S
-V
S
-V
S
-V
SP
AUG 2009
APEX PA107DPUREVA
PA107DP
474 PA107DPU
SUPPLY VOLTAGE, +V
S
to V
S
40 200 V
SUPPLY VOLTAGE, V
S
-20 -100 V
SUPPLY VOLTAGE, -V
AUX
to +V
AUX
20 36 V
SUPPLY VOLTAGE, -V
AUX
-10 -18 V
OUTPUT CURRENT, Steady State, (Within SOA) 1.5 A
OUTPUT CURRENT, peak, (Within SOA) 5 A
POWER DISSIPATION, internal, DC 62.5 W
INPUT VOLTAGE -V
AUX
+ 2 +V
AUX
- 2 V
TEMPERATURE RANGE, storage -40 +85 C
OPERATING TEMPERATURE, case -25 +85 C
V
S
= 100V, -V
S
= -100V,
V
AUX
= 15V, -V
AUX
= -15V
INPUT
OFFSET VOLTAGE vs. temperature 10 V/C
INPUT RESISTANCE, DC 13 G
INPUT VOLTAGE RANGE -V
AUX
+ 2 +V
AUX
- 2 V
NOISE, RTI 1k source, 500 kHz BW, A
CL
101 13 nV/Hz
GAIN
OPEN LOOP GAIN @ DC 140 dB
OPEN LOOP GAIN @ 1MHz 40 dB
POWER BANDWIDTH, 170Vp-p Full temperature range 2 MHz
OUTPUT
VOLTAGE SWING 10M in parallel with 10 pf 187 V
P-P
VOLTAGE SWING I
O
= 1.5A V
S
10 V
CURRENT, peak 5 A
CURRENT, Steady State (within SOA) 1.5 A
SLEW RATE, 25% to 75% 2500 3000 V/S
SETTLING TIME to 0.1% 12 S
SPECIFICATIONS
PA107DP
PA107DPU 475
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
HIGH VOLTAGE SMALL SIGNAL RESPONSE
Frequency, (Hz)
V
S
=100V, V
AUX
=15V
-40
0
40
80
120
160 45
-180
-135
-90
-45
0
10 100 1K 10K 100K 1M 10M100M
P
h
a
s
e
,

(
)
Phase
Amplitude
A
m
p
l
i
t
u
d
e
,

(
d
B
)
LOW VOLTAGE SMALL SIGNAL RESPONSE
-40
0
40
80
120
160 45
-180
-135
-90
-45
0
10 100 1K 10K 100K 1M 10M100M
Frequency, (Hz)
V
S
=20V, V
AUX
=10V
P
h
a
s
e
,

(
)
Phase
Amplitude
A
m
p
l
i
t
u
d
e
,

(
d
B
)
Rail to Rail Supply Voltage, V
SS
(V)
V
AUX
=15V
N
o
r
m
a
l
i
z
e
d

S
u
p
p
l
y

C
u
r
r
e
n
t
,

I
Q

(
X
)
40 200 180 160 140 120 100 80 60
1.02
0.82
0.84
0.86
0.88
0.9
0.92
0.94
0.96
0.98
1
HIGH VOLTAGE SUPPLY CURRENT
RESPONSE to 500KHz SQUARE WAVE
Time, T (s)
A =-22, V
S
=100V, V
AUX
=15V
A
m
p
l
i
t
u
d
e
,

V
O

(
V
)
0 1.6 1.2 0.8 0.4
100
-100
-80
-60
-40
-20
0
20
40
60
80
2
Time, (ns)
A =-22, V
S
=100V, V
AUX
=15V
100
-100
-60
-20
20
60
0.0n 20n 40n 60n 80n 100n
POSITIVE SLEW
A
m
p
l
i
t
u
d
e
,

(
V
)
Time, (ns)
A =-22, V
S
=100V, V
AUX
=15V
100
-100
-60
-20
20
60
0.0n 20n 40n 60n 80n 100n
NEGATIVE SLEW
A
m
p
l
i
t
u
d
e
,

(
V
)
Case Temperature, T
C
(C)
I
n
t
e
r
n
a
l

P
o
w
e
r

D
i
s
s
i
p
a
t
i
o
n
,

P
D

(
W
)
0 150 125 100 75 50 25
0
10
20
30
40
50
60
70
80
90
DC Power
AC Power
POWER DERATING
Case Temperature, T
C
(C)
N
o
r
m
a
l
i
z
e
d

Q
u
i
e
s
c
e
n
t

C
u
r
r
e
n
t
,

I
Q
(
V
S
)

(
X
)
-40 80 60 40 20 0 -20
0.9
0.95
1
1.05
1.1
1.15
HIGH VOLTAGE CURRENT vs. TEMPERATURE
Output Frequency, F
OUT
(KHz)
H
V

S
u
p
p
l
y

C
u
r
r
e
n
t
,

I
V
S

(
m
A
)
100 3100 2600 2100 1600 1100 600
0
50
100
150
200
250
300
350
V
S
=100V
V
AUX
=15V
10pF Load
V
O
=170V
P-P
Sinewave
HIGH VOLTAGE CURRENT vs. FREQUENCY
NOTES:
1. All Min/Max characteristics and specifcations are guaranteed over the Specifed Operating Condi-
C
= 25C.
4. +V
S
and V
S
denote the positive and negative supply voltages to the output stages.
5. +V
AUX
and V
AUX
denote the positive and negative supply voltages to the input stages.
60Hz.
POWER SUPPLY
VOLTAGE, +V
S
20 100 V
VOLTAGE, -V
S
-100 -20 V
VOLTAGE, +V
AUX
10 15 18 V
VOLTAGE, -V
AUX
-18 -15 -10 V
CURRENT, QUIESCENT, +V
S
20 30 35 mA
CURRENT, QUIESCENT, -V
S
20 30 35 mA
CURRENT, QUIESCENT, -V
AUX
16 19 21 mA
CURRENT, QUIESCENT, +V
AUX
16 19 21 mA
THERMAL
RESISTANCE, AC, junction to case (Note 6) 1.5 C/W
RESISTANCE, DC junction to case 2 C/W
RESISTANCE, junction to air 30 C/W
PA107DP
476 PA107DPU
1 2 3 4 5 6 7 8 9 10 11 12
C3
1uF
C4
1uF
+V
SP
C1-2 = 10uF/A out (peak), electrolytic/tantalum, low frequency bypass.
C3-4 = 1uF 25V X7R ceramic capacitor recomended.
C5-6 = 1uF 200V X7R ceramic capacitor recomended.
+
C5
1uF
C6
1uF C1 C2 +
IN -V
S
-V
SP
OUT +V
S
OPEN OPEN OPEN GND +V
AUX
-V
AUX
12-pin SIP
Package Style DP
See Package Style EE
HIGH VOLTAGE SMALL SIGNAL RESPONSE
Frequency, (Hz)
V
S
=100V, V
AUX
=15V
-40
0
40
80
120
160 45
-180
-135
-90
-45
0
10 100 1K 10K 100K 1M 10M100M
P
h
a
s
e
,

(
)
Phase
Amplitude
A
m
p
l
i
t
u
d
e
,

(
d
B
)
LOW VOLTAGE SMALL SIGNAL RESPONSE
-40
0
40
80
120
160 45
-180
-135
-90
-45
0
10 100 1K 10K 100K 1M 10M100M
Frequency, (Hz)
V
S
=20V, V
AUX
=10V
P
h
a
s
e
,

(
)
Phase
Amplitude
A
m
p
l
i
t
u
d
e
,

(
d
B
)
Rail to Rail Supply Voltage, V
SS
(V)
V
AUX
=15V
N
o
r
m
a
l
i
z
e
d

S
u
p
p
l
y

C
u
r
r
e
n
t
,

I
Q

(
X
)
40 200 180 160 140 120 100 80 60
1.02
0.82
0.84
0.86
0.88
0.9
0.92
0.94
0.96
0.98
1
HIGH VOLTAGE SUPPLY CURRENT
RESPONSE to 500KHz SQUARE WAVE
Time, T (s)
A =-22, V
S
=100V, V
AUX
=15V
A
m
p
l
i
t
u
d
e
,

V
O

(
V
)
0 1.6 1.2 0.8 0.4
100
-100
-80
-60
-40
-20
0
20
40
60
80
2
Time, (ns)
A =-22, V
S
=100V, V
AUX
=15V
100
-100
-60
-20
20
60
0.0n 20n 40n 60n 80n 100n
POSITIVE SLEW
A
m
p
l
i
t
u
d
e
,

(
V
)
Time, (ns)
A =-22, V
S
=100V, V
AUX
=15V
100
-100
-60
-20
20
60
0.0n 20n 40n 60n 80n 100n
NEGATIVE SLEW
A
m
p
l
i
t
u
d
e
,

(
V
)
Case Temperature, T
C
(C)
I
n
t
e
r
n
a
l

P
o
w
e
r

D
i
s
s
i
p
a
t
i
o
n
,

P
D

(
W
)
0 150 125 100 75 50 25
0
10
20
30
40
50
60
70
80
90
DC Power
AC Power
POWER DERATING
Case Temperature, T
C
(C)
N
o
r
m
a
l
i
z
e
d

Q
u
i
e
s
c
e
n
t

C
u
r
r
e
n
t
,

I
Q
(
V
S
)

(
X
)
-40 80 60 40 20 0 -20
0.9
0.95
1
1.05
1.1
1.15
HIGH VOLTAGE CURRENT vs. TEMPERATURE
Output Frequency, F
OUT
(KHz)
H
V

S
u
p
p
l
y

C
u
r
r
e
n
t
,

I
V
S

(
m
A
)
100 3100 2600 2100 1600 1100 600
0
50
100
150
200
250
300
350
V
S
=100V
V
AUX
=15V
10pF Load
V
O
=170V
P-P
Sinewave
HIGH VOLTAGE CURRENT vs. FREQUENCY
PA107DP
PA107DPU 477
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PIN DESCRIPTIONS
1 IN Summing Junction Input for Inverting Operational Amplifer
2 +V
AUX
+10V to +18V Supply for Input Circuits
3 -V
AUX
-10V to -18V Supply for Input Circuits
4 GND Ground
5 Open Pin
6 Open Pin
7 Open Pin
8 +V
S
+20V to +100V Supply for Gain and Gate Driver Circuits
9 -V
S
-20V to -100V Supply for Gain and Gate Driver Circuits
10 -V
SP
-20V to -100V Supply for Output Source Follower
11 OUT High Power Output of Amplifer
12 +V
SP
+20V to +100V Supply for Output Source Follower
3. GENERAL
selection, complete Application Notes library, Technical Seminar Workbook and Evaluation Kits.
CAUTION
In order to achieve the highest speed with limited space short circuit protection and thermal protection were sacri-
fced. Do not short the output. Note that if current limiting at 1.5 A could be used, and the output was shorted, internal
dissipation would be 150 W. This would still destroy the amplifer, albeit more slowly.
4. INTERNAL POWER DISSIPATION AND HEATSINK SELECTION
tures use Power Design1 revision 10 or higher, or use the following procedure:
Find internal dissipation (PD) resulting from driving the load. Use Power Design or refer to Apex Applications Note
1, General Operating Considerations, paragraph 7. Find total quiescent power (PD
Q
) by multiplying 0.035 A by V
SS

(total supply voltage), plus 0.021 times the total V
AUX
(+V
AUX
+ |-V
AUX
|). Find output stage quiescent power (PD
QOUT
)
by multiplying 0.001 by V
SS
.
Where:
T
C
T
A
Where:
T
J
R
JC
R
SA
= -0.1C/W
T
C
- T
A
PD +PD
Q
R
SA
= -0.1C/W
T
J
- T
A
- (PD +PD
QOUT
) R
J C
PD +PD
Q
PA107DP
478 PA107DPU
5. REACTIVE LOADS
The PA107DP is stable at a gain of 20 or above when driving either inductive or capacitive loads. However an induc-
tor is essentially a short circuit at DC, therefore there must be enough resistance in series to keep low frequency
power within ratings.
When driving a 1nF capacitive load with a 180 V
P-P
square wave, the current peak is 1 A. Driving the same capacitor
with a 2.3 MHz sine wave, the power bandwidth frequency, results in 2.6 A
P-P
. The power dissipated in the amplifer
while driving a purely capacitive load is given by the formula:
P = 2V
PK
V
S
/X
C
P = 2I
PK
V
S
/
Where:
V
PK
= Peak Voltage
V
S
= Supply Voltage
X
C
= Capacitive Reactance
Notice that the power increases as V
PK
increases, such that the maximum internal dissipation occurs when V
PK
is
maximum. The power dissipated in the amplifer while driving 1 nF at 2.3 MHz would be 82.76 W. This would not
be a good thing to do! But driving 1 nF at 1 MHz at 180V
P-P
would result in 36.0 W, which could be within the AC
power rating.
This formula is optimistic; it is derived for an ideal class B amplifer output stage.
6. FEEDBACK CONSIDERATIONS
The output voltage of an unloaded PA107DP can easily go as high as 95 V. All of this voltage can be applied across
the feedback resistor, so the minimum value of a W resistor in the feedback is 18050. Practically, 20K is the
minimum value for a un-derated W feedback resistor.
In order to provide the maximum slew rate, power bandwidth, and useable gain bandwidth; the PA107DP is not
designed to be unity gain stable. It is necessary to add external compensation for gains less than 20. Often lower
performance op-amps may be stabilized with a capacitor in parallel with the feedback resistor. This is because there
is effectively one additional pole affecting the response. In the case of the PA107DP, however there are multiple
poles clustered near 30 MHz, therefore this approach does not work. A method of compensation that works is to
choose a feedback capacitor such that the time constant of the feedback capacitor times the feedback resistor is
greater than 33 n-seconds. Also install a capacitor from pin 1 to ground, the summing junction, greater than 20
times as large as the feedback capacitor. The feedback capacitor or summing junction capacitor without the other
will degrade stability and often cause oscillation. With the compensation described the closed loop bandwidth will
be the reciprocal of 2
FB
.
Alternatively, at the expense of noise and offset, the amplifer can be stabilized by a resistor across the summing
junction such that the parallel combination of the input resistor and summing junction resistor is less than a twentieth
of the value of the feedback resistor. Note that this will increase noise and offset by to 20 times the RTI values, but
with 10 mV max offset and 13 nV/(Hz)
1/2
noise, performance will be acceptable for many applications.
As seen by the very small values of capacitance used in compensation for low gain, stray feedback capacitance
and/or summing junction capacitance can have a VERY large effect on performance. Therefore stray capacitance
must be minimized in the layout. The summing junction lead must be as short as possible, and ground plane must
be kept away from the summing junction lead.
7. SLEW RATE AND FULL POWER BANDWIDTH
In the PA107DP the slew rate is measured from the 25% point to the 75% point of a 180V
P-P
square wave. Slew rate
is measured with no load and with auxiliary supplies at a nominal 15 V and V
S
supplies at a maximum 100V.
Power bandwidth is defned as the highest frequency at which an unloaded amplifer can have an undistorted sine
wave at full power as its output. This frequency can be calculated as the slew rate divided by times the peak
to peak amplitude; which would be 4.7 MHz for the PA107DP. Unfortunately running full output at this frequency
causes internal dissipation of up to 107 W, well over the power limits for the PA107DP. Cutting the frequency to 2
MHz reduces internal dissipation to 34 W, acceptable with a good heatsink.
PA107DP
PA107DPU 479
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TYPICAL APPLICATION
IMPORTANT NOTICE
+V
SP
Piezo Drive
DAC
+15V +V
S
-15V -V
S
GND
IN
OUT
-V
AUX
-V
SP
+V
AUX
+V
S
-V
S
R
IN
PA107
R
F
PA119CE PA119CEA
480 PA119U
PA119CE, PA119CEA
FEATURES
VERY FAST SLEW RATE 900 V/s
POWER MOS TECHNOLOGY 4A peak rating
PROTECTED OUTPUT STAGE Thermal Shutoff
WIDE SUPPLY RANGE 15V TO 40V
APPLICATIONS
VIDEO DISTRIBUTION AND AMPLIFICATION
HIGH SPEED DEFLECTION CIRCUITS
POWER TRANSDUCERS UP TO 5 MHz
MODULATION OF RF POWER STAGES
POWER LED OR LASER DIODE EXCITATION

DESCRIPTION
The PA119 is a high voltage, high current operational ampli-
fer optimized to drive a variety of loads from DC through the
video frequency range. Excellent input accuracy is achieved
with a dual monolithic FET input transistor which is cascoded
by two high voltage transistors to provide outstanding common
mode characteristics. All internal current and voltage levels
are referenced to a zener diode biased on by a current source.
As a result, the PA119 exhibits superior DC and AC stability
over a wide supply and temperature range.
High speed and freedom from second breakdown is assured
by a complementary power MOS output stage. For optimum
linearity, especially at low levels, the power MOS transistors
are biased in a class A/B mode. Thermal shutoff provides
full protection against overheating and limits the heatsink
requirements to dissipate the internal power losses under
normal operating conditions. A built-in current limit of 0.5A
can be increased with the addition of two external resistors.
Transient inductive load kickback protection is provided by
two internal clamping diodes. External phase compensation
allows the user maximum fexibility in obtaining the optimum
slew rate and gain bandwidth product at all gain settings. A
capacitors, and silicon semiconductor chips to maximize reli-
ability, minimize size, and give top performance. Ultrasonically
bonded aluminum wires provide reliable interconnections at all
operating temperatures. The 8-pin TO-3 package is hermeti-
cally sealed and electrically isolated. The use of compress-
Considerations.
TOP
VIEW
1
2
3
4
5
6
7
8
V
+IN
IN
OUT
C
C
R
CL
PHASE COMPENSATION
C
C
330pF
22pF
2.2pF
none
GAIN
1
10
100
1000
+V
R
CL+

TYPICAL APPLICATION
This fast power driver utilizes the 900V/s slew rate of the
PA119 and provides a unique interface with a current output
DAC. By using the DACs internal 1K feedback resistor,
temperature drift errors are minimized, since the temperature
drift coefficients of the internal current source and the internal
feedback resistor of the DAC are closely matched. Gain of
V
OUT
to I
IN
is 6.5/mA. The DACs internal 1K resistor together
with the external 500 and 110 form a tee network in the
feedback path around the PA119. This effective resistance
equals 6.5K . Therefore the entire circuit can be modeled
as 6.5K feedback resistor from output to inverting input and
a 5mA current source into the inverting input of the PA119.
Now we see the familiar current to voltage conversion for a
DAC where V
OUT
= I
IN
x R
FEEDBACK
.
+40V
40V
32.5V
R
CL+
PA119
PA119 AS FAST POWER DRIVER
R
CL
5.6pF
Up to 4A
110
500
5mA
1K
DAC
TYPICAL
APPLICATION
8-pin TO-3
PACKAGE STYLE CE
3
6
8
5
4
1
Q3
Q5
Q4
D1
D2
Q16
Q13 Q12
Q1
Q7
Q19
Q17B
Q11
Q10
2
7
Q15
Q20
Q24
Q25
Q21
Q22
Q9
Q8
Q2
Q17A
Q23
Video Power Operational Amplifier
PA119CE PA119CEA
P r o d u c t
I n n o v a t i o n
F r o m
MAY 2009
APEX PA119UREVB
PA119CE PA119CEA
PA119U 481
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SPECIFICATIONS
SUPPLY VOLTAGE, +V
S
to V
S
80V
S

TEMPERATURE, pin solder 10 sec 300C
1
175C
TEMPERATURE, storage 65 to 150C
OPERATING TEMPERATURE RANGE, case 55 to 125C
PA119 PA119A
2
INPUT
C
= 25C .5 3 .35 .75 mV
C
= 25C to +85C 10 30 5 15 V/C
C
= 25C 10 * V/V
C
= 25C to +85C 20 * V/W
C
= 25C 10 200 5 50 pA
C
= 25C .01 * pA/V
C
= 25C 5 100 3 25 pA
C
= 25C 10
11
* M
INPUT CAPACITANCE T
C
= 25C 6 * pF
3
T
C
= 25C to +85C V
S
15 V
S
12 * * V
C
= 25C to +85C, V
CM
= 20V 70 104 * * dB
GAIN
C
= 25C, R
L
= 1K 111 * dB
C
= 25C, R
L
= 15 74 88 * * dB
C
= 25C, C
C
= 2.2pF 100 * MHz
POWER BANDWIDTH, A
V
= 100 T
C
= 25C, C
C
= 2.2pF 3.5 * MHz
POWER BANDWIDTH, A
V
= 1 T
C
= 25C, C
C
= 330pF 250 * kHz
OUTPUT
VOLTAGE SWING
3
T
C
= 25C, I
O
= 4A V
S
5 V
S
1.5 * * V
VOLTAGE SWING
3
T
C
= 25C to +85C, I
O
= 2A V
S
3 V
S
.75 * * V
VOLTAGE SWING
3
T
C
= 25C to +85C, I
O
= 78mA V
S
1 V
S
.5 * * V
C
= 25C, 2V step .3 * s
C
= 25C, 2V step 1.2 * s
SLEW RATE, A
V
= 100 T
C
= 25C, C
C
= 2.2pF 600 900 750 * V/s
SLEW RATE, A
V
= 10 T
C
= 25C, C
C
= 22pF 650 * V/s
POWER SUPPLY
VOLTAGE T
C
= 25C to +85C 15 35 40 * * * V
C
= 25C 100 120 * * mA
THERMAL
4
T
C
= 25C to +85C, F > 60Hz 1.46 1.64 * * C/W
C
= 25C to +85C, F < 60Hz 1.84 2.0 * * C/W
C
= 25C to +85C 30 * C/W
to achieve high MTTF.
3. +V
S
and V
S
S
is measured from +V
S
to V
S
.
CAUTION
PA119CE PA119CEA
482 PA119U
50 100
1.0
3.0
3.5
CURRENT LIMIT
2.0
.5 C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
25 25 50 75
2.5
1.5
CASE TEMPERATURE, T
C
(C)
0
0
125
R
C
L =
0
.2
7
W
W
R
CL
= 1.2
R
CL
=

10
COMMON MODE VOLTAGE
C
O
M
M
O
N

M
O
D
E

V
O
L
T
A
G
E
,

V
C
M

(
V
P
P
)
45
100 1K 10K 100K 1M
50
55
60
65
70
40
10M
FREQUENCY, F (Hz)
FREQUENCY, F (Hz)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V

(
V

)
O
POWER RESPONSE
P
P
21
30
41
58
15
1M 20M 100K200K 2M 4M 8M 600K
80
11
8
C
C

=

2
.
2
p
F
C
C

=

2
2
p
F
C
C

=

3
3
0
p
F
| +V
S
| + | V
S
| = 80V
R
L
= 15W
0
OUTPUT CURRENT, I
O
(A)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y

(
V
)
1 2 3 4 5
+V
V
100 100M
FREQUENCY, F (Hz)
20
0
60
O
P
E
N

L
O
O
P

G
A
I
N
,

A
O
L

(
d
B
)
20
40
80
100
1K 100K 10K 1M 10M
2
.
2
p
F 2
2
p
F
3
3
0
p
F
C
(pF)
SLEW RATE VS. COMP.
S
L
E
W

R
A
T
E
,

(
V
/
s
)
10 100 400 2 4 20 40 200
40
100
200
600
400
1000
800
6 60
80
R
L
= 15W
200
TIME, t (ns)
30
20
30
PULSE RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
10
20
50 0 50 100 150
10
0
250 300
R
L
= 15W
V
IN
= 2V
A
V
= 10
t
r
= 10ns
30 60 80
S
(V)
1.4
QUIESCENT CURRENT
1.2
40 50 70
.6
.8
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
X
)
1.0
1.6
1K 10M
FREQUENCY, F (Hz)
C
O
M
M
O
M

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)
40
80
120
10K 100K 1M
20
60
100
100M 1K
FREQUENCY, F (Hz)
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)
10K 100K 1M 100M
0
20
40
60
80
100
10M
10 100 10K 1M
FREQUENCY, F (Hz)
I
N
P
U
T

N
O
I
S
E

V
O
L
T
A
G
E
,

V
N

(
n
V
/

H
z
)
INPUT NOISE
1K
10
15
20
30
7
5
3
100K
0 25 50 75 100 125
CASE TEMPERATURE, T
C
(C)
10
40
60
80
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
50
150
70
30
20
0
1.5
1.0
0.5
PA119CE PA119CEA
PA119U 483
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A
and the wire bonds.
The SOA curves combine the effect of these limits and allow
for internal thermal delays. For a given application, the direc-
tion and magnitude of the output current should be calculated
or measured and checked against the SOA curves. This is
simple for resistive loads but more complex for reactive and
EMF generating loads. The following guidelines may save
extensive analytical efforts:
1. Capacitive and inductive loads up to the following maximums
are safe:

V
S

40V .1F 11mH
30V 500F 24mH
20V 2500F 75mH
15V 100mH
2. Safe short circuit combinations of voltage and current are
limited to a power level of 100W.
SUPPLY CURRENT
The PA119 features a class A/B driver stage to charge and
discharge gate capacitance of Q7 and Q19. As these currents
approach 0.5A, the savings of quiescent current over that of a
class A driver stage is considerable. However, supply current
drawn by the PA119, even with no load, varies with slew rate
of the output signal as shown below.
OUTPUT LEADS
Keep the output leads as short as possible. In the video
frequency range, even a few inches of wire have signifcant
inductances, raising the interconnection impedance and limit-
ing the output current slew rate. Furthermore, the skin effect
increases the resistance of heavy wires at high frequencies.
Multistrand Litz Wire is recommended to carry large video
currents with low losses.
GENERAL

CURRENT LIMIT
Q2 (and Q25) limit output current by turning on and remov-
ing gate drive when voltage on pin 2 (pin 7) exceeds .65V dif-
ferential from the positive (negative) supply rail. With internal
resistors equal to 1.2, current limits are approximately 0.5A
with no external current limit resistors. With the addition of
external resistors current limit will be:
To determine values of external current limit resistors:
PHASE COMPENSATION
At low gain settings, an external compensation capacitor is
required to insure stability. In addition to the resistive feedback
network, roll off or integrating capacitors must also be consid-
ered when determining gain settings. The capacitance values
listed in the external connection diagram, along with good
high frequency layout practice, will insure stability. Interpolate
values for intermediate gain settings.

SUPPLY CURRENT
400
300
200
100
0
30K 100K 300K 1M 3M 10M
FREQUENCY, F (Hz)
S
U
P
P
L
Y

C
U
R
R
E
N
T
,

I
S

(
m
A
)
V
OUT
= 60V
P-P
SINE
R
L
= 500
I
LIM
= +.54A
.65V
R
CL
R
CL
=
.65V
I
CL
.54A
SOA
1
10
INTERNAL VOLTAGE DROP SUPPLY TO OUTPUT, V
S
-V
O
(V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

o
r

-
V
S
2
4
3
T
C
=25C
10 20 30 40 50 80
5
100
t

=

1
0
0
m
s
t

=

3
0
0
m
s
S
T
E
A
D
Y

S
T
A
T
E
PA119CE PA119CEA
484 PA119U
THERMAL SHUTDOWN
allows the heatsink selection to be based on normal operating
(areas outside of the steady state boundary). It is designed to
power dissipation within the amplifer. If the conditions that
power stresses, destroy signal integrity, and reduce the reli-
ability of the device.
STABILITY
Due to its large bandwidth, the PA119 is more likely to
oscillate than lower bandwidth power operational amplifers.
To prevent oscillations a reasonable phrase margin must be
maintained by:
1. Selection of the proper phase compensation capacitor. Use
the values given in the table under external connections and
interpolate if necessary. The phase margin can be increased
by using a larger capacitor at the expense of slew rate.
Total physical length (pins of the PA119, capacitor leads
plus printed circuit traces) should be limited to a maximum
of 3.5 inches.
2. Keep the external sumpoint stray capacitance to ground
load resistances can be used with increased phase com-
pensation and/or by bypassing the feedback resistor.
3. Connect the case to any AC ground potential.
IMPORTANT NOTICE
PA162
PA162U 485
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PA162
FEATURES
LOW COST
HIGH OUTPUT CURRENT - 1.5A PER AMPLIFIER
WIDE COMMON MODE RANGE Includes negative
supply
WIDE SUPPLY VOLTAGE RANGE Single supply:
5V to 40V Split supplies: 2.5V to 20V
VERY LOW DISTORTION
APPLICATIONS
Stereo - 11.3W RMS per amplifer
Bridge - 22.6W RMS per two amplifers
Two Bridges - 45.2W RMS per package
3 PHASE MOTOR DRIVER
3 Channels - 33.9W RMS per package
5V - Peripherals
12V - Automotive
28V - Avionic
PACKAGING OPTIONS
20-Pin PSOP, JEDEC MO-166-AB (PA162DK)
DESCRIPTION
The amplifer design is a dual power op amp on a
single monolithic die. The quad output PA162 com-
bines two dual op amp die in a single PSOP pack-
age. This approach provides a cost-effective solu-
tion to applications where multiple amplifers are
required or a bridge confguration is needed. Four
independent amplifers coupled with low quiescent
current and very low THD makes this an ideal low-
distortion 4-channel audio amplifer for applications
such as laptops and computer speakers.
The quad output PA162DK is available in a surface
mount 20-pin PSOP, JEDEC MO-166-AB package.
Built-in thermal shutdown allows the devices to self-
protect against thermal overloads. Care must be ex-
ercised to observe the Safe Operating Area (SOA)
curve and proper heatsinking will ensure maximum
reliability.
The wide common mode input range includes the
negative rail, facilitating single supply applications.
This makes it possible to have a ground-based input
driving a single supply amplifer with ground acting
as the second or bottom supply of the amplifer.
OUT
+Vs
-IN +IN
-Vs
I BIAS
MONITOR
THERMAL
PROTECT
FIGURE 1. Equivalent schematic (one channel)
JUL 2009
APEX - PA162UREVB
PA162
486 PA162U
2,3
Min Typ Max Units
INPUT
OFFSET VOLTAGE, vs. temperature Full temp range 20 V/C
COMMON MODE RANGE Full temp range -Vs +Vs V
POWER SUPPLY REJECTION Full temp range 60 90 dB
OUT
= 500mA, = 1kHz 50 68 dB
S
= 100, = 1 to 100kHz 22 nV/Hz
GAIN
OPEN LOOP GAIN V
O
= 10V, R
L
= 2.0K 89 100 dB
GAIN BANDWIDTH PRODUCT = 100kHz, C
L
= 100pF, R
L
= 2.0K 0.9 1.4 MHz
PHASE MARGIN Full temp range 65 C
POWER BANDWIDTH V
O
(P-P) = 28V 13.6 kHz
OUTPUT
CURRENT, peak 1.5 A
SLEW RATE 1.0 1.4 V/S
O
= 100mA |Vs| -1.1 |Vs| -0.8 V
O
= 1A |Vs| -1.8 |Vs| -1.4 V
V
= 1, R
L
= 50,
V
O
= .5VRMS, = 1kHz
.02 %
SUPPLY VOLTAGE, total 5 40 V
OUTPUT CURRENT SOA
POWER DISSIPATION, internal (1 amplifer) 15 W
POWER DISSIPATION, internal (2 amplifers)
5
24 W
5
36 W
5
45 W
INPUT VOLTAGE, differential -Vs +Vs
INPUT VOLTAGE, common mode +Vs -Vs-.5V
2
150 C
TEMPERATURE, pin solder - 10 secs max. 220 C
TEMP RANGE STORAGE -55 150 C
OPERATING TEMP RANGE, case
2
-40 125 C
SPECIFICATIONS (PER AMPLIFIER)
PA162
PA162U 487
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
2,3
Min Typ Max Units
POWER SUPPLY
VOLTAGE, Vss
4
5 30 40 V
CURRENT, quiescent +Vs (A/B) 8 10 mA
CURRENT, quiescent +Vs (C/D) 8 10 mA
THERMAL
DC, 1 amplifer 7.16 7.87 C/W
DC, 2 amplifers
5
4.69 5.16 C/W
DC, 3 amplifers
5
3.08 3.39 C/W
DC, 4 amplifers
5
2.51 2.77 C/W
AC, 1 amplifer 5.37 5.90 C/W
AC, 2 amplifers
5
3.52 3.87 C/W
AC, 3 amplifers
5
2.31 2.54 C/W
AC, 4 amplifers
5
1.89 2.07 C/W
7
25 C/W
NOTES:
C
= 25C).
S
= 15V, T
C
=25C.
4. +V
S
and -V
S
denote the positive and negative rail respectively. V
SS
denotes total rail-to-rail supply.
5. Rating applies when power dissipation is equal in each of the amplifers. Power and thermal ratings
are based on two separate dual monolithic power op-amps on one integrated copper heatslug.
Amplifers A and B are combined on one monolithic die while amplifers C and D are on the other.
6. If -V
S
is disconnected before +V
S
, a diode between -V
S
and ground is recommended to avoid dam-
age.
20-pin PSOP
PACKAGE STYLE DK
NC
-IN(A)
+IN(A)
+IN(B)
-IN(B)
-IN(C)
+IN(C)
+IN(D)
-IN(D)
NC
-VS
OUT(A)
+VS(A/B)
OUT(B)
-VS
-VS
OUT(C)
+VS(C/D)
OUT(D)
-VS
A
+
-
1

10
20

11
B
+
-
-
+
+
-
C
D
FIGURE 2. EXTERNAL CONNECTIONS.
PA162
488 PA162U
-40 0 40 80 120
45
55
65
75
CASE TEMPERATURE, T
C
(C)
A
V
E
R
A
G
E

B
I
A
S

C
U
R
R
E
N
T
,

I
B

(
m
A
)
BIAS CURRENT
-40 0 40 80 120
0
1
2
3
CASE TEMPERATURE, T
C
(C)
A
V
E
R
A
G
E

O
F
F
S
E
T

V
O
L
T
A
G
E
,

V
O
S

(
m
V
)
VOS
00 04 08 12 16
35
45
55
65
L
(nF)
P
H
A
S
E

M
A
R
G
I
N
,

)
20
25
0
-20
20
40
60
1 10 100 1K 10K
90
100
110
120
130
FREQUENCY, (KHz)
G
A
I
N
,

A

(
d
B
)
P
H
A
S
E
,

)
PULSE RESPONSE
TIME, t (s)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
0 10 20 30 40 50
-4
8
4
0
-8
-2
10
6
2
-6
-10
60 70
+V
S
= +15V
A
V
= +1
V
IN
= 10Vp
-V
S
= -15V
R
L
= 20
f
IN
= 20kHz
PULSE RESPONSE
TIME, t (s)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
O

(
V
)
0 200 400 600 800 1000
0
1200 1400
+V
S
= +15V
A
V
= +1
V
IN
= 10Vp
-V
S
= -15V
f
IN
= 1kHz
QUIESCENT CURRENT
2 4 6 8 10
AVERAGE QUIESCENT CURRENT, I
Q
(mA)
T
O
T
A
L

S
U
P
P
L
Y

V
O
L
T
A
G
E
,

V
S

(
V
)
20
16
12
0
4
8
-80
-40
0
40
80
120
C
A
S
E

T
E
M
P
E
R
A
T
U
R
E
,

T
C

(
C
)
OUTPUT CURRENT, I
O
(A)
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

(
V
)
0.1 0.2 0.3 0.4 0.5 0.6
0.6
1.8
1.4
1
0.2
0.8
2
1.6
1.2
0.4
0
0.7 1.0 0.9 0.8
-4
8
4
-8
-2
10
6
2
-6
-10
TYPICAL APPLICATION
R1 and R2 set up Amplifer A as non-inverting. Ampli-
fer B is set up as a unity gain inverter driven from the
output of Amplifer A. Note that Amplifer B inverts the
signals about the reference node, which is set at mid-
supply by R5 and R6. When the command input is
midrange, so is the output of Amplifer A. Since this is
also equivalent to the reference node voltage, the out-
put of Amplifer B is the same resulting in 0V across
the motor. Inputs more positive than 5V result in motor
current fow from left to right (see Figure 3). Inputs less
than 5V drive the motor in the opposite direction.
INPUT
0-10V
A
M
B
R2 R3
R4
R5
R6
R1
1/4 PA162 1/4 PA162
+28V
+
_
+
_
FIGURE 3. BI-DIRECTIONAL SPEED CONTROL
FROM A SINGLE SUPPLY.
PA162
PA162U 489
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
TYPICAL APPLICATION (CONT)
The amplifers are especially well-suited for applications
such as this. The extended common mode range allows
command inputs as low as 0V. The output swing lets
it drive within 2V of the supply at an output of 1A. This
means that a command input that ranges from 0 to 10V
will drive a 24V motor from full scale CCW to full scale
CW at 1A.
-Vs (pins 11, 15, 16 and 20) must be tied to the heatslug
externally on the PCB. To ease metal routing on the PCB,
run a direct trace from the -Vs pin to the center heat slug.
The PA162 can be used in a three amplifer confguration
for a three phase inverter or motor as shown in Figure 4.
GENERAL
siderations" which covers stability, supplies, heatsinking,
mounting, SOA interpretation, and specifcation interpre-
tation. Visit www.cirrus.com for design tools that help automate tasks such as calculations for stability, internal
power dissipation, heatsink selection; Apex Precision Power's complete Application Notes library; Technical Semi-
nar Workbook; and Evaluation Kits.
All monolithic power op amps use output stage topologies that present special sta-
bility problems. This is primarily due to non-complementary (both devices are NPN)
output stages with a mismatch in gain and phase response for different polarities of
output current. It is diffcult for the op amp manufacturer to optimize compensation
for all operating conditions. For applications with load current exceeding 300mA,
oscillation may appear. The oscillation may occur only with the output voltage swing
at the negative or positive half cycle. Under most operating and load conditions
acceptable stability can be achieved by providing a series RC snubber network
connected from the output to ground (see Figure 5). The recommended component
values of the of the network are, R
SN
= 10 and C
SN
= 0.01F. Please refer to Ap-
plication Note 1 for further details.
The SOA curves combine the effect of all limits for this
power op amp. For a given application, the direction and
magnitude of the output current should be calculated or
measured and checked against the SOA curves. This is
simple for resistive loads but more complex for reactive
and EMF generating loads. The following guidelines may
save extensive analytical efforts.
S
- V
O
(V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

-
V
S
,

(
A
)
SOA
4 AMPLIFIERS LOADED
1 AMPLIFIER LOADED
2 AMPLIFIERS LOADED
3 AMPLIFIERS LOADED
DC, T
C
=25C
DC, T
C
=85C
1 50 10
0.1
10
1
N
o
S
PA162
Quad
Using 3 amplifiers from PA162
as 3 phase motor driver.
FIGURE 4. 3 Phase Inverter
+
C
SN
0.01F
R
SN
10
FIGURE 5. R-C Snubber
PA162
490 PA162U
The PA162DK has a large exposed integrated copper heat-
slug to which the monolithic is directly attached. The solder
connection of the heatslug to a minimum of 1 square inch
foil area of the printed circuit board will result in thermal per-
formance of 25C/W junction to air rating of the PA162DK.
Solder connection to an area of 1 to 2 square inches of foil
is required for minimal power applications.
Where the PA162DK is used in higher power applications, it
is necessary to use surface mount techniques of heatsink-
ing. Surface mount techniques include the use of a surface
mount fan in combination with a surface mount heatsink on
the backside of the FR4/ PC board with through hole ther-
mal vias. Other highly thermal conductive substrate board
materials are available for maximum heat sinking.
The Power Derating graph assumes that the power dissipa-
tion is equal in each of the amplifers. Power and thermal
ratings are based on two separate dual monolithic power op amps on one integrated copper heat slug. Amps A and
B are combined on one monolithic die while amps C and D are combined on the other. This multi chip confgura-
tion provides superior thermal performance by isolating each of the dual amplifers. When loading either of the dual
amplifers it is possible to achieve better thermal performance by loading any combination of amplifers (A or B) +
(C or D).
1. Always use a heat sink. Even unloaded the PA162DK can dissipate up to .8 watts.
2. Avoid bending the leads. Such action can lead to internal damage.
POWER DERATING
J
(C)
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
0 25 50 75 100 125
20
50
10
40
0
30
(A
) A
M
P
LIF
IE
R
LO
A
D
E
D
(A
+
B
) A
M
P
L
IF
IE
R
S
L
O
A
D
E
D
(
A
+
B
+
C
+
D
)

A
M
P
L
I
F
I
E
R
S

L
O
A
D
E
D
(
A
+
B
+
C
)
A
M
P
L
IF
IE
R
S
L
O
A
D
E
D
IMPORTANT NOTICE
PA240
PA240U 491
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PA240
FEATURES
RoHS COMPLIANT
MONOLITHIC MOS TECHNOLOGY
LOW COST
HIGH VOLTAGE OPERATION350V
LOW QUIESCENT CURRENT TYP.2.2mA
NO SECOND BREAKDOWN
HIGH OUTPUT CURRENT120 mA PEAK
APPLICATIONS
TELEPHONE RING GENERATOR
PIEZO ELECTRIC POSITIONING
DEFORMABLE MIRROR FOCUSING
PACKAGING OPTIONS
7 TO-220 with staggered Lead Form (PA240CX)
7 DDPAK Surface Mount Package (PA240CC)
DESCRIPTION
The PA240 is a high voltage monolithic MOSFET operational
amplifer achieving performance features previously found only
in hybrid designs while increasing reliability. Inputs are protected
from excessive common mode and differential mode voltages.
The safe operating area (SOA) has no second breakdown
limitations. External compensation provides the user fexibility
in choosing optimum gain and bandwidth for the application.
The PA240 is packaged in two standard package designs.
The surface mount version of the PA240, the PA240CC,
is an industry standard non-hermetic plastic 7-pin DDPAK.
The through hole version of the PA240, the PA240CX, is an
industry standard non-hermetic plastic 7-pin TO-220 package.
The PA240CX is a staggered lead formed option that offers
industry standard 100 mil spacing. This allows for easier PC
board layout. (Please refer to package drawings for outline
dimensions.)
A1
PA240
A2
PA240
20R
PIEZO
TRANSDUCER
20R
R
N
20R
C
N
R
V
IN
175
+175
175
+175
10pF 10pF
LOW COST 660V p-p
PIEZO DRIVE
C
C
C
C
PA240CC
PA240CX
-
I
N
+
I
N
+
V
s
-
V
s
O
U
T
C
O
M
P

(
C
c
)
C
O
M
P

(
C
c
)
A A
-
I
N
+
I
N
+
V
s
-
V
s
O
U
T
C
O
M
P

(
C
c
)
C
O
M
P

(
C
c
)
For CC values, see graph on page 3.
Note: CC must be rated for full supply voltage.
DDPAK
PKG. STYLE CC
TO-220
STAGGERED LEADS
PKG. STYLE CX
IN
+V
S
V
S
+IN
D2 D3 D4 D5
Q5 Q4
1
2
4
5
3
Q1
Q11
Q12
D1
Q2
Q6
Q8
Q13
SUB
Q14
Q10
Q3
I
OUT
COMP
COMP
6
7
High voltage considerations should be taken when designing
board layouts for the PA240. The PA240 may require a derate in
supply voltage depending on the spacing used for board layout.
The 15-mil and 14-mil minimum spacing of the 7 TO-220 and
7 DDPAK respectively is adequate to standoff the 350V rating
of the PA240. However, a supply voltage derate to 250V is
required if the spacing of circuit board artwork is less than 11
mils. In cases where the PA240 is used to its maximum voltage
rating, the PA240CX is recommended given that the staggered
lead form allows for 100-mil standard spacing.
The metal tabs of both the PA240CC and PA240CX pack-
ages are directly tied to -Vs.
TYPICAL APPLICATION
Reference Application Notes 3, 20 and 25
MAY 2009
APEX PA240UREVF
PA240
492 PA240U
1
MIN TYP MAX UNITS
INPUT
OFFSET VOLTAGE, vs. temperature
3
25C to 85C 100 250 V/C
3
-25C to 25C 270 500 V/C
OFFSET VOLTAGE, vs supply 3 V/V
OFFSET VOLTAGE, vs time 70 130 V/kh
BIAS CURRENT, vs supply 2 pA/V
11

COMMON MODE, voltage range +V
S
14 V
COMMON MODE, voltage range -V
S
+12 V
CM
= 90V DC 84 94 dB
NOISE, broad band 10kHz BW, R
S
= 1K 50 V RMS
NOISE, low frequency 1-10 Hz 125 V p-p
GAIN
OPEN LOOP at 15Hz R
L
=

5K 90 96 dB
BANDWIDTH, gain bandwidth product 3 MHz
POWER BANDWIDTH 280V p-p 30 kHz
OUTPUT
VOLTAGE SWING I
O
= 40mA V
S
12 V
S
10 V
CURRENT, peak
3
120 mA
SETTLING TIME to .1% 10V step, A
V
= 10 2 s
SLEW RATE C
C
= 3.3pF 30 V/s
RESISTANCE
4
, 1mA R
CL
=

0 150
RESISTANCE
4
, 40 mA R
CL
= 0 5
POWER SUPPLY
THERMAL
RESISTANCE, AC junction to case F > 60Hz 5.9 6.85 C/W
RESISTANCE, DC junction to case F < 60Hz 7.7 8.9 C/W
RESISTANCE, junction to air (CX) Full temperature range 60 C/W
RESISTANCE, junction to air (CC)
5
TEMPERATURE RANGE, case Meets full range specifcations 25 25 +85 C
ABSOLUTE MAXIMUM RATINGS SUPPLY VOLTAGE, +V
S
to V
S
350V
OUTPUT CURRENT, peak
3
120 mA
C
= 25C 14W
INPUT VOLTAGE, differential 16 V
S
2
150C
TEMPERATURE RANGE, powered (case) 40 to +125C
SPECIFICATIONS
NOTES: 1. Unless otherwise noted T
C
= 25C, C
C
= 6.8pF. DC input specifcations are value given. Power supply voltage is typical
rating.
to achieve high MTTF. For guidance, refer to heatsink data sheet.
4. Since the PA240 has no current limit, load impedance must be large enough to limit output current to 120mA.
5. Heat tab attached to 3/32" FR-4 board with 2oz. copper. Topside copper area (heat tab directly attached) = 1000 sq. mm,
backside copper area = 2500 sq. mm, board area = 2500 sq. mm.
PA240
CAUTION
PA240
PA240U 493
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
0
2
4
6
8
10
12
OUTPUT CURRENT, I
O
(mA)
V
D
R
O
P

F
R
O
M

V
S
,

(
V
)
V
DROP
- @85C
V
DROP
+ @85C
V
DROP
- @25C
V
DROP
+ @25C
0 20 40 60 80 100 120
FREQUENCY, F (Hz)
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)

10 100 1K 10K 100K
40
50
60
70
80
90
100
POSITIVE
NEGATIVE
100 1K
FREQUENCY, F (Hz)
0
80
120
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)

20
60
100
10 10K 100K
40
QUIESCENT CURRENT
TOTAL SUPPLY VOLTAGE, (V)
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T

(
%
)

115
105
95
85
120
110
100
90
80
100 150 200 250 300 350
I
Q
(-25C)
I
Q
(25C
)
I
Q
(85C
)
COMPENSATION CAPACITANCE, C
C
(pF)
S
L
E
W

R
A
T
E
,

(
V
/
s
)
SLEW RATE
10 20 30 40 50 0
0
15
25
35
60 70 100 10K
FREQUENCY, F (Hz)
0.001
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

(
%
)

10
1K 100K
0.1
0.01
1
30V
P-P
60V
P-P
180V
P-P
A
V
= 20
C
C
= 15pF
R
L
= 2K
FREQUENCY, F (Hz)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

(
V
O
U
T
)
(
p
-
p
)

100K 1M 10K
10
100
1000
POWER RESPONSE
.75pF
6.8pF
15pF
33pF
68pF
1M 10M 100K 10K
-170
-160
-150
-140
-130
-120
-180
PHASE RESPONSE
FREQUENCY, F (Hz)
P
H
A
S
E
,

)

68pF
15pF
6.8pF
.75pF
-110
-100
-90
10K 1K 100 10
68pF
15pF
6.8pF
.75pF
100
80
60
40
20
0
-20
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)

FREQUENCY, F (Hz)
10M 1M 100K
T
C
= 55C
T
C
= 85C
T
C
= 25C
T
C
= 125C
100
10
1
0.1
C
O
M
P
E
N
S
A
T
I
O
N
,

p
F

100 10 1
GAIN
GAIN AND COMPENSATION
0 25 50 75 100 125
TEMPERATURE, T (C)
0
2
4
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)

10
6
8
16
12
14
PA240
494 PA240U
SAFE OPERATING AREA
The MOSFET output stage of the PA240 is not limited by
However there are still three distinct limitations:
1. Voltage withstand capability of the transistors.
2. Current handling capability of the die metallization.
3. Temperature of the output MOSFETS.
These limitations can be seen in the SOA (see Safe Operat-
ing Area graphs). Note that each pulse capability line shows
a constant power level (unlike second breakdown limitations
where power varies with voltage stress). These lines are shown
for a case temperature of 25C. Pulse stress levels for other
case temperatures can be calculated in the same manner as
DC power levels at different temperatures. The output stage is
protected against transient fyback by the parasitic diodes of
the output stage MOSFET structure. However, for protection
against sustained high energy fyback external fast-recovery
diodes must be used.
HEATSINKING
The PA240CC 7-pin DDPAK surface mountable package
has a large exposed integrated copper heatslug to which the
monolithic amplifer is directly attached. The PA240CC requires
surface mount techniques of heatsinking. A solder connection
to a copper foil area as defned in Note 5 of Page 2 is recom-
mended for circuit board layouts. This may be adequate heat-
sinking but the large number of variables suggests temperature
measurements to be made on the top of the package. Do not
allow the temperature to exceed 85C.
GENERAL
PHASE COMPENSATION
Open loop gain and phase shift both increase with increas-
ing temperature. The PHASE COMPENSATION typical graph
shows closed loop gain and phase compensation capacitor
value relationships for four case temperatures. The curves are
based on achieving a phase margin of 50. Calculate the high-
est case temperature for the application (maximum ambient
temperature and highest internal power dissipation) before
choosing the compensation. Keep in mind that when working
with small values of compensation, parasitics may play a large
role in performance of the fnished circuit. The compensation
capacitor must be rated for at least the total voltage applied
to the amplifer and should be a temperature stable type such
as NPO or COG.
OTHER STABILITY CONCERNS
There are two important concepts about closed loop gain
when choosing compensation. They stem from the fact that
while "gain" is the most commonly used term, (the feedback
factor) is really what counts when designing for stability.
1. Gain must be calculated as a non-inverting circuit (equal
input and feedback resistors can provide a signal gain of
-1, but for calculating offset errors, noise, and stability, this
is a gain of 2).
2. Including a feedback capacitor changes the feedback factor
or gain of the circuit. Consider Rin=4.7k, Rf=47k for a gain
of 11. Compensation of 4.7 to 6.8pF would be reasonable.
Adding 33pF parallel to the 47k rolls off the circuit at 103kHz,
and at 2MHz has reduced gain from 11 to roughly 1.5 and
the circuit is likely to oscillate.
As a general rule the DC summing junction impedance
(parallel combination of the feedback resistor and all input
resistors) should be limited to 5k ohms or less. The amplifer
input capacitance of about 6pF, plus capacitance of connecting
traces or wires and (if used) a socket will cause undesirable
circuit performance and even oscillation if these resistances
are too high. In circuits requiring high resistances, measure or
estimate the total sum point capacitance, multiply by Rin/Rf, and
parallel Rf with this value. Capacitors included for this purpose
are usually in the single digit pF range. This technique results
in equal feedback factor calculations for AC and DC cases. It
does not produce a roll off, but merely keeps constant over
a wide frequency range. Paragraph 6 of Application Note 19
details suitable stability tests for the fnished circuit.
10 20 30 50 100 200 300 500
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S
,

(
m
A
)
0.001
0.002
0.003
0.005
0.01
0.02
0.03
0.05
0.1
0.2
SOA
200mS 0.3
0.5
300mS
S
- V
O
, (V)
DC, T
C
= 25C
DC, T
C
= 85C
1K
1.0
PA240
PA240U 495
G
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A
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B
A
FIGURE 1
up to 16V, in some applications additional external protection
may be needed. Differential inputs exceeding 16V will be clipped
by the protection circuitry. However, if more than a few milliamps
of current is available from the overload source, the protection
circuitry could be destroyed. For differential sources above
16V, adding series resistance limiting input current to 1mA will
prevent damage. Alternatively, 1N4148 signal diodes connected
anti-parallel across the input pins is usually sufficient. In more
+Vs
-Vs
OUT
+Vs
-Vs
Z1
Z2
-IN
+IN
Q1
Q2
demanding applications where bias current is important, diode
connected JFETs such as 2N4416 will be required. See Q1
and Q2 in Figure 1. In either case the differential input voltage
the maximum power bandwidth.
In the case of inverting circuits where the +IN pin is grounded,
the diodes mentioned above will also afford protection from
excessive common mode voltage. In the case of non-invert-
ing circuits, clamp diodes from each input to each supply will
provide protection. Note that these diodes will have substantial
reverse bias voltage under normal operation and diode leak-
age will produce errors.
Some applications will also need over-voltage protection
devices connected to the power supply rails. Unidirectional
zener diode transient suppressors are recommended. The
zeners clamp transients to voltages within the power supply
rating and also clamp power supply reversals to ground.
Whether the zeners are used or not the system power supply
should be evaluated for transient performance including power-
on overshoot and power-off polarity reversals as well as line
regulation. See Z1 and Z2 in Figure 1.
APPLICATION REFERENCES:
lowing Application Notes:
AN01: General Operating Considerations
AN03: Bridge Circuit Drives
AN25: Driving Capacitive Loads
AN38: Loop Stability with Reactive Loads
IMPORTANT NOTICE
PA241
496 PA241U
PA241
FEATURES
RoHS COMPLIANT
LOW COST
NO SECOND BREAKDOWN
HIGH OUTPUT CURRENT120mA PEAK
AVAILABLE IN DIE FORMCPA241
APPLICATIONS
BIOCHEMISTRY STIMULATORS
COMPUTER TO VACUUM TUBE INTERFACE
DESCRIPTION
The PA241 is a high voltage monolithic MOSFET operational
amplifer which achieves performance features previously
found only in hybrid designs while increasing reliability. Inputs
are protected from excessive common mode and differential
mode voltages. The safe operating area (SOA) has no second
breakdown limitation and can be observed with all type loads
by choosing an appropriate current limiting resistor. External
compensation provides the user fexibility in choosing optimum
gain and bandwidth for the application.
The PA241CE is packaged in a hermetically sealed 8-pin
TO-3 package. The metal case of the PA241CE is isolated in
excess of full supply voltage.
The PA241DF is packaged in a 24 pin PSOP (JEDEC MO-
166) package. The metal heat slug of the PA241DF is isolated
in excess of full supply voltage.
The PA241DW is packaged in Apex Precision Powers her-
metic ceramic SIP package. The alumina ceramic isolates the
die in excess of full supply voltage.
20R
PIEZO
TRANSDUCER
20R
Rn
20R
Cn
R
V IN
175
+175
175
+175
R
CL
R
CL
47 47
10pF
10pF
A1
PA241
A2
PA241
LOW COST 660V p-p
PIEZO DRIVE
Two PA241 amplifers operated as a bridge driver for a piezo
transducer provides a low cost 660 volt total drive capability.
The R
N
C
N
network serves to raise the apparent gain of A2 at
high frequencies. If R
N
is set equal to R the amplifers can be
compensated identically and will have matching bandwidths.
R
CL
1 4 5 6 7 3 2 8 9 10
C
C
+IN -IN
NC NC -V
S
+V
S
I
LIM
C
C
2 C
C
1 OUT
PA241DW
R
CL
TOP VIEW
1
2
3
4
5
6
7
8
OUT
I
LIM
V
S
+V
S
C
C
1
IN
+IN
C
C
2
C
C
NOTE: PA241CE Recommended mounting torque is 4-7
inlbs (.45 -.79 Nm)
CAUTION: The use of compressible, thermally conductive
insulators may void warranty.
PA241CE
8-PIN TO-3 24-PIN PSOP 10-PIN SIP
PACKAGE STYLE CE PACKAGE STYLE DF PACKAGE STYLE DW
ILIM
OUT
-IN
+IN
+VS
-VS
CC2
CC1
TYPICAL APPLICATION
Ref: APPLICATION NOTE 20: "Bridge Mode Operation of Power Amplifers"
C
C R
CL
NC
NC
NC
NC
-IN
NC
+IN
NC
NC
NC
NC
-VS
NC
NC
NC
OUT
NC
COMP
NC
COMP
NC
ILIM
NC
+VS
24 1
+
-
PA241DF
For CC values, see graph on page 4.
Note: CC must be rated for full supply
voltage.
MAY 2009
APEX PA241UREVH
PA241
PA241U 497
G
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B
A
G
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E
D
C
B
A
PA241CE PA241DF
PA241CEA PA241DFA
SUPPLY VOLTAGE, +V
S
to V
S
350V 350V
OUTPUT CURRENT, continuous within SOA 60 mA 60 mA
OUTPUT CURRENT, peak 120 mA 120 mA
C
= 25C 12W 12W
INPUT VOLTAGE, differential 16 V 16 V
S
V
S
TEMPERATURE, pin solder 10 sec 300C 220C
2
150C 150C
TEMPERATURE, storage 65 to +150C 65 to +150C
TEMPERATURE RANGE, powered (case) 40 to +125C 40 to +125C
CAUTION The PA241 is constructed from MOSFET transistors. ESD handling procedures must be observed.
PA241CE, PA241DF PA241CEA
1
INPUT
3
25 to 85C 100 250 * * V/C
3
-25 to 25C 270 500 * * V/C
OFFSET VOLTAGE, vs supply 3 * V/V
OFFSET VOLTAGE, vs time 70 130 * * V/kh
6
5/50 50/200 * * pA
BIAS CURRENT, vs supply 0.2/2 * pA/V
6
2.5/50 50/200 * * pA
11
*
S
14 * V
S
+12 * V
CM
= 90V DC 84 94 * * dB
S
= 1K 50 * V RMS
NOISE, low frequency 1-10 Hz 125 * V p-p
GAIN
OPEN LOOP at 15Hz R
L
=

5K 90 96 * * dB
BANDWIDTH, gain bandwidth product 3 * MHz
POWER BANDWIDTH 280V p-p 30 * kHz
OUTPUT
VOLTAGE SWING I
O
= 40mA V
S
12 V
S
10 V
S
10 V
S
8.5 V
CURRENT, peak
4
120 * mA
V
= 10 2 * s
SLEW RATE C
C
= 3.3pF 30 * V/s
RESISTANCE
5
, 1mA R
CL
=

0 150 *
RESISTANCE
5
, 40 mA R
CL
= 0 5 *
POWER SUPPLY
VOLTAGE 50 150 175 * * * V
CURRENT, quiescent 2.2 2.5 * 2.3 mA
THERMAL
PA241CE RESISTANCE, AC junction to case F > 60Hz 5.4 6.5 * * C/W
PA241DF RESISTANCE, AC junction to case F > 60Hz 6 7 * * C/W
PA241CE RESISTANCE, DC junction to case F < 60Hz 9 10.4 * * C/W
PA241DF RESISTANCE, DC junction to case F < 60Hz 9 11 * * C/W
PA241CE RESISTANCE, junction to air Full temperature range 30 * C/W
PA241DF RESISTANCE, junction to air
7
TEMPERATURE RANGE, case Meets full range spec's 25 +85 * * C
SPECIFICATIONS
NOTES: * "A" specifcation is the same as the non "A" specifcation.
1. Unless otherwise noted T
C
= 25C, C
C
rating.
3. Sample tested by wafer to 95%.
5. The selected value of R
CL
must be added to the values given for total output resistance.
6. Specifcations separated by / indicate values for the PA241CE and PA241DF respectively.
7. Rating applies with solder connection of heatslug to a minimum 1 square inch foil area of the printed circuit board.
PA241
498 PA241U
PA241DW
PA241DWA
SUPPLY VOLTAGE, +V
S
to V
S
350V
OUTPUT CURRENT, peak 120 mA
C
= 25C 9W
S
2
150C
PA241DW PA241DWA
1
INPUT
3
25 to 85C 100 250 * * V/C
3
-25 to 25C 270 500 * * V/C
OFFSET VOLTAGE, vs supply 3 * V/V
OFFSET VOLTAGE, vs time 70 130 * V/kh
BIAS CURRENT, vs supply 15 50 * * pA/V
11
*
S
14 * V
S
+12 * V
CM
= 90V DC 84 94 * * dB
S
= 1K 50 * V RMS
NOISE, low frequency 1-10 Hz 125 * V p-p
GAIN
OPEN LOOP at 15Hz R
L
=

5K 90 96 * * dB
BANDWIDTH, gain bandwidth product 3 * MHz
POWER BANDWIDTH 280V p-p 30 * kHz
OUTPUT
VOLTAGE SWING I
O
= 40mA V
S
12 V
S
10 V
S
10 V
S
8.5 V
CURRENT, peak
4
120 * mA
V
= 10 2 * s
SLEW RATE C
C
= 3.3pF 30 * V/s
RESISTANCE
5
, 1mA R
CL
=

0 150 *
RESISTANCE
5
, 40 mA R
CL
= 0 5 *
POWER SUPPLY
VOLTAGE 50 150 175 * * * V
CURRENT, quiescent 2.2 2.5 * 2.3 mA
THERMAL
PA241DW RESISTANCE, AC junction to case F > 60Hz 7 10 * * C/W
PA241DW RESISTANCE, DC junction to case F < 60Hz 12 14 * * C/W
PA241DW RESISTANCE, junction to air Full temperature range 55 * C/W
TEMPERATURE RANGE, case Meets full range spec's 25 +85 * * C
SPECIFICATIONS
NOTES: * "A" specifcation is the same as the non "A" specifcation.
1. Unless otherwise noted T
C
= 25C, C
C
rating.
CL
PA241
PA241U 499
G
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C
B
A
G
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C
B
A
0
2
4
6
8
10
12
OUTPUT CURRENT, I
O
(mA)
V
D
R
O
P

F
R
O
M

V
S
,

(
V
)
V
DROP
- @85C
V
DROP
+ @85C
V
DROP
- @25C
V
DROP
+ @25C
0 20 40 60 80 100 120
FREQUENCY, F (Hz)
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)

10 100 1K 10K 100K
40
50
60
70
80
90
100
POSITIVE
NEGATIVE
100 1K
FREQUENCY, F (Hz)
0
80
120
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)

20
60
100
10 10K 100K
40
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T

(
%
)

115
105
95
85
120
110
100
90
80
100 150 200 250 300 350
I
Q
(-25C)
I
Q
(25C
)
I
Q
(85C
)
C
(pF)
S
L
E
W

R
A
T
E
,

(
V
/
s
)
SLEW RATE
10 20 30 40 50 0
5
15
25
35
60 70 100 10K
FREQUENCY, F (Hz)
0.001
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

(
%
)

10
1K 100K
0.1
0.01
1
30V
P-P
60V
P-P
180V
P-P
A
V
= 20
C
C
= 15pF
R
L
= 2K
FREQUENCY, F (Hz)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

(
V
O
U
T
)
(
p
-
p
)

100K 1M 10K
10
100
1000
POWER RESPONSE
.75pF
6.8pF
15pF
33pF
68pF
1M 10M 100K 10K
-170
-160
-150
-140
-130
-120
-180
PHASE RESPONSE
FREQUENCY, F (Hz)
P
H
A
S
E
,

)

68pF
15pF
6.8pF
.75pF
-110
-100
-90
10K 1K 100 10
68pF
15pF
6.8pF
.75pF
100
80
60
40
20
0
-20
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)

FREQUENCY, F (Hz)
10M 1M 100K
T
C
= 55C
T
C
= 85C
T
C
= 25C
T
C
= 125C
100
10
1
0.1
C
O
M
P
E
N
S
A
T
I
O
N
,

p
F

100 10 1
GAIN
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
I
LIMIT
VS. TEMPERATURE
V
B
E

(
V
)

-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE, (C)
V
BE
+
V
BE
-
0 25 50 75 100 125
TEMPERATURE, T (C)
0
3
6
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)

15
9
12
PA241CE
PA241DF
T = T
A
T = T
C
T = T
A
T = T
C
PA241DW
PA241
500 PA241U
GENERAL
PHASE COMPENSATION
as NPO or COG.
is a gain of 2).
CURRENT LIMIT
For proper operation, the current limit resistor, Rcl, must be
minimum value is 3.9 ohms, however for optimum reliability,
the resistor should be set as high as possible. The maximum
practical value is 110 ohms. Current limit values can be pre-
dicted as follows:
Ilimit =
Vbe
Rcl
Where Vbe is shown in the CURRENT LIMIT typical
graph.
Note that +Vbe should be used to predict current through
the +Vs pin, -Vbe for current through the -Vs pin, and that they
vary with case temperature. Value of the current limit resistor
at a case temperature of 25 can be estimated as follows:

Rcl =
0.7
Ilimit
When the amplifer is current limiting, there may be spurious
oscillation present during the current limited portion of the nega-
tive half cycle. The frequency of the oscillation is not predictable
and depends on the compensation, gain of the amplifer, value
of the current limit resistor, and the load. The oscillation will
cease as the amplifer comes out of current limit.
SAFE OPERATING AREA
2. Current handling capability of the die metalization.
for a case temperature of 25C and correspond to thermal
resistances of 5.2C/W for the PA241CE and DF and 10.4C/W
for the PA241DW respectively. Pulse stress levels for other
case temperatures can be calculated in the same manner as
DC power levels at different temperatures. The output stage
is protected against transient fyback by the parasitic diodes of
HEATSINKING
The PA241DF package has a large exposed integrated
copper heatslug to which the monolithic amplifer is directly
attached. The solder connection of the heatslug to a minimum
of 1 square inch foil area on the printed circuit board will result
in thermal performance of 25C/W junction to air rating of the
PA241DF. Solder connection to an area of 1 to 2 square inches
is recommended. This may be adequate heatsinking but the
large number of variables involved suggest temperature mea-
surements be made on the top of the package. Do not allow
the temperature to exceed 85C.
PA241
PA241U 501
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
S
-V
O
(V)
10 20 30 50 100 200 300 500
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S
,

(
m
A
)
2
3
4
5
10
20
30
40
50
100
D
C
,

T
C
=

1
2
5
C
D
C
,

T
C
=

8
5
C
D
C
PA241CE and DF SOA
2
0
0
m
S
120
200
S
-V
O
(V)
10 20 30 50 100 200 300 500
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S
,

(
m
A
)
2
3
4
5
10
20
30
40
50
100
D
C
,

T
C
=

1
2
5
C
D
C
,

T
C
=

8
5
C
D
C
PA241DW SOA
2
0
0
m
S
120
200
+Vs
-Vs
OUT
+Vs
-Vs
Z1
Z2
-IN
+IN
Q1
Q2
FIGURE 1
zeners clamp transients to voltages within the power supply
rating and also clamp power supply reversals to ground.
Whether the zeners are used or not the system power supply
should be evaluated for transient performance including power-
on overshoot and power-off polarity reversals as well as line
regulation. See Z1 and Z2 in Figure 1.
PA241M
502 PA241MU
PA241M
Q
25C 150V V
IN
= 0, A
V
= 100 2.5 mA
OS
25C 150V V
IN
= 0, A
V
= 100 30 mV
OS
25C 50V V
IN
= 0, A
V
= 100 30 mV
OS
25C 175V V
IN
= 0, A
V
= 100 30 mV
B
25C 150V V
IN
= 0 50 pA
B
25C 150V V
IN
= 0 50 pA
OS
25C 150V V
IN
= 0 50 pA
Q
40C 150V V
IN
= 0, A
V
= 100 2.5 mA
OS
40C 150V V
IN
= 0, A
V
= 100 60 mV
OS
40C 50V V
IN
= 0, A
V
= 100 60 mV
B
40C 150V V
IN
= 0 50 pA
B
40C 150V V
IN
= 0 50 pA
OS
40C 150V V
IN
= 0 50 pA
Q
125C 150V V
IN
= 0, A
V
= 100 3 mA
OS
125C 150V V
IN
= 0, A
V
= 100 30 mV
OS
125C 50V V
IN
= 0, A
V
= 100 30 mV
OS
125C 175V V
IN
= 0, A
V
= 100 30 mV
B
125C 150V V
IN
= 0 1 nA
B
125C 150V V
IN
= 0 1 nA
OS
125C 150V V
IN
= 0 1 nA
4 Output Voltage V
O
25C 52V R
L
= 1K, I
O
= 40mA 40 V
4 Current Limits I
CL
25C 30V R
L
= 100 50 125 mA
4 Stability/Noise E
N
25C 150V R
L
= 5K, A
V
= 1, C
L
= 10nF, C
C
= 68pF 10 mVrms
L
= 5K, C
C
= 6.8pF 5 V/s
4 Open Loop Gain A
OL
25C 150V R
L
= 5K, F = 15Hz 90 dB
L
= 5K, F = DC, V
CM
= 90V 84 dB
6 Output Voltage V
O
40C 52V R
L
= 1K, I
O
= 40mA 40 V
L
= 5K, C
C
= 6.8pF 5 V/s
6 Open Loop Gain A
OL
40C 150V R
L
= 5K, F = 15Hz 90 dB
L
= 5K, F = DC, V
CM
= 90V 80 dB
5 Output Voltage V
O
125C 50V R
L
= 1K, I
O
= 30mA 30 V
L
= 5K, C
C
= 6.8pF 5 V/s
5 Open Loop Gain A
OL
125C 150V R
L
= 5K, F = 15Hz 90 dB
L
= 5K, F = DC, V
CM
= 90V 80 dB
BURN IN CIRCUIT
burn in board.
** Internal power dissipation of approximately
2.1W at case temperature = 125C.
100K
100K
+50V
50V
5
6
8
3
7
60
**
*
U.U.T
*
2
4
1
100pF
R
CL
The PA241M is available ONLY in the CE (8-pin TO-3) package style.
SEP 2009
APEX PA241MUREVB
CPA241
CPA241U 503
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
CPA241
SUPPLY VOLTAGE, +V
S
to V
S
350V
OUTPUT CURRENT, continuous 60mA
S
TEMPERATURE, junction 150C
NOTE: Refer to parent product data sheet PA241 for typical AC electrical characteristics, precautions,
applications and other test parameters.
TYPICAL EXTERNAL CONNECTIONS DIE LAYOUT
* Required component and value if given.
Optional balance components are recommended values.
C
C
is NPO, rated for full supply voltage V
S
to +V
S
.
NOTE: Diagram for connection illustration only.
All op amp confgurations are possible.
Pad Function Pad Function
1 Output 5 +Vs
2 Compensation 6 -Vs
3 Compensation 8 +IN
4 Current Limit 9 -IN
CAUTION
The CPA241 is a MOSFET amplifer. ESD handling
procedures must be observed
Dimension: 154.5 x 117.5 2.5 Mils.
Thickness: 15 Mil (380).
Backside Metal: None, Silicon.
Bond pad: 5 Mil sq (127) AI.
Make no connection to bond pads not listed by function.
Note: The backside of the CPA241 die is isolated up to
500V. The top side walls of the CPA241 die are isolated up
to 300V.
Ordering Information:
Order #: CPA241DI80:
Die are only available in waffle packages with a total of 80
die per package.
NOTES: 1. Unless otherwise stated V
S
= 50 V, T
A
= 25C, DC input specifcation value given.
1
MIN TYP MAX UNITS
OFFSET VOLTAGE, initial V
S
= 50V 15 40 mV
COMMON MODE REJECTION V
CM
= 90 V DC 84 94 dB
VOLTAGE SWING I
O
= 40mA V
S
12 V
S
10 V
SUPPLY CURRENT, quiescent V
S
= 50 V 1.8 2.1 2.3 mA
DC WAFER PROBED SPECIFICATIONS
R
F
R
CL
+V
S
C
C
V
S
*
R
I
9
8
6
3
1
4 *
2
5
R
L
V
IN
1
2
3
4 5 6
7
8
9
10
11
12
High Power Operational Amplifier
CPA241 P r o d u c t I n n o v a t i o n F r o m
MAY 2009
APEX CPA241UREVC
PA243
504 PA243U
PA243
24-PIN PSOP
PACKAGE STYLE DF
EQUIVALENT SCHEMATIC (ONE OF TWO CHANNELS)
For C
C
values, see graph on page 3.
Note: C
C
must be rated for full supply voltage.
* Supply bypassing required. See general Operating Con-
siderations.
FEATURES
RoHS COMPLIANT
SURFACE MOUNT PACKAGE
LOW COST
NO SECOND BREAKDOWN
HIGH OUTPUT CURRENT120 mA PEAK
APPLICATIONS
TELEPHONE RING GENERATOR
DESCRIPTION
The PA243 is a dual high voltage monolithic MOSFET op-
erational amplifer achieving performance features previously
found only in hybrid designs while increasing reliability. This
approach provides a cost-effective solution to applications
where multiple amplifers are required. Inputs are protected
from excessive common mode and differential mode volt-
ages. The safe operating area (SOA) has no secondary
breakdown limitations and can be observed with all type
loads by choosing an appropriate current limiting resistor.
External compensation provides the user fexibility in choosing
optimum gain and bandwidth for the application.
The PA243DF is packaged in a 24 pin PSOP (JEDEC
MO-166) package. The heatslug of the PA243DF package is
isolated in excess of full supply voltage.
TYPICAL APPLICATION
LOW COST 660V
P-P
PIEZO DRIVE
A single PA243 amplifer operates as a bridge driver for a piezo
transducer providing a low cost 660 volt total drive capability.
The R
N
C
N
network serves to raise the apparent gain of A2 at
high frequencies. If R
N
is set equal to R the amplifers can be
compensated identically and will have matching bandwidths.
See application note 20 for more details.
A
PA243
B
PA243
20R
PIEZO
TRANSDUCER
20R
R
N
20R
C
N
R
V
IN
175
+175
175
+175
R
CL
R
CL
47 47
10pF
10pF
ILIM
OUT
-IN
+IN
+VS
-VS
CC2
CC1
Q2
D4
Q11
Q7
Q1
Q15
Q12
Q5
Q9
Q14
Q13
Q10
Q6
Q4
Q3
Q8
D2 D3
D1
D5
C
C
*
* *
*
C
C
R
CL
R
CL
+Vsa
NC
La
COMPa
COMPa
OUTa
NC
-INb
+INb
-Vsb
-Vsa
NC
NC
+INa
-INa
NC
OUTb
COMPb
COMPb
ILb
NC
+Vsb
24 1
+
-
+
-
A
B
MAY 2009
APEX PA243UREVG
PA243
PA243U 505
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
1
MIN TYP MAX UNITS
INPUT
3
25C to 85C 100 250 V/C
3
-25C to25C 270 500 V/C
OFFSET VOLTAGE, vs supply 3 V/V
OFFSET VOLTAGE, vs time 70 130 V/kh
BIAS CURRENT, vs supply 2 pA/V
11
S
14 V
S
+12 V
CM
= 90V DC 84 94 dB
S
= 1K 50 V RMS
NOISE, low frequency 1-10 Hz 125 V p-p
GAIN
OPEN LOOP at 15Hz R
L
=

5K 90 96 dB
BANDWIDTH, gain bandwidth product 3 MHz
POWER BANDWIDTH 280V p-p 30 kHz
OUTPUT
VOLTAGE SWING I
O
= 40mA V
S
12 V
S
10 V
CURRENT, peak
3
120 mA
V
= 10 2 s
SLEW RATE C
C
= 3.3pF 30 V/s
RESISTANCE
4
, 1mA R
CL
=

0 150
RESISTANCE
4
, 40 mA R
CL
= 0 5
POWER SUPPLY
THERMAL
AC, single amplifer F > 60Hz 6 7 C/W
DC, single amplifer F < 60Hz 9 11 C/W
AC, both amplifers
5
3.3 4.0 C/W
DC, both amplifers
5
5.0 6.0 C/W
6
SUPPLY VOLTAGE, +V
S
to V
S
350V
OUTPUT CURRENT, peak 120 mA
C
= 25C 12W
S
2
150C
SPECIFICATIONS
NOTES: 1. Unless otherwise noted T
C
= 25C, C
C
= 6.8pF. DC input specifcations are value given. Power supply voltage is typical rat-
ing.
CL
5. Rating applies when power dissipation is equal in the two amplifers.
6. Rating applies with solder connection of heatslug to a minimum 1in
2
foil area of the printed circuit board.
PA243
506 PA243U
0
2
4
6
8
10
12
OUTPUT CURRENT, I
O
(mA)
V
D
R
O
P

F
R
O
M

V
S
,

(
V
)
V
DROP
- @85C
V
DROP
+ @85C
V
DROP
- @25C
V
DROP
+ @25C
0 20 40 60 80 100 120
FREQUENCY, F (Hz)
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)

10 100 1K 10K 100K
40
50
60
70
80
90
100
POSITIVE
NEGATIVE
100 1K
FREQUENCY, F (Hz)
0
80
120
C
O
M
M
O
N

M
O
D
E

R
E
J
E
C
T
I
O
N
,

C
M
R

(
d
B
)

20
60
100
10 10K 100K
40
QUIESCENT CURRENT
N
O
R
M
A
L
I
Z
E
D

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T

(
%
)

115
105
95
85
120
110
100
90
80
100 150 200 250 300 350
I
Q
(-25C)
I
Q
(25C
)
I
Q
(85C
)
C
(pF)
S
L
E
W

R
A
T
E
,

(
V
/
s
)
SLEW RATE
10 20 30 40 50 0
0
15
25
35
60 70 100 10K
FREQUENCY, F (Hz)
0.001
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

(
%
)

10
1K 100K
0.1
0.01
1
30V
P-P
60V
P-P
180V
P-P
A
V
= 20
C
C
= 15pF
R
L
= 2K
FREQUENCY, F (Hz)
O
U
T
P
U
T

V
O
L
T
A
G
E
,

(
V
O
U
T
)
(
p
-
p
)

100K 1M 10K
10
100
1000
POWER RESPONSE
.75pF
6.8pF
15pF
33pF
68pF
1M 10M 100K 10K
-170
-160
-150
-140
-130
-120
-180
PHASE RESPONSE
FREQUENCY, F (Hz)
P
H
A
S
E
,

)

68pF
15pF
6.8pF
.75pF
-110
-100
-90
10K 1K 100 10
68pF
15pF
6.8pF
.75pF
100
80
60
40
20
0
-20
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)

FREQUENCY, F (Hz)
10M 1M 100K
T
C
= 55C
T
C
= 85C
T
C
= 25C
T
C
= 125C
100
10
1
0.1
C
O
M
P
E
N
S
A
T
I
O
N
,

p
F

100 10 1
GAIN
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
I
LIMIT
VS. TEMPERATURE
V
B
E

(
V
)

-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE, (C)
V
BE
+
V
BE
-
0 20 40 60 80 100
TEMPERATURE, T (C)
0
5
10
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)

25
15
20
T = T
A
T = T
C
Both Amplifiers
Single Amplifier
T = T
A
T = T
C
PA243
PA243U 507
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
GENERAL
PHASE COMPENSATION
as NPO or COG.
is a gain of 2).
CURRENT LIMIT
For proper operation, the current limit resistor, Rcl, must be
minimum value is 3.9 ohms, however for optimum reliability,
the resistor should be set as high as possible. The maximum
practical value is 110 ohms. Current limit values can be pre-
dicted as follows:
Ilimit =
Vbe
Rcl
Where Vbe is shown in the CURRENT LIMIT typical
graph.
Note that +Vbe should be used to predict current through
the +Vs pin, -Vbe for current through the -Vs pin, and that they
vary with case temperature. Value of the current limit resistor
at a case temperature of 25 can be estimated as follows:

Rcl =
0.7
Ilimit
When the amplifer is current limiting, there may be spurious
oscillation present during the current limited portion of the nega-
tive half cycle. The frequency of the oscillation is not predictable
and depends on the compensation, gain of the amplifer, value
of the current limit resistor, and the load. The oscillation will
cease as the amplifer comes out of current limit.
SAFE OPERATING AREA
2. Current handling capability of the die metalization.
PA243 SOA
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

o
r

-
V
S
,

(
m
A
)
S
- V
O
(V)
10
2
PULSE CURVES @
10% DUTY CYCLE MAX.
2
0
0
m
S
3
200
120
100
50
40
30
20
10
5
4
20 500 300 200 100 50 30
3
0
0
m
S
D
C
D
C
,

T
C
=

8
5
C
D
C
,

T
C
=

1
2
5
C
PA243
508 PA243U
for a case temperature of 25C and correspond to thermal re-
sistances of 5.2C/W for the PA243DF. Pulse stress levels for
other case temperatures can be calculated in the same manner
as DC power levels at different temperatures. The output stage
is protected against transient fyback by the parasitic diodes of
HEATSINKING
The PA243DF package has a large exposed integrated
copper heatslug to which the monolithic amplifer is directly
attached. The solder connection of the heatslug to a minimum
of 1 square inch foil area on the printed circuit board will result
in thermal performance of 25C/W junction to air rating of the
PA243DF. Solder connection to an area of 1 to 2 square inches
is recommended. This may be adequate heatsinking but the
large number of variables involved suggest temperature mea-
surements be made on the top of the package. Do not allow
the temperature to exceed 85C.
FIGURE 1
+Vs
-Vs
OUT
+Vs
-Vs
Z1
Z2
-IN
+IN
Q1
Q2
zeners clamp transients to voltages within the power sup-
ply rating and also clamp power supply reversals to ground.
Whether the zeners are used or not the system power sup-
ply should be evaluated for transient performance including
power-on overshoot and power-off polarity reversals as well
as line regulation. See Z1 and Z2 in Figure 1.
PB50
PB50U 509
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PB50
FEATURES
HIGH OUTPUT CURRENT Up to 2A Continuous
VOLTAGE AND CURRENT GAIN
HIGH SLEW RATE 50V/s Minimum
HIGH POWER BANDWIDTH 160 kHz Minimum
LOW QUIESCENT CURRENT 12mA Typical
APPLICATIONS
Electrostatic TRANSDUCERS & DEFLECTION
Programmable Power Supplies Up to 180V p-p
DESCRIPTION
The PB50 is a high voltage, high current amplifer designed
to provide voltage and current gain for a small signal, general
purpose op amp. Including the power booster within the feed-
back loop of the driver amplifer results in a composite amplifer
with the accuracy of the driver and the extended output voltage
range and current capability of the booster. The PB50 can also
be used without a driver in some applications, requiring only
an external current limit resistor to function properly.
The output stage utilizes complementary MOSFETs, provid-
ing symmetrical output impedance and eliminating secondary
breakdown limitations imposed by Bipolar Junction Transis-
tors. Internal feedback and gainset resistors are provided for
a pin-strappable gain of 3. Additional gain can be achieved
with a single external resistor. Compensation is not required
for most driver/gain confgurations, but can be accomplished
with a single external capacitor. Although the booster can
be confgured quite simply, enormous fexibility is provided
through the choice of driver amplifer, current limit, supply
voltage, voltage gain, and compensation.
This hybrid circuit utilizes a beryllia (BeO) substrate, thick
package is electrically isolated and hermetically sealed using
one-shot resistance welding. The use of compressible isolation
washers voids the warranty.
TYPICAL APPLICATION
Figure 1. Inverting composite amplifer.
OP
AMP
PB50
C
F
R
F
V
IN
R
I
+15V
15V
IN
COM
+Vs
Vs
R
CL
OUT
C
C
R
G
R
L
3
1
2
6
8
5
4
7
IN
GAIN
COM
COMP
Q1
Q4
Q2
Q3
Q5
Q6
Q7
Q8
Q10 Q9
+Vs
OUT
CL
Vs
6.2K
50K 3.1K
1
2 3
4
5
6 7
8
TOP VIEW
CL
+Vs
IN
COM
Vs
GAIN
R
G
COMP
C
C
OUT
R
CL
8-PIN TO-3
PACKAGE STYLE CE
Power Booster Amplifier
PB50 P r o d u c t I n n o v a t i o n F r o m
MAY 2009
APEX PB50UREVJ
PB50
510 PB50U
SUPPLY VOLTAGE, +V
S
to V
S
200V
C
= 25C
1
35W
INPUT VOLTAGE, referred to common 15V
1
150C
SPECIFICATIONS
2
MIN TYP MAX UNITS
INPUT
OFFSET VOLTAGE, initial .75 1.75 V
OFFSET VOLTAGE, vs. temperature Full temperature range 4.5 7 mV/C
INPUT IMPEDANCE, DC 25 50 k
CLOSED LOOP GAIN RANGE 3 10 25 V/V
GAIN ACCURACY, internal Rg, Rf A
V
= 3 10 15 %
GAIN ACCURACY, external Rf A
V
= 10 15 25 %
PHASE SHIFT F = 10kHz, AV
CL
= 10, C
C
= 22pF 10
F = 200kHz, AV
CL
= 10, C
C
= 22pF 60

OUTPUT
VOLTAGE SWING Io = 2A V
S
11 V
S
9 V
S
10 V
S
7 V
VOLTAGE SWING Io = .1A V
S
8 V
S
5 V
SLEW RATE Full temperature range 50 100 V/s
CAPACITIVE LOAD Full temperature range 2200 pF
L
= 100, 2V step 2 s
POWER BANDWIDTH V
C
= 100Vpp 160 320 kHz
SMALL SIGNAL BANDWIDTH C
C
= 22pF, A
V
= 25, Vcc = 100 100 kHz
C
= 22pF, A
V
= 3, Vcc = 30 1 MHz
POWER SUPPLY
VOLTAGE, V
S
3
5
60 100 V
CURRENT, quiescent V
S
= 30 9 12 mA
V
S
= 60 12 18 mA
V
S
= 100 17 25 mA
THERMAL
4
Full temp. range, F > 60Hz 1.8 2.0 C/W
RESISTANCE, DC junction to case Full temp. range, F < 60Hz 3.2 3.5 C/W
TEMPERATURE RANGE, case Meets full range specifcations 25 25 85 C
NOTES: 1. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation to
achieve high MTTF (Mean Time to Failure).
2. The power supply voltage specifed under typical (TYP) applies, T
C
= 25C unless otherwise noted.
3. +V
S
and V
S
5. +V
S
must be at least 15V above COM, V
S
must be at least 30V below COM.
The PB50 is constructed from MOSFET transistors. ESD handling procedures must be observed.
CAUTION
PB50
PB50U 511
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
25 0 25 50 75 100
0
10
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
25 25 125
0
1.5
2
CURRENT LIMIT
1
.5
S
L
E
W

R
A
T
E
,

S
R

(
V
/
s
)
100 10M
FREQUENCY, F (Hz)
0
60
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
20
40
80
1K 10K 10M
10
20
30
10
1K 10K 10M
FREQUENCY, F (Hz)
180
1K 10K 30K 1M
FREQUENCY, F (Hz)
11
360
POWER RESPONSE
V
Q

(
V
)
,

P
-
P
22
90
180
300 30K
FREQUENCY, F (Hz)
.01
.03
1
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

T
H
D

(
%
)
.3
300 3K 30K
FREQUENCY, F (Hz)
.001
.1
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

T
H
D

(
%
)
.01
.03
25 75
CASE TEMPERATURE, T
C
(C)
0
QUIESCENT CURRENT
20
100 0 25
INPUT OFFSET VOLTAGE
I
N
P
U
T

O
F
F
S
E
T

V
O
L
T
A
G
E
,

V
O
S

(
V
)
.01 .02 2
OUTPUT CURRENT, I
O
(A)
2
10
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

-

V
O

(
V
)
8
3K 100K 300K 1K
.003
SLEW RATE VS. TEMP.
0
300
400
100
200
0 50 75 100
40
100K
1K 3K 10K
.1 .2 1
6
-1.5
1K 10K 100K 1M
125
20
30
100K 1M
FREQUENCY, F (Hz)
C
L
O
S
E
D

L
O
O
P

G
A
I
N
,

A

(
d
B
)
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
4
50 125
5
10
15
-1
.5
0
.5
1M
135
90
45
0
45
10K
.1
CASE TEMPERATURE, T
C
C
(C)
R
CL
=
.68
R
CL
= 1.5
O
P
E
N

L
O
O
P

P
H
A
S
E
,

)
180
135
90
45
0
R
CL
=
.3
3
C
L
O
S
E
D

L
O
O
P

P
H
A
S
E
,

)
0
R
CL
= .27
AV
CL
= 10
AV
CL
= 3
AV
CL
= 25
AV
CL
= 25
AV
CL
= 10
AV
CL
= 3
V
O
+
V
O

Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
O

(
m
A
)
Vs = 60V
Vs = 30V
CASE TEMPERATURE, T
C
( C) OR V
S
(V)
25 75 100 0 25 50 125
Vs = 100V
TEMP.
25 75
CASE TEMPERATURE, T
C
(C)
100 0 25 50 125
+SLEW
SLEW
SUPPLY
C
C
= 22pF
R
L
= 25
R
L
= 25
R
L
= 1K
R
L
= 1K
NO DRIVER
V
S
= 60V
V
O
= 80V
P-P
DRIVER = TL070
V
S
= 60V
V
O
= 95V
P-P
C
C
= 22pF
PB50
512 PB50U
GENERAL
CURRENT LIMIT
CL
) must be
con nected as shown in the external connection diagram. The
minimum value is 0.27 with a maximum practical value of
47. For optimum reliability the resistor value should be set
as high as possible. The value is calculated as follows: +I
L
=
.65/R
CL
+ .010, I
L
= .65/R
CL
.
COMPOSITE AMPLIFIER CONSIDERATIONS
Cascading two amplifers within a feedback loop has many
advantages, but also requires careful consideration of several
amplifer and system parameters. The most important of these
are gain, stability, slew rate, and output swing of the driver.
Operating the booster amplifer in higher gains results in a
higher slew rate and lower output swing requirement for the
driver, but makes stability more difficult to achieve.
GAIN SET
R
G
= [ (Av-1) 3.1K] 6.2K
R
G
+ 6.2K
Av = +1
3.1K
The boosters closed-loop gain is given by the equation
above. The composite amplifers closed loop gain is determined
by the feedback network, that is: Rf/Ri (inverting) or 1+Rf/Ri
(non-inverting). The driver amplifers effective gain is equal
to the composite gain divided by the booster gain.
Example: Inverting confguration (fgure 1) with
R i = 2K, R f = 60K, R g = 0 :
Av (booster) = (6.2K/3.1K) + 1 = 3
Av (composite) = 60K/2K = - 30
Av (driver) = - 30/3 = -10
STABILITY
Stability can be maximized by observing the following
guidelines:
1. Operate the booster in the lowest practical gain.
2. Operate the driver amplifer in the highest practical effective
gain.
3. Keep gain-bandwidth product of the driver lower than the
closed loop bandwidth of the booster.
4. Minimize phase shift within the loop.
A good compromise for (1) and (2) is to set booster gain
from 3 to 10 with total (composite) gain at least a factor of 3
times booster gain. Guideline (3) implies compensating the
driver as required in low composite gain confgurations. Phase
shift within the loop (4) is minimized through use of booster
and loop compensation capacitors Cc and Cf when required.
Typical values are 5pF to 33pF.
Stability is the most difficult to achieve in a confguration where
driver effective gain is unity (ie; total gain = booster gain). For
this situation, Table 1 gives compensation values for optimum
square wave response with the op amp drivers listed.
DRIVER C
CH
C
F
C
C
FPBW SR
OP07 - 22p 22p 4kHz 1.5
741 - 18p 10p 20kHz 7
LF155 - 4.7p 10p 60kHz >60
LF156 - 4.7p 10p 80kHz >60
TL070 22p 15p 10p 80kHz >60
For: R
F
= 33K, R
I
= 3.3K, R
G
= 22K
Table 1:
Typical values for case where op amp effective gain = 1.
Figure 2. Non-inverting composite amplifer.
SLEW RATE
The slew rate of the composite amplifer is equal to the slew
rate of the driver times the booster gain, with a maximum value
equal to the booster slew rate.
OUTPUT SWING
The maximum output voltage swing required from the driver
op amp is equal to the maximum output swing from the booster
divided by the booster gain. The Vos of the booster must also
be supplied by the driver, and should be subtracted from the
available swing range of the driver. Note also that effects of Vos
drift and booster gain accuracy should be considered when
calculating maximum available driver swing.
10 20 30 40 50 100 200 300
S
V
O
(V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S

(
A
)
1
2
3
.1
S
T
E
A
D
Y

S
T
A
T
E

T

=

8
5
C
C
t

=

5
0
m
s
t

=

1
0
0
m
s
S
T
E
A
D
Y

S
T
A
T
E

T

=

2
5
C
C
S
T
E
A
D
Y

S
T
A
T
E

T

=

1
2
5
C
C
t

=

2
0
0
m
s
SOA
OP
AMP
PB50
C
F
R
F
R
I
+15V
15V
IN
COM
+Vs
Vs
R
CL
OUT
C
C
R
G
R
L
V
IN
GAIN
COMP
C
CH
PB51
PB51U 513
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PB51, PB51A
FEATURES
HIGH OUTPUT CURRENT
1.5A Continuous (PB51), 2.0A Continuous (PB51A)
HIGH SLEW 50V/s Minimum (PB51)
75V/s Minimum (PB51A)
EVALUATION KIT EK29
APPLICATIONS
PROGRAMMABLE POWER SUPPLIES UP TO 280V P-P
DESCRIPTION
The output stage utilizes complementary MOSFETs, pro-
viding symmetrical output impedance and eliminating second
breakdown limitations imposed by Bipolar Transistors. Internal
feedback and gainset resistors are provided for a pin-strapable
gain of 3. Additional gain can be achieved with a single external
resistor. Compensation is not required for most driver/gain
confgurations, but can be accomplished with a single external
capacitor. Enormous fexibility is provided through the choice
of driver amplifer, current limit, supply voltage, voltage gain,
and compensation.
connections at all operating temperatures. The 12-pin Power
SIP package is electrically isolated.
TYPICAL APPLICATION
OP
AMP
PB51
C
F
R
F
V
IN
R
I
+15V
15V
IN
COM
+Vs
Vs
R
CL
OUT
C
C
R
G
R
L
Q1
Q4
Q2
3 Q
Q5
Q6
Q7
8
12
9
11
5
2
6
1
Q8
Q10 Q9
Q11
3.1K
IN
COM
CC
GAIN
ILIM
OUT
+V
S
V
S
1 2 3 4 5 6 7 8 9 10
IN
COM
NC NC
11 12
C
C
R
G
R
CL
NC NC
OUT
+V
S
-V
S
12-PIN SIP
PACKAGE STYLE DP
Formed leads available. See package styles ED & EE
PB51 PB51A P r o d u c t I n n o v a t i o n F r o m
JUN 2009
APEX PB51UREVE
PB51
514 PB51U
SUPPLY VOLTAGE, +V
S
to V
S
300V
OUTPUT CURRENT, within SOA 2.0A
C
= 25C
1
83W
INPUT VOLTAGE, referred to COM 15V
TEMPERATURE, pin solder10s max. 260C
1
175C
SPECIFICATIONS
PB51 PB51A
2
INPUT
OFFSET VOLTAGE, initial .75 1.75 * 1.0 V
OFFSET VOLTAGE, vs. temperature Full temperature range
3
4.5 7 * * mV/C
INPUT IMPEDANCE, DC 25 50 * * k
CLOSED LOOP GAIN RANGE 3 10 25 * * * V/V
GAIN ACCURACY, internal Rg, Rf AV

= 3 10 15 * * %
GAIN ACCURACY, external Rf AV

= 10 15 25 * * %
PHASE SHIFT f = 10kHz, AVC
L
= 10, CC

= 22pF 10 *
f = 200kHz, AVC
L
= 10, CC

= 22pF 60 *

OUTPUT
VOLTAGE SWING Io = 1.5A (PB58), 2A (PB58A) VS11 VS

8 VS15 VS11 V
VOLTAGE SWING Io = 1A VS10 VS

7 * * V
VOLTAGE SWING Io = .1A VS8 VS

5 * * V
CURRENT, continuous 1.5 2.0 A
SLEW RATE Full temperature range 50 100 75 * V/s
CAPACITIVE LOAD Full temperature range 2200 * pF
SETTLING TIME to .1% RL

= 100, 2V step 2 * s
POWER BANDWIDTH VC = 100 Vpp 160 320 240 * kHz
SMALL SIGNAL BANDWIDTH CC = 22pF, AV = 25, Vcc = 100 100 * kHz
SMALL SIGNAL BANDWIDTH CC = 22pF, AV = 3, Vcc = 30 1 * MHz
POWER SUPPLY
VOLTAGE, VS
4
6
60 150 * * * V
CURRENT, quiescent VS = 15 11 * mA
VS = 60 12 * mA
VS = 150 14 18 * * mA
THERMAL
RESISTANCE, AC junction to case5 Full temp. range, f > 60Hz 1.2 1.3 * * C/W
RESISTANCE, DC junction to case Full temp. range, f < 60Hz 1.6 1.8 * * C/W
TEMPERATURE RANGE, case Meets full range specifcations 25 25 85 * * * C
NOTES: * The specifcation of PB51A is identical to the specifcation for PB51 in applicable column to the left.
C
3. Guaranteed by design but not tested.
4. +V
S
and V
S
6. +V
S
/V
S
must be at least 15V above/below COM.
The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not crush, machine, or subject to
temperatures in excess of 850C to avoid generating toxic fumes.
CAUTION
PB51
PB51U 515
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
25 0 25 50 75 100
0
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
25 25 125
0
1.5
2
CURRENT LIMIT
1
.5
S
L
E
W

R
A
T
E
,

S
R

(
V
/
s
)
100 10M
FREQUENCY, F (Hz)
0
60
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
20
40
80
1K 10K 10M
10
20
30
10
1K 10K 10M
FREQUENCY, F (Hz)
180
100K 1M 10M
FREQUENCY, F (Hz)
10
300
POWER RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
Q

(
V
P
-
P
)
20
100
200
1
TIME, t (s)
-80
PULSE RESPONSE
300 3K 30K
FREQUENCY, F (Hz)
.001
.1
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

T
H
D

(
%
)
.01
.03
25 75
CASE TEMPERATURE, T
C
(C)
0
QUIESCENT CURRENT
20
100 0 25
I
N
P
U
T

O
F
F
S
E
T

V
O
L
T
A
G
E
,

V
O
S

(
V
)
.01 .05 2
OUTPUT CURRENT, I
O
(A)
4
12
14
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

-

V
O

(
V
)
10
300K 3M 1K
.003
SLEW RATE VS. TEMP.
0
300
400
100
200
0 50 75 100
40
100K
1 1.5
8
-1.5
1K 10K 100K 1M
125
20
100K 1M
FREQUENCY, F (Hz)
C
L
O
S
E
D

L
O
O
P

G
A
I
N
,

A

(
d
B
)
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
6
50 125
5
10
15
-1
-.5
0
.5
1M
135
90
45
0
30
10K
CASE TEMPERATURE, T
C
C
(C)
O
P
E
N

L
O
O
P

P
H
A
S
E
,

)
180
135
90
45
0
C
L
O
S
E
D

L
O
O
P

P
H
A
S
E
,

)
0
AV
CL
= 10
AV
CL
= 3
AV
CL
= 25
AV
CL
= 25
AV
CL
= 10
AV
CL
= 3
V
O
+
V
O
-
Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
m
A
)
Vs = 100V
Vs = 30V
CASE TEMPERATURE, T
C
(C)
25 75 100 0 25 50 125
Vs = 150V
25 75
CASE TEMPERATURE, T
C
(C)
100 0 25 50 125
DRIVER = TL070
V
S
= 60V
V
O
= 95V
P-P
60
80
100
R
CL
=
.4
7
R
CL
= .68
R
CL
= 1.5
C
C
= 22pF C
C
= 22pF
40
50
2 3 4 5 6 7 8
-60
-40
-20
0
20
40
60
80
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
Q

(
V
)
R
L

=

3
5
R
L

=

1
K
-SLEW
+
S
L
E
W
PB51
516 PB51U
STABILITY
guidelines:
gain.
A good compromise for (1) and (2) is to set booster gain from
3 to 10 with total (composite) gain at least a factor of 3 times
booster gain. Guideline (3) implies compensating the driver
as required in low composite gain confgurations. Phase shift
within the loop (4) is minimized through use of booster and loop
compensation capacitors Cc and Cf when required. Typical
values are 5pF to 33pF.
SLEW RATE
OUTPUT SWING
GENERAL
CURRENT LIMIT
CL
) must be
minimum value is 0.33 with a maximum practical value of 47.
For optimum reliability the resistor value should be set as high
as possible. The value is calculated as follows:
+I
L
=.65/R
CL
+ .010, -I
L
= .65/R
CL
.
SAFE OPERATING AREA
However, for protection against sustained, high energy fy-
back, external fast-recovery diodes should be used.
GAIN SET
The boosters closed-loop gain is given by the equation above.
The composite amplifers closed loop gain is determined by the
feedback network, that is: Rf/Ri (inverting) or 1+Rf/Ri (non-
inverting). The driver amplifers effective gain is equal to the
composite gain divided by the booster gain.
R i = 2K, R f = 60K, R g = 0 :
Av (booster) = (6.2K/3.1K) + 1 = 3
Av (composite) = 60K/2K = 30
Av (driver) = 30/3 = 10
t

=

1
0
0
m
s
s
t
e
a
d
y

s
t
a
t
e

T
C
=

2
5
C
s
t
e
a
d
y

s
t
a
t
e

T
C
=

8
5
C
s
t
e
a
d
y

s
t
a
t
e

T
C
=

1
2
5
C
3
2
1
.2
.3
.4
.5
10 20 30 40 50 100 200 300
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

o
r

V
S

(
A
)
S
V
O
(V)
.1
SOA
R
G
= [(Av-1) 3.1K] - 6.2K
R
G
+ 6.2K
Av = +1
3.1K
DRIVER C
CH
C
F
C
C
FPBW SR
OP07 - 22p 22p 4kHz 1.5
741 - 18p 10p 20kHz 7
LF155 - 4.7p 10p 60kHz >60
LF156 - 4.7p 10p 80kHz >60
TL070 22p 15p 10p 80kHz >60
For: R
F
= 33K, R
I
= 3.3K, R
G
= 22K
TABLE 1. TYPICAL VALUES FOR CASE WHERE OP AMP
EFFECTIVE GAIN = 1.
OP
AMP
PB51
C
F
R
F
R
I
+15V
15V
IN
COM
+Vs
Vs
R
CL
OUT
C
C
R
G
R
L
V
IN
GAIN
COMP
C
CH
PB58 PB58A
PB58U 517
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
PB58, PB58A
FEATURES
HIGH OUTPUT CURRENT
1.5A Continuous (PB58)
2.0A Continuous (PB58A)
HIGH SLEW 50V/s Minimum (PB58)
75V/s Minimum (PB58A)
EVALUATION KIT See EK50
APPLICATIONS
Electrostatic TRANSDUCERS & DEFLECTION
Programmable Power Supplies Up to 280V p-p
DESCRIPTION
The output stage utilizes complementary MOSFETs, pro-
viding symmetrical output impedance and eliminating second
breakdown limitations imposed by Bipolar Transistors. Internal
feedback and gainset resistors are provided for a pin-strapable
gain of 3. Additional gain can be achieved with a single external
resistor. Compensation is not required for most driver/gain
confgurations, but can be accomplished with a single external
capacitor. Enormous fexibility is provided through the choice
of driver amplifer, current limit, supply voltage, voltage gain,
and compensation.
package is electrically isolated and hermetically sealed using
one-shot resistance welding. The use of compressible isolation
washers voids the warranty.
TYPICAL APPLICATION Figure 1. Inverting
composite amplifer.
3
1
2
6
8
5
4
7
IN
GAIN
COM
COMP
Q1
Q4
Q2
Q3
Q5
Q6
Q7
Q8
Q10 Q9
+Vs
OUT
CL
Vs
Q11
6.2K
50K 3.1K
1
2 3
4
5
6 7
8
TOP VIEW
CL
+V
S
IN
COM
V
S
GAIN
R
G
COMP C
C
OUT
R
CL
OP
AMP
PB58
C
F
R
F
V
IN
R
I
+15V
15V
IN
COM
+Vs
Vs
R
CL
OUT
C
C
R
G
R
L
8-PIN TO-3
PACKAGE STYLE CE
PB58 PB58A P r o d u c t I n n o v a t i o n F r o m
MAY 2009
APEX PB58UREVK
PB58 PB58A
518 PB58U
SUPPLY VOLTAGE, +V
S
to V
S
300V
OUTPUT CURRENT, within SOA 2.0A
C
= 25C
1
83W
INPUT VOLTAGE, referred to COM 15V
1
175C
SPECIFICATIONS
PB58 PB58A
2
INPUT
OFFSET VOLTAGE, initial .75 1.75 * 1.0 V
OFFSET VOLTAGE, vs. temperature Full temperature range
3
4.5 7 * * mV/C
INPUT IMPEDANCE, DC 25 50 * * k
CLOSED LOOP GAIN RANGE 3 10 25 * * * V/V
GAIN ACCURACY, internal Rg, Rf A
V
= 3 10 15 * * %
GAIN ACCURACY, external Rf A
V
= 10 15 25 * * %
PHASE SHIFT f = 10kHz, AV
CL
= 10, C
C
= 22pF 10 *
f = 200kHz, AV
CL
= 10, C
C
= 22pF 60 *
OUTPUT
VOLTAGE SWING Io = 1.5A (PB58), 2A (PB58A) V
S
11 V
S
8 V
S
15 V
S
11 V
S
10 V
S
7 * * V
VOLTAGE SWING Io = .1A V
S
8 V
S
5 * * V
CURRENT, continuous 1.5 2.0 A
SLEW RATE Full temperature range 50 100 75 * V/s
CAPACITIVE LOAD Full temperature range 2200 * pF
L
= 100, 2V step 2 * s
POWER BANDWIDTH V
C
= 100 Vpp 160 320 240 * kHz
C
= 22pF, A
V
= 25, Vcc = 100 100 * kHz
C
= 22pF, A
V
= 3, Vcc = 30 1 * MHz
POWER SUPPLY
VOLTAGE, V
S
4
6
60 150 * * * V
CURRENT, quiescent V
S
= 15 11 * mA
V
S
= 60 12 * mA
V
S
= 150 14 18 * * mA
THERMAL
5
Full temp. range, f > 60Hz 1.2 1.3 * * C/W
RESISTANCE, DC junction to case Full temp. range, f < 60Hz 1.6 1.8 * * C/W
TEMPERATURE RANGE, case Meets full range specifcations 25 25 85 * * * C
NOTES: * The specifcation of PB58A is identical to the specifcation for PB58 in applicable column to the left.
C
3. Guaranteed by design but not tested.
4. +V
S
and V
S
6. +V
S
/V
S
must be at least 15V above/below COM.
CAUTION
PB58 PB58A
PB58U 519
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
25 0 25 50 75 100
0
POWER DERATING
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P
(
W
)
25 25 125
0
1.5
2
CURRENT LIMIT
1
.5
S
L
E
W

R
A
T
E
,

S
R

(
V
/
s
)
100 10M
FREQUENCY, F (Hz)
0
60
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
20
40
80
1K 10K 10M
10
20
30
10
1K 10K 10M
FREQUENCY, F (Hz)
180
100K 1M 10M
FREQUENCY, F (Hz)
10
300
POWER RESPONSE
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
Q

(
V
P
-
P
)
20
100
200
1
TIME, t (s)
-80
PULSE RESPONSE
300 3K 30K
FREQUENCY, F (Hz)
.001
.1
HARMONIC DISTORTION
D
I
S
T
O
R
T
I
O
N
,

T
H
D

(
%
)
.01
.03
25 75
CASE TEMPERATURE, T
C
(C)
0
QUIESCENT CURRENT
20
100 0 25
I
N
P
U
T

O
F
F
S
E
T

V
O
L
T
A
G
E
,

V
O
S

(
V
)
.01 .05 2
OUTPUT CURRENT, I
O
(A)
4
12
14
V
O
L
T
A
G
E

D
R
O
P

F
R
O
M

S
U
P
P
L
Y
,

V
S

-

V
O

(
V
)
10
300K 3M 1K
.003
SLEW RATE VS. TEMP.
0
300
400
100
200
0 50 75 100
40
100K
1 1.5
8
-1.5
1K 10K 100K 1M
125
20
100K 1M
FREQUENCY, F (Hz)
C
L
O
S
E
D

L
O
O
P

G
A
I
N
,

A

(
d
B
)
C
U
R
R
E
N
T

L
I
M
I
T
,

I
L
I
M

(
A
)
6
50 125
5
10
15
-1
-.5
0
.5
1M
135
90
45
0
30
10K
CASE TEMPERATURE, T
C
C
(C)
O
P
E
N

L
O
O
P

P
H
A
S
E
,

)
180
135
90
45
0
C
L
O
S
E
D

L
O
O
P

P
H
A
S
E
,

)
0
AV
CL
= 10
AV
CL
= 3
AV
CL
= 25
AV
CL
= 25
AV
CL
= 10
AV
CL
= 3
V
O
+
V
O
-
Q
U
I
E
S
C
E
N
T

C
U
R
R
E
N
T
,

I
Q

(
m
A
)
Vs = 100V
Vs = 30V
CASE TEMPERATURE, T
C
(C)
25 75 100 0 25 50 125
Vs = 150V
25 75
CASE TEMPERATURE, T
C
(C)
100 0 25 50 125
DRIVER = TL070
V
S
= 60V
V
O
= 95V
P-P
60
80
100
R
CL
=
.4
7
R
CL
= .68
R
CL
= 1.5
C
C
= 22pF C
C
= 22pF
40
50
2 3 4 5 6 7 8
-60
-40
-20
0
20
40
60
80
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V
Q

(
V
)
R
L

=

3
5
R
L

=

1
K
-SLEW
+
S
L
E
W
PB58 PB58A
520 PB58U
STABILITY
guidelines:
gain.
A good compromise for (1) and (2) is to set booster gain
from 3 to 10 with total (composite) gain at least a factor of 3
times booster gain. Guideline (3) implies compensating the
driver as required in low composite gain confgurations. Phase
shift within the loop (4) is minimized through use of booster
and loop compensation capacitors Cc and Cf when required.
Typical values are 5pF to 33pF.
DRIVER C
CH
C
F
C
C
FPBW SR
OP07 - 22p 22p 4kHz 1.5
741 - 18p 10p 20kHz 7
LF155 - 4.7p 10p 60kHz >60
LF156 - 4.7p 10p 80kHz >60
TL070 22p 15p 10p 80kHz >60
For: R
F
= 33K, R
I
= 3.3K, R
G
= 22K
Table 1: Typical values for case where op amp effective gain
= 1.
Figure 2. Non-inverting composite amplifer.
SLEW RATE
OUTPUT SWING
GENERAL
CURRENT LIMIT
CL
) must be
minimum value is 0.33 with a maximum practical value of
47. For optimum reliability the resistor value should be set
as high as possible. The value is calculated as follows: +I
L
=
.65/R
CL
+ .010, -I
L
= .65/R
CL
.
SAFE OPERATING AREA
GAIN SET
R
G
= [ (Av-1) 3.1K] 6.2K
R
G
+ 6.2K
Av = +1
3.1K
The boosters closed-loop gain is given by the equation
above. The composite amplifers closed loop gain is determined
by the feedback network, that is: Rf/Ri (inverting) or 1+Rf/Ri
(non-inverting). The driver amplifers effective gain is equal
to the composite gain divided by the booster gain.
R i = 2K, R f = 60K, R g = 0 :
Av (booster) = (6.2K/3.1K) + 1 = 3
Av (composite) = 60K/2K = 30
Av (driver) = 30/3 = 10
t

=

1
0
0
m
s
s
t
e
a
d
y

s
t
a
t
e

T
C
=

2
5
C
s
t
e
a
d
y

s
t
a
t
e

T
C
=

8
5
C
s
t
e
a
d
y

s
t
a
t
e

T
C
=

1
2
5
C
3
2
1
.2
.3
.4
.5
10 20 30 40 50 100 200 300
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

o
r

V
S

(
A
)
S
V
O
(V)
.1
SOA
OP
AMP
PB58
C
F
R
F
R
I
+15V
15V
IN
COM
+Vs
Vs
R
CL
OUT
C
C
R
G
R
L
V
IN
GAIN
COMP
C
CH
Eval Kits 521
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Evaluation Kits
KIT SUPPORTED PART(s)
EK01 .........................................SA01 .............................................................................. 522
EK03 .........................................SA03 .............................................................................. 526
EK06 .........................................SA60 .............................................................................. 529
EK07 .........................................SA07 .............................................................................. 531
EK09 .........................................CE (TO-3), CR, CU, DC, DD (MO-127) Packages ......... 534
EK11 .........................................PA90, PA91, PA98.......................................................... 537
EK13 .........................................PA241DF ........................................................................ 539
EK14 .........................................PA13, PA16 .................................................................... 541
EK15 .........................................SA08 .............................................................................. 543
EK16 .........................................PA90, PA91, PA92, PA93, PA98 .................................... 546
EK17 .........................................SA12 .............................................................................. 550
EK19 .........................................PA94, PA95 .................................................................... 553
EK21 .........................................PA74 ............................................................................... 555
EK26 .........................................PA60EU .......................................................................... 559
EK27 .........................................PA50, PA52 .................................................................... 561
EK28 .........................................PA97DR ......................................................................... 564
EK29 .........................................PB51 .............................................................................. 566
EK33 .........................................PA75CX .......................................................................... 569
EK34 .........................................PA240CX ........................................................................ 571
EK42 .........................................PA15FL, PA241DW ........................................................ 573
EK50 .........................................PB50, PB58.................................................................... 574
EK51 .........................................DF Packages (24-pin PSOP) ......................................... 576
EK52 .........................................MP230, MP240 .............................................................. 578
EK56 .........................................MSA240, MSA260.......................................................... 582
EK57 .........................................MP108, MP111 ............................................................... 586
EK59 .........................................MP38, MP39 .................................................................. 590
EK60 .........................................PA78EU .......................................................................... 594
EK61 .........................................PA78DK, PA79DK .......................................................... 597
EK65 .........................................MP400 ............................................................................ 600
EK71 .........................................PA107DP ........................................................................ 604
EK-SA50 ...................................SA50CE ......................................................................... 608
DB53R ......................................SA53-IHZ ....................................................................... 609
DB63R ......................................SA57-IHZ ....................................................................... 614
DB64R ......................................SA306-IHZ ..................................................................... 619
DB303R ....................................SA303-IHZ ..................................................................... 624
Evaluation Kits Evaluation Kits
EK01
522 EK01U
EK01 SA01
INTRODUCTION
This easy-to-use kit provides a platform for the evaluation of
PWM amplifers using the SA01 pin-out confguration. It can be
used to analyze a multitude of standard or proprietary circuit
confgurations, and is fexible enough to do most standard
amplifer test confgurations. The board is designed for surface
mounting all components except the switching amplifer.
The schematic is shown in Figure 2. Note that all of the
components shown on the schematic will probably not be used
for any single circuit. Some components will simply be omitted,
while others require installation of a jumper to complete the
signal path.
Only components unique to the EK01 are provided in this kit.
Hardware similar to that shown in fgure 1 must be obtained lo-
cally. The PC board and the foot print of the heatsink measure
3" by 5".
PARTS LIST
Part # Description Quantity
HS16 Heatsink 1
MS04 PC mount Cage Jacks 1 Bag/12 each
ASSEMBLY
1. From the non-silk screen side, insert and solder cage jacks.
Be sure each one is fully seated.
2. From the non-silk screen side, push spacer grommets into
PC board until fully seated. Grommets will snug when screws
are inserted for heatsink mounting.
3. Apply TW10 thermal washer or a thin, even coat of thermal
grease to the bottom of the SA01. If grease is from a tube
make sure there is no sign separation of solids and liquids.
If from a jar, stir it prior to application.
4. Use #14 sleeving to insulate and align at least 2 opposite
pins of the amplifer.
5. Mount amplifer to heatsink using #6 screws and nuts. Do
not over torque.
6. Install components as needed. External connections may be
soldered directly or standard banana jacks may be soldered
to these pads.
7. Insert amplifer pins into cage jacks and fasten board to
heatsink.
EVAL07 PC Board 1
60SPG00001 Spacer Grommets 4
TW10 Thermal Washer 1 Box/10 each
BEFORE YOU GET STARTED
* All Apex Precision Power amplifers should be handled using proper ESD precautions.
* Always use the heatsink included in this kit with thermal grease.
* Torque the part to the specifed 8 to 10 in-lbs (.9 to 1.13 N*M)
* Always use adequate power supply bypassing.
* Do not change connections while the circuit is powered.
* Initially set all power supplies to the minimum operating levels allowed in the device data sheet.
* Check for oscillations.
Heatsink
Switching Amplifier
Hex Nut 6-32 THD 1/4"
#8 or #10 Screw (1/2" - 3/4" LG)
Spacer Grommet
6-32 x 1/2 Lg. Screw
TW10 thermal washer or
thermal grease as required
PC Board (Silkscreen side)
Cage Jack
Solder as required
FIGURE 1.
Evaluation Kit for SA01 Pin-Out
EK01 P r o d u c t I n n o v a t i o n F r o m
MAY 2009
APEX EK01UREVF
EK01
EK01U 523
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TYPICAL COMPONENT FUNCTIONS
R1 Provides -IN bias from the Reference voltage.
R2 Sets DC scaling for external feedback such as tachometers, position sensors or current sensors.
R3 With R4 sets DC operating point of +IN, with R13 and R15 sets gain of voltage feedback circuit.
R4 With R3 sets DC operating point of +IN.
R5 Input scaling of the control signal.
R6 With C6 sets the corner frequency of the integrator.
R7 With C3 & C4 forms a low pass flter for the external feedback loop. Often used with tachometers.
R8 With C2 forms a low pass flter for the current limit circuit.
R9 Current sense. Often is a piece of resistance wire.
R10 With R8 divides shutdown signal voltage feeding SHDN/FILTER pin.
R11 With C5 sets corner frequency for external feedback loop.
R12, 13, 15, 16 Provides voltage feedback for a voltage controlled output.
R14 Helps set gain or scale input voltage levels.
R17 With C12 provides low pass fltering of +IN signal.
C1 Power supply bypass.
C2 With R8 form a low pass flter for the current limit circuit, also flters the SHDN signal.
C3, 4 With R7 forms a low pass flter for the external feed back loop. Often used with tachometers.
C5 With R11 sets corner frequency for external feedback loop.
C6 With R6 sets the corner frequency of the integrator.
C7 Power supply bypass, must have very low ESR in MHz range.
C8 Filters reference or feedback voltage at +IN.
C9 Bypass for the reference voltage.
C10, 11 With R15 and R16 provides low pass fltering of voltage feedback.
C12 With R17 provides low pass fltering of +IN signal.
C13 Provides AC coupling of +IN signal.
D1 D4 Optional fyback diodes.
D5 D7 Input protection zener diodes.
FIGURE 2. PCB SCHEMATIC.
EA
PWM
+V
S
EA
OUT
IN
7.5V
REF
+IN
GND
SHDN/
FILTER
I
SENSE
A
OUT
B
OUT
SA01
1
5
2
3 7
6
9
4 8 10
+V
S
A
OUT
B
OUT
GND
C2
R13 R15
R16
C8
R4
R17
C9
C13
R14
R1
R5
C3
R7
C4
R11
C5
R2
R6
C6
C1
D4
C7
R12
R3
R8 R9
SHDN
SIG
TACH/
FEEDBACK
SIG
IN
REF
OUT
GND
+IN
R10
C10
C11
C12
D1
D5
11V
D2
D3
D7
11V
D6
11V
EK01
524 EK01U
FIGURE 3. PCB
C5
R7
D3
10
D1
A OUT
GND
+Vs
D2
C7
C1
R
1
5
D4
R
1
6
SA01
R
8
C11
C9
C12
R13
C6
R
3
R6
R17
OUT
SHDN
B
C10
R10
EVAL07 R-C
C2
R12
R9
R14
1
C4
R11
REF
OUT
R1
R4
C13
C8
R5
+IN
GND
-IN
TACH
C3
R2
SIG
TOP SIDE
BOTTOM SIDE
5.00
3.00
M I C R O T E C H N O L O G Y
OPEN LOOP OPERATION
EA
PWM
+V
S
EA
OUT
IN
7.5V
REF
+IN
GND
SHDN/
FILTER
I
SENSE
A
OUT
B
OUT
SA01
1
5
2
3 7
6
9
4 8 10
+V
S
A
OUT
IN
+2.5/+7.5
B
OUT
GND
C2
R10
C9
R17
C12
C1
C6 R6
C7
R8 R9
SHDN
SIG
REF
OUT
V
IN
Duty Cycle @ A
OUT
2.5V 0%
5V 50%
7.5V 100%
V
IN
5
2.5
(A B) =
*
V
S

I
O *
R
DSON

EK01
EK01U 525
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EA
PWM
+V
S
EA
OUT
IN
7.5V
REF
+IN
GND
SHDN/
FILTER
I
SENSE
A
OUT
B
OUT
SA01
1
5
2
3 7
6
9
4 8 10
+V
S
A
OUT
B
OUT
GND
C2
R10
C8
R4
C9
R1
R17
R5
C3
R7
C4
R11
C5
R2
R6 C6
C1 C7
R3
R8 R9
SHDN
SIG
TACH/
FEEDBACK
SIG
REF
OUT
+IN
M T
EA
PWM
+V
S
EA
OUT
IN
7.5V
REF
+IN
GND
SHDN/
FILTER
I
SENSE
A
OUT
B
OUT
SA01
1
5
2
3 7
6
9
4 8 10
+V
S
A
OUT
B
OUT
GND
C2
R10
C8
R4
C9
R1
R5
R7
R11
R17
C5
R2
R6 C6
C1 C7
R3
R8 R9
SHDN
SIG
TACH/
FEEDBACK
SIG
REF
OUT
+IN
+REF
REF
M
POSITION CONTROL
VOLTAGE CONTROL
SPEED CONTROL
EA
PWM
+V
S
EA
OUT
IN
7.5V
REF
+IN
GND
SHDN/
FILTER
I
SENSE
A
OUT
B
OUT
SA01
1
5
2
3 7
6
9
4 8 10
+V
S
A
OUT
B
OUT
GND
C2
R10
R13
C8
R4
C9
R1
R
O
R
O R
I
R
F
R
F
R5
R17
R6 C6
C1 C7
R12
R3
R8 R9
SHDN
SIG
SIG
REF
OUT
R
F
R
I
(A B) = V
IN

*

R15
R16
C10
C11
EK03
526 EK03U
EK03 SA03
INTRODUCTION
amplifer test confgurations. The board is designed for surface
mounting all components except the switching amplifer.
for any single circuit. Some components will simply be omit-
ted, while others require installation of a jumper to complete
the signal path.
Only components unique to the EK03 are provided in this
kit. Hardware similar to that shown in fgure 1 must be ob-
tained locally.
PARTS LIST
HS18 Heatsink 1
EVAL09 PC Board 1
OX7R105KWN 1F Cap 1825B105K201N, 6
Novacap
ASSEMBLY
1. From the non-silk screen side, insert and solder cage jacks.
Be sure each one is fully seated.
2. From the non-silk screen side, push spacer grommets into
PC board until fully seated. Grommets will snug when screws
are inserted for heatsink mounting.
3. Apply TW05 thermal washer to the bottom of the amplifer.
5. Mount amplifer to heatsink using #6 screws and nuts. Torque
the part to the specifed 8 to 10 in-lbs (.9 to 1.13 N*M). Do
not over torque.
6. Install components as needed. External connections may be
soldered directly or standard banana jacks may be soldered
to these pads.
7. Insert amplifer pins into cage jacks and fasten board to
heatsink.
* All Apex Precision Power amplifers should be handled using proper ESD precautions.
* Always use the heatsink included in this kit with TW05 washer.
* Initially set all power supplies to the minimum operating levels allowed in the device data sheet.
Heatsink
Switching Amplifier
#8 or #10 Screw (1/2" - 3/4" LG)
Spacer Grommet
TW05 thermal washer
Cage Jack
Solder as required
FIGURE 1.
MAY 2009
APEX EK03UREVG
EK03
EK03U 527
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A block diagram of the amplifer is shown in Figure 2 along with
pcb connections of all the commonly used external components.
Your application circuit will not use all of the components. Add
those components required by your circuit. You may have to
jumper some components to make the desired electrical con-
nections. J1 is an optional way to connect the clock circuit.
Power supply bypassing is particularly important and that is
why high quality ceramic chip capacitors are supplied with
the kit. In addition you may need to add a 10-50 uF or larger
capacitor on the +Vs pin. This additional capacitor needs to
be rated for switching operation. Note that the signal ground
and power ground are separated and tie together only at the
ground pin (5). A breadboarding area is supplied which can
accomodate 1 or 2 IC amplifers and associated components.
The large terminal pads can be used to solder wire connec-
tions or banana jacks.
SA03
*
*
*
* Input protection, 10V zener diode.
SA03

The schematic of Figure 3 can be used to verify the func-
tionality of your amplifer and help you gain a familiarity with
proper operation. At either A Out or B Out, with respect to
ground, you should observe a square wave approximately 30
V in amplitude with a fxed frequency and duty cycle that varies
from approximately 0 to 100% at a rate of 1 Hz. The current
limit is set to 2 amps.
FIGURE 3. FUNCTIONAL TEST CIRCUIT
EK03
528 EK03U
FIGURE 4. PCB
1
12 7
CLK CLK
RAMP SHDN
R
E
V
-
B
E
V
A
L
0
9
-PWM/
EK03
SIG
GND
C1
GND
SIG
GND
SIG
GND
I SENSE B I SENSE A
CVcc CVs
R4
J1
R3
SPARE
ILIM/
+PWM
IN OUT
A OUT Vcc
PWR
R1
C3
B OUT
Rb
R2
Ra
C2
1
+Vs
5.500
4.686
TOP SIDE
BOTTOM SIDE
EK06
EK06U 529
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EK06 SA60
INTRODUCTION
Fast and easy breadborading of circuits using the SA60 are
possible with the EK06 evaluation kit. The amplifer may be
mounted vertically with the HS20 heat sink, or horizontally.
Connections are provided for required power supply bypassing
recommended protection components, as well as optional current
sense resistors. A large area for component mounting provides
fexibility and makes a multitude of circuit confgurations possible.
CAUTION
Use the supplied thermal washers or ther-
mal grease between the power amplifer
and the heat sink.
ASSEMBLY
1. On the silk screen side of the evaluation board, insert and
solder the MS06 mating socket in DUT holes 1 12. Be sure
each one is fully seated.
2. Solder components for your circuit. Be sure to include proper
bypassing. See the SA60 data sheet for help in selecting
these components. 1uF capacitors and a .10 resistor have
been included with the EK06 kit but may be replaced with
other components as necessary. C1, not provided, should
be selected for the voltage required by the application. See
Apex Precision Power Application Note 30 for guidelines in
selecting this bypass capacitor. If current sense resistors are
not used, the I SENSE traces on the EVAL11 board must be
shorted to power ground in place of the resistors.
3. Place the TW07 thermal washer on the heat sink over the
mounting hole for the DUT. Place a #6 screw through the
mounting hole and thread a #6 nut onto the screw at the back
of the heat sink. Do not tighten. Note that there are two sets
of mounting holes on the HS20). Holes on one edge allow
room between the DUT and evaluation board for the MS06
socket. The holes on the other edge are for direct through
hole mounting of the DUT to the evaluation board. It is rec-
ommended that you use the MS06.
4. Mount the DUT to the HS20 by sliding under the head of the
#6 screw and on top of the thermal washer. Tighten the nut
to the specifed 8 to 10 in-lbs. (.9 to .13 N*M). Do not over
torque.
5. Install leads of the DUT into the MS06 on the evaluation board.
Use #6 self-tapping screws to secure the evaluation board
to the HS20 heat sink as shown in the assembly diagram
(Figure 1).
PARTS LIST
HS20 Heatsink 1
EVAL11 PC Board 1
MS06 Mating Socket 1
OX7R105KWN 1F Ceramic Capacitor 2
CSR07 .1 1% Resistor 2
TWO7 Thermal Washer 1 package
HS22 Heatsink 2
All Apex Precision Power amplifers should be handled using
proper ESD precautions.
Always use the heat sink and thermal washers included in
this kit.
Always use adequate power supply bypassing.
Do not change connections while the circuit is powered.
Initially set all power supplies to the minimum operating levels
allowed in the device data sheet.
Check for oscillations.
Power ground and signal ground must be separated to avoid
switching noise in the DUT.
FIGURE 1.
MAY 2009
APEX EK06UREVD
EK06
530 EK06U
FIGURE 2.
E V A L 1 1
R E V - D
1
1 2
V C C
S I G N A L G N D
TOP SIDE
BOTTOM SIDE
5.50
3.00
IC
IC
1
DUT
+Vs B OUT GND
PWR
A OUT Vcc INPUT
PWM
INPUT
SIGNAL
GND
DISABLE
Vcc
ISENSE
B
A
Rsense A
Rsense B
12
ISENSE
G C M I O R T N E C H L O O
EVAL11
REV-D
+
C1
D1
D2
Y
SIGNAL
GND
EK07
EK07U 531
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EK07 SA07
INTRODUCTION
This easy-to-use kit provides a platform for the evaluation
of PWM amplifer circuits using the SA07 pin-out. With ample
breadboarding areas it is fexible enough to analyze a multitude
of standard or proprietary circuit confgurations. Critical con-
nections for power supply bypassing, compensation and current
limiting are pre-wired. Components not usually readily available
in engineering labs are provided. External connection to the
evaluation kit can be made via the terminals at the edge of the
circuit board. These terminal pads are suitable for standard
banana jacks or direct soldering of wires. The schematic is
shown in Figure 1.
ASSEMBLY
See Figure 3.

1. Solder the surface mount ceramic capacitors to the DUT side
of the circuit board at CVs and CVcc.
2. Select a current limiting resistor from the two values pro-
vided. See the product data sheet for
information on how to select a value.
Apply a thin coating of thermal grease
to the back of the resistors. Press the
resistor body onto the circuit board foil
at positions Ra and Rb and solder the
leads.
3. Assemble the amplifer, thermal washer
and heat sink to the circuit board as
illustrated in Figure 1. As a last step
push the clip through the heat sink and
circuit board until it locks. Solder the
amplifer pins to the circuit side of the
circuit board.
4. The four holes at the corners of the cir-
cuit board are for mounting #6 standoff
spacers if desired.
5. Add other components as necessary
to complete your application circuit.
* All APEX amplifers should be handled
using proper ESD precautions.
* Always use thermal grease between
the amplifer and heatsink.
* Always use adequate power supply
bypassing.
* Do not change connections while the
circuit is powered.
* Initially set all power supplies to the
minimum operating levels allowed in
the device data sheet.
L2 L1
FIGURE 1.
AUG 2009
APEX - EK07UREVD
PARTS LIST
Part # Description, Vendor Quantity
CLAMP02 Mounting clip, Apex 1
HS21 Heat sink, Apex 1
EVAL18 PC Board, Apex 1
TWO9 Thermal washer, Apex 1 Box/10 each
OX7R105KWN Capacitor, Novacap 2
1825B105K201N
CRS01 Resistor, Caddock 2
MP725-0.10-1%
CRS02 Resistor, Caddock 2
MP725-0.05-1%
Figure 1 shows the schematic of the evaluation kit's pre-wired
connections Components supplied with the kit are marked with
an asterisk (*). All other connections are made via the bread-
boarding areas of the circuit board.
EK07
532 EK07U
FIGURE 2.
Figure 2 shows a suggested simple test circuit that you
can build to gain a familiarity with the evaluation kit as well as
the amplifer. At the A OUT or B OUT pads relative to power
ground you should observe a square wave with a frequency of
approximately 500kHz, 30V p-p which is being modulated from
approximately 0 to 100 % duty cycle at a rate of 1 Hz.
EK07
EK07U 533
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B
A
5 V 2 4
+Vs A OUT OUT SHDN
SIG GND
3
B OUT Vcc
CLK
6
IN
Ilim/
5
CLK PWR
SPARE 1 SPARE 2
GND
GND
SIG
L1
CVs
L2
Vcc
C1
PWR
Rb
IC
Ra
IC
GND
18
EVAL18
1
BOT SIDE
APEX
CVcc
REF
TOP SIDE
EVAL18 R-B
G C M I O T
PWR
GND
SIG
L1 L2
IC
R C N E L O O H Y
1
2
18
REF
B OUT
5 V
3
+Vs
OUT
Vcc
4
A OUT
SHDN IN
5
CLK
6
SPARE 1
CLK Ilim/
GND
SPARE 2
C1
IC
TOP SIDE
BOTTOM SIDE
8.00
4.50
FIGURE 3. PCB
5 V 2 4
+Vs A OUT OUT SHDN
SIG GND
3
B OUT Vcc
CLK
6
IN
Ilim/
5
CLK PWR
SPARE 1 SPARE 2
GND
GND
SIG
L1
CVs
L2
Vcc
C1
PWR
Rb
IC
Ra
IC
GND
18
EVAL18
1
BOT SIDE
APEX
CVcc
REF
TOP SIDE
EVAL18 R-B
G C M I O T
PWR
GND
SIG
L1 L2
IC
R C N E L O O H Y
1
2
18
REF
B OUT
5 V
3
+Vs
OUT
Vcc
4
A OUT
SHDN IN
5
CLK
6
SPARE 1
CLK Ilim/
GND
SPARE 2
C1
IC
TOP SIDE
BOTTOM SIDE
8.00
4.50
EK09
534 EK09U
EK09 CE (TO-3), CR, CU,
DC, DD (MO-127) Packages
INTRODUCTION
This kit provides a solid mechanical platform with good shield-
ing and grounding to breadboard eight pin TO-3 packages or
the MO-127 package with 0.060" pins. This kit is not intended
as an alternate for kits dedicated to specifc amplifers. See
www.Cirrus.com for availability of dedicated kits.
Construction will involve surface mounting and 3D techniques.
Holes are provided to mount standard banana and BNC con-
nectors for I/O. See the Apex Precision Power Accessories
Information data sheet for a selection of fat-back heatsinks
and thermal washers for these packages.
Note that HS11 is compatible with EK09 and all three sockets
can be used if desired. If the EK09 is to be used as an MO-127
platform only, HS18 rated at 1 C/W is a cost effective alterna-
tive to HS11 if internal power dissipation permits. Lower cost
alternatives for two package TO-3 applications are HS02, HS01,
and HS09. For single package TO-3 applications the HS13 is
also suitable. The six chip capacitors provided can be used as
the critical frst step in power supply bypass for dual supplies
for all three sockets. These capacitors are rated at 200V.
PARTS LIST
PB99-P2 top 1
PB99- P6 side 2
PB99-P7 side 2
MS02 cage jacks for one TO-3 socket 2
MS04 cage jacks for one MO-127 socket 1
OX7R105KWN 1F Cap 1825B105K201N,Novacap 6
Attempt to visualize the fnished circuit mechanically and in
terms of where the high currents fow.
Use proper ESD precautions.
Verify heatsink is adequate
Use thermal grease or Apex Precision Power thermal washer.
Do not make or break any connection on a hot circuit.
Start with lowest rated voltages.
Checking for oscillations with an oscilloscope is a must.
ASSEMBLY
Let us defne the side of the top board with solder pads for
each pin (roughly triangular on the TO-3 sockets) as the com-
ponent side, where all the support components will determine
circuit function and will be inside the fnished box. The other
side of this board is hereby dubbed the amplifer side.
Insert cage jacks from the amplifer side and solder. Consider
one of these techniques: 1) Place cage jacks in holes, cover
with one of the 6" copper sides, fip over and solder, or 2) place
cage jacks on pins of the amplifer, insert and solder. If done
carefully, technique 2 can be used for the MO-127 package
with 0.040" leads.
Starting with one short and one long side, locate a vertical
square corner in your work area (a large heatsink standing
on end works fne) and solder the two together. Repeat for
the other two sides, and fnally solder the two pairs together.
With the component side up , place rectangle of sides on top
and tack two opposite corners. When satisfed with alignment,
solder the box together then add connectors and components
as desired.
Note that copper on the inside and on the top of the box will
all be tied to ground. Copper on the four outer sides of the box
will be foating unless you tie them down.
Soldering a stranded #10 to #16 ground wire from the im-
mediate area of the socket(s) to the ground connector of the
power supply(ies) is good construction practice. If the circuit
is not a bridge, run this same size wire from the socket area
to the output return connector. This will avoid high currents in
the ground plane which may destroy signal integrity or even
an amplifer. This is a good time to think about star grounding
where each ground connection has a dedicated path to the
center of the star such that currents in any path are not capable
of inducing voltage in any other path.
Note that the layout makes it easy to locate the star center
nearly coincident with the socket center.
Auxiliary circuits may be mounted inside the box in 3-D fash-
ion supported on ground connections or on daughter boards
as convenient. Other style connectors, switches or indicators
can easily be added by simply drilling the appropriate holes
and mounting them.
Evaluation Kit for TO-3 and MO-127 Packages
MAY 2009
APEX EK09UREVE
EK09
EK09U 535
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FIGURE 1. COMPONENTS INCLUDED IN EK09.
5"
1.75"
1.75"
6"
Amplifier side
Component side
1 1
1 1
2 MS02,16 CAGE JACKS FOR TWO TO-3 SOCKETS
MS04,12 CAGE JACKS FOR ONE MO-127 SOCKET
OX7R105KWN, 6 CAPACITORS, 1F, 200V
EK09
536 EK09U
.
Figure 2.
External with heatsink (heatsink, amplifer, con-
nectors and switches not supplied).
Figure 4.
Socket detail shows the center of the star ground
system is right in the center of the socket.
Figure 3.
Inside of assembled box. Holes for components
on long side were user drilled.
EK11
EK11U 537
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EK11 PA90, PA91, PA98
INTRODUCTION
of linear power amplifers circuits using the PA91 pin-out. With
ample breadboarding areas it is fexible enough to analyze a
multitude of standard or proprietary circuit confgurations. Criti-
cal connections for power supply bypassing, compensation and
current limiting are pre-wired. Components not usually readily
available in engineering labs are provided. External connection
to the evaluation kit can be made via the terminals at the edge
of the circuit board. These terminal pads are suitable for stan-
dard banana jacks or direct soldering of wires. The schematic
is shown in Figure 1.
PARTS LIST
HS27 Heatsink, Apex Precision Power 1
EVAL24 PC Board, Apex Precision Power 1
TW07 Thermal Washer, 1 box, 10 ea.
P6KE250A Transient Zener, 2
Microsemi (250V)
CDC01 Capacitor .01F 1kV, 2
Sprague 5GAS10
ASSEMBLY
1. See Figure 2. Insert and solder the transient zener diodes
at D3 and D4 (250V).
2. Insert and solder the disc bypass capacitors at C1 and C2.
3. Insert the HS27 heatsink and solder the solderable studs
from the opposite side of the PCB.
FIGURE 1.
Figure 1 shows the schematic of the
evaluation kit's pre-wired connections.
Components supplied with the kit are
marked with an asterisk (*). See the
amplifer's data sheet for full application
information.
R
C4
C1*
C2*
AUX1 AUX2 IN1 IN2 OUT -VS +VS
1
R
LIM
R
2
R
3
D3*
C
C
J1
D2 D1
R
C
GND
250V
D4*
250V
1
4
5
7, 8
6
11, 12
9, 10
2
PA91
4. Add banana jacks as necessary to complete connections to
external circuits and power supplies.
5. Insert the amplifer into the PCB mounting holes located in
the space between the heatsink fns. So not solder the pins
at this time.
6. Hang the TW07 thermal washer near the end of a 6-32 X
3/8" screw. Slightly pull the amplifer away from the heat sink
face. Use the screw to position the thermal washer behind
the amplifer and insert the screw into the mounting hole of
the heatsink. Use a 6-32 nut to secure the screw from the
opposite side of the heatsink. It is important that the entire
back surface of the amplifers mounting tab be in contact
with the heatsink. Adjust the amplifers position and tighten
the mounting screw as necessary for this to be so.
7. Solder the amplifers pins to the PCB.
8. Add other passive components as necessary to complete
your circuit.
9. Most common confgurations will ground the non-inverting pin
of the amplifer. J1 is a convenient way to do this if necessary
for your application circuit.
10. The four holes at the corners of the circuit board are for
mounting #6 standoff spacers if desired.
11. R1-R3 are multiple feedback resistors in series. Commonly
available resistors do not have a breakdown voltage sufficient
to stand off the output voltage of the amplifer. Using multiple
resistors will divide down the voltage that each resistor must
withstand.
Evaluation Kit for PA90, PA91, PA98
MAY 2009
APEX EK11UREVE
EK11
538 EK11U
1
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1 2
DANGER
HIGH VOLTAGE
IC
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-
V
s
+
V
s
I
N

2
I
N

1
G
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2
A
U
X

1
D3
D4
GND
HS27
COMPONENT & DUT SIDE
EVAL24 R-A
1
MICROTECHNOLOGY
12
1
C2 Cc
Rc
R1 R2
R
C4
R3
D1
D2
GND J1
LIM
C1
TOP SIDE
BOTTOM SIDE
4.65
3.37
FIGURE 2. PCB
EK13
EK13U 539
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EK13 PA241DF
INTRODUCTION
Fast and easy breadboarding of circuits using the PA241DF
IS possible with the EK13 evaluation kit. The amplifer may
be surface mounted directly to the PC board. The PA241DF
is soldered to a 2-square inch area of foil on the PC board for
heat sinking. This foil heat sink is connected toVs. Connec-
tions are provided for required power supply bypassing, phase
compensation components, and a current limit resistor. A large
area for component mounting provides fexibility and makes a
multitude of circuit confgurations possible.
PARTS LIST
EVAL15 PC Board 1
HS24 Heatsink 1
High voltages will be present. Use caution in
handling and probing when power is applied.
CAUTION
BOTTOM
DUT SIDE
3.50
4.25
ASSEMBLY
The PA241DF is a surface mount device and should be
assembled to the EVAL15 PC board using surface mount pro-
cesses. Solder paste may be dispensed or screen-printed on the
DUT pads. The heat tab on the back of the PA241DF provides
maximum heat dissipation capabilities when soldered to the
PCB metalization that runs under the DUT on the DUT side of
the board. Solder should be applied here also. For prototype
purposes, the tab can be thermally connected to the PCB met-
alization using thermal grease.
The PA241DF and HS24 should be refowed to the PCB
using a solder refow furnace. If this is not available, a heat
plate capable of solder refow temperatures may be used. or,
though time consuming, the leads may be soldered individually
to the PCB with a soldering iron. In this case the use of thermal
grease under the heat tab is recommended instead of solder
for the thermal connection.
Evaluation Kit for PA241DF
MAY 2009
APEX EK13UREVD
EK13
540 EK13U
TOP
COMP. SIDE
OPTIONAL NO. 6 HARDWARE NOT INCLUDED
HEATSINK HS24
CIRCUIT SIDE
SURFACE MOUNT TO PCB
PA241DF
EK14
EK14U 541
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EK14 PA13, PA16
INTRODUCTION
The EK14 evaluation kit provides a convenient way to bread-
board circuits using Apex Precision Power power op amps pack-
aged in the 12-pin SIP03 package. The amplifer may be mounted
vertically with the HS20 heat sink, or horizontally. Connections
are provided for required power supply bypassing, external
compensation components, as well as current limit resistors.
A large area for component mounting provides fexibility and
makes a multitude of circuit confgurations possible.
CAUTION
Use the supplied thermal washers or ther-
mal grease between the power amplifer
and the heat sink.
PARTS LIST
HS20 Heatsink 1
EVAL16 PC Board 1
CSR10 .15 Resistor 2
TWO7 Thermal Washer 1 package
this kit.
ASSEMBLY
solder the MS06 mating socket in DUT holes 1 12. Be sure
2. Solder components for your circuit. Be sure to include proper
bypassing, required compensation components and current
limit resistors. See the op amp data sheet for help in select-
ing these components. 1uF capacitors and a .15 resistor
have been included with the EK12 kit but may be replaced
with other components as necessary.
mounting hole and thread a #6 nut onto the screw at the
back of the heat sink. Do not tighten. Note that there are
two sets of mounting holes on the HS20. Holes on one edge
allow room between the DUT and evaluation board for the
MS06 socket. The holes on the other edge are for direct
through hole mounting of the DUT to the evaluation board.
It is recommended that you use the MS06.
to the specifed 8 to 10 in-lbs. (.9 to .13 N*M). Do not over
torque.
5. Install leads of the DUT into the MS06 on the evaluation board.
Use #6 self-tapping screws to secure the evaluation board
to the HS20 heat sink as shown in the assembly diagram
(Figure 1).
Evaluation Kit for DP Package Op Amps
MAY 2009
APEX EK14UREVC
EK14
542 EK14U
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3.00
TOP SIDE
BOTTOM SIDE
COMPONENT SIDE
EVAL16 R-A
G C MI O R T N ECH L O O Y
SPARE SPARE GND -IN +IN
IC
IC
-Vs
1
DUT
C2 C1
+Vs
OUTPUT
O
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P
U
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C3
C4
+
+
-Vs GND+Vs
RLIM
1
RLIM
2
12
GND
FIGURE 1. PCB
EK15
EK15U 543
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EK15 SA08
INTRODUCTION
amplifer test confgurations.
the signal path.
kit. Hardware similar to that shown in Figure 1 must be ob-
tained locally.
PARTS LIST
Apex Part # Description Quantity
HS18 Heatsink 1
EVAL19 PC Board 1
ZX7R105KTL 1F Cap ST2225B105K501LLXW 2
Novacap
OX7R105KWN 1F Cap 1825B105K201N, 1
Novacap
TS01 Terminal Strip 66505 1
Beau Interconnect
EC01 470 f Cap 1
United Chemi-Con
82DA471M500MG2D
HS22 Heatsink 2
Thermolly 6025B
CSR03 0.010 ohm resistor 2
Caddock MP916-0.010 - 5%
Caddock MP930-0.020 - 5%
FIGURE 1.
* All Apex Precision Power amplifers should be handled using
* Always use the heatsink included in this kit with TW05
washer.
* Initially set all power supplies to the minimum operating
levels allowed in the device data sheet.
MAY 2009
APEX EK15UREVC
EK15
544 EK15U
ASSEMBLY
During assembly refer to Figure 1 and
Figure 2.
1. From the DUT of the PCB insert and
solder the 12 cage jacks. Also solder
the cage jacks from the circuit side
as well, making sure the cage jack
remains fush with the component side
of the PCB.
2. Solder the 3 surface mount ceramic
capacitors to the component side of
the PCB.
3. From the component side of the PCB
insert the terminal strip. Solder from
the circuit side of the PCB. Be sure that
the GND terminal hole in the PCB is
fully flled with solder.
4. Two values of current limiting power
resistors are supplied. Select one
value (see the amplifer data sheet to
learn how to calculate which resistor
will suit your need). Coat the backside
of the power resistor with heat sink
compound (not supplied). Using 4-40
screws and nuts (not supplied) mount
the resistors to the two small heat sinks
supplied. Solder the resistor/heat sink
assembly to the component side of the
PCB.
5. Insert the electrolytic capacitor into
the PCB from the component side and
solder from the circuit side making sure
to fll the mounting holes with solder.
6. From the circuit side, push spacer
grommets into PCB until fully seated.
Grommets will snug when screws are
inserted for heatsink mounting.
7. Apply TW05 thermal washer to the
bottom of the amplifer.
8. Use #14 sleeving to insulate and align
at least 2 opposite pins of the amplifer.
9. Mount amplifer to heatsink using #6
screws and nuts. Torque the part to
the specifed 8 to 10 in-lbs (.9 to 1.13
N*M). Do not over torque.
10. Install components as needed. Ex-
ternal connections may be soldered
directly or standard banana jacks may
be soldered to the large pads at the
edge of the PCB.
11. Insert amplifer pins into cage jacks
and fasten PCB to heatsink.
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1 6
COMPONENT SIDE
EVAL19 R-C
+Vs
1
C1
Ra
R2
Rb
PWR
C3
R1
SIG
+PWM FLAG
J1
R4
C
V
s
1
C
V
c
c
GND
GND
SIG
A OUT
CVs3
C
V
s
2
+
B OUT
GND
Vcc
SPARE SPARE
SIG
GND
Vcc
RAMP/-PWM
C2
OR
IC
IC
SHDN
TB1
6
12 7
+
G C M I O R T N E C H L O O Y
R3
D1
TOP SIDE
BOTTOM SIDE
5.500
4.686
FIGURE 2. PCB
EK15
EK15U 545
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A block diagram of the SA08 is shown in Figure 2 along with
pcb connections of all the commonly used external components.
Your application circuit will not use all of the components. Add
those components required by your circuit. You may have to
jumper some components to make the desired electrical connec-
tions. J1 is an optional way to connect the clock circuit. Power
supply bypassing is particularly important and that is why high
quality ceramic chip capacitors are supplied with the kit. In ad-
dition, a large electrolytic capacitor is included. This capacitor
was selected expressly for this evaluation kit and may not be
(and likely won't be) suitable for your end application. You will
need to select an electrolytic capacitor based on your analysis
of the capacitor's ripple current, ripple current tolerance, operat-
ing temperature, operating voltage, acceptable service life and
acceptable supply ripple. Note that the signal ground and power
ground are separated and tie together only at the ground pin (5).
A breadboarding area is supplied which can accomodate 1 or
2 IC amplifers and associated components. The large terminal
pads can be used to solder wire connections or bannana jacks.
SA08
+PWM
1 2 3 4 5 6
12 11 10 9 8 7
SIG
GND
PWR
GND
RAMP/-PWM
OR
FLAG
I
LIM
/SHDN
C3
R3
C2 C1
R4
J1
CLK IN CLK OUT + PWM FLAG
5V
10V
CLOCK
A OUT Vcc + Vs B OUT
B OUT A OUT Vcc + Vs I SENSE A I SENSE B
H
BRIDGE
DRIVER
Ra
R2
R1
CVcc
CVs1-3
5V
10V
.1V
10V
1k
1000pf
50k
Vcc
50 910
.01F
56k
5V
GND I
Lim
/SHDN
f/2 TL
470pF
D1
ground, you should observe a square wave approximately 30
V in amplitude with a fxed frequency and duty cycle that varies
from approximately 0 to 100% at a rate of 1 Hz. The current
limit is set to 2 amps.
SA08
CLK IN CLK OUT + PWM FLAG GND
5V
+PWM SIG
GND
PWR
GND
RAMP/-PWM
OR
FLAG
I
LIM
/SHDN
J1
C
L
O
C
K
C1
.01F
C3
.1F
1 Hz SDNE WAVE
+3/+7 V AMPLITUDE
VALLEY TO PEAK
10V
56k
5V
f/2 TL 470pF
I
Lim
/SHDN
H

B
R
I
D
G
E

D
R
I
V
E
R
1k
1000pf
50k
Vcc
50 910
.01F
5V
10V
.1V
10V
12 11 10 9 8 7
DUMMY LOAD
Ra
.1 OHM
R2
5k
R1
5k
CVcc
1F
CVs1-3
50 OHM 25 WATT
Rb
.1 OHM
30V HIGH
AMP
SUPPLY
15V
200 mA
SUPPLY
50
5K
D1
1 2 3 4 5 6
EK16
546 EK16U
EK16 PA90, PA91, PA92, PA93, PA98
INTRODUCTION
This easy-to-use kit provides a platform for the evaluation of linear power amplifers circuits using the PA90/PA91/
PA92/PA93/PA98 pin-out. With ample breadboarding areas it is fexible enough to analyze a multitude of standard
or proprietary circuit confgurations. Critical connections for power supply bypassing, compensation and current
limiting are pre-wired. Components not usually readily available in engineering labs are provided. External con-
nection to the evaluation kit can be made via the terminals at the edge of the circuit board. These terminal pads are
suitable for standard banana jacks or direct soldering of wires. The schematic is shown in Figure 2.
PARTS LIST
HS23 Heatsink, Wakefeld 232-200AB 1
MS06 Mating Socket Strip, Apex Precision Power 1 bag, 2 ea.
TW07 Thermal Washer, Apex Precision Power 1 box, 10 ea.
ZX7R105KTL Capacitor, NOVACAP ST2225K501LLXW 2
EC02 Capacitor, United Chemicon KME400VB33RM16X31LL 2
CSR05 Resistor, Caddock MP930-0.30 1% 1
ASSEMBLY
1. See Figure 1. Solder the surface mount ceramic capacitors to the DUT side of the circuit board at C1 and C2.
2. Solder the electrolytic capacitors to the circuit board at C3 and C4. Match the polarity markings on the circuit
board with those on the capacitor body.
3. Select a current limiting resistor from the three values provided. See the product data sheet for information on
how to select a value. Apply a thin coating of thermal grease to the back of the resistor. Using a 4-40 X 1/4"
screw and 4-40 nut, mount the resistor to the lower of the two holes in the small heat sink provided. Solder this
assembly to the circuit board at R
LIM
. After soldering the resistor leads the tabs on the heat sink may be bent with
pliers to secure it to the circuit board.
4. Examine the large heat sink. Notice that there are several holes in the face of the heat sink. These are for
mounting various Apex Precision Power amplifer models. The circuit board aligns the amplifer with the correct
mounting hole once the heat sink is attached to the circuit board. The heat sink can be mounted in either of two
positions. One position is used for mounting the amplifer to the heat sink without the mating socket strip (the
mounting hole of the amplifer is closer to the circuit board). Rotating the heat sink 180 degrees allows mounting
the amplifer with the mating socket strip (the mounting hole of the amplifer is further from the circuit board).
5. While developing your application circuit you will probably want to use the mating socket strip. Clip off the strip
after the 12th position. Insert the strip into the circuit board from the DUT side and solder one pin on the reverse
side. Check that the mating socket strip is fully seated against the circuit board then solder the remaining pins.
Insert the amplifer fully into the mating socket strip, noting the pin 1 locations on the amplifer and the circuit
board.
6. The four holes at the corners of the circuit board are for mounting #6 standoff spacers if desired. The remaining
two slotted holes are for mounting the large heat sink to the DUT side of the circuit board. Temporarily mount the
heat sink with 2 #6 X 1/2" self tapping screws from the opposite side of the circuit board. Do not fully tighten the
screws at this time. Check for alignment of the slot in the mounting tab of the amplifer with a hole in the heat
sink. Dismount and rotate the heat sink if necessary to achieve an alignment with a hole in the heat sink. Posi-
tion the heat sink so that the back of the amplifer mounting tab is fush with the heat sink then tighten the heat
sink mounting screws.
Evaluation Kit for
PA90/PA91/PA92/PA93/PA98 Pin-Out
JAN 2009
APEX EK16REVF
EK16
EK16U 547
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FIGURE 1.
7. Hang the thermal washer near the end of a 6-32 X 1/2" screw. Slightly pull the amplifer away from the heat sink
face. Use the screw to position the thermal washer behind the amplifer and insert the screw into the mounting
hole of the heat sink. Secure the screw from the opposite side of the heat sink using a nut holder.
8. Add other components as necessary to complete your application circuit.
EK16
548 EK16U
FIGURE 2.
Figure 2 shows the schematic of the evaluation kit's pre-
wired connections. Components supplied with the kit are
marked with an asterisk (*). All other connections are
made via the bread-boarding areas of the circuit board.
COMPONENTS SUPPLIED WITH EVALUATION KIT.
FIGURE 3.
Figure 3 shows a suggested simple test circuit that you
can build to gain a familiarity with the evaluation kit as
well as the amplifer. At the output (pin 6) you should
observe a 100 V p-p sine wave.
*COMPONENTS SUPPLIED WITH EVALUATION KIT.
EK16
EK16U 549
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EVAL20
APEX
1
12
CIRCUIT SIDE
GND
EVAL20 R-A
G C M I O R T N E C H L O O
+IN
OUTPUT
GND +Vs
IC
IC
-IN -Vs
R
C1
DRIVE
Cc
Rc
C2
GND
SPARE SPARE SPARE
OUTPUT
DRIVE
GND
+
+
-
-
C3 C4
+
1 12
LIM
-
Y
TOP SIDE
BOTTOM SIDE
5.50
2.87
FIGURE 4. PCB
EK17
550 EK17U
EK17 SA12
INTRODUCTION
amplifer test confgurations.
the signal path.
kit. Hardware similar to that shown in Figure 1 must be ob-
tained locally.
* Always use the heatsink included in this kit with TW05
washer.
* Initially set all power supplies to the minimum operating
PARTS LIST
HS18 Heatsink 1
EVAL19 PC Board 1
OX7R105KWN 1F Cap 1825B105K201N, 3
Novacap
TS01 Terminal Strip 66505 1
Beau Interconnect
EC03 680 f Cap 1
United Chemi-Con
KMH200VN68IM25X40T2
HS22 Heatsink 2
Thermolly 6025B
Caddock MP916-0.010 - 5%
Caddock MP930-0.020 - 5%
FIGURE 1.
Evaluation Kit for SA12 PWM Amplifier
MAY 2009
APEX EK17UREVG
EK17
EK17U 551
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ASSEMBLY
During assembly refer to Figures 1 & 2
1. From the DUT of the PCB insert and
solder the 12 cage jacks. Also solder
the cage jacks from the circuit side
as well, making sure the cage jack
remains fush with the component side
of the PCB.
2. Solder the 3 surface mount ceramic
capacitors to the component side of
the PCB.
3. From the component side of the PCB
insert the terminal strip. Solder from the
circuit side of the PCB. Be sure that
the GND terminal hole in the PCB is
fully flled with solder.
4. Two values of current limiting power
resistors are supplied. Select one
value (see the amplifer data sheet to
learn how to calculate which resistor
will suit your need). Coat the backside
of the power resistor with heat sink
compound (not supplied). Using 4-40
screws and nuts (not supplied) mount
the resistors to the two small heat sinks
supplied. Solder the resistor/heat sink
assembly to the component side of the
PCB.
5. Insert the electrolytic capacitor into
the PCB from the component side and
solder from the circuit side making sure
to fll the mounting holes with solder.
6. From the circuit side, push spacer
grommets into PCB until fully seated.
Grommets will snug when screws are
inserted for heatsink mounting.
7. Apply TW05 thermal washer to the
bottom of the amplifer.
8. Use #14 sleeving to insulate and align
at least 2 opposite pins of the amplifer.
9. Mount amplifer to heatsink using #6
screws and nuts. Torque the part to
the specifed 8 to 10 in-lbs (.9 to 1.13
N*M). Do not over torque.
10. Install components as needed. Ex-
ternal connections may be soldered
directly or standard banana jacks may
be soldered to the large pads at the
edge of the PCB.
11. Insert amplifer pins into cage jacks
and fasten PCB to heatsink.
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COMPONENT SIDE
EVAL19 R-C
+Vs
1
C1
Ra
R2
Rb
PWR
C3
R1
SIG
+PWM FLAG
J1
R4
C
V
s
1
C
V
c
c
GND
GND
SIG
A OUT
CVs3
C
V
s
2
+
B OUT
GND
Vcc
SPARE SPARE
SIG
GND
Vcc
RAMP/-PWM
C2
OR
IC
IC
SHDN
TB1
6
12 7
+
R3
D1
TOP SIDE
BOTTOM SIDE
5.500
4.686
FIGURE 2. PCB
EK17
552 EK17U
A block diagram of the SA12 is shown in Figure 3 along with pcb
connections of all the commonly used external components. Your
application circuit will not use all of the components. Add those
components required by your circuit. You may have to jumper
some components to make the desired electrical connections.
J1 is an optional way to connect the clock circuit. Power supply
bypassing is particularly important and that is why high quality
ceramic chip capacitors are supplied with the kit. In addition, a
large electrolytic capacitor is included. This capacitor was selected
expressly for this evaluation kit and may not be (and likely won't
be) suitable for your end application. You will need to select an
electrolytic capacitor based on your analysis of the capacitor's
ripple current, ripple current tolerance, operating temperature,
operating voltage, acceptable service life and acceptable supply
ripple. Note that the signal ground and power ground are sepa-
rated and tie together only at the ground pin (5). A breadboarding
area is supplied which can accomodate 1 or 2 IC amplifers and
associated components. The large terminal pads can be used
to solder wire connections or bannana jacks.
SA12
+PWM
1 2 3 4 5 6
12 11 10 9 8 7
SIG
GND
PWR
GND
RAMP/-PWM
OR
FLAG
I
LIM
/SHDN
C3
R3
C2 C1
R4
J1
CLK IN CLK OUT + PWM PWM
5V
10V
CLOCK
H
BRIDGE
DRIVER
Ra
R2
R1
CVcc
CVs1-3
5V
10V
.1V
10V
1k
1000pf
50k
Vcc
50 910
.01F
28.1k
5V
GND I
Lim
/SHDN
f/2 100pF
D1
ground, you should observe a square wave approximately
30 V in amplitude with a fxed frequency and duty cycle that
varies from approximately 0 to 100% at a rate of 1 Hz. The
current limit is set to 10 amps.
SA12
CLK IN CLK OUT + PWM FLAG GND
5V
+PWM SIG
GND
PWR
GND
RAMP/-PWM
OR
FLAG
I
LIM
/SHDN
J1
C
L
O
C
K
C1
.01F
C3
.1F
1 Hz SINE WAVE
+3/+7 V AMPLITUDE
VALLEY TO PEAK
10V
28.1k
5V
f/2 TL 100pF
I
Lim
/SHDN
H

B
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D
R
I
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E
R
1k
1000pf
50k
Vcc
50 910
.01F
5V
10V
.1V
10V
12 11 10 9 8 7
DUMMY LOAD
Ra
.02 OHM
R2
5k
R1
5k
CVcc
1F
CVs1-3
50 OHM 25 WATT
Rb
.02 OHM
30V HIGH
AMP
SUPPLY
15V
200 mA
SUPPLY
50
5K
D1
1 2 3 4 5 6
EK19
EK19U 553
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EK19 PA94, PA95
INTRODUCTION
linear power amplifers circuits using the PA94/PA95 pin-out. With
ample breadboarding areas it is fexible enough to analyze a
multitude of standard or proprietary circuit confgurations. Criti-
cal connections for power supply bypassing, compensation and
current limiting are pre-wired. Components not usually readily
available in engineering labs are provided. External connection
to the evaluation kit can be made via the terminals at the edge
of the circuit board. These terminal pads are suitable for stan-
dard banana jacks or direct soldering of wires. The schematic
PARTS LIST
TW13 Thermal Washer, 1 box, 10 ea.
P6KE440A TransZorb, General 2
Semiconductor (440V)
Sprague 5GAS10
ASSEMBLY
1. See Figures 2 & 3. Insert and solder the TransZorb diodes
at D3 and D4 (440V).
2. Insert and solder the disc bypass capacitors at C1 and
C2.
3. Insert the HS27 heatsink and solder the solderable studs
from the opposite side of the PCB.
R
C4
C1*
C2*
1
R
LIM
R
2
R
3
R
4
R
D3*
5
R
6
C
C
J1
D2 D1
R
C
GND
440V
D4*
440V
1
4
6
10
7
12
8
2
PA94/95
FIGURE 1.
Figure 1 shows the schematic of the
evaluation kit's pre-wired connections.
Components supplied with the kit are
marked with an asterisk (*). See the
amplifers data sheet for full application
information.
4. Add banana jacks as necessary to complete connections
to external circuits and power supplies.
5. Insert the amplifer into the PCB mounting holes located
in the space between the heatsink fns. So not solder the
pins at this time.
6. Hang the TW13 thermal washer near the end of a 6-32 X
3/8" screw. Slightly pull the amplifer away from the heat
sink face. Use the screw to position the thermal washer
behind the amplifer and insert the screw into the mounting
hole of the heatsink. Use a 6-32 nut to secure the screw
from the opposite side of the heatsink. It is important that
the entire back surface of the amplifers mounting tab be
in contact with the heatsink. Adjust the amplifers position
and tighten the mounting screw as necessary for this to
be so.
7. Solder the amplifers pins to the PCB.
your circuit.
9. Most common confgurations will ground the non-invert-
ing pin of the amplifer. J1 is a convenient way to do this
if necessary for your application circuit.
available resistors do not have a breakdown voltage suf-
fcient to stand off the output voltage of the amplifer. Using
multiple resistors will divide down the voltage that each
resistor must withstand.
Evaluation Kit for PA94, PA95
MAY 2009
APEX EK19UREVC
EK19
554 EK19U
FIGURE 2. PCB
1
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3
1 2
TOP SIDE
BOTTOM SIDE
4.65
3.37
DANGER
HIGH VOLTAGE
IC
C1
C2
Cc
Rc
R1
R2
R3
R4
R5
R
C4
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-
V
s
+
V
s
I
N

2
I
N

1
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X

2
A
U
X

1
R6
D1
D2
D3
D4
GND
GND
J1
HS27
LIM
EVAL23 R-A
1
MICROTECHNOLOGY
12
1
EK21
EK21U 555
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EK21 PA74
NOTE: Refer to HS11 Heatsink in Accessories section
INTRODUCTION
of power op amps that use the PA74 pin-out confguration. It
can be used to analyze a multitude of standard or proprietary
circuit confgurations. In addition, it is fexible enough to do most
standard amplifer test confgurations.
The schematic for 1/2 of the PC board is shown in Figure 2.
The schematic for the other half is identical except part refer-
ence designators are primed (i.e. R1 = R1'). Note that all of
the components shown on the schematic will probably not be
used for any single circuit. The component locations on the PC
board (See Figure 3) provide maximum fexibility for a variety
of confgurations. Also included are loops for current probes as
well as connection pads on the edge of the PC board for easy
interconnects.
The hardware required to mount the PC board and the device
under evaluation to the heatsink are included in the kit. Because
of the limitless combination of confgurations and component
values that can be used, no other parts are included in this
kit. However, generic formulas and guidelines are included in
the Apex Precision Power DATABOOK and this evaluation kit
documentation.
proper ESD precautions!
Always use the heatsink included in this kit with thermal grease
or a TW03 and torque the part to the specifed 4-7 in-lbs
(.45-.79 NM).
Do not change connections while the circuit is under pow-
er.
Never exceed any of the absolute maximums listed in the
device data sheet.
Remember that internal power does not equal load power.
Do not count on internal diodes to protect the output against
sustained, high frequency, high energy kickback pulses.
Teflon Tubing
(2 Opposite Pins
Minimum)
Recessed Nuts
Power Op Amp
Package
Heatsink
Mating Socket
PC Board
#8 Screw
#8 .375"
Hex Spacer
#8 1.00"
Hex Standoff
#6 Screw
Figure 1
PARTS LIST
HS11 Heatsink 1
EVAL02 PC Board 1
HWRE01 Hardware Kit 1
TW03 Thermal Washer 1 Box/10
HWRE01 contains the following:
4 #8 Panhead Screw 4 #6 x 1.25" Panhead Screw
4 #8 .375" Hex Spacer 4 #6 x 5/16" Hex Nut
4 #8 1.00" Hex Standoff 2 #6 x 1/4" Hex Nut
ASSEMBLY HINTS
The mating sockets included with this kit have recessed
nut sockets for mounting the device under evaluation. This
allows assembly from one side of the heatsink, making it easy
to swap devices under evaluation. The sizes of the stand-offs
were selected to allow proper spacing of the board-to-heatsink
and allow enough height for components when the assembly
is inverted.
ASSEMBLY
1. Insert a #6 x 5/16" hex nut in each of the nut socket recesses
located on the bottom of the mating socket.
2. Insert the socket into the pc board until it is frmly pressed
against the ground plane side of the pc board.
3. Solder the socket in place (see Figure 1). Be sure the nuts
are in the recesses prior to soldering.
4. Mount the PC board assembly to the heatsink using the
stand-offs and spacers included.
5. Apply thermal grease or a TW03 to the bottom of the device
under evaluation. Insert into the mating socket through the
heatsink.
6. Use the #6 x 1.25" panhead screws to mount the amplifer to
the heat sink. Do not overtorque. Recommended mounting
torque is 4-7 in-lbs (.45-.79 NM).
Mounting precautions, general operating considerations, and
heatsinking information may be found in the Apex Precision
Power DATA BOOK.
Evaluation Kit for PA74 Pin-Out
MAY 2009
APEX EK21UREVJ
EK21
556 EK21U
COMPONENT FUNCTION
R1 Feedback resistor, A side
R2 Input resistor, B side, bridge mode
R3 Feedback resistor, B side
R4 Input resistor, B side
R5 Input resistor, A side
R6 Input bias current measurement (Note 4)
R7 Output current sense resistor or loop for
current probe
R8 Output current sense resistor or loop for
current probe
R9 Input bias current measurement (Note 4)
R10 Noise gain compensation (Note 1)
R11 Resistor divider network for single supply
bias (Note 2)
bias (Note 2)
R13 Noise gain compensation (Note 1)
R14 Input bias current measurement
R15 Input bias current measurement
bias (Note 2)
bias (Note 2)
C1 Input coupling
C2 AC gain set
C3 AC gain or stability (Note 1)
C4 Power supply bypass
C5 Power supply bypass
C6 AC gain or stability (Note 1)
C7 AC gain set
C8 Input coupling
C9 Noise gain compensation (Note 1)
C10 Noise gain compensation (Note 1)
C11 Power supply bypass (Note 3)
C12 Power supply bypass (Note 3)
D1,2,3,4 Flyback protection (Note 5)
C13-16 Bias node noise bypass (Note 2)
2
1
13
3
4
C1 C2
R5
C15 C16
R17
R14
R6
A
C11 C12
D3
D1
R12 R13
C10
C4 C5
C3
R1
R2 J1
R8 R7
D2
B
D4
R3
C6
C7 C8
R4
R10
C9
R11
R16
C13 C14
6
8
9
10
R9
R15
7
+V
S
V
S
V
S
+V
S
A B
Figure 2
Figure 3.
1
8
8
1
PA74 EVAL.
EVAL02 REV. E
-V
OUT B
R
2
R
3
D
2
D
4
J1
OUT A
+V
R
1
C7
R8
C
6 C
1
2
D
3
D
1
C11
R7
C
5C
3 C4
C
9
R4
R
1
5
R
1
0
R
1
1
C8
R
1
6
C
1
3
R
1
4
C
1
0
R
1
3
R
1
2
C2
R5
R
1
7
C
1
6
C1'
R9
R6
6
7
8
C14
10
3
9
C15
4
13
2
1
+V'
OUT A'
OUT B'
-V'
C
9
'C
1
2
'
C
6
'
R
3
'
R
2
'
D
4
'
D
2
'
D
3
'
D
1
'
R
1
'
C
3
'
C
5
' R6' C1'
C2'
R5'
C
1
0
'
R
1
4
'
C
1
6
'
R
1
7
'
R
1
2
'
R
1
3
'
C
1
3
'
R
1
6
'
R
1
1
'
R
1
0
'
R
1
5
'
R9'
C7'
R4' C8'
J1'
C4'
R7'
R8'
C11'
C15'
C14'
1'
2'
13'
4'
3'
9'
10'
8'
7'
6'
TOP SIDE
BOTTOM SIDE
8.00
6.00
EK21
EK21U 557
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1
3
R5
R14
R6
A
C11 C12
D3
D1
C4 C5
R1
R2 J1
R8 R7
D2
B
D4
R3
9
R9
R15
B A
V
IN
+V
S
V
S
+V
S
V
S
Figure 4
Dual
Supply
Bridge
2
1
13
3
C1
R5
C15 C16
R17
R14
R6
A
D3
D1
R12
C4 C5
R1
R2 J1
R8 R7
D2
B
D4
R3
R9
R15
4
+V
S
+V
S
+V
S
A B
Figure 5
Single
Supply
Bridge
the load. To set the gain of the circuit you must determine the
desired voltage across the load at Vin = full scale. Inserting these
values into the following equation will yield the ratio of R1 to R5.
(V
AB
/(2*Vin)) = R1/R5
The values of R 1,2,3, and 5 should be chosen such that
input bias current will not cause an error voltage that is unac-
ceptable. Set R2 equal to R3 to confgure the slave amplifer
as a unity gain inverter.
Figure 5 shows a typical single supply bridge circuit for an AC
coupled input signal. DC coupled inputs may require a different
topology to accommodate proper gain and offset terms for a
desired transfer function.
The gain and output voltage capability for the single supply
bridge are determined the same way as the dual supply bridge
(see AN#2). The difference is the bias requirement for the slave
amplifer. The noninverting input of the slave amplifer should
be biased at mid supply, and must be bypassed.
BRIDGE MODE OPERATION
There are two types of bridge mode operation that will be
covered in this section; dual (or split) supply and single supply.
The PA74 is well suited for both types of bridge mode operation.
If another vendors pin compatible part is to be compared to the
PA74, a close look at output swing and input common mode range
is in order. The features that make the PA74 an excellent choice
for bridge operation are not included in most other amplifers. A
lack of common mode range may cause permanent damage to
other pin compatible parts and the inability of other amplifers
to swing close to the supply rails may cause a lack of available
output voltage at the load as well as increase internal dissipation.
The circuit shown in Figure 4 is a dual supply bridge using
the master-slave confguration. Resistors R 6,7,8,9,14,15
and J1 should be shorts. The available output voltage swing
is Vss(2*Vsat). If operating a PA74A at 3 Amps and 30 Volts
total supply this translates to:
V
AB
(max) = 30(2*3.5) = 23
Of course this 23 volts may be applied in either direction across
EK21
558 EK21U
HS11 HEATSINK NOTE
The HS11 Heatsink is provided in this evaluation kit to guar-
antee adequate thermal design through heat removal from
the part under evaluation. Once maximum power dissipation
for the application is determined (refer to General Operating
Considerations and Application Note 11 in the Apex Precision
Power DATA BOOK), the fnal mechanical design will probably
require substantially less heatsinking.
Apex Precision Power makes no representation that the use
or interconnection of the circuits described herein will not in-
fringe on existing or future patent rights, nor do the descriptions
contained herein imply the granting of licenses to make, use or
sell equipment constructed in accordance therewith.
NOTES:Refer to the following sections of the Apex Precision Power DATA BOOK as noted.
1. See Stability section of General Operating Considerations.
2. See Gen. Operating Considerations, and AN3 Bridge Circuit Drives.
3. See Power Supplies section of General Operating Considerations.
4. See Parameter Defnitions and Test Methods.
5. See Amplifer Protection section of Gen. Operating Considerations.
IMPORTANT NOTICE
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJ URY, OR SEVERE PROP-
EK26
EK26U 559
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P r o d u c t I n n o v a t i o n F r o m EK26 PA60EU
INTRODUCTION
Fast, easy breadboarding of circuits using the PA60EU are
possible with the PB80 PC board. Mounting holes are provided
and the provision for standard banana jacks simplifes connec-
tion and testing. The amplifer may be mounted horizontally or
vertically. Components are labeled on both sides of the board
for ease in probing.
A multitude of circuit confgurations are possible, so only
several component locations have specifc functions and will
usually be necessary:
C5,C8 Power supply bypasses MUST be used. Usually
ceramic types of 0.01 to 1.0F.
C2, C9 Power supply bypass. Suggest 10F per ampere of
output current.
R1 Feedback resistor.
R3 Input resistor.
R8, C10 Snubber network.
R4, C7 Noise gain compensation. Necessary only occasion-
ally, see Application Notes 19 and 25.
The following locations should be jumpered unless used (their
most common anticipated function is listed).
R2, R10 Input protection.
CR1 V
BOOST
.
R5, R6, R9 Output current sense.
The function of any other components is up to the designers
needs and imagination.
PA60EU CONSIDERATIONS:
When using the EK26 for the PA60EU the following components
on the schematic below must be left either shorted or open:
Short: R109, R209
Open: CR101, C106, CR201, C206
GND
IN 1
+IN 1
GND
C103 C104
R103
R104
C107 R107
C111 C112
R111 C108
C109
R109 R108
C110
CR103
CR102
CR101
C106
C105
C102
C101
R101
R102
R110
1
2
7
3
4
6
5
R105 R106
+V
OUT 1
GND
V
IN 2
+IN 2
C203 C204
R203
R204
C207 R207
C211 C212
R211
R209 R208
C210
CR203
CR202
CR201
C206
C201
R201
R202
R210
12
11
10
9
8
R205 R206
OUT2
GND
VCC
VEE
VCC
VEE
Evaluation Kit for PA60EU Pin-Out
MAY 2009
APEX EK26UREVF
EK26
560 EK26U
NOTE: Illustration only, not to scale.
C111
R
1
0
7
R
1
1
1
C
1
1
2
R110
R104
C107
CR101
CR201
R210
C207
R204 C211
C103
R103
C104 R101
R102
CR103
C101
C108 C105
CR102
CR203 CR202
C201
R201
C203
R203
C204
C
2
1
2
R
2
1
1
R
2
0
7
+IN2
GND2
IN2
OUT2
R206
R205
C206
R208
C210
R209
R108
C110
R109
R106
+IN1
GND1
IN1
OUT1
C105
C106
V
G
N
D
+
V
R109 R102
1
R202
1
R203
C102 C109
C211
R
2
0
7
R
2
1
1
C
1
1
2
R210
R204
C207
CR201
CR101 R110
C107
R104
C111
C203
C204
R202
C201
C105 C108
CR102
CR203 CR202
C101
C103
R103
C104
C
2
1
2
R
1
1
1+IN1
GND1
IN1
OUT1 R106
R105
C106
R108
C110
R109
R208
C210
R209
R206
+IN2
GND2
IN2
OUT2
R205
V
G
N
D
+
V
R102
R201
R
1
0
7
R101
C206
CR103
5"
7"
N
CIRCUIT SIDE
PB80 REV-B
R M I C E O T C H O O L G Y
EK26
COMP. SIDE
PB80 REV-C
EK26
EK27
EK27U 561
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
EK27 PA50, PA52
INTRODUCTION
linear power amplifers circuits using the PA50/PA52 pin out.
With ample breadboarding areas it is fexible enough to analyze
a multitude of standard or proprietary circuit confgurations.
Critical connections for power supply bypassing are pre-wired.
Components not usually readily available in engineering labs
are provided. External connection to the evaluation kit can be
made via the terminal block and terminal pads at the edges of
the circuit board. The terminal pads are suitable for soldering
standard banana jacks or direct soldering of wires. The schematic
* Initially set all power supplies to the minimum operating volt-
age allowed in the device data sheet.
PARTS LIST
HS18 Heatsink 1
EVAL29 PC Board 1
OX7R105KWN 1F Cap 1825B105K201N, 6
Novacap
TS02 Terminal Strip 1
Beau Interconnect 66507
TWO5 Thermal Washer 1 Box/12 each
EC05 2200 f Cap 100V 2
United Chemi-Con
82DA222M100KC2D
EC03 680F 200V 2
United Chemi-Con
KMH200VN681M25X40T2
ASSEMBLY
During assembly refer to Figure 1
1. Note that each circuit board side is identifed. From the
circuit side of the circuit board (not the component side)
insert and solder cage jack MS04 at pins 1-12. Be sure
that the cage jack sits fush with the surface of the circuit
board.
2. Solder the surface mount ceramic capacitors to the com-
ponent of the circuit board at C3-C7.
3. Mount the electrolytic capacitors at C1 and C2 from the
component side of the circuit board and solder from the
circuit side of the circuit board. Note polarity and be sure
to fll the holes with solder. Use correct voltage capacitor
for your application.
4. Mount the terminal strip TS02 to the component side of the
circuit board. Make sure the terminal strip sits fat against
the circuit board and be sure to fll the holes with solder.
6. Add other components to complete your circuit design. Note
that the solder terminals labeled 2 and 3 are left for you to
connect to the amplifer via the components that you will
add for your particular design.
7. Push the four nylon spacers into the circuit board from
the circuit side of the circuit board at the four corner loca-
tions.
8. Apply TW05 thermal washer to the bottom of the PA50.
Mount the amplifer to the HS18 heat sink provided and
loosely attach with #6 screw and nut.
9. Place the assembled circuit board over the pins of the
amplifer making sure that the pin 1 location on the circuit
board matches up with pin 1 of the amplifer. Insert the pins
of the amplifer into the circuit board mating cage jacks.
10. Mount the circuit board assembly to the heat sink with #6
self tapping or sheet metal screws at the four corners of
the heat sink.
11. Tighten the screws that mount the amplifer to the heat sink
via the access holes in the circuit board.
Evaluation Kit for PA50, PA52 Power Op Amps
MAY 2009
APEX EK27UREVC
EK27
562 EK27U
FIGURE 2. PCB SCHEMATIC. Figure 2 shows the schematic of the
pre-wired connections of the EK27.
Components which are supplied
with the kit are marked *
PA50/PA52
Heatsink
Amplifier
#8 or #10 Screw (1/2" - 3/4" LG)
Spacer Grommet
TW05 thermal washer
Cage Jack
Solder as required
FIGURE 1.
EK27
EK27U 563
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A

D
U
T

S
I
D
E
1
C
I
R
C
U
I
T

S
I
D
E
-
V
s
TS02
+
V
s
+
V
b
N
C
O
U
T
-
V
b
G
N
D
5
IC
IC
+
+
1
3 1 2
4
SIG
GND
GND SIG
OUT
C2
C1
C3
C4
C5
C6 C8
+
R-A
+
COMPONENT SIDE
HS28
R1
S
E
N
S
E
2
S
E
N
S
E
1
OPT -Vb
+Vb
12 7
C7
M
I
O
R
N
L
T
O
C
E
C
G
O
H
Y
EVAL29
5.500
4.686
TOP SIDE
BOTTOM SIDE
FIGURE 3. PCB
EK28
564 EK28U
P r o d u c t I n n o v a t i o n F r o m EK28 PA97DR
INTRODUCTION
of linear power amplifers circuits using the PA97 pin-out. With
ample breadboarding areas it is fexible enough to analyze
made via the terminals at the edge of the circuit board. These
terminal pads are suitable for standard banana jacks or direct
soldering of wires. The schematic is shown in Figure 1.
PARTS LIST
P6KE440A TransZorb, General 2
Semiconductor (440V)
Sprague 5GAS10
ASSEMBLY
1. See Figure 1. Insert and solder the TransZorb diodes at D3
and D4 (440V).
2. Insert and solder the disc bypass capacitors at C1 and C2.
3. Jumper R
LIM
and R
C
Note that heatsink HS28 is not used.
4. Add banana jacks as necessary to complete connections to
external circuits and power supplies.
5. Insert the amplifer into the PCB mounting holes located in
the space between the heatsink fns (not used) and solder
pins.
your circuit.
7. Most common confgurations will ground the non-inverting pin
of the amplifer. J1 is a convenient way to do this if necessary
for your application circuit.
available resistors do not have a breakdown voltage sufficient
to stand off the output voltage of the amplifer. Using multiple
resistors will divide down the voltage that each resistor must
withstand.
R
C4
C1*
C2*
1
R
2
R
3
R
4
R
D3*
5
R
6
C
C
J1
D2 D1
GND
440V
D4*
440V
1
4
6
10
12
8
2
PA97
FIGURE 1.
Figure 1 shows the schematic of the evaluation kit's pre-wired
connections. Components supplied with the kit are marked with
an asterisk (*). See the amplifer's data sheet for full applica-
tion information.
Evaluation Kit for PA97
MAY 2009
APEX EK28UREVC
EK28
EK28U 565
G
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I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
1
C
I
R
C
U
I
T

S
I
D
E
E
V
A
L
2
3
1 2
TOP SIDE
BOTTOM SIDE
4.65
3.37
DANGER
HIGH VOLTAGE
IC
C1
C2
Cc
Rc
R1
R2
R3
R4
R5
R
C4
O
U
T
-
V
s
+
V
s
I
N

2
I
N

1
G
N
D
A
U
X

2
A
U
X

1
R6
D1
D2
D3
D4
GND
GND
J1
HS27
LIM
EVAL23 R-A
1
MICROTECHNOLOGY
12
1
FIGURE 2. PCB
EK29
566 EK29U
EK29 PB51
INTRODUCTION
the PB51 high voltage power boosters. The PB51 is designed
most commonly in combination with a small signal, general
purpose op amp. However, they can also be used without a
driver amplifer. This kit can be used to analyze a multitude of
standard or proprietary circuit confgurations.
CAUTION
Use the supplied thermal washers or thermal
grease between the power amplifer and the
heat sink.
ASSEMBLY
solder the MS06 mating socket in DUT holes 1-12. Be sure
2. Solder components for your circuit. Be sure to incude proper
bypassing, required compensaton components and current
limit resistors. See the op amp data sheet for help in select-
ing these components.
mounting hole and thread a #6 nut onto the screw at the back
of the heat sink. Do not tighten. Note that there are two sets
of mounting holes on the HS20. Holes on one edge allow
room between the DUT and evaluation board for the MS06
socket. The holes on the other edge are for direct through
hole mounting of the DUT to the evaluation board. It is rec-
ommended that you use the MS06.
to the specifed 8 to 10 in-lbs. (.9 to .13 N*M) do not over
torque.
5. Install leads of the DUT into the the MS06 on the evaluation
board. Use #6 self-tapping screws to secure the evalua-
tion board to the HS20 heatsink as shown in the assembly
diagram (Figure1).
PARTS LIST
HS20 Heatsink 1
EVAL30 PC Board 1
TW07 Thermal Washer 1 package
this kit.
Power Booster Evaluation Kit
MAY 2009
APEX EK29UREVC
EK29
EK29U 567
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
FIGURE 1.
EK29
568 EK29U
E
V
A
L
3
0
D
U
T

S
I
D
E

C
I
R
C
U
I
T

S
I
D
E
G
N
D
1
1
COMPONENT SIDE
EVAL30 R-A1
G
C
M
I
O
R
T
N
E
C
H
L
O
O
Y
-VCC +VCC GND -IN
+IN
IC
IC
-Vs
DUT
+Vs
OUTPUT
I
N
C
O
M
C
C
G
A
I
N
+
V
S
I
L
I
M
-
V
S
O
U
T
12
U1
R1 R2
C9
C7 C6
C5
D1 C8
1
C11D2
C10
+ +
+ +
+ +
+ +
+
+ +
1
C4 C3
C2 C1
GND
+VCC
-VCC J4
J3
J2 J1
J5
G
N
D
G
N
D
J6
N
C
N
C
N
C
N
C
A
A
TOP SIDE
BOTTOM SIDE
5.50
3.00
FIGURE 3. PCB
EK33
EK33U 569
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
EK33 PA75CX
INTRODUCTION
Fast, easy breadboarding of circuits using the PA75CX or
PA35CX are possible with the EK33 PC board. Mounting holes
are provided and the provision for standard banana jacks simpli-
fes connection and testing. Components are labeled on both
sides of the board for ease in probing. This kit is not suitable for
PA75CC, PA75CD, PA35CC or PA35CD.
usually be necessary:
PARTS LIST
Eval33 Evaluation Board 1
Clamp04 Clamp for HS29 2
MS11 Pin Receptacle, 30 pin strip 1
TW14 Thermal Washer TO-220 1
10/Pack
HS29 Heat Sink, 2.7 DEG/W 1
COMPONENT FUNCTION
C1, C5, C7, C9 Power Supply bypasses MUST be used
C2, C6 for each amplifer. Usually ceramic types of
.01F to 1.0F and 10F of capacitance
per ampere of output current.
R11, R5 Feedback resistors
The following locations should be jumpered unless used
otherwise (their most common function is listed).
J3, J9 Output amp a to input amp b
J2, J8 -Vs
J4, J6 Connects paralleling output a to output b
J5, J10 Connects feedback for amp a
The following locations should be left open unless used otherwise
(their most common anticipated function is listed).
J1, J7 Connects -Vs to ground reference
The function of all other components is up to the designer's
circuit needs.
-
I
N
(
1
A
)
+
I
N
(
1
B
)
O
U
T
1
B
+
I
N
(
2
B
)
J8
O
U
T
2
B
O
U
T
2
A
GND
VIN
C1
R1
4
6
3
+
5
+
2
-
1
7
PA35A
+VS C5
J3
R5
C6
R4
R2
CR1
J5
+VS
CR3
+VS
C2
C9
C7
J9
+VS
+VS
R8
R10
R12
J10
+
I
N
(
1
A
)
R6
J2 J1
C3
O
U
T
1
A
+
I
N
(
2
A
)
-
I
N
(
2
A
)
-
V
S
1
J7
C12
J6
IC CIRCUIT
R3
+VS
R9 CR2
4
6
3
+
5
+
2
-
1
7
PA35B
R11
+VS
CR4
C4
J4
C10
R7
Evaluation Kit for PA75CX or PA35CX Pin Out
MAY 2009
APEX EK33UREVF
EK33
570 EK33U
MS11
TW14
CLAMP04
HS29
EVALUATION BOARD
#6 SELF TAPPING SCREW (TYP)
FIGURE 1.
R
3
C
R
1
J10 R
5
C5
J2
J6
R
4
C
R
3
J5
C2
J1
J7
C7
C6
C12
R9
R
1
2
R
1
1
-IN(1A) +
I
N
(
1
A
)
O
U
T
1
A
O
U
T
1
B
C9
C
R
2
R
1
V1
C8 J8
G
N
D
.
O
U
T
2
B
O
U
T
2
A
R7
-VS1
C10
-
I
N
(
2
A
)
+
I
N
(
2
B
)
CR4
C3
C1
C4
J4
J3
R10
J9
R8
C11
+IN(1B) +VS
R
6
R
2
PA35A
+IN(2A)
PA35B
C I R C U I T S I D E
E V A L 3 3
R
3
C
R
1
J 1 0
R
5
C
5
J 2
J 6
R
4
C
R
3
J 5
C 2
J 1
J 7
C
7
C 6
C 1 2
R 9
R
1
2
R
1
1
-
I
N
(
1
A
)
+ I N ( 1 A ) O U T 1 A O U T 1 B
C
9
C
R
2
R
1
V 1
C
8
J 8
G N D O U T 2 B O
U
T
2
A
R 7
- V S 1
C
1
0
- I N ( 2 A )+ I N ( 2 B )
C R 4
C 3
C 1
C 4
J 4
J 3
R 1 0
J 9
R 8
C
1
1
+
I
N
(
1
B
)
+ V S
R
6
R
2
P A 3 5 A
+
I
N
(
2
A
)
P A 3 5 B
M I O T E R O L N H O G Y C C
COMP. SIDE
EVAL33
REV C
EK33
TOP SIDE
BOTTOM SIDE
6.50
3.25
EK34
EK34U 571
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
EK34 PA240CX
INTRODUCTION
Fast, easy breadboarding of circuits using the PA240CX are
possible with the EK34 PC board. Mounting holes are provided
tion and testing. The amplifer may be mounted horizontally or
vertically. Components are labeled on both sides of the board
for ease in probing.
A multitude of circuit confgurations are possible, so only sev-
eral component locations have specifc functions and will usually
be necessary. This kit is not suitable for use with PA240CC.
PARTS LIST
Eval 34 Evaluation Board PA40/140CX 1
Clamp04 Clamp for HS29 2
MS11 Pin Receptacle, 30 pin strip 1
TW14 Thermal Washer TO220 10/Pack 1
HS29 Heat Sink, 2.7 DEG/W 1
COMPONENT FUNCTION
C1,7 Alone is a roll off, with R3, 13 is a current out stability
network (ref. AN19)
C2,6 With R6, 15 forms noise gain compensation network
(ref. AN25)
C3,4 Supply bypass, .22 to 1F ceramic
C5,8 With R9, 20 forms a Howland stability network, can
jumper both to ground +IN
Cc Sets compensation to match desired gain
Cs Normally not used.
D1-4 Flyback protection diodes
R1,11 Inverting inputs, install to input line or to ground
R2,12 Negative feedback, install to V for voltage out or to I
for current output (ref. AN19)
R3,13 With C1, 7 forms a stability network for current output
(ref. AN19)
R4,14 Current sense for current outputs (ref. AN13)
R5,15 With C2, 6 forms noise gain compensation network
(ref. AN25)
R6,17 Input R for Howland current
pump or differential, usually
shorted for non-inverting
R7,19 Current sense for Howland cur-
rent pump. Could also be used to
isolate large Cloads (ref. AN25)
R8,21 Positive feedback, install to H
for a Howland current pump,
to D for a differential circuit
R9,20 With C5, 8 forms a Howland
stability net work, can jumper
both to ground +IN
R10 With an equal value R12 pro-
vides gain = -1 for a bridge slave
(ref. AN3,20)
R18,19 Can provide mid-supply refer-
ence for single supply bridge
(ref. AN3, 20)
Rc Normally shorted.
Rs Normally not used.
C6
-IN2
+IN1
-IN1
C1
R16
OUT2
Irtn2
VIN
-Vs
+Vs
+IN2
C2
-VS
R20
-VS
+VS
C7
C5
R9
+VS
4
3
6
7
1
2
5
PA240(1)
-VS
R21
+VS
R18
R14
R8
R7
R4
D4
-VS
+VS
+VS
D1
D2
-VS
C10
+VS
OUT1
GND
Irtn1
-VS
-VS
4
3
6
7
1
2
5
PA240(2)
C8
R10
R19
-VS
D3
J3
C4 C3
R15
R3
Cs
Rc
R17
R13
R12
R11
Cs
Rs
Cc
R5
R6
R1
R2
C9
Rc
Rs
Cc
V
I
I
D
H
D
V
H
IC CIRCUIT
Evaluation Kit for PA240CX
MAY 2009
APEX EK34UREVF
EK34
572 EK34U
FIGURE 1.
EVAL34
TOP
EVAL34
BOTTOM
MS11
TW14
CLAMP04
HS29
EVALUATION BOARD
#6 SELF TAPPING SCREW (TYP)
-IN1
C
s
C
9
VIN
C
3
+IN2 +Vs
R
8
R
6
R
5
C
2
R
7
D
1
C
8
R
2
0
C
6
R
1
1
R
1
8C
7
R
1
4
D
3
R
1
9
D
4
Cc
Cc
+IN1 OUT1
Rc
GND
C4
-IN2
Rc
R
4
R
9
R
1
R
2
C
1
R
3
C
5
R
s
D
2
R
2
1
R
1
5
R
1
7
R
1
6
R
1
2
R
1
3
R
s
C
s
-Vs Irtn1 OUT2
J3
C10
R10
PA240(1)
Irtn2
PA240(2)
C
V
I
D
H
V
I
H
D
GND
EVAL34
MICROTECHNOLOGY
REV
COMPONENT SIDE
GND
EK42
EK42U 573
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
EK42 PA15FL, PA241DW
INTRODUCTION
Fast, easy breadboarding of circuits using the PA241DW
and the PA15 are possible with the EK42 PC board. Mounting
holes are provided and the provision for standard banana jacks
simplifes connection and testing. The amplifer may be mounted
horizontally or vertically. Components are labeled on both sides
of the board for ease in probing.
usually always be necessary:
C5,C7 Power supply bypasses MUST be used. Usually
ceramic types of 0.01 to 0.1F.
R1 Feedback resistor.
R2 Input resistor.
R9, C11 Compensation (see amplifer data sheet).
R5 Current limit (see amplifer data sheet).
R7 Most often used as input bias current return for +input
in non-inverting circuits.
R3, C6 Noise gain compensation. Necessary only occasion-
ally, see Application Notes 19 and 25.
The following locations should be jumpered unless used (their
most common anticipated function is listed).
R4, R8 Input protection.
R11 General purpose.
R6 Output current sense.
The function of any other components is up to the designers
needs and imagination.
+V
Out
GND
V
IN
+IN
GND
C2 C3
R2
R3
R7
R11 C10
C6
R4
C5
C1
R1
R8
C7
R9 R10
R5 1
2
6 10
7
9
8
5
C11
C12
R6
CR2
CR1
NOTE: Illustration only, not to exact scale.
EK422 REV A
COMP. SI DE
C10
R11
R7
GND
+IN
IN
R4
C2
C3
R2
R8
C6
+ C5 R9
C11 C7 +
CR1
CR2
R3
C12
C1
R1
R5
R10
R6
V
OUT
GND
+V
1
EK42
REV A
V
OUT
GND
+V
IN
+IN
GND
R9
C11
C5 +
+ C7
R4
C2
R2
C3
R3
R8
C6
R7
C10
R11
R1
R5
R10
C1
C12
R6
CR1
CR2
1
2.5"
63.5mm
3.5"
88.9mm
CAUTION High voltages will be present.
Use caution in handling and
probing when power is applied.
Evaluation Kit for PA15 and PA241DW Pin-Outs
MAY 2009
APEX EK42UREVD
EK50
574 EK50U
EK50 PB50, PB58
INTRODUCTION
This easy-to-use kit provides a platform for the evalua-
tion of the PB50 and PB58 high voltage power boosters.
The PB50 and PB58 are designed most commonly in
combination with a small signal, general purpose op
amp. However, they can also be used without a driver
amplifer. This kit can be used to analyze a multitude of
standard or proprietary circuit confgurations.
PARTS LIST
HS13 Heatsink 1
EVAL01 PC Board 1
HWRE02 Hardware Kit 1
HWRE05 8-Pin Wire Wrap Socket 1
TW0 3 Thermal Washer 1 Box/10
HWRE02 contains the following:
4 #8 x .375" Panhead Screws
4 #8 x .375" Hex Spacers
4 #8 x 2.00" Hex Stand Offs
2 #6 x 1.25" Panhead Screws
2 #6 x 5/16" Hex Nuts
E
V
A
L
0
1
R
E
V
B
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
R
C
L
P
I
N
1R
G C
C
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
O
U
T
O
P

A
M
P
1
C
O
M
I
N
I
N
+
I
N
+
V
c
c
G
N
D
G
N
D
GND
GND
Vs
+Vs
Vcc
P
B
5
0
P
B
5
8
EK 50
E
V
A
L
0
1
R
E
V
B
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
R
C
L
P
I
N
1R
G C
C
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
O
U
T
O
P

A
M
P
1
C
O
M
I
N
I
N
+
I
N
+
V
c
c
G
N
D
G
N
D
GND
GND
Vs
+Vs
Vcc
P
B
5
0
P
B
5
8
EK 50
8"
6"
CAUTION
1. Use thermal grease or Apex Precision Power Thermal Washer TW03 between power booster and heatsink.
2. Use 18 gauge tefon sleeve on at least two opposite pins
3. Mounting torque greater than 7 inlbs on power booster mounting bolts will void warranty!
ASSEMBLY
Teflon Tubing
(2 Opposite Pins
Minimum)
PB50/PB58
Package
MS03 Mating Socket
Eval01 PC Board
#8 x .375" Panhead Screw
4 places typ
#8 x .375"
Hex Spacer
4 places typ
#8 x 2.00"
Hex Standoff
4 places typ
HS13 Heatsink
8-pin wire wrap socket
Recessed Nuts
#6 x 5/16"
2 PlacesTyp
#6 x 1.25"
Panhead Screws
2 Places Typ
Evaluation Kit for PB50, PB58 Power Boosters
MAY 2009
APEX EK50UREVE
EK50
EK50U 575
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C
B
A
G
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C
B
A
VS
GAIN
COMP
CL
+VS
COM
IN
OUT
VCC
+VCC
7
1
1
3
2
8
7
6 4
5
+
+ +
+
+ +
+
+
+
+ + +
5
6
4
8
2
3
IN
VCC
+VCC +VS
GND
OUT
RG
CC
RCL
VS
+IN
AD707
PB50
PB58
IMPORTANT NOTICE
EK51
576 EK51U
EK51 DF Packages (24-pin PSOP)
INTRODUCTION
The EK51 evaluation kit provides a fast and easy breadboard
solution for all devices in Apex Precision Powers PSOP1 package
(24 PIN PSOP). The EK51 includes the EVAL43 board shown
in Figure 1, as well as the universal EVAL36 board. The combi-
nation of the two boards provides a large area for breadboard
circuit space while also providing an effective method of thermal
management of the surface mount package. The device under
evaluation is surface mounted directly to the EVAL43 PC board
which provides a foil footprint area the size of the heat slug. This
foil heat slug connection area consists of plated through thermal
vias. The thermal vias offer a cost-effective way to decrease the
thermal resistance between one side of the PC board which al-
lows for the direct mounting of a heat sink or heat sink surface
mount fan on the back side of the PC board.
PARTS LIST
Part# Description Qty
EVAL36 Universal PC Board, 1
EVAL43 PC Board, PSOP1, 1
TSM-116-01-T-SV Terminal Strip, 16pin, Samtec 2
SSW-116-01-T-S Socket Strip, 16pin, Samtec 2
OX7R105KWN Cap, 200V, 1F, Ceramic 4
*ERJ-6GEYOR00V Res, 0.0, 0805SMD, Panasonic 4
*AVS336M2AG24T Cap, 100V, 33F, CDE 4
*031606 Heat Sink w/ Fan, 3.4C/W, AAVID 1
or
*031613 Heat Sink, 11.0C/W, AAVID 1
* Parts not supplied. Parts are application dependent. Sug-
gested part numbers are provided.
Figure 1: EVAL 43
ASSEMBLY
The PSOP1 should be assembled to the EVAL43 PC board
using surface mount processes. Solder paste may be dispensed
or screen-printed on the DUT pads as well as the foil heat slug
pad. The heat slug on the bottom surface of the PSOP1 pro-
vides maximum heat dissipation capabilities when soldered to
the PCB foil footprint area. However, for prototype purposes,
the tab can be thermally connected to the PCB foil area using
thermal grease.
If soldering the heat slug, ideally the PSOP1 should be soldered
to the PCB using a solder refow furnace. If a refow furnace is
not available, a heat plate capable of solder refow temperatures
may be used. Otherwise, the leads may be carefully soldered
individually to the PCB with a thin tip soldering iron. However,
in this case, the use of thermal grease under the heat tab is
recommended instead of solder for thermal connection through
the thermal vias.
The kit comes with ceramic bypass capacitors, which should
be soldered on the space provided on the EVAL43 board.
Also, space is provided for the appropriate electrolytic by-pass
capacitors. Although these capacitors are not provided in the
kit, a recommended capacitor is listed for 100V applications.
For higher voltage applications, a larger electrolytic capacitor
can be mounted on the EVAL36 board.
The EVAL43 is a generic evaluation board for the PSOP1.
Jumpers are required to make appropriate connection to +Vs,
-Vs and ground. When applicable, surface mount 0805 0
resistors can be used in the locations provided.
Once all the surface mount components are installed, the
heat sink can then be mounted to the back of the PC board.
High thermal conductive grease should be used when mounting
the heat sink to the PC board. Note: A heat sink is not supplied
with the kit, but several options are listed which are produced
by AAVID Thermal Product, Inc.
Review Figure 2 on the next page for all other assemblies
needed to construct this evaluation kit.
* Always provide the appropriate heat sinking.
* Always use adequate power supply bypass capacitors.
* Initially set all power supplies to the minimum operating levels
Evaluation Kit for DF (24-pin PSOP)
MAY 2009
APEX EK51UREVB
EK51
EK51U 577
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A
Figure 2: EVAL36
EK52
578 EK52U
EK52 MP230, MP240
INTRODUCTION
linear power amplifers circuits using the MP230FC/MP240FC
pin out. With ample bread boarding areas it is fexible enough
to analyze a multitude of standard or proprietary circuit con-
fgurations. Critical connections for power supply bypassing
are pre-wired. Components not usually readily available in
engineering labs are provided. External connection to the
evaluation kit can be made via the terminal block and the
banana jacks at the edges of the circuit board. Additionally,
an optional BNC connector can be inserted into the hole at
the edge of the board and wired to the number 5 terminal pad.
All Apex Precision Power amplifers should be handled
using proper ESD precautions.
Initially set all power supplies to the minimum operating
voltage allowed in the device data sheet.
PARTS LIST
Ref Apex Part # Descrip/Vendor Qty
NA HS28 Heat Sink 1
NA HS26 Heat Sink 1
NA MS11 Cage jack strip 2
BJ1-4 BJ1 Banana Jack/ 4
Deltron 164-6218
NA EVAL45 PC Board 1
NA 60SPG00004 Spacer Grommets/ 4
Micro Plastics
C1-4 OX7R105KWN 1uF Cap/ 4
Novacap 1825B105K201N
TS1 TS02 Terminal Strip 1
C5,6* EC05 2200uF 100V/ 2
United Chemi-Con
82DA222M100KC2D
C5,6* EC03 680uF 200V/ 2
United Chemi-Con
KMH200VN681M25MX40T2
RLIM* CSR17 0.025 Ohm Resistor/ 1
Isotek PBV-R025-1
Isotek PBV-R050-1
Isotek PBV-R100-1
Rs1-Rs4 NA Separate purchase required 4
See text.
*Chosen per directions
-IN +IN
+Vb
-Vb
Iq Cc2
OUT
GND
GND
1 2 3 4 5 6 7 8
39 40 37 38 36 35 34 33 41 42
-Vs
OUT
Cc1 NC
-Vs -Ilim +Ilim
VIEW FROM PCB COMPONENT SIDE
+
C2
C5
C4
+
C6
R
9 10 11 12
30 32 31 29
+Vs +Vs +Vs
-Vs
OUT
OUT OUT OUT
NC
20 13 14 15 16 17 18 19
24 23 22 25 26 27 28 21
+Vs +Vs +Vs
OUT OUT OUT
-Vs -Vs -Vs
OUT OUT OUT
NC NC NC
LSD HSD
LIM
+5V
TS1
+Vs
+Vb
OUT
-Vb
GND
-Vs
C1
C3
PCB AMPLIFIER TERMINALS
PCB WIRING TERMINALS
TERMINAL STRIP TERMINALS
(ACCESSORY)
1
2
3
4
5
ACCESSORY TERMINALS
Rs1 Rs2
Rs4 Rs3
BJ1
BJ2
BJ3
BJ4
BNC
INPUT
D1
D3
D2
D4
NOTES:
1. D1-D4 OPTIONAL PROTECTION DIODES (NOT SUPPLIED)
2. Rs1-Rs4 ARE REQUIRED BUT NOT SUPPLIED (SEE TEXT)
FIGURE 1. EVAL45 Schematic
Evaluation Kit for MP230FC, MP240FC Pin-Out
MAY 2009
APEX EK52UREVH
EK52
EK52U 579
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ASSEMBLY
During assembly refer to Figure 3 and the data sheet for the
product you are using, either the MP230FC or MP240FC.
1 Note that four balancing resistors, Rs1-Rs4, are required
for this evaluation kit and that these resistors are not sup-
plied. Each application will require different values and
so these resistors must be purchased by the user before
construction of the kit begins. See the recommendation in
the product data sheet as to the type of resistor needed
and a convenient source for purchasing the resistors.
Do not be tempted to operate the amplifer without these
resistors.
2. Note that each side of the circuit board is identifed as
either the Component Side or DUT Side.
3. Locate the two pre-loaded 30-position cage jack carrier
strips. Use wire cutters to cut off and discard 10 positions
from one of the carrier strips. From the DUT Side of the
PCB insert this carrier strip into the mounting holes for pins
1-20 of the amplifer and solder from the Component Side
of the PCB. Be sure that the cage jacks are fully seated
before soldering. Be careful that solder does not fow into
the cage jack.
4. In a similar manner to step 3 cut off 8 positions from the
remaining carrier strip, insert and solder into the mounting
holes for amplifer pins 21-42.
5. Pull out and discard each of the carriers.
6. Solder the surface mount capacitors at C1, C2, C3, and
C4 on the Component Side of the PCB.
7. Solder the surface mount balancing resistors that you
purchased separately at Rs1-Rs4 on the Component
Side of the PCB.
8. Mount the four horizontal banana jacks at locations BJ1-
4 and a BNC connector, if desired (not supplied), to the
PCB pad at location 5. Solder from the DUT Side of the
PCB.
9. Mount the terminal strip to the Component Side of the
PCB. Make sure the terminal strip is fully seated and solder
the pins from the DUT Side of the PCB. Be sure to fll
the mounting holes with solder.
Component Side of the PCB. Match the polarity markings
on the capacitor with the polarity markings on the PCB.
Use the correct voltage capacitors for the product you are
using: 100V capacitors for the MP230 and 200V capacitors
for the MP240. Be sure the capacitors have snapped into
the PCB and solder from the DUT Side of the PCB. Be
sure to fll the holes with solder.
11. Several low ohm value resistors are provided with this
evaluation kit: 0.025 ohm, 0.050 ohm and 0.100 ohm.
These are used to implement current limiting in the output
circuit. Select the value most appropriate for your applica-
tion. Refer to the product data sheet to determine which
resistor value you should use.
12. Mount the HS28 heat sink to the PCB and solder the
mounting tabs of the heat sink.
13. Apply a thin layer of thermal grease on the back of the
chosen current limiting sense resistor, insert the resistor
into the PCB and mount the resistor to the HS28 heat sink
using #4 screw and nut hardware (not supplied). Solder
the leads of the current limiting resistor from the DUT
Side of the board. Be sure to fll the mounting holes with
solder.
14. Mount other components and wiring as needed to com-
plete your application circuit using the pads and holes
provided.
15. From the DUT side of the PCB snap the spacer- grommets
into the holes at the four corners of the PCB. Notice that
the holes are slightly rectangular and match the spacer-
grommets long and short sides to the holes in the PCB.
16. Apply a thin layer of thermal grease to the amplifer base.
Position the amplifer over the mounting holes in the HS26
heat sink. Firmly push the amplifer onto the heat sink
while slightly rotating the amplifer back and forth, ending
with the mounting holes of the amplifer over the mounting
holes in the heat sink.
17. Attach the amplifer to the heat sink with 4 4-40 X male-
female hex spacers (not supplied). These spacers serve
as alignment pins and aide in the assembly of the PCB to
the heat sink. Alternately, use 4-40 X machine screws
to mount the amplifer to the heat sink. Do not over-tighten
the spacers or screws as this provides no thermal beneft
and may break the hardware.
18. Place the PCB assembly onto the HS26 heat sink so that
the four hex spacers come through the aligning holes
near the four corners of the amplifer position in the PCB.
Carefully lower the PCB assembly until the pins of the
amplifer engage the cage jacks. Alternately, sight through
the aligning holes in the PCB and match-up the PCB to the
screws used to mount the amplifer. In either case be sure
the pins of the amplifer are engaged with the cage jacks
and then continue pushing the PCB assembly in the area
between the amplifers pins until the 4 spacer grommets
at the four corners of the PCB touch the HS26 heat sink.
At this point you may need to push the PCB down slightly
in the area of the amplifer if the PCB is bowed.
19. Use #8 X 1 sheet metal screws (not provided) to mount
the PCB to the heat sink at the four spacer-grommets.
20. Hook up power and signals as necessary. The amplifer
is now ready for testing.
EK52
580 EK52U
FIGURE 2.
D U T S I D E
TS1
EVAL45 R-D
COMPONENT SIDE
SIG GND
C5
IC1
IC2
+
+
MICROTECHNOLOGY
SIG GND
+5V
OUT
-Vb
GND
+Vb
-Vs
+Vs
HS28
Rlim
C1
C2
C3
C4
1
42
20
21
SIG GND
OUT
+Vs
-Vs
+Vb
-Vb
PWR GND
+5V
C6
SIG GND
RS2 RS1
RS4 RS3
BNC
SIG GND
SIG GND
1
2
3
4
5
INPUT SIG
BJ1
BJ2
BJ3
BJ4
5
+
+
D1
D3
D2
D4
9.75
6.625
BOTTOM SIDE
TOP SIDE
EK52
EK52U 581
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4-40 X 1/4 SCREWS
NO. 8-10 X 1 SHEET METAL SCREWS
HS26 HEATSINK
SPACER GROMMET
HS28 HEATSINK
CURRENT LIMITING SENSE RESISTOR
NO. 4 MOUNTING HARDWARE
ELECTROLYTIC CAPACITOR
DEVICE UNDER TEST
CAGE JACKS
SURFACE MOUNT CAPACITORS
PC BOARD
ACCESS HOLES
DIODE
HARDWARE USING
HEX SPACERS
ALTERNATE MOUNTING
TERMINAL STRIP
FIGURE 3.
INTRODUCTION
of PWM circuits using the MSA240KC/260KC pin out. With
ample bread boarding areas it is fexible enough to analyze
made via the terminal block and banana jacks at the edges
of the circuit board.
PARTS LIST
Ref Apex Part No. Description/Vendor Qty
NA HS28 Heat Sink, 2
NA HS26 Heat Sink, 1
NA MS11 30-pin socket carrier strip 2
Micro Plastics
BJ1-4 BJ1 Banana Jack/ 4
Deltron 164-6218
C1,3 ZX7R105KTL 1uf 500V Cap/
Novacap
ST2225B105K501LLXW 2
For identifcation note this capacitor has legs.
C2* EC05 2200uF 100V/ 1
United Chemi-Con
82DA222M100KC2D
C2* EC06 470uF 450V/ 1
United Chemi-Con
KMH450VN471M35X50T2
R1,2* CSR22 0.020 Resistor/ 2
Isotek PBV-R020-1
R1,2* CSR20 0.010 Resistor/ 2
Isotek PBV-R010-1
R1,2* CSR21 0.015 Resistor/2
Isotek PBV-R015-1
*Chosen per directions
ASSEMBLY
product you are using, either the MSA240KC or MSA260KC.
1. Note that each side of the circuit board is identifed as either
the component side or "DUT side".
2. Two 30-pin socket strips have been supplied with this kit
that have been loaded with cage jacks. Using wire cutters
trim the carrier to remove two sockets from one of the strips.
Insert the socket strips from the "DUT side" of the board and
solder the jacks from the "component side" of the board,
making sure that each socket strip is fully seated before
soldering. After soldering the jacks remove and discard
the plastic carrier.
3. Solder the surface mount capacitors at C1 and C3 on the
"component side" of the board.
4. From the "component side" mount banana jacks at BJ1-4
and solder from the "DUT Side" of the circuit board. Cut
off excess lead lengths. Note that BJ1 is connected to SIG
GND.
5. Several low ohm value resistors are provided with this evalu-
ation kit: 0.020, 0.015 and 0.010. These are used to
implement current limiting in the output circuit. Select the
value most appropriate for your application. Refer to the
product data sheet to determine which resistor value you
should use.
6. From the "component side" of the PCB mount the HS28
heat sink closest to C2 (to be added later) and solder the
mounting tabs of the heat sink from the "DUT side" with a
high capacity soldering iron.
chosen current limiting sense resistor R2 and insert the
resistor into the PCB. Mount the resistor to the HS28 heat
sink using #4 screw and nut hardware (not supplied). Place
the screw into the mounting hole from the narrow-channel
side of the heat sink and place the nut on the screw from
the wide-channel side of the heat sink. Do not over tighten
the screw. Finally, solder the resistor terminals to the PCB
and cut off the excess lead length.
8. Mount the remaining HS28 heat sink similarly to step 6.
9. Repeat step 7 for R1 and the second HS28 heat sink.
10. Mount the electrolytic capacitor at C2 from the "compo-
nent side" of the PCB. Match the polarity markings on the
capacitor with the polarity markings on the PCB. Use the
correct voltage capacitors for the product you are using:
A 100V capacitor for the MSA240KC, or a 450V capacitor
for the MSA260KC. Be sure the capacitors have snapped
into the PCB and solder from the "DUT side" of the PCB.
Be sure to fll the holes with solder.
11. Mount the terminal strip to the "component side" of the
PCB. Make sure the terminal strip is fully seated and solder
the pins from the "DUT side" of the PCB. Be sure to fll the
mounting holes with solder.
12. Mount a BNC connector (not supplied) to the PCB at loca-
tion 5 (near the banana jacks) if desired. The body of the
BNC connector is tied to SIG GND.
13. Mount other components to complete your application
circuit using the pads and holes provided. Refer to the data
sheet for your model and note on page 4 that:
R
RAMP
= 2 X R
OSC
It is therefore convenient to use 3 resistors of equal value
and make up R
RAMP
from two of those resistors. Note on
the PCB locations for R
RAMP1
and R
RAMP2
to do this.
EK56
582 EK56U
EK56 MSA240, MSA260
Evaluation Kit for MSA240KC and MSA260KC
MAY 2009
APEX EK56UREVJ
14. From the "DUT side" of the PCB snap the spacer- grom-
mets into the holes at the four corners of the PCB. Notice
that the holes are slightly rectangular and match the spacer-
grommet's long and short sides to the holes in the PCB.
15. Apply a thin, uniform layer of thermal grease to the amplifer;
a straight edge may be useful here. Position the amplifer
over the mounting holes in the heatsink. Firmly push the
amplifer onto the heatsink while slightly rotating the ampli-
fer back and forth, ending with the mounting holes of the
amplifer over the mounting holes in the heatsink.
16. Attach the amplifer to the heatsink with 4-40x male-
the heatsink. Alternatively, use 4-40x machine screws
to mount the amplifer to the heatsink. Do not over-tighten
17. Place the PCB assembly on the heatsink/amplifer assembly
so that the hex spacers come through the aligning holes
near the corners of the amplifer location in the PCB. Care-
fully lower the PCB assembly until the pins of the amplifer
engage the cage jacks. Alternately, sight through the align-
ing holes in the PCB and match-up the PCB to the screws
used to mount the amplifer. In either case be sure the pins
of the amplifer are engaged with the cage jacks and then
continue pushing the PCB assembly in the area between
the amplifers pins until the four spacer grommets at the
four corners of the PCB touch the heatsink. At this point
the PCB should not be bowed.
18. Using #8 X 1" sheet metal screws (not provided) mount the
PCB to the heat sink at the four spacer-grommets.
FIGURE 1: SCHEMATIC DIAGRAM
ASSEMBLY CONT.
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
5 0 9 8 7 6 5 14 13 12 11 20 19 18 17 16 25 24 23 22 21 26 27 28 2 1
Vcc
4 3
+Vs A OUT +Vs B OUT Isense B
PWR
GND
D
I
G
I
T
A
L

R
E
T
U
R
N
I
l
i
m

B
I
l
i
m

A
/
S
H
D
N
+
I
N
E
A

-
I
N
E
A

+
I
N
E
A

O
U
T
R
o
s
c
C
L
K

O
U
T
C
L
K
/
2

O
U
T
C
L
K

I
N
S
I
G

G
N
D
N
C
N
C
N
C
N
C
N
C
N
C
N
C
S
I
G

G
N
D
33
N
C
N
C
Rosc
C1
32 30 29 31
+
5
V

O
U
T
A
C

B
A
C
K
P
L
A
T
E
A
P
E
X

T
P
N
C
S
I
G

G
N
D
55 56 58 57
R
A
M
P
R
I
N
Isense A
TS1
PWR
GND
B OUT +Vs A OUT Vcc
R1 R2
R3
R4
C4
C5
C2 C3
+
1
2
4
3
5
BREAD BOARDING TERMINALS BANANA JACK
NOTE: BREAD BOARDING ARRAY NOT SHOWN
SIG GND
J2
J1
NOTE: J1 AND J2 NORMALLY REQUIRED. SEE INSTRUCTIONS ABOVE
SIG
GND
BJ1
BJ2
BJ3
BJ4
BNC
HOLE IN PCB FOR BNC CONNECTOR
RIM OF PLATED HOLE TIED TO SIG GND
R
RAMP2
R
RAMP1
SINGLE
POIINT
GND
EK56
EK56U 583
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B
A
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B
A
EK56
584 EK56U
6.625
REF.
9.750
REF.
TOP VIEW
BOTTOM VIEW
D U T S I D E
TS1
EVAL56 R-4
COMPONENT SIDE
MICROTECHNOLOGY
C2
BNC
SIG GND
SIG GND
INPUT SIG
BJ1
BJ2
BJ3
BJ4
G
N
D
+
V
s
V
c
c
P
W
R
B

O
U
T
A

O
U
T
OSC
5V
OUT
SIG
GND
HS28 HS28
GND
PWR
B OUT
A OUT
+Vs
S
I
G
N
C
IC1
SIG GND
SIG
GND
R3 R4
C4
C5
AC BACKPLATE
C1 C3
R
1
R
2
28
58 29
J1
13
+
I
N
E
/
A

+
I
N
E
/
A

-
I
N
E
/
A

O
U
T
J1,J2 NORMALLY REQUIRED
S
I
G

G
N
D
J2
DUT ON BOTTOM
RAMP2
RAMP1
Vcc
G
N
D
R
lim
R
lim
FIGURE 2:
FIGURE 3:
HS28 HEATSINK
No. 4 MOUNTING
HARDWARE
CURRENT LIMITING
SENSE RESISTOR
CAGE JACKS
SPACER GROMMET
PC BOARD
ACCESS HOLES
#4-40 x 1/4 SCREWS
HS26 HEATSINK
#8 - 10 x 1.0 SHEET METAL SCREWS
ALTERNATE MOUNTING
HARDWARE USING
HEX SPACERS
TERMINAL STRIP
DEVICE UNDER TEST
EK56
EK56U 585
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A
INTRODUCTION
linear power amplifers circuits using the MP108FD & MP111FD
pin out. With ample bread boarding areas it is fexible enough
evaluation kit can be made via the terminal block and terminal
pads at the edges of the circuit board. The terminal pads are
suitable for soldering standard banana jacks or direct wiring
of wires. Additionally, banana jacks and a BNC connector can
be inserted into the holes at the edge of the board and wired
to the numbered terminal pads.
PARTS LIST
Ref Apex Part # Description/Vendor Qty
NA HS28 Heat Sink 1
NA HS31 Heat Sink 1
NA MS11 Strip of 30 cage jacks 2
Micro Plastics
C1,4,5,6 OX7R105KWN 1uF Cap/ 4
Novacap
1825B105K201N
C2,3 EC03 680uF 200V/ 2
United Chemi-Con
KMH200VN681M25MX40T2
Isotek PBV-R050-1
Isotek PBV-R100-1
ASSEMBLY
MP108FD & MP111FD.
the "component side" or "DUT side".
2. Cut the MS11 into groups of 16 and 18 cage jacks and insert
from the "DUT side" of the board. On the "component side"
of the board, solder all cage jacks having solder pads (7, 9,
10, 23, 24, 26, 29, and 31 have no solder pads). Make sure
the cage jacks are fully seated before soldering. Be careful
that solder does not fow into the cage jacks. Remove the
unsoldered cage jacks with the carrier strip segments.
3. Solder the surface mount capacitors at C1, C4, C5, and C6
on the "component side" of the board.
4. Low ohm value resistors are provided with this evaluation
kit: 0.050 ohm and 0.100 ohm. These are used to implement
current limiting in the output circuit. Select the value most
appropriate for your application. Refer to the product data
sheet to determine which resistor value you should use.
5. Mount the HS28 heat sink to the PCB and solder the mount-
ing tabs of the heat sink.
using #4 screw and nut hardware (not supplied). Be sure
to cut off the excess resistor lead lengths.
"component side" of the PCB. Match the polarity markings
Be sure the capacitors have snapped into the PCB and
solder from the "DUT side" of the PCB. Be sure to fll the
holes with solder.
8. Mount the terminal strip to the "component side" of the PCB.
Make sure the terminal strip is fully seated and solder the
pins from the "DUT side" of the PCB. Be sure to fll the
9. Mount and wire the banana jacks and BNC connector (nei-
ther supplied) to the PCB pads at locations 1-5 as needed
or desired.
circuit using the pads and holes provided.
EK57
586 EK57U
EK57 MP108, MP111
MAY 2009
APEX EK57UREVC
Evaluation Kit for MP108FD and MP111FD
ASSEMBLY CONT.
15. Use #8 X 1" sheet metal screws (not provided) to mount
16. Inspect the assembly from the side and check that the PCB
is not bowed toward the heat sink. If the PCB is bowed use
a small tool to carefully pry the PCB away from the heat
sink until the PCB is fat.
OUT
OUT
C2
ASSESSORY TERMINALS
GND
30
-Vb
34
-IN
32
GND
33
+IN NC
31
5
4
2
3
1
TP BPLT
1
C5
2
26
+Ilim
28
C6
NC
29
-Ilim
27
R
LIM
+
C3
C4
-Vb
25
NC
24
NC
23
NC
NC CC1 +Vb CC2
3 4 5 6
+Vb NC NC
7 8 9 10
C1
+
-Vs
OUT
22 21
-Vs
OUT
20 19
-Vs
18 17
+Vs +Vs
OUT OUT
11 12 13 14
+Vs
15 16
-Vb
-Vs
GND
OUT
+Vb
+Vs
SPARE
TS1
EK57
EK57U 587
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FIGURE 2:
EK57
588 EK57U
D U T S I D E
TOP VIEW
BOTTOM VIEW
6.625
REF.
9.750
REF.
IC1
T
S
1
G
N
D
O
U
T
S
P
A
R
E
-
V
b
+
V
s
+
V
b
-
V
s
JACK
BANANA
JACK
BANANA
JACK
BANANA
JACK
BANANA
INPUT SIG
BNC
1
2
3
4
5
H
S
2
8
C2
+
+
C1
C3
C4
C5
C6
GND
GND
OUT
34
1
16
Cc
+Vb
+Vs
-Vb
-Vs
GND
SPARE
17
COMPONENT SIDE
DUT
ON BOTTOM
EVAL57 R-A
MICROTECHNOLOGY
5
Rlim
FIGURE 3:
SPACER GROMMET
CAGE JACKS
HS28 HEATSINK
TERMINAL STRIP
NO. 4 MOUNTING HARDWARE
PC BOARD
ACCESS HOLES
4-40 x 1/4 SCREWS
HS31 HEATSINK
NO. 8 or 10 x 1.0 SHEET METAL SCREWS
ALTERNATE MOUNTING
HARDWARE USING
HEX SPACERS
SURFACE MOUNT
CAPACITORS
CURRENT LIMITING SENSE RESISTOR
DEVICE UNDER TEST (DUT)
EK57
EK57U 589
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INTRODUCTION
of linear power amplifers circuits using the MP38CL-39CL
pinout. With ample bread boarding areas it is fexible enough
evaluation kit can be made via the terminal block and terminal
pads at the edges of the circuit board. The terminal pads are
suitable for soldering standard banana jacks or direct wiring
of wires. Additionally, banana jacks and a BNC connector can
be inserted into the holes at the edge of the board and wired
to the numbered terminal pads.
PARTS LIST
Ref Apex Part # Description/Vendor Qty
NA HS28 Heat Sink 1
NA HS18 Heat Sink 1
NA MS11 Strip of 30 cage jacks 1
Micro Plastics
C1-4 OX7R105KWN 1uF Cap/ 4
Novacap
1825B105K201N
C2,3 EC03 680uF 200V/ 2
United Chemi-Con
KMH200VN681M25MX40T 2
R
LIM
* CSR18 0.050 Ohm Resistor/ 1
Isotek PBV-R050-1
R
LIM
* CSR19 0.100 Ohm Resistor/ 1
Isotek PBV-R100-1
ASSEMBLY
MP38CL & MP39CL.
the "component side" or "DUT side".
2. Cut the MS11 into groups of 14 and 16 cage jacks and insert
from the "DUT side" of the board. On the "component side"
of the board, solder all cage jacks having solder pads (3,
5, 7-11, 21, 22, and 27 have no solder pads). Make sure
the cage jacks are fully seated before soldering. Be careful
that solder does not fow into the cage jacks. Remove the
unsoldered cage jacks with the carrier strip segments.
3. Solder the surface mount capacitors at C1, C4, C5, and C6
on the "component side" of the board.
4. Mount diodes at D1 and D2 and transorbs at D3 and D4
on the "component side" of the board (none supplied) as
needed by your application. See Application Note 1 para-
graphs 4.3 and 9.1.
"component side" of the PCB. Match the polarity markings
Be sure the capacitors have snapped into the PCB and
solder from the "DUT side" of the PCB. Be sure to fll the
holes with solder.
6. Low ohm value resistors are provided with this evaluation
kit: 0.050 ohm and 0.100 ohm. These are used to implement
current limiting in the output circuit. Select the value most
appropriate for your application. Refer to the product data
sheet to determine which resistor value you should use.
7. Mount the HS28 heat sink to the PCB and solder the mount-
ing tabs of the heat sink.
using #4 screw and nut hardware (not supplied). Be sure
to cut off the excess resistor lead lengths.
9. Mount the terminal strip to the "component side" of the PCB.
Make sure the terminal strip is fully seated and solder the
pins from the "DUT side" of the PCB. Be sure to fll the
10. Mount and wire the banana jacks and BNC connector
(neither supplied) to the PCB pads at locations 1-5 as
needed or desired.
circuit using the pads and holes provided.
EK59
590 EK59U
P r o d u c t I n n o v a t i o n F r o m EK59 MP38, MP39
MAY 2009
APEX EK59UREVB
Evaluation Kit for MP38CL and MP39CL
ASSEMBLY CONT.
16. Use #8 X 1" sheet metal screws (not provided) to mount
-IN +IN -Vb
CC1 +Vb
GND
1 2 3 4 5 6 7 8
27 28 25 26 24 23 20 19 29 30
-Vs
CC2 GND
-Vs -Ilim +Ilim
+
C1
C2
C4
+ C3
R
LIM
9 10
18 17
-Vs
NC NC
NC
11 12 13 14
15 16
+Vs +Vs +Vs
OUT OUT OUT
IQ
NC
SPARE
TS1
+Vs
+Vb
OUT
-Vs
GND
-Vb
C5
C6
1
2
3
4
5
ASSESSORY TERMINALS
NC NC
22 21
D4
D3
D1
D2
17. Inspect the assembly from the side and check that the PCB
is not bowed toward the heat sink. If the PCB is bowed use
a small tool to carefully pry the PCB away from the heat
sink until the PCB is fat.
EK59
EK59U 591
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FIGURE 2:
EK59
592 EK59U
6.25
4.69
D U T S I D E
IC1
T
S
1
G
N
D
O
U
T
S
P
A
R
E
-
V
b
+
V
s
+
V
b
-
V
s
JACK
BANANA
JACK
BANANA
JACK
BANANA
JACK
BANANA
INPUT SIG
BNC
1
2
3
4
5
C2
+
+
C1
C3
C4
C5
C6
GND
GND
OUT
30
1
14
Cc
+Vb
+Vs
-Vb
-Vs
GND
SPARE
15
COMPONENT SIDE
DUT
ON BOTTOM
EVAL59 R-A
MICROTECHNOLOGY
5
IQ
H
S
2
8
Rlim
GND
+
+
D2
D1
D3
D4
FIGURE 3:
DIODE
ACCESS HOLE
PC BOARD
SURFACE MOUNT
CAPACITOR
CAGE JACKS
SPACER GROMMET
ELECTROLYTIC
CAPACITOR
NO. 4 MOUNTING
HARDWARE
CURRENT LIMITING
SENSE RESISTOR
TERMINAL STRIP
HS28 HEATSINK
HS18 HEATSINK
NO. 8 X 1 SHEET METAL SCREWS
4-40 X 1/4 SCREWS
DEVICE UNDER TEST
EK59
EK59U 593
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EK60
594 EK60U
EK60 PA78EU
INTRODUCTION
The EK60 evaluation kit is designed to provide a convenient
way to breadboard design ideas for the PA78EU power opera-
tional amplifers. The EVAL60 evaluation board is pre-wired for
all required and recommended external components including
the ones for power supply bypassing, compensation and cur-
rent limiting. The EVAL60 also includes a breadboard area for
constructing your application circuit with provisions for a pre-
amplifer to drive the PA78 inputs.
PARTS LIST
HS27 Heatsink, Apex 1
EVAL60 PC Board, Apex 1
TW12 Thermal Washer, Apex 1 Box
OX7R105KWN 1 uF Cap 3530B105K501N 2
Novacap, 200V Breakdown
140-500N5-330J 33pF Cap CDR-500N5-330KS 1
XICON
146510CJ BNC Connector 3
MS02 Socket Strip 1 bag
MS11 Socket Strip 1 bag
EK60 SCHEMATIC
2
1
Jout
C
C
+ R
C
-
R
C
+
C
C
-
R
LIM
C
F
R
F
OUT
R
N
R
IN
IN+
IN-
C
N
+V
S
-V
S
C1
C2
+V
S
C
C
1+
C
R
2-
NC
C
R
1+
+IN
-IN
-V
S
NC
C
C
2-
OUT
I
LIM
1
2
3
4
5
6
7
8
9
10
11
12
P
A
X
X
E
U
R
C
+
R
C
-
2
1
J-
2
1
J+
R
S
C
S
-V
S
Jumper Cs to GND or -Vs for snubber if needed.
PACKAGE TAB CONNECTED TO STABLE REFERENCE
Breakdown voltage of C1 & C2 is 200V max.
C
T
ASSEMBLY
During assembly refer to Figure 1 and Figure 2.
1. Solder surface mount ceramic capacitors C4 and C5 on
the DUT side of the board.
2. Add components for compensation (CC-, CC+, RC- and
RC+) based on the closed loop gain and capacitive
load. Add the current limit resistor (RLIM) based on load
requirements (a minimum value of 4.5 ohms should be
used to protect the PA78 internal output devices). It is
recommended to use MSO2 sockets for the components
for quick component changes on the board. Add 33pF
capacitor (CT) between DUT pins 3 and 5.
3. While developing your application circuit you will probably
want to use the mating socket strip. Use the MS11 socket
strip for mounting the PA78 EU. Clip off the strip after the
12th position. Insert the strip into the circuit board on the
DUT side and solder one pin on the reverse side. Check
whether the mating socket strip is fully seated against the
circuit board and then solder the remaining pins. Insert
the amplifer fully into the socket strip, noting the pin 1
location on the amplifer and the circuit board.
4. For high power applications (see PA78EU datasheet for
SOA considerations) mount the heat sink (HS27) in the
outlined area on the circuit board.
5. If a heat sink is used, position the thermal washer behind
the amplifer in such a way that the hole on the washer
coincides with the hole on the tab and the heat sink.
6. For high slew rate performance connect the heat tab
to a stable reference (see PA78U datasheet for details).
7. Install the banana jacks for P1 (+Vs), P2 (-Vs) and P3
(GND) as shown in fgure 1 and 2. There are provisions
for two extra banana jacks (P4 and P5) and can be used
if desired for external connections.
Evaluation Kit for PA78EU Pin-Out
AUG 2009
APEX - EK60UREV4
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EK60
EK60U 595
5.50
4.00
TOP VIEW
BOTTOM VIEW
Figure 1: PCB Layout
P
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A
R
Y
EK60
596 EK60U
Figure 2: Assembled PCB
P
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A
R
Y
EK61
EK61U 597
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P r o d u c t I n n o v a t i o n F r o m EK61 PA78DK, PA79DK
Evaluation Kit for PA78DK & PA79DK
INTRODUCTION
Fast and easy breadboarding of circuits using the PA78DK or PA79DK is possible with the EK61 evaluation kit. The
EK61 includes both the universal EVAL36 board and the EVAL61 substrate. The use of EVAL36 and EVAL61 allows
for a large area of breadboarding space to work with while allowing a surface mount substrate for the PA78DK or
PA79DK. The PA78DK or PA79DK amplifer may be surface mounted directly to the EVAL61, a thermally conduc-
tive but electrically isolated substrate. The PA78DK or PA79DK is soldered to a DUT foil footprint area the size of
the heatslug as shown in Figure 1. The metal substrate is cost effective and can allow the PA78DK or PA79DK to
dissipate power up to the datasheet rating.
Part Number Alternate P/N Designator/Reference Quantity
C1206X103K631RT ECJ-3FB2J103K C1,C5,C9,C10 4
C1210N4R7C501N SQCB7M4R7CAJME C3,C4,C6,C7 4
C1206N330J 501RT 12067A330J AT2A C2,C8 2
R1206000ZRT ERJ -8GEYJ R00V J 2 (GND) 1
R1206302JRT ERJ-8GEYJ302V R1,R2,R3.R4 4
EVAL61 Evaluation substrate 1
EVAL36 Universal PC Board 1
TSM-116-01-T-SV Terminal Strip, 16 PIN 2
SSW-116-01-T-S Socket Strip, 16 PIN 2
PA79DK DUT 1
*031606 5V, 10mA, 3.4C/W
heatsink with fan, AAVID 1
* Parts are not supplied. Parts are application dependant. Suggested part numbers are provided.
Figure 1 - PCB
EK61
EVAL61 r 2A
C4
-VS (A)
16
14 GND
12 -IN_A
13
+IN_A 11
R2
15
10
9
GND
8
7
-VS_B
6
5
-IN_B 4
3 +IN_B
2
1
R3
C8 C6
C7
J1 J2
17
18
VOUT(A)
19
20 IL (A)
21
22 GND
23
24
+VS
25
26
VOUT(B)
27
28
IL(B)
29
30 +VS(B)
31
GND
32
(A)
C10
C5
R4
C1
C2
R1
C3
IC1
C9
DEC 2008
APEX - EK61UREVE
EK61
598 EK61U
All Apex Precision Power
TM
amplifers should be handled using ESD precaution.
Review the Apex Precision Power
TM
product datasheet and operating conditions.
Always provide the appropriate heat sinking. Power dissipation must be considered to ensure maximum junction
temperature (T
J
) is not exceeded.
Always use adequate power supply bypass capacitors, Apex Precision Power
TM
recommends at least 10F per
amp of output current.
Do not change connections while the circuit is powered
In case -Vs is disconnected before +Vs, a diode between -Vs and ground is recommended to avoid damage.
Initially set all power supplies to the minimum operating levels allowed in the product datasheet.
Check for oscillations up to and above the unity gain bandwidth of the amplifer.
ASSEMBLY
The PA78DK & PA79DK are surface mount device and should be assembled to the EVAL61 substrate using surface
mount processes. Solder paste may be dispensed or screen-printed on the DUT pads. The heat slug on the back
of the PA78DK & PA79DK provides maximum heat dissipation capabilities when soldered to the foil footprint area.
The PA78DK & PA79DK should be refowed to the substrate using a solder refow furnace. If this is not available, a
heat plate capable of solder refow temperatures may be used.
In accordance with the PA78DK and PA79DK datasheets, the package tab must be connected to a stable voltage
reference in order to achieve high slew rates. Jumpers J1 and J2 allow convenient connection of the tab to -Vs or
GND, respectively. Connect only one jumper to avoid a short circuit of the power supply.
Once the amplifer is mounted on the top of the substrate, the heat sink fan or selected heat sink can then be
mounted to the back of the substrate. A heat sink is not supplied with the kit, but several options are available
through AAVID Thermal Product, Inc. High thermal conductive thermal grease should be used when mounting the
heat sink fan or heat sink to the evaluation board.
Review Figure 3 on next page for other possible assembly methods to construct this evaluation kit.
NOTE: All grounds must be tied together on the EVAL36 board.
Figure 2 - Schematic
-VS (A)
16
8
+IN_B
9
CR+_B
10
CR-_B
4
CR+_A
5
CC+_A
6
-VS_B
7
-IN_B
1
-IN_A
2
+IN_A
3
CR-_A
11
CC+_B
12
+VS_B
13
CC-_B
14
IL_B
15
VOUT_B
16
+VS_A
17
IL_A
18
VOUT_A
19
CC-_A
20
-VS_A
PA78_79DK
IC1
IL (A)
20
VOUT(B)
26
C7
GND
22
+VS (A)
24
IL (B)
28
+VS (B)
30
GND
32
C8
VOUT(A)
18
C2 R1
C6
C9
R4
-IN_B
4
C10
C1
C5
GND
14
+IN_A
11
C3
R3
R2
C4
-IN_A
12
-VS_B
6
GND
8
+IN_B
3
HEAT TAB
J2 J1
EK61
EK61U 599
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A
E K 6 1
E V A L 6 1 r 2 A
C 4
R 2
R 3
C 8 C 6
C 7
- V S
G
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D
C 1 0
C 5
R 4
C 1
C 2
R 1
C 3
I C 1
C 9
BOT. SIDE
0.00
0
.
0
0
4.50
6
.
5
0
2
.
4
0
3
.
9
0
0.90
2.90
EVAL36 TOP
DETAIL A
DETAIL A
EVAL36
031606
(NOT INCLUDED)
EVAL61
SSW-116-01-T-S
TSM-116-01-T-SV
PA78DK OR PA79DK
Figure 3 - Assembly
EK65
600 EK65U
EK65 MP400
Evaluation Kit for MP400FC
Introduction
The EK65 Evaluation kit is designed to provide a convenient way to breadboard and evaluate design ideas for the
MP400FC power operational amplifer. The evaluation board is pre-wired for all required external components. The
evaluation board has been laid out and labeled to easily confgure the high voltage operational amplifer in a non-
inverting differential confguration for single supply operation using the MP400FC boost supply (Refer to Application
Note 21). However, the evaluation board is fexible enough to analyze a multitude of standard or proprietary circuit
confgurations.
Before You Get Started
Please read this data sheet in its entirety before starting to construct your evaluation board.
All APEX amplifers should be handled using proper ESD precautions.
Initially set all power supplies to the minimum operating voltage allowed in the device data sheet.
The MP400FC is a high voltage amplifer with an integrated switch mode power supply. Though the input
voltage will be 50V or less, the MP400FC can generate voltages greater then 350V. The high generated
voltage will be present on the evaluation board. Caution must be used when working with the evaluation
board.
Figure 1 - EK65 Schematic
Parts List (Included with kit)
Ref. Apex P/N Description/Vendor Qty.
N/C HS26 Heat Sink 1
N/C MS11 Strip of 30 cage jacks 2
N/C EVAL65 PC board 1
N/C 93505A430 Hex standoff, 4-40x1/4 4
N/C 90272A105 Screw, 4-40x3/16 4
BJ1-6 571-0100 Banana Jack, PC 6
BN1 146510CJ BNC, PC mount 1
C1 ZX7R105KTL Cap. 1 F, 500V 1
Novacap
ST2225B105K501LLXW
Cb1 EKMQ401VSN121MP30S Cap. 120F, 400V 1
Rtrim T93YA203KT20 Trim Pot, 20K 1
+
+
+
+
+
+
+
Ro1 Rb1 Ro4 Ro3 Ro2
Rf
Rin+
Cc Cc+ Rb2 Rin
J2
Rf+
PWR GND
Input
Vs
Analog GND
Input
Cin
100F
Rset
Rtrim
20K
Vin
Vin
Out
Analog GND
Load
C1
1F
J1
L1
Rcl
X1
Rs
20
Cs
1.5nF
Cb1
Cb4
Cb3
Cb2
CC
Vin
Vbias
Vin
PGND
Rset
AGND
CC+
CR+
CR
+IN
IN
Vs
PGND
PGND
PGND
PGND
PGND
PGND
PGND
Vin
Vin
Out
ILIM
Q2D
LFin
VBoost
+Vs
Q2D
Q2D
Q2D
MAY 2008
APEX - EK65UREVA
EK65
EK65U 601
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Required Components (Not included with kit)
Ref. Description
Cin Capacitor, Low ESR electrolytic, 100F or greater with voltage rating greater then the anticipated input volt-
age.
Cb1-4 Cboost capacitor, Low ESR electrolytic with voltage rating greater then the anticipated boost voltage. Refer
to the MP400FC data sheet for Cboost selection. One 120F, 400V electrolytic capacitor (Cb1) is supplied
with the kit and is adequate for most applications. The value of Cboost is selected to meet required boost
supply ripple voltage specifcations for the application and to minimize switching noise on the boost supply.
Cboost will be as large as reasonably possible, in the range of 100F to 500F. An area on the evaluation
board large enough for 4 parallel 22mm diameter capacitors is provided. This allows maximum fexibility in
the select of the capacitors for Cboost. Capacitors with snap in terminals should still be soldered to the evalu-
ation board to minimize resistance.
Rset Boost voltage programming resistor. Refer to the MP400FC data sheet for calculation of Rset. Select a
higher standard value resistor and use Rtrim (supplied) to calibrate the boost voltage to the exact desired
value. Alternatively, Rtrim can be used alone for a fully adjustable boost supply.
Rcl Operational amplifer current limit resistor. Refer to the MP400FC data sheet for selection of the current limit
resistor.
Optional Components (Not included with kit)
Ref. Description
Lf Boost supply flter inductor. The MP400FC includes a 47H inductor in series with the LFin pin and the +Vs
supply of the high voltage op amp. This on board inductor forms a 2 pole LC flter with C1 and an on board
parallel 0.1F capacitor. Combined with a properly selected Cboost, the high voltage DC boost voltage
will be sffciently clean for most applications. However an external inductor between Vboost and LFin, or
Vboost and +Vs can be used for additional fltering of the Boost supply voltage if necessary. Addition capaci-
tance can be added to the flter between +Vs and AGND.
Cs, Rs Also useful for boost supply fltering. These components form an RC snubber from drain to source
of the boost supply MOSFET switch. This snubber will help reduce or eliminate overshoot and ringing of
the MOSFET switch at switch turn-off that can appear on the boost supply voltage. The component values
shown on the schematic are adequate for most applications but can be adjusted for your specifc application.
The power in the resistor can be estimated by the formula PD = F*C*V2, where
F = 100 KHz of the switching supply
C = the value of Cs
V = the anticipated Vboost voltage.
Rs must be non-inductive. MP900 and MP9000 series resistors from Caddock Electronics or equivalent
resistors can be used.
Rs may require a heat sink such as Apex part number HS28 or HS23. Mounting holes for a heat sink are
provided on the evaluation board that will accommodate either of these heat sinks.
Cc+, Cc- High voltage op amp compensation capacitors. Refer to the MP400FC data sheet for component selec-
tion.
Ro1-4, Rf+, Rf-, Ri+, Ri- Op amp gain setting and input bias resistors used for the single supply differential con-
fguration described in applications note 21. Appendix A of apps note 21 provides a procedure for the design
of the differential confguration and selection of these components. Apps note 21 can be down loaded from
the Apex web site. The locations on the board for Ro1-4 are large enough for up to a 3W resistor. 3W 1%
resistor style CPF from Vishay Dale are widely available through distribution. RN60, RN65 or RN70 style
1/2W 1% resistors can be used for the other resistors.
Assembly
During assembly, refer to Figure 1, Figure 2 and the MP400FC data sheet.
1. Note that the silk screen side of the circuit board is labeled as the component side. The other side of the
circuit board will be referred to in these instructions as the DUT side of the board.
EK65
602 EK65U
2. The Analog ground AGND and power ground
PGND are clearly labeled on the boards. All
components for the on board boost supply are
referenced to PGND, and all components for the
high voltage op amp are referenced to AGND.
The board has been designed to keep switch-
ing currents from the boost supply out of the
analog ground. AGND and PGND are common
at only one point on the MP400, and are not con-
nected at all on the evaluation board. To avoid
ground loops and switching currents in the analog
ground, avoid making any connections between
these two ground references at the board level.
Note the dashed line on the component side of
the board showing the dividing line between the
analog ground side of the board and the power
ground side.
3. Cut one of the MS11 strips to a length of 20 cage
jacks and the other MS11 to a length of 22 cage
jacks. From the DUT side of the board, insert the
strips into the appropriate row of holes for the
DUT pins. On the component side of the board,
solder all cage jacks having solder pads (pins 3,
5, 7, 9, 11, and 16 have no solder pads). Make
sure the cage jacks are fully seated before solder-
ing. Be careful that solder does not fow into the
cage jacks. Remove the unsoldered cage jacks
with the carrier strip segments.
4. Solder the ZX7R105KTL surface mount capacitor
at C1 on the component side of the board.
5. Insert BJ1 BJ6 from the component side of the
board as desired for your application. The banana
jack locations are labeled with the associated
input or output. BJ1 is provided for use as an
input for a negative bias supply voltage to Vs for
bipolar supply operation. It also could be used as
an alternative to the BNC connector for the input
signal or other inputs to your application circuit. If
you do not anticipate using BJ1 it should be left off. Solder the banana jacks to the board from the DUT side.
6. Insert the BNC connector BN1 from the component side of the board. Solder to the board from the DUT side.
BN1 can be left off if you do not intend to use it for an input to your circuit.
7. Select and insert Rset from the component side of the board at the location shown near pin 34 of the DUT
and solder from the DUT side. Rtrim may be installed for calibration of the boost supply voltage or as an alter-
native to Rset. If installed as shown on the board with the knob toward Cin, a CW turn will increase Vboost
and a CCW turn will decrease Vboost.
8. Select and insert Rcl from the component side at the location marked for Rcl between pins 1 and 2 of the
DUT. Solder from the DUT side.
9. Select and insert other components as required for your application. J1 is required to supply Vboost to the
high voltage op amp through the on board 47H flter inductor. Vboost can be jumpered to the +Vs pin if the
flter is not to be used. Alternatives are to replace the jumper with an external inductor between the Vboost
pin and LFin or +Vs. A flter capacitor can be added between +Vs and AGND. You may want to start with J1
as shown and try other options as you are evaluating your design.
C1
Rset
Rtrim
R
c
l
J 1
C
c
+
C
c
-
Rf+
Rf-
AGND PGND Vin
J 2
S
in
g
le

s
u
p
p
ly
c
o
n
f
ig
u
r
a
t
io
n
IC1
Rin-
Rin+
N
o
n
-
in
v
e
r
t
in
g
c
o
n
f
ig
u
r
a
t
io
n
s
h
o
w
n
AGND
Input
R
o
1
R
o
2
R
o
3
R
o
4
Out
V
in
P
G
N
D
C
s
Rs
H
S

m
o
u
n
t
in
g

h
o
le
s
B
J
1
B
N
1B
J
2
B
J
3
B
J
4
B
J
5
Component Side
1
20
21
42
+
V
s
L
f
Vboost
Rb2
Cin
+
Rb1
AGND
B
J
6
++++
Cb1 Cb2 Cb3 Cb4
AGND
Do not connect
AGND &PGND.
See datasheet
EVAL65 REV 1
5.50
4.61
TOP VIEW
BOTTOM VIEW
Figure 2 - EVAL65 PCB Layout
EK65
EK65U 603
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10. J2 is required to connect the high voltage op amp Vs to AGND for single supply operation. If an external
negative supply voltage will be used, replace J2 with a high quality ceramic bypass capacitor of at least 1F,
and jumper Vs to BJ1. BJ1 can be used to connect the negative supply to the evaluation board.
11. Rin+ and Rin- when installed as marked on the component side of the board near BJ1 and BN1, will con-
fgure the op amp in the non-inverting confguration with Rin- to AGND and Rin+ to the input BNC. For an
inverting confguration, rotate Rin+ to AGND and Rin- to the input.
12. If the snubber Cs and Rs will be used, select and insert the components at the location marked near DUT
pins 12 15. If the calculated power dissipation indicates that a heat sink is required for Rs, install it with Rs.
Cs and Rs can be installed after you have started evaluating your design if they are found to be needed.
13. Vin power can be supplied to your circuitry in the breadboard area. There are two pads located below the
breadboard area near BN1. One labeled Vin and one labeled PGND can be jumpered into your circuit as
needed.
14. Mount the electrolytic capacitors at Cin, and Cboost from the component side of the PCB. Match the polarity
markings on the PCB. Solder from the DUT side of the PCB. Be sure to fll the holes with solder.
15. Apply a thin, uniform layer of thermal grease to the back side of the MP400FC. Position the amplifer over the
mounting holes of the HS26 heat sink. Firmly push the amplifer onto the heat sink while slightly rotating the
amplifer back and forth, ending with the mounting holes of the amplifer over the mounting holes in the heat
sink.
16. Attach the amplifer to the heat sink with the supplied 4-40 x 1/4 male-female hex spacer. Tightened with a
hex nut driver. Make the hex spacers snug but do not over tighten as this provides no beneft and may break
the hardware.
17. Carefully lower the PCB assemblies onto the heat sink/amplifer assembly until the pins of the amplifer
engage in and are fully seated in the cage jacks aligning the mounting holes in the PCB to the hex spacers.
Use the supplied 4-40 x 3/16 screws to attach the PCB assembly to the hex spacers.
18. Hook up power and signals as necessary. The amplifer is now ready for testing.
Figure 3 - EK65 Assembly
EK71
604 EK71U
EK71 PA107DP
Evaluation Kit for the PA107
INTRODUCTION
The EK71 Evaluation kit is designed to provide a convenient way to breadboard and evaluate design ideas for the
PA107 power operational amplifer. The evaluation board is pre-wired for all required external components. The
evaluation board has been laid out and labeled to easily confgure the high voltage operational amplifer in an invert-
ing confguration. However, the evaluation board is fexible enough to analyze a multitude of standard or proprietary
circuit confgurations. Components not usually readily available in engineering labs are provided. External connec-
tion to the evaluation kit can be made via the terminal connectors at the edge of the circuit board. These connectors
are suitable for standard banana plugs. The schematic is shown in Figure 1.
FIGURE 1 EK71 Schematic
PARTS LIST
146510CJ Connector, BNC, PCB Mount 1
571-0100 4mm Black PCB Socket Single 10
EC03 Capacitor, 680 F 2
EVAL71 PC Board 1
HS20 Heatsink 1
OX7R105KWN Cap, 1F 4
TW07 Thermal Washer, PSIP 1
P8
Vee
GND
P10
RT1
49.9
Select for Gain
RFB
P7
-Vs
P9
GND
P5
OUT
P6
-Vsp
1
2
+V
P3
+Vs
P4
+Vsp
8
9
4
+
2
11
1
-
12
10
3
PA107
1
2
-V
P2
Vcc
1.00K
RIN
BNC
P1
Select for Response
CFB
Select for Response
CSJ
1.0uF
25V
C8
1.0uF
200V
C7
1.0uF
C2
200V
1.0uF
C1
25V
680uF
C4
200V
1.0uF
C3
200V
1.0uF
200V
C5
680uF
200V
C6
APR 2009
APEX EK71UREV1
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EK71U 605
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Please read this data sheet in its entirety before starting to construct your evaluation board.
All Apex Precision Power amplifers should be handled using proper ESD precautions.
Initially set all power supplies to the minimum operating voltage allowed in the device data sheet.
Always use adequate power supply bypass capacitors, Apex Precision Power recommends 1F ceramic in par-
allel with at least 10F per ampere of output current electrolytic/tantalum.
Always provide the adequate heat sinking. Power dissipation must be considered to ensure maximum junction
temperature is not exceeded.
ASSEMBLY
1. See Figure 1 and Figure 2. Solder the surface mount ceramic capacitors to the DUT side of the circuit board at
C2, C7, C5 and C3.
2. C1 and C8 are user supplied pin-through-hole bypass capacitors for Vcc and Vee respectively. Insert C1 and C8
from the component side and solder from the circuit side.
3. Solder the electrolytic capacitors to the circuit board at C4 and C6. Match the polarity markings on the circuit
board with those on the capacitor body.
4. Clip off the mating socket strip after the 12th position. Insert the strip into the circuit board from the DUT side and
solder one pin on the reverse side. Check that the mating socket strip is fully seated against the circuit board
then solder the remaining pins. Insert the amplifer fully into the mating socket strip, noting the pin 1 locations on
the amplifer and the circuit board.
5. Examine the large heat sink. Notice that there are several holes in the face of the heat sink. These are for mount-
ing various Apex Precision Power amplifer models. The circuit board aligns the amplifer with the correct mount-
ing hole once the heat sink is attached to the circuit board.
6. The four holes at the corners of the circuit board are for mounting #6 standoff spacers if desired. The remaining
two slotted holes are for mounting the large heat sink to the DUT side of the circuit board. Temporarily mount
the heat sink with 2 #6 x 1/2 self tapping screws from the opposite side of the circuit board. Do not fully tighten
the screws at this time. Check for alignment of the slot in the mounting tab of the amplifer with a hole in the heat
sink. Dismount and rotate the heat sink if necessary to achieve an alignment with a hole in the heat sink. Position
the heat sink so that the back of the amplifer mounting tab is fush with the heat sink then tighten the heat sink
mounting screws.
7. Hang the thermal washer near the end of a 6-32 x 1/2 screw. Slightly pull the amplifer away from the heat sink
face. Use the screw to position the thermal washer behind the amplifer and insert the screw into the mounting
hole of the heat sink. Secure the screw from the opposite side of the heat sink using a nut holder.
8. To select the values of feedback resistor (RFB), feedback capacitor (CFB) and summing junction capacitor
(CSJ), please refer to the section titled FEEDBACK CONSIDERATIONS in the PA107DP data sheet.
9. Add other components as necessary to complete your application circuit. P
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FIGURE 2 - EK71 Assembly
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FIGURE 3 EVAL71 PCB Layout
TOP SIDE
BOTTOM SIDE
5.900
3.625
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EK-SA50
608 EK-SA50U
EK-SA50 SA50CE
INTRODUCTION
Fast, easy breadboarding of circuits using the SA50 are pos-
sible with the EVAL05 PC board. Mounting holes are provided
tion and testing. Components are labeled on both sides of the
board for ease in probing.
C2, C3, C4 Power supply bypass capacitors
R3, R4 Resistor divider to set the input voltage at 50%
of Vcc under nominal conditons
R5, C1 Snubber network
R1, R2 Current sensing resistors or jumpered to
ground
PARTS LIST
EVAL05 P.C. Board 1
HS14 Heatsink 1
TW03 Thermal Washers 1 bag of 10
NOTE: Illustration only, not to exact scale.
5.2"
132.1mm
3"
76.2mm
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EVAL05 R-C
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5

R
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RSENSE A
B OUT
+V
S
+
A OUT
INPUT
GND
SA50
TO-3
VCC
R3
10K
1/4W
R5
100
2W
C4
6.8F
POLY
* D
1
and D
2
Input protection, high speed such as IN4148.
D
3
through D
6
Flyback protection, high speed (<200nS).
Solder as close to SA50 as possible.
INPUT
VCC
A OUT
B OUT
*D
6
+Vs
C2
22F
TANT
C3
0.1F
R1
0.1 3W
R2
0.1
3W
C1
1000pF
R4
10K
1/4W
RSENSE B
8
7
6
5
1
2
3
4
J2
J1
*D
4
*D
3
*D
2 *D
1
*D
5
Evaluation Kit for SA50
EK-SA50 P r o d u c t I n n o v a t i o n F r o m
MAY 2009
APEX EK-SA50UREVE
DB53R
DB53RU 609
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DB53R SA53-IHZ
Demonstration Board for the SA53-IHZ
DB53R P r o d u c t I n n o v a t i o n F r o m
INTRODUCTION
The DB53R is designed to demonstrate the capabilities of the SA53 DC brush motor driver IC. This fully assembled
demonstration allows the user to directly control the speed and direction of the motor. An onboard circuit controls
the direction and provides four quadrant PWM signals to control the power outputs of the SA53. LEDs provide feed-
back for motor control status and fault indications. Provisions on the DB53R allow the user to bypass the onboard
control circuit and directly interface with the SA53 motor driver.
The DB53R demonstrates proper layout techniques for the
SA53 high current switching amplifer. The economical con-
struction uses only a two-sided PCB and allows the SA53 to
deliver peak power of over 500W.
THERMAL CONSIDERATIONS:
The SA53 is available in a surface mount package which
can deliver peak power of over 1kW. This presents an obvi-
ous and signifcant thermal challenge. The DB53R offers
a compact design which can deliver 17A peak current by
using a patent pending mounting technique. Mounting the
SA53 in an inverted fashion as shown in Figure 1 reduces
the profle height of the assembly and provides a direct in-
terface between the thermal tab of the PowerQuad package
(package outline drawing HQ) and the small HS33 heatsink.
The DB53R assembly can dissipate 7-9W in still air at 25C
ambient temperature, depending on the orientation of the
heatsink fns.
CIRCUIT OPERATION
The DB53R control circuit receives power via two terminal
block connections. The Vs connection supplies power to
drive the motor and must be above the under-voltage lock-
out threshold of the SA53, approximately 8.3V. The control
circuit requires 12V for proper operation a regulator on the
DB53R provides the 5V logic supply for the SA53. There are
no special considerations for sequencing the two supplies.
Figure 2 (next page) shows the user control features of the
DB53R. The PWM duty cycle is controlled with the poten-
tiometer (1 in fgure 2). The power LED (2) will illuminate
when the 12V supply is connected. The DB53R will power up
with the SA53 disabled. The enable button (3) will toggle the
SA53 on and off with the LED (4) illuminating to indicate the
enable status. Direction of the motor is similarly controlled
with the button (5) and is indicated by the LED (6).
Figure 1 Mounting Technique
PATENT PENDING
JUL 2009
APEX DB53RUREV1
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610 DB53RU
The DB53R monitors the Temperature warning status pin
of the SA53. If this pin goes high an LED (7) illuminates
and the enable circuit is forced to a disable status. The
temperature LED is not latched and may stay illuminated
only briefy while the temperature of the SA53 is above
135C. The temperature decrease rapidly via the heatsink
once the SA53 is disabled.
The SA53 current limit feature is set to limit at approxi-
mately 5A to provide a demonstration of the full capabili-
ties of the SA53. An LED (8) will illuminate if the SA53
cycle-by-cycle current limit circuit engages. The thermal
and current limit features are robust, but will not protect
the SA53 in all circumstances. The user must consider
the worst case thermal and power dissipation conditions.
Push-button switches 1 and 2 trigger latches (U4) for di-
rection and enable control, respectively. Diodes D7 & D8
and resistors R24, 25, 29 & 30 provide a means of by-
passing the DB53R control circuit. The 5V regulator, U3,
provides 5V to the SA53, the latches and the status LEDs.
Figure 3 Schematic
2
10
5
6
4
8
3
1
11
7
Figure 2 User Control Features
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DB53RU 611
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ENHANCING & BYPASSING THE DB53R CONTROL CIRCUIT:
Connector J5 allows the user to bypass many of the manual control features of the DB53R. A signal generator can
control the duty cycle with a 2.5 to 7.5V signal, overriding the control potentiometer. A rising 5V edge on pin 3 or 4 of
connector J5 will toggle the Direction or Enable latches, respectively. By jumping resistors R24 & R25, the latches
are bypassed completely and the logic signals on pins 3 & 4 will directly control the direction and enable functions of
the DB53R. With these resistors jumped, the direction and enable LEDs will not represent the states of the DB53R
and the pushbuttons will have no effect on the operation. The Temperature disable feature of the DB53R will also
not function, although the LED will continue to provide over-temperature status.
Connector J4 is connected directly to the PWM input pins of the SA53. This connector may be used to monitor the
signals or to bypass the control IC on the DB53R. The enable function is not controlled via these pins, although
pulling all four input pins low provides the same effect. The Enable pushbutton and the connection via J5 are also
effective as previously described. The circuit shown in fgure 3 in the dashed box is a simple circuit that allows the
user to monitor and control the enable or direction status remotely. Either feature can be toggled on the falling edge
of the signal at the node labeled TOGGLE.
A simple two layer construction is suffcient because of the convenient pinout of the SA53 PowerQuad package.
Input signals are routed into one side of the package and high power output signals are routed from the other side in
2 ounce copper. This eliminates the need to route control signals near motor connections where noise may corrupt
the signals. Filling top and bottom layers with copper reduces inductive coupling from the high current outputs. 1nF
capacitors with excellent high frequency characteristics bypass the Vs motor supplies on each phase. Two 150F
electrolytic capacitors provide a local, low inductance source to accommodate surge currents. Six 100V Schottky
diodes conduct the commutation current via low forward voltage paths which reduces the power dissipation in the
SA53. These diodes are rated for 5A continuous and are mounted close to the SA53 to reduce inductance in the
commutating current loop. For applications with continuous currents less than 5A, the Schottky diodes may not be
necessary if the higher forward voltage internal body diodes and the associated power dissipation are manageable
during commutation cycles.
Figure 4 (next page) shows the top and bottom layouts of the DB53R. Gerber fles for the circuit board are available
upon request.
BILL OF MATERIALS
Designation Description P/N
C1,C18 CAP, 1.0uF, 16V Kemet, C0805C105K4RAC
C13 CAP, 33pF, 50V Kemet, C0603C330J5GACTU
C2,C3 CAP, 1.0nF,100V Kemet,C0805C102J1GACTU
C5,C6 CAP, 150uF, 100V Panasonic, EEVFK2A151M
C7,C8,C14,C15,C16 CAP, 0.1uF,16V GRM188F51C104ZA01D
C12,C17 CAP, 2.2nF,50V GRM188R71H222KA01D
D1,D2,D3,D5,D6 Diode, 5A Schottky Diodes Inc., DS5100
D7,D8,D9 IN4148 Vishay, 1N4148WS-V-GS08
J4 Conn, 6 pin .100 ctrs Samtec, TSM-106-01-T-SV
J5 Conn, 4 pin .100 ctrs Samtec, TSM-104-01-T-SV
LED1-5 LED, Red Lite-On, LTST-C190CKT
Q1,Q2 XTR, NPN MMBT3904
R11,R13 RES 3.74K, 1% Vishay,CRCW06033K74FKEA
R24,R25 RES, 6.8K Vishay,CRCW06036K80FKEA
R26,R27 RES, 10K Vishay,CRCW060310K0FKEA
R18,R19,R20,R21,R32 RES, 1.0K, 5% RK73B1JTTD102J
R7,R31 RES, 24.9K,1/10W, 1% RK73H1JTTD2492F
R8 POT, 20K muRata, PVG3A203C01
R9,R10,R16,R17,R22,R23 RES, 4.99K CRCW06034K99FKEA
SW1,SW2 Pushbutton, SPST-NO Panasonic, EVQ-Q2B01W
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DB53R
612 DB53RU
TB1,TB2 Terminal Block, 3 pin, 5mm On Shore Tech, OSTTA034163
Thermal Grease Heatsink compound N/A
U1 SA53-IHZ Apex Precision Power, SA53-IHZ
U2 UCC3626 Texas Instruments, UCC3626PW
U3 LM78L05 National Semiconductor, LM78L05ACMX/NOPB
U4 74AC74 Texas Instruments, SN74AC74PW
Heatsink Apex Precision Power, HS33
PCB, 1.75 x 3.75 Apex Precision Power, DB53R
Screw, #4-40 x N/A
Figure 4 PCB Layout (not to scale)
TOP SIDE
BOTTOM SIDE
3.888
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DB53RU 613
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DB53R QUICK START GUIDE
1. Connect the following:
Connection Location Indicator Comment
Vs TB2-3 9-60V
Ground TB2-2
Vctrl TB2-1 LED 2 12V
Motor Phase A TB1-1
Motor Phase B TB1-2

2. Apply 12V to Vctrl. LED 2 should light.
3. Apply voltage to Vs based on rated motor voltage, normally 12-48V.
4. Press ENABLE switch 3. LED 4 will light and motor should start.
ORDERING INFORMATION
DB53R Demonstration Board includes one populated DB53R PCB and one SA53-IHZ sample.
IMPORTANT NOTICE
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, Apex and Apex Precision Power are trademarks of Cirrus Logic, Inc. All other brand and product names in
this document may be trademarks or service marks of their respective owners.
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DB63R
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P r o d u c t I n n o v a t i o n F r o m DB63R SA57-IHZ
INTRODUCTION
The DB63R is designed to demonstrate the capabilities of the SA57 DC brush motor driver IC. This fully assembled
demonstration allows the user to directly control the speed and direction of the motor. An onboard circuit controls
the direction and provides four quadrant PWM signals to control the power outputs of the SA57. LEDs provide feed-
back for motor control status and fault indications. Provisions on the DB63R allow the user to bypass the onboard
control circuit and directly interface with the SA57 motor driver.
struction uses only a two-sided PCB and allows the SA57 to
deliver peak currents of over 1kW.
THERMAL CONSIDERATIONS:
ous and signifcant thermal challenge. The DB63R offers a
compact design which can deliver 17A peak current by using
a patent pending mounting technique. Mounting the SA57 in
an inverted fashion as shown in Figure 1 reduces the pro-
fle height of the assembly and provides a direct interface
between the thermal tab of the PowerQuad package (pack-
age outline drawing HQ) and the small HS33 heatsink. The
DB63R assembly can dissipate 7-9W in still air at 25C ambi-
ent temperature, depending on the orientation of the heatsink
fns. To use the DB63R in higher power applications, use a
fan or mount a heatsink with larger thermal mass. Although
the SA57 is rated for operation from -25 to +85C, the other
components on the DB63R are limited to 0 to 70C ambient
temperature.
CIRCUIT OPERATION
DB63R provides the 5V logic supply for the SA57. There are
no special considerations for sequencing the two supplies.
Figure 2 (next page) shows the user control features of the
DB63R. The PWM duty cycle is controlled with the poten-
tiometer (1 in fgure 2). The power LED (2) will illuminate
when the 12V supply is connected. The DB63R will power up
with the SA57 disabled. The enable button (3) will toggle the
PATENT PENDING
FEB 2009
APEX DB63RUREVA
DB63R
DB63RU 615
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The DB63R monitors the Temperature warning status pin
of the SA57. If this pin goes high an LED (7) illuminates
and the enable circuit is forced to a disable status. The
temperature LED is not latched and may stay illuminated
only briefy while the temperature of the SA57 is above
135C. The temperature decrease rapidly via the heatsink
Push-button switches 1 and 2 trigger latches (U4) for di-
rection and enable control, respectively. Diodes D7 & D8
and resistors R24, 25, 29 & 30 provide a means of by-
passing the DB63R control circuit. The 5V regulator, U3,
provides 5V to the SA57, the latches and the status LEDs.
Figure 3 Schematic
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DB63R
616 DB63RU
ENHANCING & BYPASSING THE DB63R CONTROL CIRCUIT:
pulling all four input pins low provides the same effect. The Enable pushbutton and the connection via J5 are also
Input signals are routed into one side of the package and high power output signals are routed from the other side
in 2 ounce copper. This eliminates the need to route control signals near motor connections where noise may cor-
rupt the signals. Filling top and bottom layers with copper reduces inductive coupling from the high current outputs.
1nF capacitors with excellent high frequency characteristics bypass the Vs motor supplies on each phase. Two
150F electrolytic capacitors provide a local, low inductance source to accommodate surge currents up to 17A.
Six 100V Schottky diodes conduct the commutation current via low forward voltage paths which reduces the power
dissipation in the SA57. These diodes are rated for 5A continuous and are mounted close to the SA57 to reduce
inductance in the commutating current loop. For applications with continuous currents less than 5A, the Schottky
diodes may not be necessary if the higher forward voltage internal body diodes and the associated power dissipa-
tion are manageable during commutation cycles.
Figure 4 (next page) shows the top and bottom layouts of the DB63R. Gerber fles for the circuit board are available
upon request.
BILL OF MATERIALS
C13 CAP, 33pF, 50V Kemet, C0603C330J 5GACTU
C2,C3 CAP, 1.0nF,100V Kemet,C0805C102J 1GACTU
C7,C8,C14,C15,C16 CAP, 0.1uF,16V GRM188F51C104ZA01D
C12,C17 CAP, 2.2nF,50V GRM188R71H222KA01D
D1,D2,D3,D5,D6 Diode, 5A Schottky Diodes Inc., DS5100
J 4 Conn, 6 pin .100 ctrs Samtec, TSM-106-01-T-SV
J 5 Conn, 4 pin .100 ctrs Samtec, TSM-104-01-T-SV
LED1-5 LED, Red Lite-On, LTST-C190CKT
R11,R12,R13 RES 2.0K, 1% Vishay,CRCW06032K00FKEA
R18,R19,R20,R21,R32 RES, 1.0K, 5% RK73B1JTTD102J
R7,R31 RES, 24.9K,1/10W, 1% RK73H1J TTD2492F
R9,R10,R16,R17,R22,R23 RES, 4.99K CRCW06034K99FKEA
TB1,TB2 Terminal Block, 3 pin, 5mm On Shore Tech, OSTTA034163
DB63R
DB63RU 617
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PCB, 1.75 x 3.75 Apex Precision Power, EVAL69R
Screw, #4-40 x N/A
TOP SIDE
BOTTOM SIDE
3.888
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DB63R
618 DB63RU
DB63R QUICK START GUIDE
Vs TB2-3 9-60V
Ground TB2-2
Motor Phase A TB1-1
Motor Phase B TB1-2

DB63R Demonstration Board includes one populated EVAL69R PCB and one SA57-IHZ sample.
IMPORTANT NOTICE
DB64R
DB63RU 619
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DB64R SA306-IHZ
INTRODUCTION
The DB64R is designed to demonstrate the capabilities of the SA306 3 phase brushless DC (BLDC) motor driver
IC. This fully assembled demonstration allows the user to directly control the speed and direction of the motor. An
onboard controller decodes HALL Effect sensor inputs for commutation in either direction and provides four quad-
rant PWM signals to control the power outputs of the SA306. LEDs provide feedback for motor control status and
fault indications. Provisions on the DB64R allow the user to bypass the onboard control circuit and directly interface
with the SA306 brushless motor driver.
struction uses only a two-sided PCB and allows the SA306
to deliver peak currents of over 1kW.
ous and signifcant thermal challenge. The DB64R offers a
compact design which can deliver 17A peak current by using
a patent pending mounting technique. Mounting the SA306
in an inverted fashion as shown in Figure 1 reduces the pro-
fle height of the assembly and provides a direct interface
between the thermal tab of the PowerQuad package (pack-
age outline drawing HQ) and the small HS33 heatsink. The
DB64R assembly can dissipate 7-9W in still air at 25C am-
bient temperature, depending on the orientation of the heat-
sink fns. To use the DB64R in higher power applications,
use a fan or mount a heatsink with larger thermal mass. Al-
though the SA306 is rated for operation from -25 to +85C,
the other components on the DB64R are limited to 0 to 70C
ambient temperature.
CIRCUIT OPERATION
DB64R provides the 5V logic supply for the SA306. There
are no special considerations for sequencing the two sup-
plies.
Figure 2 (next Page) shows the user control features of the
DB64R. The PWM duty cycle is controlled with the potenti-
ometer (1 in fgure 2). The power LED (2) will illuminate when
the 12V supply is connected. The DB64R will power up with
the SA306 disabled. The enable button (3) will toggle the
The DB64R monitors the Temperature warning status pin of the SA306. If this pin goes high an LED (7) illuminates
and the enable circuit is forced to a disable status. The temperature LED is not latched and may stay illuminated
only briefy while the temperature of the SA306 is above 135C. The temperature decrease rapidly via the heatsink
PATENT PENDING
FEB 2009
APEX DB64RUREVA
DB64R
620 DB63RU
Hall Effect inputs to connector J3 (9) are required to com-
mutate the motor correctly. Filtering networks and 5V pull-
up are provided for glitch-free operation. The Hall sen-
sor connector, J 3 (9), also includes a tachometer output
which is based on the commutation signals from the Hall
inputs. Power for the Hall sensors is provided by U2 in
fgure 3, an integrated brushless motor controller IC. The
controller decodes the Hall sensor inputs and generates
six PWM control signals directly to the SA306. Push-but-
ton switches 1 and 2 trigger latches (U4) for direction and
enable control, respectively. Diodes D7 & D8 and resis-
tors R24, 25, 29 & 30 provide a means of bypassing the
DB64R control circuit. The 5V regulator, U3, provides 5V
to the SA306, the latches and the status LEDs.
Figure 3 Schematic
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DB64R
DB63RU 621
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ENHANCING & BYPASSING THE DB64R CONTROL CIRCUIT
Connector J4 is connected directly to the PWM input pins of the SA306. This connector may be used to monitor
the signals or to bypass the control IC on the DB64R. The enable function is not controlled via these pins, although
pulling all six input pins low provides the same effect. The Enable pushbutton and the connection via J5 are also
electrolytic capacitors provide a local, low inductance source to accommodate surge currents up to 17A. Six 100V
Schottky diodes conduct the commutation current via low forward voltage paths which reduces the power dissipa-
tion in the SA306. These diodes are rated for 5A continuous and are mounted close to the SA306 to reduce induc-
tance in the commutating current loop. For applications with continuous currents less than 5A, the Schottky diodes
may not be necessary if the higher forward voltage internal body diodes and the associated power dissipation are
manageable during commutation cycles.
Figure 4 shows the top and bottom layouts of the DB64R. Gerber fles for the circuit board are available upon re-
quest.
BILL OF MATERIALS
C13 CAP, 33pF, 50V Kemet C0603C330J 5GACTU
C2,C3,C4 CAP, 1.0nF,100V Kemet,C0805C102J 1GACTU
C7,C8,C14,C15,C16 CAP, 0.1uF, 16V GRM188F51C104ZA01D
C9,C10,C11,C12,C17 CAP, 2.2nF, 50V GRM188R71H222KA01D
D1,D2,D3,D4,D5,D6 Diode, 5A Schottky Diodes Inc. DS5100
J 3,J 4 Conn, 6 pin .100 ctrs Samtec TSM-106-01-T-SV
J 5 Conn, 4 pin .100 ctrs Samtec TSM-104-01-T-SV
LED1-5 LED, Red Lite-On LTST-C190CKT
R1,R2,R3 RES, 470, 5% RK73B1JTTDD471J
R4,R5,R6,R18,R19,R20,R21,R32 RES, 1.0K, 5% RK73B1JTTD102J
R7,R31 RES, 24.9K,1/10W, 1% RK73H1J TTD2492F
R9,R10,R14,R15,R16,R17,R22,R23 RES, 4.99K Vishay,CRCW06034K99FKEA
DB64R
622 DB63RU
TB1,TB2 Term. Blk., 3 pin, 5mm On Shore Tech, OSTTA034163
PCB, 1.75 x 3.75 Apex Precision Power, EVAL67R
Screw, #4-40 x N/A
Solder Tin/Silver 96/4
TOP SIDE
BOTTOM SIDE
3.888
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DB64R
DB63RU 623
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DB64R Quick Start Guide
Vs TB2-3 9-60V
Ground TB2-2
Motor Phase A TB1-1
Motor Phase B TB1-2
Motor Phase C TB1-3
Hall Sensor A J 3-1
Hall Sensor B J 3-2
Hall Sensor C J 3-3
Hall 5V J 3-5 Output from PCB
Hall ground J 3-6
DB64R Demonstration Board includes one populated EVAL67R PCB and one SA306-IHZ sample
IMPORTANT NOTICE
DB303R
624 DB303RU
DB303R SA303-IHZ
INTRODUCTION
The DB303R is designed to demonstrate the capabilities of the SA303 3 phase brushless DC (BLDC) motor driver
IC. This fully assembled demonstration allows the user to directly control the speed and direction of the motor. An
onboard controller decodes HALL Effect sensor inputs for commutation in either direction and provides four quad-
rant PWM signals to control the power outputs of the SA303. LEDs provide feedback for motor control status and
fault indications. Provisions on the DB303R allow the user to bypass the onboard control circuit and directly inter-
face with the SA303 brushless motor driver.
struction uses only a two-sided PCB and allows the SA303
to deliver peak power of over 500W.
ous and signifcant thermal challenge. The DB303R offers
a compact design which can deliver 17A peak current by
using a patent pending mounting technique. Mounting the
SA303 in an inverted fashion as shown in Figure 1 reduces
the profle height of the assembly and provides a direct in-
terface between the thermal tab of the PowerQuad package
(package outline drawing HQ) and the small HS33 heatsink.
The DB303R assembly can dissipate 7-9W in still air at 25C
ambient temperature, depending on the orientation of the
heatsink fns.
CIRCUIT OPERATION
DB303R provides the 5V logic supply for the SA303. There
are no special considerations for sequencing the two sup-
plies.
Figure 2 (next Page) shows the user control features of the
DB303R. The PWM duty cycle is controlled with the potenti-
ometer (1 in fgure 2). The power LED (2) will illuminate when
the 12V supply is connected. The DB303R will power up with
the SA303 disabled. The enable button (3) will toggle the
The DB303R monitors the Temperature warning status pin of
the SA303. If this pin goes high an LED (7) illuminates and
the enable circuit is forced to a disable status. The tempera-
ture LED is not latched and may stay illuminated only briefy
while the temperature of the SA303 is above 135C. The temperature decrease rapidly via the heatsink once the
SA303 is disabled.
PATENT PENDING
JUL 2009
APEX DB303RUREV1
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DB303R
DB303RU 625
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Hall Effect inputs to connector J3 (9) are required to com-
mutate the motor correctly. Filtering networks and 5V pull-
up are provided for glitch-free operation. The Hall sen-
sor connector, J3 (9), also includes a tachometer output
which is based on the commutation signals from the Hall
inputs. Power for the Hall sensors is provided by U2 in
fgure 3, an integrated brushless motor controller IC. The
controller decodes the Hall sensor inputs and generates
six PWM control signals directly to the SA303. Push-but-
ton switches 1 and 2 trigger latches (U4) for direction and
enable control, respectively. Diodes D7 & D8 and resis-
tors R24, 25, 29 & 30 provide a means of bypassing the
DB303R control circuit. The 5V regulator, U3, provides 5V
to the SA303, the latches and the status LEDs.
Figure 3 Schematic
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DB303R
626 DB303RU
ENHANCING & BYPASSING THE DB303R CONTROL CIRCUIT
are bypassed completely and the logic signals on pins 3 & 4 will directly control the direction and enable functions
of the DB303R. With these resistors jumped, the direction and enable LEDs will not represent the states of the
DB303R and the pushbuttons will have no effect on the operation. The Temperature disable feature of the DB303R
will also not function, although the LED will continue to provide over-temperature status.
pulling all six input pins low provides the same effect. The Enable pushbutton and the connection via J5 are also
electrolytic capacitors provide a local, low inductance source to accommodate surge currents. Six 100V Schottky
diodes conduct the commutation current via low forward voltage paths which reduces the power dissipation in the
SA303. These diodes are rated for 5A continuous and are mounted close to the SA303 to reduce inductance in the
commutating current loop. For applications with continuous currents less than 5A, the Schottky diodes may not be
necessary if the higher forward voltage internal body diodes and the associated power dissipation are manageable
during commutation cycles.
Figure 4 (next Page) shows the top and bottom layouts of the DB303R. Gerber fles for the circuit board are avail-
able upon request.
BILL OF MATERIALS
C13 CAP, 33pF, 50V Kemet C0603C330J5GACTU
C2,C3,C4 CAP, 1.0nF,100V Kemet,C0805C102J1GACTU
C7,C8,C14,C15,C16 CAP, 0.1uF, 16V GRM188F51C104ZA01D
C9,C10,C11,C12,C17 CAP, 2.2nF, 50V GRM188R71H222KA01D
D1,D2,D3,D4,D5,D6 Diode, 5A Schottky Diodes Inc. DS5100
J3,J4 Conn, 6 pin .100 ctrs Samtec TSM-106-01-T-SV
J5 Conn, 4 pin .100 ctrs Samtec TSM-104-01-T-SV
LED1-5 LED, Red Lite-On LTST-C190CKT
R1,R2,R3 RES, 470, 5% RK73B1JTTDD471J
R4,R5,R6,R18,R19,R20,R21,R32 RES, 1.0K, 5% RK73B1JTTD102J
R7,R31 RES, 24.9K,1/10W, 1% RK73H1JTTD2492F
R9,R10,R14,R15,R16,R17,R22,R23 RES, 4.99K Vishay,CRCW06034K99FKEA
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DB303R
DB303RU 627
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TB1,TB2 Term. Blk., 3 pin, 5mm On Shore Tech, OSTTA034163
PCB, 1.75 x 3.75 Apex Precision Power, DB303R
Screw, #4-40 x N/A
Solder Tin/Silver 96/4
TOP SIDE
BOTTOM SIDE
3.888
1.860
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DB303R
628 DB303RU
DB303R Quick Start Guide
Vs TB2-3 9-60V
Ground TB2-2
Motor Phase A TB1-1
Motor Phase B TB1-2
Motor Phase C TB1-3
Hall Sensor A J3-1
Hall Sensor B J3-2
Hall Sensor C J3-3
Hall 5V J3-5 Output from PCB
Hall ground J3-6
DB303R Demonstration Board includes one populated DB303R PCB and one SA303-IHZ sample
IMPORTANT NOTICE
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629
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ACCESSORIES
CLAMP02 ............................................................................... 630
CLAMP04 ............................................................................... 630
CLAMP05 ............................................................................... 631
HK26....................................................................................... 631
HS01....................................................................................... 632
HS02....................................................................................... 632
HS03....................................................................................... 633
HS04....................................................................................... 633
HS05....................................................................................... 634
HS06....................................................................................... 634
HS09....................................................................................... 635
HS11 ....................................................................................... 635
HS13....................................................................................... 636
HS14....................................................................................... 636
HS16....................................................................................... 637
HS18....................................................................................... 637
HS20....................................................................................... 638
HS21....................................................................................... 638
HS22....................................................................................... 639
HS23....................................................................................... 639
HS24....................................................................................... 640
HS26....................................................................................... 640
HS27....................................................................................... 641
HS28....................................................................................... 641
HS29....................................................................................... 642
HS31....................................................................................... 642
HS32....................................................................................... 643
HS33....................................................................................... 643
MS02 ...................................................................................... 644
MS03 ...................................................................................... 644
MS04 ...................................................................................... 645
MS05 ...................................................................................... 645
MS06 ...................................................................................... 646
MS11 ...................................................................................... 646
TW03 ...................................................................................... 647
TW05 ...................................................................................... 647
TW07 ...................................................................................... 648
TW09 ...................................................................................... 648
TW10 ...................................................................................... 649
TW12 ...................................................................................... 649
TW13 ...................................................................................... 650
TW14 ...................................................................................... 650
PRODUCT MARKING
CC, CD, CX ............................................................................ 651
CE, CR, CU, DC, DD, DE, EL ................................................ 652
CL ........................................................................................... 653
DF ........................................................................................... 653
DK ........................................................................................... 653
DN, DP, DQ, DR, EC, ED, EE, EP, ET, FL, FP, FU ................. 654
DW .......................................................................................... 654
EU, EW ................................................................................... 655
EX ........................................................................................... 655
FC ........................................................................................... 655
FD ........................................................................................... 656
FN ........................................................................................... 656
FQ ........................................................................................... 656
FX ........................................................................................... 657
GD, GF, KD ............................................................................. 657
GE, KE.................................................................................... 657
HC .......................................................................................... 657
HD .......................................................................................... 658
KC ........................................................................................... 658
PACKAGE OUTLINE AND DIMENSIONS
CC .......................................................................................... 659
CD .......................................................................................... 659
CE ........................................................................................... 660
CL ........................................................................................... 660
CR .......................................................................................... 661
CU .......................................................................................... 661
CX ........................................................................................... 662
DC .......................................................................................... 662
DE ........................................................................................... 663
DF ........................................................................................... 663
DK ........................................................................................... 664
DP ........................................................................................... 664
DQ .......................................................................................... 665
DR .......................................................................................... 665
DW .......................................................................................... 666
EC ........................................................................................... 666
EE ........................................................................................... 667
EL ........................................................................................... 667
EU ........................................................................................... 668
EW .......................................................................................... 668
EX ........................................................................................... 669
FC ........................................................................................... 669
FD ........................................................................................... 670
FL ........................................................................................... 670
FU ........................................................................................... 671
FX ........................................................................................... 671
GD .......................................................................................... 672
GE .......................................................................................... 672
GF ........................................................................................... 673
HC .......................................................................................... 673
HD .......................................................................................... 674
HQ .......................................................................................... 674
KC ........................................................................................... 675
KD ........................................................................................... 675
KE ........................................................................................... 676
Accessories, Product Marking
and Package Outlines
Accessories, Product Marking
and Package Outlines
Accessories
630 ACCU
CLAMP02
CLAMP04
Accessories For Apex Precision Power
Accessories P r o d u c t I n n o v a t i o n F r o m
JUN 2009
APEX ACCUREV1
DIP Clamp CLAMP02
TO-220 Clamp CLAMP04
Accessories
ACCU 631
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A
G
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F
E
D
C
B
A
CLAMP05
HK26
SIP Clamp CLAMP05
SIP Mounting Kit HK26
4-40 X 7/16 Screw (2)
Heatsink (not supplied)
Customer PCB
TW12 Thermal Washer (1)
Shoulder Washer (2)
No. 4 Lockwasher (2)
4-40 Hex Nut (2)
SIP Package Product
(not supplied)
.218
.115
Thru
.135
.031
.040
Shoulder Washer Dimensions
Keystone Part No. 3049
Nylon 6/6 per ASTM D4066
Accessories
632 ACCU
HS01
HS02
TO-3 Heatsink HS02
TO-3 Heatsink HS01
Accessories
ACCU 633
G
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B
A
G
H
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E
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B
A
HS03
HS04
TO-3 Heatsink HS03
TO-3 Heatsink HS04
Accessories
634 ACCU
HS05
HS06
Power DIP Heatsink HS06
TO-3 Heatsink HS05
Accessories
ACCU 635
G
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B
A
G
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E
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B
A
HS09
HS11
TO-3 Heatsink HS09
TO-3 + Power DIP Heatsink HS11
Accessories
636 ACCU
HS13
HS14
TO-3 Heatsink HS14
TO-3 Heatsink HS13
Accessories
ACCU 637
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B
A
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B
A
HS16
HS18
10-Pin Power DIP Heatsink HS16
Open Frame Heatsink HS18
Accessories
638 ACCU
HS20
HS21
DIP Heatsink HS21
Power SIP Heatsink HS20
Accessories
ACCU 639
G
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B
A
G
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E
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B
A
HS22
HS23
TO-220 Heatsink HS23
Accessories
640 ACCU
HS24
HS26
SMT Heatsink HS24
Accessories
ACCU 641
G
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E
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B
A
G
H
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F
E
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B
A
HS27
HS28
Accessories
642 ACCU
HS29
HS31
Accessories
ACCU 643
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B
A
G
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B
A
HS32
HS33
Flip SMT Heatsink HS33
Accessories
644 ACCU
MS02
MS03
TO-3 Socket MS03
Pin Receptacle MS02
Accessories
ACCU 645
G
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A
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MS04
MS05
Power DIP Socket MS05
Pin Receptacle MS04
Accessories
646 ACCU
MS06
MS11
Pin Receptacle MS11
Mating Socket MS06
Accessories
ACCU 647
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B
A
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B
A
TW03
TW05
Power DIP Thermal Washer TW05
TO-3 Thermal Washer TW03
Accessories
648 ACCU
TW07
TW09
DIP Thermal Washer TW09
Power SIP Thermal Washer TW07
Accessories
ACCU 649
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B
A
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A
TW10
TW12
Power SIP Thermal Washer TW12
Power DIP Thermal Washer TW10
Accessories
650 ACCU
TW13
TW14
TO-220 Thermal Washer TW14
SIP Thermal Washer TW13
MARKING
MARKING 651
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CC, CD, CX
Power Amplifiers/PWM/Motion Controllers
PRODUCT
MARKING
JUL 2009
APEX MARKINGREVE
Line 1
Line 2
Line 3
PA240CC
yyww
Line 1
Apex Logo
Line 2
Apex Part Number
Line 3
All Parts: Date Code
0329
2003 Work Week 29
Line 1
Line 2
Line 3
PA240CD
yyww
CC PACKAGE (7DDPAK)
CD PACKAGE (7TO220)
CX PACKAGE (7TO220) STAGGERED LEADS
MARKING
652 MARKING
CE, CR, CU, DC, DD, DE, EL
CE PACKAGE (TO-3),
DC, DD, CR, CU PACKAGE (MO-127 SERIES)
DE PACKAGE (10-PIN DIP SERIES)
EL PACKAGE (12-Pin DIP SERIES)
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
PA12M/883
5962-XXXXXXXXXX
8A603 Q 0337
USA BeO
60024
Line 1
SMD* Parts: Apex Part Number
Standard Parts: Apex Part Number
Custom Parts: Blank
Line 2
All Parts: APEX Logo
Line 3
SMD Parts: DSCC SMD Part Number
Standard Parts: Blank
Custom Parts: Apex Part Number
Line 4
All Parts: Lot Code
8A603
Line 5
All Parts: USA
ESD & Pin 1
Identifier
Line 6
All Parts: 60024 = APEX CAGE Code
* SMD = Standardized Military Drawing
Compliance Indicator
Q
Q = DSCC QML Compliant
C = MIL-H-38534 Compliant
None = Not Compliant
Date Code
0337
2003 Work Week 37
USA BeO
ESD & Pin 1 BeO
Identifier Identifier
MARKING
MARKING 653
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B
A
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B
A
CL
DK
DF
DF PACKAGE
(24 Pin PSOP)
Line 1
Line 2
PA243
yyww
Pin 1 ESD Identifier
Identifier
Line 1
Apex Part Number
Line 2
0309
2003 Work Week 9
DK PACKAGE
(20 Pin PSOP)
Line 1
Line 2
PA60
yyww
Identifier
Line 1
Apex Part Number
Line 2
0309
2003 Work Week 9
CL PACKAGE
APEX Part Number
Lot Code
9A268
Date Code
0329
2003 Work Week 29
Pin 1 Identifier
APEX Cage Code
Pin 30 Identifier
M
P
3
8
C
L

9
A
2
6
8
0
3
2
9
30
1
MARKING
654 MARKING
DW
D
N
,

D
P
,

D
Q
,

D
R
,

E
C
,

E
D
,

E
E
,

E
P
,

E
T
,

F
L
,

F
P
,

F
U
DW PACKAGE (Hermetic SIP)
Line 1
Line 2
Line 3
Line 4
PA241DW
5962-XXXXX
9A2680329
60024

ESD & Pin 1
Identifier
Line 1
SMD* Parts: Apex Part Number
Custom Parts: Blank
Line 2
SMD Parts: DSCC SMD Part Number
Standard Parts: Blank
Custom Parts: Apex Part Number
Line 3
All Parts:
Lot Code
9A268
Line 4
All Parts: 60024 =APEX CAGE Code
* SMD =Standardized Military Drawing
Date Code
0329
2003 Work
Week
29
Compliance Indicator
Q
Q =DSCC QML Compliant
C =MIL-H-38534 Compliant
None =Not Compliant
DN, DP, DQ, DR, EC, ED, EE,
EP, ET, FL, FP, FU PACKAGE
(Hybrid SIP Series)
Line 1
Line 2
Line 3
Line 4
SA60
9A2680329
USA BeO
60024

ESD & Pin 1
Identifier
Line 1
Custom Parts: Blank
Line 2
All Parts: Lot Code
9A268
Line 3
Made in U.S.A., BeO Identifier
Line 4
Date Code
0329
2003 Work Week 29
MARKING
MARKING 655
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A
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B
A
FC
EX
EU, EW
FC PACKAGE
APEX Part Number
Lot Code
9A268
Date Code
0329
2003 Work Week 29
Pin 1 Identifier
APEX Cage Code
Pin 42 Identifier
M
P
2
4
0
F
C

9
A
2
6
8
0
3
2
9
42
1
EU, EW PACKAGE
(Monolithic SIP)
Line 1
Line 2
PA60
TO11BP023

ESD & Pin 1
Identifier
Line 1
Apex Part Number
Line 2
Lot Code
EX PACKAGE
(23 PIN MOLDED SIP)
Line 1
Line 2
SA300EX
KAAA0642
Pin 1 & ESD
Identifier
Line 1
Apex Part Number
Line 2
Lot Code Date Code
KAAA 0642
2006 Work Week 42
MARKING
656 MARKING
FQ
FN
FD
Line 1
Line 2
SA300FQ
yyww
Pin 1 ESD
Identifier Identifier
Line 1
Apex Part Number
Line 2
0309
2003 Work Week 9
1 character space
reserved for extra
product designator
FQ PACKAGE
(16 pin SOIC with HEATSLUG)
FD PACKAGE
Lot Code
9A268
Date Code
0329
2003 Work Week 29
Pin 1 Identifier
APEX Cage Code Pin 34 Identifier
M
P
1
0
8
F
D
34
1
9
A
2
6
8
0
3
2
9
APEX Part Number
Line 1
Line 2
SA72
yyww
Identifier
Line 1
Apex Part Number
Line 2
0309
2003 Work Week 9
FN PACKAGE
(30 pin PSOP)
MARKING
MARKING 657
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B
A
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B
A
HC
GE, KE
GD, GF, KD
FX
USA
VRE310A
AX53930921
Line 1
Line 2
Line 3
Pin 1 Identifier
Line 1
Made in U.S.A.
Line 2
Custom Parts: Blank
Line 3
All Parts: Lot Code
AX5393
Date Code
0921
2009 Work Week 21
FX PACKAGE (8-pin SOIC)
GD, GF PACKAGE (8-pin DIP SMT)
KD PACKAGE (8-pin DIP)
USA
VRE310A
AX53930921
Line 1
Line 2
Line 3
Pin 1 Identifier
Line 1
Made in U.S.A.
Line 2
Custom Parts: Blank
Line 3
All Parts: Lot Code
AX5393
Date Code
0921
2009 Work Week 21
VRE310A
USA AX53930921
Line 1
Line 2
Pin 1 Identifier
Line 1
Custom Parts: Blank
Line 2
Made in U.S.A. Lot Code
AX5393
Date Code
0921
2009 Work Week 21
GE PACKAGE (14-pin DIP SMT)
KE PACKAGE (14-pin DIP)
SWR200C
AX53930921
USA 60024
Line 1
Line 2
Line 3
Line 4
ESD & Pin 1
Identifier
Line 1
Custom Parts: Blank
Line 2
All Parts: Apex Logo
Line 3
All Parts: Lot Code
AX5393
Line 4
Made in U.S.A., 60024 =APEX CAGE Code
Date Code
0921
2009 Work Week 21
HC PACKAGE (14-pin HERMETIC DIP)

MARKING
658 MARKING
HD
KC
KC PACKAGE
Lot Code
9A268
Date Code
0329
2003 Work Week 29
Pin 1 Identifier
APEX Cage Code
Pin 58 Identifier
M
S
A
2
4
0
K
C
58
1
9
A
2
6
8
0
3
2
9
APEX Part Number
HD PACKAGE (20-pin CERAMIC LCC)
VRE210M
AX53930921
60024
USA
Line 1
Line 2
Line 3
Line 4
Line 5
Pin 1 Identifier
Line 1
All Parts: Apex Logo
Line 2
Custom Parts: Blank
Line 3
All Parts: Lot Code
AX5393
Line 4
Line 5
Made in U.S.A.
Date Code
0921
2009 Work Week 21
Packages
PKGU 659
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B
A
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B
A
CC
CD
Package Outlines For Apex Precision Power
Packages P r o d u c t I n n o v a t i o n F r o m
MAY 2009
APEX PKGUREVY
7-Pin TO-220 CD
7-Pin TO-220 SMT CC
Packages
660 PKGU
CE
CL
30-Pin Open Frame CL
8-Pin TO-3 CE
Packages
PKGU 661
G
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C
B
A
G
H
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D
C
B
A
CR
CU
MO-127 60 mil Pin CR
MO-127 60 mil Pin Copper CU
Packages
662 PKGU
CX
DC
7-Pin TO-220 Staggered Leads CX
MO-127 High Voltage DC
Packages
PKGU 663
G
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C
B
A
G
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C
B
A
DE
DF
10-Pin Power DIP 60 mil Pin DE
MO-166 24-Pin PSOP DF
Packages
664 PKGU
DK
DP
MO-166 20-Pin PSOP DK
12-Pin Power SIP DP
Packages
PKGU 665
G
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C
B
A
G
H
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F
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C
B
A
DQ
DR
9-Pin Power SIP DQ
7-Pin SIP DR
Packages
666 PKGU
DW
EC
10-Pin Ceramic SIP DW
8-Pin PSIP 90 Leads EC
Packages
PKGU 667
G
H
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B
A
G
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B
A
EE
EL
12-Pin PSIP 90 Leads EE
18-Pin DIP 25 mil Pins EL
Packages
668 PKGU
EU
EW
12-Pin Plastic SIP EU
12-Pin Plastic SIP 90 Leads EW
Packages
PKGU 669
G
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B
A
G
H
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F
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B
A
EX
FC
23-Pin Plastic SIP Staggered Leads EX
42-Pin Open Frame FC
Packages
670 PKGU
FD
FL
34-Pin Open Frame FD
10-Pin Power SIP FL
Packages
PKGU 671
G
H
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C
B
A
G
H
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F
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B
A
FU
FX
10-Pin Power SIP 90 Leads FU
MS-012 8-Lead SOIC FX
Packages
672 PKGU
GD
GE
8-Pin DIP SMT GD
14-Pin DIP SMT GE
Packages
PKGU 673
G
H
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F
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C
B
A
G
H
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F
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C
B
A
GF
HC
8-Pin DIP SMT GF
14-Pin Hermetic Ceramic DIP HC
Packages
674 PKGU
HD
HQ
20-Lead Ceramic LCC HD
MO-188 64-Pin QFP HQ
Packages
PKGU 675
G
H
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C
B
A
G
H
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B
A
KC
KD
58-Pin Open Frame DIP KC
8-Pin DIP KD
Packages
676 PKGU
KE
14-Pin DIP KE
App Notes 677
Application Notes
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Application Notes Cross Reference ................................................................................................................... 678
AN01 General Operating Considerations ..................................................................................................... 679
AN02 Optoelectronic Position Control .......................................................................................................... 692
AN03 Bridge Circuit Drives ........................................................................................................................... 694
AN05 Precision Magnetic Defection ............................................................................................................ 697
AN06 Applying the Super Power PA03 ......................................................................................................... 701
AN07 Progammable Power Supplies ............................................................................................................ 707
AN08 Optimizing Output Power .................................................................................................................... 709
AN09 Current Limiting .................................................................................................................................. 713
AN10 Power Amp Output Impedance ........................................................................................................... 716
AN11 Thermal Techniques ........................................................................................................................... 717
AN13 Voltage to Current Conversion ............................................................................................................ 721
AN14 Power Booster Applications ................................................................................................................ 724
AN16 SOA Advantages of MOSFETs .......................................................................................................... 727
AN17 Wideband, Low Distortion Techniques ............................................................................................... 730
AN19 Stability for Power Operational Amplifers ........................................................................................... 733
AN20 Bridge Mode Operation of Power Operational Amplifers ................................................................... 753
AN21 Single Supply Operation of Power Operational Amplifers .................................................................. 757
AN22 SOA and Load Lines .......................................................................................................................... 763
AN24 Brush Type DC Motor Drive with Power Op-Amps ............................................................................. 768
AN25 Driving Capacitive Loads .................................................................................................................... 770
AN26 Parallel Connection ............................................................................................................................ 789
AN28 Proper Analog Wiring for Power Operational Amplifers ...................................................................... 792
AN30 PWM Basics ....................................................................................................................................... 794
AN31 Operational Amplifer Basics .............................................................................................................. 802
AN32 PWM Low Pass Filtering .................................................................................................................... 804
AN33 Spice Model and PWM Amplifer Applications .................................................................................... 814
AN37 Power Dissipation the Easy Way ........................................................................................................ 819
AN38 Loop Stability with Reactive Loads ..................................................................................................... 827
AN39 Filters and Power Dissipation for PWMs ............................................................................................. 837
AN41 Stablility and Biasing for PWM Amplifers ........................................................................................... 847
AN43 Heatsinks, Mating Sockets, Washers, Vendors ................................................................................... 863
AN44 Driving Piezoelectric Actuators ........................................................................................................... 868
AN45 Driving 3-Phase Brushless Motors ..................................................................................................... 880
AN46 3-Phase Switching Amplifer - SA306-IHZ .......................................................................................... 890
AN47 Techniques for Stabilizing Power Operational Amplifers .................................................................... 903
AN48 Increasing Output Swing in Power Operational Amplifers .................................................................. 914
AN49 Jumper Confgurable 100 Watt+ DC-to-DC Converter Fulflls Buck-Boost & Motor Drive Roles ......... 923
AN50 Optimizing Power Delivery in PWM Motor Driver ICs ......................................................................... 930
AN51 Thermal Modeling of Power Devices in a Surface Mount Confguration ............................................ 946
Technical Seminar ............................................................................................................................................. 952
Power Design Software Tools, Spice Models ..................................................................................................... 953
Power Design Technical Library ......................................................................................................................... 954
Application Notes Application Notes
678 App Notes
Application Notes Application Notes Cross Reference
Application Notes Cross Reference
The following Application Notes Cross Reference provides recommendations for specifc applications.
General Application Topic Recommended Application Note(s)
Basics of Power Amplifers App Note 1 - General Operating Considerations
Motor/Valve/Actuator App Notes 11, 22, 24, 30, 45, 46, 49
Programmable Power Supply App Notes 6, 7, 22
Electromagnetic Defection App Notes 5, 22
Electrostatic Defection App Note 22
Piezo, Electrofuorescent Display, Capacitive Load App Note 22, 44
Audio App Notes 3, 8, 11, 17, 22
Wideband App Note 17, Consult Factory
Power Delivery and Power Dissipation App Notes 8, 11, 30, 48
Power Booster or Composite Amplifer Applications App Notes 14, 19, 48
PA12 and PA10 Applications App Note 9
Safe Operating Area App Notes 16, 22
Bridge Circuit Applications App Notes 3, 20, 30
Stability App Notes 19, 25, 47
Basics of PWM App Note 30
PWM Low Pass Filtering App Note 32
Spice Model and PWM Amplifer Applications App Note 33
AN01
AN01U 679
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AN01 General Operating
Considerations
SAVE HOURS OF VALUABLE TIME
This applications information is intended to save you hours
(maybe days) of hard work and avoid many frustrating experi-
ences with power circuits. We highly recommend that you take
the small amount of time required to read this section so that you
can avoid the common pitfalls in designing and testing power
operational amplifer circuits. As a minimum, you should read all
oblique print and the frst paragraph in each numbered subsec-
tion. The majority of these problem areas have been identifed
from Apex Precision Power Design Support Request discussions
of actual circuits. They range from higher than expected errors
to total destruction of the amplifer.
1.0 ENVIRONMENTAL AND HANDLING PRECAUTIONS
Most of this document concerns design and application
practices that will ensure the long and productive life of an
Apex Precision Power amplifer. However, not all design faws
can be seen on a schematic diagram. This is a list of the most
serious handling and environmental hazards to an Apex Preci-
sion Power product.
1) ESD - All Apex Precision Power amplifers should be handled
using proper ESD Precautions. Many of our amplifers
include MOSFET devices which are particularly susceptible
to damage from ESD.
2) Condensation - If the operating environment is capable of
producing condensation on the amplifer use conformal coat-
ing to prevent a short between leads. The pin construction
on the PowerSIP package is such that condensation can
be trapped between the leads affecting performance and
reducing the life of the device.
3) Compressible Thermal Washers - On package types with
more than one point of attachment to a heatsink, compress-
ible thermal pads can cause internal mechanical damage to
the amplifer. There is more discussion in section 8.0.
4) Over-torque on the case - Follow the recommended torque
guidelines when mounting screws are used to attach the
package to the heatsink. There is more discussion in sec-
tion 8.0.
5) Heatsink pin clearance - Be sure to protect pins from the
heatsink. Use plastic or Tefon tubing on the pins to insulate
them from the heatsink with packages requiring the pins
to pass through the heatsink. There is more discussion in
section 8.0.
2.0 BEFORE YOU APPLY POWER
In the design/prototype phase of an application, many dangers
exist which will be eliminated by the time the circuit is ready for
production. Pins may be wired in reverse order, connections
may be missing, or test probes may cause momentary shorts.
Any of these can destroy power amplifers or other components
in short order.
Five procedures can be employed to substantially reduce
these dangers:
1) Set power supplies to the minimum operating levels allowed
by the data sheet.
2) Set amplifer current limit to very low levels (i.e. use a current
limit resistor of approximately 2.2 ohms for high current models
and 47 ohms for high voltage models). Consult Section
5, Current Limit, as well as the individual data sheet to
determine the proper values for the current limit resistor(s).
Do not depend on the variable current limit feature of your
lab power supply for protecting the amplifer.
It is much safer to install current limit resistors. Setting
the current limit to a low value on a commercial lab supply
will not protect the amplifer against the surge current avail-
able from the output flter capacitors. Even when average
power dissipation is low, SOA violations can occur due to
secondary breakdown of bipolar output stages. This mode
of output stage destruction results from simultaneous
application of high current and voltage to the conducting
transistor. See Section 6 on SOA and the individual data
sheets to better understand SOA limits.
3) Check for oscillations. With low voltage applied and
reduced current limits in place, set the input signal to zero
and connect a wide bandwidth (100 MHz or greater) oscil-
loscope to the output of the op amp. With the time base set
to the microsecond region, check for oscillations present
at any amplitude settings. Next, inject a signal into the
circuit and monitor the output for oscillations. Excessive
ringing on small signal square wave response indicates
marginal stability.
If an oscillation is found, measure the frequency and
amplitude of oscillation. Also note whether the oscillation
only shows up on the positive or negative half of the output.
Refer to Section 10, Stability, for diagnosing and fxing
the cause of instability.
With low voltage applied and reduced current limits
in place, the basic function of the circuit can be verifed.
Once the circuit is operating as desired, raise the current
limit and check worst case operating conditions, i.e. motor
reversal, square wave drive of reactive loads, or driving
the output to V
S
/2 for resistive loads. Only then should you
gradually raise the supply voltages to the maximum while
checking worst case operation. This procedure not only
saves many failures but it also helps to pinpoint problems
to specifc voltages and power levels.
4) Use the largest possible heatsink for your prototype work.
This precaution provides the best environment to make
thermal measurements on the case of the amplifer during
worst case loading conditions without premature failures
from thermal overload. Once you verify your calculations,
you may decide to use a smaller heatsink for your fnal
circuit. Consult Section 7, Internal Power Dissipation
And Heatsinking, for information on calculating heatsink
requirements for your application.
5) Avoid switching while the circuit is under power. This
includes plugging/unplugging banana jacks, switching
relays in high current lines, switching within a feedback
loop, etc. See Sections 9.1 and 9.3 for a further discussion
of the dangers of switching.
6) When using an externally compensated amplifer, be aware
that the compensation capacitor will be stressed to nearly
the total supply voltage. A check of the equivalent circuit
diagram will show one compensation terminal is within a
few volts of one of the supply rails (often connected to the
General Operating Considerations
APEX AN01 P r o d u c t I n n o v a t i o n F r o m
MAY 2009
APEX - AN01UREVG
AN01
680 AN01U
gate of a FET) and the other is very close to the output
voltage. At 300V and below, normal voltage margins are
adequate. Above this it is advisable to rate the capacitor
at twice the supply voltage. In this area, partial discharge
and corona effect can take place. A good way to visualize
the problem is to think of little packets of energy jumping
across the capacitor. The FET gate can be destroyed long
before incremental damage to the capacitor is ever seen.
3.0 ABSOLUTE MAXIMUM SPECIFICATIONS
Amplifers should always operate below their Absolute
Maximum Ratings to prevent permanent damage. If operation
results in one of these maximums being reached, no perma-
nent damage will result. Simultaneous application of two or
more of these maximum stress levels may result in permanent
damage to the amplifer. Note that proper operation is only
guaranteed over the ranges listed in the Specifcations table.
Example: Most amplifers have an Absolute Maximum
case temperature rating of +125C. If the Specifcations table
gives an operating temperature range of up to +85C, then
the parameter limits in the Specifcations table are not valid
between +85C and +125C. In addition, the amplifer may not
even be operational in this range, (for example, the amplifer
may latch to one of its supply rails when above +85C). How-
ever, the device will not sustain permanent damage unless
the latched condition also violates the safe operating area.
The absolute maximum power dissipation rating used by
Apex Precision Power is the generally accepted industry
method which assumes the case temperature of the ampli-
fer is held at 25C and the junctions are operating at the
absolute maximum rating. This standardization provides a
yardstick when comparing ratings of various manufacturers.
However, it is not a reasonable operating point because it
requires an ideal (infnite) heatsink. Furthermore, even with
the best heatsink, sustained operation at the maximum rated
junction temperature will result in reduced product life. Refer
to Section 7, Linear Power Dissipation And Heatsinking,
for information regarding operating junction temperatures and
relative product life. Apex Precision Power generally recom-
mends operating at a case temperature that keeps maximum
junction temperatures at 150C or below.
Absolute Maximum Common Mode Voltage is another
rating that illustrates the difference between the rated abso-
lute maximum and the specifed operating range. On many
amplifers, the rated absolute maximum voltage applied to both
inputs simultaneously is equal to the power supply voltage.
However, the linear operating range is 5V to 30V less than
each power supply rail. This means that inputs exceeding the
linear range specifcation will not damage the part but the
amplifer may not achieve the specifed rejection ratio, may
start to distort the signal, or could even latch the output to
one of the supply rails.
For more information on specifcations and limits, see Sec-
tion 9, Amplifer Protection And Performance Limitations,
Section 6, SOA, Section 4, Power Supplies, and the
Parameter Defnitions section.
4.0 POWER SUPPLIES
4.1 VOLTAGE SPECIFICATION
The specifed voltage (Vs) applies for a dual supply having
equal voltages ( 30V). An asymmetrical (+50V/10V) or a
single supply (60V) may be used as long as the total voltage
between +Vs and Vs does not exceed the maximum rating.
Never allow reverse voltage on a supply pin. On a dual supply
circuit, do not operate with only one supply connected.
4.2 POWER SUPPLY BYPASSING
Inadequate power supply bypassing can lead to power
amplifer circuit oscillations. Each supply pin should be bypassed
to common with a low frequency bypass capacitance of 10F
per Ampere of peak output current. Tantalum capacitors should
be used, although computer grade aluminum electrolytics can
be substituted for operating temperatures above 0C.
In addition, a high frequency bypass, .1F to 1F ceramic
capacitor, should be added in parallel with the low frequency
bypass capacitors from each supply rail to common. Refer to
Figure 1. The ceramic capacitors must be mounted as close as
possible (1/4" is good) to the supply pins. The larger capacitors
should be within a few inches.
4.3 OVERVOLTAGE PROTECTION
The amplifer should not be stressed beyond its Absolute Maxi-
mum supply voltage rating. The amplifer should be protected
against any condition that may lead to this voltage stress level.
Two common sources of overvoltage are the high energy pulses
from an inductive load coupled back through fyback diodes
into a high impedance supply and AC main transients passing
through a power supply to appear at the op amp supply pins.
Unipolar devices also protect against reverse polarity.
Note that an open supply pin can cause supply reversal and
sometimes amplifer destruction. Transient suppressors with a
voltage rating greater than the maximum power supply voltage
expected but less than the breakdown voltage of the amplifer
will prevent the amplifer from damage.
Transients from the AC mains can be clamped through the
use of MOVs (Metal Oxide Varistors) such as those made by
General Electric, or bipolar TransZorbs. Connect either of these
devices across the inputs to the power supply to reduce transients
before they reach the power supply. Low pass fltering can be
done between the AC main and the power supply to cut down
on as much of the high frequency energy as possible. Note that
inductors used in power supply flters will pass all high frequency
energy and capacitors used in the flter are usually electrolytics
which have high ESR. Because of this high ESR, high frequency
energy will not be attenuated fully and therefore will avoid the
capacitor with little reduction. Refer to Figure 2 (next page).
5.0 CURRENT LIMIT
The primary function of current limit is to keep an amplifer
within its SOA. See Section 6, Safe Operating Area. Some
models of Apex Precision Power Power Op Amps have an internal
current limit, while most of our models have an adjustable limit
that is set with one or two external resistors.
+Vs
Vs
OP
AMP
C2
C1
C1
C2
<2"
C1 = .1 to .1F, Ceramic, High Frequency Bypass
C2 = 10F/Amp out (peak), Electrolytic/Tantalum,
Low Frequency Bypass
FIGURE 1. POWER SUPPLY BYPASSING
AN01
AN01U 681
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Any attempt to limit current with a circuit external to the ampli-
fer must be approached with extreme caution. The pitfalls are
generally time related and are often catastrophic. Most power
supply current limit circuits are effective only AFTER stored
energy in a large output flter capacitor has been depleted.
This energy plus energy in local supply bypass capacitors is
often more than enough to destroy the amplifer.
Slow response time is also a problem with even the fastest
fuses. A 15 second response time to a 200% over current is
common. In most applications the amplifer will give its life
protecting the fuse. Even if the fuse does blow, the ampli-
fer may still be damaged. The blowing fuse is a mechanical
interruption in a current carrying line which can cause voltage
spikes above the supply rating of the amplifer.
5.1 CURRENT LIMIT PRECISION
Standard current limit circuitry is not designed to provide
a precision current limit function. A rule of thumb is to allow
20% variation at room temperature. Furthermore, the current
limit varies over temperature. This temperature dependence is
generally shown in a typical performance graph in the product
data sheet. Specifc values of the nominal current at any given
temperature may be calculated by modifying the 0.65V term of
the current limit equation given in Section 5.3 with 2.2mV per
degree (Centigrade) of case temperature rise above 25C. For
example, at a case temperature of 125C, this term becomes
0.43V rather than 0.65V; (650mV(125C25C)(2.2mV)).
When working with high currents, the impedance of PCB
traces, lead lengths and solder joints must be included in the
current limit calculations.
5.2 EXTERNALLY ADJUSTABLE CURRENT LIMIT
Models with provisions to adjust current limit externally
must have the current limit resistors connected as shown in
the external connection diagram.
Current limit should never be set at a value greater than
the rated maximum output current of the power op amp. This
maximum is due to the current density limitations of conduc-
tors in the package and exceeding it can destroy the amplifer.
Also, using a very low resistance (such as a jumper wire) will
lead to increased bias current in the output stage. This raises
power and temperature, while lowering resistance to second
breakdown, thereby destroying reliability.
Operation without current limit resistors installed (current
limit pins left open) can also cause failures, especially with
inductive loads. This includes even a momentary open circuit
while switching current limits with mechanical contacts. For the
high current series power op amps, minimum programmed
limits should be 20mA, while 10mA is minimum for most of the
high voltage, low current series. Open circuits or limits below
these minimums can cause voltage breakdown of the current
limit transistors.
5.3 CALCULATING CURRENT LIMIT
Power op amps with provisions to adjust current limit exter-
nally require one or two current limit resistors (R
CL
) which must
be connected as shown in the applicable external connection
diagram below. Since output current fows through these resis-
tors, wattage ratings must be considered. For optimum reliability,
the resistor values should be set as high as possible. Some
amplifer data sheets provide model specifc equations, but in
general each resistor and its power dissipation is calculated
as follows:
I
LIM
is the value of current limit desired and should be chosen
to provide the amount of protection required for the specifc
application. For details on choosing safe levels of current limit
and the protection/performance trade offs involved, see Section
6.3, Fault Protection Using Current Limit.
For two resistor current limit schemes, asymmetrical current
limiting (R
CL+
R
CL)
is permissible.
Foldover current limit, discussed in detail in AN #9, Current
Limiting, provides a lower current limit for short circuit condi-
tions while increasing current limit for load drive. Apex Preci-
sion Power power amplifers, the PA10, PA12 PA04 and PA05,
have this feature. Foldover reduces the protection/performance
trade-off inherent in setting current limit. The Power Design Tool
will calculate and plot current limit on an SOA graph for most
linear amplifer models. It is available free at www.Cirrus.com.
6.0 SAFE OPERATING AREA (SOA)
6.1 READING THE SOA GRAPH
The horizontal axis on the SOA curve, V
S
V
O,
defnes the
voltage stress across the output device that is conducting.
It does not defne a supply voltage or total supply voltage or
the output voltage. V
S
V
O
is the magnitude of the differential
voltage from the supply to the output across the transistor that
is conducting current to the load. Put another way: if the ampli-
fer is sourcing current, use (+V
S
)V
O.
If the amplifer is sinking
current, use (V
S
)V
O.
Refer to Figures 3a & 3b.
The vertical axis represents the current that the amplifer is
sourcing or sinking through the Output pin.
The Safe Operating Area curves show the limitations on the
power handling capability of the amplifer. Refer to Figure 4 .
There are three basic limitations:
1) Current handling capability. This horizontal line near the top
of the SOA CURVE represents the limit on output current
imposed by current density constraints in the wire bonds,
die junction area and thick flm conductors.
2) Power dissipation capability. This is the power dissipation
capability of the amplifer output stage. Note that the prod-
uct of output current on the vertical axis and V
S
V
O
on the
horizontal axis is constant over this line. In other words, this
portion of the SOA curve is a constant power line. For T
C =

25C, this line represents the maximum power dissipation
capability of the amplifer at maximum junction temperature
using an infnite heatsink. As case temperature increases,
this constant power/thermal line moves toward the origin.
The new constant power line can be determined from the
Power Derating curves on the data sheet. The case tem-
perature is primarily a function of the heatsink used. For
more details, refer to Section 7, Linear Power Dissipation
And Heatsinking.
BIPOLAR
TRANSZORB
MOV
OP
AMP
+Vs
-Vs
POWER
SUPPLY
FILTER AC
V
S
< V
Z
< V
MAX (OP AMP)
0.65
I
LIM
(A)
R
CL
(ohms) =
PR
CL
(watts) = 0.65 I
LIM
AN01
682 AN01U
3) Second Breakdown. Second breakdown is a phenomenon
exhibited by bipolar transistors when they are simultane-
ously stressed with high collector-emitter voltage and high
collector current. Non-uniform current density in the emitter
results in localized heating and hot spots at the junction.
The temperature dependence of junction current results in
increased current density at the hot spots. This concentra-
tion of current tends to further increase the temperature.
The process is cumulative, leading to thermal runaway and
transistor failure. Note that MOSFET power transistors do
not have this second breakdown limitation.
The transient second breakdown lines (t = 0.5ms, t = 1ms, and
t = 5ms) are based on a 10% duty cycle. For instance, in Figure
4, the amplifer may deliver 1.5A at a V
S
V
O
of 60V for 5ms but
then must wait for 50ms before repeating this stress level. It is
highly recommended to avoid entering the region beyond the
DC second breakdown limits. Operation outside steady state
limits in transient SOA regions is difficult to analyze adequately
enough to insure best possible reliability.
6.2 HIGH SOA STRESS CONDITIONS
For resistive loads tied to ground, calculating power dissi-
pation in the amplifer is reasonably simple. Refer to Section
7.1, DC Power Dissipation, and Section 7.2, AC Power
Dissipation. However, with reactive loads, the voltage/cur-
rent phase difference results in higher power being dissipated
in the amplifer.
An example of an excessive transient stress condition cre-
ated by a capacitive load is shown in Figure 5a. In this case
the capacitive load has been charged to V
S.
Now the ampli-
fer is given a go positive signal. Immediately the amplifer
will deliver its maximum allowed output current (IL
IM)
into the
capacitor, which can be modeled at time t=0+ as a voltage
source. This leads to a voltage stress across the conducting
device equal to the rail-to-rail supply voltage. Simultaneously,
the amplifer will be conducting its maximum (current-limited)
value of current.
Figure 5b shows a similar transient stress condition for an
inductive load. For this situation we imagine the output is near
the positive supply and current through the inductor has built
up to some value I
LOAD.
Now the amplifer is given a go nega-
tive signal which causes the output voltage to swing down to
the negative supply. However, the inductor at time t=0+ can
be modeled as a current source that requires the amplifer to
continue to source I
LOAD.
This leads to the same situation as
before, that is, total supply voltage across a device conducting
maximum rated current.
Note also that reactive loads cause higher thermal stress
levels than resistive loads even under steady state sinusoidal
conditions. For purely reactive loads, all of the power is dis-
sipated in the amplifer, none in the load.
6.3 FAULT PROTECTION USING CURRENT LIMIT
With a given supply voltage, current limit can be used to
keep the amplifer within its Safe Operating Area. This allows
amplifer protection during fault conditions such as shorts to
ground or shorts to either supply. The cost of protection is
lowered output current capability.
For short-to-ground fault protection, set current limit to the
value given by the intersection of the supply voltage and the
DC SOA curve for the appropriate case temperature. Simply
fnd the supply voltage on the horizontal axis. When the output
is shorted to ground, V
O
= 0; therefore, V
S
V
O
= V
S,
follow up
to the SOA curve intersection and then across to the output
current. Referring to Figure 6, we see that in this example, a
2A current limit provides short circuit protection to ground at a
case temperature of 25C with 30V supplies. Note that better
heatsinking allows higher values of current limit.
For short-to-either supply protection, set current limit to the
value given by the intersection of the rail-to-rail supply volt-
age (V
SS)
and the DC SOA curve. This requires a signifcant
lowering of current limit. For this type of protection, add the
magnitudes of the two supplies used, fnd that value on the
V
S
V
O
axis, follow up to the SOA limit for the case temperature
anticipated, then follow across to fnd the correct value of cur-
+Vs
I
LIM
Vo = Vs
5a: CAPACITIVE
+Vs
I
LOAD
Vo = Vs
5b: INDUCTIVE
FIGURE 5. TRANSIENT STRESS WITH REACTIVE LOADS
5.0
3.0
2.0
1.5
1.0
.7
.5
.3
.2
10 15 20 25 30 3540 50 60 70 80 100
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V

O
R

V

(
A
)
S
S
SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE V V (V)
S O
T
H
E
R
M
A
L
T
c
=
2
5
C
T
c
=
8
5
C T
c
=
1
2
5
C
steady state
S
E
C
O
N
D

B
R
E
A
K
D
O
W
N
t

=

0
.
5
m
s
t

=

1
m
s
t

=

5
m
s
FIGURE 4. TYPICAL SOA CURVE
+IN
IN
+VS
(+15V)
VS
(15V)
I
OUT
Vo
(+Vs) Vo
(+15V) 10V = 5V
|5V| = 5V
(+10V)
R
L
+IN
IN
+VS
(+15V)
VS
(15V)
I
OUT
Vo (10V)
R
L
(Vs) (Vo)
(15V) (10V) = 5V
|5V| = 5V
FIGURE 3A. SOURCING CURRENT
FIGURE 3B. SINKING CURRENT
AN01
AN01U 683
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
facturers of power op amps have adopted the 60HZ rule: Below
60HZ, use peak power and DC thermal resistance; otherwise
use RMS power and AC thermal resistance.
7.1 DC POWER DISSIPATION
Power in the output transistor is the output current multiplied
by the voltage across that transistor, or supply-to-output dif-
ferential, Vs - Vo. For a purely resistive load, maximum power
dissipation occurs at Vo = 1/2Vs and has a value of:
Where:
Vs is the supply magnitude of the conducting transistor.
R
L
is the load resistance.
For AC signals below 60HZ driving reactive loads, plot the
load line to fnd stress levels. Use the highest power level from
the plot for heatsink selection. Application Note 22 discusses
SOA and Load Lines. As an example, consider the PA12A,
48V supplies, 40V signal at 50HZ driving a 69mH coil with
12.5 resistance, mounted on a 0.3C/W heatsink. Figure 7
is the load line for this circuit with peak internal dissipation of
67.5W at 1.28A. Load impedance is 25 at 60 resulting in
apparent power of 32VA and a power factor of 0.5. Quite a
limitation for an amplifer boasting an ABSOLUTE MAXIMUM
RATING of 125W! The software secret behind this plot will
be revealed later.
ELECTRICAL MEASUREMENT METHOD
Although we present this under the DC heading and it is
primarily used at low frequencies, instrumentation errors are
the only limitations on frequency. The ideal way to run this test
is to have an amplifer/heatsink combination you are certain is
large enough to handle all the power. While this may sound like
circular cells in a spreadsheet, the test still has its place. Many
loads do not change impedance with changing drive amplitude.
If this is true, it is possible to replace the power amp in Figure
8 (next page) with a signal generator or a low power amplifer.
Set the drive signal to a convenient fraction of the ultimate
level, and rescale the voltages and currents measured prior
to calculating power levels. If using a programmable signal
generator, the actual output amplitude is not likely to match the
programmed level because the load impedance is not likely to
match the generator output impedance.
rent limit. Referring to Figure 6, we see that in this example,
a 0.7A current limit allows short protection to either supply.
It is often the case that requirements for fault protection and
maximum output current may confict. Under these conditions
there are only four options. The frst is to simply go to an ampli-
fer with a higher power rating. The second is to trim some of
the requirements for fault protection. The third is to reduce the
requirement for maximum output current. The fourth option is a
special type of current limit called foldover or foldback. This
is available on some amplifers such as the PA10 and PA12.
For a detailed discussion of foldover current limit and SOA fault
protection refer to Application Note 9, Current Limiting. For
an explanation of how to choose current limit resistors to adjust
current limit, see Section 5.3, Calculating Current Limit.
7.0 LINEAR POWER DISSIPATION AND HEATSINKING
It is important to not confuse Internal Power Dissipation
with power delivered to the load. These two power levels are
equal only at unique signal levels. Low impedance faults or
highly reactive loads will likely result in internal power dissipa-
tion being the higher level. Well-designed circuits with less
reactance will yield higher efficiency.
There are two main steps in the heatsink selection process.
First, the maximum internal power dissipation must be cal-
culated. Secondly, the maximum desired junction and case
temperatures must be chosen and the thermal model used to
calculate the required thermal conductance of the heatsink. The
following four sub-paragraphs deal with fnding internal power
dissipation in the output transistors generated by delivering
current to the load only.
For purposes of power dissipation calculation, DC refers to
any signal with a frequency below 60HZ. At true DC, heat is
generated in only one output transistor and ability to conduct
this heat to the surface of the amplifer case is determined
by thermal conductance of materials and square area. As
frequency increases, our original transistor now has a time
variable heat load and the opposite side output transistor now
generates the heat on alternate half cycles. This means the
wattage fgure can move from peak value toward RMS and
more square area is used to conduct heat to the case, imply-
ing a lower thermal resistance. At 1HZ, internal thermal time
constants are so fast compared to the half-second duration
of the conduction cycle of each transistor, that no advantage
gained. At 1KHZ, conduction cycles are short compared to
internal time constants and thermal averaging allows taking
advantage of both RMS power levels and the lower thermal
resistance. While physics produces a smooth curve between
these frequencies, the math is quite cumbersome. Most manu-
R-L LOAD and the SOA
0.010
0.100
1.000
10.000
100.000
1
0
0
.
0
9
2
.
8
8
6
.
1
7
9
.
9
7
4
.
1
6
8
.
8
6
3
.
8
5
9
.
2
5
4
.
9
5
1
.
0
4
7
.
3
4
3
.
9
4
0
.
7
3
7
.
8
3
5
.
0
3
2
.
5
3
0
.
2
2
8
.
0
2
6
.
0
2
4
.
1
2
2
.
4
2
0
.
7
1
9
.
3
1
7
.
9
1
6
.
6
1
5
.
4
1
4
.
3
1
3
.
2
1
2
.
3
1
1
.
4
1
0
.
6
9
.
8
9
.
1
8
.
4
7
.
8
7
.
3
6
.
7
6
.
3
5
.
8
5
.
4
5
.
0
Suppl y to Output Differential Voltage, Vs-Vo (V)
C
u
r
r
e
n
t

L
i
m
i
t
,

A
FIGURE 7
V
S
2
4R
L
PD (max) = [Purely resistive load only]
10
3.3
2.2
1
0.7
0.1
10 30 60 100
O
u
t
p
u
t

C
u
r
r
e
n
t

(
A
m
p
s
)
Supply to Output, V
S
-V
O
(Volts)
I (desired)
Short to Gnd
Short to V
S
SOA Violation
SOA Limit
MAX
Vs = 30 Volts
1
2
3
3
2
1
FIGURE 6. CURRENT LIMIT FAULT PROTECTION
AN01
684 AN01U
1. Use a small value current sense resistor between the load
and ground to develop a voltage proportional to I
L
. Use this
signal to drive one channel of the XY display of an oscil-
loscope.
2. Use the output voltage of the amplifer, V
O
, to drive the other
channel of the XY display.
3. Calculate instantaneous power dissipation in the amplifer
for several points on the ellipse using:
PD
OUT
= (V
S
V
O
) I
LOAD
4. Plot the points on the SOA curve and check for violations.
7.2 AC POWER DISSIPATION
Again, AC for the purpose of determining power dissipation
means at least 60HZ. For the moment, we will also confne
the discussion to sinusoidal signals and symmetric supplies.
Starting with the simple: When driving a pure resistance, power
dissipation is maximum when the sine wave peak is 0.637*Vs.
Refer to Figure 9 to see how the heat load on the amplifer
decreases as signal amplitude varies in either direction. This
equation yields maximum power:
Where:
V
S
is the magnitude of each supply.
R
L
is load resistance.
SIMPLE APPROXIMATION FOR REACTIVE LOADS
As loads move from pure resistance toward pure reactance,
three changes should be noted:
1) The fraction of Vs corresponding to maximum power dis-
sipation goes from 0.637 toward one. See Figure 10.
2) Power factor goes from one toward zero. With a pure reac-
tance, no heat is generated in the load (no work is done).
3) The difference between load VA and true watts is dissipated
in the amplifer.
Even with these changes, one of the two following formulas
can be used to approximate internal power dissipation. The
key is knowing the phase difference between V & I in the load,
to fnd the power factor, COS, where is the angle between
the voltage and the current. With only one reactive element in
the load it is easy to determine what frequency will produce
the largest power dissipation. With the power factor and load
impedance measured or calculated, the formulas are:
Where:
V
S
is the magnitude of each supply.
Z
L
is load impedance magnitude.
MORE ACCURATE METHODS
This method can be used analytically or on the bench as
long as the test amplifer and heatsink are large enough to
accommodate any errors in the frst pass estimate of the circuit
operation. Just as in the previous method, phase angle of the
load must be known. Not only is it a term of the equations, but
it is needed to determine the proper signal amplitude. Find the
maximum power producing amplitude from Figure 10. If this is
lower than the maximum amplitude your circuit will drive, use
it. If not, use the circuit maximum.
1) Find the power delivered TO the amplifer from the supply:
Amplitude Resulting in Maximum Power
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
5 10 15 20 25 30 35 40 45 50
V to I Phase, Degrees
V
o
u
t

a
s

a

F
r
a
c
t
i
o
n

o
f

V
s
Peak
Values
RMS
Values
FIGURE 10. AMPLITUDE PRODUCING MAXIMUM POWER
MOVES WITH PHASE ANGLE
1
-1
0
-20 0 +20
Resistive
Load
Complex Reactive
Load
Y
I
(Amps)
INPUT
L
X V (Volts)
INPUT O
POWER
AMP
LOAD
V
IN
R
I
R
F
+V
S
-V
S
V
O
Z >>.1
I
L
0.1
CURRENT SENSE
I
L
= -------
V
0.1
Purely
Reactive
Load (max.
current at
zero voltage)
FIGURE 8. AC PD
OUT
: ELECTRICAL MEASUREMENT
2(Vs)
D
P
e
g
a
r
e
v
A
)
s
r
o
t
s
i
s
n
a
r
t
h
t
o
b
(
T
U
O
0
VIN
-Vs
R
L
VO PEAK (AC) (relative to VS)
2
+Vs
2
Vs
Vs
4
Vs
2
3Vs
4
Vs
FIGURE 9. AC POWER DISSIPATION VS. PEAK OUTPUT
VOLTAGE
2
R
L
2V
S
2

2
Z
L
COS
PD (max) = [Primarily resistive loads, < 40]
V
S
2
2 Z
L
PD (max) = COS
]
[Primarily reactive loads, > 40]
4
[
2V
S
2
2
R
L
PD (max) = [Purely resistive load only]
AN01
AN01U 685
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
2) Find the power delivered from the amplifer to the load:
P
OUT
= (1/2)V
PEAK
I
PEAK
COS
3) Calculate power left in the amplifer:
PD
INT
= P
IN
P
OUT
7.3 OTHER POWER DISSIPATION
For waveforms other than sinusoids, or for more complex
energy storing loads such as motors, a Spice analysis and an
electrical test method as described under DC Power Dissipa-
tion is recommended. Application Note 24, Brush Type DC
Motor Drive may also prove useful.
7.4 EASY POWER DISSIPATION
Power Design is an Excel spreadsheet available free from
www.Cirrus.com. It remembers all the rules and formulas pre-
sented here, has a data base of model capabilities and fnds
the critical phase angle for you. Answers for simple loads are
tabulated and load line plotted as fast as you can enter the
data. Frequency sweeps on up to 54 component complex loads
take a little longer. It also does calculations in the following
paragraphs on heatsink selection plus, has sheets for stabil-
ity, model selection, PWM flters and PWM power dissipation.
7.5 WHERE TO SET T
J
MAX
For that matter, what is T
J
max? In the ABSOLUTE MAXIMUM
RATINGS area of a data sheet, it is the temperature limit set
by the transistor manufacturer to insure leakage of that transis-
tor does not become destructive. Especially on older bipolar
models, 200C appears frequently. This is not a good place
to be on a continuous basis. From here on, T
J
max will mean
the design maximum for the circuit.
Reliability is a strong function of temperature. Figure 11,
based on data from MIL-HDBK-217F, shows that a bipolar
transistor operated a junction temperature of 175C will have
a mean failure rate more than ten times higher than with a
junction temperature of 25C. A MOSFET can be expected to
fail almost nine times as often with the same temperature rise.
Apex Precision Power has seen applications required by
military contract to meet a T
J
max of 100C. More often the
designer must set T
J
max based on application details. Would
1.0
1.5
2.0
3.0
4.0
5.0
6.0
8.0
10
15
175 150 125 100 75 50 25
F
A
I
L
U
R
E

R
A
T
E

M
U
L
T
I
P
L
I
E
R
J
(C)
Bipolar
MOSFET
This data has been extracted from the base failure rate tables
of MIL-HDBK-217F, revision of 2 December 1991.
FIGURE 11. MTTF VS. TEMPERATURE
failure eliminate one bell or whistle on a non-critical piece of
equipment, or completely stop a $1M per hour production line?
How about consequential damage? Is the amplifer used for
30 seconds each day, or continuously? Can the amplifer be
easily replaced, or does this require a space vehicle? Simply
trade off these concerns against time, size, weight and cost
budgets to arrive at the perfect T
J
max.
There are three approaches to lowering junction tempera-
tures. The frst is to lower internal power dissipation. Application
Note 8, Optimizing Output Power, Notes 3 and 20 on bridge
circuits and AN26 on parallel operation may prove helpful here.
The second method is to lower the ambient temperature. This
may involve placement choices inside an equipment enclosure
or the use of a chilled liquid cooling system rather than air-
cooling. Last on the list, we must minimize thermal resistance
from the transistor junctions to the ambient environment.
7.6 THERMO-ELECTRIC MODELS
Thermo-electric models translate power terms into their
electrical equivalent. In these models, power is modeled as
current, temperature as voltage and thermal resistance as
electrical resistance. Since 1980, Apex Precision Power has
advocated using a simplifed calculation of case and junction
temperatures of power op amps. This shortcut assumed qui-
escent power was added to power dissipated due to output
current and the total is used to calculate both temperatures.
This yields the correct case temperature but predicts output
transistor junction temperatures higher than the real world. This
error is in the safe direction and generally insignifcant until
the amplifer combines high voltage and high speed causing
quiescent power to be a signifcant percentage of the power
rating of the output transistors alone.
The more accurate model shows that adding all the qui-
escent power to the calculation for the output transistors is
an error because quiescent power is spread among all the
components of the amplifer. From the data sheet point of
view, the POWER DERATING graphs show power handling
capability of the output transistors only, but the simple method
produces a temperature rise in the output transistors due to
current which does not fow in them. In the PA94, maximum
quiescent current times maximum supply voltage develops
21.6W, over 70% of the power rating of the output stage. How-
ever, less than 1% of this power is in the output stage and the
simple method imposes a false but severe limitation on power
handling capability of the output transistors. It is very easy to
design a reliable PA94 circuit where total power dissipation is
greater than that allowed by the POWER DERATING graph.
THE SIMPLE MODEL
In Figure 12, P
D
is the total power dissipation, that is P
D
(internal dissipation of the output transistors due only to output
current) plus quiescent power of the amplifer. Quiescent power
(PD
Q
) is quiescent current (I
Q
) * total supply voltage.
PD
Q
= I
Q
(+V
S
+ |-V
S
|)
A MORE ACCURATE MODEL
In Figure 13 (next page), quiescent power has been split
according to the actual transistors generating the heat. PD
Qout

is only the quiescent current fowing in the output transistors.
When appropriate, this specifcation will appear in the amplifer
data sheet. Multiply this output stage quiescent current times
the total supply to fnd worst case PD
Qout.
PD
Qout
= I
Qout
(+V
S
+ |-V
S
|)
2V
S
I
PEAK
P
IN
=
AN01
686 AN01U
PD
Qother
is the current fowing in all the other components
and could be found by subtracting PD
Qout
from PD
Q.
Note that the data sheet junction-to-case thermal resistance
speculations refer to only the output transistors. Thermal
resistances and power dissipations of other components vary
wildly. Design rules applied by Apex Precision Power for all
these components insure they will be reliable when operating
within maximum supply voltage, maximum input voltage and
maximum Meets full range specifcations case temperature.
No matter which model you use, there are three thermal
resistances contributing directly to hot junctions. The thermal
resistance should be attacked on all three fronts:
1) Buy an amplifer with the lowest possible R
JC
.
2) Use good mounting practices-see section 8 below.
3) Use the largest practical heatsink.
The amplifer is often a large portion of the thermal resistance
budget. Better amplifers usually cost more and sometimes
are larger. Increased amplifer size is usually of little concern
when compared to the size and weight of an adequate heatsink
solution. If a larger amplifer can eliminate the need for liquid
cooling or a fan, increased amplifer cost may not even be an
issue. A reasonable starting point for amplifer selection is to
fnd an ABSOLUTE MAXIMUM RATING of twice the power
the circuit will actually dissipate.
R
CS
is often overlooked, but consider this: The PA12 with
a AC thermal resistance of 0.9C/W is mounted on the HS11
liquid cooled heatsink boasting thermal resistance of 0.1C/W.
If T
A
is 25 and R
CS
is 0.1, 125W will place junctions at 162.5C.
If a mica or plastic washer is used or the amplifer is mounted
bare, power to maintain this junction temperature could be cut
to less than 70W! Again, see section 8 below.
The heatsink performance is the last element of the thermal
resistance challenge. A quick glance at an SOA curve showing
the power handling difference between case temperatures of
85C and 125C tells a story; but not the whole story. Data
sheet SOA curves always assume T
J
max is allowed to go to
the ABSOLUTE MAXIMUM RATING. If your design is more
conservative, the difference in power ratings will be even larger.
Also be aware that heatsink ratings should be viewed more a
guideline than an absolute.
7.7 HEATSINK SELECTION
Lets start with the heatsink rating. The HS03 is rated at
1.7C/W in free air. True, when power dissipation is about 45W,
but check the actual curve at 10W and youll fnd a rating more
like 2.3C/W. On top of that, free air means no obstructions
to air fow and the fat mounting surface must be in the vertical
plane. Demands for higher performance in smaller packages
can be at odds with optimum heatsinking. Poor installation
choices can easily reduce effectiveness 50%.
Adding a fan to your design improves the thermal resistance
rating of heatsinks. Please remember: Most fans are rated
in cubic delivery and this rating varies with working pressure.
A 5-inch diameter fan delivering 100 CFM produces over 700
FPM right at the fan. If this air fows through a 19 x 24 inch
rack, theoretical velocity is down to 32 FPM, will vary with
location and goes lower as the rack is sealed tighter.
The bottom line: Without case temperature measurements,
your design effort is NOT complete!
There are two temperature limitations on power amplifers.
A rating for each limitation must be calculated and numerically
lower rating used. The most obvious limitation is the junction
temperature of the output transistors. The case temperature
must also be limited. In addition to reliability concerns (Figure
11 applies to the front end transistors as well as the output
stage), DC error budget items of voltage offset drift and bias
current drift are based on case temperature. Allowing a case
temperature of 85C as opposed to 40C will increase voltage
offset change by a factor of 4 and may double the failure rate
of front end semiconductors. This would be a good time to
recommend reading section 3 where the difference between
ABSOLUTE MAXIMUM RATINGS and Meets full range
specifcations is discussed.
Here are some case-to-heatsink thermal resistance ratings
(R
CS
) of various package styles. These ratings assume the
amplifer is mounted with either an Apex Precision Power alu-
minum thermal washer or with a thin coating of fresh thermal
grease covering the entire mounting surface. If designing the
mounting surface, see the ACCESSORIES INFORMATION
data sheet for recommended hole sizes.
TO-3 MO-127 PD10 SIP02,3 SIP12, 04, 5 (Kapton)
0.1C/W 0.05C/W 0.08C/W 0.1C/W 0.2C/W
Using either thermal model, the heatsink rating based on
case temperature limitations is:
Where:
T
C
= maximum case temperature allowed.
PD = output transistor power dissipation due to load current
PD
Q
= Total quiescent power.
THE SIMPLE METHOD
If PD
Q
is one tenth of less PD, this simple method will work
well. If the amplifer has a slew rate of several hundred volts/
microsecond and the application is above 300V, use the more
accurate method. The simple formula is:
PD PD
Q
out
FIGURE 13. MORE ACCURATE THERMO-ELECTRIC MODEL
TJother = varies & safe by design
TJout=(PD + PDQout) RJC +(PD +PDQ)(RSA +RCS) + TA
TC = (PD + PDQ) )RSA + RCS) + TA
T
Jout
T
Jouther
PD
TC
TS
RJCother RJCout
RCS
RCA
TA
input
Q
T
C
T
A
PD + PD
Q
R
SA
= R
CS
T
T
T
T
J
= P
D
(R
JC
+ R
CS
+ R
SA
) + T
A
FIGURE 12. SIMPLE THERMO-ELECTRIC MODEL
R
JC
R
SA
P
D
R
CS
T
J
AN01
AN01U 687
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Where:
T
J
= maximum junction temperature allowed
R
JC
= AC or DC thermal rest from the specifcation table
THE MORE ACCURATE VERSION
With the unique combination of high voltage and speed such
as the 900V and 500V/us of the PA94, traditional formulas for
heatsink selection will falsely lower the apparent power handling
capability of the amplifer. To more accurately predict operating
temperatures use the following procedure.
Look for an output stage only quiescent current rating in the
data sheet. If the data sheet does not list this specifcation, it
can be estimated as 5% of the total quiescent current.
Find output stage quiescent power (PD
QOUT
) by multiplying
the output stage only quiescent current by the total supply
(V
ss
). Calculate a heatsink rating which will maintain output
transistor junctions at 150C or lower:
Where:
T
J
R
JC
=AC or DC thermal resistance from the specifcation table.
THE EASY AND ACCURATE METHOD
1) Set aside the slide ruler and calculator.
2) Start Power Design, an Excel spreadsheet available free
from www.Cirrus.com
3) Enter amplifer, V
S
, min/max frequency, output amplitude
and load components.
4) Read load, supply and amplifer power levels, heatsink rating
& maybe some warnings.
5) Tweak design as desired.
6) Enter design notes and press Print button for documentation.
7) Ask your boss for a raise.
8.0 AMPLIFIER MOUNTING AND
MECHANICAL CONSIDERATIONS
For Power Op Amp designs, high reliability consists of
mechanical considerations as well as electrical considerations.
Proper mounting is very important for power amplifers. Once
the proper heatsink has been selected as described in Section
7, the following mounting techniques should be used.
All Apex Precision Power metal can products have either
an isolated case, ground connected case or a dedicated pin
for the case. This means electrical insulating washers are
generally not necessary and will likely increase operating
temperatures if used.
In addition, Apex Precision Power uses a thin beryllia substrate
to get the lowest possible thermal resistance. While this leads
to cool running, high reliability amplifers, it is important not to
run the risk of cracking this substrate. In order to prevent this,
two major precautions must be observed:
1) Do not use compressible thermal washers. These are
silicon rubber based pads such as Silpad. The amount
of compressibility in a washer over 2 mil thick can lead to
header fexing, which can crack the substrate. The use of
these washers voids the warranty. Also, thermal grease has
superior thermal properties.
2) When using refow soldering with package types DF
(PSOP1), DK (PSOP2), EF (QFP01) and EK (QFP02), be
aware that these packages are moisture sensitive. These
devices should be baked at 125C for 48 hours and the
refow operation should be performed within 48 hours of
baking. Black carriers (EF and EK packages) are suitable
for baking. Clear plastic tubes (DF and DK packages) are
NOT suitable for baking; the devices need to be removed
from these tubes prior to baking. Caution must be exercised
to avoid mechanical or ESD damage.
3) Do not over torque the case. Recommended mounting torque for
the TO-3 and SIP packages is 4-7 in-lbs (.45-.79 N-m) and for the
MO-127 Power Dip packages (PD10 AND PD12) is
8-10 in-lbs (.90-1.13 N-m). Refer to Figure 14. Apply a thin,
uniform flm of thermal grease or an Apex Precision Power
thermal washer between the case and heatsink. Apply small
increments of torque alternately between each screw when
mounting the amplifer.
Due to dimensional tolerances between heatsink thru-holes
and power op amp packages, extreme care must be taken not
to let the pins touch the heatsink inside the thru-holes. Do not
count on the anodization for insulation as it can nick easily,
exposing bare aluminum, an excellent electrical conductor.
Use plastic tubing to sleeve at least two opposite pins if you
are using a mating socket or printed circuit board. If you are
wiring directly to the pins, it is best to sleeve all pins. Refer
to the Package and Accessories Information section of the
Hybrid & IC Handbook for further details on sleeving sizes,
mating sockets and cage jacks for PC board mounting of
power amplifers. While tefon covers virtually all applications,
the actual requirements are to withstand the maximum case
temperatures and total supply voltage of the application.
Never drill out the entire area inside the pin circle, drill indi-
vidual holes for each pin. Often, heatsinking is accomplished
with a custom heatsink or by directly mounting to a bulkhead.
These approaches require the use of heatsink thru-holes for
the amplifers pins. For the 8-Pin TO-3 package, the main path
for heat fow occurs inside the circumference of 8 pins. Refer
to Figure 15. Therefore, a single, large hole, to allow the 8
pins to pass through, will remove the critical heatsinking from
where it is most needed. Instead, 8 separate #46 drill size
holes must be drilled.
9.0 AMPLIFIER PROTECTION AND
PERFORMANCE LIMITATIONS
9.1 OUTPUT PROTECTION
Attempting to make sudden changes in current fow in an
4-7 IN-LBS
TORQUE MAX
THIN FILM OF THERMAL GREASE
OR APEX THERMAL WASHER
TEFLON
SLEEVING
INDIVIDUAL
PIN HOLES
HEATSINK
FIGURE 14. MOUNTING CONSIDERATIONS
T
J
T
A
(PD + PD
QOUT
) R
JC
PD + PD
Q
R
SA
= R
CS
T
J
T
A
PD + PD
Q
R
SA
= R
JC
R
CS
AN01
688 AN01U
inductive load will cause large voltage fyback spikes. These
fyback spikes appearing on the output of the op amp can
destroy the output stage of the amplifer. Brush type DC motors
can produce continuous trains of high voltage, high frequency
kickback spikes. In addition, mechanical shocks to a piezo-
electric transducer will cause it to generate a voltage. Again,
this can destroy the output stage of an amplifer.
Although most power amplifers have some kind of internal
fyback protection diodes, these internal diodes should not
be counted on to protect the amplifer against sustained high
frequency, high energy kickback pulses. Many of these diodes
are intrinsic epi diodes that occur as a result of the manu-
facture of the power darlington output transistor. Epi diodes
generally have slow reverse recovery times and may have large
forward voltage drops. Under sustained high energy fyback
conditions, high speed, fast reverse recovery diodes should be
used from the output of the op amps to the supplies to aug-
ment the internal diodes. See Figure 16. These fast recovery
diodes should have reverse recovery times of less than 100
nanoseconds and for very high frequency energy should be
under 20 nanoseconds.
One other point to note is that the power supply must look
like a true low impedance source when current fows in the
opposite direction from normal. Otherwise, the fyback energy,
coupled back into the supply pin, will merely result in a voltage
spike at the supply pin of the op amp. This would lead to an
overvoltage condition and possible destruction. Refer to Sec-
tion 4.3 for information on overvoltage protection.
9.2 COMMON MODE VOLTAGE LIMITATIONS
One of the most widely misunderstood parameters on an
op amp data sheet is the Common Mode Voltage Range,
which specifes how close an input voltage common to both
inputs may approach either supply rail. When these limits are
exceeded, the amplifer is not guaranteed to perform linearly.
The Absolute Maximum Common Mode Voltage specifcation
on most data sheets refers to the voltage above which the
inputs may not exceed or damage will result to the amplifer.
There are two cases which clearly illustrate the constraints of
common mode voltage specifcations: single supply operation
and asymmetrical supply operation.
Example:
Th e Ap ex Pr e c i s i o n Powe r PA8 2 J h a s
a Common Mode Vol t age Range of Vs
10. This implies that if the PA82J is to be operated from a
single supply, both inputs must be biased at least 10 volts
above ground. Figure 17 illustrates an implementation of this
which keeps both inputs above 10 volts for the given range
of input voltages. Note that for single supply operation, the
output of the amplifer is never capable of swinging all the way
down to ground. This is due to the output saturation voltage
of the amplifer.
Figure 18 illustrates a very practical deviation from true single
supply operation. The availability of the second low voltage
source allows ground (common) referenced signals but also
maximizes the high voltage capability of the unipolar supply. As
long as the amplifer remains in the linear region of operation,
the common mode voltage will be zero. With the 12V supply
the allowed positive common mode voltage range is from 0 to
2V. Note the output of the PA81J can swing all the way to zero
now also. The 12V supply in this case need only supply the
quiescent current of the power op amp. If the load is reactive
or EMF generating, the low voltage supply must also be able
to absorb the reverse currents generated by the load.
9.3 DIFFERENTIAL INPUT VOLTAGE LIMITATIONS
AND PROTECTION
Exceeding the Absolute Maximum Differential Input Voltage
specifed on the data sheet can cause permanent damage to
the differential input stage. Failure modes range from increased
V
OS
and V
OS
drift, I
B
and I
B
drift, and input offset current, up to
input stage destruction. Although the differential input voltage
(V
ID
) under normal closed loop conditions is microvolts, several
conditions can cause it to be in the Volt range. Causes of V
ID
:
1) Fast rise-time inputs.
2) Signal input while not under power.
3) High impedance output states (current limit, thermal shut-
down, sleep mode).
4) Switching within the feedback loop.
D/A
PA81J
0/5V
2K
50K
+12V
130V
0/125V
FIGURE 18. NON-SYMMETRICAL SUPPLY OPERATION
2.5K
D/A
+2.5/10V
2.5K
50K
+210V
50K
+210V
50K
+210V
PA82J
+50/+200V
50K
FIGURE 17. SINGLE SUPPLY OPERATION:
CM
CONSIDERATIONS V
+Vs
-Vs
OP
AMP
FAST
RECOVERY
DIODES
Supplies must be
able to absorb
transient energy,
i.e., low impedance
NOTE:
FIGURE 16. OUTPUT PROTECTION
FIGURE 15. MAIN HEAT FLOW PATH: 8-PIN TO 3 PACKAGE
AN01
AN01U 689
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
An example of condition 4 is shown in Figure 19a.
This confguration is often used in ATE systems for changing
the gain of an op amp. The amplifers full scale transition time
(microseconds) is faster than the typical relay switching time
(milliseconds); therefore when the relay opens the feedback
loop, the Aol of the amplifer will drive the output to one of the
supply rails. In the example shown, the output will approach
150V while the relay is still switching. Because the 100K
feedback resistor has completely discharged its associated
rolloff capacitor, the relay will connect 150V directly to the
input. Since the Absolute Maximum V
ID
for the PA08 is 50V,
the input stage will be destroyed.
Effective input protection networks provide two functions:
1) Limit differential voltage to less than the reverse breakdown
voltage of the input transistors base-emitter junction, typi-
cally ~6V.
2) Limit input transient current fow to less than 150mA.
Figure 19b shows an example of an input V
ID
protection
network. The diodes should be high speed devices such as
1N4148 and the series impedance should limit instantaneous
current to a maximum of 150mA.
10.0 STABILITY
The most common application problem when working with
power op amps is stability. Although most power op amps
are compensated for unity gain stability, they are frequently
required to drive reactive loads, deliver high currents, or use
high impedances due to high voltage. These conditions make
stability more difficult to achieve. However, EVERY circuit can
be stabilized if the guidelines given here are followed. Table
1 provides a troubleshooting guide for stability problems. The
Probable Cause / Possible Solution Key gives insight
into the origin of the problem and provides guidance as to the
appropriate fx.
An amplifer becomes an oscillator when two conditions are
met: total phase shift reaches 360 and the amplifer has gain
at this frequency. With operational amplifers using negative
feedback, half the required phase shift is provided by the
inverting nature of the circuit. This means phase shift from
all other sources totals a second 180 when oscillating. The
crucial element here is to examine phase shift at frequencies all
V
IN
V
OUT
10K
PA08
+150V
-150V
K1
100K
.001F
500K
.001F
1K
FIGURE 19b. GAIN SWITCHING AND VID PROTECTION
the way out to the intersection of open and closed loop gains.
Putting it another way, just because the circuit is designed for
DC only, does not preclude it from oscillating at 1MHz. Most
Apex Precision Power amplifers have gain well into the MHz
region and phase shifts of both amplifers and parasitic ele-
ments grow rapidly in this area.
KEY TO PROBABLE CAUSE / POSSIBLE SOLUTION
A. Cause: Supply feedback loop (insufficient supply bypass-
ing).
Solution: Bypass power supplies. See Section 4.2.
B. Cause: Supply lead inductance.
C. Cause: Ground loops.
Solution: Use Star grounding. See Figure 21.
D. Cause: Capacitive load reacting with output impedance
(Aol pole).
Solution: Raise gain or use input R C compensation
network. See Figure 24.
E. Cause: Inductor within the feedback loop (noise gain
zero).
Solution: Use alternate feedback path. See AN#5, Pre-
cision Magnetic Defection, or AN#13, V I
Conversion.
F. Cause: Input capacitance reacting with high R
F
(noise
gain zero).
Solution: Use Cf in parallel with Rf. (Cf =~Cin). Do not use
too much Cf, or you may get problem J.
G. Cause: Output to input coupling.
Solution: Run output traces away from input traces, ground
the case, bypass or eliminate R
B
(the bias current
TABLE 1.
CLBW= Closed Loop Bandwidth
UGBW= Unity Gain Bandwidth
See Figure 20 for loop check circuit.
Indeterminate; may or may not make a difference.
*Loop check (Figure 20) will stop oscillation if Rn << |Zcf|
at UGBW .
**Only oscillates over a portion of the output cycle.
Oscillates unloaded?
Oscillates with V
IN
= 0?
Loop Check
fixes oscillation?
Oscillation Frequency (in order of probability)
Probable Cause(s)
CLBW fosc UGBW N Y N A, C, D, B
CLBW fosc UGBW Y Y Y K, E, F, J
CLBW fosc UGBW N Y G
fosc CLBW N Y Y D
fosc = UGBW Y Y N* J, C
fosc <<UGBW Y Y N L, C
fosc > UGBW N Y N B, A
fosc > UGBW N N** N A, B, I, H
CONDITION AND
PROBABLE CAUSE
TABLE
fosc
V
IN
V
O
+V
S
-V
S
Rn
R
I
R
F
Rn
R
1
10
FIGURE 20. LOOP CHECK CIRCUIT
V
IN
V
OUT
10K
PA08
+150V
-150V
K1
100K
.001F
500K
.001F
FIGURE 19a. GAIN SWITCHING AND V
ID
VIOLATION
AN01
690 AN01U
ground loops. For lower frequencies, perform a loop analysis
using Application Notes 19 and 25
10.2 COMMON SOURCES OF NON-LOOP
INSTABILITY
The following is a list of the most common instability situ-
ations reported:
1) Large electrolytic or tantalum capacitors are installed close
to the amplifer pins as recommended, but small ceramic
bypass capacitors are omitted. The circuit may oscillate
because the high frequency impedance of the large capaci-
tors is not low enough to decouple the power supplies.
2) A prototype circuit is checked out and approved. A printed
circuit board is built and all modes of operation test okay.
A step and repeat technique then uses this same artwork
to generate a multiple amplifer board. When tested, every
amplifer on the board oscillates. Cross coupling through the
supplies is a major problem in multiple amplifer circuits. Use
lots of bypass capacitors, ground the case, and consider
all items in the following section.
3) Ungrounded cases can cause oscillations, especially with
faster amplifers. The cases of most Apex Precision Power
metal can amplifers are electrically isolated to provide
mounting fexibility. The case is in close proximity to all the
internal nodes of the amplifer and can act as an antenna.
Providing a connection to ground prevents noise pickup,
cross-coupling or positive feedback leading to oscillations.
Some models have heatsink tabs connected to V
S
, serving
the same purpose as long as V
S
is

clean.
4) A standard inverting circuit includes an impedance match-
ing resistor in series with the non-inverting input to take
advantage of the improved input offset current specifcation.
The high impedance input becomes an antenna, receiving
positive feedback, causing oscillation. Calculate the errors
without using the resistor (some amplifers have equal bias
and offset currents negating the effect of the resistor). If the
resistor is required, bypass it with a ceramic capacitor of at
least .01uF.
10.3 LOOP STABILITY ISSUES
A majority of loop instability problems are due to one or
more of the following:
1) Amplifer compensation not matched to the circuit closed
loop gain. This includes using amplifers below their recom-
mended gain, choosing the wrong external compensation
or failure to realize high frequency (not DC) gain is what
counts. (A feedback or integrating capacitor lowers gain at
high frequency).
2) The use of large impedance values for input or feedback
networks allows parasitic elements too much control. Con-
sider a 100K feedback resister with a parasitic of 3pF.
This places a pole (with an additional 45 phase shift) at
about 53KHz!
3) Capacitive loads reacting with amplifer output impedance,
effectively adding a pole and corresponding phase shift to
the amplifer.
4) Voltage-to-current phase shift of an inductor is inside the
feedback loop of current output circuits.
5) Too many amplifers inside a single loop. Each amplifer
contributes to the total as you go around the loop.
Solutions for these include one or more of the following:
1) Change to an amplifer suitable for lower gain, increase
external phase compensation, or modify the circuit.
2) Lower impedance values.
compensation resistor from IN to ground)
H. Cause: Emitter follower output reacting with capacitive
load.
Solution: Use output snubber network. See Section
10.1.
I. Cause: Composite PNP output stage with reactive
load.
Solution: Use output snubber network. See Section
10.1.
J. Cause: Feedback capacitance around amplifer that is
not unity gain stable (integrator instability).
Solution: Reduce Cf and/or increase Cc for unity gain
stability.
K. Cause: Insufficient compensation capacitance for closed
loop gain used.
Solution: Increase Cc or increase gain and/or use input
RC compensation network. See Figure 24.
L. Cause: Servo loop stability problem.
Solution: Compensate the front end or servo ampli-
fer.
10.1 BASICS OF STABILITY
Some basic practices must be followed to ensure stability.
Proper ground practices are mandatory and are illustrated in
Figure 21. Improper grounding can lead to oscillations near
the unity gain bandwidth frequency of the amplifer. Proper
bypassing of power supplies is also illustrated in Figure 21. The
local bypassing close to the amplifer with a small electrolytic
and ceramic capacitor insure good high frequency grounding
of the supply lines. The internal phase compensation on op
amps will be referred to one of the supply lines and this is the
reason for the importance of good local bypassing.
Table 1 shows the frequency of an oscillation is the most
important clue about its source. For frequencies above unity
gain the amplifer, try a snubber network as shown in Figure
22. For frequencies near the intersection of open and closed
loop gains, check for weak high frequency supply bypass or for
V
IN
R
I
+V
S
-V
S
C
S
R
F
R
S
V
O
1-100
.1-1F
FIGURE 22. OUTPUT R-C-NETWORK ("SNUBBER")
V
IN
R
I
R
B
-V
S
R
F
V
OUT
R
L
+V
S
FIGURE 21. BASIC REQUIREMENTS FOR STABILITY
AN01
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3) Add an isolation resistor outside the feedback loop to defeat
the effect of the capacitive load as shown in Figure 23.
This is the simplest external component solution and has
surprisingly little effect on circuit performance.
4) Increase DC closed loop gain.
5) Increase AC gain only with noise gain compensation as
shown in Figure 24. This technique works well with inverting
circuits but is not recommended for non-inverting circuits.
V
IN
R
I
V
O
R
F
Rn
Cn
+Vs
-Vs
FIGURE 24. INPUT R-C NETWORK COMPENSATION
6) Lower the intersection rate of open and closed loop gains
with a properly sized roll off capacitor. Usually, bigger is
not better.
7) Add an AC voltage gain limiter to the current output circuit.
At the higher frequencies where the inductor demands very
high voltages, this R-C network puts the amplifer into a
voltage feedback mode.
8) Lower amplifer count.
Most of these solutions tend to negatively impact bandwidth,
especially in the current output circuits. Apex Precision Power
has been known to boast, "Any circuit can be made stable".
Notice that bandwidth trade offs were not part of the quotation;
this is where the engineering work lies. Upon looking at the
Application Notes mentioned above, some of you may be think-
ing about the amount of this work, with phrases we can't print
here. Have no fear, Power Design takes care of all the tedious
math and graphing for you making design iterations a snap.
10.4 A FINAL STABILITY NOTE
When youre at your wits end trying to solve an oscillation
problem, dont give up because you have it down to an accept-
ably low level. A circuit either oscillates or it doesnt, and no
amount of oscillation is acceptable. Apply these techniques
and ideas under your worst case load conditions and you can
conquer your oscillation problems.

THE APEX PRECISION POWER DESIGN SUPPORT
REQUEST
The Apex Precision Power Design Support Request provides
technical support all the way through your project. In many
cases, specifc failure prevention can be suggested immedi-
ately. In some instances we will need the amplifer to be sent to
Apex Precision Power for a failure analysis. The results of the
analysis can pinpoint the area of damage which then narrows
down the circuit problem.
V
IN
R
I
R
F
+V
S
-V
S
C
L
FIGURE 23. CAPACITIVE LOAD ISOLATION
R
ISO
IMPORTANT NOTICE
AN02
692 AN02U
AN02 Optoelectronic
Position Control
INTRODUCTION
Power Op Amps are ideally suited for position control because
their response time is fast compared to any mechanical drive
train. The optoelectronic technique of position control can move
to and maintain fxed index points on linear or rotary motion
components while adding no linkages or independently moving
parts. The resulting system features high reliability, accuracy
and repeatability. If the integration of photodiode currents is
required, select a power amplifer with an FET input to maintain
very low bias current levels such that the integrating capacitor
voltage will remain constant during periods when both photo-
diodes are not illuminated. Further selection criteria should be
based on motor ratings and/or available power.
SEQUENTIAL POSITION CONTROL
In the circuit shown in Figure 1, the PA07 integrates the
differential output of the pair of photodiodes and drives the
motor in the proper direction until the photodiode currents are
equal. This differential confguration negates the well known
temperature and time instabilities of optoelectronic devices. To
move between index points, a fxed input current is momen-
tarily switched to the amplifer input causing the amplifer to
drive the motor in the desired direction. The charge on C
F
will
maintain motor drive as the input current is switched off prior
to reaching the index point. As the frst photodiode is illumi-
nated, its output reinforces the current direction of motion. As
the second photodiode is illuminated, its current will reverse
the motor drive, causing the system to lock to the index point.
As motor response and system inertia vary widely, C
F
and
R
F
must be selected for the individual application to provide
proper damping. C
F
must be small enough to allow drive reversal
before the index point passes the second photodiode or the
system will continue on to the next index. Very small values of
C
F
can cause severe overshoot or oscillation leading to motor
burnout and/or drive train failure. R
F1
and R
F2
are required to
stabilize the control loop at the unity gain point and to mini-
mize overshoot. R
L
and C
L
form a lead network which may be
included to improve response time by enabling the amplifer
to modify the motor drive based on a change of the sensor
output. In this manner, a braking force can be applied to the
motor prior to reaching the index point. The motor shown in
Figure 1, having EMF of 14V, will apply a 46V stress across
the conducting output transistor when reversed. With a duration
longer than 5ms, the steady state secondary breakdown line
of the SOA for the PA07 curves requires the current limits to
be set to 1A. See PA07 data sheet.
SINGLE POINT POSITION CONTROL
A variation of the above technique shown
in Figure 2 can be used to return a wheel to
a single index point after rotating in either di-
rection. The low inertia, fast response system
will take the shorter route to the index point
when switched from run to stop. The PA12A
was selected for this application because it
provides high power while keeping bias cur-
rent levels low with respect to the photodiode
currents. To improve response time, the lead
network compensates for motor response
lagging behind any change in drive voltage.
A run control current of sufficient amplitude
to override the photodiode currents is fed to
the amplifer inverting input. Removal of this
current restores control to the photosensors.
POSITION CONTROL MASK
Figure 3 shows details of the wheel prepara-
tion and sensor placements at the stop index.
Arrows indicate direction of rotation when the
corresponding photodiode has the higher out-
put. While it is theoretically possible to achieve
a stable position on the opposite side of the
R
F2
R
F1
C
F
R
CL+
.68
MOTOR
V = 28
EMF = 14V
R
W
= 14
LIGHT
32V
PD1 PD2
-V
+V
+32
FIGURE 1. SEQUENTIAL POSITION CONTROL
.68
R
CL
R
L
C
L
PA07
Optoelectronic Position Control
RUN/STOP
CONTROL
100K 47K
R
L
C
L
R
F1
R
F2
PD1
PD2
PA12A
+15V
15V
MOTOR
LIGHT
R
CL+
R
CL
.06
LEAD NETWORK
FIGURE 2. SINGLE POINT POSITION CONTROL
1F
.06
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wheel, system noise or a slight movement will imbalance the
equal photodiode currents and the higher current sensor will
receive even more light. This causes the wheel to seek the
desired index point. Masking of the wheel at an angle to the
radial softens the control function and prevents overshoot.
SPOT SIZE
Optimum relationship of beam size to active areas of the
photodetectors is shown in Figure 4. A centered beam should
illuminate half the photosensitive area of each diode. Too large
a beam will produce no change of sensor output for a range of
positions, while a smaller beam will produce a nonlinear transfer
function near the center line between the photosensitive areas.
This makes selection of C
F
to dampen the circuit difficult and
requires a higher intensity light source.
DIGITAL INTERFACING
For systems with digital control, Figure 5 illustrates a method
not requiring generation of bipolar control signals thus saving the
cost of digital to analog conversion. When logic lines are low, the
signal diodes will not conduct. This condition leaves control to
the photodiodes. A high level on line 2 will cause current to fow
to the summing junction and the amplifer will swing negative.
A high level on line 1 will raise the summing junction voltage
above ground, and the amplifer will swing positive. Select a
resistance value such that a high logic level will provide at least
twice the maximum current from each photodiode to insure
control override regardless of photodiode signals.
DUAL SENSORS
For applications requiring high precision, the use of a dual
element position sensing PD1(Figure 5) will allow smaller beam
size, tighter beam control and provide better thermal equilib-
rium. The specifed resolution of the detector recommended
for this application is better than .0127mm (.0005 inch). The
detector is a three terminal device requiring a current inverter as
shown in Figure 6 to achieve the differential confguration. Two
equal resistors, R1 and R2, should be scaled to the maximum
photodiode current and swing capability of the signal amplifer.
LINE 1
D1
PD1 PD2 4.7K
LINE 2
D2
R2 R3
4.7K
POWER
OP AMP
FIGURE 5. DIGITAL INTERFACE
4.7K
R1
FIGURE 3. SINGLE INDEX POINT DISK
FIGURE 4. BEAM-SENSOR ALIGNMENT
C
F
POWER
OP AMP
SIGNAL
OP AMP
R2
FIGURE 6. CURRENT INVERSION
R1
AN03
694 AN03U
AN03 Bridge Circuit
Drives
INTRODUCTION
Two power op amps confgured in a bridge circuit can provide
substantial performance advantages:
1. Bi-directional output with a single supply
2. Twice the output voltage
3. Twice the slew rate
4. Twice the output power
5. Half the power supply requirement
Low current outputs can reach the kilovolt range or mulitple
ampere outputs of hundreds of volts can be obtained. To achieve
these levels of performance, both terminals of the load must
be driven and extra components are required.
BI-DIRECTIONAL DRIVE ON A SINGLE SUPPLY
Figure 1 depicts a bi-directional motor speed control us-
ing a single supply which features ground referenced bipolar
input signals. A mid-supply reference created by R3 and R9
establishes the DC operating levels for A1 and A2. Inverter A2
drives the load equally in the opposite direction with respect
to the output of input amplifer A1. This confguration places
both load terminals at the reference voltage with a zero input
condition and prevents premature saturation of either amplifer.
To understand the operation of the circuit, consider A1 as
having two sets of inputs:
1. Voltage dividers from the supply voltage to establish com-
mon mode bias.
2. Actual input signal and tachometer feedback.
One sixth of any supply voltage variation will appear equally
at both inputs of the amplifer. However, the common mode
rejection (CMR) of the op amp will reduce its response by four
orders of magnitude at low frequencies. The low pass function
of C3 insures optimum rejection by keeping the common mode
inputs in the low frequency spectrum. The common mode volt-
age (CMV) range of the amplifer sets the minimum common
mode bias at the inputs of A1. The circuit shown provides a
nominal 5.9V from the supply rail (ground) which allows power
supply variations to 10% below nominal.
For the actual input signal, C1, R1, R2, and A1 form an inte-
grator (non-inverting input is constant). With the control voltage
applied across R2 and the tachometer voltage applied across
R1, integration forces the motor speed to be proportional to
the input voltage. The value of C1 must be selected for proper
damping of the total system which includes the mechanical
characteristics of the drive train.
Resistors R4 and R6 set current limits of A1 to 7.5A. When
A1 current limits, A2 will reduce its output voltage equal to the
voltage change of A1. By insuring A1 will limit prior to A2, power
stress levels of the two amplifers are equalized. In addition
to amplifer protection, this programmability is being utilized
to limit the temperature rise in the motor, thereby increasing
expected life of the system. Maximum continuous load rating of
the motor shown is 10A and locked rotor (stall) current is 20A.
Since locked rotor ratings generally refer to abnormal condi-
tions, the motor is being used near capacity while maintaining
a comfortable safety margin for motor and drive circuit.
The key to accuracy of this circuit lies in matching the divi-
sion ratios from the reference voltage to ground for both the
inverting and non-inverting inputs of A1. The inverting side
division ratio is affected by the impedances of the control
signal and tachometer. Normally, the impedance of a voltage
output DAC and the winding impedance of the tachometer are
negligible. This allows use of cost effective 1% resistors and
requires only trimpot RV1 to provide precision adjustment.
.16mA
.16mA 10V+
T
+35V
V
REF
+35V +35V
C1
R1
29.5 5.5
V = 24V
EMF = 12V
R = 1.2
R5
R7
C2
R8
2K
R12
10K
1.0 F
C3
R9
150
R3
150
RV1
R10
250
R11
4.99K
2K
R6
.08
+5V 5V
M
0/10V
V
TACH
10K
R4
.08
R2
4.99K
A1
V
CM
5.9V
NOTE: V
CM
+V
R1
+V
TACH
= V
REF

FOR V
IN
= +5 : 5.9V + 1.6V + 10V = 17.5V
.1 F
A2
.065
.065
PA12A PA12
FIGURE 1. BI-DIRECTIONAL BRIDGE FOR A SINGLE SUPPLY
Bridge Circuit Drives
MAY 2009
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TRANSIMPEDANCE BRIDGE FOR MAGNETIC
DEFLECTION
The circuit shown in Figure 4 drives the electro-magnetic
defection yoke of a precision x-y display. Two factors constitute
the design challenge of this circuit:

1. Greater than 15V drive levels are required to change current
magnitude and polarity to achieve fast endpoint-to-endpoint
display transition times.
2. Only 15V power supplies are available in the system.
The bridge circuit can drive almost double the single power
supply voltage, thereby eliminating the need of separate sup-
plies solely for CRT defection. The maximum transition time
between any two points is 100s for display ratings of:
Yoke inductance = 0.3mH
Full scale current = 3.75A
DC coil resistance = 0.4 ohms
The voltage required to change the current in an inductor is
proportional to current change and inductance, but inversely
proportional to transition time.
V = di*L/dt
V = 7.5A*0.3mH/100s = 22.5V
The Apex Precision Power low voltage power op amp PA02
is an ideal choice for this circuit due to its high slew rate and
ability to drive the load close to the supply rail. A1 in Figure 4
Ratio match errors will appear as tachometer output errors.
These errors will be of a size equal to the ratio of mismatch
times the reference voltage.
The second major accuracy consideration of this circuit is the
voltage offset of A1. As this error will appear at the tachometer
at a gain of three, the PA12A was selected for its improved
specifcation of 3mV compared to 6mV for the regular PA12.
Changes of input voltage range, RPM range or tachometer
output ratings are easily accommodated. Lowering the values
of R1 and R12 (ratio match still required) will re-scale smaller
tachometer voltage spans or lower RPM ranges to the 5V input
level. While increased input signal levels could be re-scaled
in the same manner, increasing R2 and R11 provides the
required re-scaling with the added beneft of lowering control
signal drive requirements.
Higher voltage tachometer voltage spans require a different
approach to re-scaling due to the CMV limitations at the inputs
of A1. Figure 2 illustrates a technique using a 25V tachometer
which will maintain adequate CMV for A1 with supply voltages
down to 20V. Calculations for the divide by fve network at the
tachometer includes winding impedance to achieve accurate
scaling to the 5 input signal. For error budgets, this factor
of fve must be applied to both the ratio mismatch errors and
voltage offset errors as above. Total gain for calculating offset
errors will be 10.
ELECTROSTATIC DEFLECTION
The cathode ray tube (CRT) shown in Figure 3 requires
500Vpp nominal drive. Allowing for a 5% gain error plus
a 10% (of full scale) centering voltage tolerance, brings the
desired defection voltage swing to 575Vpp. Two PA84 high
voltage power op amps provide this differential voltage swing.
Slew rates of 400 volts per microsecond at the CRT enable the
beam to traverse the face plate in less than 1.5 microseconds.
The gain of A1 is set by (R3+RV1)/R1 at 100. The circuit
provides for both gain adjustment (RV1) and beam centering
(RV2). For proper scaling, R4 and R6 reduce the centering
control voltage of trimpot RV2 to 250mV. C2 provides the
desired low AC impedance to ground to enhance stability and
eliminate noise pickup. A2 inverts the output of A1 at unity gain
(set by R8/R5), to yield an overall gain of 200 for single ended
input signals measured at the differential output. R9 and C4
constitute a second input to A2 with an AC gain of 100 (R9/R8).
Using ground as an input has no direct signal contribution, but
it does allow both amplifers to use the phase compensation
recommended at a gain of 100 (20K, 50pF), thereby achieving
a large power bandwidth of 250kHz.
R1
1K
+150V
150V
GAIN
RV1
10K
R3
95K
1/2W
R5
100K
1/2W
C1
50pF
R6
47K
C2
.47
F
R4
1K
2.5V
p-p
+150V
150V
C3
50pF
R8
100K
1/2W
R9
1K
C4
.047F RV2
10K
+12V
12V
CTR
R7
20K
A2
PA84
A1
PA84
FIGURE 3. ELECTROSTATIC DEFLECTION AMPLIFIER
R2
20K
T
50
175
0/25V
25
10K
10K
5V
10K 8.75V 10K
17.5V
REF
A1
FIGURE 2. HIGH OUTPUT TACHOMETER
FIGURE 4. ELECTROMAGNETIC DEFLECTION AMPLIFIER
1.5K 1.5K 1.5K 1.5K
1.5K
Rs
2
36K
7.5V
1.5K
-15V
+15V
0.4
-15V
+15V
0.3mH
100pF
A1
PA02
A2
PA02
AN03
696 AN03U
is confgured as a Howland Current Pump. Voltage on the bot-
tom of the sense resistor is applied directly to the load; voltage
at the top is the applied voltage plus a voltage proportional to
load current. With both these points for feedback, the ampli-
fer sees a common function of load voltage on both inputs
which it can reject (CMR), but sees a function of load current
differentially. In this arrangement, A1 drives the load anywhere
required (with in saturation limits) to achieve load current
commanded by the input signal. As ratio match between the
two feedback paths around A1 is critical, these four resistors
are often implemented with a resistor network to achieve both
precision match and tracking over temperature. A2 provides
a gain of -1 to drive the opposite terminal of the coil. Gain
setting resistors for A2 are not nearly as critical, a mismatch
here simply means one amplifer works a little harder than the
other. Starting values for the R-C compensation network come
from the Apex Precision Power Power Design tool and are fne
tuned with bench measurements.
A frst glance, it might appear the choice of 2 for the sense
resistor is quite large because the peak voltage drop across it
is 7.5V, or half the supply voltage.
If one were to add to this the peak voltage drop across the
coil resistance (1.5V) and the sense resistor (7.5V), it would
be easy to assume a total swing of 31.5V or greater than 15V
at 3.75A would be required of each amplifer.
Salvation for this problem lies in analyzing current fow
direction.
In the middle graph of Figure 5, we fnd the large sense resistor
does not destroy the circuit drive capability. The main portion
of the transition is complete in about 80s and settles nicely.
In the top graph, we fnd a surprise; both amplifers are actu-
ally swinging OUTSIDE their supply rails. The "upside down"
topology of the output transistors in the PA02 allows energy
stored in the inductor to fy back, turning on the internal protec-
tion diodes. The result is peak voltages in the frst portion of
the transition greater than total supply.
In the bottom graph, we fnd stored energy in the inductor
V

(
V
)
V

(
V
)
I
(
R
C
O
I
L
)

(
A
)
40
0 200 400
TIME (s)
FIGURE 5. MAGNETIC DEFLECTION VOLTAGE AND
CURRENT WAVEFORMS
600
V (RSENSE)
V (COIL)
I (COIL)
V (A)
V (B)
800
20
0
20
40
4
2
0
2
4
20
10
0
10
20
develops voltage across the sense resistor, which ADDS to
the op amp voltage until current crosses zero. In this manner,
peak voltage across the coil is nearly 40V!
The seemingly large value of sense resistor did not kill us
on voltage drive requirements and gives two benefts: First,
internal power dissipation is lower than with a smaller resis-
tor. Secondly, with larger feedback signal levels, the amplifer
closed loop gain is lower; loop gain is larger; fdelity of the
current output is better; and voltage offset contributes a lower
current offset error.
EFFICIENT USE OF POWER SUPPLIES
To illustrate the advantages of the bridge circuit, Figures
6 and 7 show two high performance audio amplifer designs
with equal output power, but substantially different supply re-
quirements. In the circuit of Figure 6, the instantaneous load
current will appear on only one supply rail. This means each
supply rail must support the total wattage requirement and
utilization is only 50% at peak outputs. In contrast, the equal
and opposite drive characteristic of the bridge circuit shown in
Figure 7 loads both positive and negative supply rails equally
during each half cycle of the signal. This improved utilization
reduces size, weight and cost of the power supply for the
circuit in Figure 7 even though input and output power ratings
are essentially equal.
CONCLUSION
Bridge circuits can make the difference when performance
requirements exceed voltage limitations of either the available
power supplies or the power op amps. The input section of
these circuits consists of a standard amplifer circuit for driving
a single ended load. The added amplifer serves merely as
an inverter. It doubles drive voltage by providing an equal and
opposite output, thereby making the output fully differential.
The performance increases usually outweigh the increased
cost and complexity.
C1 150K
R7
8.2K
R3
R5
R4
R1
C2
C3
+30V
30V
PWR = 30V AT 3A = 180W
FIGURE 6. STANDARD AUDIO AMPLIFIER
R2
1K
PA10
.18
.18
1F
.001F
1F
8.2K
R1 R2
R3 150K
R4 150K
R6
.16
.16
R10
A2
PA02
A1
PA02
.2
R9
.2
R5
8
1nF
.47F
.47F
C4
R11
18K
15V 15V
+15V +15V
150K 18K
R8
2.2K
C3 1nF
C2
R7
2.2K
C1
FIGURE 7. BRIDGE AUDIO AMPLIFIER
POWER = 15V AT 3A = 90W
AN05
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AN05 Precision
Magnetic Defection
INTRODUCTION
Closed loop power op amp circuits offer distinct advantages
in current control over open loop systems. Using a power op
amp in the conventional voltage to current conversion circuit,
the negative feedback forces the coil current to stay exactly
proportional to the control voltage. The resulting accuracy
makes many new applications feasible. For example, by plac-
ing the non-linear impedance of the defection yoke inside
the feedback loop, steady state positioning, which is difficult,
if not impossible, to achieve with open loop circuits, can eas-
ily be implemented with a power op amp. In addition, sweep
systems with substantially improved linearity can be designed
using power op amps.
Typical applications include: heads-up displays, which
require random beam positioning or E-beam lithography; and
other complex data displays which can achieve the needed
accuracy with a power op amp. Moreover, the versatility and
ease of use of power op amps will help speed up the design
process while at the same time reducing development cost.
The fnal result will be a more accurate and reliable display
using fewer parts.
HIGH RESOLUTION AND HIGH EFFICIENCY
The vertical defection circuit of Figure 1 was designed to drive
a high efficiency RCA CODY ll tube. The PA02 was selected
for this confguration because of its exceptional linearity and
other advantages such as high slew rate, fast settling time,
low crossover distortion, and low internal losses. All of these
advantages contribute to a superior resolution display.
The key to this circuit is the sense resistor (R
S
) which converts
the yoke current to a voltage for op amp feedback. With the
feedback applied to the inverting input and the position control
voltage applied to the non-inverting input, the summing junc-
tions virtual ground characteristic assures the voltage across
R
S
is equal to the input voltage. Thus, the highly linear control
of the voltage across R
S
insures accurate beam positioning.
The value assigned to R
S
has signifcant impact on the circuit
performance. All op amp input errors such as voltage offset,
imperfect common mode rejection, offset drift, etc., will appear
across the sense resistor, producing current errors. While it is
easy to see large sense resistors minimize DC errors, it takes
a little more study to realize they help dynamic response also.
The R
S
value is a major player in setting the loop gain of the
circuit. Larger feedback voltages will result in noticeable im-
provements in power bandwidth and settling time. The limiting
factors on raising R
S
values are brought on by the fact that load
current fows through them; voltage drive capability decreases;
and power dissipation in this resistor increases.
Weighing these trade-offs between errors, bandwidth, and
efficiency in the selection of R
S
value will produce the optimum
choice for each application. The voltage drive requirements will
then be defned by inductance, transition times and current.
This display must operate at 50Hz or 60Hz with retrace times
of 730s and coil currents of 2.25A
P-P
.
The drive voltage required to change the current in an induc-
tor is proportional to both current change and inductance, but
inversely proportional to transition time.
V
DRIVE
= I * L/t (1)
V
DRIVE
= 2.25A
P-P
* 6.5mH/15.93ms = .918V (2)
V
DRIVE
= 2.25A
P-P
* 6.5mH/730s = 20.03V (3)
To determine the power supply levels, add the supply-to-
output differential rating of the power op amp (from the Amplifer
Data Sheet) and the voltage dropped across the combined
values of the sense resistor plus the coil resistance, to these
drive requirements to arrive at +28V and -9V as follows:
V
DROP
= I
PK
* (R
S
+ R
L
) (4)
V
DROP
= 1.125A
PK
* (2 + 3) = 5.625V (5)
V
S
= V
DRIVE
+ (V
S
- V
O
) + V
DROP
(6)
V
S
= .918V + 2V + 5.625V 8.6V (sweep) (7)
V
S
= 20.03V + 2V + 5.625V 27.7V (retrace) (8)
Caution should be exercised when using asymmetric power
supplies, because the inductive load has the potential to store
energy from the higher supply. This could be initiated by an
abnormal condition causing the high output voltage to remain
on the yoke longer than the normal retrace time. After such
an occurrence, the collapsing magnetic feld would discharge
the stored energy into the lower voltage supply via the induc-
tive kickback protection diodes in the power op amp. This will
produce a voltage transient on the supply rail with its amplitude
a function of stored energy and the transient impedance of
the power supply. If this transient added to the supply volt-
age exceeds the rail-to-rail voltage rating of the amplifer, the
result will be destructive. In such cases, a zener clamp on the
amplifer output should be used.
A note of caution when using modular construction. Instruc-
tion manuals always specify, power down frst, then remove
the module. However, because this doesnt always happen,
protective action should be taken. The mechanical break of
the connection to any inductance, coil or wire, causes high
voltage fyback pulses. The stored energy must be absorbed
somewhere. Its much better to use the zener clamp than to
risk the op amp.
V =
L I
t
YOKE DRIVER:
47F .1F
.1F
47F
9V
+28V
2.25V
R
1K
R
.47
C
10nF
R
.47
2
6
5
7
3
1
R
2
.6.5mH
3
2.25A
p-p
CL+
F
CL
F
S
FIGURE 1. HIGH CURRENT ASYMMETRICAL SUPPLY
PA02
R
D
82K
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Precision Magnetic Deflection
MAY 2009
APEX AN05UREVE
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the amplifer rating because overdrive is small and the R
D
/C
F

network is a feedback path at the equivalent high frequency
signal. At time C, the output current has caught up with the
command signal, so the op amp begins closing the loop and
settling. Time D is the end of the allotted retrace time and the
electron beam is turned back on. Note the non-linearity of
the current waveform between times C and D will not cause
problems because of this timing.
Note that we calculated a supply voltage requirement of
about 73V to change current 5A in 730s, but most of this
change takes place in about 550s. The frst thing making
this possible is shown in the amplifer output voltage trace of
Figure 3, where saturation voltage of the amplifer is much
better than the 6.5V level of the calculations. At time B, current
is still fowing through the negative side output transistor, NOT
the positive side. The stored energy in the inductor is actually
helping the op amp swing closer to the rail. A second factor
helping reduce current slew time is again related to stored
energy. From time B until current reaches zero, voltage de-
veloped across the sense resistor adds to the op amp voltage
rather than subtracting from it. Spice analysis indicates peak
voltage across the coil at time B is 74.6V.
If a circuit does not include offset and amplitude adjustment
capability, the positive peak of the input signal needs to be
increased by an amount equal to the normal current change
between the actual input peak and time D. From Figure 3
this would be about 5A/15.93ms * .32ms 0.1A, or 2.35
VPK

input.
When evaluating slew rates of potential amplifers for these
circuits, note that the amplifer is required to swing nearly twice
the peak-to-peak output in a small fraction of the total retrace
time. In this example, voltage slewing time was about 10%
of the retrace time.
Both the PA02 used in Figure 1, and the PA10 used in Fig-
ure 2, have raised accuracy levels by placing the non-linear
inductive element inside the op amp feedback loop. The very
high gain of the op amp and the use of negative feedback
produces superior linearity.
STABILITY CONCERNS
Since the current control capabilities of this circuit rely on
feedback from the current-to -voltage conversion sense resistor,
phase shift due to the inductance of the yoke will be evident
in the feedback signal. Because the phase shift approaches
90 on a perfect inductor and the phase margin of an op amp
is always less than 90, design adaptations are required to
prevent oscillation.
The network consisting of R
D
, R
F
and C
F
, serves to shift
from a current feedback via R
S
to a direct voltage feedback
at the upper frequencies. This bypasses the extra phase shift
caused by the inductor. In selecting component values for
this network, R
F
should be much larger than R
S
, but should
not exceed 1K for the PA02, because the input capacitance
of the op amp would otherwise add phase shift. In selecting
values of R
D
and C
F
, start with values prescribed by the Apex
Precision Power Power Design tool which will yield a stable
circuit. Spice analysis and bench measurements will usually
allow impedance of both these components to increase and
speed up the circuit.
For an even more powerful version of this circuit, the PA10
power op amp can be used, as shown in Figure 2. With this
device, a 7.8mH 4 coil can be driven at 5A
P-P
with the same
timing requirements. Calculations for this design are:
V
DRIVE
= 5A
P-P
* 7.8mH/15.93ms = 2.45V (9)
V
DRIVE
= 5A
P-P
* 7.8mH/730s = 53.43V (10)
V
DROP
= 2.5APK * (1 + 4) = 12.5V (11)
V
S
= 2.45V + 6.5V + 12.5V 21.5V (sweep) (12)
V
S
= 53.43V + 6.5V + 12.5V 72.5V (retrace) (13)
Both of the circuits illustrated have a 730s retrace time
requirement, met easily by the op amps slew rate and settling
time which is substantially faster.
To better understand this and other applications, Figure 3
illustrates input and output waveforms. Traces prior to time A,
are the end of the sweep portion where current is changing
at a relatively slow rate. The peak output voltage at time A is
roughly the sum of equations 9 and 11.
Retracing begins at time A; the electron beam is turned off;
and the amplifer starts running open loop because output
current is not keeping up with the input command. Circuit
slew rate is displayed between time A and time B where the
output saturates. This slew rate is usually somewhat less than
A B C
200Vs/DIV
FIGURE 3. RETRACE WAVEFORMS
I
(
R
C
O
I
L
)

(
A
)
V
(
A
)

(
V
)
V
(
1
)

(
V
)
3
2
1
0
1
2
3
3
2
1
0
1
2
3
20
0
20
40
60
80
D E
V =
L 1
t
YOKE DRIVER:
47F .1F
.1F
47F
22V
+73V
R
1K
R
.2
C
470pF
2.25V
R
560K
3
4
5
6
1
R
.5
7.8mH
4
5Ap-p
D
F
CL+
F
S
8
2
R
.2
CL
PA10A
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RAPID TRANSITION FOR HEADS-UP DISPLAY
Heads-up displays demand swift transition between any
two points on the screen. The waveforms of Figure 4 depict
the input drive voltage and required current to the yoke to
achieve a single full-scale step in beam position for the circuit
in Figure 5. The 3V levels sustain the steady state current
through the coil resistance and the sense resistors. The 29V
level corresponds to the peak output voltage required for a
position change.
Starting with amplifer slew rates and settling times from
the data sheet, it is determined what percentage of the total
transition time will be required for slewing and settling. A
reasonable starting point would be to allow 50% of the total
transition time.
This circuit was designed for a maximum transition time
of 4s when delivering 2A
PK
currents to the 13H coil. While
the fundamentals of this circuit are the same as previously
detailed, there are differences due to the higher speed. To
achieve rapid transitions, amplifer slew rates must be opti-
mized. As a rule of thumb, compensation for this type circuit
should not be lighter than that specifed for a gain of 100.
Again, the Power Design tool will help selecting values for
R
D
and C
F
. With high speed circuits, it is even more important
to analyze performance on the bench to insure parasitics
don't spoil the circuit.
If 50% of the total transition time is allowed for slewing
and settling, 2s will remain to change the yoke current
with full voltage applied to the coil. Voltage requirements are
calculated as follows:
V = di* L/dt (14)
V = 4A*13H/2s = 26V (15)
V
DROP
= 2A* (.5 + 1) = 3V (16)
V
DRIVE
= 26V +3V = 29V (17)
V
S
= 29V +8V = 37V (18)
With the external compensation selected, the PA09 Data
Sheet indicates the amplifer slew rate will be 400V per micro-
second. For a calculated swing of 58V, the required voltage
slewing time is 145 nanoseconds. Adding the settling time
to 0.01% of 1.2s, the total is comfortably below the 50%
allotment of 2 microseconds.
When the circuit was tested, values were further optimized
for best performance. The value of R
D
had a considerable
effect on damping of the circuit. This could be predicted
because R
D
affects the corner frequency where the roll off
slope must be fattened near the unity gain point. The value
of C
F
was not critical; however, a compensation capacitor
of 2pF, as opposed to the data sheet recommendation of
5pF, helped to increase the slew rate without signifcant
affect on stability.
Due to the high speed of PA09, specifc precautions are
recommended to insure that optimum stability and accuracy
are maintained:
1. To help prevent current feedback, use single point ground-
ing for the entire circuit or utilize a solid ground plane.
2. To insure adequate decoupling at high frequency, bypass
each power supply with a tantalum capacitor of at least
10F per ampere of load current, plus a .47F ceramic
capacitor connected in parallel. The ceramic capacitors
should be connected directly between each of the two
amplifer supply pins and the ground plane. The larger
capacitors should be situated as close as possible.
3. Use short leads to minimize trace capacitance at the input
pins. Input impedances of 500 or less combined with the
PA09 input capacitance of approximately 6pF will maintain
low phase shift and promote stability and accuracy.
4. The output leads should also be kept as short as possible.
In the video frequency range, even a few inches of wire
have signifcant inductance, thereby raising the intercon-
nection impedance and limiting the output slew rate. Also,
the skin effect increases the resistance of heavy wires at
high frequencies. Multistrand Litz Wire is recommended
to carry large video currents with low losses.
5. The amplifer case must be connected to an AC ground
(signal common). Even though it is isolated, it can act as
an antenna in the video frequency range and cause errors
or even oscillation.
TRANSIMPEDANCE BRIDGE FOR HIGHER DRIVE
VOLTAGE
The circuit illustrated in Figure 6 drives the defection yoke
of a precision x-y display from an available 15V supply. Only
the bridge confguration can provide the high voltage drive
levels required with the power supplies available. This enables
the system to drive double the single amplifer output voltage.
Consequently, the need for separate power supplies solely
for CRT defection is eliminated.
A1 in Figure 6 (next page) is confgured as a Howland
Current Pump. Voltage on the bottom of the sense resistor
is applied directly to the load; voltage at the top is the ap-
plied voltage plus a voltage proportional to load current. With
both these points for feedback, the amplifer sees a common
L
13H
1
i = V /R i S
di
dt
= 2A/s
Y
S
R
.5
100
R
F
R
12K
D
C
F 470pF
PA09
8
7
3
+37V
C C
2pF
V i
5
6
37V
4
1
FIGURE 5. PA09 AS DEFLECTION AMPLIFIER
INPUT
V
OUT

I
OUT
0
0
-3V
-2A
FIGURE 4. FULL SCALE STEP FUNCTION WAVEFORMS
+29V
+3V
+2A
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function of load voltage on both inputs which it can reject
(CMR), but sees a function of load current differentially. In this
arrangement, A1 drives the load anywhere required (with in
saturation limits) to achieve load current commanded by the
input signal. As ratio match between the two feedback paths
around A1 is critical, these four resistors are often implemented
with a resistor network to achieve both precision match and
tracking over temperature. A2 provides a gain of -1 to drive
the opposite terminal of the coil. Gain setting resistors for A2
are not nearly as critical, a mismatch here simply means one
amplifer works a little harder than the other. The PA02 brings
a unique combination of high slew rate and low saturation
voltage to this circuit. Starting values for the R-C compensa-
tion network come from Power Design and are fne tuned with
bench measurements.
At frst glance, it might appear the choice of 2 for the sense
resistor is quite large because the peak voltage drop across it
is 7.5V, or half the supply voltage.
Voltage across the inductor required to move the beam is
given by:
V
L
= 300H * 7.5A / 100s = 22.5V (19)
If one were to add to this the peak voltage drop across the
coil resistance (1.5V) and the sense resistor (7.5V), it would
be easy to assume a total swing of 31.5V or greater than 15V
at 3.75A would be required of each amplifer.
Salvation for this problem lies in analyzing current fow
direction.
In the middle graph of Figure 7, we fnd the large sense resistor
does not destroy the circuit drive capability. The main portion
of the transition is complete in about 80s and settles nicely.
In the top graph, we fnd a surprise; both amplifers are actu-
ally swinging OUTSIDE their supply rails. The "upside down"
topology of the output transistors in the PA02 allows energy
stored in the inductor to fy back, turning on the internal protec-
tion diodes. The result is peak voltages in the frst portion of
the transition greater than total supply.
)
V
(
V
)
V
(
V
)
A
(
)
L
I
O
C
R
(
I
40
0 200 400
TIME (s)
FIGURE 7. BRIDGE DRIVE CURRENTS AND VOLTAGES
600
V (RSENSE)
V (COIL)
I (COIL)
V (A)
V (B)
800
20
0
20
40
4
2
0
2
4
20
10
0
10
20
A1
PA02
0.4 100pF
.3mH
A2
PA02
1.5K 1.5K 1.5K 1.5K
7.5V
1.5K
1.5K
Rs
2
36K
15V
-15V
15V
-15V
FIGURE 6. CURRENT-OUT BRIDGE DRIVE
In the bottom graph, we fnd stored energy in the inductor
develops voltage across the sense resistor, which ADDS to
the op amp voltage until current crosses zero. In this manner,
peak voltage across the coil is nearly 40V!
The seemingly large value of sense resistor did not kill us
on voltage drive requirements and gives two benefts: First,
internal power dissipation is lower than with a smaller resis-
tor. Secondly, with larger feedback signal levels, the amplifer
closed loop gain is lower; loop gain is larger; fdelity of the
current output is better; and voltage offset contributes a lower
current offset error.

CONCLUSION
The capabilities of the power op amp provide higher accuracy
levels, the ability to position beams in any desired position and
to retain a steady state position. Having both the power and
signals stage in one compact package offers space/weight
advantages. The lower parts count increase reliability.
Power op amps are comparatively inexpensive and easy
to use. They represent the most efficient solution to reducing
development costs and decreasing design time.
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AN06 Applying the
Super Power PA03
have major drawbacks in increased cost, excessive weight
and reduced reliability. Furthermore, the large size can be a
cumbersome design burden. System designers need a small,
reliable power op amp capable of producing up to 1,000W
while maintaining top notch performance. The PA03 meets
this challenge!
Using the super power PA03 offers many advantages.
With an internal power dissipation of up to 500W, the PA03s
ratings top the previously most powerful op amp (Apex Preci-
sion Power PA12) by a factor of four, and one PA03 is more
cost effective and far more reliable than four less powerful op
amps. Its thermal tracking of internal bias components makes
the PA03 much safer to use under abnormal conditions than
several units in parallel. Moreover, internal protection circuits
insure that almost any power level not violating the 2,400W,
1ms Safe Operating Area (SOA) is safe. The amplifer will
shut down upon overload, avoiding self-destruction. Internal
current limiting resistors eliminate bulky, expensive milliohm
external resistors which are normally required for power op
amps. The common collector complementary output stage
allows the output to swing within 4V of the supply rail at 12A
and within 6V at 30A and has full shut-down control. This gives
the designer a tool to protect sensitive loads or to minimize
power consumption under battery operation. By operating in
class A/B, it exhibits low crossover distortion, a feature hard
to implement without the inherent thermal tracking of single
package construction.
INTRODUCTION
The super power PA03 is the result of a design effort to
substantially increase output power without sacrifcing the high
performance engineers are accustomed to when using small
signal op amps. Thus, this new building block can perform
accurate and complex tasks previously reserved to modular
and rack mount devices.
The major applications for the PA03 will be in single ended
circuits where up to 1,000W must be delivered to the load or
in bridge motor servo systems delivering up to 2,000W peak.
Linear motion control, magnetic defection, programmable
power supplies, and power transducer drives are typical of
these applications. High power sonar, such as phased array, is
another key application made possible by the accurate phase
response and linearity of the class A/B output stage. Robot,
motion control, and other high current applications which were
previously impossible to implement with IC Power Op Amps
because of power limits, are now possible using the PA03 as
a building block.
The most powerful TO-3 hybrid ICs currently available can
dissipate up to 125W and drive loads up to 250W (Apex Preci-
sion Power PA12), while available monolithic ICs handle less.
Where peak power requirements for dynamic motor control
exceed 250W, three approaches were commonly used to
increase power output: (1) parallel or bridge operation of two
or more power op amps; (2) external booster transistors; (3)
modular or rack mount power op amps.
While these options extend power capabilities, they can
C1 1.0nF
R1A
200K
R1B
50K
R2A
50K
R2B
50K
+88V
A2
C3
3.3nF
R4
1K
R10A
50K
R15
1K
C6 3.3nF
R10B 200K
R10D
200K
R17
82K
R10C
50K
R8D
50K
R8C
200K
R13B
50K
R13C
50K
R13D
200K
R1C
200K
+88V R12
.05
50W
R9
2.4M
R11
.05
50W
R8A
200K
+88V
C5
3.3
nF
R2C
50K
R16
250K
C2
3.3
nF
R2F
50K
R13A
200K
R7
250K
R2D
50K
R5
.05
50W
R6
.05
50W
R14
1K
+15V
15V
R8B
50K
R3
1K
+88V
A1
50A
70V
1.4
R1D
50K
C4 10nF
DRIVE NODE
REFERENCE
NODE(+44V)
+88V
+88V
+88V
+88V
1.25V
+15V
15V
1 2
A4
FIGURE 1. APPLYING THE SUPER POWER PA03
M
A5
R2E
50K
A3
Applying The Super Power PA03
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An external balance control option allows the already low
offset voltage to be zeroed. The PA03s high overall accuracy
makes it suitable for interfacing directly to photo-diodes; to
build long time period integrators; or to design 12 bit and better
resolution programmable power supplies.
The super power PA03 is a hybrid IC housed in the innova-
tive Power-Dip dual in-line package. It has .060 pins on .200
centers to accommodate higher currents and allows layout on
the standard 0.100 grid. The Power-Dip copper header of the
PA03 provides 8.5 times the thermal conductivity, and three
times the area of the conventional steel TO-3 package.
A SUPER POWER TORQUE DRIVE
The parallel bridge circuit in Figure 1 is shown to demon-
strate several possible power enhancement techniques in one
application. It operates in the transimpedance mode to drive
the torque motor. This allows the D to A converter (DAC) to be
programmed directly for delivered torque, since motor torque
is directly proportional to armature current. The bridge uses an
economic and efficient single output power supply and doubles
delivered power levels again by increasing the current drive
capability. Delete A3 and A4, and associated components if
this option is not required.
Looking at the bridge confguration frst, A2 and A4 invert the
output of A1 and A3 with respect to the mid-supply reference
node. Therefore, A2 and A4 drive the load equal to A1 and A3
in the opposite direction about the mid-supply reference point.
The mid-supply node assures that neither amplifer saturates
prematurely. Figure 2 shows the actual output voltages of A1/
A3 and A2/A4 when delivering full scale output currents to
the torque motor.
A5 (Figure 1) confgured as a level shifter at a gain of 4,
takes the 1.25V input from the DAC and swings the drive node
to 5V with respect to the reference node. A1 and A3 each
amplify this differential 5V signal to a 25A output level driving
terminal 1 of the motor. A4 is a unity gain follower of the A2
output voltage. Since A2 and A4 have equal output voltages
and equal current control resistors, they share the total 50A
current equally.
The very low bias current of the PA03 FET input stage makes
it possible to keep power dissipation low by using relatively large
value precision resistors. This not only minimizes temperature
variations in the resistive networks, but also reduces power
dissipation in A5. Current balancing for both the reference
and drive nodes is used to prevent level shifting of the high
impedance nodes as a function of drive voltage. This is an
easy task because of the symmetric drive levels with respect
to the reference node.
A1 A2
A3 A4
1 2
M
+80.25V
(+7.75V)
+7.75V
(+80.25V)
+80.25V
(+7.75V)
+7.75V
(+80.25V)
.05 .05
.05 .05
FIGURE 2. FULL SCALE DRIVE VOLTAGES
+9V
(+79V)
+79V
(+9V)
Figure 3 shows a breakdown of the currents associated with
the reference node. R2E and R2F form the basic voltage divider.
At a zero drive level, the current through R13A and R13B will
match the current through R7. The voltages applied to R1, R8,
R9, and R10 will all be zero with respect to the 44V reference
so the circuit is balanced. The voltages shown correspond to
full scale drive level. R7 roughly balances the current through
R13A and R13B to the +1.25V DAC input. R10A, R10B, R10C,
and R10D current will nearly match the currents of R1C and
R1D plus R8A and R8B. The differences encountered so far
total 15 microamps, which is provided by R9 to insure the
reference node remains at 44V.
Figure 4 illustrates currents associated with the drive node
where R2C and R2D form the basic voltage divider. At zero
drive, no voltage is applied to R17, R1 and R8, and the output
of A5 will be zero and the drive node voltage will be 44 volts.
This means currents of R2C and R2D balance. The currents in
R16 balance the currents of R13C and R13D and the remain-
ing resistor currents are zero. For a full scale input of +1.25V,
A5 will drive to approximately +10V. The currents through
R16, R13C and R13D are no longer balanced because the
drive node voltage has risen to 49V. The currents through
R1A and R1B, plus R8C and R8D, make the node even less
balanced. R17 was selected to slightly over compensate the
current imbalance. Since the differential circuit of A5 (Figure 1)
REFERENCE
NODE (44V)
880A
+88V
176A
+88V
145A
+80.25V
145A
+80.25V
880A +1.25V
171A
+9V
140A
+7.75V
165A
+9V
140A
R2E
50K
(44V)
R7
250K
(44V)
R10B
200K
R10A
50K
(36.25V)
R10D
200K
R10C
50K
(36.25V)
R2F
50K
(44V)
R13A
200K
(42.75V)
R13B
50K
R1C
200K
(35V)
R1D
50K
R8A
200K
(35V)
R8B
50K
R9
2.4M
(36.25)
FIGURE 3. CURRENT BALANCING OF THE REFERENCE NODE
780A
+88V
156A
+88V
381A
+80.25V
+9.44V
791A
196A +7.75V
165A
+7.75V
165A
DRIVE
NODE (49V)
R2C
50K
(39V)
R16
250K
(39V)
R17
82K
(31.25V)
R2D
50K
R13D
200K
(49V)
R1A
200K
(41.25V)
R8C
200K
(41.25V)
R13C
50K
R1B
50K
R8D
50K
FIGURE 4. CURRENT BALANCING OF THE DRIVE NODE
AN06
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current on the four-terminal shunt resistor, and provides a
signal of 0.333V/A to the comparator. The comparator will trip
at a current of 18A, setting the latch, and the latch then shuts
down the PA03 until the fault is cleared and the latch is reset.
This safety circuit limits arcing hazards in the test socket.
The feedback resistor of 16K yields the required 32V
full-scale output when the DAC output is 2mA. The 0.05
current sense resistor develops a 0.75V signal at the full-
scale output current of 15A. This amplitude is a compromise
between monitoring the current accurately without imposing
an excessively high power rating on the sense resistor. How-
ever, the sense resistor still must be mounted on a heatsink
due to 11.25W dissipation at 15A and the possible 88W at
the built-in maximum current limit of 42A.
To derive the power supply voltage needed, the 0.75V
drop on the sense resistor must be added to the headroom
(supply-to-output differential) required by the op amp. From
the PA03 specifcations (a drop of 7V at 30A and 5V at 12A), a
maximum drop of 6V at 15A can safely be assumed. Selecting
a positive voltage of 39V leaves a margin of 0.25V. Without
remote sensing, such a conservative approach is best due
to potential IR drops in the high current leads. For the nega-
tive supply, a minimum operating voltage of 10V is required
to satisfy the input common mode voltage specifcations.
Four power levels must be examined to determine the worst
case maximum power dissipation of the power op amp. The
frst three are the output voltage levels for the devices under
test at the maximum current of 15A. Calculating all three shows
the 18.5V output to be the worst case scenario. The 18.5V
output plus the 0.75V drop across the sense resistor leaves
a voltage of 19.75V across the output stage of the PA03. At
15A, this produces an internal power dissipation (including
quiescent power of 9.8W) of 306W and a junction to case
temperature rise of 92C (PA03 =0.3C/W).
Because the worst case power demand exists only for
500ms, an examination of average power and thermal time
constants will help to reduce the heatsink size. Figure 6 shows
the general test plan and the specifc testing sequence with
the resulting power dissipation levels demanded of the PA03.
The 32V output level requires 103.6W (39V supply less 32V
output and 0.75V across the sense resistor times 15A plus
9.8W of quiescent power) for 500ms. The 28V level amounts
to 163.6W (39V supply less 28V output and 0.75V across
the sense resistor times 15A plus 9.8W of quiescent power)
for another 500ms.
For the balance of the test of 4.5s, the maximum current of
controls drive node voltage, its nominal swing will be a 9.44V,
correcting the overall current imbalance of 12A. Thus the
overcompensation of R17 insures A5 will not be required to
swing beyond its rated 10V due to component tolerances.
There are a lot of resistor networks in the circuit, but each
has a critical task. The ratios are most important to insure gain
accuracy. In addition, ratio matching provides common mode
rejection and differential voltage amplifcation. Specifcally,
the R13 quad around A5 sets drive node swing to +5V with
respect to the reference voltage even though the reference
changes with supply variations. Similarly, the R1 quad and
the R8 quad set the full scale voltage across sense resistors
R5 and R11 at 1.25V. The 35V output swings across the
impedance of the torque motor are rejected as a common
mode signal to maintain the programmed voltage to current
transfer function. Thus impedance variations of the motor
winding and the associated connections do not affect accuracy.
R10 fxes the gain of A4 to unity while keeping its input pins
about 4V closer to the reference than the amplifers output
voltage. With the output swinging to within nearly 7V of the
supply rails, the common mode voltage requirement of Vs
10V is satisfed.
A PROGRAMMABLE POWER SUPPLY USING THE PA03
Figure 5 shows the PA03 in a simple, reliable programmable
power supply which utilizes the PA03s shutdown features. It
requires little calibration because the current to voltage con-
version of the D to A converter output is done by the power
op amp itself, and the 12 bit DAC80 provides accuracy levels
high enough to eliminate the need for adjustments.
The programmable power supply is designed to test DC-
to-DC converter modules drawing up to 15A. The majority of
tests are performed at 28V. High and low limits of 18.5V and
32V will be applied for 500ms. The outputs must be accurate to
within 0.5% and survive an occasional short circuit to ground.
The OP07 differential amplifer circuit senses the D.U.T.
DAC80
SHTDN+
SHTDN
+39V
+5V
+39V 16K
3R 3R
.05
10V
R
+15V
RESET
CLEAR
FAULT
CMOS
LATCH
+5V
+15V
15V
.019R
.001R
ANALOG
OUT
5V = 15A
.333V/A
.999
R
D.U.T.
0/-2mA
FIGURE 5. HI-POWER PROGRAMMABLE POWER SUPPLY
APPLICATION
COMP
OP07
PA03
1.8nF
OV
OA
9.8W
4.0

3.92
18.5V
15A
306
W
.5
15.3
28V
1A
20.8W
2.0s
4.16
28V
15A
164
W
.5s
8.2
28V
1A
20.8W
2.5s
5.2
32V
15A
104
W
.5s
5.15
41.93W
P (W)
AVG
FIGURE 6. PROGRAMMABLE POWER SUPPLY INTERNAL
POWER DISSIPATION
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1A amounts to 20.8W. During the minimum removal/insertion
time of 4s, the power dissipation is only the quiescent power
of 9.8W. This means the average power dissipated is only
41.9W. With a heatsink that has a thermal time constant of ten
seconds, the highest peak (306W for 500ms) amounts to 5%
of the time constant, or 4.9% of the rise for 306W continuously.
Adding this spike equivalent of 15W to the 41.9W average will
bring the peak short term equivalent power to 57.23W (though
this peak could vary slightly depending upon the exact timing).
If, for reliability, a peak junction temperature of 150C is
selected, and a maximum ambient temperature of 38C is as-
sumed, the allowable temperature rise of the heatsink is 18C
(150C 38C 92C). At a peak short term equivalent of 52.2W,
this requires a heatsink rated at 0.35C/W. The Apex Precision
Power HS06 (0.6C/W free air) with a forced air velocity of 500
ft/min can provide the required rating.
In this application, if abnormal situations arise due to faulty
timing or defective test units, short term operation at the 306W
level will not destroy the PA03 because the thermal shutdown
will limit the temperature rise. The worst case would be a short
in the test socket which could push the PA03 to a maximum
current limit of 42A. At this current, the sense resistor (R
S
) would
drop 2.1V leaving 36.9V across the PA03. These current and
voltage levels (1.55KW) are well within the PA03s 1ms second
breakdown line of the SOA curve. Therefore, the fast response
of the PA03s thermal shutdown circuit will protect the power
op amp for the time required to eliminate the short.
REMOTE SITE MOON BOUNCE ANTENNA MOTOR DRIVE
Power conservation is essential for solar powered data gath-
ering, while a considerable amount of motive force is required
for positioning a 40 Ft dish antenna.
With a 3 beam angle and a position accuracy of 0.5, the
lunar angular velocity of 14.4/Hr allows a position update
only once per minute. The PA03s shutdown control used for
intermittent operation combined with a worm gear drive to
hold position during shutdown periods, facilitates an energy
efficient positioning system.
The D to A Converter in Figure 7 converts position data to
a voltage which is fed to the inverting input of the PA03 con-
fgured as an integrator by feedback capacitor C1 and input
resistor R1. The precision reference and potentiometer apply
a feedback voltage equivalent to actual position to the non-
inverting input. The PA03 drives the motor with the integrated
difference between the desired and actual positions. R2 acts
M
DAC
REF
10V
+24V
1.8nF
+5V
SHT DN
R1
+S
S
C1
R2
0/10V
PA03A
FIGURE 7. REMOTE SITE MOON BOUNCE APPLICATION
24V
as a damping element limiting the integration time constant
to minimize overshoot.
The shutdown control is released for six seconds after each
position update, which allows the PA03 sufficient time to posi-
tion the antenna and reduces the standby power to 2W for 54
seconds or 90% of the time.
The normal current requirement of the motor is 8A, but
under high wind conditions, up to 17A may be drawn. In this
application, the amplifer output will be decaying pulse; thus
driving the motor to a new position once a minute. Because
the amplifer is at maximum output (saturated) most of the
time, the power dissipation at the full output voltage is the
appropriate level to calculate.
At 17A the PA03 will drive to within 5.5V of the supply volt-
age (rail) dissipation of 93.5W. The quiescent current of 0.2A
times the total supply voltage of 48V adds another 9.6W for
a total of 103.1W dissipated in the amplifer. At the maximum
ambient temperature of 45C and a maximum junction tem-
perature of 140C, the allowable rise is 95, which requires a
thermal resistance for the heatsink as follows:
Q
HS
= 95/103.1 0.3 = 0.62/W.
The Apex Precision Power HS06 meets this criteria.
Under normal low wind conditions, the peak battery drain will
be 201.6W. However, due to the 10% maximum duty cycle and
the power-saving shutdown feature of the PA03, the average
power consumption will be only:
P
AV
= 0.1 (24*8+48*0.2) +0.9 (48 *0.040) = 22W
To further reduce standby power to 2W, the shutdown feature
can be activated only when communications are required.
USING THE PA03 IN YOUR APPLICATION
To achieve maximum efficiency, the power supply voltage
should be selected for the minimum voltage necessary to
produce the required output.
For example, to obtain a 45V output at 12A, add the sup-
ply-to-output differential as specifed on the Data Sheet (5V)
to produce 50V.
Dual supplies may be as high as 75V and asymmetric
or single supply operation is permitted as long as the total
rail-to-rail voltage doesnt exceed 150V. Input voltages must
always be at least 10V less than the power supply voltage
due to the common mode voltage specifcation being supply
voltage minus 10V.
Because of the greater power levels involved, the ther-
mal path to remove the heat from the amplifer is of great
importance to the successful application of the PA03.
A 1C/W rated heatsink may be suitable to remove 20-
50W, but it is insufficient to handle 500W. For the PA03,
a heatsink with a thermal resistance on the order of
0.1C/W is often required such as: very large surfaces, forced
air cooling, or even water cooling. Fortunately, if insufficient
heatsinking is provided, the unique safety circuits of the PA03
will generally result in thermal shutdown rather than destruction.
Destructive power levels are so high that in most applications
they need not be of any concern.
As with all high current Power Op Amps, precautions must
be taken to avoid current feedback due to voltage drops in the
wiring of electromagnetic radiation. This is especially true when
using the PA03 because of its higher current rating. The wiring
for all supply and output leads must be done with wire equiva-
lent to 12 gauge or thicker, as the PA03 has a higher current
capacity than most branch circuits in residential wiring.
To avoid feedback through the power supplies, they must
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be bypassed with a ceramic capacitor of 0.47F or greater,
in parallel with a 10F per ampere of peak output current
(up to 300F), mounted not more than 1.5 inches from the
supply lines.
Even when using excellent bypassing components, good
layout techniques and quality power supplies can easily cause
substantial AC ripple. Ripple must be considered as a possible
source of error. Positive feedback can also occur if the power
supply also powers other circuit elements.
WATCH THE POWER DISSIPATION
The internal power dissipation (P) in a DC circuit is:
P = (V
S
V
O
) I
O
+(| + V
S
| + | V
S
|) I
Q
where: I
O
: OUTPUT CURRENT
I
Q
: QUIESCENT CURRENT
V
O
: OUTPUT VOLTAGE
V
S
: SUPPLY VOLTAGE
Errors often arise in the calculation if the wrong supply volt-
age is used. The voltage (V
S
) must be the one at the supply
pin sinking or sourcing the current. Incorrect selection of the
worst case conditions (short to ground or supplies) can also
create errors.
When driving reactive loads, due to the phase shift between
output voltage and current, the power dissipation may be several
times higher than the equivalent resistive loads. These have a
totally different, but equally simple approach that can be used
to obtain the correct power dissipation (P):
P = P
I
P
O
where: P
I
= POWER DRAWN FROM THE POWER SUP-
PLY
P
O
= POWER DELIVERED TO THE LOAD
Keep in mind that using purely reactive loads means that all
power drawn from the supplies is dissipated in the amplifer.
JUNCTION TEMPERATURES
The absolute maximum power dissipation of the PA03 is
500W and was derived using the industry standard derating
procedure. This assumes operation at maximum junction
temperatures (175C) with the case at 25C.
With the power dissipation and the maximum ambient
temperature (T
A
) of the application known, the operating
temperatures of both case (T
C
) and junction (T
J
) of the power
transistors can be determined:
T
C
= T
A
+ P
HS

where:
HS
= THERMAL RESISTANCE FROM THE HEAT-
SINK MOUNTING SURFACE TO AMBIENT
AIR

JS
= INTERNAL THERMAL RESISTANCE,
JUNCTION TO CASE
Apply this to the PA03 by following these steps:
1. Calculate the maximum internal power dissipation (P).
2. Determine the maximum junction temperature allowable to
achieve the desired reliability of the PA03. This must be less
than 175C. Apex Precision Power recommends 150C or
less.
3. Calculate T
J
T
A
, the allowable rise of the junction tempera-
ture above the maximum ambient temperature.
4. Calculate the required thermal resistance of the heatsink:
HS
= (T
J
T
A
)/P
JC
For example, in a circuit dissipating 300W at an ambient
temperature of 30C and the junction temperature not to
exceed 150C:

HS
= (150 30)/300 0.3 = 0.1C/W
HOW THE PA03 WORKS
The circuit diagram shown in Figure 8 shows that the input
section of the PA03 is similar to most Apex Precision Power
FET input hybrid power op amps. Q21, D1 and D4 form voltage
references to bias both input and output stages of the amplifer.
Q31 is the current source for the input stage which consists
of Q20A and Q20B (the FET input pair), Q17 and Q18 (the
cascode transistors), and Q2 and Q3 (the half dynamic load).
The current through Q5 sets the operating voltage (source-
drain) for the FET input pair.
Q12 acts as an impedance
buffer between the high
output impedance of the
input stage and Q6, the
output driver.
The collector load of
output driver Q6 consists
of current source, Q29, and
the output stage consisting
of Q16, Q9, Q24, and Q26.
The common collector con-
fguration of Q9 and Q26
enable the PA03 output to
swing close to the supply
rails. Inverters Q16 and
Q24, form local feedback
networks which cause the
output stage to be linear
like an emitter follower with
very high input impedance. The V
BE
multiplier Q19, provides
DC bias for the output transistors via Q16 and Q24, and is
thermally coupled to the power dissipating transistors in the
output stage. In addition, the V
BE
multiplier utilizes thermistors
to fne tune the temperature stability of the quiescent current
through output transistors Q9 and Q26. This class A/B stage
provides low crossover distortion, as well as stability of the
quiescent current over the full temperature range.
3
4
5
2
1
12
11
8
7
6
9
10
V
+
BAL
BAL
+V
Q31
Q20
A
Q17
Q2
Q3
Q5
Q20
B
Q18
+SHUT
DOWN
SHUT
DOWN
Q14
Q22
Q21
COMP
Q12
D1
Q1
Q6
Q7
Q19
Q29
Q30
Q34
Q32
Q26
D3
OUT
Q9 D2
Q16
Q4
FIGURE 8. PA03 EQUIVALENT SCHEMATIC
D4
+
Q24
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CONCLUSION
The PA03 is a versatile new building block which eases
many design tasks and overcomes size and weight barriers
which previously prevented implementation of linear power
controls in limited space. The giant step up in power levels,
improved protection circuits and high performance small signal
characteristics make the PA03 a very cost effective innovation.
D2 and D3 are high speed diodes which protect the output
stage from inductive kickback by bypassing it into the supply
rails. The 18.6 milliohm emitter resistors of Q9 and Q26 sense
the output current of the amplifer. Currents in excess of 35
amps will develop .65 volts, thereby turning on Q1 or Q34.
In turn, these transistors rob the base drive from Q6 or Q29,
thus limiting the output currents to 35A. Q4 and Q32 are the
sensors for the innovative SOA protection of the PA03. These
two transistors are mounted directly on top of power transistors
Q9 and Q26, eliminating thermal gradients and minimizing the
response time to temperature changes in the output transis-
tor junctions. The emitters of the sensors are connected to
Q7 and Q30 which act as level translators to turn on current
limit transistors Q1 and Q34, respectively. The complementary
pair Q14 and Q22 activate the shut down of the PA03. While
common mode voltage is rejected, differential voltages ap-
plied between these two transistors turn on the current limit
circuit consisting of Q1 and Q34, thereby shutting down the
entire output stage. In this mode the output pins appear as a
high impedance to the load. Figure 9 illustrates the physical
arrangements to achieve fast and reliable thermal shut down.
THERMISTOR EPOXY JUINCTIONS:
THE HEAT SOURCE
SOLDER
Q19
BeO
COPPER HEADER
HEATSINK
Q4,32
POWER TRANSISTOR Q9,26
FIGURE 9. THERMO-MECHANICAL DESIGN
H
E
A
T

F
L
O
W

H
E
A
T

F
L
O
W

IMPORTANT NOTICE
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AN07 Progammable
Power Supplies
INTRODUCTION
The programmable power supply (PPS) is not only a key
element in automated test equipment, but it is also used in
felds as diverse as industrial controls, scientifc research and
vehicular controls. When coupled to a computer, it bridges the
gap from the software to the control task at hand. This application
note examines the basic operation of the PPS, the multitude of
possible confgurations and the key accuracy considerations.
VOLTAGE OUTPUT VERSIONS
The most basic and often most accurate version of the PPS
requires only a current output Digital to Analog Converter
(DAC), a power op amp and a feedback resistor as illustrated
in Figure 1. According to op amp theory, the voltage at the in-
verting input (summing junction) will be zero and op amp input
current will be zero. As a result, all current from the DAC fows
through the feedback resistor R
F
. Ohms law then causes the
circuit to provide a precise output voltage as function of DAC
output current. Given a perfect DAC and feedback resistor, only
two op amp parameters contribute signifcantly to the output
voltage errors. These are voltage offset (V
OS
), modeled by the
battery, and bias current (l
B
), represented by the current source.
Due to the high output impedance of the current output DAC
in relation to R
F
, V
OS
errors appear at the output without gain.
For a 10V output and op amp offset of 5mV, this error
contributes only 0.05%. For a 100V output, a 0.5mV offset
contributes an error of only 5ppm. Clearly, the DAC can easily
be the major error source.
Op amp bias currents add to the DAC output current. The
majority of available DACs have full scale currents of 1mA
or 0/2mA. Most of todays bipolar input power op amps feature
bias currents of less than 50nA. This results in errors of only
25 ppm maximum of the full scale range (FSR). FET input bias
currents at 25C are seldom over 100 pA and are specifed
as low as 10pA. These errors translate to 0.05ppm and 0.005
ppm. Since FET bias currents are generally characterized as
doubling every 10C, the bias current of the two examples
could become 100nA and 10nA at 125C, producing errors
of 50ppm and 5.4ppm, respectively. Again,the DAC is the
critical error source.
To determine the signifcance of the error contribution of a
specifc power op amp to the performance of various systems,
refer to Table 1, next page. The least signifcant bit (LSB) is the
value of the smallest step change of output. Comparing the
calculated errors to the LSB values reveals system compatibility.
For current output, DACs op amp bias currents compare directly
with the DAC current LSB and V
OS
errors compare directly with
the full scale output voltage. Thus, the importance of low bias
currents is dependent solely on system resolution. However,
the signifcance of voltage offset specifcations varies with both
resolution and full scale voltage range.
USING VOLTAGE OUTPUT DACS
When using a voltage output DAC, the power op amp can
be added with either inverting or non-inverting gain to form the
PPS. It usually costs more than implementation with a current
output DAC, and has less accuracy. However, system or logistic
factors may dictate the use of the voltage output DAC.
Figure 2 illustrates the basic inverting gain version and Figure
3 shows a non-inverting setup. Error calculations are still simple
even though some new variables have been added. Voltage
offset errors appear at the output multiplied by the gain of the
circuit (A
V
+1 for inverting circuits). To maximize accuracy, the
highest output DAC's should be used with minimum voltage
gains in the op amp confguration. When using 10V DACs,
a direct Vos to LSB comparison can be made using the 20V
FSR values listed in Table 1. Also, bias currents fow through
the feedback resistor producing output voltage errors; thus,
values of R
F
and R
IN
are usually kept as low as possible.
A CASE FOR REMOTE SENSING
The circuit of Figure 4 shows the wire resistance (R
W
) from
the power op amp to the load and back to the local ground
via the power return line. A 5A load current across only 0.05
DAC
R
V
F
FIGURE 2. INVERTING VOLTAGE GAIN
RIN
AV = RF/RIN
DAC
R
F
FIGURE 4. REMOTE SENSING PROGRAMMABLE POWER SUPPLY
R
IN
R
W
R
IN
POWER
OP AMP
HI SENS
LO SENS
RTN
OUT
LOAD
R
F
R
W
DAC
AV = 1 + RF /RIN
R
V
F
FIGURE 3. NON-INVERTING VOLTAGE GAIN
RIN
DAC
V
V = IR
R
I
F
F
FIGURE 1. CURRENT TO VOLT CONVERSION
Programmable Power Supplies
MAY 2009
APEX AN07UREVD
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PROGRAMMABLE ACTIVE LOADS
To obtain the V-I characteristics of a power source, it may
be desirable to control the output voltage and measure the
output current or visa versa. The current output circuits shown
are suitable as active current loads. The circuit of Figure 9
performs voltage loading of a solar cell panel. The power op
amp forces the DAC voltage to appear across the panel and
also performs an I to V conversion providing the data to plot
V-I characteristics.
Due to its fexibility, accuracy and ease of use, the power op
amp is the leading choice when programmable power supplies
are called for. They greatly simplify circuits requiring unipolar
outputs and are very cost effective when designing bipolar
power supplies. The only remaining question is whether to buy
the power op amp or to make one in discrete form. For low
quantity production runs, the required design effort renders the
make option too expensive. For high volume runs, the question
is more involved. In many applications, the smaller size and
lower weight plus high reliability, make the buy decision the
only reasonable choice. (See The Advantages of IC power op
amps.") In all applications, the hybrid power op amp enhances
design quality, speeds assembly and reduces overhead costs.
in each line would produce a 0.5V IR drop. Without remote
sensing, this would become an error at the load. With the
addition of the second ratio matched R
F
/R
IN
pair and two low
current sense wires, IR drops in the power return line become
common mode voltages for which the op amp has a very high
rejection ratio. Voltage drops in the output and power return
wires are inside the feedback loop; therefore, as long as the
power op amp has the voltage drive capability to overcome
the IR losses, accuracy remains high.
CURRENT OUTPUT VERSIONS
A current output PPS using a current output DAC can be
implemented as shown in Figure 5. Another version of the cur-
rent output PPS is shown in Figure 6. This allows the load to
be grounded, but is more complex and has additional errors.
Especially if the output currents are relatively low, the current
through the lower R
F
/R
IN
pair may become signifcant because
it is also sensed by R
S
. Major errors can be caused by ratio
mismatching between the R
F
/R
IN
pairs. The resulting voltage
errors across the sense resistor equal the output voltage times
the ratio mismatch. For example, consider a 0.2 sense resistor,
a 5A output requiring a 20V drive and a ratio mismatch of only
0.1% causes an error of 2%. Even an 8-bit LSB is only 0.39%!
In all of the current output circuits discussed, errors due
to voltage offset appear across the sense resistor at a gain
of one or more. This means higher sense resistor values will
minimize output current errors at the expense of increased
power dissipation in R
S
, the power op amp and system power
supplies. One other word of caution, if the load contains induc-
tive elements, refer to Applications Note 5 which discusses
maintaining stability in precision current output circuits having
reactive loads such as defection coils. A current output PPS
using a voltage output DAC is shown in Figure 7. The power
op amp drives current through the load until voltage on the
sense resistor (R
S
) equals the input voltage. To achieve high
efficiency (low voltage across R
S
compared to the load volt-
age), this circuit requires a low voltage DAC or a high voltage
op amp. If neither is possible, the circuit of Figure 8 allows the
sense resistor voltage drop to be lower than the input voltage.
DAC
R
1mA
F
FIGURE 5. A CURRENT-IN, CURRENT-OUT
R
S
POWER
OP AMP
LOAD
I =
OUT
I
*
R
R
IN
S
F
DAC
R
F
FIGURE 6. CURRENT-OUT FOR A GROUNDED LOAD
R
IN
I =
OUT
R
IN
POWER
OP AMP
LOAD R
F
R
S
V
*

R
F IN
R
*

R
S IN
V
DAC
V
FIGURE 7. A HIGH VOLTAGE CURRENT-OUT
PROGRAMMABLE SUPPLY
R
S
POWER
OP AMP
LOAD
I = V /R
IN S
DAC
R
V
F
FIGURE 8. A HIGH CURRENT, CURRENT-OUT
R
S
POWER
OP AMP
LOAD
I =
OUT
V
*
R
R
*
R
IN
IN
F
S
R
IN
DAC
V
FIGURE 9. SOLAR PANEL TESTER
POWER
OP AMP
V
OUT
= (I
IN

*

R
F
) +V
IN
SOLAR
PANEL
R
F
I
IN
FULL SCALE RANGE
BITS PPM 2mA 20V 50V 200V
8 3906 7.8A 78mV 195mV .78V
10 977 1.95A 19.5mV 48.8mV 195mV
12 244 488nA 4.88mV 12.2mV 48.8mV
14 61 122nA 1.22mV 3.05mV 12.2mV
16 15.3 30.5nA 305V .763mV 3.05mV
TABLE 1. LSB VALUES FOR VARIOUS OUTPUT LEVELS
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Output Power
OPTIMIZING THE POWER SUPPLY
To deliver the most output power and achieve maximum
efficiency, internal power dissipation must be minimized. This
condition is met if the power supply voltage is selected for the
minimum voltage necessary to produce the required output.
Internal power dissipation is the sum of quiescent power plus
the product of output current and the supply to output differential.
Supply voltage is the only variable for the designer to optimize.
Refer to the product data sheets specifed minimum supply to
output differential voltage. Each extra volt here dissipates one
more watt for every ampere of output current. Trade-offs in this
area are not recommended. Deriving required outputs from
existing system supplies reduces efficiency if the difference
between supply and required output exceeds the supply to
output differential of the op amp. Also, this supply vs. efficiency
trade-off must be considered when contemplating the use of
unregulated supplies. When using unregulated supplies, line
and load variations must be taken into consideration along with
the ripple content of the supply. The result is a voltage band
above the minimum operating voltage required by the power op
amp to produce the required output. Power in this band must
be dissipated. Voltage above the minimum operating voltage
decreases the power handling capability of the power op amp.
The choice is whether to dissipate the power in the power
op amp or in a separate regulator. As current levels increase,
the dollar per watt cost generally rises faster for the power op
amp than it does for a DC regulator.
Usually, unregulated supplies are not economical because
they lack transient protection. Power lines are notorious for
being extremely noisy. They have high voltage, high speed
spikes riding on the sine wave which pass right through the
power transformer. Furthermore, the large electrolytic capaci-
tors used for fltering often do not have low equivalent series
resistances at those high frequencies. A 1K volt spike on the
incoming line can result in an excessive voltage spike at the
amplifer supply pin. Destruction of the op amp may be the
result. Therefore, line flters and zener clamps are required to
eliminate the voltage spikes; thus, the economy of unregulated
supplies is reduced.
Once the minimum supply voltages above have been
selected, steps need to be taken to minimize IR losses.
Some of today's modern hybrid power op amps handle cur-
rents higher than most branch circuits in residential wiring.
Losses can be kept to a minimum, especially as frequencies
increase, if leads are as short as possible between supply
and amplifer, as well as between the amplifer and the load.
In the video frequency range, where even a few inches of wire
have signifcant inductance, and the skin effect increases the
resistance of heavy wires at high frequency, multi-strand litz
wire is recommended.
SINGLE OR ASYMMETRIC SUPPLY OPERATION
Asymmetric output swings present another opportunity to
optimize power supplies. Consider the circuit of Figure 1. If
the symmetric power supplies were used, power dissipation
would be substantially increased, a power op amp with a
higher voltage rating would be necessary and output power
would be reduced.
THE MODERN POWER OP AMP
Power op amps are attractive because they reduce circuit
design time enormously. Assembly costs of the power op amp
design amount to a fraction of the discrete counterpart due
to vastly reduced parts count. Careful attention to the power
aspects of a circuit is required, as the well known op amp
design rules based on low power devices. The objectives are
to maximize reliability plus optimize output power and system
efficiency. This application note points out some optimizing
techniques and some areas to be especially watchful.

INTERPRETING SPECIFICATIONS
The frst step in achieving high power levels is to operate
within specifcations. This means check the data sheet frst.
Apex Precision Power data sheets are divided into product
description, absolute maximum ratings, specifcation table,
typical performance graphs, and application hints. Each sec-
tion should be checked for relevant information.
Absolute maximum ratings are stress levels which, when
applied to the amplifer one at a time, will not cause permanent
damage. However, proper operation is only guaranteed over
the ranges listed in the specifcations table. For example, most
amplifers have an absolute maximum case temperature range
of 55C to 125C. If the specifed operating temperature range
is less, i.e. 25C to 85C, an amplifer may latch to one of its
supply rails when operating above that temperature (+85C).
However, the device will not sustain permanent damage unless
the latched condition also violates the safe operating area.
Simultaneous application of two or more of these maximum
stress levels, such as maximum power and temperature, may
induce permanent damage to the amplifer.
The generally accepted industry method of specifying abso-
lute maximum power dissipation assumes the case temperature
is held at 25C and the junctions are operating at the absolute
maximum rating. This standardization provides a yardstick to
compare ratings of various manufacturers. However, it is not
a reliable operating point. An ideal heatsink is required, and
even with the best heatsink, it would still result in reduced
product life due to operation at extreme temperatures. Apex
Precision Power recommends maximum junction temperature
of 150 or less.
The specifcations table should be the prime working
document while designing the application. In addition to the
minimum/maximum parameters (voltage offset, output capabil-
ity, etc.), this table contains the guaranteed linear operating
ranges: common mode voltage, temperature ranges, power
supplies, etc.
Typical performance graphs are most useful in determining
performance variation as operating conditions change. For
example, all amplifers are specifed for a minimum voltage
output at maximum current rating. If your application needs
only 75% of this current, you might determine from the typical
graph you will gain 0.5V at this level. A safe design will assume
output capability of 0.5V better than the specifcation table,
not the actual number on the typical graph. Bear in mind, if
your design is based on the typical performance graphs, it will
statistically work 50% of the time.
Optimizing Output Power
MAY 2009
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temperature controller in Figure 3.
Programmable power supplies (PPS) for automated test
equipment must often tolerate short circuits in the device under
test. For the PPS shown in Figure 4, the worst case dissipation
will occur with a short to one of the 24V DUT supplies if the
PPS is programmed to the opposite voltage. Assuming the
current limit of the 24V supply is greater than the PPS limit,
the PPS goes into current limit with considerably higher power
levels than encountered under normal operation. Worst case for
the amplifer could be its supply voltage plus the DUT supply
voltage times the current limit.
AC OUTPUTS ALLOW HIGH POWER LEVELS
If an AC drive has a frequency of 60Hz or greater, the half-
wave period of the power dissipating waveform is shorter than
the thermal time constant of the power amplifer. The resultant
power averaging between the output transistors results in a lower
thermal resistance. This lower thermal resistance immediately
increases the power handling capability of a given amplifer.
Apex Precision Power data sheets provide both AC and DC
ratings of thermal resistance. Power levels specifed on both
the absolute maximum rating and the power derating typical
performance graphs are based on DC thermal resistance. This
means an AC only application is capable of delivering more
power or running cooler (more reliably).
Sine wave circuits share a similarity with DC circuits. Maxi-
mum internal RMS power dissipation occurs when the peak
output voltage swings to 63.7% of supply voltage. Maximum
internal power may be calculated as follows:
5V
1K
+40V
7.2K
1.3
+24V
24V
D.U.T.
40V
1.3
I = .5A
*
64V = 32W
CL
FIGURE 4. PPS POWER DISSIPATION CONSIDERATIONS
PA10
Fortunately, most power op amps are suitable for operation
from a single supply voltage. The common mode operating
requirements do, however, impose the limitation that the input
voltages not approach closer than 5 to 10 volts to either supply
rail (determined by the common mode voltage specifcation).
Thus, single supply operation requires the input signals to be
biased 5 to 10V from either supply rail. Figure 2A illustrates
one bias technique to achieve this.
Figure 2A illustrates a very practical alternative to single
supply operation, a second low voltage supply. This allows
ground referenced input signals, but also maximizes the volt-
age swing of the unipolar output. The 12 volt supply in Figure
2B must usually supply only the quiescent current of the power
op amp unless the load is reactive or EMF producing.
KNOW YOUR POWER DISSIPATION
Power requirements of the load are most often well known,
but calculating the power dissipated inside the amplifer is not
always simple.
For purely resistive loads, maximum internal power dissipation
occurs when the output voltage equals half the supply voltage.
This is the worst case to analyze if the amplifer does not have
to withstand short circuits. An example of DC application is the
REF
TEMP.
SET
POINT
+36V
5V
TEMP.
SENSOR
PA73
.2
.2
10
MAX INTERNAL POWER MAX OUTPUT POWER
1/2 V = 18V V = 28V
I = 1.8A I = 2.8A
P = 32.4W P = 78.4W
P = 32.4W P = 22.4W
FIGURE 3. TEMPERATURE CONTROL CIRCUIT POWER LEVEL
OUT
OUT OUT
S
OUT
INT INT
OUT
+210V
50K
50K
2.5K
2.5/10V
2.5K
50K
50K
+210V
+50/+200V
PA82J
FIGURE 2A. TRUE SINGLE SUPPLY OPERATION
D/A
+210V
130V
+12V
50K
2K
PA81J
0/125V
0/5V
FIGURE 2B. ASYMMETRIC SUPPLIES
D/A
YOKE DRIVER: V =
L I
t
R
.15
CL+
R
.15
CL
R
2K
D 6.5mH
3
1.8AP-P
S R
.5
F
R
1K
.1F 47F
7V
+26V
47F .1F
.9VP-P
6
2
1
8
7
5
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P = V
SS
2
/(2
2
* R
L
)
Where: V
SS
= total rail-to-rail supply voltage
R
L
= load resistance
REACTIVE LOADS INCREASE DISSIPATION
When driving reactive loads, more caution is required due
to the phase difference between V
O
and I
O
. The actual power
dissipation may be several times higher than the equivalent
resistive loads. In such cases, It is best to use a totally different,
but equally simple, approach to calculate power dissipation (P):
P = P
1
P
O

Where: P
1
= Power drawn from the power supply
P
O
= Real power delivered to the load
In calculating P1, use DC supply voltage and AVERAGE
output current (RMS
*
.9003 [.9003 = AVG/RMS or 2/ 0.5]).
For example, a 1A RMS output, with supplies of 15V, means
.9003
*
1
*
15 = 13.5W plus quiescent current
*
30V.
Driving purely reactive loads means that all power drawn
from the supplies is dissipated in the amplifer because the
load power factor is reduced to zero.
DEALING WITH MOTOR DRIVES
Motor control applications often place brutal requirements
on the driving circuit. Section A of Figure 5 shows two output
transistors of a power amplifer and the motor with its ratings.
It is important to recognize that the winding resistance and
the voltage rating of the motor alone do not determine the
running current. The back EMF of the motor must also be
considered when calculating the running current. This EMF
can be modeled as a battery whose voltage is proportional
to instantaneous velocity as shown in Section B of Figure 5.
When the amplifer is given a reversal command, it changes
its output very quickly while the actual speed and EMF can
diminish only as fast as mechanical system inertia is dissi-
pated. The initial result of the vastly different response times
between the electronics and the mechanics is shown in
Section C of Figure 5. The amplifer has responded to its new
drive command, but the EMF has not yet had time to change.
The model shows that if the amplifer could produce the
programmed output level of 24V, a total of 36V would be
applied across the winding resistance developing a current on
9A. In this situation, the output voltage is determined by the
current limit of the amplifer rather than the control voltage.
The programmed limit of 4A through the winding resistance
produces 16V. Adding the initial 12V EMF places the ampli-
fer output voltage at -4V. With 24V across the conducting
transistor, the internal power dissipation is eight times the level
encountered in steady state operation. Failure to analyze this
situation has taken the lives of many power op amps.
A useful technique to maximize available power for steady
state running requirements is to limit the rate of change of the
drive voltage to approximately the same limitation imposed
by the inertia of the mechanical system. In this manner, the
extremely high power levels described can be avoided. In
other words, fast reversal times can be traded off for high
levels of running torque.
CIRCUIT DESIGNS TO INCREASE OUTPUT POWER
Two power op amps confgured in a bridge circuit can double
power levels. To illustrate the advantages of the bridge circuit,
Figure 6 shows a composite where alternate connections
transform the circuit from single ended to a bridge. A1 is a
standard single ended power op amp which would drive the
4 ohm speaker. If A2 is added, it completes a bridge circuit.
The resulting doubling of the voltage drive would be suitable
for an 8 ohm speaker. With this trick, not only are power levels
doubled, but the same supply is capable of powering either
circuit. This is possible because the single ended circuit peak
current demand utilizes only 50% of the supply capability. In
contrast, the equal and opposite drive characteristics of the
bridge circuit loads both positive and negative supply rails
equally during each half cycle of the signal.
Parallel operation is often used to increase output current or
wattage. However, due to their low output impedance, power
op amps cannot be connected in parallel without modifying
the circuits. Figure 7 illustrates one method of doing this.
This uncommitted master amplifer, confgured as required to
satisfy the circuit function, has a small sense resistor inside
its feedback loop. The slave amplifer is a unity gain buffer.
Thus, the output voltages of the two amplifers are equal. If
the two sense resistors connected to the load are equal, the
amplifers share current equally. More slaves may be added
as desired.
18K 150K
150K
150K
+15V
15V
15V
+15V
.2
.2
8
36W RMS
4
18W
RMS
1nF
.16
.16
2.2K
1nF
2.2K
.47F
FIGURE 6. DOUBLING POWER WITH A BRIDGE
A2 A1
FIGURE 5. POWER DISSIPATION IN MOTOR DRIVES
24V @ 3A
R
W
= 4
EMF = 12V
+28V
28V Section A
Section B
Section C
I
OUT
I
LIM
28V
+28V
3A
*
4V = 12W 12V
+24V +12V
4V 16V
4
4
12V 4A
*
24V = 96W!
REVERSAL
STEADY STATE
AN08
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There are two factors to consider in the selection of the sense
resistors. First, the output current will produce a voltage drop
which adds to the supply requirements. Second, the voltage
offset of the slave appears across the sum of the two sense
resistors. Thus, a small current will circulate strictly between
the two amplifers. This wastes power. When this technique
is used, it is recommended that inputs be limited in such a
way that they demand only 50% of the typical slew rate of the
amplifer. This prevents two amplifers with different slew rates
from generating large currents between each other during
fast transitions.
PROPER HEATSINKS INCREASE OUTPUT POWER
With a given power op amp, the larger the heatsink is, the
higher attainable output power can be. Furthermore, as power
levels increase, it is more cost effective to use a larger heatsink.
To minimize space and weight, forced air cooling or even
liquid cooling is often used with power amplifers. While obvi-
ously easier to implement, forced air cooling gives a maximum
improvement of only about 2:1. At higher power levels, liquid
FIGURE 7. PARALLEL OPERATION
R1
R
R
MASTER
SLAVE
I LOSS = V /R
S
V LOSS = I
*
R
OS
OUT
S
S
F
R
S
cooling becomes a more attractive option. Reasonable heatsink
ratings, which can be achieved given an area 6 inches square
and 2 inches tall, are 0.85C per watt for free air cooling, 0.4C
per watt for forced air, and 0.05C per watt for a liquid cooled
system. See the Apex Precision Power application note on
heatsinking for more information.
THERMAL SHUTDOWN CAN HELP
Internal thermal protection can increase output power under
nominal operating conditions because the amplifer shuts off
when the substrate temperature exceeds safe limits. This allows
the amplifer circuit design to be based solely on normal condi-
tions but prevents excessive temperature during abnormally
high power conditions.
The thermal shutdown feature is especially valuable in
circuits such as programmable power supplies (PPS). Here
the output voltage is the normal operating voltage of the unit
under test. Occasionally the unit under test will be defective
which may short the output of the PPS to ground; thus, power
levels increase substantially. Thermal shutdown will simply
shut the device off rather than lead to destruction. Thermal
shutdown is not a panacea for all problems. It does not mean to
disregard the second breakdown curves of the safe operating
area. Assume the time constant for operation of the thermal
shutdown is 250-500ms. This means the worst case power
levels should not exceed the steady state second breakdown
line of the SOA curve.
OPTIMIZING IS A TEAM EFFORT
Apex Precision Power power op amps employ unique thermis-
tor circuits that provide superior control of internal currents and
offer exceptional specifcations plus a superb quality record.
With careful attention to design of the application, the end result
will be advanced products of greater value.

IMPORTANT NOTICE
AN09
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AN09 Current
Limiting
INTRODUCTION
Power op amp circuits without suitable current limiting can
be compared to putting a gun in the hands of a child you may
get away with it but disaster is waiting to strike. While elaborate
circuits have been used, most power op amps use a simple and
cost effective circuit which still requires engineering homework
to be safe. The objective is delivering desired power to the
load without violating the SOA.
BASIC CURRENT LIMITING
Current limiting circuits in power op amps are local to only
the output stage so they can very quickly (sub microsecond)
reduce output current to a predetermined level. There are at
least four reasons to incorporate such a limit:
1. The output transistors of the amplifers are almost always
capable of delivering more current than the ABSOLUTE
MAXIMUM RATING of the amplifer. Exceeding this limit
can destroy metal, usually a wire bond to the supply or
the output pin fuses. A common mistake is to rely on the
power supply current limit for this protection. Do NOT fall
into this trap. Filter capacitors (both inside the supply and
local to the op amp) often store plenty of energy to vapor-
ize a wire bond.
2. Loads with variable impedance may need protection against
possible fault conditions. A mechanical jam on a motor drive
is a good example.
3. Current limit can prevent overloading power supplies. This
may be critical if other circuits share the same supply.
4. Observing the Safe Operating Area (SOA) of the power
amplifer keeps junction temperatures to a reasonable level.
Output current is one term of the power equation.
A fxed current limit is usually adequate for the frst three
reasons. A simple and cost effective approach to current limit-
ing is shown in Figure 1. Current through the output transistor
Q1 is converted to a voltage by the sense resistor Rcl. When
this voltage exceeds the Vbe of the current limit transistor Q2,
drive current from the preceding stage is diverted to the output
to shut down Q1. In addition to being an amplifer, Q2 serves
as an imperfect voltage reference for the current limit set point.
At room temperature the typical value is around 0.65V. Rb
along with the capacitance of Q2 slow the circuit just enough
to prevent oscillation. In equation form:
Icl = 0.65/Rcl (1)
or
Rcl = 0.65/Icl (2)
where Icl is the current limit in amperes and Rcl is the cur-
rent limit resistor in ohms.
The fourth reason is more complex. Figures 2 and 3 illustrate
the challenge of meeting SOA limitations with fxed current limit.
First, note that the X axis labeling of the PA10 SOA graph is
NOT output voltage but the stress voltage across the conduct-
ing transistor. Assume DC signals and a case temperature of
25C for the following. The resistive load implies stress voltage
is limited to single supply voltage and that maximum heat in
the output transistor occurs at an output of 50% of supply. At
25V the SOA graph tells us maximum current is 2.7A. This
implies a minimum load of about 9.3 ohms will limit current
to safe levels at any output voltage. Maximum current will be
4.75A (44V/9.3 ohms) and maximum output power will be
209W. Note: The voltage swing specifcation of the PA10A is
Vs-6V at 5A. However, if the application must survive a shorted
component or cable on the output, the stress voltage jumps to
50 and maximum safe current is only 1.05A. Once this current
limit is set output power is limited to 46W peak into 44 ohms.
For energy storing loads, assume an initial voltage of nearly
-50V and a positive going signal. Initial supply to output stress
is nearly 100V and maximum safe current is less than .3A.
CURRENT LIMIT IS A MOVING TARGET
The largest variable of the current limit circuit is the tem-
perature coefficient of the imperfect reference voltage, the Vbe
of Q2. It decreases approximately 2.2mV for each degree C
Q2
Q1
Rb
Rcl
280
+VS
FIGURE 1. CLASSIC CURRENT LIMIT CIRCUIT
V
O
5.0
3.0
2.0
1.5
1.0
.7
.5
.3
.2
10 15 20 25 30 35 40 50 60 70 80 100
S
V
O
(V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S

(
A
)
S
E
C
O
N
D

B
R
E
A
K
D
O
W
N
T
C =
2
5
C
T
C =
8
5
C
T
C =
1
2
5
C
T
H
E
R
M
A
L
steady state
t

=

0
.
5
m
s
t

=

1
m
s
t

=

5
m
s
FIGURE 2. SOA GRAPH OF PA10
PA10A
50V
+ 50V
FIGURE 3. DIFFICULT LOADS OR POSSIBLE FAULT CONDITIONS
Current Limiting
MAY 2009
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increase in case temperature. Thus the 0.65 term ranges from
0.826 at -55C to 0.43 at 125C. From an steady state power
dissipation point of view, this slope is in the right direction but
it is still possible to get in trouble. Comparing this slope to our
initial reasons to limit current:
1. The reason does not vary with temperature.
2. The reason is load dependent.
3. The reason is supply dependent.
4. The reason does not vary with temperature.
It is best to plot the limit on the SOA graph and compare
to other requirements of the system. To this end, visit the
Apex Precision Power web site at www.Cirrus.com or contact
Apex Precision Power applications engineering for software
to automate the task.
Looking again at Figure 1, we can fnd several reasons actual
current limit varies from the equations presented. When in the
limiting mode, Q2 is shunting drive stage current away from
Q1 directly to the output. This means actual current limit can
not be less than drive stage capability. Some data sheets give
a minimum practical current limit. Operation in this region
is unusual because drive stage current is so much less than
output capability that being in this region implies amplifer
capability is likely an overkill for the application.
Now consider that when Q2 is conducting there will be
base current fowing through Rb which effectively increases
the reference voltage. On some amplifers this effect is large
enough that the specifc data sheet will give a unique value
greater than 0.65 to use in the equations.
Although it is not immediately obvious looking at fgure 1,
resistance of internal wire bonds, solder joints, wiring traces
and the leads of Rcl all add to the rated value of Rcl unless
pins are provided to implement four wire current sensing. In
high current applications, measurements of prototype circuits
may be the best way to fnalize the design.
We now have a very wide range of "safe" currents depending
on loads or fault conditions which must be tolerated. We have
also seen that while simple and cost effective, these limiting
circuits are not reference standards; think in the area of +/-20%.
The sad part is that the fxed current limit set to protect for
worst case fault condition also limits current for the non-fault
condition. It is also interesting to note that we assumed an
unrealistic heatsink and safe currents are still only a fraction
of the absolute maximum for the amplifer. This shows the
importance of both heatsinking and current limiting. An ideal
solution for SOA protection might be the addition of a stress
voltage sensor and multiplier for each output transistor such
that limiting could be based on watts. If all this circuitry is fast
enough, SOA concerns would be no more. This approach is
quite rare because the cost measured in components, design
time and space is almost always more than that of using a
larger amplifer. Clearly, an affordable improvement in current
limit technique is called for.
FOLDOVER CURRENT LIMIT BASICS
Apex Precision Power models PA04, PA05, PA10 and PA12
can take advantage of foldover current limiting. Adding only
one resistor to the classic current limiting circuit (Figure 4)
provides dynamic response to output voltage swing. Realizing
that Rcl is typically three orders of magnitude below Rb, it is
reasonable to ignore Rcl and say Rb and Rfo form a voltage
divider between ground and the output voltage. With Rfo
typically being a couple orders of magnitude larger than Rb,
the divider adds a very small portion of the output voltage in
series with the base of Q2. With a 0V output, current limit will
be the same as the classic circuit. However, as the output goes
positive, the addition of the divider voltage effectively increases
the reference voltage (Vbe of Q2) allowing more current to fow.
For negative output voltages (Q1 is still conducting), the very
small fraction of the negative output added reduces current
fow. Another way to view this would be state we have added
a term to the current limit equation based on output voltage
but modifying current limit in an inversely proportional manner
to voltage stress on the conducting transistor. While this is still
a long way from the ideal of a multiplier calculating watts, and
it does nothing in the case of variable supplies, it does add a
desirable slope to the current limit function. In equation form:
where Vo is output voltage in volts and resistors are from
Figure 4 and in ohms.
Looking again at the case of the resistive load driver which
must tolerate a short on the output, let us further assume the
objective is to drive 22 ohms to 88W peak (44Wrms, 44V pk
and 2A pk). Start with an Rb of 280 ohms and Rfo of 20Kohms
and use Equation 4 to calculate Rcl = 0.629 ohms for peak
current at peak voltage. Use a 0.62 ohm resistor. Equation 1
now shows us current during the short fault condition is limited
to 1.05A. Plotting the current limit on the SOA graph as shown
in Figure 5 reveals that this current limit is safe for any output
voltage from zero to supply. Using foldover instead of fxed
current limit has nearly doubled the power delivery capability.
In the case of the energy storing load, Equation 3 shows us
this foldover circuit current limit crosses zero and turns negative
within the swing capability of the amplifer at all temperatures
above 25C. This can cause amplifer latch-up and MUST be
avoided. A lower supply voltage or a larger foldover resistor
will solve this problem.
Even though we know the current limit is safe for a short to
ground and for the full 100V stress level, Figure 5 shows that
at 25C and colder allowable current crosses above the SOA
line in between these points. Increasing Rcl will lower current
limit at all output voltages and solve this problem.
) (
Rb
R
FO
+ R
B
0.65 + V
O

R
CL
I
CL
= (3)
) (
Rb
R
FO
+ R
B
0.65 + V
O

I
CL
R
CL
= (4)
R
FO
R
CL
V
O
R1
Q1
Q2
+V
S
FIGURE 4. BASIC FOLDOVER CURRENT LIMIT CIRCUIT
280
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more complex than the previous example:
where Icl is in amperes, Vo is in volts Rcl is in ohms and Rfo
is the PA10 or PA12 external foldover resistor and is in Kohms.
Foldover connections for the PA04 or PA05 are shown in
Figure 6. Use 270 ohms for Rb and use equations 3 and 4.
Beware that even momentary shorts directly at pin 10 can
destroy the amplifer now that pin 10 is isolated from the output
by the 270 ohms.
CONCLUSION
Current limit is to the power op amp as survival instinct is to
an animal; a REALLY good thing to have. While basic current
limiting is simple, adding temperature variations and circuit
options such as foldover make the job of checking all the
points of possible danger quite a chore. First comes the math,
then data plotting on the SOA graph with those log scales we
all love so well. This drudgery has become history with the
spreadsheet automation. Get your copy from the Apex Preci-
sion Power web site at www.Cirrus.com or call Apex Precision
Power applications.
TWO TYPES OF FOLDOVER
The PA10 and PA12 have an internal Rb of 280 ohms and
internal Rfo of 20K for both the positive and negative current
limit transistors. The two 20K resistors tie together at pin 7 where
the user may ground the pin for maximum foldover slope or
add an additional resistor in series from pin 7 to ground for less
foldover action. Since both 280 ohm resistors tie essentially to
Vo and the two series networks of 0.28K + 20K are essentially
in parallel, the equations specifc to the PA10 and PA12 are
PA04/05
Rcl
Rb
Rfo
Vo
10
7
11
FIGURE 6. FOLDOVER CIRCUIT FOR PA04 OR PA05
)

( (
10.14

10.14 + R
FO
)

.28

20.28
0.65 + V
O

R
CL
)

( (
10.14
10.14 + R
FO
)

.28
20.28
0.65 + V
O

I
CL
I
CL
= (5)
R
CL
= (6)
25C
55C
SOA
125C
85C
10.000
1.000
0.100
15.8 25.1 39.8 63.1 100
C
U
R
R
E
N
T

L
I
M
I
T
,

A
S
V
O
(V)
FIGURE 5. FOLDOVER ILIMIT VS. VOUT
IMPORTANT NOTICE
AN10
716 AN10U
AN10 Power Amp
Output Impedance
and unloaded conditions. This method measures the dynamic
impedance in series with a perfect voltage source. Variations
in output with loading are due to this impedance.
A more direct method is to generate a signal which is im-
pressed into the output of an amplifer operating under open
loop conditions. A measurement of current will determine the
effective impedance that this signal is looking into.
ACTUAL IMPEDANCE VALUES
Several Apex Precision Power power amplifers were mea-
sured using the gain variation with loading method. The test
circuit of Figure 2 was loaded with 10 ohms. To establish unifor-
mity of measurement, the smallest possible amplitude at 10Hz
was used. Where a range of values is shown, it represents a
range observed for several devices.
PA02: 10-15 ohms
PA07: 1.5-3 ohms
PA08: 1500-1900 ohms (high voltage amplifer)
PA09: 15-19 ohms
PA10: 2.5-8 ohms
PA12: 2.5-8 ohms
PA19: 30-40 ohms
PA51: 1.5-8 ohms
PA61: 1.5-8 ohms
PA84: 1400-1800 ohms (high voltage amplifer)
The high voltage amplifers are much lower in current capa-
bility than the high current amplifers. As a result, the higher
impedance is to be expected.
The high impedance shown for PA19 is a result of the drain
output MOSFET circuit without local feedback at the output
stage. This is an example of how this parameter can be mis-
leading. If 30 to 40 ohms of resistance were in series with
the output, then the PA19 would never be capable of greater
than 1 amp of output current. Under closed loop conditions,
the output impedance is reduced to milliohm levels like any
other power amplifer. Keep in mind the output impedance is
an abstract term as far as output voltage and current capabil-
ity are concerned.
To demonstrate the effect of output impedance when model-
ing, use the highest and lowest expected values. The results
will verify that output impedance plays an insignifcant role in
power amp performance.
INTRODUCTION
In the design of power amp circuits, the need often arises
for a power amp model with specifed output impedance. Most
often, this requirement revolves around the need to accurately
predict the phase performance of power amp circuits.
Output impedance of any op amp is modifed by the feed-
back network present around the device. In voltage source
type circuits, the effect of the network is to reduce the output
impedance by a factor equal to the ratio of open loop gain to
closed loop gain. In power amps, the net result is an effective
output impedance of milliohm levels at frequencies below 1kHz.
Wiring and interconnections often create larger impedances
than the output impedance of the closed loop power amp.
Therefore, output impedance will play a minor role in the phase
performance at low frequencies. At high frequencies, reactive
load considerations are already addressed by capacitive load
specifcations given on many power amplifers.
Current control circuits, or current sources, include the load
as a series element in the feedback loop with a sense resistor
developing a voltage proportional to load current. Figure 1
shows a generalized example of just such a circuit. The load
often consists of an inductive element such as a defection
yoke which can have up to 90 of phase shift at higher frequen-
cies. Totally accurate prediction of phase in the feedback loop
might at frst seem to involve the series equivalent of output
impedance and yoke impedance. In reality, its because the
feedback the op amp is operating as a true current source
with an impedance approaching infnity. A realistic approach
to stabilizing the circuit merely involves an auxiliary feedback
whose effect dominates before the combination of yoke feed-
back and amplifer phase approaches 180. Output impedance
is not necessary to determine stability.
It is also important to realize that output impedance of a power
op amp is not related in any way to power delivery capability
or internal losses. A model of a power amp with the output
resistance in series with the output will develop inordinate
losses which are not observed in real world op amps.
Output impedance is dependent on several variables such
as frequency, loading and output level. Often, the impedance
will rise at higher frequencies. A class C amplifer, such as
PA51 or PA61, will exhibit higher impedances at lower levels
due to bulk emitter resistance effects in the emitter follower
outputs.
OUTPUT IMPEDANCE MEASUREMENT
Several methods are available to measure output impedance.
The simplest method is to measure open loop gain in loaded
V
R
S
C
FIGURE 1. GENERALIZED CURRENT CONTROL CIRCUIT
LOAD
FIGURE 2. OUTPUT IMPEDANCE MEASUREMENT CIRCUIT
562
56.2K
V
V
IN
OUT
A =
V
OUT
V
IN
O
10
10
R
L
A = IS UNLOADED
O
R
L
R = ( 1)
O
A
O
A'
O
A' = IS 10 LOADED
O
Power Amp Output Impedance
MAY 2009
APEX AN10UREVC
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AN11 Thermal
Techniques
THERMAL MANAGEMENT
As power op amps shrink in size and become more powerful,
the importance of a good thermal design is more critical than
ever. Most importantly, reliability is a direct function of internal
component temperatures and dissipated power. Furthermore,
as the amplifer case rises above 25C, derating factors do
not just reduce the allowable power level. Voltage and current
offsets drift, current limits change and, sometimes even dy-
namic performance is affected. This application note discusses
thermal management starting with actual dissipation vs. allow-
able dissipation, the common cooling options, how to achieve
maximum performance with sound mounting techniques, as
well as the benefts of thermal capacity.
Thermal management techniques must be applied to remove
as much heat as possible from the semiconductor junction,
thereby maintaining minimum operating temperatures and
maximum reliability. A further goal is to minimize the effects of
the removed heat on other devices. Figure 1 shows the aver-
age of bipolar and MOSFET power transistor failure rates at
elevated temperatures relative to operation at 25C. All elec-
tronic components encounter similar increased failure rates.
MAXIMUM POWER RATING
Your new home stereo system boasts 200W. Industrial
amplifer #1 claims 100W audio output. Industrial amplifer #2
claims 67W internal dissipation.
Your challenge is to determine which of these is the most
powerful. With a 115V input current rating of only 0.4A, we
can dismiss the stereo. Analysis of the industrial amplifers
requires we either fnd internal dissipation for amplifer #1 or
fnd maximum audio output for amplifer #2. Power Design is
the tool for this work once circuit details become known (load
impedance, supplies and a few other amplifer specifcations).
Figure 2 illustrates the general concept that there could be
almost a 2:1 ratio between output power and internal power
for AC signals and about 3:1 for DC signals (even assuming
a purely resistive load).
Pint Pout Vout Iout Tcase Tjunction
AC (rms) 59W 100W 20V 5A 85C 138C
DC (peak) 72W 200W 28.3V 7.07A 98C 200C
With internal dissipation of industrial amplifer #1 being
only 59W when delivering its maximum output of 100W, #2
is the power champion because at 100W output it still has
8W reserve as far as internal dissipation is concerned. The
second concept to note in Figure 2 is that DC signals result in
higher temperatures than AC signals. This is because with AC
signals, each power transistor has a half cycle to cool while
the opposite polarity transistor does the work. The bottom
line on power ratings: All of the four wattage numbers above
accurately describe the circuit, but the actual number can vary
better than 3:1, depending on defnitions.
JC
is the thermal resistance from junction to case. With
these ratings (one for DC and a more advantageous one for
AC) output power capability for any type circuit can be easily
determined. A great deal of effort has been put into minimizing
this thermal resistance. It is the major specifcation affecting
power handling capability. When allowing for a case tempera-
ture of 25C and maximum junction temperature, the maximum
internal dissipation rating is developed.
P
MAX
= (T
JMAX
25C) /
JC
(1)
This rating is consistent with rating methods of most transis-
tor manufacturers and should not be confused with advertised
output power which is highly application dependent. Before
using this rating, check for factors which might degrade the
rating such as actual ambient temperature (T
R
), heatsink
thermal resistance (
HS
) mounting, and in some cases, an
isolation washer.
P
MAX
= (T
JMAX
T
A
)/(
JC
+
HS
+
HSC
) (2)
Equation 2 gets back to the real world where a real heatsink
is used, the interface between amplifer and heatsink is not
prefect, ambient temperature may not be ideal, and reliability
requirements may not allow junction temperatures up to data
sheet maximums. Read the heatsink data sheet carefully.
There are multiple thermal ratings for heatsinks because they
vary with power level, sometimes with orientation and always
with fow rate (air or liquid). Thermal interface rating between
cases and heatsinks are built into Power Design and can be
found on the Apex Precision Power Accessories Information
data sheet.
WASHERS AND WASHERS
The most common is the thermal washer mounted between
the amplifer and the heatsink. Its prime objective is to en-
hance thermal conduction compared to a bare joint. This is
0
2
4
6
8
10
12
25 50 75 100 125 150 175
Junction Temperature, C
F
a
i
l
u
r
e

r
a
t
e
,

N
o
r
m
a
l
i
z
e
d
This data was extracted from
the base failure rate tables of
MIL-HDBK-217F, Notice 2,
revision of 28 February, 1995.
FIGURE 1. MTBF vs. Temperature.
4
+34V
-34V
HS=0.86C/W
Ta=25C
FIGURE 2. What Wattage Number Should be Applied to This Circuit?
Thermal Techniques
MAY 2009
APEX AN11UREVE
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718 AN11U
ally) #6 hardware. A spacer length of 0.25" plus a washer at
least 0.02" (almost all washers are thicker than this) will insure
amplifer components do not touch the PCB.
When DIP10 packages are mated with very small heatsinks
(about the same size as the amplifer and fns of 1" or less, the
method in Figure 6 may be used.
Generally, The BC series amplifers are used in systems
requiring large power delivery. As discussed in the previous
the washer which MUST NOT BE COMPRESSIBLE. Using
a compressible washer on a metal can type package VOIDS
THE WARRANTY. The most common of these washers is
an aluminum substrate with a thermal coating on each side.
Thermal performance of these washers is at least as good as
a joint with properly applied thermal grease. Advantages over
grease include removal of operator variables on performance
(too thick, too thin, missing coverage), and not being messy.
When electrical isolation is required, similar washers with a
Kapton substrate provide isolation at the expense of additional
thermal resistance on the order of 2x. These washers are not
reusable. When replacing an amplifer, the old coating residue
should be removed from the heatsink to avoid buildup and
possible amplifer damage.
The second washer type used in mounting power devices
is the compression washer used under the head or nut of the
mounting screw. These may be (in order of effectiveness) Bel-
leville washers, split lock washers or tooth lock washers. One
of these washers should be considered when the equipment
would be regularly subjected to temperatures where humans
would require protective clothing.
SYSTEM LAYOUT
Thermal management starts with determination of actual
dissipation and should result in a layout of an optimized ther-
mal system to convey the heat to the ambient environment.
In systems using natural convection, heat sources should be
separated as widely as possible. In contrast, systems using high
velocity air or liquid cooling perform optimally when localizing
these devices. Understanding convection and radiation may
help avoid layout related problems. Since convected heat rises,
it is best to place the heat sources near the top of the enclosure
and avoid having temperature sensitive circuits above or near
the heat sources. The hot air should fow in its natural vertical
direction using vertical board and fn orientation. Heatsinks
should be oriented so air can pass freely over all the fns.
MOUNTING THE AMPLIFIER
The design of the amplifer mounting must:
1. Provide the required thermal path from amplifer to ambi-
ent.
2. Maintain intimate contact between amplifer and heatsink
surfaces.
3. Maintain amplifer lead positions with respect to a PCB,
socket or wire.
Occasionally, an Apex Precision Power amplifer will not re-
quire a heatsink. If this appears to be the case, double check
the thermal calculations, and then proceed to use cage jacks,
socket or soldering leads directly on the pins to fnish the design.
Figure 3 shows common mounting layouts for metal can
type packages. While the PC board example shows the use
of cage jacks, this is drawing would also apply when soldering
the pins directly to the PCB. Note that in this example, either
the heatsink is supporting the PCB or the PCB is supporting
the heatsink. In this latter case, if the heatsink is more than
four square inches (in the same plane as the PCB), consider
the confguration in Figure 4 where heatsink mass places less
stress on the PCB in the immediate area of the amplifer when
subjected to shock or vibration.
Figure 5 shows the preferred mounting method for the DIP10
products. Number 4 hardware is frst used to mate the amplifer
to the fat surface of the heatsink. Do not forget the thin layer
of thermal grease spread evenly over this area. The heatsink/
amplifer assembly can now be mounted to the PCB with (usu-
Teflon Tubing
(2 Opposite Pins
Minimum)
Mating Socket
PC Board
Heatsink PC BOARD
MATING SOCKET
DIRECT WIRE
Teflon Tubing
(All Pins)
Cage Jacks
Power Op Amp
Package
Power Op Amp
Package
Power Op Amp
Package
Teflon Tubing
(All Pins)
Heatsink
Heatsink
Wire
FIGURE 3. Mounting Techniques (Cross Section Views)
FIGURE 4. Large Heatsinks Need More Support.
CUSTOMER
HEATSINK
CL (DIP10)
SPACER
& HDWR
CUSTOMER
PCB
NO. 4
HARDWARE
SUGGESTED MOUNTING METHOD
FIGURE 5. Preferred mounting for CL (DIP10) packages.
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section, large heatsinks may often necessary to keep the am-
plifer cool while delivering signifcant power. The mechanical
assembly of the printed circuit board, BC amplifer, and heatsink
deserves some discussion.
The heatsink should be the main structural element that sup-
ports the amplifer and the PCB. The BC pins and most circuit
card material are not strong enough to support a heatsink of
any signifcant size. Failures are likely to arise by doing so -
circuit traces may crack, pins may bend and lose contact with
sockets, and solder joints may weaken and lose effectiveness.
Figure 7 shows one acceptable arrangement where the PCB
and heatsink are supported by standoffs to some structural
element. The BC amplifer is attached to the heatsink with 2
screws. Cage jacks or solder connections may be used for the
electrical connection to the pins. Half-inch standoffs provide
stable support of the heatsink above the PCB.
Commercial heatsinks usually specify a surface fnish of 63
micro inches, fatness of 4mils/inch in the direction of extrusion
and 6mils/inch perpendicular to the direction of extrusion. This
is marginal but generally considered acceptable for packages
up to about 1 square inch. Apex Precision Power procures all
heatsinks with fatness specifed at 2mils/inch. This forces a
machining operation on the mounting surface, resulting in less
than 1mil/inch actual fatness. We recommend this approach
when specifying a heatsink, whether it is a normally an off the
shelf model, a custom designed heatsink or uses structural
members of equipment as a heatsink. Do not forget to require
deburring of all holes. When amplifer pins go through the
heatsink, specify a hole for each pin of the amplifer. A single
hole or cutout for all the pins will thermally isolate the amplifer
from the heatsink.
Aging of this thermal interface has proven to be no problem,
0.5 INCH
SPACER
PCB
MECHANICALLY STABLE FOUNDATION
FIGURE 7. Heatsink is not mechanically supported by the PCB or
the BC Amplifier.
as long as the mechanical assembly is not disturbed. If disas-
sembled, clean off grease or washer coating material from both
amplifer and the heatsink, reapply and reassemble.
THERMAL CAPACITY
The power levels that can be achieved in the pulse mode of
operation are elevated far above those of steady state opera-
tion. This is due to the thermal capacity of the heatsink. As
heat is frst applied, the rate at which the case temperature
increases can be compared to its electrical equivalent, the
voltage build up on a capacitor of a R-C network. Figure 8
displays this analogy.
Thermal capacity is the amount of heat needed to raise the
temperature of the given object 1C. The generally published
parameter for materials is specifc heat given in calories/gram,
so multiplying by grams yields calories. Multiplying this by
4.186 will convert to watt-seconds, again for a 1C change.
The thermal time constant (Tau) is the product of the thermal
capacity and the thermal resistance. This time constant defnes
the rate at which the material reaches thermal equilibrium.
The time required to achieve 95% of the fnal temperature is
three time constants.
To illustrate the principle, aluminum has a density of 2.7gr/
cm and a specifc heat of .22calorie/gram/C (times 4.186
= 0.921watt-seconds/gram/C). The Apex Precision Power
HS05 heatsink weighs 18.3 ounces (518.8grams) and has a
thermal resistance (free air) of 0.85C/W. Thermal capacity
of the heatsink is then 0.0921 515.8 or 478watt-seconds/C.
Finally, the time constant of the HS05 with a free air mounting
will be 478 0.85, or 406 seconds.
Adding a fan to the application reduces thermal resistance,
but thermal capacity remains constant, meaning the time
constant will be proportional the thermal resistance. Graphs
for the HS05 indicate 500 feet/minute linear air fow produces
a thermal resistance of 0.3C. The new time constant is 478
0.3, or 143 seconds.
If power is applied as a single pulse, the case temperature
follows the curve in Figure 4. The T in C for both heating
and cooling follow these equations :
T
HEAT
= W*
HS
(1-e
t/tau
) (3)
T
COOL
= T
HEAT
(e
t/tau
) (4)
The Figure 9 (next page) curve indicates that thermal capacity
plays a major role when the duty cycle is extremely low.
Figure 10 (next page) shows the initial response to application
of repetitive pulses. The pulse train is repetitive when the duty
cycle does not allow the circuit to return to its initial temperature
between pulses. The following procedure will predict operating
V
T V
R
t t
ELECTRICAL THERMAL
C C
I P
dQ = id
t
= C2V
I R = V
dq = C
d(T) = Pd
t
P = T
V T
FIGURE 8. Electrical and Thermal Models.
CUSTOMER
HEATSINK
DIP10
1/4"
SPACER
No. 4
HARDWARE
CUSTOMER
PCB
FIGURE 6. Mounting CL (DIP10) packages to very small heatsinks.
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720 AN11U
temperatures after the heatsink has reached equilibrium. Peak
power is multiplied by duty cycle to arrive at average power.
The average temperature of the case will be T
A
+ (P
AVERAGE

HS
). To determine the peak power, the pulse duration and
time constant are substituted into equation 3 above. Then 1/2
heating is added to average temperature to yield the maximum
case temperature. This case temperature should be used in
conjunction with the SOA curves to determine the maximum
power available from the device.
T
t
t t
ON OFF
Teq
FIGURE 9. Single Pulse Response.
T
Teq
t
ON
t
OFF
FIGURE 10. Repetitive Pulse Response.
CONCLUSION
Thermal management optimizes space, cost and size for your
power levels and temperature range. When properly applied,
it will get the heat out and keep your circuits cool; thereby,
maintaining the highest possible reliability and performance.
For easy calculations of this information see the spreadsheet
EE Friend at www.Cirrus.com.
IMPORTANT NOTICE
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AN13 Voltage to
Current Conversion
VOLTAGE TO CURRENT CONVERSION
Voltage controlled current sources (or VCCSs) can be useful
for applications such as active loads for use in component testing
or torque control for motors. Torque control is simplifed since
torque is a direct function of current in a motor. Current drive
in servo loops reduces the phase lag due to motor inductance
and simplifes stabilizing of the loop.
VCCSs using power op amps will assume one of two
basic forms, depending on whether or not the load needs to
be grounded.
CURRENT SOURCE: FLOATING LOAD
Figure 1A illustrates the basic circuit of a VCCS for a foat-
ing load. The load is actually in the feedback path. R
S
is a
current sense resistor that develops a voltage proportional to
load current.
Note the inclusion of resistor R
B
in Figure 1A and subsequent
fgures where non-inverting VCCSs are described. This resis-
tor is present to prevent the non-inverting input from foating
when the input voltage source is disconnected or goes to high
impedance during the power on cycle. R
B
provides a path for
input bias current of the amplifer and commands the amplifer
output current to zero in cases where V
IN
is disconnected or
goes to a high impedance. Figure 1B shows an implementation
of a VCCS for a foating load. At low frequencies the added
components Cf, Rd, and R
F
have no effect and are included
only to insure stability. Considerations for these components
are discussed in the section on Stabilizing the Floating Load
VCCS covered later in this application note.
The amplifers loop gain will force the voltage across R
S
to
assume a value equal to the voltage applied to the non-inverting
input, resulting in a transfer function of:
I
O
=V
IN
/R
S
LOAD
+VS
VS
RB VIN
RS
FIGURE 1A. BASIC VCCS FOR FLOATING LOAD
Several variations are possible for this basic circuit. It is not
necessary to have a direct feedback connection from R
S
to
the inverting input; components can be included to raise the
gain of the circuit. Figure 2 shows a higher gain version with
its equivalent transfer function. Higher gain circuits will lose
some accuracy and bandwidth, but can be easier to stabilize.
Figure 3 shows an inverting VCCS. The input voltage results
in an opposite polarity of current output. Just as in the case
of inverting voltage amplifers, the advantage of not having
any common mode variation at the amplifer input is higher
accuracy and lower distortion.
Figure 4 is a current input version which is actually a CCCS,
or current controlled current source. This is truly a current
amplifer. This circuit could be useful with current output Digital-
to-Analog Converters (DACs), or in any application where a
current is available as an input.
LOAD
+VS
VS
RB VIN
RS
I O
Rd Cf
RF
I O =
VIN
RS
FIGURE 1B. VCCS FOR FLOATING LOAD WITH STABILITY
COMPENSATION
LOAD
+VS
VS
RB VIN
RS
I O
Rd Cf
RF
I O =
VIN
RS
(1 + )
RF
RI
FOR: R << R or R
S F I
RI
FIGURE 2. VCCS FOR FLOATING LOAD; INCREASED
GAIN CONFIGURATION
LOAD
+VS
VS
RS
I O
RF
I O =
VIN
RS
RF
RI
FOR: R << R or R
S F I
RI
VIN
Rd Cf
FIGURE 3. VCCS FOR FLOATING LOAD; INVERTING
CONFIGURATION
LOAD
+VS
VS
RS
I O
RF
I O =
I IN
RS
RF
FOR: R << R
S F
I IN
Rd Cf
FIGURE 4. CCCS FOR FLOATING LOAD; INVERTING
CONFIGURATION
Voltage to Current Conversion
MAY 2009
APEX AN13UREVD
AN13
722 AN13U
STABILIZING THE FLOATING LOAD VCCS
Because the load is in the feedback loop on all of these
circuits, it will have a signifcant effect on stability. If the load
was always purely resistive, the analysis would be simple and
many circuits would not require any additional components
(such as Cf and Rd) to insure stability. In the real world however,
we usually fnd ourselves using these circuits to drive such
complex loads as magnetic coils and motors.
Stability analysis is most easily accomplished using Rate of
Closure techniques where the response of the the feedback is
plotted against the amplifer open loop gain. This technique uses
information easily obtained on any amplifer data sheet.
Rate-of-closure refers to how the response of the feedback
and amplifer Aol intersect. If the slope of the combined intersec-
tion is not over 20 dB per decade, the circuit will be stable.
For an example, consider the amplifer of Figure 1A. Assume
a PA07 amplifer with a 0.5 ohm current sense resistor will be
used to drive a 50 H coil with 1 ohm of series resistance. In
Figure 5 we have superimposed on the Aol graph of the PA07
the response of the load and sense resistor.
The intersection of the responses exhibits a combined slope
of 40 dB per decade, leading to ringing or outright oscillation.
Lets refer to that point as the critical intersection frequency.
Compensation for this circuit is best accomplished with an
alternate feedback path; the response of which will dominate
at the critical intersection frequency.
A good criteria for the response of the alternate feedback
would be:
1. A response which dominates by at least an order of mag-
nitude (20 dB) at the critical intersection frequency.
2. The alternate feedback response should have a corner
occurring at a frequency an order of magnitude less than
the critical intersection frequency.
To provide this response, the alternate feedback components
have been selected to provide the compensating response
illustrated in Figure 6. A
B
in Figure 6 is the dominant feedback
path the amplifer will see in its closed loop confguration. R
F

merely acts as a ground leg return impedance for the alternate
feedback loop, and should be a low value between 100 and
1000 ohms. Rd is then selected to provide the desired high
frequency gain, and Cf is selected for the alternate feedback
+VS
VS
RB
VIN
RS
PA07
100K
LL
RL
50H
1.0
0.5
120
100
80
60
40
20
0
20
1 10 100 1K 10K .1M 1M10M
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
FREQUENCY, F(Hz)
40dB/decade
rate of
closure
Feedback
Response
(1/)
1/ DC
Fz =
RL+RS
2L L
FIGURE 5. PLOTTING FEEDBACK RESPONSES
DC
=
.5
1.5
= .333 1/ = 9.5dB Fz =
1.0 + .5
2 50H
= 4.77kHz
corner.
Note that these are similar to techniques used to stabilize
magnetic defection amplifers described in Apex Precision
Power AN05, Precision Magnetic Defection.
CURRENT OUTPUT FOR GROUNDED LOAD
The VCCS for a grounded load is sometimes referred to as
the Improved Howland Current Pump. It is actually a dif-
ferential amplifer which senses both input signal and feedback
differentially.
Figure 7 shows a general example for this VCCS with its
associated transfer function.
First among the special considerations for this circuit is that
the two input resistors (R
I
), and the two feedback resistors
(R
F
), must be closely matched. Even slight mismatching will
cause large errors in the transfer function and degrade the
output impedance causing the circuit to become less of a true
current source.
As an example of the matching requirement, consider the
actual example using PA07 in Figure 8. Matching the resis-
tors as closely as tolerances permitted produced an output
impedance of 43 K ohms. A 1% mismatch reduced output
impedance to 200 ohms and introduced nearly 20% error into
the transfer function.
This suggests that matching to better than 0.1% is required
which is probably best accomplished with prepackaged resis-
+VS
VS
RB
VIN
RS
PA07
100K
LL
RL
50H
1.0
0.5
120
100
80
60
40
20
0
20
1 10 100 1K 10K .1M 1M10M
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)
FREQUENCY, F(Hz)
Rd Cf
FB #1
RF
100
332 .047F
FB #2
FB #2
FB #1
A
FIGURE 6. COMPENSATING THE AMPLIFIER

I O =
VIN
RS
RF
RI
FOR: R << R or R
S F I
+V S
V S
R S
I O
R
F
R
I
R I
V IN
R F
FIGURE 7. VCCS FOR A GROUNDED LOAD
LOAD
AN13
AN13U 723
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H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
tor networks with excellent ratio match. The circuit of Figure
8 actually required a slight amount of mismatch in the two
(R
F
) resistors to compensate for mismatches elsewhere,
suggesting that the inclusion of a trimpot may be necessary
to obtain maximum performance.
STABILITY WITH THE GROUNDED LOAD CIRCUIT
The grounded load circuit is remarkably forgiving from a
stability standpoint. Generally, no additional measures need
to be taken to insure stability.
Any stability problems that do arise are likely to be a result
of the output impedance of the circuit appearing capacitive.
The equivalent capacitance can be expressed as follows:
Where: fo = THE GAIN-BANDWIDTH PRODUCT OF THE
AMPLIFIER
This capacitance can resonate with inductive loads, re-
sulting most often in ringing problems with rapid transitions.
The only effective compensation is a simple Q-snubber
technique: determine the resonant frequency of the inductive
load and output capacitance of the circuit. Then, select a
resistor value one-tenth the reactance of the inductor at the
resonant frequency. Add a series capacitor with a reactance
at the resonant frequency equal to one-tenth of the resistor
value. An alternate method would be to put a small inductor
and damping resistor in series with R
S
.
Also keep in mind that the equation favors larger values of
R
I
and R
S
, and the use of op amps with better gain-bandwidth
to reduce effective capacitance. In circuits where good high
frequency performance is required, this will necessitate
increasing either or both R
I
and R
S
with the upper limits be-
ing established where stray capacitance and amplifer input
capacitance become signifcant.
An infrequent second cause of instability in this circuit is
due to negative resistance in the output impedance charac-
teristic of the circuit. This problem can be solved by trimming
the feedback resistors to improve matching.
THE CURRENT MIRROR
The current mirror circuit is a handy device for generating
a second current that is proportional to input current but op-
posite in direction.
The mirror in Figure 9 must be driven from a true current
source in order to have fexible voltage compliance at the
input. Any input current will attempt to develop a drop across
R1 which will be matched by the drop across R2 causing the
current through R2 to be ratioed to that in R1. For example, if
R1 were 1.0 K ohm and R2 were 1 ohm, then 1 mA of input
current will produce 1 Amp of output current.
RATE-OF-CLOSURE AND FEEDBACK RESPONSE
Rate-of-closure stability analysis techniques are a method
of plotting feedback response against amplifer response to
determine stability.
The closed loop gain of any feedback amplifer is given by:
Acl = Aol/(1-Aol)
Where: Aol IS THE OPEN-LOOP GAIN OF THE AMPLI-
FIER, AND Acl IS THE RESULTANT CLOSED
LOOP GAIN
is a term describing the attenuation from the output signal
to the signal fed back to the input (see Figure 10). In other
words, is the ratio of voltage fed back to the amplifer over
the amplifers output voltage. (Vfeedback=Vout)
In the examples used in this application note, the plotting
of versus amplifer response is facilitated by plotting an
equivalent closed loop response (1/) of the amplifer circuit
and superimposing this response on the amplifer open loop
response. This equivalent closed loop response is also
referred to as noise gain, Av (n).
In the example in Figure 5, the curve referred to as feedback
response is actually representative of the closed loop noise
gain response of the amplifer due to the feedback network
consisting of yoke and sense resistor. In Figure 6, an additional
feedback response for Cf, Rd, and R
F
is plotted independently
of all other responses. There are several important points to
be noted in the use of these graphs:
1. In the case of multiple feedback networks such as in Figure
6, the response with the lowest noise gain at any given
frequency will be the dominant feedback path. In Figure
6 this dominant feedback path is labelled A
.
2. Whenever the noise gain and open loop gain intersect
with a combined slope, or rate of closure, exceeding 20
dB/decade, poor stability will result. 40 dB/decade will
defnitely oscillate since this represents 180 degrees of
phase shift. An example of this is shown in Figure 5.
+VS
VS
R1
I O = I IN
I IN
R2
I O
(MUST BE
TRUE
CURRENT
SOURCE)
R1
R2
FIGURE 9. CURRENT MIRROR
Z
F
Z
I
+V
S
V
S
V
O
V
FB
V
IN
=
V
FB
V
O
=
Z
I
Z
F
Z
I
+
FIGURE 10. FEEDBACK FACTOR,
0.1
+VS
VS
RS
I O
R
F
I O = -10A/Volt input
R
I
RI
VIN
RF
10K
10K
10K
10.0007K
PA07
RC
CC
*
*
Zo =
43K with
EXACT R , R
VALUES
SHOWN
F I
OPTIONAL COMPENSATIONSEE TEXT
*
FIGURE 8. ACTUAL PA07 VCCS
R
I
+ R
F
2foR
I
R
S
Ceq =
AN14
724 AN14U
AN14 Power Booster
Applications
require placing a 22 K ohm resistor in series with the built-in
6.2 K ohm internal feedback for a total feedback resistance of
approximately 28 K ohm. In this case a 22 pF compensation
capacitor produces a rolloff at 260 kHz, again corresponding
to the PB50 small signal response graph.
COMPOSITE AMPLIFIER STABILITY CONSIDERATIONS
The PB series data sheets provide 4 guidelines for insuring
the stability of circuits designed with these boosters. Use of
these guidelines can be complemented by the use of standard
techniques such as plotting the overall gain response of the
driver/booster combination and superimposing the feedback
network response.
An example for determining the Aol (open loop gain) re-
sponse of the composite amplifer is illustrated in Figure 1. At
any given point on the frequency response, the overall gain is
the sum of the gains (in dB) of the two amplifers.
FIGURE 1. PLOTTING Aol FOR THE COMPOSITE AMPLIFIER
Figure 2 shows an example of such a plot for the defec-
tion amplifer described in this application note. As a general
rule, the intersection of the feedback response and open loop
response should equate to a slope of no greater than 20 dB/
decade to insure stability.
FIGURE 2. DEFLECTION AMPLIFIER FEEDBACK (I/)
The particular defection amplifer described in this applica-
tion note is a testament to the ease with which the PB series
The Apex Precision Power PB series of power booster ampli-
fers, PB50 and PB58, are high performance, yet economical
and fexible, solutions to a wide variety of applications. Their
voltage and current ratings of up to 200 volts at 2 amps for the
PB50, and 300 volts at 1.5 amps for the PB58, satisfy most
high voltage and high current requirements. In addition, the PB
series is fast. The 100 V/s slew rate these boosters offer is
matched or exceeded by only a few expensive power or high
voltage op amps. If accuracy, in the form of low offset, drift, and/
or bias current, is the system requirement, the PB series, with
the proper choice of driver amplifer, can deliver high voltage
performance with accuracy equal to the best small-signal op
amps available on the market, and do it economically.
DESIGNING WITH BOOSTER AMPLIFIERS:
BASIC CONNECTIONS
Power supply requirements for the PB50 dictate that the nega-
tive supply rail must be at least 30 Volts below the COMMON
terminal (pin 5), setting the minimum supply voltage at +/-30
V. The PB58 can operate from supplies as low as +/-15 volts.
The INPUT terminal of the PB series devices is a low im-
pedance input typically on the order of 50 K. Maximum safe
input voltage range must be limited to less than +/-15 volts.
These power boosters will always have an offset of typically
.75 volts as a result of the common base bipolar input stage.
When used with a driver amplifer, this offset will subtract from
the swing available from the driver. For example, a driver op
amp that is required to swing 20 volts peak-to-peak will actu-
ally swing -10.75 and +9.25 volts. This offset has no effect on
offset of the total driver and booster circuit since this offset is
effectively reduced by the open loop gain of the driver ampli-
fer. Remember that this offset will always be apparent when
used without a driver amplifer.
The COMMON terminal provides a ground reference for the
internal input and feedback circuitry. It might be noted that it
is possible to use this ground terminal as an input; however,
the PB series has not been characterized for such usage. The
ground terminal would appear as a low impedance inverting
input which must be driven from a low impedance source such
as an op amp output.
The GAIN terminal allows the connection of additional
resistance in series with the built-in feedback resistor of the
PB series. The compensation capacitor connected to COMP,
pin 8, is in parallel with the feedback resistor. Designers can
predict the frequency response of the PB series amplifers for
any compensation by simply calculating the pole frequency of
the parallel connection of feedback resistor, R
G
, and compen-
sation capacitor. The pole frequency is given by:
Where: R
G
= EXTERNAL FEEDB ACK RESISTANCE
C
C
= EXTERNAL COMPENSATION CAPACITOR
For example, a 22 pF compensation capacitor across the
6.2 K ohm feedback resistor results in a pole frequency of 1.2
MHz. This corresponds with the Closed Loop Small Signal
Response graph on the PB50 data sheet. A gain of 10 will
120
1 10 100 1K 10K 100K 1M 10M
G
A
I
N

(
d
B
)
A
o
l

R
E
S
P
O
N
S
E

O
F

C
O
M
P
O
S
I
T
E

A
M
P
L
I
F
I
E
R
A
o
l

R
E
S
P
O
N
S
E

O
F

T
L
0
7
1
RESPONSE OF PB58 @ AV
CL
= 3
100
80
60
40
20
0
120
100
80
60
40
20
0
1 10 100 1K 10K 100K 1M 10M
)
B
d
(
N
I
A
G
O
C
M
O
P
l
o
A
E
T
I
S
K
C
A
B
D
E
E
F
Y
R
A
I
L
I
X
U
A
DOMINANT FEEDBACK PATH
Fz
(due to
R , L , R )
L L S
Fp
(due to Cf,
Rd, R //R )
I F
PRIMARY
FEEDBACK
1
2 (R
G
+ 6.2K) C
C
FP =
Power Booster Applications
MAY 2009
APEX AN14UREVC
AN14
AN14U 725
G
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B
A
devices can be designed into circuits where stability is usually
a problem. The magnetic defection circuit, which is a current
source with an inductive load inside the feedback loop, is inher-
ently unstable. The composite amplifer responded quite well to
standard techniques used to stabilize defection amplifers (see
AN #5, Precision Magnetic Defection) and presented no
special stability problems.
The designer who may be apprehensive about using a booster
(buffer with gain) need have no reservations when using PB50
or PB58.
APPLICATION EXAMPLES: PROGRAMMABLE POWER
SUPPLIES
The programmable power supply (PPS) application is useful to
demonstrate the versatility of the PB series boosters. Along with
the need to supply high voltages and currents, programmable
power supplies often need high accuracy and low drift, while at
other times they may need to be fast-responding. The PB series
allows the designer to optimize the circuit for these choices. Figure
3 is an example of a high accuracy PPS. An AD707 is selected as
the driver amplifer to provide the extremely low offset required to
obtain best possible performance from a high accuracy 18-bit DAC.
The divider network on the output, R1 and R2, scale the output
swing down to the full-scale range of the DAC. Accuracy will be
affected by this divider, necessitating the use of high quality, low
temperature coefficient (TC) resistors. If a packaged network can
be used, then absolute TC is not nearly as important as TC ratio
between R1 and R2. The use of this divider is preferable to the
alternative technique of using an external DAC feedback resistor,
since using the internal DAC feedback resistor insures the best
possible temperature drift performance of the DAC itself. Most DACs
can exhibit up to 300 ppm/C drift with external feedback resistors.
FIGURE 3. HIGH ACCURACY PPS
APPLICATIONS AT LESS THAN FULL
VOLTAGE AND CURRENT
The PB series do not have to be used at high voltages to realize
all their performance benefts. Presently, only a few expensive IC
power amplifers can match these parts for slew rate and power
bandwidth. Magnetic defection applications require amplifers with
good speed performance at current levels often within those that
the PB series can supply. While these applications dont always
require high supply voltages, the high voltage capability of the
PB series is useful when fast transitions are required with high
inductance yokes, necessitating high supply voltages as a result
of the yoke energy requirement:
The basic techniques of magnetic defection amplifer design
R1
130K R2
10K
+280V
15V
RCL
CC
RG
VO
(0-270
Volts)
AD707
PB58
3
2
1
8
7
6
4
5
+15V
15V
R
FB
10K
1mA
I DAC
AD1139
18-BIT DAC
VO I DAC =
R R2 + R2 R1 + R1 R FB FB
R2
I DAC = (270K)
are detailed in AN#5, Precision Magnetic Defection.
Figure 4 is an example of these techniques put to use in
the design of a magnetic defection amplifer using the
PB58. This circuit forces a yoke current proportional to
input voltage by including the yoke within a current sensing
feedback loop. In this example, the feedback resistors R
F

and R
I
are confgured for a minimum gain of 5 to compen-
sate for the added booster gain, thereby easing stability
considerations. The auxiliary feedback network Cf and Rd
act to bypass the 90 phase shift of the yoke/sense resistor
feedback at higher frequencies ensuring stability with best
transition times. The fastest transition time in any magnetic
defection amplifer is determined by the available voltage
swing and yoke inductance. In the circuit of Figure 4, nearly
140 volts could be made available for the 200 microhenry
yoke, resulting in a minimum possible transition time of 2
microseconds. The TL071 and PB58 combination can slew
at 40 V/microsecond which means the amplifer requires
an additional 4 microseconds to provide full voltage swing.
The end result is a circuit that can deliver total transition
times of less than 6 microseconds, equating to sweep
speeds of 83 kHz.
FIGURE 4. ELECTROMAGNETIC DEFLECTION AMPLI-
FIER
An important advantage of a separate booster ampli-
fer in defection applications is the ability to swing the
output stage supply rails to improve efficiency. Slower
sweep speeds can use lower power supply voltages than
higher speeds. In addition, during a high speed sweep
the high voltage is only needed for a short period of time
until yoke current builds and can then be switched to a
lower value. Using the lower supply voltages whenever
possible improves efficiency and reduces dissipation. In
applications where the supply rails will be fexed in this
manner, only the rails connected to the power booster need
to be fexed. The constant supply available at the driver
amplifer enhances the driver amplifers ability to maintain
overall loop control by preventing the coupling of supply
switching transients into the input section of the amplifer.
Figure 4 provides a general idea of the circuitry involved
.75
+150V
150V
RCL
CC
R =0 G
TL071
PB58
3
2
1
8
7
6
4
5
+15V
15V
.4
22pF
HV SWITCH
HV SWITCH
R1
1K C1
.001F
VIN
+15V
15V
RL
LL
200H
I O
YOKE
Rd
RF
24.3K
3.9K
Cf
68pF
RI
1K .5
RS
I O = (9.8) (V )
IN
dl
dt
V = L
AN14
726 AN14U
in switching the supply rails. The actual implementation could
take on many forms that are beyond the scope of this ap-
plication note.
A fnal performance consideration in magnetic defection
amplifers is avoidance of slew rate overload (or any condition
which could result in input overload). This problem actually oc-
curs during the rapid retrace transition, but shows up during
the trace interval. The evidence of input overload is ringing
during the trace interval. To eliminate this problem, reduce the
transition time of the retrace portion of the input waveform to
a rate which is within the slew rate specifcation of the ampli-
fer. Slower transition times do not necessarily reduce circuit
performance since the amplifer was overloaded to begin with,
and eliminating ringing is actually an improvement on settling
time when returning to the trace interval. Controlling input slew
rate can be accomplished in many ways. If the actual risetime
of the input signal itself cannot be controlled, a simple low-
pass R-C flter at the input of the amplifer will suffice. In the
example shown in Figure 4., R1 and C1 provide a flter which
limits the slew rate of any input signal rise time to within the
amplifers slew rate.
Selection of the correct flter time constant takes into ac-
count both amplifer slew rate and gain of the circuit. In the
case of a magnetic defection amplifer, the appropriate value
for gain would be the effective gain of the alternate feedback
path Cf and Rd.
Where: V
IN
= PEAK TO PEAK INPUT VOLTAGE
Av = COMPOSITE AMPLIFIER CLOSED LOOP GAIN
SR = RATED SLEW RATE OF THE AMPLIFIER
V
IN
Av
SR
t =
BOOSTER WITH NO DRIVER
It is entirely possible to use power boosters without an ex-
ternal driver. This could be done for simplicity or economy. It
also provides the best slew rate and bandwidth performance
possible with the PB series. All of this is made possible due to
the boosters self-contained internal feedback loop.
When used without a driver, the PB50 will have an inherent
offset of typically 750 millivolts. Harmonic distortion remains
under 0.5% at up to 30 kHz. Input impedance will be 25 K ohms
minimum. Power bandwidth will typically be the full 320 kHz at
the 100 Volts P-P output the PB50 is capable of.
The ground terminal on pin 5 of the PB50 presents possibili-
ties as an additional input. Some improvement in bandwidth
would be noted if this terminal were used as an input with the
actual input terminal grounded. This forces the input transistor
into a cascode connection. It is possible to utilize the booster
as if it had true op amp type inverting and non-inverting inputs.
IMPORTANT NOTICE
AN16
AN16U 727
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AN16 SOA Advan-
tages of MOSFETs
when the output voltage swings closest to the rail supplying
the current. The tradeoff occurs when setting current limits,
usually for either of two fault conditions: shorts to ground or
shorts to either supply rail. A stalled motor is equivalent to a
short to ground through the motor winding resistance, while
a reversal could assume the stresses of a short to either rail.
From Figure 2, line 1, a limit safe for shorts to ground would
be 4A (4A*50V=200W). This is well below the amplifers full
20A capability. Even more stringent is the current limit for a
short to either rail of 2A indicated by line 2 of Figure 2. A 2A
limit, combined with external fyback diodes, would result in
an amplifer tolerant of virtually any short or voltage kickback
stress on its output. Keep in mind that this brief example uses
as its basis, the 25C SOA limits. In reality, internal dissipa-
tion and heatsinking limitations elevate temperatures, further
reducing safe current levels.
NEW MOSFET POWER OP AMPS EASE
SAFE OPERATING AREA LIMITATIONS
Hybrid power op amps continue to provide higher levels of
performance and power handling than their monolithic coun-
terparts. Power MOSFETs promise to continue the dominance
of the hybrid power op amp in terms of power delivery and
Safe Operating Area (SOA).
Protection issues must not be neglected regardless of
amplifer choice, but the compromises required to protect
the amplifer are eased with MOSFET designs. Protection of
an amplifer is a matter of keeping it within its SOA under all
expected conditions including faults such as short circuits.
An example of a common mistake in selecting an amplifer
for a motor drive application is to use a 5A rated amplifer to
drive a 1A motor. Specifying an amplifer for a motor drive
application is not that simple, and stall or reversal conditions
could overstress the amplifer.
Here is an illustration using a motor with the following
specifcations:

Winding resistance: 1.24 ohms
Voltage constant: 7.41V/K RPM
Torque constant: 10oz/in/A
The actual running current depends on the required torque.
Of most concern is the worst-case current requirements that
occur under stall and acceleration conditions. Under stall
conditions, the amplifer is presented with a load equal to the
winding resistance of the motor. This condition must be within
the SOA of the amplifer.
The motors speed determines the applied voltage. If there
are sudden reversals, the motor back EMF could theoretically
reach a value equal to the full applied voltage or equal to the
amplifers supply rails. This would be equivalent to shorting the
amplifer output to one of its supply rails with only the motor
winding resistance in series.
While the MOSFET power op amps are often featured for
their high speeds, motor drive applications can take advantage
of the MOSFET SOA that is free from second breakdown.
Second breakdown is a limitation of all bipolar output power op
amps. Second breakdown severely limits an op amp's current
capacity under conditions of high voltage stress. The MOSFET
on the other hand is strictly limited by its power dissipation, or
thermal limits. Figure 1 compares the 25C SOA of the PA04
MOSFET amplifer with the bipolar PA03. While the PA03 is
rated for higher currents and dissipation, the PA04 has greater
current capacity when there is more than 110V stress on the
output devices.
For 25C SOA calculations with a MOSFET amplifer an
SOA graph is not even necessary. As long as the product of
voltage and current stress is within the power dissipation rat-
ing, the amplifer is safe. MOSFETs, to reiterate, are strictly
power limited.
Proper selection of current limit will determine if an amplifer is
safe under fault conditions. One way of viewing this limitation is
to draw a graph of output voltage and current, and superimpose
SOA limits as shown in Figure 2. This graph (PA04 and 50V
supplies shown) illustrates how greater currents are available
20
50 0 50
0
20
Volts
A
m
p
e
r
e
s
S
O
A
S
O
A
1
1
2
2
3
3
2
4
2
4
FIGURE 2. PLOT OF OUTPUT VOLTAGE AND CURRENT WITH
SOA SUPERIMPOSED
40
40
1
5
10
20
30
40
Voltage
A
m
p
e
r
e
s
10 20 50 100 200
FIGURE 1. COMPARISON OF SOA FOR BIPOLAR (PA03) AND
POWER MOSFET (PA04) POWER OP AMPS
S
E
C
O
N
D
B
R
E
A
K
D
O
W
N
T
H
E
R
M
A
L
P
A
0
4
T
C =
2
5
C
P
A
0
3
T
C =
2
5
C
60
SOA Advantages of MOSFETs
MAY 2009
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FOLDOVER CURRENT LIMITING
The PA04 features four-wire current limit to overcome sens-
ing errors occurring when working with such low resistances.
While this four-wire current limit is useful in improving accuracy
of current limit, it also facilitates implementing foldover current
limiting. This limiting is known as load line limiting.
Foldover current limit allows more amplifer current as the
output swings closer to the rail supplying the current shown
by line 3 in Figure 2. Figure 3 shows the circuit to implement
foldover current limiting. Rb and Rf confgure a voltage divider
that reduces the signal to the current limit transistors as the
output swings closer to the current-supplying rail. Rf determines
the slope of the foldover function. The value selected for Rb
corresponds to the similar resistor internal to PA12 (actually
280 ohms) so that equations and methods developed for use
with PA12 foldover limiting would be easily applied to PA04
external foldover limiting. The capacitor across Rb prevents
stability problems while in current limit.
The foldover slope must not be too steep, or latching may
occur. This sets a limit to the value of Rf equal to V
S
/.0025
which results in a foldover characteristic where current available
when the voltage output has swung fully to the rail opposite to
the one supplying current is zero. The current available when
the output is closest to the rail supplying current is twice that
available when the output is at zero volts. When using PA12
equations, substitute this value of Rf, in Kohms.
A PA04 incorporating foldover limiting at 50V and requir-
ing safety for a short to ground, would have R
CL
selected for a
4A limit (this presumes the amplifer case can be maintained
at 25C for the duration of the short, otherwise it would have
to be reduced further to stay within temperature limitations).
The foldover limiting would then allow 8A at full output swing,
or near zero current when delivering current from the rail op-
posite the output voltage polarity. A bipolar amplifer such as
PA12 would be limited to 3.2A under the same criteria. The
most powerful monolithic would be limited to 300mA because
it is confgured only for simple single resistor current limiting.
SATURATION VOLTAGE AND BOOST PINS
In motor drive applications at lower voltages, the saturation
voltage, described on the data sheet as voltage swing, the
PA04 could result in considerable power dissipation. At 15A,
the PA04 output can only swing to within 8.8 volts of the rail
resulting in 132W of dissipation. Boost pins are provided on
the PA04 to power the front-end of the amplifer on voltages
higher than the output stage, thus improving saturation. Us-
ing these terminals reduces the swing-to-rail to 5.3V at 20A
for 106W dissipation. At 15A it is 4.7V for 60.5W dissipation.
Several methods can be used to supply the higher voltage
required by the front-end. Additional power transformers, or
additional taps on existing power transformers, or additional
regulated supplies are obvious options. Modern voltage con-
verter ICs make it inexpensive to develop these voltages under
almost any condition. In Figure 4, zener regulated voltages
are referred to each rail and provide power to Maxim voltage
converter ICs to develop the boost potentials.
MOSFET ADVANTAGES AT HIGHER VOLTAGES
The PA04 is rated at 100V or 200V rail-to-rail. This is twice
the rating of any bipolar hybrid power op amp other than PA03,
and 2.5 times the rating of any monolithic power op amp.
MOSFETs have made possible this increase in voltage rat-
ings and this can be useful in motor drive applications at high
voltages. Surprisingly, some DC motors require voltages around
100 volts. The PB50 power booster is a low-cost hybrid buffer
with gain that gives the same 100 volt capability of PA04 with
a maximum current of 2A. Because the PB50 is a MOSFET
device, it can still provide 200mA at a full 200V stress.
An upgrade to the PB50 is the PB58 providing voltage
capability up to 150 volts. While PB58 is rated 1.5A, the pre-
mium PB58A is specifed up to 2A. A key advantage of PB58,
especially for motor drives, is its 87W dissipation. Operated at
100V, the PB58 can provide 435mA with complete safety. At
50V, PB58 can deliver up to 870mA. This is well over twice
what could be tolerated from an amplifer such as the PA12
under the same conditions, much less from monolithic power
op amps.
Both PB50 and PB58 are power booster amplifers, not
stand alone op amps. Refer to PB50 and PB58 data sheets
for typical examples of actual composite amplifer circuits.
FIGURE 4. VOLTAGE BOOST CIRCUITS
V
V
boost
4 3 5
1 8 7
6
10F
330F
100F
(a) Positive
(b) Negative
10F
+V
330H
.1F
4 5
3
7
1
100F
+V
boost
Max632
Max636
FIGURE 3. FOLDOVER CURRENT LIMITING CIRCUIT
V
S
+V
S
PA04
11
10
7
Rcl
OUTPUT
Rb
R
F
470pF
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Several alternatives are given. They range from low speed,
high accuracy circuits, to high speed circuits.
ADVANCED AMPLIFIER PROTECTION
The PA04s adaptability to foldover current limiting is important
but not the last word in protection. Prior efforts at SOA protec-
tion have been based on bipolar transistor designs sensing
output transistor temperature combined with current limiting.
These techniques have shortcomings when overstress occurs
while operating in the second breakdown region of bipolar
power devices. The isolated hot spot occurring during second
breakdown can escape sensing by the temperature sensor.
15
10
5
3
2
1.5
1
.7
.6
.3
10 20 50 100 200 300
P
A
1
2
T
C =
2
5
C
PB58 T
C
= 25C
S
E
C
O
N
D
B
R
E
A
K
D
O
W
N
Volts
A
m
p
e
r
e
s
FIGURE 5. COMPARISON OF SOA FOR PA12 AND PB58
For example, PA03 senses power transistor temperature to
provide a high degree of protection. But at total rail-to-rail volt-
ages in excess of 60V (30V), second breakdown still makes
the amplifer prone to failure in extreme stresses.
In a MOSFET power output device, if a local hot spot occurs,
the local transconductance decreases along with an increase
in Rds at the hot spot. This facilitates thermal spreading rather
than concentrating heat. As a result thermal sensing should
prove extremely effective with power MOSFETs. Apex Preci-
sion Power is developing such amplifers and early testing has
shown that this may be the key to ultimate amplifer protection.
IMPORTANT NOTICE
AN17
730 AN17U
AN17 Wideband, Low
Distortion Techniques
Where: Df = % DISTORTION WITH FEEDBACK
D = % DISTORTION OPEN LOOP
A = OPEN LOOP GAIN
Af = CLOSED LOOP GAIN
It is obvious that open loop distortion is an important criteria
in amplifer selection. A high open loop gain is also desirable,
but op amps with high open loop gains most often have a
severe tradeoff in gain-bandwidth.
The minimum useful closed loop gain is determined by the
amplitude of the drive signal available to the power op amp
circuit. Most often this drive is likely to come from a small sig-
nal op amp with the customary 10 V peak drive capability. If
for example a PA04 power op amp is being designed which
operates at the full 100 V supply rail limit of the PA04, this
will require a minimum gain of 10.
In the event the drive signal is not a full 10V peak, a trad-
eoff must be made as to whether the power op amp should be
operated at a higher gain, or an additional small signal op amp
be included for additional gain. Consider that the additional
small signal op amp will result in insignifcant contributions to
distortion as long as its gain is low (<30). The light loading of
the power amp circuit further minimizes distortion from the
small signal op amp. These considerations favor this multiple
op amp approach with a lower gain power op amp compared
to a single high gain power op amp.
Low closed loop gain in the power op amp equates to in-
creased amounts of negative feedback. This condition occasion-
ally meets with unfounded objections when the requirement is
low distortion, especially under transient conditions. However,
this is dealt with by slew rate limiting to be discussed later.
The inverting amplifer confguration forces common mode
potentials to zero. By doing so, non-linearities due to common-
mode effects are also reduced to zero. The main advantage a
non-inverting confguration would have is greater freedom of
design regarding input impedance of the power op amp circuit
along with the obvious lack of inversion.
Although the inverting confguration reduces input imped-
ance, the two amplifer approach insures that the power amp
circuit is driven by a source adequate to handle the resultant
impedance. The cascade of two inverting amplifers yields a
non-inverting circuit. A further possible useful feature of the
inverting power amp circuit is that the summing node can be
monitored and any voltage detected used to indicate fault or
non-linear conditions.
EXTERNAL PHASE COMPENSATION
Many power op amps are internally compensated for unity
gain stability. However, this trades off gain-bandwidth product
for stability under all operating conditions. Since distortion
reduction is proportional to the ratio of open loop to closed
loop gain, it is desirable to have as high as possible open-loop
gain at high frequencies. Since it is unlikely that the power
op amp will be confgured for unity gain, the external phase
compensation allows for a reduced compensation, yielding
improved distortion and slew performance.
WIDEBAND, LOW DISTORTION TECHNIQUES FOR
MOSFET POWER AMPS
Shake table systems, function generators and acoustic instru-
ments all have requirements similar to quality audio amplifers:
wide bandwidths along with low distortion. In the past, industrial
grade power op amps have traded off bandwidth to insure unity
gain stability, and the bipolar designs have not always met the
linearity requirements of demanding applications. The PA04
changes all this with a MOSFET based architecture that sets
new standards for bandwidth and linearity of integrated circuit
power amplifers.
The development of the PA04 was driven by sonar applica-
tion requirements for a highly linear, high power amplifer with
a power bandwidth in excess of 100 kHz. MOSFETs are the
optimum choice power device to provide this performance, and
in the PA04 Apex Precision Power goes several steps further in
using MOSFETs in all active gain stages. While this application
note will focus on getting best bandwidth and linearity from the
PA04, the techniques described apply to any power op amp.
Op amps depend on negative feedback to improve perfor-
mance in all ways including accuracy, linearity and bandwidth.
The ideal condition is to use feedback around a design which
has inherently good open loop characteristics. Evaluation of
prospective amplifers under open loop conditions quickly
reveals linearity and bandwidth defciencies. Even a simple
distortion measurement under open loop conditions will give
rapid comparative evaluation. Alternatively, an X-Y comparison
using an oscilloscope and the circuit of Figure1, which multiplies
summing node error by 100, will give a visual display of ampli-
fer linearity. The circuit of Figure 1 will reveal that PA04 has
an inherently linear characteristic while even the best bipolar
designs such as PA07 have quite a bit of curvature in their open
loop linearity. This is traceable to the better inherent linearity
of MOSFET devices in comparison to bipolar transistors.
CIRCUIT CONSIDERATIONS
The design considerations desirable for wideband, low
distortion designs can be summed up with four guidelines:
1. Lowest possible closed loop gain.
2. Inverting confguration.
3. External phase compensation.
4. Input slew-rate limiting.
Distortion reduction in an op amp circuit is proportional to
the amount of feedback, and this corresponds to lower gain
circuits having reduced distortion. Distortion reduction is de-
scribed mathematically as:
FIGURE 1. SIMPLE TEST CIRCUIT
1K
INPUT
False summing node
10K
Horizontal
10
10K
100
Vertical
Df = D ( )
Af
A
Wideband, Low Distortion Techniques
MAY 2009
APEX AN17UREVC
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When a power amplifer drives a capacitive load, the interac-
tion between output resistance and capacitive load creates an
additional pole and attendant phase shift in amplifer response
(Figure 3). Inductive loads can result in stability problems due
to rising impedances at high frequencies. Most follower type
output stages are immune to the effects of inductive loads, but
collector output, drain output and quasi-complementary output
stages with local feedback loops are susceptible to parasitic
oscillations driving inductive loads.
Figure 4 shows several measures are available to improve
stability, each with some advantage and disadvantage: (a.)
Capacitor across feedback resistor. This provides a compensat-
ing phase lead in the feedback path to counteract the effects of
additional poles. This technique generally requires a unity-gain
stable amplifer. (b.) Parallel inductor-resistor combination in
The small signal response curve for PA04 shown in Figure 2
helps to illustrate the comparative advantage of external phase
compensation. The straight line at 20dB represents a gain of
10 amplifer which if the PA04 were compensated for unity gain
would provide a 200 kHz rolloff. Decompensation for a gain of
10 results in a 700 kHz rolloff. In addition, note that loop gain
for the unity-gain compensation is only 22 dB at 20 kHz, while
it is 30 dB for the gain of 10 compensation. This increase in
loop gain results in 2.5 times less distortion at 20 kHz.
The large amount of feedback at low gains obviously reduces
distortion. Problems can occur however under transient condi-
tions. If a step function is applied to the input of the amplifer
circuit, the output can only change as fast as the amplifer slew
rate allows. During this slew interval the input summing node
will develop a large differential voltage. This nonlinear condition
and input overload can cause a host of difficulties including a
slow and poorly behaved recovery from this overload.
Restriction of the input slew rate can avoid these transient
distortion problems. The input should never be allowed to
slew faster than the amplifer output can follow. If the actual
slew rate of the source cannot be predicted or controlled,
then simple low pass fltering at the amplifer input will prevent
transient distortion.
The flter time constant is a function of amplifer slew rate.
The maximum acceptable rate-of-change on the input signal
is limited to a value less than the amplifer slew rate divided
by the amplifer gain. With a known maximum step function
input, the maximum rate-of-change at the low pass flters output
occurs at t=0 and is determined by:
dv/dt = (V/R)/C
The RC time constant trc required at the amplifer input is:
trc = (V
IN
A
V
)/S
R
Where: V
IN
= PEAK-TO-PEAK INPUT VOLTAGE
A
V
= CLOSED LOOP GAIN
S
R
= SPECIFIED AMPLIFIER SLEW RATE
Note that there is some reduction in bandwidth with this flter.
However, with the PA04 this still permits a 40 kHz bandwidth.
This limitation again favors the use of the fastest possible
power amplifers. Keep in mind that transient behavior is actu-
ally enhanced by the addition of the input flter.
FIGURE 3. CAPACITIVE OP AMP LOADS
V
IN
R
O
C
L
2-pole response
2nd pole due to R
O
and C
L
=
20
40
60
80
100
120
140
0.001 0.01 0.1 1 10 100 1k 10k 100k 1M 10M
220pF
100pF
PA04
R
C
= 120
I
OUT
= 10A
V
S
= 50V
R
L
= 4
S
R
@ C
C
= 470pF = 9.81V/S
@ C
C
= 220pF = 18.75V/S
@ C
C
= 100pF = 45.1V/S
Bandwidth for unity gain compensation (for gain of 10 circuit)
Frequency (Hz)
470pF
G
a
i
n

(
d
B
)
Bandwidth for
gain of
10 compensation
Loop gain at 20kHz
22dB for unity gain compensation
30dB for gain of 10 compensation
0
FIGURE 2. THE SMALL SIGNAL RESPONSE FOR THE PA04
(c)
(a)
(b)
(d)
FIGURE 4. STABILITY ENHANCING TECHNIQUES
C
C
C
C
C
C
L
C
R
O
R
C
R
C
AN17
732 AN17U
TYPICAL DESIGN EXAMPLE
A design utilizing all of the guidelines described here
would be constructed around a PA04 in an inverting gain of
10 confguration as shown in Figure 5. For additional gain the
PA04 is preceded by a small signal op amp also operating
at an inverting gain of 10. Many choices are available for this
op amp such as the 5534 or OP37. The PA04s tolerance of
reactive loads negates the need for additional stability en-
hancement components.
With an 8 ohm load this circuit can supply over 300W at
up to 150 kHz with the input slew rate flter bypassed. With
the flter in place, gain begins to rolloff at 40kHz, although
full output swing is available up to 150kHz. Distortion never
exceeds 0.02% THD. Power supplies will need to be capable
of at least 7A to support 8 ohm loads in ac coupled applica-
tions. Regulated supplies arent necessary but are desirable
from a reliability standpoint.
When designing for low distortion with PA04, the imped-
ance of the feedback and input networks around the op amp
should be kept as low as possible. The input MOSFETs of
the PA04 cause it to have a large input capacitance which is
nonlinear with variations in input signal. Excessive impedances
will increase distortion due to these higher order capacitance
effects. The 2K ohm input resistor of Figure 5 is high enough
to avoid excessive loading of the small signal op amp and low
enough to avoid distortion effects with the PA04.
Several basic practices are important to implement when
using PA04. Power supply bypassing consisting of good high
frequency capacitors, generally ceramic, must be connected
from each supply rail to ground. Unless these capacitors are
physically close to the amplifer, parasitic oscillations may
occur. Even an inch away from the socket pins is too far. Be
sure to read and observe all ESD precautions on the PA04
data sheet, and those shipped with PA04.
INPUT 1K
3.9nF
10K 100K
20K +80V
80V
PA04
C
C
100pF
R
C
R
CL
OUTPUT
OP 37
2K
1
8
9
10
7
4
3
6
5
0.068
CURRENT-LIMITING
RESISTOR
SLEW-LIMITING
FILTER
FIGURE 5. A HIGH PERFORMANCE OP AMP DESIGN
2
120
11
series with amplifer output. Feedback must be taken directly
at output of amplifer so that inductor-resistor has the effect
of isolating the amplifer and feedback network from the ca-
pacitive load. (c.) Series resistor and capacitor from amplifer
output to ground, often referred to as a snubber. Used only in
situations where amplifers are sensitive to inductive loads.
Insures a low, resistive load impedance at high frequen-
cies. (d.) Series R-C network across op amp inputs, often
referred to as noise-gain compensation. Simply described,
this technique reduces feedback at high frequencies to the
point where stability is not a problem.
Methods a and b offer the best overall bandwidth perfor-
mance and transient behavior. Method a has been mentioned
already as having the tradeoff of requiring a unity gain stable
amplifer. However, with proper attention to design, it is
possible to incorporate method a with any amplifer to help
control overshoot and ringing behavior.
Method d, the noise gain compensation, will have the effect
of reducing the closed loop bandwidth of the resultant circuit
to the same effective closed loop bandwidth corresponding
to the noise gain. To illustrate, consider a gain of 10 ampli-
fer with a network across the inputs confgured for a high
frequency noise gain of 100. If the gain of 10 amplifer had an
uncompensated bandwidth of 100 kHz, with the noise gain
compensation, the bandwidth would be reduced to 10 kHz. In
addition, the response curve peaks near the high frequency
limit resulting in overshoots in the square wave response.
All amplifers vary in their ability to tolerate capacitive
loading before stability problems occur. PA04 is especially
good in this regard tolerating well over 1 uF while operating
at a gain of 10. In the case of PA04, no additional stability
enhancement measures are required and this is the ideal
case for best frequency response.
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AN19 Stability for Power
Operational Amplifers
1.0 LOOP STABILITY VS NON-LOOP STABILITY
There are two major categories for stability considerations
Non-Loop Stability and Loop Stability.
Non-Loop Stability covers design areas not related to feed-
back around the op amp that can cause oscillations in power
op amp circuits such as layout, power supply bypassing, and
proper grounding.
Loop Stability is concerned with using negative feedback
around the amplifer and ensuring that the voltage fed back
to the amplifer is less than an additional 180 phase shifted
from the input voltage.
The two key factors to troubleshooting an oscillation prob-
lem are:
1) What is the frequency of oscillation? (refer to Figure 1 for
defnitions of UGBW (Unity Gain Bandwidth) and CLBW
(Closed Loop Bandwidth) to be used throughout this text)
2) When does the oscillation occur?
The answers to these two questions, along with the sections
that follow, should enable you to identify and solve most power
op amp stability problems. More importantly, by applying the
recommendations in the following sections, you can design
power op amp circuits free of oscillation.
2.0 NON-LOOP STABILITY
2.1 CASE GROUNDING
* fosc < UGBW
* oscillates unloaded?may or may not
* oscillates with V
IN
= 0?may or may not
Ungrounded cases of power op amps can cause oscilla-
tions, especially with faster amplifers. The cases of all Apex
Precision Power amplifers are electrically isolated to allow for
mounting fexibility. Because the case is in close proximity to
all the internal nodes of the amplifer, it can act as an antenna.
Providing a connection from case to ground forms a Faraday
shield around the power op amps internal circuitry that prevents
noise pickup and cross coupling or positive feedback.
2.2 RB+ BIAS RESISTOR
* fosc < UGBW
* oscillates with V
IN
= 0?may or may not
Figure 2 is a standard inverting op amp circuit which includes
an input bias current matching resistor on the noninverting input.
The purpose of this resistor is to reduce input offset voltage errors
due to bias current drops across the equivalent impedance as
seen by the inverting and non-inverting input nodes. RB+ can
form a high impedance node on the noninverting input which
will act as an antenna receiving unwanted positive feedback.
Calculate your DC errors without the resistor. Some op amps
have input bias current cancellation negating the effect of RB+.
Some op amps have such low input bias currents that the error
is insignifcant when compared with the initial input offset volt-
age. Leave RB+ out, grounding the + input, if possible. If the
resistor is required, bypass it with a .1 uF capacitor in parallel
with RB+ as shown in Figure 2.
2.3 POWER SUPPLY BYPASSING
* fosc < UGBW
* oscillates unloaded?no
* oscillates with V
IN
= 0?may or may not
Supply loops are a common source of oscillation problems.
Figure 3 shows a case where the load current fows through
the supply source resistance and parasitic wiring or trace re-
sistance. This causes a modulated supply voltage to be seen
at the power supply pin of the op amp. This modulated signal
is then coupled back into a gain stage of the op amp via the
compensation capacitor. The compensation capacitor is usually
referred to one of the supply lines as an AC ground.
Figure 4 shows a second case for supply loop oscillation
problems. Power supply lead inductance interacts with a ca-
pacitive load forming an oscillatory LC, high Q, tank circuit.
FIGURE 1. DEFINITION OF CLBW & UGBW
.1 1 10 100 1K 10K 100K 1M 10M 100M
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY, f (Hz)
G
A
I
N

(
d
B
)
220
Aol
AV
CL
CLBW = 10KHz
UGBW = 1MHz
UNITY GAIN
V
OUT
49.9K
RB+
V
IN
100K
IBIAS
IBIAS
100K
FIGURE 2. RB+
V
OUT
49.9K
RB+
V
IN
100K
IBIAS
IBIAS
RI
RF
CB+
.1F
GAIN
STAGE
RL
POWER
STAGE
IL
FIGURE 3. IL MODULATION
Cc
Vs
Rs
Stability for Power Operational Amplifiers
MAY 2009
APEX AN19UREVD
AN19
734 AN19U
Fortunately, both of the above supply line related problems
can be eliminated through the use of proper power supply
bypass techniques. Each supply pin must be bypassed to
common with a high frequency bypass .1uF to .22uF ceramic
capacitor. These capacitors must be located directly at the
power op amp supply pins. In rare cases where power supply
line inductance is high, it may be necessary to add 1 to 10
ohms of resistance in series with the high frequency bypass
capacitor to dampen the Q of the resultant LC tank circuit.
This additional resistor will probably only be necessary when
using a wideband amplifer since amplifers of 5 MHz unity
gain bandwidth or less will not respond to the high frequency
oscillation caused by line inductance interacting with the high
frequency bypass capacitor. Refer to Figure 5.
In addition, a low frequency bypass capacitor, minimum
value of 10uF per Ampere of peak output current, should be
added in parallel with the high frequency bypass capacitors
from each supply rail to common. Tantalum capacitors should
be used when possible due to their low leakage, low ESR and
good thermal characteristics. Aluminum Electrolytic capacitors
are acceptable for operating temperatures above 0C. These
capacitors should be located within 2" of the power op amp
supply pins. Refer to Figure 5.
2.4 MULTIPLE AMPLIFIER BOARDS
* fosc < UGBW
* oscillates with V
IN
=0?yes
A prototype circuit is built and bench tested to confrm desired
performance. Several channels of the same circuit are used on
a printed circuit board layout. Much to the dismay of the design
engineer, the amplifer circuits on the printed circuit board
oscillate. Cross coupling through the power supply lines can
be a major problem on multiple amplifer printed circuit boards.
Ground the case of each amplifer and ensure each amplifer
has its own power supply bypassing per Section 2.3.
2.5 OUTPUT STAGE OSCILLATIONS /
OUTPUT R-C SNUBBER
* fosc > UGBW
* oscillates with V
IN
= 0? no, only oscillates over a portion
of the output cycle
Sometimes output stages of power op amps can contain
local feedback loops that give rise to oscillations. The frst type
of output stage instability problem arises from a tendency of
emitter followers to appear inductive when looking back into
their emitter. This occurs if they are driven from a low impedance
source and can create output stage oscillations if capacitance
is present on the amplifers output. Refer to Figure 6. This type
of instability is rare and usually only shows up when driving
load capacitances within a limited range of values.
The second, more common type of output stage oscillation
is due to non-emitter follower output type stages. These stages
have heavy local feedback paths. Refer to Figure 7 which is an
C2
C1
+
C1
C2
+
OP
AMP
V
S
+V
S
FIGURE 5. POWER SUPPLY BYPASSING
C1 = .1 TO .22 F, CERAMIC DISC
C2 = 10 F/AMP OUT (PEAK), ELECTROLYTIC
Rs = 3 10 (PROVISIONAL
HIGHLY INDUCTIVE P.S. LINES)
< 2"
< 2"
Rs
Rs
OP
AMP
CL
FIGURE 4. LC OSCILLATION
+Vs
Lw
POWER OP AMP
FIGURE 6. EMITTER FOLLOWER WITH C LOAD
CL
FIGURE 7. COMPOSITE OUTPUT STAGE
R1 R2
Q2
Q1
Vs
L
O
A
D
FIGURE 8. OUTPUT RC SNUBBER
.1 to 1F
V
IN
V
OUT
RI RF
10 to 100
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example of a composite PNP type output stage. This stage is
typical of monolithic power op amps where high current PNP
transistors are not readily available. The local feedback in the
Q1, Q2 loop will cause output stage oscillations when the
output swings negative under reactive loading.
Both of these output stage problems can be fxed by using
an R-C Snubber on the output of the op amp to ground or the
negative supply rail. This is provided the negative supply rail
is properly bypassed per Section 2.3. The Snubber network
consists of a 10 to 100 ohm resistor in series with a capacitor
of .1 to 1 F (refer to Figure 8). This network lowers the high
frequency gain of the output stage preventing unwanted high
frequency oscillations.
2.6 GROUND LOOPS
* fosc < UGBW
* oscillates with V
IN
= 0?yes
Ground loops come about from load current fowing through
parasitic layout resistances and wiring. If the phase of the out-
put signal is in phase with the signal at the node it is fed back
to, it will result in positive feedback and oscillation. Although
these parasitic resistances (RR in Figure 9) in the load current
return line cannot be eliminated, they can be made to appear
as a common mode signal to the amplifer. This is done by
the use of a star ground approach. Refer to Figure 9. The
star ground is a point that all grounds are referenced to. It is a
common point for load ground, amplifer ground, signal ground
and power supply ground.
2.7 PRINTED CIRCUIT BOARD LAYOUT
* fosc < UGBW
* oscillates with V
IN
= 0?no
High current output traces routed near input traces can
cause oscillations. This is especially true when the output
is adjacent to the positive input, giving undesirable positive
feedback through capacitive coupling between the adjacent
traces. Feedback, input, and bypass components, along with
current limit sense resistors, should be located in close prox-
imity to the amplifer.
If a printed circuit board has both a high current output trace
and a return trace for that high current, then these traces should
be routed adjacent to each other (on top of each other on a
multi-layer printed circuit board) so they form a twisted pair
type of layout. This will help cancel EMI generated outside
from feeding back into the amplifer circuit.
3.0 LOOP STABILITY
3.1 BETA SS - FEEDBACK FACTOR
Control theory is applicable to closing the loop around a
power op amp. The block diagram in Figure 10 consists of a
circle with an X, which represents a voltage differencing circuit.
The rectangle with Aol represents the amplifer open loop gain.
The rectangle with the represents the feedback network.
The value of is defned as the fraction of the output voltage
that is fed back to the input; therefore, can range from 0 (no
feedback) to 1 (100% feedback).
The term Aol that appears in the V
OUT
/V
IN
equation in Figure
10, has been called loop gain because this can be thought
of as a signal propagating around the loop that consists of the
Aol and networks. If Aol is large, there is a lot of feedback.
If Aol is small, there is not much feedback.
3.2 RATE OF CLOSURE & STABILITY
Refer to Figure 11. Aol is the amplifers open loop gain
curve. 1/ is the closed loop AC small signal gain in which the
amplifer is operating. The difference between the Aol curve
and the 1/ curve is the loop gain. Loop gain is the amount
of signal available to be used as feedback to reduce errors
and non-linearities.
A frst order check for stability is to ensure when loop gain
goes to zero, open loop phase shift must be less than 180
degrees where the 1/ curve intersects the Aol curve. Another
way of viewing that same criteria is to say at the intersection
FIGURE 9. GROUND LOOPS
V
IN
GROUND
PROBLEM
V
IN
SOLUTION
STAR
GROUND
POINT
RI RF
RL
RR RR
IL
RI RF
RR
RL
RR
RR
FIGURE 10. BETA () FEEDBACK FACTOR
V
OUT
V
OUT
+
A
OI
1+
V
OUT
V
OUT
+

Aol
V
IN
V
OUT
V
OUT
V
IN
V
OUT 1

V
IN
=

Aol

RF
RI
Vfb

Aol

= Aol

Aol

Aol

=

=
( FOR: Aol b >> 1)
Vfb =
V
OUT
RI
RI + RF
Vfb = V
OUT
=

RI + RF
RI
V
IN
V
IN
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of the 1/ curve and the Aol curve the difference in the slopes
of the two curves, or the RATE OF CLOSURE, is less than or
equal to 20 dB per decade. This is a powerful frst check for
stability. It is, however, not a complete check. For a complete
check we will need to check the open loop phase shift of the
amplifer throughout its loop gain bandwidth.
A 40 dB per decade RATE OF CLOSURE indicates marginal
stability with a high probability of destructive oscillations in
your circuit. Figure 11 contains several examples of both stable
(20 dB per decade) and marginally stable (40 dB per decade)
rates of closure.
3.3 EXTERNAL PHASE COMPENSATION
External phase compensation is often available on an op
amp as a method of tailoring the op amps performance for a
given application. The lower the value of compensation capaci-
tor used the higher the slew rate of the op amp. This is due
to fxed current sources inside the front end stages of the op
amp. Since current is fxed, we see from the relationship of I
= CdV/dt that a lower value of capacitance will yield a faster
voltage slew rate.
However, the advantage of a faster slew rate has to be weighed
against AC small signal stability. In Figure 12 we see the Aol
curve for an op amp with external phase compensation. If we
use no compensation capacitor, the Aol curve changes from a
single pole response with Cc = 33pF, to a two pole response
with Cc = 0pF. Curve 1 illustrates that for 1/ of 40 dB the op
amp is stable for any value of external compensation capaci-
tor (20 dB/decade rate of closure for either Aol curve, Cc =
33pF or Cc = 0pF). Notice that 1/ curve continues on past the
intersection of the Aol curve. At the intersection of 1/ and Aol,
the AV
CL
closed loop gain curve, or V
OUT
/V
IN
gain begins to roll
off and follow the Aol curve. This is because there is no loop
gain left to keep the closed loop gain fat at higher frequencies.
Curve 2 illustrates that for 1/ of 20 dB and Cc = 0pF, there
is a 40 dB/decade rate of closure or marginal stability. To have
stability with Cc = 0pF minimum gain must be set at 40dB. This
requires a designer to not only look at slew rate advantages of
decompensating the op amp, but also at the gain necessary
for stability and the resultant small signal bandwidth.
3.4 STABILITY - RATE OF CLOSURE
Figure 13 shows a typical single pole op amp confguration
in the inverting gain confguration. Notice the additional V
NOISE

10 100 1K 10K .1M
100
80
60
40
20
0
FREQUENCY, F (Hz)
1M 10M
120
O
P
E
N

L
O
O
P

G
A
I
N

A
o
l

(
d
B
)
STABLE FOR ANY Cc
STABLE FOR ANY Cc

= 0pF 2
1

AV
CL
1/

Aol

Cc = 0pF

Cc = 33pF
1
2
RI
RF
Cc
FIGURE 12. EXTERNAL PHASE COMPENSATION
1
FIGURE 13. STABILITY RATE OF CLOSURE
1
fz
100 1K 10K 100K 1M
100
80
60
40
20
0
FREQUENCY, F (Hz)
G
A
I
N

(
d
B
)

V
OUT

V
NOISE

V
IN
fp =
1
2 RF CF
RI + RF
2 RI RF CF
Aol
fp 1
fp1
Aol
fp2
10
fcl
CF
RF
RI
Vfb
fz =
40 dB
DECADE
FIGURE 11. RATE OF CLOSURE & STABILITY
1/1
1/2
1/3
1/4
1 10 100 1K 10K 100K 1M
100
80
60
40
20
0
*
*
*
FREQUENCY, F (Hz)
G
A
I
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(
d
B
)
**
* 20 dB/ DECADE RATE OF CLOSURE STABILITY
** 40 dB/ DECADE RATE OF CLOSURE MARGINAL STABILITY
*
Aol
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degrees phase shift from feedback network components would
yield -360 degrees phase shift). This condition would continue
to feed upon itself causing the amplifer circuit to break into
uncontrollable oscillations.
Notice in Figure 14 this open loop plot is really a plot of Aol
. The slope of the open loop curve at fcl is 40 dB per decade
indicating a marginally stable circuit. As shown, the zero from
the 1/ plot in Figure 13 became a pole in the open loop plot
in Figure 14 and likewise the pole from the 1/ plot in Figure 13
became a zero in the open loop plot of Figure 14. We will use
this knowledge to plot the open loop phase plot to check for
stability. This plot of the open loop phase will provide a complete
stability check for the amplifer circuit. All the information we
need will be available from the 1/ curve and the Aol curve.
4.0 STABILITY & THE INPUT POLE /
INPUT & FEEDBACK IMPEDANCE
* fosc < CLBW
* oscillates unloaded?yes
* oscillates with V
IN
= 0?yes
All op amps have some input capacitance, typically 6-10
pF. Printed circuit layout and component leads can introduce
additional input stray capacitances. When high values of
feedback and input resistors are used, this input capacitance
will contribute an additional pole to the loop gain response (a
zero in the 1/ plot, a pole in the open loop phase check for
stability, or a pole in the Aol , loop gain, plot).
We will refer to Figure 15 for a detailed look at the input pole
and stability. Remember, our frst order criteria for stability is a
voltage source shown at the +input of the op amp. This is shown
to aid in conceptually viewing the 1/ plot.
An inverting amplifer with its +input grounded, will always
have potential for a noise source to be present on the +input .
Therefore, when one computes the 1/ plot, the amplifer will
appear to run in a gain of 1 + RF/RI for small signal AC. The
V
OUT
/V
IN
relationship will still be RF/RI. This is also why an
amplifer can never run at a gain of less than one for small
signal AC stability considerations.
The plot in Figure 13 shows the open loop poles from the
amplifers Aol curve, as well as the poles and zeroes from
the 1/ curve. The locations of fp and fz are important to note
as we will see that poles in the 1/ plot will become zeroes
and zeroes in the 1/ plot will become poles in the open loop
stability check.
Notice that at fcl the RATE OF CLOSURE is 40 dB per de-
cade indicating a marginal stability condition. The difference
between the Aol curve and 1/ curve is labelled Aol which
is also known as loop gain.
3.5 STABILITY - OPEN LOOP
Stability checks are easily performed by breaking the feedback
path around the amplifer and plotting the open loop magni-
tude and phase response. Refer to Figure 14. This open loop
stability check has the frst order criteria that the slope of the
magnitude plot as it crosses 0 dB must be 20 dB per decade
for guaranteed stability.
The 20 dB per decade is to ensure the open loop phase
does not dip to 180 degrees before the amplifer circuit runs
out of loop gain. If the phase did reach -180, the output volt-
age would now be fed back in phase with the input voltage
(-180 degrees phase shift from negative feedback plus -180
FIGURE 14. STABILITY OPEN LOOP
1 100 1K 10K 100K 1M
100
80
60
40
20
0
FREQUENCY, F (Hz)
G
A
I
N

(
d
B
)
V
OUT
fz =
1
2 RF CF
fp =
RI + RF
2 RI RF CF
Aol
fp1
fp
(fp2 + fz)
10
fcl
V
IN
CF
RF
RI
40 dB
DECADE
10 100 1K 10K
FREQUENCY, F (Hz)
1M 10M
FIGURE 15. THE INPUT POLE
1
100
80
60
40
20
0
G
A
I
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(
d
B
)
100K
20
120
2
4
1
3
1
2
5
4
Aol
CI

/ CF

> RF

/ RI

CF

>> CI

RF

/ X
CI
CI

/ CF

= X
CF
/ X
CI

CF
RF
RI
CI
CI

/ CF

= RF

/ RI

3
5
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Rate Of Closure of 20dB per decade or less. Curve 1 is the op
amps Aol plot. Curve 5 shows the effect of input capacitance
with no CF feedback capacitor. We see the rate of closure
is 40 dB per decade and marginal stability exists. With just
CI present, as frequency increases, the impedance from the
-input of the op amp decreases, thereby causing the 1/ plot
to increase (remember X
CI
= 1/2fCI). If we now add some
small value of CF as in Curve 2 we see the 1/ plot fatten
out to intersect the Aol at a rate of closure 20 dB per decade
implying stability. If we further increase CF, as in Curve 3, such
that both breakpoints are the same frequency, we will have
ZF/ZI constant over frequency and the 1/ plot will be fat with
frequency. This yields the ever-stable 20 dB per decade rate
of closure. If we then continue to increase CF as in Curve 4,
we will see CFdominate as frequency increases and the net
result is a low pass flter frequency roll-off. For this case the
op amp must be unity gain stable, since the op amp operates
at a gain of one for frequencies above 10KHz.
Often you will see CF recommended to be used to decrease
overshoot and improve settling time for a transient input into
a given op amp circuit. In the AC small signal domain, we are
merely optimizing the circuit for stability.
Minimize values of feedback and input resistor values. This
will reduce the effect of the input pole as well as help reduce
DC errors by keeping voltage drops due to bias currents low. A
summing node of an op amp can pick up unwanted AC signals
and amplify them if that node is high impedance. Keeping the
feedback and input resistance values low will reduce the im-
pedance at the summing nodes and minimize stray signal pick
up. Practical values for feedback and input resistance values
are from 100 ohms to 1 megaohm.
5.0 LOOP STABILITY EXAMPLES
5.1 VOLTAGE TO CURRENT CONVERSION
FLOATING LOAD
* fosc < CLBW
* oscillates unloaded ? yes
* oscillates with V
IN
= 0 ? yes
Figure 16 illustrates a common voltage to current conver-
sion circuit. The input command voltage of +/-10V is scaled to
control -/+1.67A of output current through the load.
This V-I (Voltage to Current) topology is a foating load drive.
Neither end of the load, series RL and LL, is connected to ground.
V
IN
.301
R
CL +
1K Rs
FIGURE 16. V-I CIRCUIT AND STABILITY
10V
RI
4.99K
PA07
RF
1.2
VRs
LL
159mH
I
OUT

1.67A
RL
9
28V
+28V
Cf
.301
R
CL
FB#2
FB#1
Rd
FIRST GUESS 825K 820pF
FINAL VALUES 82.5K .068mF
Rd

Cf
The easiest way to view the voltage feedback for load current
control in this circuit is to look at the point of feedback which is
the top of Rs. The voltage gain VRs/Vin is simply -RF/RI which
translates to (1K/4.99K = -.2004). The Iout/Vin relationship is
then VRs/Rs or Iout = - Vin (RF/RI)/Rs which for this circuit is
(Iout = -.167 Vin). We will use our knowledge of 1/, Rate of
Closure, and open loop stability phase plots, to design this V-I
circuit for stable operation. There are two voltage feedback paths
around the amplifer, FB#1 and FB#2. We will analyze FB#1 frst
and then see why FB#2 is necessary for guaranteed stability.
STABILITY SOLUTION FOR V-I CIRCUIT
STEP 1: On Figure 17 plot the op amps Aol curve as given
by the manufacturer.
STEP 2: On Figure 17 plot FB#1. Refer to Figure 18 for calcu-
lation of FB#1. At DC, LL is a short and so is a voltage
divider through resistors as shown in Figure 18. As we go
to higher frequencies, the reactance of LL will increase
(XL = 2fL). This will increase the net load impedance
which will cause to decrease and 1/ to increase as
frequency increases. Since we are working with a single
reactive element the increase of that gain will be 20 dB
per decade. Figure 18 details the breakpoint fz where this
increase begins. We see that at the intersection of FB#1
and the PA07 Aol curves the rate of closure is 40 dB per
decade indicating marginal stability.
STEP 3: Refer to Figure 19 which repeats PA07 Aol and FB#1.
We will add FB #2 to force the high frequency part of the
1/ curve to fatten out and intersect the PA07 Aol curve
at 20 dB per decade. FB #2 will dominate at frequencies
above 1 KHz. Although our V-I circuit has two feedback
paths, the op amp will follow whichever feedback path is
dominant. This means the larger is, the more voltage
is fed back from the output to the -input as negative feed-
back (Remember = Vfb/V
OUT
). With a larger , 1/ will
FIGURE 17. Aol AND FB # 1 MAGNITUDE PLOT FOR STABILITY
.1 1 10 100 1K 10K 100K 1M 10M 100M
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY, F (Hz)
G
A
I
N

(
d
B
)
220
PA07 Aol
fz
FB#1
fp3 3p
fp2
fp1
FIGURE 18. FEEDBACK NO.1 (FB #1)
RI
4.99K
V
OUT
9
RL
1.2
Rs
1K
RF
Vfb
(.098)
=
Vfb
V
OUT
= .098 1/ = 10.2 20dB
fz =
Rs+ RL
2
=
1.2 + 9
2 159mH
= 10.2Hz
FB #1 DC

( LL = 0, Cf = )
LL
(1)
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become smaller; therefore, the dominant feedback path
out of FB#1 and FB#2 will be the lowest gain path.
Plot a desired feedback path for FB#2. At high fre-
quencies, FB#2 will be a fat line since Cf will be a short
leaving a pure resistive divider for . At DC, FB#2 will
be infnite since Cf is an open. This will be limited by the
PA07 Aol curve. Since we only have one reactive element
in FB#2, we will have a 20 dB per decade slope from low
to high frequency. Set fz1 one half to one decade below
the intersection of FB#1 and FB#2. This Decade rule of
thumb ensures that as component values and Aol curves
vary we will not get into stability troublemore about this
later.
STEP 4: In Figure 19 the long-dashed line represents the 1/
feedback path that the PA07 operates in for small signal
AC. According to our frst order check for stability we see
a 20 dB per decade rate of closure indicating a stable
design. But lets do our complete stability check by using
the 1/ curve and PA07 Aol curve to plot the open loop
phase plot. Remember the following rules when plotting
open loop phase plots for stability checks.

RULES FOR PLOTTING OPEN LOOP PHASE PLOTS
1) Poles in 1/ plot become zeroes in the open loop
stability check.
2) Zeroes in 1/ plot become poles in the open loop
stability check.
3) Poles and zeroes in the Aol curve of the op amp remain
respectively poles and zeroes in the open loop stability
check since the op amp Aol curve is an open loop curve
already.
4) Phase for poles is represented by a -45 degree phase
shift at the frequency of the pole with a -45 degree per
decade slope, extending this line with 0 degree and -90
degree horizontal lines.
5) Phase for zeroes is represented by a +45 degree phase
shift at the frequency of the zero with a +45 degree per
FIGURE 20. FIRST GUESS OPEN LOOP PHASE PLOT FOR STABILITY
P
H
A
S
E

S
H
I
F
T

(
d
e
g
r
e
e
s
)
FREQUENCY, F (Hz)
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
MARGIN = 0 DEGREES
fp
fp1
fz
fp3
fp2
FIGURE 19. FIRST GUESS MAGNITUDE PLOT FOR STABILITY
.1 1 10 100 1K 10K 100K 1M 10M 100M
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY, F (Hz)
G
A
I
N

(
d
B
)
220
1/
FB#1
250
FB#2
fp1
fz1
3p fp3
fp2
fp
PA07 Aol
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decade slope, extending this line with 0 degree and +90
degree horizontal lines.
Figure 20 is the resultant open loop phase plot using
the information from Figure 19. After plotting individual
open loop poles and zeroes, and drawing the appropriate
slopes, we graphically add the slopes to yield a resultant
open loop phase as shown in Figure 20. Notice fp3 in
Figure 20 is a triple pole. It is easier to plot this as shown
in Figure 20 as three poles on top of each other. This
FIGURE 21. FINAL VALUE MAGNITUDE PLOT FOR STABILITY
.1 1 10 100 1K 10K 100K 1M 10M 100M
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY, F (Hz)
G
A
I
N

(
d
B
)
220
1/
FB#1
250
FB#2
fp1
fp
fz1
fz
3p fp3
fp2 31.6
PA07 Aol
fcl
P
H
A
S
E

S
H
I
F
T

(
d
e
g
r
e
e
s
)
FREQUENCY, F (Hz)
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
fz
fp3
fp2
fp
ADD ZERO FOR 45 f MARGIN
MARGIN = 45
fcl
fp1
FIGURE 22. FINAL VALUE OPEN LOOP PHASE PLOT FOR STABILITY
makes it easier to add graphically for a resultant open loop
phase plot. As shown in Figure 20, our open loop phase
dips to -180 at 100Hz. Our frst attempt at compensation
was not successful since we desire at least 45 degrees
of phase margin (open loop phase should not dip to less
than -135 degrees).
STEP 5: We need to revisit FB#2 to make this V-I circuit stable.
Figure 21 shows a new FB#2 and the resultant 1/ plot.
Before we look at the open loop phase plot, lets discuss
Figure 21. We see that in the PA07 Aol curve there is a
pole at fp1, 10Hz, which will be a pole in our open loop
phase plot. We also see a zero at fz, 10Hz, in the 1/
plot, which will become a pole in our open loop phase
plot. Now we have two poles at 10Hz in our open loop
phase plot. To keep the open loop phase from reaching
-180, we must add a zero at 100Hz to get 45 degrees of
phase margin. Poles and zeroes a decade beyond fcl,
the intersection of 1/ and PA07 Aol, are of no concern
for stability since at fcl the loop gain is zero. The reason
we must look a decade beyond fcl on the magnitude plot
is that poles and zeroes have an effect on phase plus or
minus a decade away from their physical location on the
magnitude plot.
Viewing the magnitude plot in this way can help us save
iterative steps in compensating to guarantee good stability.
Refer to Figure 22 for fnal open loop phase plot stability.
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Once the open loop phase plot verifes stability, it is time
to compute fnal values for FB#2 components Rd and Cf.
Figure 23 (next page) details these calculations. Notice
in Figure 23 that to work with it is easiest to set Vout
to 1 which then allows us to easily use voltage dividers
and currents to calculate values for Rd. Cf is computed
as given by the formula in Figure 23.
OPEN LOOP PHASE PLOTS FOR STABILITY FINAL
NOTE:
This hand plotting technique is a linear graphical method.
Actual magnitude plots run on such analog circuit simulations
as SPICE will be 3 dB different and actual phase plots will be
6 degrees different.
5.2 CAPACITIVE LOADING & STABILITY
* fosc < CLBW
* oscillates with V
IN
= 0?yes
5.2.1 CAPACITIVE LOADING - GENERAL
Refer to Figure 24 (next page) for discussion of power op
amps and capacitive loading. The output impedance of a
power op amp, Ro, can interact with capacitive loads and form
an additional high frequency pole in the op amps Aol curve.
This modifed Aol curve is what we must look at for stability
checks. In Figure 24, we see a modifed Aol curve whose slope
changes from 20 dB per decade to 40 dB per decade at 10
kHz. Note that the rate of closure for this circuit is 40 dB per
decade indicating marginal stability.

5.2.2 CABLE AND CAPACITIVE LOADING
Beware of coaxial cables which can appear capacitive. A
coaxial cable appears capacitive, instead of its characteristic
impedance, resistive, if the length of the cable is less than
one-fortieth of the wavelength in the cable at the frequency of
interest, f. This length, l, is given by:
where K is a propagation constant that is sometimes called
the velocity factor (0.66 for coaxial cable) and c is the velocity
of light (3.00 X10
8
m/s).
EXAMPLE: If f = 10KHz:
Cables less than 495 meters will appear capacitive for 10 kHz
signals at the rate of 95 pF/meter (29 pF/foot) for RG-58A/U,
a commonly used coaxial cable.
5.2.3 AMPLIFIER OUTPUT IMPEDANCE, RO
AND CAPACITIVE LOADING
In the design of power amp circuits, the need often arises
for a power amp model with specifed output impedance. Most
often, this requirement revolves around the need to accurately
predict the phase performance of power amp circuits.
Output impedance of any op amp is modifed by the feed-
back network present around the device. In voltage source
type circuits, the effect of the network is to reduce the output
impedance by a factor equal to the ratio of open loop gain to
closed loop gain. In power amps, the net result is an effective
output impedance of milliohm levels at frequencies below 1kHz.
Wiring and interconnections often create larger impedances
than the output impedance of the closed loop power amp.
meters l
1 Kc
40 f
l
1 (0.66) (3x10
8
)
40 10
4
= 495 meters (1624 feet)
FIGURE 23. FEEDBACK NO. 2 (FB #2) FINAL VALUE CALCULATIONS
RI
4.99K
V
OUT
(1)
Rd
1.2
Rs
Vfb
Ifb =
FB #2 HI f

( CF

= 0, LL= )
1K
RF
(.01)
Ifb
1/ = 40dB = 100 = .01
RI

// RF 833
Vfb / (RI

// RF) = .01/833 = .12mA
R
T
= V
OUT
/ Ifb = 1/.012mA = 83.3K
(R
I
// R
F
) = 83.3K 833 82.5K
USE 82.5K
Rd R
T

fz1 =
1
2 Rd Cf
= 31.6Hz
NOTE: AVOID DOUBLE POLE IN
1/ PLOT AT FR COMPLEX POLES IN
OPEN LOOP STABILITY 180
PHASE SHIFT AT FR.
FREQUENCY, F(Hz)
G
A
I
N

(
d
B
)
1/
FB #2 FB #1
Cf

= .068F
FR
Aol
FIGURE 24. CAPACITIVE LOADING
10 100 1K 10K .1M
100
80
60
40
100
0
FREQUENCY, F (Hz)
1M 10M
120
O
P
E
N

L
O
O
P

G
A
I
N

A
O
L

(
d
B
)

1
20
UNSTABLE
STABLE
RF
RI
CL
UNITY GAIN STABLE AMPLIFIER
BUT: UNSTABLE 40 dB/DECADE WITH CL
1/ Aol
Aol

WITH CL

AV
CL
Ro
AN19
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Therefore, output impedance will play a minor role in the phase
performance at low frequencies. At high frequencies, reactive
load considerations are already addressed by capacitive load
specifcations given on many power amplifers.
Within the bandwidth of the amplifer the output impedance of
most Apex Precision Power power op amps appears predomi-
nantly resistive. As an output stage drives higher currents, its
output impedance changes when compared to the low current
or unloaded output impedance. In general, this impedance
reduces as current is driven through the output stage.
When compensating circuits with capacitive loading we will
use the low current or unloaded output impedance for Ro. This
will be the highest value of Ro causing the lowest frequency
additional pole which modifes an amplifers Aol curve when
driving a capacitive load. Many designs in the past have verifed
that compensating for this condition will give the best stability
for all conditions when driving capacitive loads.
The following is a list of output impedances for Apex Preci-
sion Power power op amps and boosters.
OP AMP OR BOOSTER . . . . OUTPUT IMPEDANCE
PA01 . . . . . . . . . . . . . . . . . . . . 2.5-8.0 ohms
PA02 . . . . . . . . . . . . . . . . . . . . 10-15 ohms
PA03 . . . . . . . . . . . . . . . . . . . . 25 ohms
PA04 . . . . . . . . . . . . . . . . . . . . 2.0 ohms
PA05 . . . . . . . . . . . . . . . . . . . . 5 ohms
PA07 . . . . . . . . . . . . . . . . . . . . 1.5-3.0 ohms
PA08 . . . . . . . . . . . . . . . . . . . . 1.5K-1.9K ohms
PA09 . . . . . . . . . . . . . . . . . . . . 15-19 ohms
PA10 . . . . . . . . . . . . . . . . . . . . 2.5-8.0 ohms
PA12 . . . . . . . . . . . . . . . . . . . . 2.5-8.0 ohms
PA19 . . . . . . . . . . . . . . . . . . . . 30-40 ohms
PA51 . . . . . . . . . . . . . . . . . . . . 1.5-1.8 ohms
PA61 . . . . . . . . . . . . . . . . . . . . 1.5-1.8 ohms
PA73 . . . . . . . . . . . . . . . . . . . . 1.5-1.8 ohms
PA81J . . . . . . . . . . . . . . . . . . . 1.4K-1.8K ohms
PA82J . . . . . . . . . . . . . . . . . . . 1.4K-1.8K ohms
PA83 . . . . . . . . . . . . . . . . . . . . 1.4K-1.8K ohms
PA84 . . . . . . . . . . . . . . . . . . . . 1.4K-1.8K ohms
PA85 . . . . . . . . . . . . . . . . . . . . 50 ohms
PA88 . . . . . . . . . . . . . . . . . . . . 100 ohms
PA89 . . . . . . . . . . . . . . . . . . . . 100 ohms
PB50 . . . . . . . . . . . . . . . . . . . . 35 ohms
PB58 . . . . . . . . . . . . . . . . . . . . 35 ohms
5.2.4 COMPENSATING CAPACITIVE LOADS
There are two main ways to compensate for capacitive loads
or two pole Aol curves. The Feedback Zero and Noise Gain
or Input R-C Network compensation techniques for capacitive
loads will both be discussed.
The Feedback Zero technique uses a pole in the 1/ plot
(a zero in the open loop phase check for stability or a zero
in the Aol , loop gain, plot) to compensate for the additional
pole due to capacitive loading in the amplifers modifed Aol
curve. Refer to Figure 25. Note that in Curve 1 there is both a
pole and zero in this 1/ plot. The pole is due to the interaction
of Rf and Cf. The zero can be found by graphically extending
the 1/ plot to zero dB. Remember from previous discussion
that an op amp cannot operate at a gain of less than 1 for
small signal AC.
The Noise Gain compensation technique raises the small
signal AC gain of the amplifer to run at a gain that is high
enough to ignore the additional high frequency pole in the Aol
curve due to capacitive loading. Refer to Figure 25. Curve 2
shows the 1/ plot for noise gain compensation.
Notice in Figure 25 that both Curve 1 and Curve 2 yield a 20
dB per decade rate of closure implying stability; whereas, with
just resistive feedback at the given gains the circuits would be
unstable with a 40 dB per decade rate of closure.
5.2.4.1 FEEDBACK ZERO COMPENSATION
Figure 26 illustrates a circuit utilizing Feedback Zero Com-
pensation for stability when driving a capacitive load. Figure
27 is our magnitude plot to work with for stability. The following
procedure will ensure a logical approach to optimize stability:
FIGURE 25. CAPACITIVE LOAD COMPENSATION
10 100 1K 10K .1M
100
80
60
40
100
0
FREQUENCY, F (Hz)
1M 10M
120
O
P
E
N

L
O
O
P

G
A
I
N

A
O
L

(
d
B
)
1
20
RF
RI
CL
FEEDBACK ZERO COMPENSATION
RF
RI
CL
Cn
Rn
2
1
2 1
w/CL w/o CL
CF
1/
NOISE GAIN COMPENSATION
Aol
1/
fp2 =
1
2 Ro CL
=
1
2 100 159nF
= 10 kHz
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fcl such that if the modifed Aol plot in the real world
moves to the left towards lower frequency we will
not be back at a 40 dB per decade rate of closure.
Note in Figure 27 that the 1/ plot has fp5 and fz1.
The feedback network continues to feed back output
voltage beyond fcl until we reach 0 dB. Then the 1/
plot fattens out at 0 dB. It is important to include fz1
since it will be a pole in our open loop phase check
STEP 1: Modify the PA88 Aol due to CL. Here we use the
output impedance number for the PA88 of Ro = 100
ohms.
The higher frequency poles of the unmodifed PA88
Aol must be added into the modifed Aol as shown
in Figure 26.
STEP 2: Calculate DC for circuit.
DC = RI/(RF + RI) = 10K/(316K+10K) = .030674846
DC 1/ = 20 Log (1/.030674846) = 30.26 dB
STEP 3: Plot DC 1/. Add pole in 1/ plot to compensate for
fp2. Ensure fp5 is one-half to one decade away from

RF

RI

Cc

+225V
10K

225V
316K

R
CL
6.5

3.3pF

CL

159nF

CF

47pF
FIGURE 26. FEEDBACK ZERO COMPENSATION FOR CL
PA88
V
IN
FIGURE 27. FEEDBACK ZERO COMPENSATION FOR CL
MAGNITUDE PLOT FOR STABILITY
.1 1 10 100 1K 10K 100K 1M 10M 100M
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY, F (Hz)
G
A
I
N

(
d
B
)

220
fp2
fp5
fp1
dp V
O
/ V
IN

PA88 w/Cc = 3.3pF
1/ fcl
fp4
fdp3
MODIFIED Aol : R
O
= 100 , CL = 159nF
fz1
FIGURE 28. FEEDBACK ZERO COMPENSATION FOR CL OPEN LOOP PHASE PLOT FOR STABILITY
P
H
A
S
E

S
H
I
F
T

(
d
e
g
r
e
e
s
)

FREQUENCY, F (Hz)
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
fdp3
fp1
fp4
fz1 fp2
fp5
MARGIN = 67 fcl
AN19
744 AN19U
and will affect phase at frequencies lower than fcl. At
fcl loop gain is zero and beyond fcl we are not con-
cerned with phase shift to guarantee stability. Note
that the V
O
/V
IN
plot follows the 1/ plot until at which
point there is no loop gain and V
O
/V
IN
will follow the
Aol curve on down in gain.
STEP 4: Plot open loop phase as in Figure 28. We see we
have 67 degrees of phase margin and therefore
guaranteed stability.
STEP 5: Once you have chosen CF to get the fp5 you want
you automatically set fz1. fz1 can be gotten graphi-
cally from the 1/ plot. For those of you who want
exact breakpoints, here are the formulae for the 1/
plot in Figure 27.
5.2.4.2 NOISE GAIN COMPENSATION
Figure 29 illustrates how Noise Gain compensation works.
One way to view noise gain circuits is to treat the amplifer
as a summing amplifer. There are two input signals into this
inverting summing amplifer. One is V
IN
and the other is a noise
source summed in via ground through the series combination
of Rn and Cn. Since this is a summing amplifer, V
O
/V
IN
will be
unaffected if we sum zero into the Rn-Cn network. However, in
the small signal AC domain, we will be changing the 1/ plot
of the feedback as when Cn becomes a short and if Rn << RI
the gain will be set by RF/Rn. Figure 29 shows the equivalent
circuits for AC small signal analysis at low and high frequencies.
Notice in Figure 29 that the V
O
/V
IN
relationship is fat until
the Noise Gain forces the loop gain to zero. At that point, fcl,
the V
O
/V
IN
curve follows the Aol curve since loop gain is gone
to zero. Since noise gain introduces a pole and a zero in the
1/ plot, here are a few tips to keep phase under control for
guaranteed stability. Keep the high frequency fat part of the
noise gain no higher in magnitude than 20 dB greater than the
low frequency gain. This will force fp and fz in Figure 29 to be
no more than a decade apart. This will also keep the phase
from dipping to -135 since there is usually an additional low
frequency pole due to the amplifers Aol already contributing
an additional -90 degrees in the open loop phase plot. Keep fp
one half to one decade below fcl to prevent a rate of closure of
40 dB per decade and prevent instability if the Aol curve shifts
to the left which can happen in the real world.
Usually one selects the high frequency gain and sets fp.
fz can be gotten graphically from the 1/ plot. Once again
for completeness, here are the formulae for noise gain poles
and zeroes:
Figure 30 illustrates a circuit utilizing noise gain compensa-
tion for stability when driving a capacitive load. Figure 31 is
our magnitude plot to work with for stability.
The following procedure will ensure a logical approach to
optimize stability:
fp =
1
2 Rn Cn
fz =
RF + RI
(2) (Cn) (RFRI + RFRn + RIRn)
fp2 =
1
2 Ro CL
=
1
2 100 159nF
= 10KHz
V
OUT
V
IN
RF
RI
1/ LOW f
Rn
Cn
V
OUT
FIGURE 29. NOISE-GAIN COMPENSATION
V
OUT
1/ HIGH f (Rn < .1RI)
10 100 1K 10K .1M
100
80
60
40
100
0
FREQUENCY, F (Hz)
1M 10M
120
O
P
E
N

L
O
O
P

G
A
I
N

A
o
l

(
d
B
)
RF/Rn
fp
fcl
RF/RI fz
1/
V
O
/V
IN
1
V
OUT
20
Aol
NOISE GAIN COMPENSATION
RF
Rn
Cn
RF
RI
Rn
Cn

RF

RI

Cc

+225V
1K

225V
274K

R
CL
6.5

3.3pF

CL

159nF
FIGURE 30. NOISE GAIN COMPENSATION FOR CL

V
O
PA88

Cn
274

.56F

Rn

V
IN
fp5 =
1
2 RF CF
fz1 =
RI + RF
2 CF RI RF
AN19
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A
STEP 1: Modify the PA88 Aol due to CL. Here we use the
output impedance number for the PA88 of Ro = 100 ohms.
The higher frequency poles of the unmodifed PA88 Aol
must be added into the modifed Aol as shown in Figure
31.
STEP 2: Calculate DC for circuit, Cn is an open for DC.
DC = RI/(RF+RI) = 1K/(274K+1K) = .003636363
DC 1/ = 20 Log (1/.03636363) = 48.79 dB
FIGURE 31. NOISE GAIN COMPENSATION
MAGNITUDE PLOT FOR STABILITY
.1 1 10 100 1K 10K 1M 10M 100M
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY, F (Hz)
G
A
I
N

(
d
B
)

220
fp1
dp
V
O
/ V
IN

PA88 Aol w/Cc = 3.3pF
1/
fcl
fdp3
fp
fz
100K
fp2
fp4
STEP 3: Plot DC 1/. Add noise gain compensation using
the hints given above. Things look okay. We have 20 dB
per decade rate of closure. fp is a decade away from fcl.
High frequency 1/ is less than 20 dB greater than low
frequency 1/, and fz is less than a decade spaced from
fp.
STEP 4: Plot open loop phase plot as in Figure 32 from the
information given in Figure 31. We see from this plot we
have 45 degrees of phase margin.
5.3 COMPOSITE AMPLIFIER & STABILITY
There are design cases where the input characteristics of a
power op amp may not be sufficient to meet required specifca-
tions. In these cases one can still have the advantages of using
the power op amp for linear analog control, but can optimize
the front end of the circuit to meet the required specifcations.
A composite amplifer such as Figure 33 (see following page)
will provide a highly accurate 75uV input offset voltage versus
the 40 mV input offset voltage of the PA241. In the composite
amplifer, the PA241 acts as a booster running in a closed loop
gain of 11. The PA241 booster and the OP07 form a new
composite amplifer with the feedback from output all the way
back to the input of the OP07.
The application in Figure 33 (next page) provides an excellent
opportunity for us to utilize our knowledge of stabilizing circuits
with capacitive loads, as well as acquire new techniques for
dealing with stability and composite amplifers.
FIGURE 32. NOISE GAIN COMPENSATION OPEN LOOP PHASE PLOT FOR STABILITY
P
H
A
S
E

S
H
I
F
T

(
d
e
g
r
e
e
s
)
FREQUENCY, F (Hz)
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
fdp3
fp1
fp4
fp2
fp
MARGIN = 45
fz
fcl
AN19
746 AN19U
The following steps will provide a simple, logical approach
to attacking composite amplifer stability problems:
STEP 1: Given specifcations:
V
IN
= 2.5 VOLTS
DC fn 1.6 KHz
CL = .1F
V
OUT
= /+ 40 VOLTS
15 Volts available in system
Input offset voltage 100V
STEP 2: From given specifcations determine maximum slew
rate needed to track highest frequency output.
S.R. [V/s] = 2()f Vopk (1x106)
S.R. = 2() (1.6K) 40V (1x106) = .4V/s
STEP 3: From calculated slew rate and given CL, determine
current needed to drive capacitive load.
I = C dV/dt
I = .1F (.4V/s) = 40mA
STEP 4: Select power op amp and host amplifer.
PA240 is the lowest cost power op amp with 40mA of
output capability; a slew rate of 20V/us, with Cc=15pF,
and Vsat of 12V at 40mA out. PA241 is the same
monolithic chip, but in a package with enough pins
for programmable current limit. In this application,
fault tolerance afforded by having current limit justifes
the additional cost of the PA241.
OP07 will provide 75V of input offset voltage; a
slew rate of .17 V/s; and an output voltage swing of
+/-12V from +/-15V supplies. The maximum output
voltage swing of the host times the booster gain
must meet the desired output voltage swing. Here
there is no problem since +/-12V out of OP07 times
11 (booster gain) will yield potential for +/-120V out
of the composite amplifer confguration.
The slew rate of the host amplifer times the booster
gain should be less than or equal to the booster slew
rate. If it is greater than the booster slew rate, the host
FIGURE 33. PA241 COMPOSITE PIEZO TRANSDUCER DRIVE
15
+40V
40V
V
OUT
1.6KHz
22pF
CF
+60V
RF
340K
.1F
R
CL
PA241
Cc
15pF 60V
.1F
CL
.1F
RI
34K
+15V
15V
340K
RFC
22pF
CFC
+15V
.1F
15V
.1F
RIC
21K
V
IN
2.5V
Rn
3.4K
Cn
10nF
ALL DIODES 1N41481
OP07
amplifer can outrun the booster during high slew rate
demands and consequently the composite amplifer
will be running open loop and hence non-linearities
and distortion will be uncontrolled.
Host S.R. x Booster Gain = .17/s x 11 = 1.87V/s
1.87V/s < 20V/s (Booster S.R.)
We will run the booster amplifer in a closed loop
gain of 11 as shown in Figure 33 to allow more margin
to work with when compensating the capacitive load.
We know this from experience in designing many
power op amp circuits with capacitive loads on the
output.
STEP 5: The booster stage of the composite must be stable
before we consider the overall composite amplifer.
Booster circuit data was entered into the Cload sheet
of the Apex Precision Power Power Design spread-
sheet. Initial indications were an intersection rate of
40dB per decade and a phase margin of only 19.
Figure 34 shows Power Design has already added the
150 amplifer output impedance to the 15 current
limit resistor and calculated the pole with the capaci-
tive load to be at 9.6KHz. The booster stage was
compensated with Cf producing a closed loop pole
(a feedback zero) at 21.3KHz. Do not be confused
by sub-Hertz or multi-GHz entries in the table; these
show up because the spreadsheet avoids division
by zero errors by forcing extremely small values for
non-existent capacitors. Refer to Figure 35 to see
phase contributions of all elements added, closure
frequency of 75KHz, closure rate of 20dB per decade,
and a phase margin of 52.
STEP 6: We are now ready to enter the composite circuit
data as shown in Figure 36 (next page). Note that
the closed loop gain of the booster stage has been
added to the Aol of the OP07. Closure rate is 60dB
per decade and we have a guaranteed oscillator.
An attempt to compensate with just CFC was made,
but was not good enough. A better compensation
AN19
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technique will use noise gain to raise the 1/ curve
to 41.4dB and then use CFC to obtain an intersection
with the composite Aol of 20dB per decade.
STEP 7: Figure 37 (next page) shows the effect of adding our
stabilization components. We have achieved the
desired intersection rate of 20dB per decade. Note
that the output signal does not rise at 686Hz when
the noise gain kicks in, but does begin to roll off at
21.3KHz due to the 22pF roll off capacitor.
Once again our fnal stability check is completed by the
open loop phase plot for the composite amplifer as shown
in Figure 38 (next page). The resultant 50 degrees of phase
margin guarantees a stable composite amplifer confguration.
P.S. Refer to Figure 33. The 1N4148-1 diodes on the input
of the OP07 provide differential and common mode overvolt-
age protection from transients through CFC. Piezo elements
being electromechanical devices can generate high voltages
if shocked mechanically. Output diodes of the OP07 prevent
overvoltage transients that occur through CF and shunted
through PA241 internal input protection diodes, from damaging
the output of the OP07 connected to +input of PA241.
6.0 REAL WORLD STABILITY TESTS
We have devoted much text to discussing how to design
stable circuits. Once a circuit is designed and built it is often
difficult to open the feedback path in the real world and measure
open loop phase margin for stability.
The following Real World Stability Tests offer methods to
verify if predicted open loop phase margins actually make it
to the real world implementation of the design. Although the
curves shown for these tests are only exact for a second order
system, they provide a good source of data since most power
Bode Plot
-20
0
20
40
60
80
100
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Frequency, Hz
G
a
i
n
,

d
B
MODEL PA241,3-150 Note/PBs Rn 9999999999 Kohms
Rcl 15 Ohms Cn 0 nF
Cload 0.1 uF Cf 22 pF
Rin 34 Kohms Riso 0 Ohms
Rf 340 Kohms
Total Rout 165 Ohms
Pole Zout/Cload 9.645744481 KHz
1/Beta (DC) 20.8 dB
Noise Gain 0.0 dB
Pole Noise Gain 0.159154943 KHz
Zero Noise Gain 0.159154938 KHz
Pole Cf/Rf 21.27739784 KHz
Zero Rf/Cf 234.051377 KHz
Zero Riso/Cload 1.59155E+11 KHz
Aol
Aol/Cload
1/eta
Acl
Fcl
FIGURE 34.
Estimated Closure Frequency = 74.98942 KHz
Suggested maximum bandwidth 11.54782 KHz
Estimated Closure Rate = 20.0 dB/decade
Estimated Phase Margin = 51.78278 Degrees
Phase Shift Components
-180
-135
-90
-45
0
45
90
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Frequency, Hz
P
h
a
s
e

S
h
i
f
t
,

D
e
g
r
e
e
s
OPEN LOOP
POLE 1
Cf ROLL OFF
Cl & Zout
ROLL OFF HITS 0dB
POLE 2
POLE 3
FIGURE 35.
MODEL OP07 READ ME
Aol = 135 dB Pole 1 = 0.1 Hz
Pole 2 = 7.00E+05 Hz Pole 3 = 7.00E+06 Hz
Rin 21 Kohms Rn 999999999 Kohms
Rf 340 Kohms Cn 0 nF
Cf 0 pF Using Look-Up data
Bode Plot
-20
0
20
40
60
80
100
120
140
160
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Frequency, Hz
G
a
i
n
,

d
B
Fcl
Aol Host
Aol Composite
1/eta
FIGURE 36.
MODEL OP07 READ ME
Aol = 135 dB Pole 1 = 0.1 Hz
Pole 2 = 7.00E+05 Hz Pole 3 = 7.00E+06 Hz
Rin 21 Kohms 3.4 Kohms
Rn
1/Beta (DC) 24.7 dB
Noise Gain 16.7 dB
Bode Plot
-20
0
20
40
60
80
100
120
140
160
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Frequency, Hz
G
a
i
n
,

d
B
Aol Host
Aol Composite
1/eta
Acl
Fcl
FIGURE 37.
AN19
748 AN19U
of the square wave is adjusted to be 2 Vpp at a frequency of
1 kHz. The key elements of this test are to use low amplitude
(AC small signal) and a frequency that will allow ease of read-
ing when triggered on an oscilloscope. Amplitude adjustment
on the oscilloscope wants to accentuate the top of the square
wave to measure easily the overshoot and ringing. The results
of the test can be compared to the graph in Figure 40 to yield
open loop phase margin.
A complete use of this test is to run the output symmetrical
about zero with +/-1V peak and then re-run the test with various
DC offsets on the output above and below zero. This will check
stability at several operating points to ensure no anomalies
show up in feld use.
op amp circuits possess a dominant pair of poles that will be
the controlling factor in system response.

6.1 AVCL PEAKING TEST
Figure 39 illustrates the AVcl Peaking Test for measuring
open loop phase margin in the real world closed loop domain.
From the closed loop Bode plot, we can measure the peaking
in the region of gain roll-off. This will directly correlate to open
loop phase margin as shown.
6.2 SQUARE WAVE TEST
Figure 40 illustrates the Square Wave Test for measuring open
loop phase margin by closed loop tests. The output amplitude
V
OUT
FIGURE 40. SQUARE WAVE TEST
RF RI
2 1 4 3 6 5 8 7 0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
V
O
,

R
E
L
A
T
I
V
E

O
U
T
P
U
T

T
O

A

S
T
E
P

F
U
N
C
T
I
O
N

I
N
P
U
T
9 10
LOAD
CF
2vpp
1KHz
13 0.2*
35 0.4*
40 0.6*
90 1.4*
64 1.0*
52 0.8*
77 1.2*
V
IN
* OPEN LOOP PHASE MARGIN AND DAMPING FACTOR
n
t
-180
-135
-90
-45
0
45
90
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Frequency, Hz
P
h
a
s
e

S
h
i
f
t
,

D
e
g
r
e
e
s
OPEN LOOP
NOISE GAIN
HOST Cf
BOOSTER Fcl
BOOSTER Cf
POLE 2
BOOSTER POLE 2
POLE 3
ROLL OFF HITS 0dB
FIGURE 38:
FIGURE 39. AV
CL
PEAKING TEST
10
20
30
40
0
0
O
P
E
N

L
O
O
P

P
H
A
S
E

M
A
R
G
I
N

(
d
e
g
r
e
e
s
)

RF
V
IN
V
O
RI
LOAD
CF
AV
CL
=
V
O
V
IN
50
5 10 15 20 25
PEAKING (dB)
PEAKING

A
V
C
L

(
d
B
)

PEAKING MEASURED CLOSED LOOP
f
AN19
AN19U 749
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
6.3 DYNAMIC STABILITY TEST
An expansion on the Square Wave Test is shown in Fig-
ure 41(see second page following this one). The Dynamic
Stability Test superimposes a small signal AC square wave
on a low frequency, large signal AC sinewave to dynami-
cally test the power op amp circuit under all operating point
conditions. The resultant ringing on the square wave can
be compared to the graph in Figure 40 for relation to open
loop phase margin. Note that R1 // R2 in Figure 41 must
be much greater than RIN or the input summing test imped-
ances will affect the compensation of the power op amp
circuit under test.
7.0 STABILITY TROUBLESHOOTING GUIDE
Figure 42 (see third page following this one) provides a
troubleshooting guide for the most common stability prob-
lems. The Probable Cause/Possible Solution Key gives
insight into the origin of the problem and provides guidance
as to the appropriate fx.

8.0 FINAL STABILITY NOTE
When youre at your wits end trying to solve an oscil-
lation problem, dont give up because you have it down
to an acceptably low level. A circuit either oscillates or it
doesnt, and no amount of oscillation is acceptable. Apply
the techniques and ideas in this Application Note under
your worst case load conditions and you can conquer your
oscillation problems.
If time is short or you cant see the forest from the trees,
Apex Precision Power would be happy to provide Technical
Support via Design Support Request, (800) 625-4084. More
importantly, as we tell all our customers, we would be happy
to review your schematic for stability considerations, etc.,
before you ever build a circuit or even buy a power op amp.
FIGURE 41. DYNAMIC STABILITY TEST
RF
V
IN
R1
LOAD
CF
RI
V
O

+ V
S
V
S
R2
ADDED FOR STABILITY TESTING
f = 10Hz
+
+
(V
IN
TO SWEEP V
O
)
(V
IN
FOR 100 mV V
O
)
f = 10KHz
R1//R2 > R
IN
0
100mV p-p SQUARE WAVE
DRAWN OUT OF SCALE FOR
CLARITY
V
O
+Vs
t
Vs
Oscillates unloaded?
Oscillates with V
IN
= 0?
Loop Check
fixes oscillation?
Oscillation
Frequency
Probable Cause(s)
(in order of probability)
fosc UGBW N Y N C, D
fosc CLBW Y Y Y K, E, F, J
fosc UGBW N G, A, M, B
fosc CLBW N Y Y D
fosc UGBW Y Y N* J, C
fosc CLBW Y Y N L, C
fosc > UGBW N Y N B, A
fosc > UGBW N N** N A, B, I, H
CONDITION AND PROBABLE CAUSE TABLE
FIGURE 42. STABILITY TROUBLESHOOTING GUIDE
CLBW = Closed Loop Bandwidth
UGBW = Unity Gain Bandwidth
See Figure 42A for loop check circuit.
Indeterminate; may or may not make a difference.
*Loop check (Figure 42A) will stop oscillation if Rn << |X
CF
|
at UGBW.
**Only oscillates over a portion of the output cycle.
KEY TO PROBABLE CAUSE / POSSI BLE SOLUTI ON
A. Cause: Supply feedback loop (insufficient supply bypassing).
B. Cause: Supply lead inductance.
C. Cause: Ground loops.
Solution: Use St ar grounding. See Figure 9.
D. Cause: Capacitive load reacting with output impedance (Aol pole).
Solution: Raise gain or use Noise Gain Compensation network.
See section 5.2.4.2.
E . Cause: Inductor within the feedback loop (loop gain pole) .
Solution: Use alternate feedback path. See section 5.1.
F . Cause: Input capacitance reacting with high RF (noise gain zero).
Solution: Use CF in parallel with RF. (CF =~Cin). Do not use
toomuch CF, or you may get problem J.
G. Cause: Output to input coupling.
Solution: Run output traces away from input traces, ground the
case, bypass or eliminate +RB (the bias current
compensation resistor from +IN to ground)
H. Cause: Emitter follower output reacting with capacitive load.
Solution: Use output snubber network. See Section 2.5.
I . Cause: Composi t e PNP output stage with reactive load.
Solution: Use output snubber network. See Section 2.5.
J . Cause: Feedback capacitance around amplifier that is not
unity gain stable (integrator instability).
Solution: Reduce CF and/or increase Cc for unity gain stability.
K. Cause: Insufficient compensation capacitance for closed loop
gain used.
Solution: Increase Cc or increase gain and/or use Noise Gain
Compensation network. See section 5.2.4.2.
L. Cause: Servo loop stability problem.
Solution: Compensate the front end or servo ampl i fi er.
M. Cause: Unwanted signals coupling into op amp through case.
Solution: Ground the case.
V
IN
V
O
+V
S
V
S
Rn
RI RF
Rn
RF
100
FIGURE 42A. LOOP CHECK CIRCUIT
AN19
750 AN19U
9.0 REFERENCES
1) Frederiksen, Thomas M. : INTUITIVE IC OP AMPS, R.R.
Donnelley & Sons, 1984.
2) Huelsman, Lawrence P. : BASIC CIRCUIT THEORY WITH
DIGITAL COMPUTATIONS, Prentice-Hall, Inc., Englewood
Cliffs, N.J., 1972.
3) Faulkenberry, Luces M. : AN INTRODUCTION TO OPERA-
TIONAL AMPLIFIERS WITH LINEAR IC APPLICATIONS,
John Wiley & Sons, New York, 1982.
4) Dorf, Richard C. : MODERN CONTROL SYSTEMS (Third
Edition), Addison-Wesley Publishing Company, Reading,
Massachusetts, 1980.
10.0 APPENDIX
This appendix contains some handy tools for plotting mag-
nitude and phase plots for stability analyses. The Log Scaling
Technique covers an easy way to read exact frequency locations
of poles and zeroes from magnitude plots for stability. Included,
as well, are blank magnitude and phase plots for copying and
using to plot phase and magnitude plots for stability.
One fnal tip. Once a magnitude plot has been plotted con-
taining the Aol curve and 1/, it is easy to translate the poles
and zeroes to an open loop phase plot for stability. Simply use
a light table (ours is very basic a piece of plexiglass that fts
over a 60W incandescent desk light !) to trace the locations of
poles and zeroes. Remember poles and zeroes in the Aol curve
are poles and zeroes in the open loop phase check for stability.
But poles in the 1/ plot become zeroes, and zeroes in the 1/
plot become poles in the open loop phase check for stability.
l
d
= LOG (fcl)
fcl = LOG
1

l
d
( )
*fcl = 10
(l/d)

fcl = 10
(1.4"/2")
= 5.012Hz
* This can be used between
any decade of frequencies
by normalization of scale for
1 to 10.
d
l
FREQUENCY (Hz)
1 10
fcl = 501.2 KHz
fcl = 10
(1.4"/2")
= 5.012Hz
Scale is normalized for
1 to 10 by dividing by
100. Answer to fcl is
multiplied by 100 to
yield final answer in KHz.
d
l
FREQUENCY (Hz)
100K 1M
fcl
fcl
LOG SCALING TECHNIQUE
When using rate-of-closure graphical techniques it is convenient to
measure what frequency fp or fz might be at without detailed
calculation. This handy reminder about log scale will give you that
power:
Definition by example is easiest
What frequency is fcl below?
IMPORTANT NOTICE
AN19
AN19U 751
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
.
1
1
1
0
1
0
0
1
K
1
0
K
1
0
0
K
1
M
1
0
M
1
0
0
M
0
2
0
4
0
6
0
8
0
1
0
0
1
2
0
1
4
0
1
6
0
1
8
0
2
0
0
2
2
0
2
4
0
F
R
E
Q
U
E
N
C
Y

(
H
z
)
G A I N ( d B )
AN19
752 AN19U
P H A S E S H I F T ( d e g r e e s )
F
R
E
Q
U
E
N
C
Y

(
H
z
)
.
1
1
1
0
1
0
0
1
K
1
0
K
1
0
0
K
1
M
1
0
M
1
8
0
1
0
0
M
1
3
5
9
0
4
5 0
+
4
5
+
9
0
+
1
3
5
+
1
8
0
.
1
1
1
0
1
0
0
1
K
1
0
K
1
0
0
K
1
M
1
0
M
1
8
0
1
0
0
M
1
3
5
9
0
4
5 0
+
4
5
+
9
0
+
1
3
5
+
1
8
0
.
1
1
1
0
1
0
0
1
K
1
0
K
1
0
0
K
1
M
1
0
M
1
8
0
1
0
0
M
1
3
5
9
0
4
5 0
+
4
5
+
9
0
+
1
3
5
+
1
8
0
AN20
AN20U 753
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
AN20 Bridge Mode Operation of
Power Operational Amplifers
table current limit, set the master to current limit 20% lower
than the slave. If the master cannot be reduced, then raise the
slave 20% above the master to provide better overall protection
than leaving them equal. If a fault occurs in the load such as
a short across the load, this will cause the master to current
limit and its output will clip. Since the master is driving the
slave, we are effectively clipping the drive to the slave also.
Under these conditions the SOA voltage stress will be equally
shared between the two amplifers.
With op amps having fxed internal current limits it is impos-
sible to insure that the master current limits frst. This is not a
total disaster, it just means that under load fault conditions it
cannot be guaranteed that the amplifers will share the SOA
voltage stress, and it must be assumed that one amplifer could
bear the entire stress.
Figure 2 is a simplifcation of output stages to give examples
of amplifer stress under a difficult (low resistance such as a
stalled DC motor) load condition. The worst case stress must be
used where amplifer current limiting cannot be controlled. From
this example it can be seen that proper setting of current limit-
ing, when possible, can halve stresses under fault conditions.
Consider each amplifer individually for load analysis, SOA
plotting and power dissipation calculations by halving the
actual load impedance. Each individual amplifer cannot see
the amplifer connected to the other end of the load. The other
amplifer doubles the voltage, and thus the current, in the load.
4.0 STABILITY
4.1 STABILITY CONSIDERATIONS FOR THE SLAVE
Because the slave amplifer must operate as a unity gain
inverter it will be the most critical with regards to stability. Sta-
bility enhancement methods invariably involve a tradeoff of
frequency response. Fortunately, in the case of the bridge, the
master amplifer bandwidth is naturally restricted by operating at
higher gains (as well as easing stability considerations for the
master). Usually the slave can be compensated such that the
resultant circuit will have matching bandwidths on both halves.
Noise gain compensation is the favored method of enhancing
stability. Keep in mind that noise gain compensation depends
on the non-inverting input being connected to a low impedance
(< 0.1Rn). This is not a problem when the non-inverting input
can be grounded, as in split supply applications, but it must
be considered in single supply applications as the half supply
1.0 ADVANTAGES OF THE BRIDGE CONNECTION
The bridge connection of two power op amps provides output
voltage swings twice that of one op amp. And it is the only way
to obtain bipolar DC coupled drive in single supply applications.
Two possible situations where this is an advantage would be
in applications with low supply voltages, or applications that
operate amplifers near their maximum voltage ratings in which
a single amplifer could not provide sufficient drive.
There are other incidental advantages of the bridge con-
nection. It effectively doubles the slew rate, and non-linearities
become symmetrical reducing second harmonic distortion in
comparison to a single amplifer circuit.
2.0 BRIDGE CONCEPTS AND TERMINOLOGY
Figure 1 is a circuit diagram for the most common variation
of a bridge connection using power op amps. To clarify the dis-
cussion of this circuit, well refer to the left hand amplifer A1 as
the master amplifer, and A2 as the slave. The master amplifer
accepts the input signal and provides the gain necessary to
develop full output swing from the input signal. The total gain
across the load will be twice the gain of the master amplifer.
The master amplifer can be set up in virtually any op amp
type circuit: inverting or non-inverting, differential amplifer, or as
a current source such as an Improved Howland Current Pump.
Always confgure the slave as a unity gain inverting amplifer
and drive it from the output of the master. Later discussions
in connection with Safe Operating Area (SOA) and protection
will show the importance of this point.
3.0 PROTECTION AND SOA
In the following discussions that all general precautions in
using power op amps, such as the need for external fyback
diodes, transient protection, input protection, etc., must be
addressed. These subjects are dealt with in GENERAL OP-
ERATING CONSIDERATIONS. The following discussion will
concern itself only with specifc protection issues related to
bridge connections.
The concept of driving the slave from the output of the
master power op amp is essential for proper protection. The
best illustration of the value of that confguration is shown with
an example such as Figure 1 where op amps with adjustable
external current limiting have been used. With externally set-
FIGURE 1. BRIDGE MODE WITH DUAL SUPPLIES ( MASTER/SLAVE )
V
S
PREVENT SOA VIOLATIONS
SET I
LIM
(A2) > 1.2 I
LIM
(A1)

BANDWIDTH MISMATCH
+V
S
R
i
R
f
A1 A2
R
CL+
R
CL
R
R
R
CL+
R
CL
+V
S
V
IN
V
S
V
LOAD
= +/2V
S
LOAD
+28
I
Lim
= 4A
4A x 1.24= 4.96V ACROSS LOAD
28-4.96 = 23.0V
23V WORST CASE STRESS
11.5V IF AI CURRENT LIMITS FIRST OR IF CURRENT
LIMITS MATCH PERFECTLY
FIGURE 2. EVALUATION AGAINST SOA
1.24
A1
A2
Bridge Mode Operation of Power Operational Amplifiers
MAY 2009
APEX AN20UREVE
AN20
754 AN20U
gain limit of 26 dB in the slave is not exceeded. In the event
the master will also require noise gain compensation for stabil-
ity, the same principle of matching the noise gain will help to
insure matched bandwidths.
The upper corner frequency of the noise gain compensation,
or zero, is determined by Cn such that :
where F= desired zero frequency. Cn should be selected so
that the zero is lower than one-tenth the frequency where the
high frequency noise gain crosses the Aol.
4.3 STABILITY CONSIDERATIONS FOR THE MASTER
In the case of the master, as well as the slave, capacitive
loads should also be considered. The only time the master
would need noise gain compensation would be for very low
gains, capacitive loading, or when using amplifers with minimal
phase margin such as the PA10 and PA12. Methods of analysis
for capacitive loads are discussed in detail in STABILITY FOR
POWER OP AMPS, Application Note 19.
Amplifers with emitter follower or source follower outputs
generally do not have problems with inductive loads. However,
collector or drain output amplifers such as the PA19, PA03
and especially the PA02, with its local feedback loop in the
output stage, can oscillate into inductive loads. Monolithic
amplifers with quasi-complementary output stages can also
be sensitive to inductive loading. Compensate these ampli-
fers with a series R-C snubber from each amplifer output
to ground. For power amplifers the resistors typically run 1 to
10 ohms and capacitors 0.1 to 1.0 F.
5.0 SPECIAL CASES OF THE BRIDGE CONNECTION
5.1 CURRENT OUTPUT
The bridge connection can be a useful tool in a current output
circuit. The maximum rate-of-change of current in an inductor,
as would be used in a defection application, is a function of
available voltage. For that reason the bridge circuit could double
the speed of a magnetic defection application.
In a current source confguration, the slave remains as an
inverting voltage amplifer. Only one amplifer needs to be (or
should be) a current source. Of the available ways of confgur-
ing an op amp for current output, only the Improved Howland
Current Pump is practical for a power op amp bridge.
In Figure 4, the master amplifer is confgured as the current
pump. R8 is the current sensing resistor. The Improved Howland
voltage reference point must be a good AC ground. The sim-
plest way to insure a good AC ground is by good bypassing in
the form of a tantalum or electrolytic capacitor in parallel with
a ceramic capacitor.
4.2 NOISE GAIN COMPENSATION
As shown in Figure 3, a simple way of visualizing the effect
of noise-gain compensation is that it raises the apparent gain
that the amplifer sees (or in other words, reduces feedback)
while not affecting the actual signal gain. Select Rn such that
Rn > = 0.1Ri to limit the phase shift added by the noise gain
compensation. Note from the graph in Figure 3 that, in the
example shown, the noise gain compensation introduces a
pole in the feedback path. In this case, at approximately 300
Hz. At 3000 Hz there is a zero in the feedback path. The region
between these points should be kept to less than a decade in
frequency wide, and a maximum gain difference of 20 dB is
implicit in that requirement. In short, noise gain for the slave
(which has an uncompensated noise gain of 2, or 6 dB) must
be = 20, or 26 dB.
Another consideration that could be given to the selection
of Rn is in regard to frequency response (gain vs. frequency).
From Figure 3, the signal gain of a circuit using noise gain
compensation rolls off at the point where the noise gain in-
tersects the amplifer Aol. In the case of Figure 3, the normal
bandwidth would be about 250 KHz, with compensation about
25 KHz. Without compensation, the slave would have wider
bandwidth than the master which is operated at higher gains.
An ideal value for Rn would be one which makes the noise
gain of the slave match the signal gain of the master, assum-
ing there is not greater than 20 dB of difference, and the noise
R
F
R
I
C
N
R
N
R
F
Z
I
Z
F ( = RF )
Z
I
= R
I
II R
N
2 + X
C
2
FIGURE 3. NOISE-GAIN COMPENSATION
1 10 100 1K 10K .1M 1M 10M
120
100
80
60
40
20
0
100
FREQUENCY, f (Hz)
O
P
E
N

L
O
O
P

G
A
I
N

A
o
l

(
d
b
)
Zf/Zl
Zf/Zl
Aol
1/
R
F
/ R
I
V
N
=
1
2 F R
N
A1
PA02
0.4 100pF
.3mH
A2
PA02
1.5K 1.5K 1.5K 1.5K
7.5V
1.5K
1.5K
Rs
2
36K
15V
-15V
15V
-15V
FIGURE 4. ELECTRO-MAGNETIC DEFLECTION
(BRIDGE AMPLIFIER)
AN20
AN20U 755
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
connected between supply and ground. This provides a 1/2
supply center operating point for the entire bridge. This point
should be well bypassed.
The simplest way to understand the confguration for the
master is to delete the resistors Ro, upon which the master
becomes the standard circuit for a differential amplifer. The
two Rf resistors should be reasonably matched to each other,
and the two Ri resistors matched to each other. An advantage
of this confguration is that the gain is simply the ratio of Rf/Ri.
Now consider the Ro resistors. Their sole purpose is to
provide an equal DC bias on each input and to get the quies-
cent DC level within the amplifers COMMON MODE voltage
range requirements. This is generally anywhere from 5 to 12
volts inside of each supply rail and is given on all amplifer
data sheets. For example, using PA05 on a 90 volt supply,
the COMMON MODE VOLTAGE RANGE of the PA05 dictates
that the inputs must never come closer than within 8 volts of
either rail. So the objective is to select Ro, to set the amplifer
inputs to at least 8 but not more than 82 volts, and to stay within
these limits under normal input swings. As far as exactly what
voltage? It could be argued that half supply is the optimum
common-mode point assuming this doesnt cause excessive
current to fow in the Ri resistors. In higher voltage applications
the range of 5 to 15 volts is more practical though.The PA75 is
especially easy to use in single supply applications. Since these
amplifers common-mode range includes the negative rail, or
ground, their inputs can be driven directly without additional
biasing components. The slave must still have its noninverting
input biased at 1/2 supply for proper bridge operation.

5.4 PARALLEL CONNECTION
The bridge circuit can also be combined with the parallel
connection of power op amps. Figure 7 shows how substantial
audio power outputs can be obtained along with improved reli-
ability since the parallel connection spreads the load among
more amplifers.
Note that in the parallel connection, the pair of paralleled
amplifers are labeled as master and slave also. Because the
slave amplifer operates as a unity gain buffer, an amplifer
must be selected which has a COMMON MODE voltage range
that exceeds its output voltage swing capability. If this cannot
Current Pump has many special considerations which will not
be discussed here, but it will suffice to say that generally the
feedback and input resistors should be very closely matched,
usually better than 0.1%.
For details on voltage and current waveforms of this circuit,
refer to Applications Note 5, Precision Magnetic Defection.
5.2 UNIPOLAR OUTPUT
A particularly powerful way of applying the bridge is in the
unipolar bridge. By unipolar, we mean that the output can
only swing from 0 to one polarity. Figure 5 is used to illustrate
this technique.
The master is a PA241 operating on supply rails of +330
and -15 volts. The slave is operated at +15 and -330 volts. The
lower voltage supplies need only be large enough to respect
the linear COMMON MODE voltage range requirements of
whatever amplifer is used (14 volts in the case of the PA241).
The circuit is designed to accommodate positive going inputs
only. At full output swing the master can reach +318 volts
while at the same time the slave is at 318 volts for a total
voltage across the load of 636 volts. The full dynamic range
with regard to the load is 0 to 636 volts unipolar.
The circuit could also be designed such that it accepts nega-
tive going inputs and the output of the master swings negative
and the slave positive by reversing the supplies.
5.3 SINGLE SUPPLY APPLICATIONS
In the single supply circuit shown in Figure 6, connect the
slaves non-inverting input to a pair of equal value resistors
FIGURE 6. BRIDGE MODE WITH SINGLE SUPPLY (OTHER THAN PA21)
V
S
LOAD
V
S
R
i
R
f
R
O
+V
S
A1 A2
R
CL+
R
CL
R1
R
2
R3
R4
R
CL+
R
CL
R
O
R
i
R
f
+V
S
V
IN
+V
S
R3 = R4
10K
A1
1/2 PA75
10K
10K 10K 1K
10K
1.0
1.0 1.0
1.0
+V
S
+V
S
100K
V
IN
10K
+2.2F
+2.2F
+2.2F
28V 36W 18W
40V 36W 16W
4 8
V
S
P
O
FIGURE 7. SINGLE SUPPLY PARALLEL BRIDGE
A2
1/2 PA75
A2
1/2 PA75
A1
1/2 PA75
+Vs
A1
PA241
A2
PA241
20R
PIEZO
TRANSDUCER
20R
Rn
20R
Cn
R
15
+330
330
+15
R
CL
R
CL
180
180
10pF
10pF
V
IN
ONLY
0 TO 636
VOLT ACROSS LOAD
ONE POLARITY ONLY
FIGURE 5.
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be done, confgure the slave as a differential amplifer with 4
equal valued and closely matched resistors.
Stability can also be a problem with the slave in the parallel
amplifer. A resistor may have to be inserted in the feedback
to allow for the use of noise gain compensation. (Noise gain
compensation does absolutely nothing when placed across
the inputs of a unity gain buffer with no series resistance in
the feedback path)
10K
R
FM
+12V +48V
+48V +48V
.1F
R
IM
1K
R
NM
C
NM
V
IN
+/5V
12V
OP07
48V
.649
IN5806
IN5806
48V 48V
IN6290
IN5806
IN6290
IN5806
9.31K
RG
PB58 PB58
100K
+48V +12V
R
CL
48V
OP-07
12V
R
IS
100K
R
FS
100K
A2 A1
M
LOAD
.1F
.1F
.082F
33F
33F .1F
1W
CC
.511
R
CL
1W
CC
9.31K
R
G
33F .1F
C
NS
1500PF
R
NS
6.34K
.1F
.1F
FIGURE 8. PB58A MOTOR DRIVE BRIDGE
33PF 33PF
.1F 33F
+
+
+
+
5.5 BRIDGES USING POWER BOOSTERS
A bridge circuit using the PB50 or PB58 would require a
composite amplifer for both master and slave. The composite
amplifer is not an optimum confguration to operate at unity
gain when stability is considered. Use noise gain compensation
to establish an adequately high noise gain at high frequencies.
Note that observing the criteria previously discussed regarding
noise gain would typically dictate that the noise gain for the
slave be 26 dB (Gain = 20). See Figure 8 for a bridge circuit
using power boosters.
IMPORTANT NOTICE
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of Power Operational Amplifers
2.5 CAPACITIVE COUPLED LOAD
In applications such as audio, it is possible and often desir-
able to AC couple the load with a capacitor. A simple series
capacitor allows driving a ground connected load, as in Fig. 1D.
An alternative is to connect the ground side of the load to two
large electrolytics, as in Fig. 1E. The only possible advantage
of Fig. 1E is the possible reduction of turn-on pop in circuits
where this may be a problem.
FIGURE 1. LOAD CONNECTION OPTIONS
LOAD
A. LOAD TO GROUND
LOAD
C.1/2 SUPPLY
1/2 V
S
LOAD
D. AC COUPLED SINGLE CAP
LOAD
E. AC COUPLED DUAL CAP
+V
S
V
S
B. BRIDGE
LOAD
1/2 V
S
+V
S
+V
S
+V
S
+V
S
R
R
1.0 SINGLE SUPPLY OPERATION INTRODUCTION
Single supply operation of power op amps is most often
done out of necessity. Examples of such applications are bat-
tery powered applications or circuits operating from vehicular
power systems.
Single supply operation improves the efficiency of power
supply usage. In split supply applications, current is drawn
from only one supply at a time, with the opposite supply sitting
idle unless bridge circuits are used.
This application note deals exclusively with applications
operating off of positive supplies as this occurs 95% of the
time. Negative supply principles are identical except for the
reversal of polarity.
2.0 RESTRICTIONS OF SINGLE SUPPLY OPERATION
2.1 COMMON-MODE RESTRICTIONS
Keeping op amp inputs biased to within their linear common-
mode voltage range is the most important requirement in single
supply circuits. The actual value required varies for each amplifer
model, and is described in individual model data sheets under
SPECIFICATIONS, COMMON MODE VOLTAGE RANGE. DO
NOT USE the specifcation given in the ABSOLUTE MAXIMUM
RATINGS block of the data sheet.
2.2 LOAD CONNECTION TO GROUND
There will be several options available for load connection,
as shown in Fig. 1. The frst option shown in Fig. 1A, is a load
connected to ground. Obviously only positive going outputs are
possible. Note that when the output voltage the load sees is
near zero, the amplifer considers its output to be swung to its
negative rail.
Note also that amplifers have limits as to how close they can
swing to either rail. So the output for the grounded load can
never actually go to zero. It has been observed that substantial
current is available under these non-zero conditions, and that
the amplifer has full source and sink capability. As an example,
a PA12 in a single positive supply will swing as low as 2.5 volts
on the output. If a load is connected from output to ground,
even with the amplifer overdriven in a negative direction, it
will supply substantial positive current, on the order of amps,
and up to the current limit, into the load.
2.3 BRIDGE LOAD CONNECTION
The bridge load connection using two amplifers, as shown in
Fig. 1B, permits bipolar swings across the load. For DC coupled
loads this is the only practical way to obtain bipolar swings.
Note that the bridge effectively doubles the gain of the circuit.
2.4 LOAD TO HALF SUPPLY
Bipolar drive is possible if the load can be referred to a
point at half supply, as in Fig. 1C. This is usually not practical,
nor efficient, as the half supply point must have the current
capacity to support the load requirements. It might be possible
to use a second power op amp as a high current source and
sink regulator for this point, but this second op amp would be
much more efficiently utilized as the second half of a bridge.
Single Supply Operation of Power Operational Amplifiers
MAY 2009
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3.0 CIRCUIT TOPOLOGIES
3.1 UNSYMMETRICAL SUPPLY
Oddly enough, the frst option that should be considered is
to not use a single supply. Many applications such as those
using high voltage amplifers require a single large high voltage
supply and unipolar output swings. This is to allow incorporation
into systems which already have lower bipolar supplies such
as 15 or 12 volts present. Should this be the case, then use
the 15 or 12 volt supply on the negative rail of the op amp
(more than a few high voltage applications have large negative
supplies along with 12 or 15 volt bipolar supplies).
As shown in Fig. 2, as long as the small supply is large
enough to accommodate the common-mode requirements of
the amplifer over the range of normal inputs, then no other
additional components are required.
3.2 DIFFERENTIAL CONFIGURATION
The most universally useful single supply circuit is the dif-
ferential confguration shown in Fig. 3. This topology makes it
possible to set the gain simply as the ratio of R
F
/R
I
where each
R
F
pair and R
I
pair are matched to each other. It is feasible
to use the circuit either non-inverting or inverting, but keep
in mind that noninverting will accommodate inputs which go
positive only with respect to ground, and non-inverting negative
only with respect to ground. Also note that the R
O
pair must be
closely matched to each other.
The R
O
resistors provide the input common-mode biasing
to keep the amplifer linear. An advantage of this method is
that (assuming adequate resistor matching) the output would
be unaffected by variations in power supply voltage. Normally
this inherent supply rejection is desirable, but in the case of
the bridge amplifer, this could be a problem since the slave
of the bridge is referred to a voltage divider operating from
supply voltage. That divider is subject to supply fuctuations,
and if the master amplifer of the bridge was equally subject to
such fuctuations, it would appear as a common-mode signal
across the load and be rejected.
R
O
needs to be selected to satisfy common mode voltage
requirements, and it turns out this encompasses a wide range
of acceptable values for any given circuit. The designer is con-
fronted with the question of just exactly what common mode
voltage to set the inputs to. It could be set anywhere within
the common mode range, but there will be some practical
limitations even within that range.
To illustrate, assume the use of a PA85 with +450 volt sup-
plies. R
O
can be selected for anything from 12 volts to 438
volts for linear operation. It could be argued that the ideal
value is half supply, or 225 volts, but such a selection would
require unreasonably large values for R
I
to keep currents within
reasonable values. A very large R
I
would require an even
larger R
F
, and the net overall impedance would be so high
that stray capacitance and amplifer input capacitance would
create enormous bandwidth and stability problems. For high
voltage applications, minimum values such as 12 to 15 volts
of common mode biasing are easier to accommodate.
When selecting R
O
, consider it part of a voltage divider where
the ground leg of the divider is the parallel resistance of R
F

and R
I
. Using that assumption, at full negative input voltage
swing in conjunction with full theoretical negative output swing
of zero, you will be designing to meet common mode require-
ments. Dynamically, the inputs will only move positive from
this point, simplifying worst-case analysis to double checking
the most positive excursion. R
O
selection can be aided with
the following equation:
V
CM
is the desired common mode voltage. Once a value is
settled on for R
O
and the common mode bias point, it should
be rechecked over the expected range of input signal values
to verify common mode restrictions are met dynamically and
readjusted if necessary. Also consider that part of the R
O
cur-
rent fows in R
I
and through the source driving the input. The
source must be able to accommodate this current.
The differential confguration is so useful that in section 7.0,
several design examples will be explored. Appendix A outlines
a procedure for the design of this circuit.
4.0 EXPANDED TECHNIQUES
4.1 BRIDGE CONNECTION
The bridge connection shown in Fig. 4 (next page) uses
the differential confguration for the master, A1 amplifer, and
a unity gain inverter for the slave, A2 amplifer. The slave non-
inverting input is referred to a point on a divider at half sup-
ply voltage. Since this divider is referred to the supply, there
will be susceptibility to power supply variation. Note that the
zero output point is defned as the point where both amplifer
outputs are equal, and this point is set by the non-inverting
input of the slave.
FIGURE 2. UNSYMMETRICAL SUPPLIES
+430V
V
OUT
0 to 415 V
-15V
V
IN
R
I
R
f
PA85
FIGURE 3. SINGLE SUPPLY NON-INVERTING CONFIGURATION
V
S
R
i
R
O
V
S
R
f
R
O
R
i
R
f
V
CM
V
IN
0
V
CM
=
S
V
O
V =
R
i
R
f
For V
IN
= 0:
V
CM
=
V
CM
= V
CM
+
For V
IN
> 0:
(R
i
||R
f
)
O
R +(R
i
||R
f
)
IN
V (R
O
||R
f
)
i
R +(R
O
||R
f
)
@V
IN
= 0
V
CM

(V
S
V
CM
)
R
O
=
V
CM
R
I
|| R
F
( )
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The preferred way of improving the bridge circuit tolerance
to power supply variations would be to regulate the half sup-
ply point. In the event this is not possible or desirable, Fig. 5
(next page) shows a bridge topology that reduces sensitivity to
supply variations. The ratio of R2/R1 should be ratio matched
to the ratio of R3/R4. Note that gain of A1 will be:
A
V
= ((Rf/Ri)+1) (R2/(R2+R1))
Or, consider that while R1/R2 attenuate the input signal by
half, and the bridge circuit effectively doubles circuit gain with
respect to the load, then A
V
is equal to the non-inverting gain
of A1, or R
F
/R
I
+1.
The AC coupled bridge is a special case of the single supply
bridge amplifer circuit, and is especially useful for audio where
a stable DC operating point is desirable. Fig. 6 depicts such a
circuit. Note that both non-inverting inputs use the half supply
point as a bias reference. C1 AC couples the input signal. C2
blocks the DC ground path in the feedback loop insuring a
unity gain for A1 at DC.
4.2 CURRENT OUTPUT CONFIGURATION
Any voltage to current confguration is possible in the single
supply environment, as long as common mode restrictions are
met. The foating load current source will be restricted to unipolar
outputs although the output cannot swing to zero current. Of
course a bridge topology has many benefts including bipolar
output, the ability to deliver zero current, and more voltage
available to the load. In magnetic defection applications, the
higher voltages make for faster current transitions.
Since the Improved Howland Current Pump resembles
a differential amplifer, it easily lends itself to single supply
applications. The only modifcation will be the addition of the
R
O
common mode biasing resistors. The Howland is subject
to wide dynamic range variations on both input and amplifer
output with an infnite number of possibilities when various
gains are factored in. Suffice to say the designer must analyze
input common mode values at the four extremes of dynamic
range:
1. Most positive input, most positive output
2. Most positive input, most negative output
3. Most negative input, most negative output
4. Most negative input, most positive input.
5.0 SPECIAL OP AMP CASES
5.1 PA02 SINGLE SUPPLY BEHAVIOR
A PA02 presents a special problem in single supply ap-
plication. Like all BiFET input op amps, a negative common
mode violation on either or both inputs causes the output to go
full positive. Common mode violations are inherent in power
up conditions in all op amp circuits since common mode is
measured with respect to the supply rail.
In the case of a PA02, when the inputs are closer than 6
volts to either supply rail there is a common mode violation. It
is implicit in this requirement that until total rail-to-rail supply
voltage has reached at least 12 volts, the amplifer will not
be linear. With a PA02 in particular, until the negative supply
rail is at least 5 to 6 volts more negative than BOTH inputs,
the output will be hard positive. This causes PA02 output to
go full positive during power up in single supply applications.
When used as an audio amplifer, this results in a loud pop
from the speaker during power up.
There is no elegant solution to this problem. If the speaker is
AC coupled and returned to positive supply rather than ground,
this may help some. But most applications have shown the only
dependable solution would be a relay that closes the circuit to
the speaker once full supply voltage has been reached.
5.2 PA74 SINGLE SUPPLY CONSIDERATIONS
A PA74 is without a doubt the easiest power op amp to use
on single supplies since the input common mode range can
actually go more negative than the negative rail. Inputs can
be applied to a PA74 in single supply applications without the
need for additional biasing circuitry. The circuit shown on the
front of the PA74 data sheet illustrates just how easy it is to
apply for unipolar inputs in a DC motor drive application.
FIGURE 5. MODIFIED SINGLE-SUPPLY BRIDGE FOR IMPROVED
SUPPLY REJECTION
LOAD
R
i
A1 A2
R
2
V
IN
R
1
R
f
R
5
R
6
R
3
R
1
= R
2
R
3
= R
4
R
5
= R
6
Since by R
1
, R
2
, and A2 doubles gain
then A
V(LOAD)
= +1
Rf
Ri
V
IN
2
R
4
+Vs +Vs
+Vs
FIGURE 6. AC COUPLED BRIDGE
20F
1/2
PA74
0.1F
V
IN
10K
R
4
1K
1K
1/2
PA74
10K
R
L
= 4
P
O
= 8W
10K
R
F
A1 A2
+12V
C
2
10K
R
2
R
3
R
5
R
6
+12
C
3
1K
R
I
2F
C
1
100K
R
1
FIGURE 4. BRIDGE MODE WITH SINGLE SUPPLY OTHER THAN PA21
V
S
LOAD
V
S
R
i
R
f
R
O
+V
S
A1 A2
R
CL+
R
CL
R
1
R
2
R
3
R
4
R
CL+
R
CL
R
O
R
i
R
f
+V
S
V
IN
+Vs
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5.3 COMMON MODE BEHAVIOR IN GENERAL
It is helpful if the designer has some idea of which ampli-
fers are subject to unusual behavior during common mode
violations. Like the BiFET PA02 described above, any FET
input power op amp can exhibit polarity reversals during com-
mon mode violations. The polarity of most FET input stages,
such as a PA07, all high voltage op amps, and Burr-Browns
OPA541, are such that a positive common mode violation will
cause a reversal of output polarity. This occurs since gate
to drain of input FETs becomes forward biased under these
conditions and the signal effectively bypasses the FET and
its normal inversion.
5.4 AMPLIFIERS WHERE SINGLE SUPPLY OPERA-
TION IS NOT RECOMMENDED
The use of a PA89 in single supply circuits is discouraged.
The input common mode voltage range dictates the inputs must
always operate at least 50 volts inside of either supply rail, an
impractical value to establish bias in the differential confgura-
tion. Unsymmetrical supply techniques are more applicable for
getting large unipolar swings out of PA89 circuits. In the case
of a PA89, the smaller supply needs to be at least 50 volts.
The power boosters PB50 and PB58 also present unique
problems. For example, the ground pin of these parts must
see a clean analog ground with low impedance over a wide
bandwidth. This can be difficult to insure in a single supply
environment. A PB50 must operate with its ground pin 30
volts more positive than the negative rail, while a PB58 must
operate at least 15 volts, and preferably 20 volts more positive
than the negative rail. While it is possible to use these parts
in a single supply environment, it is far preferable to use them
with split or unsymmetrical supplies.
6.0 TURN ON POPS
Regardless of amplifer choice, audio applications where
the load is AC coupled and connected to ground will always
be susceptible to turn on pops. The two main reasons this
occurs are: the amplifer is not linear until supply voltage is
high enough; and the amplifer output inherently must go from
zero to about half supply.
A bridge confguration will often improve (reduce) the likeli-
hood of pops. Or as mentioned above, a relay which closes the
circuit to the load once full supply voltage has been reached
can help; although, with an AC coupled grounded load the
output capacitor must still be charged.
Controlling power supply rise time to be sufficiently slow can
also alleviate this problem. It may require slowing it such that
it even takes seconds. Even this technique will add a relay or
some type of solid state switch. The easiest way to implement
a slow rise supply is with a sufficiently large resistor in series
with a flter capacitor.
7.0 DESIGN EXAMPLES
7.1 DESIGN SPECIFICATIONS:
Supply voltage = 28 volts. Input signal range = 0 to 5 volts.
Unipolar output, single ended.
A PA12 has been selected for a unipolar voltage output mo-
tor drive. Differential confguration is selected, see Fig. 7. (Note
that many details will not be discussed here, but are covered in
other app notes, such as current limit resistors, fyback diodes,
and power supply bypassing.)
Select R
F
/R
I
: This requires arbitrarily fxing one of these re-
sistor values. In general, the best practice is to fx R
I
at about
10K ohms, as this is an impedance that most any small signal
source will drive with no problem.
dV
IN
has been established at 5 volts. While it is true that
an op amp output cannot actually swing exactly to each rail,
the circuit scaling should be selected as if it could; therefore,
on a 28 volt supply, dV
OUT
=28 volts. This results in a value for
R
F
of 56K ohm.
Now R
O
must be selected to respect PA12 common mode
requirements which dictate that the inputs must be kept 5 volts
inside of either supply rail. So the inputs could be set anywhere
from 5 to 23 volts. An ideal value would be 14 volts. Lets try
an R
O
value based on that and see if currents through the
input resistors and input terminals remains reasonable. From
the equation in 3.2 above, this would result in an R
O
value of
approximately 8.48K ohms, nearest standard value 8.2K ohms.
This would result in 1.65mA fowing to the input terminals and no
inordinate power dissipation in any of the input circuit resistors.
Since the process used to select R
O
is based on worst case
negative voltage input/output relationships, the common mode
should be re-checked for full positive inputs and outputs. As-
suming +5 volts at the input and a theoretical +28 volts at the
amplifer output, the circuit simplifes to R
O
and R
F
being in
parallel to +28 volts and forming a voltage divider with RI as
the ground leg. This results in a voltage at the amplifer input
of 16.32V, that is within the maximum positive common mode
restriction of 23 volts.
Supply voltage = 28 volts. Input voltage -2.5 to +2.5 volts.
Voltage in, current output (will require Improved Howland Cur-
rent Pump). Output range 2A.
A PA02 is selected for this application along with a bridge
circuit. Referring to Fig. 8, the R1, R2 and R4, R3 ratios were
selected to provide the required transfer function based on
a 0.301 ohm current sense resistor, R
S
. Note that over the
expected normal range of input signals and output voltages
that common mode requirements are met. While true for this
application, each one should be checked to verify the voltages
are within acceptable limits. Note that even on this circuit that
exceeding the 2.5 volt dynamic range on the inputs will cause
common mode violations to occur.
FIGURE 7. UNIPOLAR MOTOR DRIVE EXAMPLE
R
CL +
PA12
R
F
R
I
R
O
R
CL
R
CL
+28
8.2K
10K
+28
R
I
V
IN
0 to 5V
R
O
+28
8.2K
56K
10K
56K
R
F
R
F
=
R
I
dV
OUT
dV
IN
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Supply voltage = 450 volts. Input voltage 0 to 10 volts.
High voltage bridge for piezo drive. Low power consumption.
A PA88 is selected to meet low consumption requirements,
the circuit is shown in Fig. 9. R
F
and R
I
must provide a gain on
the master amplifer of 45. In the process of minimizing power
consumption and maintaining a reasonable physical size for
components, consider there can be as much as 450 volts
across R
F
. In order to use a half watt resistor, R
F
would need to
be 510K ohms. For a gain of 45, R
I
would then be 11K ohms.
In this high voltage application, it is wise to design for the
minimum acceptable common mode voltage which is 12 volts
for a PA88. 15 volts will be used to provide a little margin. 300K
ohms will be required for R
O
. 510K ohms will also be required
for both gain setting resistors on the slave.
The half supply reference point resistors will each have 225
volts across them. The minimum acceptable value for half watt
resistors would be 101K ohms each, but to minimize consump-
tion, 200K ohms each is used. These must be bypassed.
With the large value feedback components around the slave,
amplifer problems can result from feedback poles being cre-
ated by amplifer input capacitance and stray capacitance. This
may require a small compensation capacitor from 2 to 20 pF
across the feedback resistor.
Supply voltage = 450 volts. Input voltage 0 to 10
volts. Wide band high voltage driver. Single ended.
The circuit in Fig. 10 contrasts with the previous
example in that it is a wideband circuit and requires
the lowest possible impedances at all modes. The
standard differential confguration will be used. This
is an example where minimum common mode bias
will have to be set to avoid excessive current and
dissipation problems in resistors.
Gain for this circuit will be 45. In order to use
the lowest possible value for R
F
to insure good
bandwidth, a 5 watt resistor will be used. Assum-
ing worst case voltage stress across R
F
to be 450
volts, the lowest permissible standard value is 43K
ohms. For a gain of 45 volts, R
I
must be (nearest
standard value) 910 ohms. Because of such low
impedances, a minimum common mode bias
(from the PA85 data sheet) of 12 volts must be set.
Solving for R
O
, assuming 12 volts of common mode bias,
with an input of 0 volts and theoretical 0 volt output, the value
is (nearest next lowest standard value) 30K ohms. This resistor
will have 438 volts across it and will dissipate 6.4 watts.In ad-
dition, 15mA will fow through the input terminal. These values
will be difficult, if not impossible, to work with. It may be possible
to scale up by a factor of two and have sufficient bandwidth.
Re-calculating using 91K ohms R
F
, and 2K ohms R
I
, R
O

solves to 68K ohms, the nearest standard value. Dissipation
in R
O
is now 2.8 watts and 6.3mA fows to the input resistor.
While these numbers are better, they could still be a problem.
Further scaling up of impedances will aggravate bandwidth
problems as the effects of parasitic and amplifer input capaci-
tance become signifcant.
This design example has been shown to be feasible in the
design of a single supply circuit. But use of a 15 volt supply
for the negative rail will eliminate the impedance constraints
and permit the circuit to be designed for maximum possible
bandwidth with a conventional circuit.
R
F
91K
+450
+450
+450
R
CL
R
O
68K
R
I
2K
R
O
68K
C
C
FIGURE 10. PA85 H.V. DRIVE
(FOR R
C
, C
C
SEE PA85 DATA SHEET)
R
C
R
I
2K
R
F
91K
V
IN
0 to 10V
PA85
V
O
510K 510K
R
F
+450 +450 +450 +450
510K
R
O
R
I
11K
R
I
11K
R
O
R
CL 510K
200K
0.1
LOAD
R
F
R
C
C
C
C
C
R
C
FIGURE 9. PA88 H.V. BRIDGE
R
2
R
CL
+450
R
1
R
3
C.1
200K
R
4
V
IN
0 to 10V
300K
300K
PA88 PA88
2.1K
.258
RCL1+
+28V
8.66K
.258
RCL1
8.66K
R3
RW = 6.5
V
IN
4.99K
R5
4.99K
R6
.205
RCL2
+28
4.99K
R8
4.99K
R7
+28
.205
RCL2+
.301
RS
VA1 VA2
.1F
C1
VCM
+2.5V
V
IN
V
A1
V
A2
2.5V
6.0V
16.5V
7.2V
20.8V
20.8V
7.2V
2A
+2A
I
OUT
V
CM
FIGURE 8. LIMITED ANGLE TORQUE CONTROL (SINGLE SUPPLY)
R1
R2
2.1K
R4
PA02 PA02
AN21
762 AN21U
APPENDIX A: PROCEDURE FOR DESIGN OF
DIFFERENTIAL CONFIGURATION
1. Select R
F
and Ri:
In general, R
I
should be the resistor value on which all others
pivot. This is because R
I
essentially represents the load
presented to the input signal. Most small signal op amps
work best if R
I
is 10K ohms or larger, but many would permit
R
I
to drop as low as 1K or 2K ohms if necessary.
2. Select R
O
:
3. Check dissipation in Ro. If too high, all resistor values need
to be re-scaled upward.
4. Re-check V
CM
at all four possible extremes of both input
signal and amplifer output voltage. Although some of these
operating conditions may not actually occur, it is wise to
have a circuit that has linear common mode bias under all
conditions if for no other reason than it is the only hope the
op amp has to recover from the following conditions:
a. Full negative input (usually 0), full negative output (theo-
retical 0). This condition is accounted for in the equation
to select R
O
.
b. Full negative input, full positive output (assume theoreti-
cal maximum equal to supply voltage).
c. Full positive input (dont forget that most small signal op
amps could swing beyond their 10 volt linear limit, often
up to a full 15 volts), full negative output.
d. Full positive input, full positive output.
R
F
=
R
I
dV
O
dV
I
GAIN =
V
S
V
CM
R
O

V
CM
R
I
|| R
F
( )
(MIN, from amplifier data sheet)
If any of these four conditions do not meet common mode
restrictions, adjust R
O
accordingly. For instance, if a violation
is more negative than minimum allowable common mode bias,
reduce R
O
(most common likely problem). If the violation is
positive, which is unlikely with most realistic bias levels, then
R
O
should be increased.
5. If being used in a bridge, it is recommended that the slave
amplifer noninverting half supply bias point be regulated,
either with a zener diode or derived from some regulated
voltage.
IMPORTANT NOTICE
AN22
AN22U 763
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
AN22 SOA and
Load Lines
1.0 MEANING OF SOA GRAPH
SOA (Safe-Operating-Area) graphs defne the acceptable
limits of stresses to which power op amps can be subjected.
Figure 1 depicts a typical SOA graph.
The voltage value on the right of the graph defnes the maxi-
mum with no regard to output current or device temperature.
Note that this voltage is related to the output voltage but is
different; these two voltages are NOT interchangeable. The
current value at the top of the graph defnes maximum; again,
with no regard to temperature or voltage. Inside the graph
area will be one or more curves with a slope of -1 (as voltage
doubles, current drops to half) labeled with a case tempera-
ture. These are constant power lines defned by DC thermal
resistance and the rise from case temperature to maximum
junction temperature (2.6C/W and 200C in this case). Lines
with a steeper slope (about -1.5 in this case) are unique to
bipolar output transistors. The steady state second breakdown
reduces the amplifer's ability to dissipate DC power as voltage
becomes more dominant in the power equation. Fortunately,
the lines with time labels indicate higher power stress levels
are allowed as long as duration of the power stress does not
exceed the time label.
Transient SOA limits shown on data sheets are based on
a 10% duty cycle pulse starting with junctions at 25C. The
repetition rate then would logically be defned by the time re-
quired for the junction to return to 25C between pulses. Some
amplifers such as PA85 allow transient currents beyond the
maximum continuous current rating. Most often though, the
transient ratings are based on power or second breakdown
restrictions.
2.0 ANALYTICAL METHODS
2.1 PLOTTING RESISTIVE LOAD LINES
Resistive load lines can be plotted quite easily. Keep in
mind that since SOA graphs are log-log graphs, the resistive
load line will have a curvature, so several points should be
calculated and plotted.
Output voltage and current will always have the same polar-
ity with a resistive load, so calculations can be performed at
all times from 0 to 90 of the output cycle. Figure 2 depicts an
example of resistive load line. It is interesting to note that this
is a safe load which can require a 5 amp peak capability. If
the output of the PA12 is unintentionally shorted to ground the
voltage stress on the output will be 50 volts, which is not safe
at the 5 amp current limit required to drive the load. In applica-
tions where the amplifer output would not be subject to abuse
these operating conditions are acceptable. Foldback current
limiting can be used to improve on the safety of this situation.
2.2 PLOTTING REACTIVE LOAD LINES
Reactive load lines of any phase angle can be plotted with
the methods shown here. A completely reactive load line almost
looks like an ellipse on the SOA graph since current stresses
will occur at two different levels of voltage stress.
The voltage output waveform will defne the reference phase
angles for all point-by-point stress calculations. The waveform
shown in Figure 3 (next page), starts at 90, since current
in capacitive loads will lead in phase. The waveform ends at
270 since that corresponds to the maximum phase lag of the
current in an inductive load. All calculations will be within the
limits of these angles.
Calculations proceed according to the steps in Figure 4 (next
page). Currents will only need to be calculated over 180 since
the load line for each half of the amplifer is a mirror image.
Capacitive loads will start at 90 and progress through +90.
5.0
3.0
2.0
1.5
1.0
.7
.3
10 20 25 30 35 40 50 60 70
S O
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V

O
R

V

(
A
)
S
S
.5
t

=

1
m
s
T
C =
8
5
C
s
t
e
a
d
y

s
t
a
t
e
15 80 100
10
15
T
C =
1
2
5
C
T
C =
2
5
C
T
H
E
R
M
A
L
t

=

5
m
s
t

=

0
.
5
m
s
PA12
+50
50
9
FIGURE 2. PLOTTING RESISTIVE LOAD LINE
V
O
V
S
V
O
I
O
0 50 0
5 45 .556
10 40 1.11
15 35 1.67
20 30 2.22
25 25 2.78
30 20 3.33
35 15 3.89
40 10 4.44
45 5 5.00
SECOND BREAKDOWN
OUTPUT CURRENT (AMPS)
FIGURE 1. TYPICAL SOA PLOT
T
c
=
1
2
5
C T
H
E
R
M
A
L
s
t
e
a
d
y

s
t
a
t
e

S
E
C
O
N
D

B
R
E
A
K
D
O
W
N
t

=

1
m
s
t

=

5
m
s
t

=

0
.
5
m
s
.2
.3
.4
.6
.8
1.0
1.5
2.0
3.0
4.0
5.0
10 15 20 25 30 35 40 50 60 70 80 100
T
c
=
8
5
C
S
V
O
(V)
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V
S

O
R

V
S

(
A
)
SOA and Load Lines
MAY 2009
APEX AN22UREVD
AN22
764 AN22U
Inductive load calculations will start at +90 and progress to
+270. Step 2 in the procedure defnes the starting angle for
calculations based on the load phase angle. For example, a
45 load would start at 45 and continue to +135. A 45
load will start at 45 and continue to 225
Example of a typical load calculation:
In the resistive load example the load line of a 9 ohm resistive
load was plotted and was quite safe. For this example lets use
the same impedance but with a 60 phase angle.
Figure 5 shows a PA12 driving an inductive load of 9 ohm
at 60. From step 2 of our procedure we know we begin cal-
culating current at 60 and continue to 60+180 or 240. For
this example we will use 15 increments. Actually, it is only
necessary to perform the step-by-step calculations for current
up to the point where peak current occurs, in this case 150.
The increments back down to 240 will be a mirror image of
what was just calculated. However, dont get this lazy with the
voltage calculations we have yet to do.
Even though the point of maximum voltage stress occurring
at full negative output swings is not evident in the voltage stress
calculations, it is inconsequential since we have established
that no current fows through the output device at that time.
As long as the amplifer itself is within its voltage ratings, all
will be well.
After all points are calculated, they may be plotted on the
SOA graph. In this particular case note there are signifcant
excursions beyond the steady state 25C SOA limit. Is this
acceptable? Consider the following factors to help make the
decision: 1. The area beyond the continuous SOA is quite size-
able. 2. A calculation of maximum average power dissipation
using the formula shown in Fig 5 (refer to General Operating
Considerations for background on this calculation) shows the
amplifer dissipating 107 watts.
The 107 watt dissipation will certainly cause the amplifer
to operate at signifcantly elevated temperatures, even with
a generous heatsink. Realistically the SOA limits are being
reduced by the heating. We can even defne exactly how badly.
Assume a 25C ambient (thats pretty optimistic). Using an
HS05 heatsink rated 0.85C/watt results in an amplifer case
temperature 91C. It is evident that the PA12 is not well suited
5.0
3.0
2.0
1.5
1.0
.7
.3
10 20 25 30 35 40 50 60 70
S O
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V

O
R

V

(
A
)
S
S
.5
t

=

1
m
s
T
C =
8
5
C
s
t
e
a
d
y

s
t
a
t
e
15 80 100
10
15
T
C =
1
2
5
C
T
H
E
R
M
A
L
t

=

5
m
s
t

=

0
.
5
m
s
PA12
+V
S
(+50V)
FIGURE 5. TYPICAL LOAD LINE CALCULATIONS

V
I

Vd (V
S
V
O
)
60 0 11
75 1.29 6.53
90 2.5 5
105 3.54 6.53
120 4.33 11
135 4.83 18.2
150 5A 27.5
165 4.83 38.4
180 4.33 50
195 3.54 61.6
210 2.5 72.5
225 1.29 81.8
240 0 89

45V
9 <+60
(INDUCTIVE) LOAD
45V
P
9
= 5A
PK
T
C =
2
5
C
(NOTE THAT Pd max =
Vs
2
2Z
L
4
Cos
L
= 107 w
V
S
(50V)
LOAD
FIGURE 3. TYPICAL WAVEFORMS ASSOCIATED WITH
REACTIVE LOAD LINE ANALYSIS
90 0 90 180 270
I
O
RESISTOR
I
O
CAPACITOR
(90)
I
O
INDUCTOR
(+90)
(45)
(+45)
V
O
VOLTAGE WAVE FORM ESTABLISHES REFERENCE PHASE ANGLE
FOR ALL LOAD LINE CALCULATIONS. SHADED AREA REPRESENTS
CALCULATION REGIONS
1. KNOWN: Vp , Z
L
,
L
2. BEGIN POINT CALCULATIONS WITH
L
AT 0 +
L
AND PLOT
FOR NEXT 180 IN WHATEVER INCREMENTS NEEDED FOR
DESIRED ACCURACY (15 OR 30 INCREMENTS RECOMMENDED.)

3. Ipk =
Vp
Z
L
CALCULATE ONLY ONCE
4. CALCULATE EACH INCREMENT:
I = Ipk (sin (
V

L
))

5. CALCULATE EACH INCREMENT:
Vd = Vs Vp (sin
V
)
FIGURE 4. REACTIVE LOAD CALCULATIONS
AN22
AN22U 765
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
all limiting values.
Figure 6B portrays foldover limiting according to formulas
contained in Application Note 9 or the PA12 data sheet. The load
of Figure 5 obviously cannot be driven. Note that with foldover
limiting a peak current of 2.8 amps is available yet short circuit
current is limited to 1.5 amps making it possible to safely drive
a 16 ohm resistive load. To determine the minimum acceptable
value for a reactive load, consider that 70.7% of peak current
for this application. The alternatives include either paralleling
PA12s or upgrading to a PA05.
2.3 SPECIAL CASES OF LOAD LINE PLOTTING
AND OTHER GENERALIZATIONS
For parallel connected amplifers, assume each amplifer
drives a load rated at half the current of the total load. In es-
sence, double the load impedance. Do just the opposite for
a bridge circuit.
Some simple relationships to keep in mind: for totally reac-
tive loads maximum current occurs at a voltage stress corre-
sponding to Vs and maximum dissipation occurs at a voltage
stress of Vs+(0.707Vs), where current is also 0.707*Ipeak. In
a resistive load, stresses are much less with maximum current
occurring at maximum output voltage swing. This generally
corresponds to the maximum swing specifcation given in
every amplifer data sheet.
Also keep in mind that there are many load lines which will
ft well within an amplifer SOA and be quite safe to drive. Yet
these same loads can demand current capability that requires
current limits be set so high the amplifer output will not be
able to tolerate inadvertent shorts on its output. This is usually
acceptable in applications with committed loads; however,
applications where the amplifer output terminals are acces-
sible to poorly defned loads or fault conditions demand fault
tolerance on the part of the amplifer. A good example is a set
of screw terminals like those found as the output connectors
of an audio amplifer.
The methods shown here calculate load lines for reactive
loads at only one frequency. For inductive loads worst case
stresses will occur at the lowest frequency of interest with the
opposite true for capacitive loads.
MOSFET amplifers have an important difference from bipolar
amplifers regarding SOA limits: MOSFETs are only limited by
power dissipation, or the product of V*I stress. Bipolar amplifers
are power limited up to certain voltages indicated on the SOA
graphs, where second breakdown imposes even lower limits
on safe current than power dissipation would allow.
2.4 PLOTTING AMPLIFIER CURRENT LIMITS
Additional information which can be plotted on the SOA graph
to help assess amplifer safety is the current limit of the amplifer.
Simple fxed current limiting is simply plotted along the current
corresponding to that limit. Any load line excursions beyond
that level can be disregarded. They are simply not possible.
Figure 6A depicts the SOA graph from Figure 5 with a fxed
current limit drawn in. The fxed limit is set to 1.5 amps to
provide short circuit safety at up to 85C case temperature. It
is obvious the load line is totally outside this current limit. The
maximum available output will be set by the 1.5 amp current
limit and impedance of the load. Or in the case of a resistive
load, the lowest load impedance is a function of maximum
output voltage and current limit.
Foldover current limiting can also be plotted on an SOA graph.
This is important with inductive loads since foldover limiting
in conjunction with inductive loads can cause more problems
than it solves unless applied carefully. When foldover current
limiting occurs with an inductive load, a violent fyback spike
occurs that transitions all the way up to one of the supply rails.
External ultra-fast recovery fyback diodes are a must when
combining foldover limiting and inductive loads. It is also pos-
sible for relaxation oscillation to occur. This can be prevented
by insuring that the normal inductive load line is well within
5.0
3.0
2.0
1.5
1.0
.7
.3
10 20 25 30 35 40 50 60 70
S O
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V

O
R

V

(
A
)
S
S
.5
t

=

1
m
s
T
C =
8
5
C
15 80 100
10
15
T
H
E
R
M
A
L
t

=

5
m
s
t

=

0
.
5
m
s
FIGURE 6. PLOTTING CURRENT LIMITS
T
C =
2
5
C
T
C =
1
2
5
C
CURRENT LINE
A FIXED 15A CURRENT LIMIT
Max V
O
(PEAK) REACTIVE = I
LIM
x Z
L
LOWEST POSSIBLE R
L
=
V
O
(pK)
I
LIM
= = 30
5.0
3.0
2.0
1.5
1.0
.7
.3
10 20 25 30 35 40 50 60 70
S O
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V

O
R

V

(
A
)
S
S
.5
t

=

1
m
s
T
C =
8
5
C
s
t
e
a
d
y

s
t
a
t
e
15 80 100
10
15
T
H
E
R
M
A
L
t

=

5
m
s
t

=

0
.
5
m
s
T
C =
2
5
C
T
C =
1
2
5
C
CURRENT LINE
B FOLDOVER CURRENT LIMIT
86 REACTIVE LOAD
R
CL
= 0.433 PIN

7 OF PA12 GROUNDED
.65 + V
O
.28
20
( )
R
CL
I
O
=
LOWEST POSSIBLE R
L
=
45
2.8
= 16
45
1.5
REACTIVE LOAD
0.707 I
PK
@ V
S
+ 0.707 (V
S
) = 50 + 35 = 85V
I
LIM
@ 85v = 370 mA
0.707 V
O
0.707 x 45
0.37A 0.37
= = 86
s
t
e
a
d
y

s
t
a
t
e
AN22
766 AN22U
tion either in the amplifer power supply or the oscilloscope is
connected to an isolation transformer.
Rs is a current sensing resistor. When possible, use of a 1
ohm resistor provides a direct scale factor on the vertical input
of volts = amps. If other values must be used consider scaling
accordingly. The current sense resistor must be right at the
amplifer power pin. This is one of those rare cases where it
is temporarily necessary to violate the rules of proper power
supply bypassing. Any capacitance present at the node, where
the resistor meets the amplifer will interfere with high frequency
measurements. If an oscilloscope current probe is available it
is certainly preferable to the current sensing resistor since it
provides accuracy and speed without having to disrupt the circuit.
4.0 SOA MEASUREMENT CIRCUITS
Another means of analyzing SOA stresses in operating circuits
uses an analog multiplier to calculate real time instantaneous
power dissipation. This method is especially applicable where
second breakdown is not encountered. For example, working
with MOSFET amplifers under any condition or most bipolar
amplifers at total rail-to-rail supply voltages of less than 30 volts.
The circuit shown in Figure 8 senses output device current
and voltage stress as is done with an oscilloscope. Differential
amplifers with wide common-mode ranges are used for sens-
ing these values and levels, translating them to be applied to
an analog multiplier. The output of the multiplier will be the
product of the voltage and current stress on the output device.
The Rs current sense resistor must be in the supply line so
current is measured in only the output device corresponding
to the voltage stress measurement.
This circuit provides a signal indicating instantaneous power
dissipation. When working with a MOSFET amplifer such as
the PA04, the designer should be concerned that this output be
occurs at a voltage stress of Vs+(0.707Vs). A reactive load
line within that operating point will likely be within all operating
points and representative of minimum acceptable load.
Figure 6B depicts the worst case acceptable reactive load. It
really doesnt fll up much of the permissible operating region,
but such are the trade-offs involved in driving difficult loads.
3.0 BENCH TESTING SOA
An oscilloscope can be used to do real world plotting of
load lines on actual working circuits. The SOA limits can be
drawn in on the scope screen if necessary. First, the SOA limits
should be redrawn on linear-linear graph paper. This results in
an SOA graph as shown in Figure 7A. The graph shown is for
a PA12 bipolar amplifer, and second breakdown causes the
break in the shape at 55 volts. MOSFET amplifers will have
a continuous curve representative of power dissipation. This
can then be transferred to a transparency sized to properly ft
on a scope screen.
The easiest method of connecting a scope to plot actual
output device stresses will be to refer the scope ground to
the negative supply of the circuit as shown in Figure 7B. This
connection results in the proper phases for easy viewing on
the oscilloscope. Since the oscilloscope ground is connected
to the negative supply line, be certain there is ground isola-
15
FIGURE 8. INSTANTANEOUS POWER DISSIPATION TESTER
+15
+15
15
V
SENSE
I
SENSE
(from R
S
)
7
1
5
6
X1 4
7
1
5
6
4
X2
Y1
Y2
X
ANALOG
DEVICES
AD534
OUT
Z1
Z2
15
+15
V
O
BURR
BROWN
INA 117
BURR
BROWN
INA 117
OP AMP
UNDER
TEST
P
D
= 189
V
O
R
S
V
I
V
O
P
D
+V
S
R
S
1
A
V
= 0.053
Av = 1
V
S
+
O'SCOPE
V H
R
S
BYPASS
V
S

(SEE TEXT)
BYPASS
+V
S
14
15
12
13
14
15
12
13
10
11
8
9
6
7
4
5
2
3
0
1
10 20 30 40 50 60 70 80 90 100
PAI2 PLOT OF 25 C STEADY STATE SOA ON LINEAR GRAPH
FIGURE 7. OSCILLOSCOPE TESTING OF SOA
A
B
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within the 200 watt dissipation of the PA04, or less if elevated
temperatures are considered.
5.0 OTHER FACTORS FOR DETERMINING SOA FIT
Since different SOA limits are shown for different tempera-
tures, it is helpful to be able to predict the amplifer tempera-
ture. One factor that only the designer can defne is ambient
temperature. In particular, maximum ambient temperature.
Amplifer power dissipation will also be a factor in determining
case temperature. Equations for predicting power dissipation
maximums are discussed in the Apex Precision Power Hand-
book, General Operating Considerations, section 7.0, and the
equations are shown here for convenience:
Once worst case dissipation is known, use the heat sink
thermal resistance and ambient temperature to calculate
amplifer case temperature since SOA temperature limits are
based on case temperature.
P
D (OUT)MAX
=
2Vs
2
2
Z
L
Cos
, < 40
Cos] > 40
Vs
2

2Z
L
4

[ P
D (OUT)MAX
=
Z
L
=
|
Z
L|
P
TOTAL
= P
D(OUT)MAX
+P
D(IQ)
Effects of current limiting with reactive loads can also be
evaluated when plotting load lines. Current limit lines can be
drawn on the SOA representing current limit values. If reac-
tive loads exceed these limits, distortion will occur. Often an
inductive load causes what appears at frst to be crossover
distortion when viewing an amplifer output. In fact, what is
actually occurring is that the current peaks when voltage
transitions through zero and a light excursion into current limit
looks much like crossover distortion.
Foldover current limits can be plotted on SOA graphs point
by point as is done with load lines. Again, reactive loads must
ft well within current limits. This is especially important when
relaxation oscillation can occur if current limits are exceeded.
In such cases the foldover effect must be reduced or even
eliminated.

6.0 AUTOMATED LOAD LINES
For DC and sine wave outputs, use Power Design
1
to plot
a load line. Make sure the load line does not cross the short-
est time curve and that excursions beyond any other second
breakdown curve do not exceed the time label, and have a
duty cycle of no more than 10%.
1
available free from www.Cirrus.com.
IMPORTANT NOTICE
AN24
768 AN24U
AN24 Brush Type DC Motor
Drive with Power Op-Amps
1.0 AMPLIFIER SELECTION
One of the most entertaining moments as a power op amp ap-
plications engineer is when a customer calls up asking for an op
amp to drive a 24V, 2A motor and has already settled on a 5 amp
amplifer. Its just not that simple. This current rating could have
many meanings, and actually there are two current rating condi-
tions to be considered when designing a reliable application: stall
current and reversal current.
Reversing a motor is about the most stressful application to which
power op amps are subjected. Its important to establish from the
outset if it will be necessary to sustain reversals. Some applications
can disregard this; a good example being a simple speed control
for a motor always rotating the same direction.
1.1 STALL RESISTANCE
Every motor will be stalled. This is the required state of transition
to get a motor rotating. And it is doubtful any mechanical system
can be devised which is guaranteed to never jam.
A single operating point for the stalled condition can be plotted.
The location of the point is defned by several factors: 1) If the
product of current limit and stall resistance is greater than maxi-
mum output voltage swing ((Ilim*Rs)>Vomax) the amplifer output
will be at maximum swing; or 2) If the product of current limit and
stall resistance is less than maximum swing, then the amplifer
output voltage will be at the value of Ilim*Rs. To calculate dissipa-
tion, subtract this voltage from the supply voltage and multiply by
current limit: Pd = (Vs-Vo)*Ilim
Alternatively, stall resistance can be plotted as a load line on
the SOA graph. On the SOA graph, current limit should also be
plotted. This is useful for conditions where the amplifer output will
be attempting to go to some other value than full output voltage
under stall conditions. Remember, maximum dissipation occurs at
an output voltage one half way between zero and the supply rail.
Figure 1 shows just such an example of a calculation. This
example uses a PA12A along with a motor which has a 3.2 ohm
stall resistance and bipolar 50V power supplies. If we simply plot
the condition where the amplifer is against the rail, we have ap-
proximately 44V at the output and 13.8A of current fow. The supply
to output differential and current result is a dissipation of 6 * 13.8,
or 82.5W, which is within the amplifer SOA. If the amplifer output
voltage were commanded to one half supply rail or 25V under a
stalled condition, the power dissipation would be 195W, which is
beyond the continuous SOA.
This illustrates the value in plotting the stall resistance load line.
Both the low output and full output conditions are within the SOA,
but intermediate values create excessive dissipation and this is
immediately apparent by plotting the load line. The point where
the load line exceeds the 25C continuous SOA is a good value
for maximum acceptable current limit.
In summary, design for stalled conditions should at least plot
the resistive load line to determine proper setting of current limits.
If the load line completely falls within the SOA, then other fault
conditions of shorts from output to ground or output to either rail
will take precedence in determining current limit values in the event
these faults must be accounted for.
1.2 REVERSAL
Reversal brings the back EMF of the motor into the stress equa-
tion. The back EMF is equivalent to a new source of voltage with
a polarity such that it adds to the supply voltage and increases
voltage stress on the output devices. As in the stalled condition,
motor resistance also plays a part.
Determining back EMF may seem difficult, but most motor data
sheets shed some light on determining its value. Knowing the
motor resistance and current draw permits exact calculation of
back EMF: it is the applied voltage, less the drop across the motor
resistance. Worst case assumption for back EMF should assume
it could be equal to applied voltage, and this would be true for any
motor drawing negligible current.
The schematic in Figure 2 shows an example of what happens
to the circuit in Figure 1 during reversalassuming the amplifer
current limit is set at 3 amps. Motor operating current is a function
of load. So for this example, lets assume the motor requires 1A
under normal running conditions. Maximum output from the PA12
could be up to 45V. Subtract 3.2V for the drop across the motor
resistance for a back EMF of 41.8V. Upon command to reverse the
negative half goes into 3A current limit. The resulting voltage drop
across the motor resistance subtracts from the back EMF, providing
the values shown during the reversal. The dissipation during this
event is 246Wclearly outside the PA12 SOA. Motor reversal by
nature is a transient condition. If it can be assured the motor can
reverse within an amount of time equivalent to transient stress limits
on the SOA graph, then the application could be safe.
1.2.1 PLOTTING REVERSAL LOAD LINE
Just as stall load lines can be plotted, so can reversal load lines.
The process of plotting a worst-case reversal load line starts with
the assumption that back EMF is equal to maximum amplifer output
voltage. An even worse assumption is that it is equal to the supply
voltage of one of the rails.
Plot the load line by:
1. Calculate the drop across the motor resistance at various cur-
rents within the SOA.
5.0
3.0
2.0
1.5
1.0
.7
.3
10 20 25 30 35 40 50 60 70
S O
O
U
T
P
U
T

C
U
R
R
E
N
T

F
R
O
M

+
V

O
R

V

(
A
)
S
S
.5
t

=

1
m
s
s
t
e
a
d
y

s
t
a
t
e
15 80 100
10
15
T
C =
1
2
5
C
T
C =
2
5
C
T
H
E
R
M
A
L
t

=

5
m
s
t

=

0
.
5
m
s
FIGURE 1. EXAMPLE OF MOTOR DRIVE LOAD LINE ANALYSIS
+50
50
D1
D2
3.2 STALL
RESISTANCE
3.2
LOAD
LINE
T
C =
8
5
C
3A I
LIM
SECOND BREAKDOWN
STALL LOAD LINE
REVERSAL LOAD LINE
REVERSAL
WITH 3A
LIMIT
PA12
Brush Type DC Motor Drive with Power Op Amps
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2. Subtract that voltage from the back EMF to result in the ampli-
fer output voltage.
3. Take the resulting difference between supply rail and output
as the stress point.
Figure 1 also shows its reversal load line. This load line indi-
cates that it is not within the continuous SOA unless current is
limited to approximately less than 400mA. If this application were
required to tolerate reversal, an amplifer with better SOA should
probably be used.
Load lines that exceed the continuous SOA, but are within
transient SOA, may be safe if the time conditions are met with
certainty. This is difficult to assess, and usually requires a judge-
ment call when any signal other than pulse is present. In general,
as in any case, life is simpler and more reliable if we at least make
the effort to keep within continuous SOA limits.
1.3 NOMINAL OPERATING CONDITIONS
Nominal operating conditions can only be determined on a by
application basis. All motor data sheets shows torque and RPM
constants allowing the engineer to determine required voltage and
current once the load is known. The worst case normal operating
point will be when the amplifer output is halfway between zero
and the supply rail.
2.0 AMPLIFIER PROTECTION AND HEATSINKING
As has already been shown, the load lines must be within
the amplifers capabilities or current limit must be confgured to
restrict operation to within the SOA. However, the SOA shrinks
with increasing temperature. Therefore, either adequate (read:
generous) heatsinking must be provided for, or SOA analysis
should consider limits of higher case temperature curves. Using
standard heatsink formulae the exact amplifer case temperature
can be determined under any operating condition (as well as
junction temperature).
2.1 FOLDBACK CURRENT LIMITING
Current limit, as demonstrated, is truly a good thing and neces-
sary. But designers must not be lured into the attraction of using
foldback current limiting as available on PA10, PA12 and can be
used on PA04, PA05. Reason being that foldover current limiting
causes more problems than it solves when used with nonlinear
loads. For instance, with inductive loads (and motors are very
inductive), the amplifer can go into relaxation oscillation. And
with an inductive load, when the amplifer goes into current limit,
it generates a violent pulse all the way up to the supply rail (limited
only by fyback diodes, without which it would go beyond the rail).
If a designer insists on experimenting with foldover current
limiting, then it would be wise to plot the current limit line on the
SOA along with the expected load lines. If the load lines are within
the current limit boundaries, then youre OK. Keep in mind that
foldover current limiting slope can be varied and sometimes a
gentle foldover characteristic can provide adequate protection.
2.2 FLYBACK DIODES
Brush type DC motors generate a continuous pulse train of
inductive kick-back due to brush commutation. This inductive
kickback must be clamped within the limits set by the power
supply rails by fyback diodes as shown in Fig. 1.
Many amplifer schematics show these diodes internally, but
this does not mean they can be depended upon in motor drive
applications. In most bipolar, darlington, emitter-follower output
stages, these diodes are the substrate diodes of the darlington
output transistors. This causes the diodes to exhibit slow recovery,
which will in turn overheat under the stress of a continuous pulse
train of inductive kickback.
Amplifers with no diodes, or slow recovery diodes, internally
must have external fast or ultra-fast recovery diodes added. If
these are not available, then standard recovery is better than
nothing. The diodes must be rated for voltage well in excess of the
total rail-to-rail voltage. Current requirements are not demanding.
One amp types will suffice.
All Apex Precision Power amplifers require external fyback
diodes except the MOSFET output amplifers PA04, PA05, PA09,
PA19; and the PA02 and PA03 which are bipolar amplifers with
built-in high speed fyback diodes. In general, on any Apex Preci-
sion Power data sheet schematic or in the Apex Precision Power
data book, if the fyback diodes have a different part numeral than
the output transistor, then they are separate fast recovery diodes.
Diodes with the same part number as the output transistor are
slow recovery diodes and external additions will be needed. For
example in the PA12, the upper output transistor is Q2A and Q2B
and the fyback diode is D2. If youre not sure, there is no harm
in adding them even if they are not needed.
3.0 AMPLIFIER PERFORMANCE
3.1 VOLTAGE VS CURRENT OUTPUT BEHAVIOR
Voltage output confgurations are generally used for speed con-
trol. Although a voltage output confguration can be incorporated
within a larger current control loop. The importance of voltage
output in the amplifer itself relates to output impedance, which
will be very low. As such, the output voltage as seen on a scope
will generally be quiet and steady under steady state conditions.
Current output can be implemented as mentioned above with
a larger current sense loop that incorporates a voltage output
power amp. Alternatively, current output circuits can be imple-
mented within the feedback loop around the op amp alone. When
this is done, the amplifer apparently exhibits a very high output
impedance. A current source should do this by defnition. This is
mentioned because if the output of such a circuit is scoped, the
fyback pulses will be exaggerated by this high impedance a
perfectly normal behavior for current output.
There is no performance advantage in selecting voltage or cur-
rent output, at least not due to power op amp circuit choice alone.
Many other factors will play a part in which choice provides the
best performance. In general, without using larger control loops,
the voltage output confguration is preferred for speed control,
and the current output for torque control.
45V
R
W
= 3.2ohms
I = 1A
EMF
41.8
R
W
3.2ohms
+
MOTOR
MODEL
STEADY STATE REVERSAL
+50
50
R
CL
+
R
CL
+45V
1A
41.8
+3.2V
+50
50
R
CL
+
R
CL
3A
41.8
9.6V
+ 32.2V
V
S
V
O
= 82.2V
Pd = 82.2 x 3 = 246.6W
FIGURE 2. MOTOR REVERSAL
1A
AN25
770 AN25U
AN25 Driving
Capacitive Loads
culation. For details on derivation of this formula see
For capacitive load applications this formula reduces to:
STEP 5: Summarize what we know and pick power op amp.
+/-Vs = +/-200Vdc
S.R. = 11.3V/s
Iop = 120mAp
Vop = 180Vp
P
DOUT MAX
= 17W
In viewing the Apex Precision Power High Voltage Se-
lector Guide there is only one likely candidate for this
designPA85.
STEP 6: Review the chosen amplifers data sheets for details.
Figure 1: Contains relevant excerpts from the PA85
data sheet.
Figure 1A: From the output specifcations, a worst
case saturation voltage of 10V at 200mA is identifed.
Therefore we can meet 180Vp out at 120mAp without
a problem.
Figure 1B: From the power response curve we see
360Vpp at 10KHz is within the power response curve
for any value of Cc (PA85 compensation capacitor).
Figure 1C: Since we want 180Vp out for 10Vp in we
will be operating at a gain of 18. This is close enough
to 20 to choose Cc = 10pF and Rc = 330. This will
maximize small signal bandwidth as well as slew rate
should a last minute decision require more performance
out of the design.
Figure 1D: At Cc =10pF the slew rate is about 400V/s,
so there is no question about meeting the requirement
for an 11.3V/s slew rate.
Figure 1E: At a closed loop gain of 18, (25 dB), it
can be determined that for Cc =10pF the closed loop
bandwidth of this circuit (fcl) is about 2MHz. This frst
check says not only can a 10KHz sinewave be tracked
in the large signal domain, but the PA85 will also have
enough bandwidth to have a fat response at 10KHz in
the small signal domain.
Figure 1F: From our previous calculation P
DOUT MAX
=
17W. An Applications Engineers rule of thumb for power
derating curves works as follows:

For a 25C ambient temperature you can fnd a heatsink that
will allow you to keep the case temperature at 85C using free
air convection cooling.
Therefore, 17W output power dissipation almost intersects
with the Tc = 85C line on the power derating curve. This
means our frst look says we should be able to heatsink the
PA85 for this design.
Now it would seem the work is done and you can proceed
to build a breadboard or commit to printed circuit board layout.
But frst you must proceed to look at other key issues for driving
capacitive loads with power op amps such as stability.
1.0 INTRODUCTION
High voltage power op amps are often selected to drive ca-
pacitive loads, such as PIEZO TRANSDUCERS, CAPACITORS,
ELECTRO-LUMINESCENT DISPLAYS, ELECTROFLUORES-
CENT LIGHTING, ELECTROSTATIC DEFLECTION, etc. There
are some special considerations when designing circuits to
meet your high voltage needs.
We will look in detail at the selection of the power op amp,
stability considerations, power dissipation in the op amp and
heatsink selection, support components for the circuit, and
power supplies and their effect on circuit performance. When
we complete these areas of investigation we will look at some
alternative power op amp circuits for attaining high voltage
control across capacitive loads.
The format of our information will be defnition by example
along with generic formulae for your specifc design.
2.0 EXAMPLE DESIGN FOR DRIVING A CAPACITIVE LOAD
GIVEN: +/-Vs= +/-200Vdc
frequency = DC to 10KHz (sinewave)
V
IN
= +/-10V
piezo load with CL = 10.6nF
V
OUT
= 360Vpp
Tambient = 25C, free air convection cooling
only
Inverting gain okay
FIND: Power op amp, heatsink and recommended
schematic for piezo drive.
SOLUTION: Sections 2.1 thru 2.6 will provide a detailed,
logical approach to designing a solution for
this capacitive load drive problem.
2.1 POWER OP AMP SELECTION
STEP 1: Defne capacitive load. Here we are given CL = 10.6nF
STEP 2: Calculate large signal response (slew rate) using high-
est frequency and largest voltage swing. The required
slew rate to track a sinewave at a given frequency for
a given output amplitude is as follows:
S.R. = 2 f Vop (1 X 10
6
)
Slew Rate [V/s] = 2 X X frequency X V
OUT
peak X (1 X
10
6
)
S.R. = 2 10KHz 180 (1 X 10
6
) = 11.3V/s
STEP 3: Calculate maximum current requirements. This will
occur at highest frequency with capacitive loads.
METHOD 1: Calculate Xc @ highest frequency.
METHOD 2: Use highest slew rate and largest voltage swin
STEP 4: Do a frst pass worst case power dissipation cal-
Xc =
1
2 f CL
Xc =
1
2 10 KHz 10.6nF
= 1.5K
Iop =
Vop
Xc
= 120mAp =
180V
1.5K
Iop = CL
dV
dt
Iop = 10.6nF
11.3V
s
= 120mAp
Driving Capacitive Loads
P
DOUT
max =
Vs
2
2 ZL
[
4
cos
]
4 Vs
2
2 Xc
=
4 (200)
2
2 1.5K
= 17W P
DOUT
max =
MAY 2009
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B
A
0 25 50 75 100 125 150
CASE TEMPERATURE, T
C
(C)
0
8
24
32
POWER DERATING
O
U
T
P
U
T

S
T
A
G
E
I
N
T
E
R
N
A
L

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N
,

P

(
W
)
16
40
FIGURE 1F
10 10M
FREQUENCY, F (Hz)
20
0
60
120
O
P
E
N

L
O
O
P

G
A
I
N
,

A

(
d
B
)

20
40
80
100
100 1K 10K .1M 1M 100M
FIGURE 1E
C
C
= 10pf
C
C
= 3.3pf
C
C
= 68pf
AV
CL
fcl
0 60
C
(pf)
100
SLEW RATE
S
L
E
W

R
A
T
E
,

(
V
/
m
S
)
200
1000
90 15 45
500
30 75
FIGURE 1D
1
2 3
4
5
6 7
8
CL
+Vs
+IN
Vs
COMP
OUT
R
CL
IN
C
C
COMP
R
C
Gain C
C
R
C
1 68pf 100
20 10pf 330
100 3.3pf 0
C
C

PHASE COMPENSATION
FIGURE 1C
EXTERNAL
CONNECTIONS
TOP VIEW
500K 5M
FREQUENCY, F (Hz)
25
125
500
O
U
T
P
U
T

V
O
L
T
A
G
E
,

V

(
V

)

O

100
250
POWER RESPONSE
P
P

75
50
1M
C

=

3
.
3
p
f

C

C

=

1
0
p
f

C

C

=

6
8
p
f

C

R = 2K
L
2M 50K 100K 200K
FIGURE 1B
FIGURE 1. PA85 DATA SHEET EXCERPTS
OUTPUT MIN TYP MAX UNITS
VOLTAGE SWING I
O
= 200mA Vs 10 Vs 6.5 V
VOLTAGE SWING I
O
= 75mA Vs 8.5 Vs 6.0 V
VOLTAGE SWING I
O
= 20mA Vs 7.5 Vs 5.5 V
C
= 85C 200 mA
SLEW RATE, A
V
= 20 C
C
= 10pf 400 V/s
SLEW RATE, A
V
= 100 C
C
= OPEN 1000 V/s
CAPACITIVE LOAD, A
V
= +1 Full Temperature Range 470 pf
C
= 10pf, 2V step 1 s
CL
= 0 50
FIGURE 1A
2.2 SMALL SIGNAL STABILITY
Figure 2 is a complete schematic of our PA85 drive circuit.
The gain of -18 will give us 360Vpp out for 20Vpp in. We will
now look at the details for selecting stability components Rn,
Cn, and CF.
2.2.1 MODIFIED AOL FOR CAPACITIVE LOADS
Figure 3 illustrates how the amplifers Aol curve gets modi-
fed by Ro, the amplifers unloaded output impedance, and CL,
the capacitive load. Output impedance, Ro, of the amplifer,
is fat within the bandwidth of the amplifer and predominantly
resistive. Refer to Apex Precision Power Application Note 19
for a detailed discussion of this issue.
AN25
772 AN25U
Figure 4 lists high voltage Apex Precision Power amplifers
and boosters most commonly used to drive capacitive loads
and their corresponding output impedance.
OP AMP OR BOOSTER OUTPUT IMPEDANCE
PA41 150 ohms
PA81J 1.4K-1.8K ohms
PA82J 1.4K-1.8K ohms
PA83 1.4K-1.8Kohms
PA84 1.4K-1.8K ohms
PA85 50 ohms
PA88 100 ohms
PA89 100 ohms
PB50 35 ohms
PB58 35 ohms
FIGURE 4. OUTPUT IMPEDANCE HIGH VOLTAGE OP AMPS
AND BOOSTERS
2.2.2 STABILITY PLOTS
Figure 5 illustrates the magnitude plot for stability needed to
analyze and check for good stability on our PA85 drive circuit.
The low frequency pole for the Aol curve can be determined
from the Small Signal Response curve, and the high frequency
pole can be extrapolated from the Phase Response curve in
the Apex Precision Power data sheet for the PA85.
STEP 1: Modify Aol due to capacitive load and amplifers
output impedance:
STEP 2: Check 1/ for resistive feedback alone:
1/ [1/(beta)] is the small signal AC gain at which the
op amp runs. Refer to Apex Precision Power Applica-
tion Note 19 for details. First order stability criteria
for magnitude plots states that the Rate-of-Closure
(difference between the slopes of Modifed Aol and
the 1/ plot) be 20dB per decade at fcl. Refer to Apex
Precision Power Application Note 19 for details on Rate-
of-Closure. With AC small signal gain set only by RF
and RI the 1/ plot will be a fat line at 25.6dB. At the
intersection of modifed Aol and 25.6dB the Rate-of-
Closure will be 40 dB per decade indicating marginal
stability and potentially destructive oscillations.
FIGURE 2. PA85 PIEZO TRANSDUCER DRIVE
+200V
200V
200V
+200V
*
*
R
CL
4.64
RF
90K, 1/2W
CF
18pF
4.7F .1F
.1F
4.7F
10pF
Cc
330
Rc
CL
10.6nF
P6KE250
P6KE250
Rn
900
RI
5K
Cn
.018F
1N4148's
DC to
10KHz
PA85
V
IN
10V
*INTERNAL TO PA85
+
+
V
OUT
FIGURE 3. CAPACITIVE LOADING
RF
RI
CL
UNITY GAIN STABLE AMPLIFIER
UNSTABLE 40 dB/DECADE WITH CL
Ro
10 100 1K 10K .1M
100
80
60
40
100
0
FREQUENCY, F (Hz)
1M 10M
120
O
P
E
N

L
O
O
P

G
A
I
N

A
O
L

(
d
B
)
1
20
UNSTABLE
STABLE
1/ Aol
Aol

w/CL

AV
CL
fp2 =
1
2 (Ro + R
CL
) CL
=
1
2 (50+ 4.64) 10.6nF
= 275 KHz
fp4 = 10MHz pole from amplifier's original Aol plot (fp3)
STEP 3: Add Noise Gain Compensation as a frst step towards
good stability:
Rn and Cn will form a noise gain compensation network
which will raise the gain of the 1/ plot without directly
affecting the V
OUT
/V
IN
relationship. Refer to Apex Preci-
FIGURE 5. MAGNITUDE PLOT FOR STABILITY
(PA85 PIEZO TRANSDUCER DRIVE)
.1 1 10 100 1K 10K 1M 100M
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY, F (Hz)
G
A
I
N

(
d
B
)
220
fp1
V
O
/ V
IN

PA85 Aol w/Cc = 10pF, Rc = 330
fcl
fz1
100K
fp5
1/ RF/RI
fz2
fp3
fp6
fp2
25.6
10M
fp4
275K
MODIFIED Aol DUE TO CL = 10.6nF & Ro = 50
1/ RF/Rn
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STEP 5: Review of rules for open loop phase plots:
1) Poles in the 1/ plot become zeros in the open loop
stability check.
2) Zeros in the 1/ plot become poles in the open loop
stability check.
3) Poles and zeros in the Aol curve or modifed Aol curve
of the op amp remain respectively poles and zeros in
the open loop stability check since the op amp Aol
curve is an open loop curve already.
4) Phase for zeros is represented by a +45 degree phase
shift at the frequency of the zero with +45 degree per
decade slope, extending this line with 0 degree and
+90 degree horizontal lines.
5) Phase for poles is represented by a 45 degree phase
shift at the frequency of the pole with a 45 degree per
decade slope, extending this line with 0 degree and
90 degree horizontal lines. Refer to Apex Precision
Power Application Note 19 for further details.
STEP 6: Plot open loop phase using information from magni-
tude plot: Figure 6 is the open loop phase plot for our
PA85 drive circuit.
Notice in Figure 5 that the 1/ plot continues beyond fcl all
the way until it intersects at 0dB forming fz2 in the 1/ plot.
An amplifer will not run in an AC small signal gain of less
than 0dB. You must account for an additional high frequency
pole in the open loop phase check. This pole is easily read
sion Power Application Note 19 for details.
Noise Gain equations:
High frequency gain = RF/Rn = 90K/900 = 100 ==>
40dB
fz1 ==> Can be obtained graphically using +20dB per
decade slope starting at the intersection of fp5 and the
high frequency gain of the noise gain compensation
and proceeding towards the DC gain.
Even though we have raised the higher frequency
portion of the 1/ curve to 40dB, it will still intersect
the modifed Aol at 40dB per decade Rate-of-Closure.
STEP 4: Add feedback zero (1/ pole) to 1/ plot to gain best
AC small signal stability (Refer to Apex Precision Power
Application Note 19 for details):
Now at fcl, you have the desired 20dB per decade
Rate-of-Closure and good stability according to our frst
order criteria for magnitude plots. You will now need to
plot the open loop phase plot for a complete stability
check.
P
H
A
S
E

S
H
I
F
T

(
d
e
g
r
e
e
s
)

FREQUENCY, F (Hz)
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 1 10 100 1K 10K 100K 1M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 10
180
135
90
45
0
+45
+90
+135
+180
FIGURE 6. OPEN LOOP PHASE CHECK FOR STABILITY
(PA85 PIEZO TRANSDUCER DRIVE)
MARGIN = 45
1 100 100K 10M
10M
1K 10K
fcl
1M 100M
fp5
fp6
fp2
fz2
fp4
fp1
fz1
fp5 =
1
2 Rn Cn
=
1
2 900 .018F
= 9.8 KHz
fp6 =
1
2 RF CF
=
1
2 90k 18pF
= 98 KHz
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graphically from Figure 5 rather than calculating it from lengthy
derivations.
A review of Figure 6 shows graphical addition of the contribu-
tions from all poles and zeros to yield a net open loop phase
plot. The phase margin from DC to fcl is never less than 45
degrees which implies good stability for this circuit.
2.2.2.1 RULES OF THUMB FOR STABILITY PLOTS
Now that we know we have good stability, lets return to the
magnitude plot in Figure 5 for a few handy rules of thumb:
1) Think of open loop phase when you play with the 1/
plot: Notice that fp1 (pole in open loop) is spaced about
a decade away from fz1 (pole in open loop). If you dont
add fp5 (zero in open loop) within a decade of fz1, (pole
in open loop) the open loop phase margin will dip to less
than 45 degrees.
2) As you run out of loop gain (difference between Aol curve
and 1/ plot), keep poles and zeros one-half to one de-
cade away from zero loop gain. Notice that fp6 is about
one-half decade away from the modifed Aol curve near
fp2. This allows Real World Aol curves and component
tolerances to stack against you without creating stability
nightmares.
3) Always design your circuits, using these stability tech-
niques, for 45 degrees of phase margin in the open loop
phase check for stability. This is because the frst order
linear approximations for phase have a six degree er-
ror. As well, there is no guarantee you will consistently
receive op amps with the typical Aol graph.
In a typical design procedure, you will plot magnitude plots
for stability frst, do an open loop phase plot, and then return
to calculate fnal component values to create the desired
magnitude plot that yields 45 degrees open loop phase margin
for stability.
Refer to Apex Precision Power Application Note 19 for handy
tips and short cuts for plotting magnitude and phase plots.
2.2.3 REAL WORLD STABILITY TEST
Once a circuit is built, there is a relatively easy test you can
run to verify if the predicted open loop phase margin made it
from design to the real world.
Figure 7 details the Square Wave Test for measuring open
loop phase margin by closed loop testing. The output amplitude
of the square wave is adjusted to be 2Vpp at a frequency of
1 KHz. The key elements of this test are to use low amplitude
(AC small signal) and a frequency that will allow ease of read-
ing when triggered on an oscilloscope. Amplitude adjustment
on the oscilloscope wants to accentuate the top of the square
wave to measure easily the overshoot and ringing. The results
of the test can then be compared to the graph in Figure 7 to
yield a reading for open loop phase margin.
A complete use of this test is to run the output symmetrical
about zero with +/-1V peak and then re-run the test with various
DC offsets on the output above and below zero. This will check
stability at several operating points to ensure no anomalies
show up in feld use.
Refer to Apex Precision Power Application Note 19 for more
involved closed loop tests for measuring open loop phase
margin and checking real world stability.
2.3 CLOSED LOOP RESPONSE
From Figure 5 the V
OUT
/V
IN
relationship for our PA85 circuit
is seen as fat from DC to 100 KHz, where it begins to roll at
20dB per decade. It continues until we reach 1.33 MHz where
it rolls off at 40dB per decade until reaching 10MHz, where
our slope changes to 60dB per decade.
The V
OUT
/V
IN
phase shift for any given frequency is given by
the following:
where f = frequency of interest for phase shift
FIGURE 7. SQUARE WAVE TEST
2 1 4 3 6 5 8 7 0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
V
O
,

R
E
L
A
T
I
V
E

O
U
T
P
U
T

T
O

A

S
T
E
P

F
U
N
C
T
I
O
N

I
N
P
U
T

9 10
13 0.2*
35 0.4*
40 0.6*
90 1.4*
64 1.0*
52 0.8*
77 1.2*
* OPEN LOOP PHASE MARGIN AND DAMPING FACTOR
w
n
t
V
OUT
RF
RI
LOAD
CF
2vpp
1KHz
V
IN
Phase Shift = Tan
1 f
fp6
Tan
1 f
fcl
Tan
1 f
fp4
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are rated at 30C/W. When the case of the amplifer must be
kept below 85C, this imposes a maximum power dissipation
of 2W even with an ideal ambient temperature of 25C. At
27W our PA85 would burn up very quickly without a heatsink.
The PA85 data sheet tells us the AC thermal resistance is
2.5C/W. We will allow 0.2C/W for R
CS
and use the following
to determine a maximum heatsink rating.
Select Apex Precision Power HS03; R
SA
= 1.7C/W with
forced air fow at 100 ft/min.
As a last check, multiply the total power times the sum of the
thermal resistance of the heatsink and the mounting interface
and add to ambient temperature to verify the case temperature
does not exceed 85C.
27W (1.7C/W + 0.2C/W) + 25C = 76.3C
Refer to Package and Accessories Information section of
Apex Precision Power Amplifer Handbook.See Apex Precision
Power catalog GENERAL OPERATING CONSIDERATIONS
for details on heatsinking and mounting the amplifer.
2.5 HIGH VOLTAGE AMPLIFIER SUPPORT COMPONENTS
High voltage op amps require some special considerations
when selecting support components for completion of your
circuit design. The following list covers these critical areas of
concern:
1) ESD Handling Precautions:
All Apex Precision Power high voltage amplifers are rated
Class 1 for ESD sensitivity, as defned in MIL-H-38534. This
requires that proper ESD handling precautions be observed
from receiving through manufacturing until the device is
installed in a properly designed circuit. Areas which will
require strict ESD control include, but are not limited to,
personnel, tabletops, stocking containers, foors, soldering
irons, and test equipment.
2) Input Protection (Refer to Figure 10):
Most high voltage amplifers have a differential input volt-
age rating of +/-25V. It is easier on high voltage amplifers
to cause differential input overvoltages than on lower volt-
age op amps. These overvoltages on the input can occur
during power cycling or can be transients fed back through
CF from the output to the input.
The input diodes, Dp, clamp the maximum input differential
voltage to +/-1.4V while allowing sufficient differential voltage
for overdrive when demanding maximum slew rate from the
amplifer. The diodes shown are low capacitance fast signal
diodes. If lower leakage and lower capacitance diodes are
desired, J-FETs may be connected as diodes as shown.
3) Output Diodes (Refer to Figure 10):
MOSFET high voltage amplifers have internal, intrinsic
diodes that are connected from the output to each supply
rail. High voltage Bipolar amplifers do not have these diodes
and must be added externally as shown. The MOSFET
amplifers internal diodes are sufficient for an occasional
transient that may be created in a piezo drive situation where
the piezo element is stressed mechanically, thereby creating
an electrical voltage. For applications where there is poten-
For our upper frequency of interest of 10 KHz lets see what
the V
OUT
/V
IN
phase shift is:
The formula above can be expanded to include any number
of poles. If the V
OUT
/V
IN
relationship has zeros simply add the
following for each zero:
2.4 POWER DISSIPATION AND HEATSINKING
Power dissipation inside the amplifer consists of two com-
ponents, P
DQ
, quiescent power dissipation, and P
DOUT
, output
stage power dissipation. Simply compute P
DQ
= Iq[+Vs - (-Vs)]
and add the worst case power dissipation for the output stage to
this to form P
DINT
, total internal power dissipation. Figure 8 shows
the Thermo-Electric Model that is applicable for this situation.
In our PA85 design case we have AC power dissipation in
the output stage. From Section 2.1, Step 4, that power dis-
sipation is:
Quiescent power is:
P
DQ
= I
Q
[+V
S
(V
S
)] = 25mA [+200 (200)] = 10W
There are two thermal requirements we must meet in this
application. First, the case temperature must be kept below
85C. Second, the junction temperature must be kept below
150C. We know the application is dissipating a total of 27W,
but the data sheet contains three different thermal resistance
ratings which vary substantially. The frst is an AC rating where
the two output transistors share the heat load at a frequency
of 60Hz or greater. When the power is dissipated in mainly
one output transistor, use the DC thermal resistance. The last
rating is applied only if no heatsink is used.
This is a rare practice with power op amps. Let us briefy pursue
the possibility we might be able to not heatsink the amplifer
in this application. Figure 9 models this case. TO-3 packages
FIGURE 9. THERMOELECTRIC MODEL (NO HEATSINK)

R
JA
FIGURE 8. THERMOELECTRIC MODEL
T
A
T
C
R
CS
T
S
T
J
= P
DINT
(R
JC
+ R
CS
+ R
SA
) +T
A
P
DINT
T
J
R
SA
R
JC
+Tan
1 f
fz
; where fz is the frequency of the zero
P
DOUT
max =
4 Vs
2
2 Xc
=
4 (200)
2
2 1.5K
= 17W
R
SA
T
J
T
A
PD
INT
(max)
R
JC
- R
CS
(150 25)C
27W
2.5C/W 0.2C/W
R
SA
1.9C/W
Phase Shift = Tan
1 10 KHz
100 KHz
Tan
1 10 KHz
1.33MHz
Tan
1 10 KHz
10MHz
= 6.2 degrees
AN25
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tial for sustained high energy fyback, in ATE applications,
where everything that is not supposed to happen usually
can and does, or in applications where Kilovolt fashovers
can occur and be inmpressed onto the amplifers output, it
is recommended to use fast (500nS or less depending upon
the anticipated fyback energy frequency) reverse recovery
diodes, DFB, external to the amplifer. Remember to size the
diodes for a Peak Reverse Voltage rating of at least the rail
to rail supplies the amplifer is operating at (for Vs=+/200V
==> 400V Peak Reverse Voltage rated diode).
4) Transient Voltage Suppressors (See Figure 10):
Transient Voltage Suppressors, V
TR
, can be added to the
supply lines to provide protection from undesired transients
on the power supply line. The frst is power supply overvolt-
age on power cycling. Secondly, when energy is dumped
into the supplies from DFB, if the power supply terminals
at the amplifer do not look like a low impedance for the
frequency of that energy, the amplifer could become over-
voltaged. Transient suppressors, such as TRANSZORBS,
manufactured by General Semiconductor Industries, Inc,
will provide a low impedance path for this energy. If you
use unipolar transient suppressors, they will prevent polar-
ity reversal across the amplifer since they will become a
forward biased diode if supplies are reversed.
Selection of the transient suppressors may require a
series string of devices to reach the desired reverse stand-
off voltage rating for higher voltage op amps. Choose the
transient suppressor for a reverse stand-off voltage slightly
greater than the maximum DC or continuous peak operat-
ing voltage level. This selected device will then have an
actual breakdown voltage that is typically 1.1 to 1.36 times
higher. For example, a P6KE250 has a reverse stand-off
voltage of 202V with a breakdown voltage of 225V to 275V.
Herein lies the trade-offs of transient suppressors. They are
excellent devices with a sharp breakdown curve and can
dissipate large amounts of power for short periods of time.
The problem is the exact breakdown voltage is not a tightly
controlled parameter for any given model.
A typical design dilemma is the case where an engineer
desires to use a part at its full power supply rating and still
provide transient voltage protection on the supply lines.
Now you ask, how high is Apex Precision Powers Absolute
Maximum Rating for Supply Voltage, REALLY? Well, the
guaranteed Absolute Maximum Rating for Supply Voltage is
exactly what our vendors guarantee to us. Lawyers aside, it is
known in the electronics industry that a 400V transistor may
actually breakdown at 500V from a given lot. In a nutshell,
you are in no-mans land above the Absolute Maximum Rat-
ing; however, it is much better to limit the transient voltages
to as low as possible than to not limit at all!
5) Power Supply Bypassing (See Figure 10):
The rule of thumb is .1F ceramics directly at the op amp
with 10F/Ampere of peak output current in parallel within
2 inches or so of each amplifer. Many of the high voltage
amplifers are less than 200mA and the .1F ceramic is all
that will be needed. In cases of PA89, +/600V supplies, .01F
seems to be more readily available and this is adequate for
high frequency bypassing on the power supply line. Watch
the voltage ratings for these capacitors!
6) Compensation Capacitor and Resistor (See Figure 10):
Cc must be rated for the rail-to-rail supply voltage at
which the amplifer is operating. In this case a 1200V rating.
It is recommended that the compensation capacitor be a
temperature stable capacitor for reliable performance over
temperature. Mepco / Centralab, Inc, series D and S type
capacitors are available in 50Vdc through 6KVdc ratings
in various temperature characteristics.
Rc will normally see little or no voltage since most of
the voltage stresses will be across Cc. Rc then can be a
standard 1/8W metal flm resistor.
7) Feedback and Input Components (See Figure 10):
RI will generally have little voltage stress or power dissi-
pation since most input signals are less than 10 volts peak.
Standard metal flm resistors will work fne.
CF can have up to one supply impressed across it. In
this case it would need to be a 600Vdc minimum rated
capacitor.
RF1, RF2, and RF3 will need some special consider-
ations. Power dissipation will become of prime importance
since up to one of the supply rails can be impressed across
these resistors at a given time. This could yield power dis-
sipations of: P
D
= Vs
2
/ RFeq. The second consideration is
voltage coefficient of resistance. This is a parameter that
defnes how a resistor changes its resistance with applied
voltage. At low voltages this characteristic is not a dominant
factor. At higher voltages it can become a more signifcant
factor causing reductions in gain for a given resistor ratio
or increased distortion. Dale RNX, ROX, FHV, MVW, and
HVX series resistors are well characterized for high voltage
use. The power dissipation factors and voltage coefficient
of resistance may require several resistors to be used in
series in the feedback path of the op amp.
8) Current Limit Resistor (See Figure 10):
Remember that all the load current fows through the
current limit resistor, R
CL
, and therefore size it according to
the value of current limit, Ilim, by P
D
= (Ilim
2
)(R
CL
). Maximum
voltage stress across R
CL
will be about +/-.7V for most am-
plifers. Check the Current Limit section of the applicable
data sheet for exceptions to this.
9) PWB Layout:
Higher voltages will require wider spacings between
traces on a printed circuit board layout as well as spacings
between ground planes and other conductive layers. Mil-
Std-275 provides some guidelines in these areas.
FIGURE 10. HIGH VOLTAGE SUPPORT COMPONENTS
+600V
600V
600V
+600V
R
CL
RF1
CF
Cc Rc
RI
V
IN
Dp
Dp
Dp
Dp
1N4148
or
1N914
RF2 RF3
C
BP
V
TR
V
TR
C
BP
DFB
DFB
V
O
PA89
RFeq
OR
2N4416
or
2N5457
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FIGURE 12A: R
ISO
& CL
R
ISO
CL
RO
VO
fp =
1
2 CL (R
O
+ R
ISO
)
fz =
1
2 R
ISO
CL
RG
+130V
30V
RG
21.5K
PB58
Cc
5pF
CL
26F
R
ISO
5
R
CL
.3 2W
FIGURE 12B: PB58 w/ R
ISO
& CL
P
H
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S
E

S
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T

(
d
e
g
r
e
e
s
)
FREQUENCY, F (Hz)
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
fp
fp3
fp2
FIGURE 14. OPEN LOOP PHASE PLOT FOR STABILITY CURVE 1 (w/o R
ISO
)
fp1
fcl1 MARGIN = 0
FIGURE 11. PA85 PSR
1 10 100 1K 10K .1M 1M
140
120
100
60
80
20
40
94.5
PA85
P
O
W
E
R

S
U
P
P
L
Y

R
E
J
E
C
T
I
O
N
,

P
S
R

(
d
B
)

FREQUENCY, F (Hz)
120
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Do not plug or unplug an amplifer into a live, powered
socket. The transients generated can destroy the high volt-
age amplifer.
Do not use fuses in the power supply lines of high voltage
amplifers or ever power them with one supply disconnected
and no path to ground for that disconnected power supply.
This can lead to a sneak path for permanent destruction on
several of the high voltage amplifers.
2.6 POWER SUPPLIES
2.6.1 POWER SUPPLY REJECTION
Often times high voltage amplifers require the use of either a
switching power supply or a simple AC full-wave bridge rectifed
supply (make real sure you use transient suppressors if you
use this type of supply). The question then is asked what will
be the effect on the output of the amplifer due to the ripple of
the power supply?
Figure 11 (previous page) is the Power Supply Rejection
curve for the PA85. We will use this and our familiar circuit of
Figure 2 to understand power supply ripple effect on ampli-
fer output. Figure 11 is a referred-to-input specifcation. Lets
assume there is a 1Vpp, 120Hz ripple on the power supply
line. From Figure 11 this implies PSR of 94.5dB. Since this is
a rejection curve, the gain is actually -94.5dB which is a gain
of .000018836. This gain times 1Vpp on the power supply line
means you will see .018836mVpp appear as an input offset
10) Probing, Plugging and Powering:
Be extremely careful when probing a high voltage amplifer
with the power on. An inadvertent slip of a probe can destroy
a high voltage amplifer. There are often compensation pins
adjacent to power supply pins. Those compensation pins
are often connected to the gates of MOSFETs which do not
take kindly to the full power supply being impressed upon
them.
FIGURE 13. R
ISO
& CAPACITIVE LOAD EFFECTS
.1 1 10 100 1K 10M 100M
0
20
40
60
80
100
120
140
160
180
200
G
A
I
N

(
d
B
)
220
240
PB58 AV
CL
PB58 Aol
1M
FREQUENCY, F (Hz)
75
fp
fp1
fz
fcl1
fp2
fp3
2
10K
153
MODIFIED Aol w/CL = 26mf, R
ISO
= 5, R
O
= 35W 2
MODIFIED Aol w/CL = 26mf, R
O
= 35 1
100K
fcl2
1
P
H
A
S
E

S
H
I
F
T

(
d
e
g
r
e
e
s
)
FREQUENCY, F (Hz)
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
MARGIN = 90
FIGURE 15. OPEN LOOP PHASE PLOT FOR STABILITY CURVE 2 (w/R
ISO
)
fcl
fz1
fp1
fp
fp2
fp3
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FIGURE 16. PB58 PIEZO DRIVE w/R
ISO
+15V
15F
100K
10K
V
IN
3
2
100K
.1F
LF355
A1
6
4
.1F
15V
15V
100K
R
ADJ
.1F
10K
1K

3
2

5600pF
15V
4
7
7
LF355
A2
.1F
+15V
PB58
A3
4
5
3
6
+130V
.1F 22mF
22F
30V
.1F
8
7
2
R
CL
.3 2W
21.5k
RG 1/2W
C
C
5pF
1N6286
MUR120
5
20W
R
ISO
CL

26F
V
OUT
1N6301
56pF
100K
1/4W
1N4148's
.1F
OFFSET
+
+
MUR120
voltage in the circuit. At a gain of 19 this means our output will
see .358mVpp ripple at 120Hz due to power supply fuctuations.
2.6.2 HIGH VOLTAGE POWER SUPPLIES
See the last few pages of the ACCESSORIES INFORMATION
data sheet for a list of manufacturers of high voltage supplies.
As a group, these vendors offer AC and DC inputs, standard
and custom units in linear and switching topologies. No matter
what supply you use, check it for possible overshoot at power
up, power down and even power cycling. Beware that many high
voltage supplies feature foldback or foldover current limiting. In
these circuits, current limit is reduced at low voltages compared
to full output voltage. Current sources in Apex Precision Power
high voltage amplifers draw their rated quiescent current at
somewhere around half their minimum supply voltage rating.
For example, the PA85 is likely to draw over 20mA as soon as
the supplies reach +/-7 to 10V. If a foldback feature does not
allow this operating point, the system will latch up.
3.0 HIGH VOLTAGE AMPLIFIER VARIATIONS
3.1 RESISTOR ISOLATION FOR CAPACITIVE LOADS
In Section 2.2.2 one method for stabilizing capacitive loads
FIGURE 18. COMPOSITE MAGNITUDE PLOT FOR STABILITY
.1 1 10 100 1K 10K 1M 10M 100M
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY, F (Hz)
G
A
I
N

(
d
B
)
220
240
100K
V
OUT
/V
IN
29.4K
fcl
1/
COMPOSITE Aol
FIGURE 17. CREATION OF COMPOSITE Aol
.1 1 10 100 1K 10K 1M 10M 100M
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY, F (Hz)
G
A
I
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(
d
B
)
220
240
100K
PB58 AV
CL
LF355 Aol
COMPOSITE Aol
was discussed. There is another common way to isolate ca-
pacitive loads and thereby acquire good stability.
Figure 12A (back 2 pages) illustrates a technique for isolating
the capacitive load through the use of R
ISO
. This isolates the
point of feedback, where RG is connected, from the capaci-
tive load. The addition of R
ISO
adds a zero in the modifed Aol
plot to counteract the pole formed by Ro and CL. Figure 12A
also contains the equations for the modifed Aol curve defn-
ing fp and fz.
Figure 12B (back 2 pages) will be part of a real world design
for a PIEZO DRIVE CIRCUIT. Here a PB58 will be required to
drive a 26F capacitive load. Figure 13 (previous page) illus-
trates the modifed Aol curve with and without the use of Riso.
From Figure 14 (back 2 pages) we see 28 degrees of phase
margin without R
ISO
. However, in Figure 15 (previous page) we
have 90 degrees of phase margin through the use of R
ISO
.
STEPS FOR CALCULATING R
ISO
: (See Figure 13, previous
page)
STEP 1: Calculate initial fp: Use Ro and CL which are given
by virtue of the load for the application and the choice of
power op amp. Plot location of fp.
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780 AN25U
STEP 2: Graphically choose fz: From plot of fp and fp1 you
can see a 40 dB/decade slope heading towards 0 dB gain.
Choose fz at a location such that it will change slope of
modifed Aol from 40 dB/decade to 20 dB/decade for at
least a decade above AV
CL
and within a decade of fp1.
STEP 3: Calculate fnal value for R
ISO
: Calculate from formula
for fz in Figure 12A the value for R
ISO
from fz location in Figure
13. Recalculate fnal value for fp and plot fnal modifed Aol
ensuring fnal location of fz meets criteria in STEP 2.
One disadvantage with the use of R
ISO
is that the point of
feedback is not directly at the capacitive load. This means
that accurate control of the voltage at CL is not obtained. This
is usually not a problem since most piezo drives are used
inside of an outer control loop such as position feedback
P
H
A
S
E

S
H
I
F
T

(
d
e
g
r
e
e
s
)

FREQUENCY, F (Hz)
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 10 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
FIGURE 19. COMPOSITE OPEN LOOP PHASE PLOT FOR STABILITY
fcl
MARGIN = 45
1 100
FIGURE 20. V
OUT
/V
IN
FOR VARIOUS CL
.1 1 10 100 1K 10K 1M 10M 100M
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY, F (Hz)
G
A
I
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(
d
B
)
220
240
100K
1 2 3 V
OUT
/V
IN
V
OUT
/V
IN
FOR CL = 26f
V
OUT
/V
IN
FOR CL = 10f
V
OUT
/V
IN
FOR CL = 3f
1
2
3
1.22K 3.I8K
FIGURE 22. A1: MASTER AMPLIFIER MAGNITUDE PLOT FOR STABILITY
.1 1 10 100 1K
10K
1M 100M
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY, F (Hz)
G
A
I
N

(
d
B
)
220
PA88 Aol w/Cc = 3.3pF
100K
10M
1
3
4 2
1
2
3
4
5
23.7K
26.5K
39.2K
53K
75K
A1 GAIN = 10
A1 GAIN = 5
A1 GAIN = 2
A1 GAIN = 1
5
dp
CL = .06F
CL = .03F
A1 GAIN = 22.7
AN25
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A
FIGURE 21. PA88 BRIDGE PZT DRIVE WITH SELECTABLE GAIN
4.4K
10K
4.22K
1500pF
20K
4.22K
1000pF
10K
4.22K
470pF
10K
5.62K
270pF
.1F
8.66W
RIM
CFM
15pF
100K
RFM
+120V
PA88
A1
.1F
120V
Cc
3.3pF
120V 120V
**
*
.03F
to
.06F
*
+120V +120V
*
*
6.98W
PA88
A2
Cc
3.3pF
100K
RIS
CFS
15pF
.1F
4.7F
+
.1F
4.7F
+
100K
RFS
Cn
270pF
Rn
5.62K
120V
NOTES: UNLESS OTHERWISE NOTED:
1) ALL DIODES ARE 1N4148; *DIODES = 1N5617; **TRANSZORBS = 1N6300 or 1.5KE160
2) USE HS02 HEATSINK @ 25C AMBIENT
V
IN
**
+120V
P
H
A
S
E

S
H
I
F
T

(
d
e
g
r
e
e
s
)
FREQUENCY, F (Hz)
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 10 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
FIGURE 23. A1: MASTER AMPLIFIER OPEN LOOP PHASE PLOT CL = .06mf GAIN = 6dB
fcl
MARGIN = 29
1 100
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782 AN25U
into a microprocessor which will then generate an error
command to the input of the PB58 piezo drive circuit. The
major advantage of R
ISO
is that a wide range of capacitive
loads can now be driven with good stability.
3.1.1 PB58 PIEZO DRIVE WITH R
ISO
Figure 16 (previous page) is a piezo drive amplifer using
the PB58 and our R
ISO
technique for capacitive load stability.
The design goal for this amplifer was to have an adjustable
DC offset and still allow an AC input signal to swing about the
DC offset. Amplifer A1 AC couples V
IN
and offsets it around
the selected DC offset set by R
ADJ
.
The stability of the PB58 composite amplifer begins with frst
ensuring the PB58 itself is stable. This is accomplished with the
use of R
ISO
in Section 3.1 and Figure 13. Figure 17 (previous
page) creates the composite Aol by adding the closed loop volt-
age gain of the PB58 to the open loop gain of the LF355 front
end amplifer. For details on stabilizing composite amplifers,
refer to Apex Precision Power Application Note 19. Figure 18
(back 3 pages) illustrates the 1 plot selected for good stabil-
ity. Note the V
OUT
/V
IN
relationship which will be discussed later.
Figure 19 (back 2 pages) verifes good stability through the
open loop phase plot.
Since output voltage across CL is not controlled directly, it
is of interest to see how the V
OUT
/V
IN
relationship changes with
capacitive loads. Figure 20 (back 2 pages) shows the V
OUT
/V
IN

which is at the output of the amplifer. Curves 1 thru 3 show
the effect of the additional V
OUT
/V
IN
pole formed by R
ISO
and
CL. As the capacitive load is decreased its possible to gain a
wider bandwidth since the additional pole due to R
ISO
and CL
is moving out higher in frequency.
So far the small signal response for this amplifer has been
examined. The large signal response has two limitations. The
frst is slew rate. The slew rate for the composite is limited
to slew rate of the front end times the booster gain. In this
case S.R. = 5V/S X 10 = 50V/S. The upper frequency of a
sinewave we can track is a 120Vpp sinewave of 133KHz from
S.R.=2 f V
OP
. This is not a limiting factor for this circuit since
the small signal bandwidth begins to roll off at 28.4 KHz for
V
OUT
/V
IN
(refer to Figure 20). The second large signal limitation
is current drive capability. As the capacitive load is increased,
the impedance is lowered as the frequency increases. This
translates to higher currents.
The following is lab data taken on the circuit of Figure 16
for power response:
P
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A
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S
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I
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T

(
d
e
g
r
e
e
s
)

FREQUENCY, F (Hz)
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 10 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
FIGURE 24. A1: MASTER AMPLIFIER OPEN LOOP PHASE PLOT CL = .06f GAIN = 20dB
fcl
MARGIN = 45
1 100
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AN25U 783
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P
H
A
S
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S
H
I
F
T

(
d
e
g
r
e
e
s
)

FREQUENCY, F (Hz)
.1 1 10 100 1K 10K 100K 1M 10M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 1 10 100 1K 10K 100K 1M
180
100M
135
90
45
0
+45
+90
+135
+180
.1 10 1K 1M
180
100M
135
90
45
0
+45
+90
+135
+180
FIGURE 25. A1: MASTER AMPLIFIER OPEN LOOP PHASE PLOT CL = .06f GAIN = 27.5 dB
MARGIN = 67
1 100 100K
fcl
10M 10K
10M
FIGURE 26. PA241 COMPOSITE PIEZO TRANSDUCER DRIVE
15
+40V
40V
V
OUT
1.6KHz
22pF
CF
+60V
RF
340K
.1F
R
CL
PA241
Cc
15pF 60V
.1F
CL
.1F
RI
34K
+15V
15V
340K
RFC
22pF
CFC
+15V
.1F
15V
.1F
RIC
21K
V
IN
2.5V
Rn
3.4K
Cn
10nF
ALL DIODES 1N41481
OP07
AN25
784 AN25U
the PA241 has a 40mV input offset voltage. In high voltage
applications where low drift or high accuracy are desired this
can be accomplished through the use of a composite ampli-
fer which uses a low cost monolithic front end amplifer to
control accuracy and drift. The PA241 now acts as a voltage
and current booster.
There are three simple steps to stabilize a composite with
a capacitive load:
STEP 1: Compensate PA241 for stability frst: Refer to Figure
27 which shows how capacitive load modifes Aol. Figure 28
confrms that the selected 1/ plot will guarantee stability
for the PA241.
STEP 2: Create composite Aol: Refer to Figure 29 (see next
Page) which shows addition of closed loop gain of PA241
to OP07 Aol on dB plot to yield net Composite Aol.
POWER RESPONSE (Ilim = 1.3A)
CL = 10F f V
OUT
400Hz 100Vpp
700Hz 50Vpp
4KHz 10Vpp
CL = 22F f V
OUT
200Hz 100Vpp
400Hz 50Vpp
2KHz 10Vpp
Of equal interest is the power supply rejection for this com-
posite since the choice of front end amplifer will change this
number to some degree. The following lab data for the circuit
of Figure 16 illustrates the PSR for the positive supply.
POSITIVE POWER SUPPLY REJECTION
(DC set for +Vs = +110V, AC set for 2Vpp Ripple)
f V
OUT
Ripple Attenuation Referred to input PSR
1KHz 30mVpp .015 .0015 -56.5db
10KHz 290mVpp .145 .0145 -36.8db
100KHz 420mVpp .210 .0210 -33.6db
3.2 CAPACITIVE LOADS AND GAIN SWITCHING
Often times in an end product or test system a customer
desires control over the gain setting for the amplifer. With any
load this raises some important questions. Capacitive loads
only complicate matters somewhat.
Figure 21 (back 3 pages) shows a bridge circuit for driving
piezo transducers. The bridge circuit allows up to twice the peak
voltage across the load than driving the load ground referenced.
This is because as A1 goes towards +120V, A2 drives towards
-120V yielding up to twice the peak voltage across the load.
Correspondingly, the bridge circuit also doubles the voltage
slew rate across the load for the same reason. Forcing the
master amplifer, A1, to current limit frst, equally distributes
SOA stresses between A1 and A2 in case of a shorted load.
A range of loads was defned for this amplifer as shown in
Figure 21 (back 3 pages) . The key to successfully changing
the gains in this circuit is to change the noise gain compen-
sation components as the input resistor is changed to select
the desired gain setting. It is HIGHLY RECOMMENDED NOT
to switch in different values of Cc around the PA88 amplifer
A1 as gains are changed. There are MOSFET gates that are
connected to the compensation pins that could be destroyed
with compensation capacitor switching. It is also critical for
stability that Cc be located directly at the amplifer which
does not yield itself easily to switching. Figure 22 (back 2
pages) illustrates the 1/ plots for stability for all select-
able gain settings. Notice that the stability technique applied
here uses both noise gain compensation on the input along
with the feedback zero to maximize phase margin for stabil-
ity. The modifed Aol curves are shown for CL =.06F and
CL =.03F. Output impedance for the PA88 of 100 ohms was
used. Figures 23, (back 3 pages) 24, (back 2 pages) and 25
(previous page) prove through open loop phase plots that good
stability is guaranteed. Open loop phase plot for A2 will be the
same as Figure 23.
3.3 HIGH ACCURACY, HIGH VOLTAGE, LOW COST PZT DRIVE
Figure 26 (previous page) is an example of a high accuracy
(input offset = 60V), low drift high voltage amplifer. Though
only used here at +/-60V, the PA241 can be used up to +/-175V
supplies. The PA241 is a low cost monolithic ASIC designed for
high voltage. The limitations of the high voltage ASIC technol-
ogy do not allow for optimization of input characteristics, thus
Bode Plot
-20
0
20
40
60
80
100
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Frequency, Hz
G
a
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d
B
MODEL PA241,3-150 Note/PBs Rn 9999999999 Kohms
Rcl 15 Ohms Cn 0 nF
Rf 340 Kohms
Total Rout 165 Ohms
1/Beta (DC) 20.8 dB
Noise Gain 0.0 dB
FIGURE 27.
Fcl
Acl
1/eta
Aol
-180
-135
-90
-45
0
45
90
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Frequency, Hz
P
h
a
s
e

S
h
i
f
t
,

D
e
g
r
e
e
s
OPEN LOOP
POLE 1
Cf ROLL OFF
Cl & Zout
ROLL OFF HITS 0dB
POLE 2
POLE 3
FIGURE 28.
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A
3.5 860VPP SINGLE SUPPLY PIEZO DRIVE
Occasionally it is desired to provide a bipolar drive to a capaci-
tive load using only a single supply. This will reduce area and
cost by only requiring one power supply. It will however require
the use of a bridge circuit with two high voltage amplifers.
Figure 33 (next page) is an implementation of an 860Vpp
piezo drive. There are four simple steps to setting up the single
supply scaling:
STEP 1: Defne maximum V
OP
:
MAX V
OP
= +Vs - VsatA - VsatB
MAX V
OP
= +450 - 10V -10V = 430Vp
STEP 2: Calculate gain:
Gain = V
OPP
/ V
INPP
= (VA - VB)pp / V
INPP

Gain = 860Vpp / 12Vpp = 71.67
Gain = 2 RF/RI with the bridge confguration. That is the
voltage gain across the load is twice that of the master
amplifer, A, since +1V out of amplifer A yields -1V out of
amplifer B, relative to the midpoint power supply reference
of +225V. Therefore: RF/RI = 71.67/2 = 35.833
STEP 3: Calculate offset:
But when V
IN
= 0 then VA-VB =+430V
Using RF/RI = 35.833 and solving above equation yields
STEP 3: Compensate composite op amp: Figure 30 (see next
page) shows the selected 1/ plot to stabilize composite
amplifer. Both noise gain compensation and feedback zero
compensation are used to maximize stability. Figure 31 (see
next page) plots the open loop phase for the composite am-
plifer yielding 50 degrees phase margin and good stability.
3.4 HIGH HIGH VOLTAGE AMPLIFIER CIRCUIT
Figure 32 (see next page) illustrates the current state of the
industry with regards to highest voltage available using op amps.
This bridge circuit will give us up to +/-1160V across the load.
Remember when using the PA89 to pay particular attention to
input protection, heatsinking (low quiescent current times high
voltage ==> power dissipation!), components (power dissipa-
tion and voltage coefficient of resistance), and compensation
capacitor (1200V rating necessary).
MODEL OP07 READ ME
Aol = 135 dB Pole 1 = 0.1 Hz
Pole 2 = 7.00E+05Hz Pole 3 = 7.00E+06Hz
Rin 21 Kohms 3.4 Kohms
Rn
1/Beta (DC) 24.7 dB
Noise Gain 16.7 dB
Bode Plot
-20
0
20
40
60
80
100
120
140
160
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Frequency, Hz
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Aol Comp
Aol Host
1/eta
Acl
Fcl
FIGURE 30.
-180
-135
-90
-45
0
45
90
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Frequency, Hz
P
h
a
s
e

S
h
i
f
t
,

D
e
g
r
e
e
s
OPEN LOOP
NOISE GAIN
HOST Cf
BOOSTER Fcl
BOOSTER Cf
POLE 2
BOOSTER POLE 2
POLE 3
ROLL OFF HITS 0dB
FIGURE 31.
Cn
560pF
V
IN
RFM
500K,1W
RIM
10K
Rn
10K
220
Rc
33pF
Cc
33pF
Cc
18.7
R
CL
23.2
R
CL
+600V +600V
600V 600V
220
Rc
PA89 PA89
FIGURE 32. 1160V PIEZO DRIVE BRIDGE
ALL DIODES IN4148's
RIS
500K,1W RFS
500K,1W
VA VB = +Vs(2 (1+ RF/RI)(
RB
RA +RB
) 1) 2(RF/RI)V
IN
MODEL OP07 READ ME
Aol = 135 dB Pole 1 = 0.1 Hz
Pole 2 = 7.00E+05 Hz Pole 3 = 7.00E+06 Hz
Rin 21 Kohms Rn 999999999 Kohms
Bode Plot
-20
0
20
40
60
80
100
120
140
160
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Frequency, Hz
G
a
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,

d
B
Aol Comp
Aol Host
1/eta
Acl
Fcl
FIGURE 29.
AN25
786 AN25U
RA = 36.669RB
Choosing RB = 12K implies RA = 440K
STEP 4: Check for common mode voltage compliance:
The resistor divider of RA and RB was set to yield the desired
offset. These values yield V
R
= 11.95V which is greater than
the minimum common mode voltage specifcation of 10V
for the PA85.
FIGURE 33. 860Vpp PIEZO DRIVE (SINGLE SUPPLY BRIDGE)
.1F
PA88
A1
PA88
A2
500K 1/2W Trimpot

500K
1/2W Trimpot
+450V
RA
440K
V
R

(11.95V)

RB

12K
1/4W
C5
RFM
490.9K
VR1 +450V
+
C1 10F
C2 .1F
R
CLA

4.87
1/4W
D1 D3
D2 D4
V
A
V
B
R
cb
330

+450V
RFS

432K,1/2W
C4 .1F
+450V
RX
432K
1/4W
RY
432K
1/4W
C3
.1F
Cn
120pF Rn
12.1K
C
cb

10pF
R
CLB

3.79
1/4W
R
ca
330

C
ca

10pF
V
IN
RIM

13.7K
1/4V
RIS

432K,1/2W
A
B
+12V
V
IN
V
R
V
A
V
B
+6V
10
225
440
225
430
0
V
A
0V 440 10 +430
D1-D4 = 1N5619
All others = 1N4148s
IMPORTANT NOTICE
4.0 FINAL NOTE
You have now looked at several ways to drive capacitive loads
using high voltage amplifers. The techniques presented here
are intended to enable you to complete your circuit designs
in a short time.
If there are additional questions or concerns not covered
in this application note, please feel free to contact Cirrus AP-
PLICATIONS ENGINEERING through our TOLL FREE Design
Support Request, (800) 625-4084.
AN25
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.
1
1
1
0
1
0
0
1
K
1
0
K
1
0
0
K
1
M
1
0
M
1
0
0
M
0
2
0
4
0
6
0
8
0
1
0
0
1
2
0
1
4
0
1
6
0
1
8
0
2
0
0
2
2
0
2
4
0
F
R
E
Q
U
E
N
C
Y

(
H
z
)
G A I N ( d B )
AN25
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P H A S E S H I F T ( d e g r e e s )
F
R
E
Q
U
E
N
C
Y

(
H
z
)
.
1
1
1
0
1
0
0
1
K
1
0
K
1
0
0
K
1
M
1
0
M
1
8
0
1
0
0
M
1
3
5
9
0
4
5 0
+
4
5
+
9
0
+
1
3
5
+
1
8
0
.
1
1
1
0
1
0
0
1
K
1
0
K
1
0
0
K
1
M
1
0
M
1
8
0
1
0
0
M
1
3
5
9
0
4
5 0
+
4
5
+
9
0
+
1
3
5
+
1
8
0
.
1
1
1
0
1
0
0
1
K
1
0
K
1
0
0
K
1
M
1
0
M
1
8
0
1
0
0
M
1
3
5
9
0
4
5 0
+
4
5
+
9
0
+
1
3
5
+
1
8
0
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AN26 Parallel
Connection
PARALLEL CONNECTION OF POWER OP AMPS
Power op amps can be paralleled to increase current, im-
prove SOA (Safe-Operating-Area), or double thermal capabil-
ity. While the basic topology seems simple, there are design
details which require careful attention such as common-mode
range considerations, stability, slew rate, and losses which can
reduce efficiency and increase power dissipation.
1.0 BASIC PARALLEL TOPOLOGY
A1 in Figure 1 referred to as the master amplifer, can be
confgured in any form desired, inverting or non-inverting, and
any gain desired. Feedback for A1, and only A1, will come
from the overall output of the parallel connection. The output
of each amplifer will have in series equal small-value resistors
to improve current sharing characteristics. The slave amplifers,
A2 and up to An, are confgured as unity gain non-inverting
buffers driven from the output terminal of the master amplifer
A1. Each slaves individual feedback is taken directly at its
output terminal.
The idea of this connection is since each slave is a unity
gain buffer, the slave outputs will match as closely as pos-
sible the output of the master. Yet with the master feedback
being wrapped around the entire circuit, overall accuracy is
maintained.
2.0 LOSSES
The output of the slaves in this confguration will not exactly
match the master. Since the slaves operate at unity gain, the
difference will be equal to the worst case offset of a single
amplifer for two amplifers in parallel since only the offset of the
slave causes this mismatch. With more than one slave, each
slave could have worst case offset in opposite directions, and
in the worst case, the mismatch is twice the input offset voltage.
These offset voltages produce a drop across the current
sharing resistors and a corresponding current fow. This is
F
R
V
IN
S
R
L
R
2I
I
R
I
I
S
R
+V
S
+V
S
V
S
V
S
A1
A2
CONSIDERATIONS
I
LOSS
= V
OS
/2R
S
V
LOSS
= I
OUT
R
S
SLEW RATE MISMATCH
WILL GIVE LARGE I
CIRC
FIGURE 1. BASIC CONNECTION.
current that is lost, never appearing in the load and increasing
amplifer dissipation.
Even a unity gain buffer (the slave amplifer) has phase shift
making its instantaneous output voltage different from the
master amplifer, and again producing a voltage drop across
the sharing resistors. If the desired signal frequency is grater
than half the power bandwidth of the amplifer, the parallel
connection will likely not be practical. To check a specifc ap-
plication, Use Power Design to fnd closed loop phase shift,
multiply the sine of that angle times the peak output voltage to
fnd the peak difference voltage across the sharing resistors.
This current is again lost, never appears in the load and
increases amplifer heating.
2.1 CURRENT SHARING RESISTOR CHOICE
Increasing values of current sharing resistors will reduce
the circulating current loss. But this improvement must be
weighed against direct losses through the current sharing
resistors when delivering current to the load. The challenge
to the designer is to fnd the happy medium for Rs values. As
a general rule, power amplifers will be used with Rs values
of from 0.1 ohm to 1.0 ohm.
3.0 CURRENT LIMITING
Current limit of the master should be set 20% lower than
the slaves if possible, and the ultimate current limit of the
overall circuit will be that limit multiplied by the total number of
amplifers. The idea here is the master current limits frst, and
since it provides the drive for all other amplifers, that drive is
also clipped. This insures equal sharing of all stresses during
current limit.
4.0 SLEW RATE CONSIDERATIONS
Assume an initial condition where the output of the circuit
in Figure 1 is resting close to the negative rail. Then apply a
step function to the input of the master amplifer to drive the
output positive. The output will slew as fast as the amplifers
slew rate to the positive rail. With the slave being driven from
the master, the slave doesnt get its input transition until the
master slews, and then the slave requires additional time to
slew positive.
In the interval where the master has reached positive output
and the slave is trying to catch up, there is a large difference
in the output voltage of the two amplifers developing current
through the two current sharing resistors. This can be a large
current equivalent to the current limit of the amplifer. Thats
the bad news. The good news is that it is a transient current
and as such may be within transient SOA limits. But this can
be difficult to prove for certain.
When in doubt, the best rule of thumb is to not use the
parallel connection at greater than half the rated slew rate of
the amplifers.
5.0 STABILITY CONSIDERATIONS
For detailed information on stability, refer to Application Note
19, Stability For Power Operational Amplifers. All discussion
here is based on the stability theory contained in Application
Note 19.
Parallel Connection
MAY 2009
APEX AN26UREVD
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5.1 SLAVE STABILITY
The most obvious problem from a stability standpoint is the
unity gain buffer connection of the slaves. This confguration
has the least ability to tolerate poor phase margin. Poor phase
margin usually occurs as a result of excessive capacitive loading.
But in the case of the PA12, the unity gain buffer connection
should not be used without additional compensation. Externally
compensated amplifers should normally be compensated for
unity gain and may still require additional compensation. Al-
ternatively, they may be decompensated to improve slew rate
and use noise gain compensation to insure stability.
The most common way we recommend to compensate the
slave is with a noise gain compensation network across the
inputs to the amplifer. However, for noise gain compensa-
tion to work, there must be impedance in the feedback path.
Figure 2 shows the modifcations necessary to incorporate
noise gain compensation.
The R
FS
value of Figure 2 is somewhat arbitrary, but its choice
will dictate the fnal values of Rn and Cn. As is the general
case in any op amp circuit, excessive impedance for RFs is
something to be avoided. A realistic range of values for RFs is
from 1 K to 1 M with a good starting point being 10 K.
Once the value of R
FS
is pegged, noise gain compensa-
tion should usually be set to give a noise gain of 10. This
corresponds to Rn being one-tenth Rf. Cn must be found
analytically according to procedures outlined in Application
Note 19 after considering the effects of amplifer bode plot and
additional poles resulting from capacitive loading. In many
cases, selecting Cn for a corner frequency of 10KHz based
on the value of Rn (Xcn = Rn@10KHz) will result in a stable
circuit; although, analytical methods will maximize bandwidth
in comparison to this method.
5.2 MASTER STABILITY
A1 is subject to all normal considerations for stability. If A1
is a gain of 10 or greater, its stability will be equal to that of
the slave with noise gain compensation described above. At
gains below 10, the optimum noise gain will be a gain of 10
to match the slaves.
6.0 COMMON MODE CONSIDERATIONS
The unity gain buffer confguration must be able to accept
inputs equal to the maximum output swing of the master. This
will be a problem with MOST amplifers. Light loads make the
situation worse. Both the output voltage swing and the common
mode voltage range specifcations are given as volts from the
supply rail. Read the output voltage swing from the typical graph
at the lowest possible current the amplifer will be required to
drive when the input signal calls for saturation. Read the com-
mon mode voltage specifcation from the specifcation table in
the MIN column. For the parallel confguration to work without
special circuitry, the output voltage swing must be at least as
large as the common mode voltage specifcation.
The PA02 does not lend itself to parallel connection. Negative
inputs which get closer than 6 volts of the negative supply rail
can cause output polarity reversals which can be catastrophic
in the parallel connection.
6.1 OVERCOMING COMMON MODE RESTRICTIONS
A method most useful with high voltage amplifers where
currents are low, is to simply use zener diodes in series with
the supply line to the master amplifer as shown in Figure
3A. These drop the master supply low enough to restrict its
output swing to be within the common-mode range of the
slaves. Determine wattage ratings based on expected load +
quiescent current fow.
The PA04 and PA05 present another opportunity to overcome
common-mode limitations by taking advantage of their boost
pins. Originally incorporated to improve output voltage swing,
we effectively increase common-mode range by increasing
front-end supply voltages. A boost of at least 5 volts will be
adequate to overcome this limitation. Figure 3B elaborates
on this connection.
f
R
V
IN
S
R
I
R
I
I
S
R
+V
S
V
S
A1
A2
TRADITIONAL
(V
SAT
V
CM
)
FIGURE 2. SLAVE STABILITY.
ZL
R
CL+
R
CL
.8R
.8R
CC2
Cn
Rn
R
FS
VA2
V
OUT
+V
S
V
S
R
CL+
CC1
R
CL
R
VA1
R
V
IN
I
OUT
2I
F
R
V
IN
S
R
I
R
I
I
S
R
+V
S
V
S
A1
A2
HIGH VOLTAGE
(V
SAT
< V
CM
)
FIGURE 3A. OVERCOMING COMMON MODE RESTRICTIONS.
ZL
R
CL
.8R
CC2
Cn
Rn
R
FS
VA2
V
OUT
+V
S
V
S
CC1
VA1
.1F
I
OUT
2I
VRZ
VRZ
.1F
R
CL
R
VRZ > V
CM
V
SAT
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V
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R
I
R
I
I
S
R
+V
BOOST
V
BOOST
A1
A2
HIGH POWER with V
BOOST
(V
SAT
< V
CM
)
FIGURE 3B. OVERCOMING COMMON MODE RESTRICTIONS.
ZL
R
CL
.8R
CC2
Cn
Rn
VA2
V
OUT
+V
S
V
S
CC1
VA1
.1F
I
OUT
2I
R
CL
R
V
BOOST
>V
S
V
SAT
+ V
CM
V
S
+V
S
F
R
R
FS
Other methods include operating slaves on slightly higher
voltages than the master. This is what is accomplished with
the zeners described previously, but is not easily applied to
high current power amplifers unless they have boost voltage
provisions. In such cases the zeners can be included in series
with the Vboost pins of the master amplifer.
It may seem possible to attenuate the output of the master and
set the slaves up with corresponding gain, but it will be found
that unless very strict matching requirements of the associated
resistors are met, extremely large circulating currents will fow.
7.0 BRIDGE CIRCUITS
The master-slave combination once realized and taken as
a whole, comprises one effective op amp. Treated this way,
incorporation into a bridge circuit is simply a matter of using an
inverting unity gain confguration on the slave side of the bridge
(note that the slave of the parallel combination and the slave
side of a bridge are two different things). Bridge techniques are
discussed in detail in Application Note 20, Bridge Operation.
8.0 SINGLE SUPPLY
There are no unique considerations concerning single supply
except those described in Application Note 21, Single Supply
Operation. Again, as in the bridge, treat the parallel combina-
tion as a single op amp.
IMPORTANT NOTICE
AN28
792 AN28U
AN28 Proper Analog Wiring for
1.0 AVOID PREDICTABLE FAILURES
This brief application note is intended to guide you through
successful prototyping and fnal construction of power op amp
circuits by using proper component location and interconnec-
tion techniques.
Proper analog construction of power op amps is just as
critical as choosing the proper power op amp, heatsink, or
schematic design. For reliable success, you should treat all
power op amps as high frequency devices. Even though you
may have designed a circuit to operate at 400Hz, the ampli-
fer will, in general, have a bandwidth capability out to 4MHz
or so and will be happy to oscillate at that frequency if not
constructed properly.
In addition to this application note, be sure to read General
Operating Considerations in the Apex Precision Power hand-
book for details on stability, supplies, heatsinking, mounting,
current limit, SOA, and specifcations interpretation.
2.0 PROPER MECHANICAL MOUNTING
Refer to Figure 1. This side view of the amplifer mounted to
a heatsink shows optimum mounting to allow for wiring ease of
the peripheral components associated with the power op amp.
Notice the necessity of tefon sleeving to insulate the amplifer
leads from the heatsink; the use of a mating socket for ease
of solderable component connections; and the use of an Apex
Precision Power thermal washer (or thermal grease) as the
only approved interface between the amplifer and the heatsink.
You also want to be sure the recommended mounting torque of
4-7in-lbs (.45-.79 N-m) for the 8-pin TO-3 package and 8-10in-lbs
(.90-1.13 N-m) for the Power Dip, JEDEC MO-127, package
is used. This torque needs to be applied in small increments
alternating between the two mounting bolts, similar to tightening
the lug nuts on a car tire.
2.1 8-PIN TO-3 MOUNTING
Since the 8-pin TO-3 package is more sensitive to improper
mounting torque, here is a rule of thumb for those who do not
have ready access to a torque screwdriver:
i) After an Apex Precision Power thermal washer or grease
is applied and the tefon sleeving installed on the leads,
assemble the power op amp onto the heatsink and press
it frmly into the mating socket until it is frmly seated and
there is no gap in the assembly.
ii) Insert the two mounting bolts through the mounting holes in
the fange of the amplifer and tighten them fnger-nail tight.
Literally use your fngernail as a screwdriver. This ensures
no overtorque and gives a starting point so that the nut fts
snugly against the mating socket.
iii) After using fnger-nail tightening, one complete revolution
on the head of each mounting bolt is 4-7in-lbs. Apply this
torque one quarter of a turn at a time, alternating between
the two mounting bolts, until one complete revolution is
reached.
3.0 PROPER ANALOG CONSTRUCTION
Figure 2 illustrates a typical inverting power op amp circuit
which will be used to discuss proper component locations and
wiring. Other power op amp circuits will use similar techniques.
Refer to Figure 3. This Figure shows the proper routing of
connections and component locations for the circuit of Figure
2.
The mating socket will be facing towards you to allow for
unlimited height so a circuit ball or birds nest of components
can be soldered directly to the mating socket. This will result
in an analog construction equivalent to a properly designed
printed circuit board.
Note the location of all components associated with the power
op amp circuit shown in Figure 2 are directly at the power op
amps mating socket. A single point ground is illustrated by
physical connection of the power supply ground, input signal
ground, and output load ground.
For the single point ground wire running from the power
supply to the power op amp, strip back the wires insulation
about 2 or 3 inches and tin it with solder. This wire can then be
bent or bussed wherever it needs to go to pick up all ground
points for the power op amp and its associated components.
Stand components on end, cordwood style, or leave them
hanging in mid-air, using the leads of the components them-
selves as interconnection wires.
DO NOT RUN WIRES FROM EACH PIN OF THE POWER OP
AMP OVER TO A PIECE OF VECTOR BOARD, PERF BOARD,
OR PRINTED CIRCUIT BOARD WHERE THE POWER OP
AMPS ASSOCIATED COMPONENTS ARE LOCATEDTHIS
WILL BECOME AN OSCILLATORY, ANALOG DISASTER!
Teflon Tubing
(At least 4 pins)
Power Op Amp
Package
Heatsink
Mating Socket
APEX Thermal Washer
(or thermal grease)
TOP
BOTTOM
FIGURE 1. SIDE VIEW.
Proper Analog Wiring for Power Operational Amplifiers
MAY 2009
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RF
+V
S C1
C3
C2
C4
RCL
RCL+
RI
V
IN
V
O
V
S
5
3
1
2
8
6
4
10F
V
O
10F
.1F
.1F
FIGURE 2. SCHEMATIC.
FIGURE 3. TOP VIEW. BOTTOM VIEW OF AMPLIFIER.
V
O
RCL+ RCL
C1
C2
C3 C4
RF
RI
POWER SUPPLY
+V
S
V
S
SIGNAL GENERATOR
OUTPUT
V
O
AN30
794 AN30U
AN30 PWM Basics
1.0 INTRODUCTION
This note is divided into three sections. The frst section
provides general information on Pulse Width Modulation
amplifers and examines a typical block diagram. The second
section on designing with PWM amplifers is NOT intended for
optional reading. The family of PWM amplifers are not equal in
protection features and some of the design errors that would
cause a linear amplifer to oscillate will destroy some of the
less protected PWM amplifers. The fnal section examines
some ways to use PWM amplifers.
PWM circuits are taking the same general course of develop-
ment traveled by op amps and many other electronic functions.
Concepts were brought to life using discrete components and
were followed by modules, hybrids and then monolithics. Since
the introduction of the frst hybrid PWM amplifers from Apex
Precision Power, the product family has broadened to include
a wide range of power levels and package types. The family
includes models with up to three levels of internal protection
circuitry and low cost models that feature no frills PWM power.
With digital or analog input capability on most amplifers, the
Apex Precision Power PWM family can ft the requirements of
many applications.
2.0 WHY PWM
As power levels increase the task of designing variable drives
increases dramatically. While the array of linear components
available with sufficient voltage and current ratings for high
power drives is impressive, a project can become unmanage-
able when calculation of internal power dissipation reveals the
extent of cooling hardware required. A 20A output stage often
requires multiple 20A semiconductors mounted on massive
heatsinks and usually employs noisy fans or liquid cooling in
some cases.
Figure 1 illustrates the linear approach to delivering power
to the load. When maximum output is commanded, the driver
reduces resistance of the pass element to a minimum. At this
output level losses in the linear circuit are relatively low. When
zero output is commanded the pass element resistance ap-
proaches infnity and losses approach zero. The disadvantage
of the linear circuit appears at the midrange output levels and
is often at its worst when 50% output is delivered. At this level,
resistance of the pass element is equal to the load resistance
which means heat generated in the amplifer is equal to the
power delivered to the load! We have just found the linear circuit
to have a maximum efficiency of 50% when driving resistive
loads to midrange power levels. When loads appear reactive
this efficiency drops even further.
Figure 2 illustrates the most basic PWM operation. The PWM
DRIVER
LOAD
PASS ELEMENT
Vs
FIGURE 1. LINEAR POWER DELIVERY
control block converts an analog input level into a variable duty
cycle switch drive signal. As higher outputs are commanded, the
switch is held ON longer portions of the period. Normally, the
switch is ON and OFF once during each cycle of the switching
frequency, but there are many designs capable of holding a
100% ON duty cycle. In this case, losses are simply a factor of
the ON resistance of the switch plus the inductor resistance.
As less output is commanded the duty cycle or percent of ON
time is reduced. Losses include heat generated in the fyback
diode. At most practical supply voltages this diode loss is still
small because the diode conducts only a very small portion
of the time and this voltage drop is a small fraction of the
supply voltage.
The job of the inductor is storing energy during the ON por-
tion of the cycle for fltering. In this manner the load sees very
little of the switching frequency but responds to frequencies
signifcantly below the switching frequency. A rule of thumb
is to expect a usable bandwidth to be one decade below the
switching frequency. Inductive loads often provide adequate
fltering without dedicated flters.
With the PWM circuit, the direct (unfltered) amplifer output
is either near the supply voltage or near zero. Continuously
varying fltered output levels are achieved by changing only
the duty cycle. This results in efficiency being quite constant
as output power varies compared to the linear circuit. Note
that efficiency claims on the hybrid PWM amplifer data sheet
do not include flter losses. Typical efficiency of fltered PWM
circuits range from 80 to 95%.
Almost all power amplifers (low duty cycle sonar amplifers
are a notable exception) must be designed to withstand worst
case internal power dissipation for considerable lengths of time
compared to the thermal time constants of the heat sinking
hardware. This forces the design to be capable of cooling
itself under worst case conditions. Conditions to be reckoned
with include highest supply voltage, lowest load impedance,
maximum ambient temperature, and lowest efficiency output
level. In the case of reactive loads, maximum voltage-to-current
phase angle (lowest power factor) must also be addressed.
Consider a circuit delivering a peak power of 1KW. A 90%
efficient PWM circuit generates 100W of waste heat when
running full output and around 50W delivering half power. The
theoretically perfect linear circuit will generate 500W of waste
heat while delivering 500W. Table 1 shows three possible ap-
95% 50% 5%
Vs
PWM
CONTROL
FIGURE 2. PWM POWER DELIVERY
PWM Basics
MAY 2009
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3.1 HYBRID H-BRIDGE BASICS
The H-bridge switches work in pairs to reverse polarity of
the drive even though only one polarity supply is used. Notice
how the levels of the A-B waveform are different even though
shape is identical to the A waveform. Q1 and Q4 conduct dur-
ing one portion of each cycle and Q2 and Q3 are on during
the remainder of the cycle.
Figure 5 shows a block diagram typical of Apex Precision
Power PWM amplifers. The hybrid construction of these
amplifers can allow monitoring of temperature directly on
the surface of each power die rather than case or heatsink
temperature monitoring - the best that a discrete design could
implement. Direct die temperature measurement eliminates
thermal resistance variables and reduces response time by
orders of magnitude. The thermal limit is set at approximately
165C. Activation of the thermal shutdown circuit will latch all
of the H-bridge switches off. Toggle the shutdown pin or cycle
the power to reset the amplifer and resume normal operation.
3.2 CURRENT SENSE, CURRENT LIMIT AND CUR-
RENT SHUTDOWN
The frst of two current limits in the PWM block is the high
side current limit that activates only upon output shorts to
ground (assuming the programmable current has been properly
confgured.) This circuit has a variable response time based on
the current magnitude in +V
S
line. With a fault current of about
1.5 times the rated output current it will require several cycles
of the switching frequency to activate the circuit. As higher
currents are sensed the response time decreases. Once a
fault has been sensed the amplifer will remain latched off until
power is cycled or the shutdown pin is toggled.
The second current limit circuit in the block diagram is pro-
grammable and activates upon a load fault or a short to the power
supply. An external resistor senses current fowing between
ground and the low side of the H-bridge. The sensed voltage
is fed to the current limit pin. When this voltage exceeds the
threshold (see individual datasheets for this value), all switches
in the H-bridge are shut off for the remainder of the switching
cycle. Because the sense voltage will have considerable spike
content, the hybrid includes an internal flter stage. A second
external stage of R-C fltering allows larger peak currents for
any given value of current sense resistor. In some models, the
current limit function can be used to shut the amplifer down
on command of a logic level input voltage.
In most circumstances (half bridges are a common exception)
all of the load current fnds its way through a sense resistor
to ground. This implies that the choice of resistor should be
capable of handling the maximum load current defned by the
current limit resistor value.
proaches to this type design. In all three cases it is assumed
ambient temperature is 30C and maximum case temperature
is 85C. It is also assumed power ratings of the TO-3 devices
is 125W each. Heatsinks for linear designs require multiple
sections mounted such that heat removed from one section
does not fow to other sections. The linear approaches require
fve times the heatsink rating of the PWM approach. The bad
news with the hybrid linear design is that the heat is concen-
trated in such a small area that this design is right on the edge
of requiring liquid cooling. With its high package count the
discrete linear approach will likely have more than fve times
the heatsink size and weight of the PWM.
3.0 HOW IT WORKS
The simple form of PWM circuit examined thus far is very
similar to a number of switching power supply circuits. If the
control block is optimized for producing a wide output range
rather than a fxed output level, the power supply becomes an
amplifer. Carrying this one step further we get the PWM circuit
employing four switches confgured as an H-bridge providing
bipolar load current from a single supply. This does mandate
that both load terminals are driven and zero drive results from
50% of supply voltage on both load terminals. See Figures 3
and 4 for the basic bridge operation and typical waveforms.
Vs Vs
Q2
Q4
Q1
Q3
A B
LOAD/FILTER
FIGURE 3. BIPOLAR OUTPUT OF THE BRIDGE
Vs
A
B
A-B
0
Vs
0
+Vs
Vs
95% DUTY CYCLE
(+90% OUTPUT)
50% DUTY CYCLE
(0 OUTPUT)
5% DUTY CYCLE
(90% OUTPUT)
FIGURE 4. H-BRIDGE WAVEFORMS
+PWM
-PWM/RAMP
CLK IN
DIV
2
CURRENT
LIMIT
THERMAL
DRIVERS
Vs
A
B
I LIMIT
FIGURE 5. BLOCK DIAGRAM
Discrete Linear Hybrid Linear Hybrid PWM
Waste heat 500W 500W 100W
Pkg count 16 x TO-3 2 x PA03 1 x SA01
Heat sink 0.11C/W 0.11C/W 0.55C/W
TABLE 1. CONTRASTING DISCRETE LINEAR, HYBRID LINEAR
AND HYBRID PWM 1kW DESIGNS
AN30
796 AN30U
NOTE: Some amplifers, such as the SA60 and others,
do not have the current limit feature, but do allow the use of
current sensing resistors for use in a current feedback loop.
Because these amplifers are unprotected, it can be tempting
to use large resistance values for R
SENSE
to limit the current
(I
MAX
= V
SUPPLY
R
SENSE
). However tempted you may be, DO
NOT attempt to use high value resistors for R
SENSE
. When you
do this, there is signifcant voltage developed across R
SENSE

- between the source of the lower output FET and ground.
This can allow the gate driver circuit to drive the gate of the
FETs below the source enough to blow them.
3.3 ACCURACY - CLOSED LOOP
In closed loop applications (the only kind that have any ac-
curacy), an integrating error amplifer is used to eliminate the
difference between command signals and feedback signals.
Its output voltage will go to the exact voltage required by the
PWM block to generate the proper duty cycle corresponding
to the desired output. The frst job of the error amplifer is
responding to input signal changes, but it also compensates
other variables inside the feedback loop. Variations in supply
voltage will require an adjustment of the input to maintain a
output stability. On resistance of the H-bridge, resistance of
the flter inductor and sometimes load resistance temperature
variations are compensated. Systems such as speed controls
may place mechanical factors such as conveyer belt load
weight inside the loop where the error amplifer compensates
the variations. Closing a voltage or current loop around PWM
amplifer is non-trivial. Application Note 41 discusses closed
loop PWM in great detail and is recommended reading for
designers looking for precision control from their PWM circuit.
The PWM circuit converts the error amplifer output into a
variable duty cycle drive signal that includes 0% and 100%.
A dead time (all 4 of the H-bridge switches turned OFF) is
inserted between each change of polarity at the output. This
prevents shoot through current spikes caused by both H-
bridge switches in the same leg of the H conducting at the
same time. If these spikes were allowed to exist they would
cause high stress and possibly destruction of both amplifer
and power supply components.
3.4 DUTY CYCLE
There are many methods for converting an analog input
into a PWM output. Of the methods used in Apex Precision
Power products, the following is most common and provides
a good foundation for understanding any of the various tech-
niques used by Apex Precision Power and others. Accurate
analog PWM generation is founded on a triangular reference
signal (sometimes simply called RAMP). To provide a good
reference, the ramp must have a linear rise and fall. The most
economical method for generating this ramp signal is to start
with a moderately stable square wave oscillator and use a
divide by two circuit to ensure that the duty cycle is exactly
50%. An R-C network can convert this square wave into a
reasonably linear triangle wave that is really exponential rise
and fall. With carefully chosen peak voltages, the error caused
by a non-linear triangle reference can be kept around 1% in
an open loop system because most of the error on the rise is
compensated on the fall. With a closed loop, the affect of this
non-linearity is virtually unnoticeable.
To generate a PWM signal, the analog input voltage is com-
pared to the triangle ramp reference. When the input signal
is greater than the ramp voltage the A side of the H-bridge
switches to V
S
and the B side to GND. Similarly, when the
input signal is less than the ramp, the B side switches to V
S
.
Figure 7 illustrates this principle. If the input is always within
the peak to peak ramp voltage then an infnitely variable duty
cycle can be achieved. If the input signal is outside the peak
to peak ramp voltage there is no switching - the A side or the
B side is V
S
(0% or 100% duty cycle)
For the safety of the amplifer, the load, and bystanders in
the general vicinity, it is important that the two switches on
the same side of the H-bridge are never on at the same time.
This would essentially create a short from V
S
to GND and it
would not be pretty. Dead time is the solution to this potential
problem. During the transition from the A side to the B side of
the H-bridge, there is a period of time in which neither side is
high - this is the dead time. Each amplifer has a fxed dead
time based on the properties of the switches used inside. Dead
time causes a small non-linear region in the variable duty
cycle near 0% and 100%. Notice in each product datasheet
that the output duty cycle will jump from approximately 97%
to 100% (or 3% to 0%). Dead time also contributes a very
small amount of inefficiency to the system. It is important to
note that some models have variable switching frequencies.
Since the dead time is not variable, efficiencies will drop as
switching frequency increases - the dead time accounts for a
larger percentage of the switching cycle.
In fgure 7, note that the input voltage depicted is a straight
line. The input voltage will obviously vary, but keep in mind
that the useful bandwidth of the PWM amplifer is signifcantly
+Vs
A OUT
B OUT
ILIM/SHDN
I SENSE A
I SENSE B
GND
CLK IN
CLK OUT
PWM/RAMP
+PWM
Vcc
SHUTDOWN
CONTROL
OUTPUT
DRIVERS
PWM
56K
470pF
2 OSC
CURRENT
LIMIT
9
8
3
10
4
2
1
5
11
12
6
7
FIGURE 6. PWM CONTROL BLOCK
+PWM
(INPUT SIGNAL)
-PWM/RAMP
A OUT
B OUT
DEAD TIME
FIGURE 7. PWM WAVEFORMS
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less than the switching frequency. If the slew rate of the input
voltage were allowed to approach that of the triangle wave,
dead time circuitry could be ineffective at preventing shoot
through.
The output waveform during dead time is primarily a func-
tion of load impedance. Current fow is interrupted by the
dead time and the load or flter inductance will discharge its
fyback energy at this time. While generally not shown in the
block diagrams, each power switch has a diode to conduct
the fyback current.
The outputs of this block labeled A OUT and B OUT do
not directly represent high and low states of the two ampli-
fer output pins. When the A Drive line is high it turns on the
switch between the A output and the power supply and also
the switch between the B output and ground. When the A Drive
is low, both these switches are off. B Drive controls the other
two switches in the bridge.
4.0 FREQUENCY, FREQUENCY, FREQUENCY
In designing with and using PWM technology, the switch-
ing frequency is one of the critical system parameters. Note
however, that most Apex Precision Power PWM datasheets
specify a clock frequency. Circuitry in the amplifer divides
this clock frequency by two to provide the basis for the triangle
or ramp signal. For example, the SA08 has an internal clock
frequency of 45kHz and therefore has a switching frequency
of 22.5kHz. The switching frequency is the basis for any flter
design that might be required.
Some PWM amplifer models include CLK OUT and CLK IN
pins. Generally these pins are simply connected together so
the amplifer generates its own clock source. You can, how-
ever, use the CLK IN pin to synchronize the clock frequencies
of multiple amplifers in a system or to some other external
source. In some cases this can be helpful for managing EMI.
However, the divide-by-two function does not guarantee that
the ramp signals of multiple devices are in phase, so simply
sharing the same clock source does not allow multiple ampli-
fers to be used in parallel. A parallel PWM design is not trivial
and is far beyond the scope of this text.
The third frequency important to consider in any PWM system
is the signal frequency. As mentioned previously, the PWM
signal must be averaged over time to achieve an analog type
of output. The precision and cleanliness of the signal depends
on how many output pulses are used to achieve the signal
level. As a rule of thumb, the analog signal frequency should
be at most 10% of the switching frequency. This relationship of
signal and switching frequency is analogous to analog to digital
conversion and the necessity to have many digital samples to
accurately represent the changes in the analog signal.
4.1 CHANGING THE CLOCK FREQUENCY
At times it may be useful to reduce the switching frequency
of an Apex Precision Power PWM amplifer. In some ampli-
fers, this is possible with the addition of an external capacitor
and a clock signal of the desired frequency. The Operating
Considerations discussion in the datasheet will indicate if this
is possible. The clock signal should be connected to the CLK
IN input pin and should swing from GND to V
CC
. The properly
sized external capacitor connected between the -PWM/RAMP
pin and ground will return the peak to peak ramp voltage to
the datasheet specifcations.
The exponential charge and discharge of the capacitor in the
R-C network determine the clock frequency. However, only
a simple ratio is required to calculate the size of the external
capacitor for the new switching frequency. Note that the toler-
ance of the natural switching frequency is 2%.
F
SW(natural)
C
(internal)
= F
SW(desired)
C
(total)
So,
C
(external)
= ((F
SW(natural)
C
(internal)
) / F
SW(desired)
) - C
(internal)
SA14 Example:
Desired switching frequency = 10kHz
Natural switching frequency = 22.5kHz
Internal Capacitor = 470pF
Solving for C:
Total C = 1058pF
588pF required externally.
560pF is the closest standard value and corresponds to a
switching frequency of 10.27kHz. If you insert a 10kHz clock
signal, the peak to peak ramp voltage will vary slightly from the
datasheet, but the center voltage will not change. Non-linearity
will result if the ramp voltages are extended far beyond the
datasheet specifcations.
5.0 DESIGNING WITH PWMS
PWM amplifers are high power switching devices whose
voltage and current slew rates often surpass those found in
either digital or analog circuits. Even though signal bandwidth
may not top 1KHz, adopting the viewpoint of an RF designer
can be very wise. Here are a few useful things to keep in mind:
** Wire inductance @ 20nH per inch
** Inductor voltage = dI/dt L
** Capacitor current = dV/dt C
** A good square wave = very large harmonic content
5.1 POWER SUPPLY BYPASS
It is difficult to over emphasize this aspect of the PWM
design. Most of us are familiar with the good design practice
of including a supply bypass capacitor at every IC in a low
level logic design. If this is not done, the high switching rates
cause problems on the power bus. As the most common fault in
switching circuit design, inadequate bypass causes ripple and
spikes on the supply line which make circuits inoperative and
can even destroy components. Careful attention to location, size,
ESR and ripple current capacity can result in a good design.
Power supply bypassing is a wideband job requiring at least
two components for satisfactory operation of the amplifer. Use
at least 10F per ampere of load current to bypass the lower
frequencies. Some applications appear to require many times
this amount of capacitance. Capacitors with lower ESR ratings
may ease the burden of fnding space for such large devices.
Locate this capacitor within a few inches of the amplifer. The
high frequency bypass is absolutely critical! Think of frequen-
cies in the 1 to 10Mhz range. Remember that many capaci-
tors appear inductive in this range. Use ceramic capacitor(s)
totaling 1F to 10F. Type X7R is recommended to ensure
low ESR and ESL. Connect these capacitors directly between
the supply and ground pins of the amplifer minimizing trace
length, i.e. trace inductance. To illustrate the importance of this,
consider a design having 3" between the supply pin and the
ground point that terminates the capacitor: At 20nH per inch
of parasitic trace inductance, the supply pin can have spikes
equal to the supply voltage! When this happens, signal integrity
is in question and peak voltages applied to components may
be twice expected values. Connect the capacitor right at the
amplifer pin.
The function of bypass capacitors is to satisfy AC current
demands of the amplifer, which is isolated from the power
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supply by the inductance of the very same line that connects
them. The degree of isolation increases with current magnitude,
frequency and distance. When this isolation prevents current
fow to the power supply, it must come from the bypass capaci-
tors. Attempting to calculate capacitor currents is a question-
able investment but ignoring them is no solution. Keep the
requirement in mind when selecting components and follow
up with temperature measurements on the prototype. Run the
system at maximum frequency and power until temperatures
stabilize. During this process, keep in mind that under-rated
capacitors can explode.
5.2 HOW MUCH INDUCTANCE?
PWM amplifers driving resistive loads with no fltering are
unable to modulate the output voltage, they can only switch
polarity. Loads with small amounts of inductance may over
heat with high ripple current even with a 50% duty cycle (zero
output) drive. Other types of loads may suffer performance
degradation if ripple currents exceed 1% or even 0.1% of the
full-scale current. Once a design limit on peak-to-peak ripple
current has been set, calculate minimum total inductance. It
is proportional to supply voltage and inversely proportional to
I
P-P
and switching frequency:
L = V
S
/(2FI)
where V
S
is the supply voltage and F is the switching fre-
quency. As an example, this means the SA01 (switching at
42Khz) on 100V needs 300mH to keep ripple current down
to 4A
P-P
.
5.3 GROUND CONCERNS AND LAYOUT CONSIDERATIONS
The circuit layout allows little room for compromise because
the PWM amplifer combines both high-speed switching of large
current and small-signal analog levels in one circuit. Though
challenging, successful PBC layouts are not unreachable with
some effort and care. However, some ordinary layout techniques
and practices (including those used by auto-routing software)
often cause major problems in switching applications, so be
sure not to violate the following rules.
1) Power supply bypass. Connect all capacitors directly to the
power-supply pins keeping trace/lead length as short as
possible. Use ceramic capacitors for the high frequency
content. Review the previous bypass discussion for more
details.
2) Star ground. Make all ground connections in a star pattern
with the ground pin of the amplifer at the center of the
star. The dI/dt produced by switching circuits can produce
substantial voltages over even short conductors that may
interfere with low-level analog signals.
3) Separate small signal and power grounds. Connect your
small signal ground the power ground star at only one point
- the center of the star. If your circuit uses low level logic as
well as small signal analog and high current PWM devices,
keep these three grounds separate, connecting only at the
center of the star.
Improper grounding can allow switching noise to enter the
small signal analog channels disrupting the control of the
signal. Using the star ground technique will ensure that high
currents in one ground path do not induce voltages at other
ground points. This is the only way to guarantee that the
ground reference is clean and stable at all important points.
4) Avoid capacitively coupled feedback. Parasitic capacitance
between traces or layers can couple unintended feedback
from the output to the input section of the amplifer. With
PWM outputs switching hundreds of volts in a few nanosec-
onds, it is not difficult to calculate what a few pF of parasitic
coupling might do in the circuit.
5) Keep small signal traces away from outputs. High current
outputs can magnetically couple to the small signal sections
of your circuit. Never, ever, consider running small signal
traces between the output pins.
6) Keep ground plane current to a minimum. If you are con-
vinced that you must have a ground plane, do not under any
circumstances connect high current return lines to it.
7) Keep traces to and from current limit resistors as short as
possible. The current limit threshold voltage on most Apex
Precision Power PWM amplifers is 100mV. Fast rise times
in the current limit resistors and parasitic inductance can
cause false current limiting or confuse the control logic in
the device. This particular bit of the layout can cause high
levels of hair loss if the proper attention is not given.
5.4 IS THE SCOPE TELLING THE TRUTH?
Could be, but touching the probe tip to the ground clip may
reveal otherwise. If the scope shows a waveform with this
grounded input, or all high impedance nodes appear to have
spikes that they should not, there are at least three possible
sources of error. The amplifer local ground may be quite differ-
ent from the local ground seen by the scopes input amplifers
and their common mode rejection is less than perfect. First,
disconnect all other signal cables from the scope to remove
interaction with any other local grounds. If a battery-operated
scope is available give it a try. If not, install a ground breaker
on the scope power cord.
Use only shielded probes, and do not use any extenders,
grabbers, or clips which do not have nearly complete shielding.
Capacitive coupling into high impedance nodes works best
when voltage slew rate is high and these switching amplifers
have plenty to get in trouble.
That 3" to 6" ground lead may have to go. It is forming an
inductive pickup loop and the PWM is moving lots of high
frequency current. If luck holds, the scope accessory kit will
yield an RF adapter capable of providing a ground lead less
than 1/4" long. If not, consider buying one or making your own
from a length of spring wire.
5.5 INTERNAL POWER DISSIPATION
PWM amplifers share the following thermal principles with
their linear counterparts.
Quiescent current and supply voltage determines standby
power.
Driving the load generates additional heat.
The heatsink must dissipate both the above.
The case temperature range must not be exceeded.
Load related power elevates power transistor junctions
above case temperature.
Maximum junction temperatures must be observed.
Lower temperatures (case and junction) increase reliabil-
ity.
There are two major differences in the thermal aspects of
linear power amplifers and PWM amplifers. First, power in
the PWM amplifer due to loading can be calculated without
knowing the output voltage or the supply voltage. The second
difference is subtle but affects the very reason a PWM ampli-
fer is used: Efficiency drops rapidly as junction temperature
increases. This means heatsinking the PWM is more than a
reliability issue. Thermal design of the PWM amplifer has a
frst order affect on circuit performance.
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First order calculation of power due to loading involves the
output current and the total ON resistance of the amplifer.
The high-speed waveforms present at the output pins do
indicate second order calculations could be made but this
document will concentrate only on the basic elements of
power dissipation.
Total On resistance includes impedance of the H-bridge
power switches (most often FETs) plus resistance of the metal
interconnects. Consult the amplifer data sheet to fnd the
contribution of each element. If interconnect resistance is not
specifed, consider it to be insignifcant. Consider interconnect
resistance to be constant over temperature. Because FET ON
resistance is a function of temperature, choose a maximum
junction temperature consistent with your design standards
(not to exceed the data sheet absolute maximum). Find FET
ON resistance(s) at your maximum junction temperature. I
2
R
now yields power due to loading. This is a single calculation on
lower current amplifers using all N-channel FETs, but requires
another calculation if P-channel FETs are used and a third if
interconnect resistance is broken out separately. Sum the above
calculations with standby power to obtain total heat loading on
the heatsink. If the amplifer has a separate low voltage sup-
ply pin, dont forget to include it in the total power calculation.
With total internal power dissipation now known, it is time
to determine the heatsink requirement. Again, consistent with
your design standards, choose a maximum case temperature.
Do not exceed the product operating temperature range listed
on the last line of the specifcations table. R
CS
is the thermal
resistance of the package to heatsink interface.
The last item to check is the junction temperature. Multiply
power in a single FET by the thermal resistance of the ampli-
fer and add to the maximum case temperature. In models that
have higher P-channel on resistance use the P-channel power
level and realize the N-channel devices will run cooler. An al-
ternative to fnding the specifc junction temperature is to fnd
the appropriate fraction of total power and then use the power
derating graph to make sure junctions do not exceed 150C.
As an example consider an SA01 delivering up to 10A
from a supply of 70V in a maximum ambient of 35C. Design
rules allow case and junction temperatures up to data sheet
maximums.
Standby power = 70V 90mA = 6.3W
N-channel power = 10A
2
.145 = 14.5W
P-channel power = 10A
2
.26 = 26W
Interconnect power = 10A
2
.05 = 5W
Total power = 51.8W
Maximum case rise = 85C - 35C = 50C
Allow .02C/W for case to heatsink thermal resistance
Heatsink maximum rating = 50C/51.8W - .02C/W = .95C/
W
Junction temperature = 85C + 26W 1C/W = 111C
This example would actually run cooler than the above
calculations would seem to indicate because junction tem-
peratures are lower than the assumed starting point and FET
ON resistance is lower. An iteration of the above based on an
assumed maximum junction of 110C would yield a heatsink
rating of 1.1C/W and result in maximum junction temperatures
of 106C. This will still have a small safety margin because the
N-channel junctions run cooler than the P-channel junctions.
It is interesting to note that heatsinking will not only protect
the amplifer from thermal problems, but it will also increase
the efficiency of the amplifer by maintaining low on resistance.
At lower temperatures, the FET ON resistance is lower and
there is less dissipation. Essentially, using a larger heatsink
will increase efficiency as well as protect the devices.
6.0 PWM TRANSFER FUNCTION
The transfer function of an op amp circuit is simple: V
OUT
=V
IN
gain. With the high PSRR of most op amps, supply
voltage variations are largely ignored. Thermal effects are
mostly second order, and changes in the load have little affect
on the output voltage. Of course, op amps are almost always
run closed loop.
PWMs can offer similar performance in a closed loop system.
How to close the loop is a topic for another discussion, but it
is important to understand how a PWM system behaves open
loop. PWM amplifers are affected by a variety of infuences
that rarely come into the picture in a linear design, or they are
present in a much more subtle way than with PWMs. Hope-
fully, this discussion impresses the importance of closing the
loop in most PWM systems.
The transfer function of a PWM amplifer is stated as fol-
lows:
V
O
=(((V
MID
-V
IN
)/V
PK
)V
S
)-(I
OUT
R
ON
)
Where:
V
O
= output voltage (averaged over time, i.e., fltered)
V
MID
= midpoint of the ramp signal
V
PK
= + of the ramp p-p voltage
V
IN
= input voltage
V
S
= supply voltage
I
O
= output current
R
ON
= total on resistance (1 switch if 1/2 bridge, 2 switches
if full bridge)
The equation above relates the output voltage (averaged
over time) to the input voltage, the ramp signal, and the losses
of the switches. There are several things to notice from the
equation above.
** There is no supply line regulation. As the power supply
varies, so does the output voltage.
** There is poor load regulation. As the load changes, so
will the output current, and the output voltage will vary by
I
O
R
ON
** The PWM amplifer is temperature sensitive. As discussed
in the previous section, the ON resistance changes with
temperature. Since R
ON
is a factor in the output voltage,
this must be dealt with.
So, it is easy to see that open loop operation of a PWM
amplifer is far from a precise endeavor. Closing the loop
locally around the PWM amplifer or using system feedback
to close the whole system are equally valid. It is sometimes
easier, but far from trivial to close the loop locally around the
PWM amplifer. This can eliminate all of the effects of the
sources mentioned above - and others that have not been
mentioned. Application note 41 discusses several methods for
analog closed loop solutions and how to use the PowerDesign
spreadsheet to aid in the design process.
7.0 DIGITAL INTERFACE TECHNIQUES
Apex Precision Power PWM Amplifers are analog products
by design. Most of the previous discussion has assumed that
R
SA
R
CS
T
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mode voltage range. The gain adjust potentiometer corrects
initial inaccuracies stemming from error amplifer voltage offset,
tolerance of the 3.83K bias resistor in the inverting input and
possibly even for offsets in the input signal. The 470 resistor
and the two associated capacitors form a low pass flter to at-
tenuate components of the switching frequency which may be
coupled to the tachometer through the motor. The gain adjust
potentiometer compensates tachometer variables of accuracy
and internal resistance plus tolerances of other resistors in the
feed back path. The 10K input resistor sets overall gain to 3.4.
The 3.83K resistor was selected to pull the inverting input of
the error amplifer up to 5V when both the input voltage and
tachometer output voltage are zero. The two R-C networks
were selected to provide circuit stability while maximizing sys-
tem response time. Specifc values will depend on both motor
parameters and mechanical load characteristics.
8.1 MOTOR POSITION CONTROL
While one of the simplest forms of position sensing is shown
in Figure 9, options such as optical encoders, LVDT sensors
and variable capacitance transducers are also viable. Again,
error amplifer inputs are biased to 5V. While 20K input and
feedback resistors would have set proper gain and biasing for
the inverting input, they would have allowed common mode
violations at the error amplifer. This could happen if the system
was at one position extreme while a very quick command came
in to travel to the opposite extreme. The three 30K resistors
the input signal is analog and a comparison is made to a tri-
angle ramp reference to generate the PWM signal. But, with
a few exceptions, Apex Precision Power PWM amplifers can
also be driven with digital input signals. The following discus-
sion explains how to interface an Apex Precision Power PWM
amplifer with a digital signal from a DSP or microcontroller.
Most Apex Precision Power PWM amplifers have 2 inputs,
PWM+ and PWM-/RAMP. To control the amplifer digitally,
apply the logic signal to PWM+. For the input signal to be
processed properly the PWM-/RAMP pin must be biased to
1/2 of the logic level. For example, for 5V logic signal, bias
PWM-/RAMP to 2.5V. The exact voltage of the bias is not criti-
cal as the two inputs go directly into a comparator, however
it is very important to use a low impedance reference. The
PWM-/RAMP pin has an internally generated triangle ramp
signal that must be overcome sufficiently that the comparator
can operate properly.
There may be a temptation to disable the internally generated
clock signal when using digital control. After all, if the DSP
or microcontroller is generating the PWM frequency, there is
no obvious reason for the internal clock. There is however,
a not-so-obvious reason to keep the CLK IN pin connected.
For amplifers with current limit circuitry, a low-side current
limit activation is reset once every clock cycle. If there is no
signal at CLK IN then any signal on the current limit pin that
activates the low-side current limit will shut down the amplifer
outputs until power is cycled.
7.1 SPEED KILLS
In most cases, the natural internal clock frequency of an
Apex Precision Power PWM is balanced to provide reasonable
efficiency while maintaining reasonable bandwidth. There are
cases that require more bandwidth than the natural internal
clock frequency will allow. By driving the PWM digitally, you can
extend the usable bandwidth. If digital control is approached
without caution, however, the consequences can range from
undesirable to devastating.
Really fast switching speeds can be dangerous. As input
cycle time approaches the rise time of the output drive signal
there is a real potential for destruction of the amplifer as well
as surrounding components and the load. The controlling
circuit inside the amplifer simply becomes overwhelmed
and confused when the input changes more quickly than the
output can follow.
Always observe the following rules when selecting a PWM
frequency:
1) Never increase the switching frequency more than twice
the internal PWM frequency of the amplifer given in the
datasheet.
2) Never apply any pulse shorter than 3% of the natural PWM
period of the amplifer.
8.0 TYPICAL APPLICATIONS
The following are a few example design discussions. In
most cases, the actual amplifer model is not important and
almost any model could be used in the same circuit topology.
However, there may be design considerations mentioned that
are specifc to a supply voltage issue or PWM frequency issue.
8.1 MOTOR SPEED CONTROL
The design steps of the PWM speed control employing a
tachometer feedback shown in Figure 8 are as follows: The
7.5V reference output is used to bias the non-inverting input
of the error amplifer to the middle of its 2V to 8V common
PWM
17V
.22 .022
470
GAIN
2.5K 32.4K 3.83K
.068
3.4K
.0047 470K
10K
5V
IN
7.5V
7.5V
1.47K 3.01K
100
OFFSET
M T
FIGURE 8. PWM SPEED CONTROL
.0047
10K
5K
7.5V
10V
7.5V
30K
5K
30K 30K
+10V
10V
470K
EA
PWM M
FIGURE 9. PWM POSITION CONTROL
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becomes critical. It should also be noted that even though the
signal gain is 20, the gain of offset errors is 50 because the
effective input resistance is the parallel combination of the
signal input resistor and the pull-up resistor.
8.3 PROGRAMMABLE CURRENT SOURCE - DIGITAL
Figure 11 shows a digital implementation of a programmable
current source. Only a half bridge is required for this single
sided current source. In a half bridge, the current sense resis-
tor (R
SENSE
) must be in series with the load to sense source
and sink currents. An instrumentation amplifer with a high
common-mode voltage range senses the voltage across the
sense resistor and feeds the information back to the controller.
9.0 CONCLUSION
The switching amplifer provides a solution to high power
drives that could otherwise require an inordinate amount of
heat sinking hardware. The arrival of the hybrid PWM speeds
the design process and in many cases greatly enhances fault
tolerance by offering protection circuits simply not possible in
a discrete implementation.
prevent common mode problems by increasing impedance
from summing junction to the two 10V signal levels at the
output and at the input while adding an impedance to ground.
8.2 COMMON VOLTAGE FEEDBACK CIRCUIT
Figure 10 shows a differential input, voltage controlled output
circuit resembling the familiar differential op amp confguration.
The SA01 includes the error amplifer within the package so
the circuit can really be quite minimal. Signal gain is 2RF/
RI. Again, two pull-up resistors are used to bias error amplifer
inputs within the common mode range. Select this value to
get 5V bias when both inputs are zero and both outputs are
1/2 the supply voltage (50/50 duty cycle.) At zero drive to the
load, this differential stage is rejecting 1/2 the supply voltage
present on both outputs. This means resistor ratio matching
DIGITAL
CONTROL
(TTL)
+PWM
-PWM/RAMP 2.5V
.01
Rs
LOAD
FIGURE 11. DIGITALLY CONTROLLED PROGRAMMABLE CUR-
RENT SOURCE
EA
EA OUT
OUT
A
B
SHDN/
FILTER
SHUT
DOWN
Cfilter
Rfilter
Rcl
PWM
SA01
Ri
Rf
Rf
Rf
Rf
Ro
Ro
Ri
Cf
7.5V
Cf
Cf
Cf
1K
1K
10K
10K
10K
10K
10K
10K
1
5
2
3
6
9
8 10
FIGURE 10. VOLTAGE FEEDBACK - SA01
IMPORTANT NOTICE
AN31
802 AN31U
AN31 Operational
Amplifer Basics
HISTORY
The performance and shape of operational amplifers has
changed considerably since the vacuum tube units were pro-
duced by George Phil brick, and others, over three decades
ago. Dis crete transistor-circuit op amps were the main catalog
item for com panies like Burr-Brown Research Corp. and Analog
De vices. The monolithic age of high-produc tion-volume op
amps began with the uA709 from Fair child. Mod ern op amps
have taken on many signal processing challenges. The Apex
Precision Power family has been spe cialized for high power
and high voltage. What ever the specialty or construc tion tech-
nique, the underlying theory remains the same.
IDEAL MODEL
An ideal opera tio nal amplifer (modeled in Fig ure 1) is a volt-
age con trol led voltage source. The input sense pins have infnite
imped ance to ground and to each oth er. The output source has
a zero output impedance and the transfer con stant (Open-
loop Gain, A
ol
) ap proaches infnity. This unit, simply placed in
a system, would be of little use in a linear mode without the
benefts of closed loop control in the form of negative feed back.
FEEDBACK CONTROL
Consider the circuit in Figure 2. For this frst example, the op
amp is placed in an inverting confgu ration with input resistor
R
i
and feedback resistor R
f
. Since the op amp input imped ance
is infnite, all current fowing through R
i
must fow through R
f
.
If one writes the equations for current fow from V
i
to V
o
and
solves for the V
i
to V
o
ratio the result is:
FIGURE 1. ELEMENTARY MODEL OF
AN OPERATIONAL AMPLIFIER.
Where: A
ol
approaches infnity.
The operational amplifer has now been converted into a
lin ear circuit element with sig nifcant possible ex tensions.
It is important to notice that the inverting input of the op amp
(junction of R
i
and R
f
) is maintained very near to the potential
of the non-inverting input. This point is a summing junction
and is called a virtual ground. The op amp out put is adjust ing to
main tain this re lation ship. This fact gives rise to two signifcant
exten sions. The input imped ance is constant at the value of R
i

and it is possible to have multiple in puts which are summed at
the output. Each input may have a different gain associ ated
with it as shown in Figure 3.
The output of this confgura tion is given by the expres s ion:
Our discussion up to here has ignored the non-inverting in put.
Write the current summa tion equations for the circuit in Figure
4 and solve for V
o
in terms of V
i
as above. With A
ol
approaching
infni ty, the fol lowing rela tion ship results.
This circuit has the features that the output signal is not
inverted as it is amplifed, the input impedance ap pro aches
in fnity, and the gain can not be less than unity.
By combining the inverting and non-inverting circuits it is
possible to make a full, wei ght ed sum and difference system
element as shown in Fig ure 5.
FIGURE 2. BASIC INVERTING CONFIGURATION.
FIGURE 3. SUMMING AMPLIFIER CONNECTION.
FIGURE 4. NON-INVERTING CONFIGURATION.
V
o
V
i
R
f
R
i
=
V
1
R
1
V
o
= R
f
+ +
( )
V
2
R
2
V
3
R
3
V
o
= V
i
1 +
( )
R
f
R
i
Operational Amplifier Basics
MAY 2009
APEX AN31UREVC
AN31
AN31U 803
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Through the use of super-po si tion the sum and difference
amplifer can be analyzed. The accuracy of this relationship
depends on the matching accura cy of the two resis tors labeled
R
f.
The complete trans fer func tion is given by:
NON-IDEAL OP AMPS
All of the discussion to this point has assumed an ideal
device. With real world op amps there are deviations from the
ideal, or errors. The magnitude of some of the possible errors
for an op amp are listed in the speci fcation sheet for that device.
A description of the circuits used to measure these parame-
ters can be found in the sec tion titled Parame ter Defni tions
& Test Meth ods.
When the magnitude of the er ror, as seen at the output, is a
direct function of the closed loop gain that error magnitude is
specifed referred to the input (RTI). The maximum error to be
expected at the output is the error value times the non-invert-
ing gain of the amplif er. The most common of these errors is
initial voltage off set.
Recall that the op amp works because the negative feedback
brings the inverting input to equal the non-invert ing input. When
con nected as a non-invert ing am plifer both inputs will be at a
potential equal to the input signal. Since this input is common
to both inputs it is called the Common Mode Volt age. In an
ideal amplifer the common mode signal would be subtracted
out and not appear at the output. Due to limita tions imposed
by the real world circuits there is an error sig nal at the out put
which is a function of the common mode voltage. A limit exists
on the range of the com mon mode volt age that the op amp
can with stand.
POWER SUPPLY SYMMETRY
To this point we have not consid ered the power supply
confguration. When op amps are furnished symmetric power
supplies common mode volt age limits are easy to meet. It is
general ly pos sible to operate from a single supply if the com-
mon mode volt age lim its are hon or ed. For further ex ten si ons on
single supply oper a tion Ap pli cation Note 21 should be stud ied.
AC CONSIDERATIONS
All of the relation ships discussed above can be extended
to the AC do main by re placing resis tance with im pedance
and allowing for the fnite frequency response of the op amp.
If a plot is made of open loop gain vs fre quency it would look
similar to Figure 6. This gra phic dis play is used to de scribe the
op amps open loop performance as a function of frequency
and to predict stabi lity.
The two change of slope points in the response curve are
caused by the existence of poles in the transfer function of the
op amp. Most op amps have Bode plots very similar to that
shown in Figure 6. The slope of the trace between 10 Hz and
1 MHz is -20 dB per fre quency de cade. Extensive dis cussions
of stability are pre sented in Application Note 19 and others.
In the opening discus sion we assumed the op amp gain to
ap proach infnity. The differ ence between the open loop gain
of the op amp and the closed loop gain, set by the feed-back
network, is re ferred to as ex cess loop gain. As the excess
loop gain decreases the op amp circuit deviates more from
the ideal. Consider the op amp of Figure 6 if it were used in a
closed loop gain confguration of 20 dB (X10) as shown by the
dashed line. At low fre quen cies the excess loop gain is 80 dB.
As the frequency is in cre ased the excess loop gain de creases
until it reaches zero dB at 100 KHz. The performance of the
circuit would be very near ideal at low frequencies and deviate
more from ideal as the frequency approached 100 KHz. If the
closed loop gain was increased to 40dB(X100). The non-ideal
response would become apparent one frequency decade earlier.
CONCLUSION
Some of the basic features of operational ampli fer circuits
have been dis cussed here. The concept of negative feedback
and the graphical representation of the Bode plot are the most
common tools used in op amp cir cuit design. The application
notes that follow present techniques for solving many of the
prob lems which arise in the use of op amps.
FIGURE 6. TYPICAL BODE PLOT.
FIGURE 5. SUM AND DIFFERENCE AMPLIFIER.
V
1
R
1
V
o
= R
f
+ +
( )
V
2
R
2
V
3
R
3
V
4
R
4
1.0 INTRODUCTION
Pulse width modulation (PWM) amplifers require low pass
fltering of the output to demodulate the PWM carrier. Some
applications also utilize the flter as a way to achieve an imped-
ance transformation which draws less power supply current
than is delivered to the load. These flters can be as simple
as a single inductor, to multiple LC nodes depending on the
application. In some applications the load will have enough
inductance to act as its own flter. Deciding on the type and
size of a flter can be time consuming since the calculations
can be tedious and often give component values that are not
easily obtainable. This application note is an effort to reduce
flter calculation time. Using the Apex Precision Power Power
Design tool, available at www.Cirrus.com. will further reduce
time. Power Design.exe is a self-extracting Excel97 spreadsheet
and will be used extensively in this application note.
2.0 FILTER TYPES
PWM flters are normally a low pass confguration. These
exhibit low attenuation to the frequency spectrum from 0 Hertz to
the frequency of cutoff (F
C
). This low attenuation region is called
the pass band. Beyond the F
C
, attenuation increases at a rate
determined by the flter type and the number of poles (order).
Figure 1 indicates the general response of the low pass flter.
Many different types of low pass flters exist. Each has
favorable and unfavorable traits and the selection usually is
a compromise of performance in one area to achieve desired
performance in another area. Some characterizations are:
pass band fatness, rate of attenuation, and phase shift versus
frequency. Common flters include Butterworth, Chebyshev,
and Bessel.
The Butterworth flter has a fat response in the pass band
and good roll off beyond the cutoff frequency. Component varia-
tions do not greatly affect the performance. It is considered a
good general flter that is often used and therefore will only be
considered here.
3.0 INITIAL CONSIDERATIONS
If you are unfamiliar with Apex Precision Power PWM
amplifers or with locked anti-phase modulation, please refer
to Application Note 30. This should convince you that using
unfltered PWM outputs is useless for some loads (applies only
full supply voltage) and can often be destructive to the load or
the amplifer. Filter design requires trading off many variables.
Here are some things to consider:
1. This flter design technique assumes amplifer output imped-
ance is low compared to the load impedance and that the
combined impedance of the load plus matching network is
constant over frequency. The demand for circuit efficiency
will insure the impedance relationship requirement is met.
Beware that changing load element values, without cor-
responding matching network value changes, will alter the
flter response curve. With some loads, such as solenoids
or valves that tend to change inductance with position, the
textbook response curve is nearly impossible to achieve. In
these cases, try designing for the highest impedance, and
then check performance driving the lower impedance.
2. As shown in Figure 2, a full bridge PWM amplifer driving a
frst order (single pole) flter with F
C
set at 1/10, the switching
frequency will be required to deliver approximately 15% of
the peak output current as peak ripple current. The ripple
is at the switching frequency; measured when the modula-
tion level is 50%; and assumes peak output current equals
Vs/R
L.
Figure 2 also indicates that changing to a second or
higher order flter will drop this to almost 10%. A second and
even more effective way to reduce this ripple current is to
widen the ratio between signal and switching frequencies.
As switching frequencies of Apex Precision Power PWM
amplifers range from 22.5KHz to 500KHz, this technique
has obvious limits
2.1 This ripple current fows through the frst inductor of the
flter, meaning high frequency core loss is of concern. With
frst order flters driving resistive loads, it also fows through
the load. With higher order flters, most of the ripple current
fows in the frst flter capacitor, affecting the ripple capacity
rating of these components.
2.2 In applications where full modulation is expected (output
current is expected to approach V
S
/R
L
), the workload imposed
on the amplifer by delivering the ripple current is of minor
concern. While 15% (or less as shown in Figure 2) of maxi-
AN32
804 AN32U
AN32 PWM Low
Pass Filtering
Passband
FC
Frequency
V
o
l
t
a
g
e

O
u
t
FIGURE 1. LOW PASS FILTER RESPONSE
PWM Low Pass Filtering
0
2
4
6
8
10
12
14
16
18
10 10 0
Fs w / Fc
N

=

1

N

=

2

N

=

6

FIGURE 2. OUTPUT RIPPLE CURRENT VARIES WITH ORDER
AND RATIO OF SWITCHING TO SIGNAL FREQUENCY
OUTPUT RIPPLE CURRENT AT 50% MODULATION
R
i
p
p
l
e
P
K

a
s

%

o
f

V
S
/
R
L

MAY 2009
APEX AN32UREVE
mum output may seem more than minor, Figure 3 shows this
ripple current decreases as modulation percentage moves
away from 50% (a graph of zero to 50% would produce a
mirror image curve) In other words, heatsink size is not
increased 15% because maximum DC output and maximum
ripple output never occur at the same time. The heatsink
will be sized to handle the much larger output current. The
ripple current curve of Figure 3 is also valid for half bridge
circuits, but the Vout curve would need to be re-scaled from
0.5 at 50% modulation to 1 at 100%.
2.3 For applications spending a major portion of the time near
the 50% modulation level, the ripple current will be quite
noticeable in terms of lowered efficiency (power supply load-
ing and heatsink temperature). These circuits include full
bridges spending most of their time delivering small signals
compared to peak output capability; full bridges whose peak
output voltage is considerably less than supply voltage; and
half bridges spending most of their time delivering half the
supply voltage.
3. Filter attenuation at 100% of cutoff frequency is 3db, that is,
a factor of 0.707 for voltage output (and consequentially,
current) and 0.5 for power output. Refer to Figures 4 and 5
for more data on attenuation as signal frequency approaches
cutoff frequency. Designing the cutoff frequency at least twice
the actual maximum signal frequency is a very common
technique to obtain a fatter response in the portion of the
pass band actually used.
4. With supply voltage and desired maximum ripple voltage
at the load held constant, a larger ratio between signal
frequency and switching frequency will lower the number
of flter poles required. This will lower cost, weight and size.
For example, starting with a 10:1 ratio requiring a 4 pole
flter; changing to 21.4:1 brings N down to 3; and changing
to 100:1 yields N=2.
5. In the design of servo loops or any other application where
feedback is taken at the flter output or beyond, phase shift of
the flter is critical to stability of the overall loop. With properly
terminated flters, phase shift at the cutoff frequency will be
45 per pole and the shift will decrease in a linear fashion
at lower frequencies. Power Design will calculate voltage
and current phase shift at the load for all cases, but frst and
second order flters are likely to be the maximum acceptable.
In fact, many designs use no dedicated flter components,
but instead rely on load inductance and resistance to form
a frst order flter. The important point to check is how this
inductance reacts to square waves of the switching frequency.
6. When using second and higher order flters, impedance
AN32
AN32U 805
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A
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
50 60 70 80 90 100
Ir
ip
p
le
V
o
u
t
FIGURE 3. RIPPLE CURRENT AND OUTPUT VOLTAGE IN THE
FULL BRIDGE
OUTPUT RIPPLE AND VOLTAGE
N
o
r
m
a
l
i
z
e
d

V
a
l
u
e
s
Percent Modulation
70
75
80
85
90
95
100
20 30 40 50 60 70 80 90 100
FIGURE 4. REDUCED V & I AS FSIGNAL APPROACHES Fc
VOLTAGE AND CURRENT OUTPUT
% of Cutoff Frequency
O
u
t
p
u
t

a
s

%

o
f

D
C

O
u
t
p
u
t
N

=

1
N

=

6
50
55
60
65
70
75
80
85
90
95
100
20 30 40 80 90 100 50 60 70
FIGURE 5. REDUCED POWER AS FSIGNAL APPROACHES FC
POWER OUTPUT
% of Cutoff Frequency
O
u
t
p
u
t

a
s

%

o
f

D
C

O
u
t
p
u
t
N

=

1
N

=

6
7
0.
0.
1.
1.
0.
8
9
1
1
2
0.1 0.3 0.5 0.7 0.9
N
=
6
N
=
1
FIGURE 6. AMPLIFIER OUTPUT CURRENT CAN BE MORE
THAN EXPECTED
AMPLIFIER OUTPUT CURRENT
N
o
r
m
a
l
i
z
e
d

O
u
t
p
u
t

C
u
r
r
e
n
t
Fraction of Cut Off Frequency
presented to the PWM amplifer will dip below the load
impedance as signal frequency approaches F
C
. Figure 6
shows this in reciprocal form. Putting some numbers to
go with the worst point: N=6, F
C
=1KHz, F
SIGNAL
=900Hz,
I
LOAD
=10A, amplifer output=12.3A. This extra current fows
in the output devices of the PWM amplifer increasing inter-
nal power, increasing ON resistance, increasing junction
temperatures and reducing efficiency. This effect should be
considered also with regard to amplifer and power supply
current ratings and design of current limit circuits. We will
see what looks almost like a duplicate of this graph when
discussing flter component stress levels.
Figure 7 shows efficiency data for a perfect component flter
(no parasitics) designed for an SA03 running maximum output
voltage into a 10 load while mounted on a 0.1C/W heatsink.
At 10% of F
C
, about 3.3% is lost in the amplifer and the flter
is having very little affect on efficiency. As signal frequency
increases, three effects combine to bring high frequency effi-
ciency down further. First, quiescent power remains constant
even though the output signal is rolled off. Secondly, the peaking
output current demanded by second and higher order flters
increases internal PWM losses. The last item is the positive
non-linear temperature coefficient of the ON resistance of the
PWM, which increased about 1% in this example. The point
here is that flter choices can double efficiency loss even before
allowing for flter component loss. Importance of this data varies
with the spectral content of the signal being amplifed. Consider
an audio application versus a fxed 400Hz inverter application.
Desired attenuation of the PWM square wave output must
be known to establish the order of the flter. While standard
flter equations assume sine wave inputs, the PWM applies
square waves at the switching frequency. Artifcially increasing
the bridge supply voltage by 25% approximates a correction
factor for this. A non-integer value of this requirement is given
in the following equation:
Where:
A (in db) = 20 log (bridge supply voltage * 1.25/load peak
ripple voltage)
F
X
= frequency of the desired attenuation (usually the switch-
ing frequency)
F
C
= flter cutoff frequency
N is rounded up to the next integer
Note that ripple voltage on the load is a differential specifca-
tion. With a full bridge circuit, it is not the voltage seen at either
load terminal with respect to ground.
4.0 FILTER TABLES
Filter analysis begins by developing general mathematical
equations to describe the flters. Each flter equation can be
reduced to a set of coefficients.
Filter coefficient tables are usually in a normalized form.
Normalized coefficients are calculated at a frequency of 1
radian per second and an impedance of 1 ohm. This is done
for convenience so the designer does not have to calculate
coefficients for every case. The normalized coefficients require
the designer only to scale the frequencies and impedances to
ft the particular requirement.
The flters most designers are familiar with are the sym-
metrical load type. These assume equal terminations on both
ends of the flter. These confgurations will generally not work
here because the output impedance of the amplifer bridge is
usually low and the actual load usually will be much higher.
Apex Precision Power PWM amplifers have room temperature
output impedances from less than 0.1 ohm to about 1 ohm and
are mostly resistive. The flter tables here assume a very low
source impedance and a higher impedance load.
The coefficient table also assumes zero loss components;
therefore, real components will compromise results.
Filter orders up to 6 are given which is more than what is
usually needed. Beyond order 5 or 6, the point of diminishing
returns begins as losses in the flter components, parasitics
of the physical layout, and undesired coupling eat up all the
theoretical advantages of additional poles.
The single-ended flter confguration is shown in Figure 8. A
frst order flter would use only L1, a second order adds C1, a
third order adds L2, and so on. The coefficients of Table 1 are
used directly to fnd values for these flters. This confguration
must be used with half bridge circuits and can be used with full
bridge circuits by substituting the second PWM output for all
the ground connections. This substitution is very rarely done
because it places the high speed square waves of the PWM
output on both load terminals and all the cabling between the
amplifer and load. With rise and fall times usually in the tens
of nanoseconds, and amplitude nearly equal to supply voltage,
this is an extreme RFI problem
5.0 FULL BRIDGE FILTER TOPOLOGIES
With full bridge circuits, an additional flter requirement
is introduced in that common mode voltage applied to both
load terminals usually needs to be minimized. The technique
to achieve low common mode voltage is to simply split the
inductor values in half, applying half to each PWM output as
shown in Figure 9.
If one could acquire a perfect PWM amplifer (equal rise and
AN32
806 AN32U
FIGURE 7. EVEN A THEORETICAL FILTER CAUSES REAL
POWER LOSS
N

=

6
N

=

3
N
=
1
OVERALL EFFICIENCY
Fraction of Cutoff Frequency
E
f
f
i
c
i
e
n
c
y

L
o
s
s
,

%
.01 0.3 0.5 0.7 0.9
-7.5
-6.5
-5.5
-4.5
-3.5
RL
C2
L2
C1
L1
PWM
FIGURE 8. FOURTH ORDER, SINGLE-ENDED FILTER
CONFIGURATION
N
A
10
F
X
F
C
2 LOG
[ ]
fall times, no dead time plus an exact out of phase condition),
this flter would output common mode voltage proportional to
inductor mismatch only. With real PWM amplifers, the output
will contain large amounts of high frequency harmonics. Each
application is different, but peak-to-peak noise amplitude may
approach the supply voltage. The spectral content of this noise
extends well above the switching frequency. A pair of small
capacitors added from the output side of each half of L1 to
ground, as shown in Figure 10, will remedy this problem. It is
not necessary (and sometimes it is counterproductive) to use
more than this one pair of leg capacitors. Placing these small
capacitors on the load side of L2 or L3 is not as effective as
the placement shown.
Value selection for these ground leg capacitors is less criti-
cal than for the main flter capacitors. It has been determined
empirically that setting the impedance value of these capacitors
at the cutoff frequency, to between 10 to 30 times the value
of the load resistance will provide reasonable common mode
fltering. The addition of these capacitors will typically produce
no more than 0.05db peaking, nor more than 0.2db change at
the cutoff frequency in any order flter. From the technical point
of view, the two Clegs are in series, and this is in parallel with
C1. This means that on all but frst order flters, C1 could be
reduced by half the value of Cleg to eliminate even these small
errors. Figure 11 shows the results of the following equation
where the impedance ratio was set to 23:1:
From a practical point of view, the lower left quadrant of this
graph is textbook material only when using second and higher
order flters. C1, C2, and C3 must be capable of bipolar operation
and will be an order of magnitude or more larger than the leg
capacitors. While the bipolar capacitors exhibit very low ESL
and ESR to provide good roll off in the high frequency spectrum,
this leads to very large and expensive banks of capacitors.
We previously noted that the two ground leg capacitors form
an equivalent capacitor one half the value of the two individual
devices. Carrying this thought a little further, we arrive at the
common topology shown in Figure 12 where only unipolar
capacitors are used, and where very good common mode
fltering is inherent.
Do not assume this dual capacitor topology is a panacea
for all high current, low frequency flters. The total amount of
capacitance increases fourfold over the single capacitor topol-
ogy. Additionally, the high frequency performance of these large
unipolar capacitors tends to fall off more rapidly than bipolar
varieties (ESL and ESR rise faster). As the two capacitors are in
series, the equivalent ESL and ESR are TWICE the individual
values rather than half. If maximum high frequency attenuation
is required, large high quality bipolar capacitors are a must.
The dual capacitor topology using unipolar capacitors always
works with second order flters and may work with higher order
flters. Be sure to read section 6.0 FILTER COMPONENTS,
where we will fnd it is very common for higher order flters to
apply negative voltage to these capacitors.
6.0 REACTIVE LOADS
One more time: to achieve these flter responses a constant
and purely resistive load termination is required. If a reactive load
can be modeled as resistance in series with either capacitance
AN32
AN32U 807
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A
RL
C2
1/2L2
C1
1/2L1
PWM
1/2L1
PWM
1/2L2
FIGURE 9. BASIC SPLIT INDUCTOR TOPOLOGY FOR THE
FULL BRIDGE
RL
C2
1/2L2
C1
1/2L1
PWM
1/2L1
PWM
1/2L2
Cleg Cleg
FIGURE 10. GROUND LEG CAPACITORS FILTER HIGH
FREQUENCY COMMON MODE NOISE
1/2L1
PWM
1/2L1
PWM
2C1 2C1
1/2L2
1/2L2
2C2 2C2
RL
FIGURE 12. DUAL CAPACITOR TOPOLOGY MAY ALLOW
UNIPOLAR CAPACITORS
FIGURE 11. GROUND LEG CAPACITORS FOR COMMON MODE
FILTERING
1
10
100
100 1000 10000
4
7
F
2
7
F
1
5
F
1
0
F
4
.
7
F
2
.
7
F
1
.
5
F
1
F
4
7
0
n
F
2
7
0
n
F
1
5
0
n
F
1
0
0
n
F
4
7
n
F
2
7
n
F
1
5
n
F
1
0
n
F
Cutoff Frequency, Hz
L
o
a
d

R
e
s
i
s
t
a
n
c
e
GROUND LEG CAPACITORS
TABLE 1. FILTER COEFFICIENTS
ORDER
1 1
2 1.4142 .7071
3 1.5 1.3333 .5
4 1.5307 1.5772 1.0824 .3827
5 1.5451 1.6944 1.382 .8944 .309
6 1.5529 1.7593 1.5529 1.2016 .7579 .2588
L1 L2 C1 C2 L3 C3
L =
COEF * R
L
2 * * F
COEF
2 * * F * R
L
C =
L in Henries
C in Farads
R
L
in Ohms
C =
1
145 FC RL
or inductance, a simple conjugate match network can be used
as shown in Figure 13. The resistor in the network will equal
the resistor of the load model. As the network is in parallel
with the load, all signals in the pass band will be applied to the
network and power dissipation must be checked. Realize that
combined impedance of the network plus load is constant and
that changing frequency shifts the power between the network
and the load. This means a 100W capacitive load drive will
require a 100W matching network if DC signals are allowed.
The Power Design frequency sweep capability will prove
quite useful in determining power dissipation and in possibly
choosing a non-perfect network trading off lower power dis-
sipation for some distortion of the ideal flter response curve.
Figure 14 illustrates one response example where the ideal
match network resistor was doubled to reduce power dissipa-
tion. It is perfectly acceptable to omit the network as long as
the resulting attenuation curve is also acceptable.
7.0 FILTER COMPONENTS
Filters used in high power switching circuits often are the
largest physical part of the circuit. Expect the flter to occupy
more space than the rest of the circuitry. Expect currents and
voltages to be greater than the output signal.
Filter components should be low loss, high current, high
frequency devices. Check current ratings carefully as different
manufacturers can use different rating methods. Make sure the
inductors chosen have the required inductance at the maximum
rated current and at the square wave switching frequency (many
inductors are rated only with sine waves applied). We have seen
laminated steel core inductors destroy circuits even when cutoff
frequency was only 100 Hz! Successful applications usually
implement powdered iron, ferrite, or air cores.
Polyester, polycarbonate, polypropylene, and chip ceramic
capacitors are often used in the best PWM flters. Tantalum
(preferred if voltages and temperatures allow) or electrolytic
capacitors may be required in low frequency flters. The capaci-
tors should have low loss at the switching frequency and well
beyond (to at least the tenth harmonic).
While there is absolutely no substitute for fnding real parasitic
values for flter components, Power Design provides a default
parasitic calculator for frst pass design efforts, as shown in
Figure 15. Parasitics vary WILDLY form part to part. The default
calculator is ONLY intended to get somewhere in the pall park.
These defaults are reasonable for parts suitable for switching
applications. Your real parts could be better, but could easily
be much worse.
Consult manufactures data sheets or measure the parts to
get accurate data.
Components loaded into this sheet by the PWM Filters
sheet are for single-ended flters (to minimize spreadsheet
size and sweep execution time). Use buttons 85-87 to put
physical component values
here for the type of flter
you intend to build. Values
to desi gn si ngl e-ended
flters will not be changed.
For split-inductor designs,
L will be divided by 2. For
dual-capacitor designs, L
will be divided by 2, plus C
will be doubled.
Enter actual parasitics or
calculate default values with
button 91.
Use buttons 88-90 to
re-load into the flter/load
area and run the sweep.
Values for Single-ended
designs are not changed.
For split-inductor designs,
L and the parasitic R will be
doubled plus parasitic C will
be divided by 2. For dual-
capacitor designs, inductors
will be treated the same as
for split-inductor designs
AN32
808 AN32U
FIGURE 15. TRANSLATING VALUES FOR THE THREE TOPOLOGIES AND
DEFAULT PARASITIC CALCULATION
-4
-3
-2
-1
0
1
2
1 10 100
A
t
t
e
n
u
a
t
i
o
n
,

d
b
FIGURE 14. TRADING MATCH NETWORK POWER FOR SOME
PEAKING OF THE FILTER
FILTER ATTENUATION
(In Load Current If Lout)
Frequency, KHz
FIGURE 13. CONJUGATE MATCHING NETWORKS
RL RL RM RM
CL CM
LL LM
FILTER FILTER
FILTER FILTER
-OR-
and C will divided by 2, plus parasitic R & L will be doubled.
Please note that even when using similar quality capacitors,
the Q of a dual capacitor equivalent of a single capacitor is
likely to be four times lower.
The folly of ignoring parasitics is illustrated by the data in
Table 2. A second order flter was designed to provide 100.9db
attenuation at the switch-
ing frequency. Using default
parasitics, attenuation is listed
for the three flter topologies
using electrolytic and plastic
capacitors.
There are t wo concl u-
sions to draw from this data:
frst, plastic capacitors have
a definite advantage over
electrolytic types. Secondly,
the dual-capacitor topology is
inferior to the other two. In a
related issue, do not fall into
the trap of thinking that adding
a small high frequency capaci-
tor in parallel with a much
larger one having poor ESR
and ESL will regain the ideal
attenuation. Adding a plastic
or ceramic capacitor equal
to 1/10 the value of the large
electrolytic brings attenuation
up to only 81.1db for the split-
inductor topology, still almost
20db short of ideal.
7.1 FILTER COMPONENT
STRESS LEVELS
Multi-pole flters are a com-
bination of one or more series
resonant circuits and they do
develop currents and voltages
above the input and output
levels as the signal frequency
approaches the cutoff fre-
quency. The highest stress
levels will be born by L1 and
C1. Higher order flters produce
higher amplifcation levels. The
last two components of the
flter do not see stress levels
above the signal level. Figure
16 illustrates these stress
levels for L1, L2, C1, and C2 for
all flter orders up to 6. Voltages
and currents are normalized to
the DC or very low frequency
output signal amplitude and
are based on ideal components.
Data on current can be used directly for any flter topology
for both inductors and capacitors. If a split inductor topology is
used, the inductor voltage data must be divided by two. Volt-
age data can be used directly for capacitors not connected to
ground. Ground terminated capacitors have a DC bias equal
to 1/2 the supply voltage which must be added to half the peak
voltage calculated from the graphs. To fnd peak capacitor
voltages the equation is:
V
PEAK
= Vs/2 + Vout
PEAK
/2 * graph reading
Do this calculation for BOTH the positive and negative peak
output voltages. Note that if output voltage is nearly equal to
supply voltage, and the flter order is three or more, the most
AN32
AN32U 809
G
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I
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C
B
A
G
H
I
F
E
D
C
B
A
TABLE 2. COMPARING FILTER TOPOLOGY AND
CAPACITOR TYPES
TOPOLOGY ELECTROLYTIC PLASTIC
Split-inductor 68.1db 81.8db
Single-ended 68.6db 82.4db
Dual-capacitor 62.4db 75.3db
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0.1 0.3 0.5 0.7 0.9
V
,

N
o
r
m
a
l
i
z
e
d

t
o

s
i
g
n
a
l

v
o
l
t
a
g
e
0.7
0.75
0.8
0.85
0.9
0.95
1
1.05
0.1 0.3 0.5 0.7
V
,
N
o
r
m
a
l
i
z
e
d

t
o

s
i
g
n
a
l
v
o
l
t
a
g
e
0.7
0.75
0.8
0.85
0.9
0.95
1
1.05
1.1
0.1 0.3 0.5 0.7 0.9
A
,

N
o
r
m
a
l
i
z
e
d

t
o

s
i
g
n
a
l

c
u
r
r
e
n
t
0
0.2
0.4
0.6
0.8
1
0.1 0.3 0.5 0.7 0.9
A
,

N
o
r
m
a
l
i
z
e
d

t
o

s
i
g
n
a
l

c
u
r
r
e
n
t
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0.1 0.3 0.5 0.7 0.9
V
,

N
o
r
m
a
l
i
z
e
d

t
o

s
i
g
n
a
l
v
o
l
t
a
g
e
0.7
0.75
0.8
0.85
0.9
0.95
1
1.05
1.1
1.15
1.2
0.1 0.3 0.5 0.7 0.9
V
,

N
o
r
m
a
l
i
z
e
d

t
o

s
i
g
n
a
l
v
o
l
t
a
g
e
0.7
0.8
0.9
1
1.1
1.2
1.3
0.1 0.3 0.5 0.7 0.9
A
,

N
o
r
m
a
l
i
z
e
d

t
o

s
i
g
n
a
l
c
u
r
r
e
n
t
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0.1 0.3 0.5 0.7 0.9
A
,

N
o
r
m
a
l
i
z
e
d

t
o

s
i
g
n
a
l

c
u
r
r
e
n
t
N
=
6
N = 5
N = 4
N = 3
N
=
4
N
=
5
N

=

6
N
=
6
N = 5
N = 4
N
=
3
N
=
4
N
=
5
N

=

6
N
=
6
N = 2
N = 1
N
=
2
N
=
6
N
=
3
N
=
4
N = 6
N
=
1
N
=
2
N
=
3
N = 6
N = 4
N = 3
N = 2
FIGURE 16. FILTER COMPONENT STRESS LEVELS
0.9
SIGNAL FREQUENCY VOLTAGE ON L2 SIGNAL FREQUENCY VOLTAGE ON C2
L2 SIGNAL FREQUENCY CURRENT C2 SIGNAL FREQUENCY CURRENT
SIGNAL FREQUENCY VOLTAGE ON L1 SIGNAL FREQUENCY VOLTAGE ON C1
L1 SIGNAL FREQUENCY CURRENT C1 SIGNAL FREQUENCY CURRENT
Frequency, Fraction of Fc Frequency, Fraction of Fc
negative going peak for C1 will be negative with respect to
ground. The same is true for C2 with ffth and sixth order flters.
This means even a ground-terminated capacitor can have
BIPOLAR voltages applied. From a practical point of view,
this situation implies the use of unipolar capacitors limits flter
order to two.
As an example, consider flter options for an SA06, which
is to deliver 470V to a 332 resistive load at 1KHz. Current
will be 1.414A peak or 1A RMS. Power will be 665W peak or
332Wrms. A supply of 480V will provide plenty of headroom
for internal losses and maximum linear duty cycle limitations.
The worst case for voltage and current extremes will be a
sixth order flter.
L1 peak current = 1.414A * ~1.23 = 1.75A
L1 peak voltage = 470V * ~1.82 = 850V
C1 RMS ripple current = 1A * ~1.82 = 1.82A
C1 peak voltage (differential) = 470V * ~1.17 = 548V
C1 + peak voltage (grounded) = 240V + 274V = 514V
C1- peak voltage (grounded) = 240V - 274V = -34V Must be
bipolar
The same math with graph values from the other four graphs
will yield stress levels for L2 and C2.
We can now make some general statements about flter
design. Higher order flters can increase component ratings by
as much as 82%. The two most costly increases are frst, the
ripple current on C1 and then the voltage rating of L1. While
lowering flter order helps this situation, an even better way
to minimize component requirements is to design the cutoff
frequency as a multiple of the maximum input signal frequency.
Turning this around, limiting input signal to one half or less
of the cutoff frequency, limits these stress level increases to
about 6% for sixth order flters and even less for more moder-
ate (and practical) orders. Figures 17 and 18 show the Power
Design answers for L1 and C1 stress levels of this example
modifed for a cutoff frequency of 2KHz rather than 1KHz. An
additional beneft of this change is a 2:1 reduction in the values
of flter components. The performance cost of this change at
the switching frequency is a reduction of attenuation equal to
6db for each order (@ N=4, -108db drops to -84db).
8.0 SAFETY CONCERNS
A word of CAUTION. These graphs were generated with
perfect components giving the best possible circuit Q, compared
to real components having losses and therefore generating
lower peaks. On the opposite side, these graphs refect perfectly
terminated flters; and normal component tolerances destroy
this perfection. Do NOT power up flters unless your are sure
they are properly terminated. Use Power Design to CHECK
COMPONENT TOLERANCES.
These graphs also assume sine wave inputs (the only wave-
form Power Design deals with). Figure 19 is a Spice simulation
of this original example showing L1 and C1 stresses when
the input signal is a 900Hz, 470V square wave. L1 voltage =
582V and is for 1/2 the total inductance. L1 current peaks at
2.14A. C1 current peaks at 3.18A. C1 is grounded and has
voltage peaks of 587V and -107V. The output is a very good
looking sine wave instead of a square, and peak amplitudes
have risen from 470V to 527V, from 1.414A to 1.59A and from
665W to 838W.
AN32
810 AN32U
0
50
100
150
200
250
300
0 0.2 0.4 0.6 0.8 1 1.2
0.99
1
1.01
1.02
1.03
1.04
1.05
1.06
1.07
0 0.2 0.4 0.6 0.8 1 1.2
MaxVpk= 387.5805
MaxApk= 1.503523
Peaks
calculated
from graph
maximums
FIGURE 17. DOUBLING Fc LOWERS L1 STRESS LEVELS
SIGNAL FREQUENCY VOLTAGE ON L1
L1 SIGNAL FREQUENCY CURRENT
s
m
r
V
,
s
t
l
o
V
s
m
r
A
,
t
n
e
r
r
u
C
Frequency, KHz
Frequency, KHz
FIGURE 18. DOUBLING Fc LOWERS C1 STRESS LEVELS
MaxA = 0.933137
330
335
340
345
350
355
0 0.2 0.4 0.6 0.8 1 1.2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 0.2 0.4 0.6 0.8 1 1.2
Red warning
appears if
grounded
cap is
driven
negative
As Differential Cap:
MaxVpk=497.9921
Max as Grounded cap:
PosVpk= 488.9961
NegVpk= -8.996067
Use Bipolar Cap
s
m
r
V
,
e
g
a
t
l
o
V
Frequency, KHz
Frequency, KHz
s
m
r
A
,
t
n
e
r
r
u
C
SIGNAL FREQUENCY VOLTAGE ON C1
C1 SIGNAL FREQUENCY CURRENT
V(VC1)
V(L1)
V(OUT)
-750
-500
-250
0
250
500
750
V
(
V
)
I (C1)
I (L1)
I (RLOAD)
-4
-2
0
2
4
I

(
A
)
4.5 5.0 5.5 6.0 6.5 7.0 7.5
TIME (ms)
FIGURE 19. SQUARE WAVES THROUGH A 6 POLE FILTER
COME OUT AS LARGER SINE WAVES
9.0 EXAMPLES
Example 1. The voice coil of a shaker table has 7 resistance
and 100uH inductance. The desired drive level is 50V peak from
10Hz to 2KHz. Starting with the Power Design, Part Selection
sheet, SA60, PA93, PA04, and SA01 are the frst choices in
order of cost. SA60 was rejected because it has no current
limit. In the Power sheet, it takes only about a minute to fnd
that the PA93 cannot handle the internal power dissipation
(about 140W). Switching to PA04 reveals the circuit is pos-
sible, but would require a 0.2C/W heatsink to keep junction
temperatures to 150C and has efficiency in the 50% area. This
temperature may not be acceptable from a reliability point of
view and leaves poor choices for the heatsink. Choice one is
the Apex Precision Power HS11 with liquid cooling; read this
as costing nearly as much as the amplifer before calling a
plumber. Choice two involves a custom heatsink.
The SA01 PWM amplifer is the most cost effective choice
and will run much cooler. With PWM amplifers, a power supply
voltage substantially higher than peak output voltage is not a
killer in terms of internal power dissipation. This allows an 80V
unregulated supply, saving a lot in terms of efficiency, cost and
design time over a regulated supply required by a linear solution.
The SA01 circuit will follow the voltage control example given
in Application Note 30 PWM BASICS. It was determined that
150mV peak ripple at the 42KHz switching frequency would
be acceptable. In order to maximize pass band fatness and
avoid the numerous pitfalls of driving signals right up to the
cutoff frequency, Fc will be designed for 4KHz. Figure 20 shows
this data loaded into the PWM Filters sheet of Power Design.
Figure 21 gives all the component choices for the third order
flter. If a single ended flter was desired, components under
that heading would be used. If a dual capacitor topology is
desired, use components from the dual cap column. To form
the most common topology, the split inductor, this example will
use inductors from the differential column and capacitors from
the single-ended column. Leg capacitors will be 0.27uF per
Figure 11. The 2.28Ap-p ripple will be the maximum ripple in
L1 at the switching frequency. The 0.57A is used to calculate
power loss in the amplifer.
The inductors will be custom wound. L1s are 47 turns of #12
on a Micrometals T184-18 torriodal core. L2s are 39 turns of
#12 on a T130-18 core. The single ended capacitor is metallized
polypropylene and the leg capacitors are X7R ceramic. The
matching network capacitor is a pair of 1uF, X7R ceramics in
parallel. Figure 22 shows the delivered power to
be about 2% low at the lowest frequencies. This
is primarily from copper loss in the inductors and
suggests a simple gain adjustment be included
in the circuit. At frst glance the power roll-off at
2KHz looks a bit large. However a linear sweep
analysis of a perfect drive to the voice coil reveals
the coil inductance itself is responsible for over
half this droop.
With your own copy of Power Design, you will
use the PWM Power sheet to fnd the SA01 deliv-
ers full power while averaging an internal loss of
under 15W. When mounted on the Apex Precision
Power HS16 without a fan, the SA01 will have a
case temperature rise of only 19C and junctions
only 3warmer. Adding in flter loss (including the
matching network) as shown in Figure 23, still
yields efficiency better than 92% over most of the
frequency band.
Example 2. This example illustrates the trans-
former-like action of a PWM system. The require-
ment is to drive a 2 thermo-electric cooler at 10V, using an
existing single 48V supply. Any linear solution will draw 5A or
240W from the supply and will need to dissipate 190W. SA60
is the least expensive PWM amplifer having analog input
capability. A 10Hz bandwidth will be plenty and ripple voltage
should be kept below 100mV across the cooler. It is also desir-
able to keep the common mode ripple as low as possible, so
a dual capacitor flter will be considered. A frst pass with the
PWM Filter sheet loaded with switching frequency=45KHz and
cutoff frequency=100Hz, called for inductors of 2.25mH and
capacitors of 1125uF. The large capacitance values suggest
electrolytic types which generally offer lower performance in
AN32
AN32U 811
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B
A
G
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I
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E
D
C
B
A
168
169
170
171
172
173
174
175
0 0.5 1 1.5 2 2.5
FIGURE 22. POWER DELIVERY TO THE SHAKER TABLE
LOAD V-A
s
m
r
A
-
V
Frequency, KHz
FIGURE 20. SETTING UP THE PWM DESIGN FOR ANALYSIS
N = 3 L1 = 0.2089 mH 0.4178 mH
C = 15.157 uF 7.5786 uF
L2 = 0.0696 mH 0.1393 mH
P-P Iripple = 2.2796 Amps out of the amplifier
Avg. Iout for thermal calculations = 0.5699
Shading indicates values for Split Inductor topology
Dual Cap Filter Single-ended Filter
FIGURE 21. THIRD ORDER DATA ONLY FROM THE
COMPONENTS SCREEN
23nH values calculated for the 10F capacitors. The equivalent
single-ended capacitor has half the capacitance and twice
the resistance and twice the inductance. Translate back to
single-ended with button 88 and return to the Defne Load
area when the sweep is complete. Now enter the equivalent
values for the pair of 10F capacitors as shown in Figure 27,
and run the sweep.
Now for the real beauty of this circuit: when delivering the
full 5A (50W), the SA60 mounted on an Apex Precision Power
HS03 1.7C/W heatsink (needs a mounting hole drilled), has
an internal dissipation of only about 15W! Throwing in flter
loss also, the supply is working to the tune of only about 70W,
or about 1.5A.
Example 3. This circuit drives a magnetic bearing requiring
up to 12A DC plus up to 3A peak AC up to 300Hz. Bearing
coil inductance is 5mH and resistance is 2. Using the Power
sheet reveals the AC drive will require 29Vpk, which brings
total peak voltage up to 54V. As the PWM circuit will be inside
a larger loop based on a position sensor, low phase shift is
much more important than amplitude accuracy. The SA03 will
handle this job using a current output circuit based on its data
sheet typical application. Maximum 22.5KHz ripple voltage at
the bearing is 1V peak. Knowing that flters shift phase the least
amount in the lowest portion of the bandpass, it was decided
to set the cutoff frequency to 3KHz. A split inductor topology
will be used with N=3. This data was loaded into Power Design
yielding 80uH for the L1s, 35uF for the capacitor, 27uH for the
L2s, and 1250uF for the capacitor in the matching network.
Leg capacitors will be 1uF. Figure 28 shows the initial current
control results.
In checking the graph on load current, it agrees by saying
current at 300Hz is down to about 20% of DC levels. The
ideal flter keeps output voltage constant in the pass band. In
this case the large inductance of the load called for an R-C
matching network, which draws most of the current at 300Hz.
the high frequency spectrum. A second pass at the design
set cutoff frequency at 1KHz, yielding the data in Figure 24.
In checking available metallized polypropylene capacitors,
it was discovered that a single-ended capacitor would cost
less than a third that of the pair of dual value capacitors. The
fnal flter shown in Figure 25 is a hybrid where the table for
leg capacitors is ignored and the three capacitors form the
equivalent of a 55uF single capacitor and provide excellent
common mode attenuation.
Figure 26 illustrates fnding default parasitics and loading
equivalent components to run the frequency sweep on. In the
Filter Component Work Area, enter values by hand and then
use button 91 to calculate the parasitics. Note the 0.1 and
AN32
812 AN32U
Pole 1 Pole 3
L1 0.45 mH L2 0 mH
Rl1 0.155 ohms Rl1 0 ohms
Cl1 12.8125 pF Cl1 5 pF
Pole 2 Pole 4
C1 50 uF C2 5 uF
Rc1 0.134949 ohms Rc2 0.1 ohms
Lc1 32.08661 nH Lc2 23 nH
FIGURE 27. MANUAL ENTRY OF COMPONENT EQUIVALENTS
FOR A HYBRID FILTER TOPOLOGY
-16
-14
-12
-10
- 8
- 6
- 4
- 2
0
1
FIGURE 28. THIS IS IDEAL RESPONSE?
0.001 0.01 0.1
FILTER ATTENUATION (In Load Current if Lout)
b
d
,
n
o
i
t
a
u
n
e
t
t
A
Frequency, KHz
Filter Component Work Area README
Pole 1 Pole 3 Pole 5
L1 0.225 mH L2 0 mH L3 0 mH
Rl1 0.0775 ohms Rl1 0 ohms Rl3 0 ohms
Cl1 25.625 pF Cl1 20 pF Cl3 20 pF
Pole 2 Pole 4 Pole 6
C1 50 uF C2 10 uF C3 0 uF
Rc1 0.134949 ohms Rc2 0.1 ohms Rc3 0.15 ohms
Lc1 32.08661 nH Lc2 23 nH Lc3 30 nH
Select Capacitor type: E=electrolytic, P=plastic or ceramic
p
P E
FIGURE 26. FINDING DEFAULT PARASITICS FOR A HYBRID
FILTER TOPOLOGY
TEC
2
50F
225H
PWM
225H
PWM
10F 10F
FIGURE 25. A CROSS BETWEEN SPLIT INDUCTOR
AND DUAL CAPACITOR TOPOLOGIES
0
1
2
3
4
5
6
7
8
9
10
0 0.5 1 1.5 2 2.5
FIGURE 23. POWER LOSS IN THE FILTER AND MATCHING
NETWORK
FILTER LOSS, REAL
W
a
t
t
s
,

R
M
S
Frequency, KHz
Dual Cap Filter Single-ended Filter
N = 2 L = 0.2251 mH 0.4502 mH
C = 112.54 uF 56.269 uF
Shading indicates values for Split Inductor topology
FIGURE 24. CHANGING Fc TO 1KHz YIELDS MORE
REASONABLE COMPONENT VALUES
To estimate internal power dissipation for the SA03, a new
sweep was run with amplitude set to the RMS sum of 12A
DC and 3Apk AC (~12.2Apk). Putting the 1.48C/W minimum
rating from this sweep into the Heatsinks sheet brings up the
HS06 rated at .96C/W. This will result in a case temperature
a little over 60 and junctions a little over 70 at maximum drive.
10.0 FINAL CONSIDERATIONS
DO NOT DRIVE THESE FILTERS WITHOUT PROPER
LOADING.
If you were taught to never have a load on a power circuit
the frst time you turn it on, be aware that the resonant circuits
of these flters can generate voltages many times larger than
the input voltage.
Poor circuit layout cannot be remedied by good fltering. PWM
circuits, by their nature, have high frequency, and high power
transients, that are difficult to eliminate from the desired output
signal. Use ground planes and shielding as much as possible,
but do not use these as a high current path. Use wide traces on
circuit boards for power supply and output signals and heavy
gauge wire for interconnects. Use star grounding techniques
with the PWM amplifer ground pin as the center. A very small
amount of inductance can cause large transients where high
currents switch quickly. A rule of thumb is to expect 20nH per
inch of conductor. Assume all output current changes its path
through the PWM output switches each cycle of the switching
frequency in 20 to 50ns. Space circuit board traces and wiring
away from sensitive circuits to avoid extraneous noise pickup.
Use bypass capacitors liberally.
The response curves for prefect components imply that the
attenuation increases continuously with increasing frequency.
With real components and real interconnects this is simply
not the case. If you have a design claiming 150db attenuation,
check it again.
We found earlier that removing a matching network causes
voltage peaking at the flter output; this is exactly what we need
to keep current constant due to the bearing inductance. Total
removal causes about an 8db peaking (a gain of about 2.5),
but a few iterations later, 470uF and 13 was found to produce
the results shown in Figures 29-34.
AN32
AN32U 813
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G
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A
-2
-1 .8
-1 .6
-1 .4
-1 .2
-1
-0 .8
-0 .6
-0 .4
-0 .2
0
0 0 .1 0 . 2 0 .3 0 . 4
FIGURE 31. OUTPUT VOLTAGE PHASE WITH THE MODIFIED
MATCHING NETWORK
LOAD VOLTAGE PHASE
D
e
g
r
e
e
s
Frequency, KHz
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 0.1 0.2 0.3 0.4
FIGURE 32. CURRENT OUTPUT PHASE WITH THE MODIFIED
MATCHING NETWORK
LOAD CURRENT PHASE
D
e
g
r
e
e
s
Frequency, KHz
0
5
10
15
20
25
30
35
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35
FIGURE 33. AMPLIFIER OUTPUT VOLTAGE WITH THE MODIFIED
MATCHING NETWORK
AMPLIFIER OUTPUT VOLTAGE
V
o
l
t
s
,

p
e
a
k
Frequency, KHz
0
5
10
15
20
25
30
35
0 0.1 0.2 0.3 0.4
FIGURE 34. POWER DISSIPATION IN THE MODIFIED MATCHING
NETWORK
POWER IN RMATCH
P
o
w
e
r
,

W
r
s
m
Frequency, KHz
1.95
2
2.05
2.1
2.15
2.2
0.2 0.3 0.4
FIGURE 30. CURRENT OUTPUT WITH THE MODIFIED MATCHING
NETWORK
LOAD CURRENT
Frequency, KHz
0.1 0.0
C
u
r
r
e
n
t
,

A
m
p
s
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.001 0.01 0.1 1
FIGURE 29. DB RESPONSE OF THE MODIFIED MATCHING NETWORK
FILTER ATTENUATION (In Load Current if Lout)
b

d

,

n

o

i

t

a

u

n

e

t

t

A

Frequency, KHz
PWM AMPLIFIER INTRODUCTION
The recent availability of high-voltage and high-current
PWM amplifers in hybrid packages has attracted the interest
of many designers who traditionally use linear amplifers. The
advantage of PWM amplifers is obvious: efficiency of 70 to
97%. High efficiency translates to lower internal power loss,
smaller heat sinks, and reduced overall physical size.
To make it easier to design with these amplifers, a simple
and versatile generic PWM Spice model lets you check out
PWM waveforms without the fear of blowing up the amplifers
or getting shocked by high voltages. The methodology behind
generating such a model applies not only to hybrid PWM ampli-
fers, but also to monolithic and discrete PWM amplifers. The
inputs to the model come from the PWM amplifers data sheet,
and you can run the model on any commercial Spice program.
Even though a PWM amplifer offers analog signals in and
analog signals out, its circuit functionality is entirely different
from a linear amplifers. A PWM amplifer modulates a pulse
train in the time domain and uses LC fltering to extract the
analog-signal output. You can use PWM amplifers to emulate
linear constant- voltage amplifers or linear constant-current
amplifers, both at much higher levels of efficiency.
If youre unfamiliar with how a PWM amplifer works, youre not
alone. Just like op amps, PWM amplifers come in many sizes
and favors, some with fancy bells and whistles. Fortunately,
the amplifers all operate under the same principle.
A PWM amplifer converts an analog signal into a pulse train
of variable duty cycle. The analog input controls the duty cycle
of the output pulse train, which switches on and off once during
each cycle. When a high output is necessary, the pulse train
switches on most of the time and vice versa.
Figure 1a shows a basic PWM amplifer. Vin is the analog
input of 1 to 8V dc. AOUT is a pulse train, and BOUT is its
inverse. The PWM oscillator determines the frequency of the
pulse train, and some PWM amplifers allow you to put in your
own PWM oscillator. As Vin changes from its minimum to its
maximum value, the duty cycle of AOUT changes from 0 to
100%, and the duty cycle of BOUT changes from 100 to 0%. The
difference voltage of AOUTBOUT has the same pulse train as
AOUT but with double the amplitude of 2xVs p-p (Figure 1b).
If you connect a dc brush-type motor across AOUT and
BOUT, you can control the motor speed with Vin. When you
set Vin in the middle of its range, for 50% duty cycle at AOUT
and BOUT, the motor stands still. With Vin at its maximum,
the motor turns at maximum rpm; with Vin at its minimum, the
motor reverses direction of rotation and turns at maximum rpm
again. You can directly connect AOUT and BOUT to a motor
because the winding inductance of the motor turns the pulsed
voltage into a rippled dc current whose magnitude controls
the motor speed and whose polarity controls the clockwise or
counterclockwise direction of the motor. As Figure 1a indicates,
most other applications need LC flters to flter out the PWM
pulse train to ensure that an analog signal appears at the load.
USE A GENERIC SPICE MODEL
Figure 2 shows the generic Spice subcircuit model of a
PWM amplifer. V1 is a ramp of fxed frequency. E1 serves as a
comparator that converts the PWM ramp as it crosses Vin into
a variable-dutycycle pulse train (Figure 3). S5, V5, S6, and V6
limit the amplitude of the pulse train to 5V. S1/R1, S2/R2, S3/
R3, and S4/R4 represent the four MOSFET drivers for which
AN33
814 AN33U
AN33 Spice Model and
PWM Amplifer Applications
PWM
OCILLATOR
H-BRIDGE
DRIVE
CIRCUITRY
VIN
VS
LOAD
A OUT
B OUT
0V
VS
VS
VS
0V
VS
A OUT
B OUT
(AOUTBOUT)
FIGURE 1.
(a)
(b)
A PWM amplifier (a) converts an analog signal into
a pulse train of variable duty cycle (b). AOUT and
BOUT can directly drive a dc motor, but most other
loads require additional LC filtering.
+
+
+
+
+
+
+
+
+
+
E1
1E9
V1
Vin
S5
S6
S4
S3
R3 R1
R4 R2
S1
S2
V5
5Vdc
V6
5Vdc
GND
X1
INV
+Vs
ISENSE B ISENSE A
BOUT
AOUT
FIGURE 2. A generic Spice model of a PWM amplifier includes
a fixed-frequency ramp (V1), a comparator (E1), an
inverter (X1), and MOSFET drivers (S1 to S4) and
their respective on-resistances(R1 to R4).
+
Spice Model and PWM Amplifier Applications
MAY 2009
APEX AN33UREVC
R1, R2, R3, and R4 are the respective on-resistances. The
four MOSFETs always turn on and off in diagonal sets, that is,
when S1 and S4 are on, S2 and S3 are off and vice versa. The
inverter X1 provides the diagonal switching control. ISENSE
A and ISENSE B are current-sensing terminals, usually avail-
able at two output pins for current-feedback control circuitry.
For open-loop operation or for voltage-feedback control, just
connect ISENSE A and ISENSE B to ground.
When an external load connects between AOUT and
BOUT, current fows from Vs to ground through one of two
routes: Vs to S1/R1, to an externally connected load between
AOUT and BOUT, to S4/R4, and then to ground or Vs to S3/
R3, to the external load, to S2/R2, and fnally to ground. The
voltage across the load actually doubles the Vs voltage. For
example, when Vs=100V, the voltage across the load is 200V
pp. This voltage-doubling feature is another advantage PWM
amplifers offer for high-voltage applications. To double voltage
using linear amplifers you must use two linear amplifers in a
bridge-mode confguration.
DESIGN EXAMPLE: CONSTANTCURRENT AMPLIFIER
You commonly use constant-current amplifers for applications
such as motor-torque control and battery chargers. You can use
the model and the specifcations of a commercial PWM ampli-
ferin this case, the Apex Precision Power SA50to design
a constant-current amplifer (also called a voltage-to-current
converter). You start out with the following specifcations from
the SA50 data sheet:
Analog input voltage/output duty cycles:
Vin=4V; AOUT=0% and BOUT=100%
AN33
AN33U 815
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+
E1
Vin
PWM RAMP
FIGURE 3. In the PWM amplifier model, E1 serves as a comparator
that converts the PWM ramp as it crosses Vin into a
variable duty cycle pulse train.
FIGURE 4. The analog input-voltage range and the switching
frequency (in this case, 4 to 8V and 45kHz, respectively)
determine the wave form of the PWM ramp.
TIME (SEC)
RAMP (V)
8
7
6
5
4
45 35 25 15 5
_
+
_
+
+
+
X3
PA26
X4
PA26
NOTES:
Ein: 10 TO +10V.
I(Load)/Ein= 0.5A/V.
V2
12
V3
12
VEE
VCC
+
Ein
R12
10K
VEE
VCC
C3
71n
C2
180p
Rq
600
C7
0.35
C6
0.35
C1
180p
R14
10K
R9
10K
R8
10K
R11
200K
R13
100
R15
100
Rb
0.1
Ra
0.1
R10
200K
Vin
+
Vs
80
BOUT
AOUT
L3
400
Lload
1m
Load
Rload
16
L1
400
C4
3.1
C8
3.9
C5
3.1
R17
16
+Vs
+
Vcc
12
Vcc
4.5 kHz
_
_
+
+
+
+
+
+
+
+
+
+
+ E1
1E9
V1
R3
0.25
R1
0.25
R4
0.25
R2
0.25
S1
V5
5
V6
5
GND
X1
INV
ISENSE B ISENSE A
S6
_S6_MOD
S3
_S3_MOD
S1
_S1_MOD
S2
_S2_MOD
S4
_S4_MOD
S5
_S5_
MOD
SA50
FIGURE 5. Combining the generic Spice model with the specifications for the SA50 PWM amplifier,
you can use the model to simulate a voltage-controlled, constant-current amplifier.
switching frequency: 45 kHz.
MOSFET on-resistance: 0.5 total or 0.25 each
The analog input voltage range of 4 to 8V dc and the switching
frequency of 45 kHz determine the waveform of the PWM ramp
(Figure 4), which V1 in Figure 2 produces. You can describe
this waveform as a constant-voltage source in any commercial
Spice program, such as Intusofts Model ICAP/4Rx V8.8.1. You
enter V1s parameters as manual-driven inputs, and this Spice
program automatically generates the following statement for V1:
V1 12 0 PULSE 4 8 0 11.1E-6 11.1E- 6 1E-12 22.2E-6, where
12 0 designates the two nodes for V1.
The MOSFET on-resistance of 0.25V determines the values
of R1, R2, R3, and R4. The addition of Rq=600 and Vcc=12V
model the SA50 amplifers quiescent current and the low-voltage
power supply necessary to power the H-bridge drive circuitry.
Figure 5 shows the complete Spice subcircuit for the SA50.
This basic SA50 can drive a bidirectional motor for which Vin
controls the motor speed and direction of rotation. You can
add LC flters that let you drive other loads. Even when driv-
ing a motor, LC flters next to the amplifer module are useful
for EMI and EMC purposes. Without flters, the long cables
to the motor carry high-voltage switching pulses and act as
antennas. Because the waveform across AOUT and BOUT
is a pulse train of variable duty cycle and because Vin, the
analog input signal, controls the pulse trains duty cycle or
pulse width, you must frst flter the PWM pulse train to extract
the analog output signal.
In Figure 5, the load comprises Rload and Lload. L1, C4,
L3, and C5 form a low pass flter with a cut off frequency (Fc)
of 4.5 kHz to flter out the SA50 amplifers 45-kHz PWM pulse
train. A rule of thumb is to set the LC flters corner frequency
one decade below the PWM frequency. Of course, you can
push the corner frequency higher by using multiple-pole LC
flters. The equations to calculate flter LC values are as follows:
Because of the flters differential confguration, these equa-
tions include a x0.5 factor for L1 and L3 and a x2 factor for
C4 and C5. In this example, Rload=16, and Fc=4.5 kHz, so
L1=L3=400 H, and C4=C5=3.1 F. Because the load for this
example is inductive, adding the matching network of R17 and
C8 creates a combined load of 16. The equations for R17
and C8 are as follows:
In this example, Lload=1 mH, and Rload=16, so C8=3.9
F, and R17=16. Similarly , if you have a capacitive load, you
can use a LR matching network to make the combined load
resistive, for which
Figure 6 shows the frequency response of the flter with and
without the matching network. Ignoring the feedback circuitry
of X3 and X4, a 1kHz 3.5V p-p sine wave with 6Vdc offset at
Vin produces a 120V pp sine wave across the load (Figure 7).
To complete the design of a constant-current amplifer , you
must have some means of sensing the load current and provide
feedback control in case of a load change. Ra and Rb are the
two current-sensing resistors. Op amp X4 and its associated
components serve two purposes: frst, as a difference amplifer
with a gain of 20 that converts the current difference between
Ra and Rb into a voltage output of 0.5A/V and, second, as
a lowpass flter comprising C1, C2, C6, and C7 that flters the
ripple currents in Ra and Rb with a corner frequency of 4.5
kHz. The design equations are as follows:
To minimize power losses, you should choose Ra and Rb
values of 0.01 to 0.1. In this example, Fc=4.5 kHz, R8=R9=10
k. To minimize loading effects, these resistors must be much
greater than R13=R15=100. Substituting these values into
AN33
816 AN33U
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-20
-40
-60
-80
A
T
T
E
N
U
A
T
I
O
N

(
d
B
)
FREQUENCY(Hz)
100 10k
WITHOUT MATCHING
NETWORK
WITH MATCHING
NETWORK
FIGURE 6. The LC filter's frequency response differs with and
without the matching network.
1.4142 Rload
2 Fc
and
0.7071
2 Fc Rload
L1 = L3 =
C4 = C5 =
0.5, (1)
2. (2)
R17 = Rload, (3)
C8 = (4)
Lload
Rload
2
GAIN = A/V, (6)
C6 = C7 = , (7)
C1 = C2 = , (8)
R9
R10 Ra
1
2 R13 Fc
1
2 R10 Fc
80
40
0
-40
-80
8
7
6
5
4
I
N
P
U
T

V
O
L
T
A
G
E

(
V
)
0.2 0.6 1.0 1.4 1.8
OUTPUT
INPUT
FIGURE 7.
O
U
T
P
U
T

L
O
A
D

V
O
L
T
A
G
E

(
V
)
TIME (mSEC)
Ignoring the feedback circuitry of X3 and X4, a 1-kHz,
3.5V p-p sine wave with offset at Vin produces a 120V
p-p sine wave across the load.
Rload Cload L
2

.
=
(5)
small error between the Spice output and the expected value.
For example, with Ein=10V, the expected output current
should be 5A, but Figure 8 shows 4.8A. This difference is
because of the loss resulting from the 0.25 MOSFETs on-
resistance. If you set the on-resistance to zero, you get exactly
Equation 7 and Equation 8, C6=C7=0.35 F, and C1=C2=180
pF. Choosing R10=200 k, Equation 6 yields a gain of 0.5 A/V.
X3 is an integrator that compares the error voltage from X4
with the input voltage Ein and provides the correct input voltage
for the SA50 amplifer to close the feedback loop. The design
equations for the integrator are as follows:
You can complete the design by choosing R12=R14=10 k
and C3=71 nF (Figure 6).
You can now run the Spice program. The load current
waveforms (Figure 8) are as expected. Note that there is a
LISTING 1SA50 CONSTANT-CURRENT-AMPLIFIER SPICE CIRCUIT
AN33
AN33U 817
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*#save V(1) V(25) @R4[i] @R4[p] V(3) @R1[i] @R1[p] V(5)
*#save V(29) @R3[i] @R3[p] V(7) V(19) @R2[i] @R2[p] V(9)
*#save @Vs[i] @Vs[p] V(10) @S4[i] @S4[p] V(11) @S2[i] @S2[p]
*#save @S3[i] @S3[p] @S1[i] @S1[p] V(12) @V1[i] @V1[p] V(13)
*#save V(18) @E1[i] @E1[p] @V5[i] @V5[p] V(8) @S6[i] @S6[p]
*#save @V6[i] @V6[p] V(17) @Rload[i] @Rload[p] @Lload[i] @Rb[i] @Rb[p]
*#save @Ra[i] @Ra[p] V(16) V(14) V(20) V(21) @R8[i] @R8[p]
*#save @R9[i] @R9[p] @R10[i] @R10[p] @R11[i] @R11[p] @V3[i] @V3[p]
*#save @C1[i] @C2[i] V(24) V(18) V(26) @R12[i] @R12[p] @VEin[i]
*#save @VEin[p] @C3[i] @R14[i] @R14[p] @S5[i] @S5[p] V(15) V(30)
*#save V(2) @L1[i] @L3[i] @C4[i] @C5[i] @R13[i] @R13[p] @C6[i]
*#save @R15[i] @R15[p] @C7[i] V(23) V(29) V(6) V(4) V(21)
*#save V(22) @V2[i] @V2[p] V(27) @Vcc[i] @Vcc[p] @Rq[i] @Rq[p]
*#save V(28) @R17[i] @R17[p] @C8[i] @Rload[i]
*#VIEW TRAN Y1
*#alias Y1 @Rload[i]
.TRAN 22.2E-9 4000E-6 0 22.2E-8 UIC
.PRINT TRAN Y1
R4 1 25 0.25
R1 3 23 0.25
R3 5 29 0.25
R2 7 19 0.25
Vs 9 0 DC=80
S4 29 1 10 0 _S4_mod
.MODEL _S4_mod SW VT=2.5 RON=1E-9 ROFF=1E9
S2 23 7 11 0 _S2_mod
S3 9 5 11 0 _S3_mod
S1 3 9 10 0 _S1_mod
X1 11 10 INV { }
.SUBCKT INV 1 2
* in out
B1 3 0 V=~V(1)
RD 3 2 1
CD 2 0 .87NF
.ENDS
V1 12 0 PULSE 4 8 0 11.1E-6 11.1E-6 1E-12 22.2E-6
E1 13 0 12 18 1E9
*#save @E1[i] @E1[p]
L1 23 4 400u
V5 15 0 DC=5
S6 11 8 0 13 _S6_mod
V6 0 8 DC=5
Rload 17 6 16
V2 0 22 DC=12
Lload 4 17 1m
Rb 25 0 0.1
Ra 19 0 0.1
X4 16 14 20 21 22 PA21 { }
.SUBCKT PA21 1 2 3 4 5
* PINOUT ORDER +IN -IN OUT +V -V
Q1 10 1 8 QI1
Q2 11 2 9 QI2
R3 12 8 7.39E+03
R4 12 9 7.39E+03
I2 12 5 3.61E-05
C1 12 5 2.73E-12
R5 12 5 1.11E+06
R1 4 10 8.85E+03
R2 4 11 8.85E+03
C2 10 11 9.00E-12
I1 4 5 3.70E-02
G1 6 15 11 10 1.13E-04
G2 6 15 12 15 6.36E-09
R6 6 15 1.00E+05
D1 6 15 DD
D2 15 6 DD
C3 6 7 3.00E-11
G3 15 7 15 6 8.85E+00
R7 7 15 1E3
D3 7 16 DD
V1 18 16 1.60E+00
D4 17 7 DD
V2 17 19 1.60E+00
RE1 15 0 0.001
E2 18 0 4 0 1
E3 19 0 5 0 1
R8 7 20 50
C4 20 15 3.08E-09
Q3 19 20 21 QOP
Q4 18 20 22 QON
Q5 4 23 29 QON
Q6 5 24 30 QOP
Q7 25 27 31 QLN
Q8 26 28 31 QLP
R11 21 23 1.70E-01
RCLP 29 31 1.70E-01
RCLN 30 31 1.70E-01
R13 22 24 1.70E-01
D5 23 25 DL
D6 26 24 DL
R9 27 29 1E3
R10 28 30 1E3
I3 18 23 7.92E-03
I4 24 19 7.92E-03
R15 31 3 5.42E-01
RSN 3 34 1
CSN 34 5 0.1E-6
.MODEL DD D(CJO=0.1PF IS=1E-17)
.MODEL DL D(CJO=3PF IS=1E-13)
.MODEL QI1 NPN (BF=6.55E+02 IS=8E-16)
.MODEL QI2 NPN (BF=4.24E+02 IS=8.46E-16)
.MODEL QOP PNP (BF=4.64E+02 IS=1E-14)
.MODEL QON NPN (BF=4.64E+02 IS=1E-14)
.MODEL QLN NPN (BF=100 IS=1E-14)
.MODEL QLP PNP (BF=100 IS=1E-14)
.ENDS
R8 16 30 10K
R9 14 2 10K
R10 14 20 200K
R11 16 0 200K
Vcc 27 0 DC=12
V3 21 0 DC=12
C1 16 0 180p
C2 14 20 180p
Rq 27 0 600
X3 0 24 18 21 22 PA21 { }
R12 24 26 10K
VEin 26 0 DC=10
C3 18 24 71n
S5 15 11 13 0 _S5_mod
L3 29 6 400u
R14 24 20 10K
C4 4 0 3.1u
C5 0 6 3.1u
R17 28 6 16
R13 30 25 100
C6 30 0 0.35u
C8 4 28 3.9u
R15 2 19 100
C7 2 0 0.35u
.END
R12 = R14, (9)
C3 = , (10)
1
2 (0.05Fc) R12
5A. Listing 1 is the complete Spice circuit description for the
constant-current amplifer.
CONSTANTVOLTAGE AMPLIFIER
In applications such as audio-speaker drivers, motor-speed
control, and power inverters, you need a constant voltage ampli-
fer. You can use the Apex Precision Power SA02 to design a
high efficiency, high-power PWM audio-speaker driver. The
SA02 data sheet lists the following specifcations:
Analog input voltage/output duty cycles:
Vin=1.25V; AOUT=0%, BOUT=100%
switching frequency: 250-kHz
MOSFET on-resistance: 0.42 total or 0.21 each.
The LC flter design is similar to that of the constant-current
amplifer except the LC flter requires no matching network
because of the 8 resistive load (Figure 9a). The SA02 ampli-
fers PWM frequency is 250 kHz, so the design sets the LC
flters corner frequency to 25 kHz. The design of the difference
amplifer (X4) is somewhat different, however. This constant-
voltage amplifer confguration senses the output voltage, not
the output current. The voltage at AOUT and BOUT is much
higher than the voltage across the current-sensing resistors
in the previous example. Instead of boosting the gain, resistor
dividers lower the sense voltage to levels that a small signal
amplifer can handle. The integrators (X3) time constant is
faster to provide the frequency response necessary for audio
applications. The SA02 audio-speaker driver has a 10V/V volt-
age gain and a 10-kHz power bandwidth. Figure 9b shows the
circuits input and output waveforms. Note that it takes about
50 sec for the outputs sine wave to stabilize.
The SA02 has many bells and whistles, such as thermal
sensing and external-logic shutdown, that the generic model
does not implement. A design engineer can easily analyze these
independent features with a paper and pencil. However, this
simple yet versatile model
makes it easy to model the
main PWM function when
manual analysis of this
feed-back-control circuit
becomes unmanageable.
AN33
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80
20 60 100 140 180
40
0
40
80
8
4
0
4
8
I
N
P
U
T

V
O
L
T
A
G
E

(
V
)
L
O
A
D

V
O
L
T
A
G
E

(
V
)
FIGURE 9 (B).
TIME (SEC)
_
+
_
+
+
+
+
X3
PA26
X4
PA26
V2
12
V3
12
VEE
VCC
+
Ein
R12
10K
VEE
VCC
C3
6n
C2
32p
C7
3.6n
C6
3.6n
C1
32p
R14
10K
R9
99K
Vs
80
R8
99K
R18
1K
R17
1K
R11
100K
R13
9K
R15
9K
R10
100K
Vin SA02
GND
ISENSE B ISENSE A
BOUT
AOUT
L3
36u
Rload
8
L1
36u C4
1.1
C5
1.1
10 KHz
+Vs
+
NOTES:
Ein: -6.5V to +6.5V.
E(Rload)/Ein = -10/V.
SAME MODEL AS FIGURE 5, EXCEPT Rq = 171 and R1 to R4 = 0.21.
FIGURE 9 (A). A similar model using specifications from the SA02 amplifier is part of a constant-voltage
feedback amplifier (a). The output sine wave takes about 50 sec to stabilize (b).
Vcc
12
Vcc
4
2
0
2
4
0.4 1.2 2.0 2.8 3.6
TIME (mSEC)
L
O
A
D

C
U
R
R
E
N
T

(
A
)
E
in
= 10V
E
in
=10V
E
in
=5V
E
in
=0V
E
in
= 5V
FIGURE 8. Spice-simulation runs indicate the load-current
waveforms of the constant-current amplifier for
various values of Ein.
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AN37 Power Dissipation
the Easy Way
1.0 INTRODUCTION
With the massive amounts of literature on the subject of
power dissipation, one may question why any more time should
be devoted to such a basic subject. Assume for a moment you
have your favorite text book(s) in front of you. Your mission is
to look up formulas to fnd heat both in the load and the driv-
ing amplifer. The chances are high that you will fnd yourself
in several chapters before you fnd Ohms Law (OK, forget that
one), impedance, phase shift and power factor for reactive load
elements and fnally power dissipation in the amplifer. By now
you probably have 10 to 20 formulas with at least three devoted
to the amplifer.
Of the three amplifer related equations (typically DC, current-
to-voltage phase angles less than 40, and phase angles greater
than 40), only one may be required. Even the power amplifer
data sheet is likely to present two separate thermal ratings for
below or above 60Hz. With the proper equations selected and
worked out in the right order, you have a wattage rating to apply
to the next group of equations needed to select a heatsink. The
sad part is that hours have passed.
By the way, did your research turn up a procedure for plotting
load lines? This is especially important for bipolar transistor output
amplifers having second breakdown limitations which can be
destructive even though a properly selected heatsink keeps the
amplifer cool. On top of all this, text covering amplifer power
dissipation presents classic circuits where one amplifer using
dual symmetric supplies drives a load with respect to ground.
This still leaves you on your own when it comes to bridge circuits,
single supplies, highly reactive loads at very low frequencies
or parallel amplifers. Calculating power dissipation is anything
but a basic subject.
If intuition or experience tells you it would be a major beneft
to have one piece of software that remembers all the equations,
can select the right ones and can apply them in the right order,
then Apex Precision Powers Power Design is a tool you need. It
is a Spice alternative dedicated to the analysis of power dissipa-
tion and local loop stability of the most common power amplifer
circuits. While written with hybrid power operational amplifers
in mind, it can be used with just about any power amplifer from
multiple KW discrete monsters down to the monolithic world.
2.0 FASTER WAY TO MORE ACCURATE ANSWERS
The traditional power dissipation equations for amplifers do not
appear in any cell of Power Design. Calculations start by fnding
peak and RMS values of current, voltage and power (both appar-
ent and true) in the load. For frequencies less than 60Hz, stress
levels are picked off the load line plot. This procedure catches
some stress levels that can slip by the traditional equations.
The DC equation yields peak power levels, but assumes zero
current-to-voltage phase shift. Both AC equations account for
increased heating in the amplifer due to the phase shift, but
yield only RMS power levels. Consider a 5Hz, 60 load where
the frequency is too low to use RMS power, but the peak power
is substantially more than identical currents and voltages in a
purely resistive application.
Power Design next calculates power delivered to the amplifer
from the power supplies. For frequencies at or above 60Hz,
true power in the load is subtracted from delivered power
to yield internal power dissipation. The key element here is
knowing what signal amplitude corresponds to worst case
power dissipation. A polynomial approximating worst case
signal amplitude is used to eliminate the step function found
when switching between the pair of traditional equations at
the 40 mark.
3.0 THE CLASSIC AMPLIFIER
Figure 2 illustrates the most common power amplifer con-
fguration and the one that relates directly to the traditional
power dissipation equations. It is also the starting point for
Power Design which will compute power levels for DC and
sine wave signals.
All data entry cells in Power Design are yellow on the
monitor (shaded in black and white as in Figure 3 shown on
next page). The data shown here will be used in the following
example. In the top left, a pull-down entry of amplifer model
reads an internal database containing enough specifcations
to fag operation outside the amplifers capability and to cal-
culate a heatsink rating. The data base contains all amplifers
manufactured by Apex Precision Power and comments in the
cells with red triangles tell users how to enter other data. This
feature makes Power Design valuable to a very wide spectrum
of engineers designing one ton rack mount systems down to
monolithic users. Model data has no effect on calculation of
load parameters. Going down, enter the supply voltage that will
be assumed to be the magnitude of both positive and negative
supplies. The next two cells specify minimum and maximum
frequencies for the output signal. .001KHz will work fne for
most DC applications. Next is magnitude of the output signal
followed by a pull down entry labeled Sig as ?. This is where
those magnitude units are defned as volts, amps or watts
with choices of peak, peak-to-peak or RMS. Yes, its that easy
to fnd what is needed to drive a 3.2 ohm speaker to 150W!
If your load can be modeled by one of the four simple dia-
Load Power
Supply
11W out
10VA
5W True
6W Internal
FIGURE 1. A SIMPLE VIEW OF WORK AND HEAT
Z
-Vs
+Vs
FIGURE 2. THE CLASSIC DUAL SYMMETRIC SUPPLY
OP AMP DRIVING A GROUNDED LOAD
Power Dissipation the Easy Way
MAY 2009
APEX AN37UREVB
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FIGURE 3. POWER DESIGN DATA INPUT SCREEN
FIGURE 4. ALL THE POWER DATA
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grams keep going down, entering component values. Each
load is computed independently so the previous entries other
than the 15 ohms and 0.3mH of our current R-L load make no
difference. If you have both an L and a C in your load and the
resonant frequency is shown as lying between your min/max
range, check the READ ME to see if you have a peak or a
dip as far as internal power is concerned. If your load is more
complicated, you will use the Defne command button. More
on this later. Just below the data entry cells, note the number
of watts labeled Piq. This is the standby power of the ampli-
fer you entered as the Model when running on dual supplies
of the value you specifed. For hybrid op amps this will be the
total quiescent current of the amplifer. For discrete designs,
quiescent current would normally be set to the quiescent current
of only the output transistors because the driver stages are
not normally on the same heatsink as the output transistors.
Referring again to Figure 3, to the right of the signal mag-
nitude entry cell is the pull-down bridge question cell. Make
sure this cell contains No. Below this is the cell specifying the
number of amplifers connected parallel. Make sure this cell
contains 1. Below this, we need
to specify Bipolar output current.
From here, go up to enter the
maximum ambient temperature
your application will encounter.
This is the starting point for the
heatsink. To the right, enter the
maximum junction temperature
you wish to allow for the power
transistors. 150 is acceptable
for many commercial applications
but in one respect transistors are
just like cars: the hotter your run
them, the shorter the life. Using
lower temperatures should be
considered when down time
would be very costly. The last
entry cell on this screen is that
of maximum case temperature.
In addition to life concerns, case
temperature affects DC accuracy
of the power op amp (check volt-
age offset and bias current drift)
and often has signifcant affect
on current limit values. In this
example, a tight DC error
budget mandates a maximum
case temperature of 70C.
To see power calculations
use the Results button under
the appropriate load diagram.
The entire power data output
is shown in Figure 4. Load
lines based on voltage output
from 90 to 270. With purely
resistive loads this produces
one-quarter cycle of current
output. With purely reactive
loads one-half cycle of current
is displayed. In this case the
amplifer seems to be loaf-
ing at high frequency and is
comfortably within SOA at low
frequency.
The left side of both curves seems to indicate current drops
to zero abruptly. This is not the electrical case, but is a function
of Excel plotting routines. Note that at low frequency the load
is mainly resistive (only ~7) and the curve shows maximum
current at minimum voltage stress across the conducting tran-
sistor (at the peak of the output voltage wave form). It drops to
zero current (right end of the curve) at a stress voltage of just
a little more than supply voltage or just a little after zero cross-
ing of the output voltage. At high frequency, the load is mainly
inductive (~85) and peak current appears at a stress voltage
approaching the supply voltage (near zero crossing of the output
voltage). Current does not drop to zero until stress voltage is
considerably more than supply voltage or until well after zero
crossing of the output voltage. This explains why current drops
better than 12:1 from low to high frequency but RMS internal
dissipation drops only about 6:1 and peak drops less than 5:1.
This SOA graph is dynamic in that the constant power portion
of the curve is drawn to meet the maximum case and junction
temperatures you specifed earlier. Data sheet graphs usually
show one curve for a case temperature of 25C plus others for
FIGURE 6. THE COMPLEX LOAD
FIGURE 5. HEATSINK SELECTION AND AIR VELOCITY CALCULATIONS
AN37
822 AN37U
elevated temperatures. All these curves assume maximum
junction temperature as published in the product data sheet
(up to 200C on some bipolar transistors) but this is not in the
best interest of long-term reliability. Power Design draws only
one constant power line according to the case and junction
temperatures you specify. If you assign an actual heatsink more
generous than the minimum for the application, the constant
power curve will be artifcially low until you use the Set Tcase
max according to last used Actual HS on... button.
For details on the load, refer to upper left block of numbers.
Just about all the electrical information you could want is
detailed. Mixed in here is a line showing power delivered to
the amplifer by the power supply (except for quiescent cur-
rent). Percent Efficiency = is based on watts drawn from the
supply (including quiescent) and VA delivered to the load. It
does not include power factor of the load. Vpk Capability is
supply voltage minus an estimate of the saturation voltage of
the power amplifer at the peak load current.
Turn your attention to the upper right hand corner where the
frst line of numbers indicate the peak output voltage producing
the maximum internal power dissipation. Below this are results
of power calculations at these worst case signal levels. The
bottom two are the most important:, true watts in the load and
power delivered to the amplifer. At low frequency signals, peak
internal power dissipation is at about 22.3Vpk, less than the
maximum signal amplitude specifed earlier. The Power Design
assumes real signal amplitude does vary and the amplifer
must be able to survive the lower signal level.
The 32.86W is then used on the left (long arrow) as well
as the 16.31 true watts that is subtracted from input power
to yield Dissipation RMS of 16.55W. Dissipation Peak is
higher than the RMS value but is ignored because minimum
frequency is well above 60Hz in this case. Total in the heatsink
at low frequency is the addition of the 16.55W RMS and 5.25W
calculated for quiescent earlier.
The same calculations are repeated for maximum frequency.
In this case the very high phase angle demands the amplifer
swing all the way to the supply rail (35V) to experience worst
case internal heating. As our maximum signal amplitude is
less, the input power (short arrow) and true load power are
used from the user specifed signal amplitude. Again, RMS
and quiescent powers are added to fnd the heatsink total at
maximum frequency (peak values are ignored). The last line
picks the higher power level of the two frequencies and displays
the DC thermal resistance if the frequency is below 60Hz or
the AC thermal resistance.
To the right with bold face heading we fnd the minimum
heatsink rating for this application. Your job is to fnd or design a
heatsink and enter its actual thermal rating. Entering the 1.7C/
W rating causes display of case and junction temperatures for
the amplifer. A little below this area are the actual calculations
which include thermal interface resistance between the ampli-
fer and the heatsink. Separate calculations are made to insure
both case and junction limitations are met. In this example,
case temperature is the limiting factor. If the heatsink had
been sized according to junction temperature only, the case
would have been running about 97, outside the guaranteed
performance range for drift with the commercial part.
In this general area you may also fnd up to three warning
fags. The most common warning is for excessive tempera-
tures. The other two warnings will pop up if your application
is demanding more voltage or current output than the ampli-
fer is specifed to deliver. The voltage calculation takes into
consideration the supply voltage and the output saturation
characteristics of the amplifer.
If youre asking whats so magic about 1.7C/W, refer to Figure
5 where an Apex Precision Power heatsink can be selected.
To use this sheet, simply enter the desired heatsink rating and
package type, then click on the command button. Even though
our example used the HS03 without a fan, note that an HS02
inside a 2x3 duct fed with a 15CFM fan would be more than
adequate to produce the required thermal rating.
4.0 USING THE COMPLEX LOAD
Using the load shown in Figure 6 requires complex numbers
which most Excel users do not automatically activate. You will
probably need to use Tools, Add-Ins and Analysis ToolPak.
Unless you have known good data already entered, use the
Zero the Load button to place extremely high impedance com-
ponents in all the vertical strings with a ground connection and
extremely low impedance components in the horizontal strings.
Refer to the sample load diagram in Figure 7 to illustrate
data entry. Lets start on the left at the amplifer connection.
Use any one of the three strings for the capacitor. Note that
we are also entering values for ESR and ESL for the capacitor.
These may be found on the data sheet or measured with an
impedance analyzer. R1 is used to model ESR of the 2200uF
capacitor and L1 to model ESL. It is important to open the other
two unused strings in parallel with our component model. The
easiest way to achieve this is entering zero capacitance in each
string. Our second group of components could again use any
of the three strings with a ground termination. The resistor is
actually a coil and parasitic inductance is also entered. Proceed
through groups of components until fnished.
After entering your load data, the View Results button will
show performance at the minimum and maximum frequencies.
To see whats happening in between, press the Frequency
Sweep button. Figure 8 illustrates typical results of a sweep.
This specifc load shows the need to analyze carefully in the
low KHz area.
Setting the min/max frequencies to 2/4KHz and re-running
the sweep as shown in Figure 9 will allow a more precise
determination of the peak values for current output and internal
power dissipation. Notice that peaks and dips do NOT coincide
exactly. In this case set Fmin to 2.54KHz and Fmax to 2.84KHz
and click View Results to see maximums in numerical form
and select the heatsink rating.
5.0 NORMAL BRIDGE CIRCUITS ARE EASY
The master/slave approach shown in Figure 10 is an easy way
to implement a bridge circuit. The master maybe be confgured
any way desired. The job of the slave is to invert the masters
output such that the load is driven equally but opposite at its
two terminals. The schematic suggests calculating internal
power dissipation might be tricky, but not so when using Power
C1
2200
C4
10
R4
4.5
R7
14
C10
4.7
R10
1
R16
12
FIGURE 7. A SAMPLE COMPLEX LOAD (PARASITICS NOT SHOWN)
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Impedance Loading the Amplifier
0
1
2
3
4
5
6
7
8
0 5 10 15 20 25 30 35 40 45
Frequency, KHz
I
m
p
e
d
a
n
c
e
,

O
h
m
s
Peak Output Current
0
1
2
3
4
5
6
7
8
9
0 5 10 15 20 25 30 35 40 45
Frequency, KHz
C
u
r
r
e
n
t
,

A
FIGURE 8. GRAPHS RESULTING FROM A FREQUENCY SWEEP
Amplifier Output Current Phase
-50
-40
-30
-20
-10
0
10
0 5 10 15 20 25 30 35 40 45
Frequency, KHz
P
h
a
s
e
,

d
e
g
r
e
e
s
Total Power in the Amplifier
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30 35 40 45
Frequency, KHz
I
n
t
e
r
n
a
l

P
o
w
e
r

D
i
s
s
i
p
a
t
i
o
n
,

W
a
t
t
s
Total Power in the Amplifier
0
10
20
30
40
50
60
70
80
90
100
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Frequency, KHz
I
n
t
e
r
n
a
l

P
o
w
e
r

D
i
s
s
i
p
a
t
i
o
n
,

W
a
t
t
s
Peak Output Current
0
1
2
3
4
5
6
7
8
9
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Frequency, KHz
C
u
r
r
e
n
t
,

A
FIGURE 9. ZEROING IN ON THE PEAK VALUES OF A COMPLEX LOAD
Design. Enter signal amplitude applied to the total load, enter
the total load components, enter Yes for the bridge ques-
tion and all the modeling is taken care of automatically. Load
impedance shown will be the total value, currents are for load
and each amplifer. Voltages, wattages and heatsink ratings
are for a single amplifer and are fagged as such.
6.0 SINGLE OR NON-SYMMETRIC SUPPLY BRIDGES
REQUIRE A TRICK
The circuit shown in Figure 11 is often used to achieve bi-
directional drive on a single supply or to double voltage swing
capability when a single higher voltage amplifer is not cost
effective or does not exist. To easily accommodate ground
referenced small signal driver circuits, a small negative supply
is often used to overcome common mode voltage restrictions.
Note that zero drive to the load requires both amplifer outputs
to be equal to that of the voltage divider (two equal resistors).
This forces the center of the load to be constant and at 50%
of a true single supply or centered between the two supply
voltages. If one algebraically subtracted the correct voltage
from both the positive and negative supply pins of the ampli-
fers and the lower divider termination, you would end up with
operation identical to the symmetric supply bridge of Figure 10.
For Power Design to analyze this circuit, enter a supply volt-
age equal to half the single supply or half the sum of the absolute
values of both supplies. For 110V single supply, enter 55V. If
an opposite polarity supply of 10V is added, enter 60V.
7.0 BIAS LEVELS ON AC ONLY LOADS
There are two bias voltages to determine with AC only loads;
one affects internal power dissipation, the other does not. Refer
to Figure 12, noting that neither bias level affects output cur-
rent. The DC blocking property of the load capacitance means
current demand is a function of only the load impedance and
the applied AC signal. DC bias levels can be ignored, even if
they result from the load being terminated at one of the ampli-
fer power supplies or a separate supply. While constant load
bias has no affect on internal power dissipation, output bias
directly affects voltage across the conducting transistor and
therefore power levels. Power Design always assumes output
AN37
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bias is zero meaning equal power dissipation in both transistors.
Given a requirement to drive a capacitive load at 7.07VAC
riding on 100VDC, the least expensive op amp solution would
be a 100V reference supply and a low voltage op amp. The
catch is that this reference supply must sink and source current.
If using an output flter capacitor 10 to 100 times the value of
the Cload is acceptable, this type solution is likely to be lower
cost overall. Remember that if these two capacitance values
are constant, the resulting drive voltage errors due to the non-
zero impedance of the reference supply can be compensated
by increasing the drive signal.
Refer to TABLE 1 for a way to approximate power levels
given the following assumption: +120V and -10V will be used
to accommodate voltage saturation on the high side and
common mode voltage on the low side. Calculate voltage
stresses on each transistor from mid point of the sine wave to
each supply. In this case, 20V to the positive supply and 110V
to the negative supply. Run two calculations using each of
these values. Select an arbitrarily large initial heatsink value.
The numbers in TABLE 1 are a result of a PA88 driving 15
ohms and 0.04uF at 40kHz with Ta=25, Tc max=70 and the
actual heatsink 1.7C/W. Subtract case temperatures from
junction temperatures to fnd temerature rise. The 110V data
tells us the hardest working transistor is 35.5 above case
temperature. The 20V data tells us the other transistor is only
6.2 above case temperature. Now set supply voltage to 65V
(the average of 110 and 20) to fnd a minimum heatsink rating
of 10.3 C/W is required. Enter an actual heatsink rating, such
as 4.5C/W corresponding to an Apex Precision Power HS02
with no fan. To fnd a case temperature of 44.8C add to this
the previously calculated temperature rises. To fnd the output
transistors junction temperatures of 80.3 and 51C. Iterate
the last step if this is too hot.
Vs Tj Tc Delta Heatsink
110 73.2 38.2 35.5 6.1
20 33.5 27.3 6.2
TABLE 1. MULTIPLE PASS METHOD OF DETERMINING
TEMPERATURE WITH DC BIAS ON A CLOAD
8.0 TECHNIQUES FOR PARALLEL OPERATION
Calculation methods for parallel operation of power ampli-
fers is simple; however, getting two or more power amplifers
to cooperate rather than kill each other is often quite another
matter. Power Design assumes all the precautions of Apex
Precision Power Applications Note 26 PARALLEL CONNNEC-
TION or some other authoritative reference have been followed.
Potentially destructive currents between amplifers are NOT
modeled. Causes of these currents include voltage offset,
common mode errors and violations, phase shift, and current
limit sequence errors. If you have overcome all these, refer to
Figure 13 for the most common approach to parallel opera-
tion along with a way to think about an equivalent load for the
single amplifer.
To use Power Design for parallel operation, enter the number
of amplifers in parallel in the yellow cell below the bridge ques-
tion. Total values are then calculated for the load results area
and scaled by the number of amplifers for the SOA graph and
amplifer internal power dissipation results. The heatsink rating
will then need to be applied to each amplifer.
9.0 UNIPOLAR OUTPUT CURRENT
Programmable Power Supplies (PPS), Thermo-Electric
Coolers (TEC) and heaters are often confgured for current
Z
-Vs
+Vs
R
R
+Vs
-Vs
Master
Slave
FIGURE 10. THE MOST COMMON METHOD USED TO
IMPLEMENT A BRIDGE CIRCUIT
Z
-Vs
or
Gnd
+Vs
R
R
+Vs
-Vs
or
Gnd
Master
Slave
+Vs
-Vs
or
Gnd
FIGURE 11. THE CLASSIC NON-SYMMETRIC BRIDGE CIRCUIT
Load
VDC
+Vs
-Vs
Vref
VDC
Output
Bias
Bias
FIGURE 12. BIAS LEVELS FOR AC ONLY LOADS
-Vs
+Vs
Master
+Vs
-Vs
Slave
Z
1 = 2 2
2F = 1F 1F
FIGURE 13. A COMMON PARALLEL CIRCUIT AND CIRCUIT
ALGEBRA TO MODEL A SINGLE AMPLIFIER'S
LOAD CURRENT
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FIGURE 14. OUR CLASSIC EXAMPLE TURNED INTO A UNI-POLAR CURRENT OUTPUT AMPLIFIER
of only one polarity. This means only one output transistor
is doing the work and therefore the DC thermal resistance
specifcation of the amplifer must be used even if the signal
frequency is quite high. Most op amp data sheets footnote
the AC rating as applying if current alternates between the
two output transistors are at a rate greater than 60Hz. The
mechanism yielding an improved AC rating is simply a larger
square area of the package materials used to conduct heat
when two transistors are active.
All the previous examples assumed output current was
bipolar. In cell D13 (under the parallel question), you can enter
Unipolar to force all heatsink calculations to be based on DC
thermal resistance and change the quiescent power calculation
to refect the supply voltage you entered as being a true single
supply, plus change the supply problem fag.
A word of caution is in order here. Many loads will demand
bipolar current even though the voltage is uni-polar. The easiest
to visualize is the capacitive load: current fow is determined only
by rate of change and direction of change. Both positive and
negative direction changes can be achieved without changing
polarity. A good rule of thumb is to not use this feature if the
phase angle for your load is greater than 10.
If your application uses a low voltage supply opposite a high
voltage supply which is doing all the work, enter the high volt-
age supply ignoring the low one. This will result in an error in
quiescent power by a factor of Iq*Vs low (usually negligible).
Returning to our classic example with the PA09, reducing
the maximum frequency to 1.2KHz and setting cell D13 to
Uni-polar results in data shown in Figure 14. The frequency
change keeps us within the 10 limit. Note that neither peak nor
RMS power dissipation has changed but total in the heatsink
has come down 2.63W. This change is due to total supply
voltage being reduced by 35V. Thermal resistance used has
jumped from 1.25C/W (AC rating) to 1.6 (DC rating). Just as
before, the limitation of this application is case temperature
rather than junction temperature. It is interesting to note that
the same heatsink now produces a case temperature about 5
lower but the increased thermal resistance produces junction
temperature only 1 lower.
10.0 A LITTLE WHAT IF? GAME
You have a PA12A rated at +/-50V, 15A, 125C case, 200C
junction. It can drive to within 5V of the rail at 5A and to within
6V at 15A. How much power can be delivered when mounted
on a 0.5C/W heatsink?
The frst correct answer is: that depends. Start with a sine
wave driving a 225 ohm pure resistor which will be voltage
limited. We need no help on this one; 45V peak output will drive
.2Apk or 9W peak or 4.5W RMS. Yes, a ridiculous job for the
PA12A but it shows the importance of impedance matching.
Set up the PA12A as above, set the signal to 44Vpk and defne
the load as 4.4 ohms (0mH). This would be 10Apk, 440W peak
and 220W RMS. Can it be done? Still depends. If you have
a frequency below 60Hz, no; if not, we are just barely over the
limit. Assume we must operate below 60Hz. What can we do?
Lower the peak output voltage and the supply voltage by equal
amounts until the TOO HOT fag goes away. Did you arrive at
something like 120W RMS and 240W peak?
Change the rules just a bit; stay below 60Hz, but you may
vary the load resistor to achieve maximum output power. High
power demands high efficiency which means saturation voltage
loss (a relatively constant value) must be small compared to
output voltage. This means maximum supplies and signal level
should be used. Now enter increasing values of load resistance
until the TOO HOT fag goes away. Did you get something like
7.35 ohms, 132W RMS and 263W peak?
This time I have looked up the specs on a high quality
woofer: 8 ohms nominal impedance, 5.9 ohms resistive,
0.93mH inductance, 40Hz to 4KHz usable frequency range.
The amplifer is too hot at maximum supply and signal levels,
so bring them both down. How does 122W RMS at 40Hz but
only 30W at 4KHz sound?
One last item: The circuit will use -5V and +95V, resistive
load at DC. You tell me the rest of the story.
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11.0 CONCLUSION
The Apex Precision Power Power Design Tool automates
examination of sine wave power levels of both the load and
the power amplifer. Gone is the need to remember or look
up multiple formulas or even decide which ones to use. With
almost instant plotting of load lines with plenty of resolution, the
tendency to scrimp on this part of power design is eliminated.
With frequency sweep capability, sweet points or hot spots of
complex loads can be quickly located. Whi l e ai med
at and containing a database of power amplifers from Apex
Precision Power, this tool is usable for just about any power
amplifer application. It is available free of charge at www.
Cirrus.com.
Please remember that answers to perfect calculations are
only as accurate as the input data and assumptions they are
based on. Do not let the bad news of poor assumptions ruin
your day. Here are some things to consider: How good is the
power supply regulation? Does load impedance change with
temperature, current, voltage or mechanical loading? How
well were all the parasitic values nailed down? What is the
phase margin of the circuit? What is the reduction in airfow
due to backpressure?
There is still no excuse to skip measurement of operating
temperatures on your equipment under worst case operating
conditions. With Power Design, these measurements are more
likely to say Job well done! than Oops.
PS. About 303W (SOA graph will be fne when case temp
is set to 77.5C).
Other Application Notes in this Power Design Tool series
are: Application Note 38: Loop Stability With Reactive Loads
Application Note 39: Filters & Power Dissipation for PWMs
IMPORTANT NOTICE
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with Reactive Loads
INTRODUCTION
One defnition of an oscillator: A circuit with gain and a total
phase shift of 360. Usually 180 comes from the ideal amplifer
being inverting. The remaining shift comes from feedback ele-
ments and the non-ideal portion of the amplifer.
A second defnition of an oscillator: A circuit the power ampli-
fer designer has nightmares about.
If you are looking for a l o n g and b o r i n g Application Note
with lots of formulas you no longer remember how to deal with,
this is not the document for you. This article works in conjunc-
tion with the Apex Precision Power Power Design CAD tool to
remember and apply correctly all the rules and formulas, thus
allowing concentration on the big picture. As a toddler, you prob-
ably had toys that gave you the feel that square pegs do not
ft in round holes. The objective here is to give you a feel for
what curve to bend in which direction allowing you to slay the
evil dragon of power amplifers, the oscillator.
WHY THE DRAGON APPEARS
By far and away, the most common cause of oscillation is lack
of adequate supply bypassing! This is often true even of circuits
having hundreds or even thousands of microfarads of bypass.
It is all too easy to forget details such as:
1. The amplifer has gain into the MHz range even when used
at DC.
2. In the MHz range, some capacitors have signifcant inductive
reactance.
3. Even a straight piece of wire has inductance.
4. Resistance of PC traces and even wire makes a difference
in power circuits.
Bypassing supplies for a power amplifer is such a broadband
job that it often requires multiple sets of components and demands
proper placement of each set. For the high frequency spectrum
(this includes the frequency where the amplifer runs out of gain)
the use of small value ceramic capacitors placed right at the pins
of the amplifer is required. In the range of the signal frequency,
capacitors will be larger in value and physical size so they will
be further from the supply pins of the amplifer. Relying on the
output capacitors of the power supply may be acceptable, but
not if they are multiple feet from the amplifer.
The second most common cause of oscillation is the elusive
ground loop. Refer to Figure 1 for an over-simplifed picture of
the problem. Load currents fowing through the parasitic imped-
ances in the line back to the supply, develop voltages which are
inserted as positive feedback. To break the loop, designate
one physical point as the center of a star ground. Make sure
every connection to ground has its own path to the center of
the star. Do not forget the low side of the bypass capacitors.
The best news about this problem is that the frequency of
oscillation usually points to the cause by being right at the
unity gain frequency of the amplifer.
The least common cause of oscillation is related to design
of the output stage of the amplifer itself and also raises a
fag to identify itself. If the oscillation is above the unity gain
frequency of the overall amplifer (below 0db on the bode plot),
we have a local feedback problem in the output stage. First,
check supply bypass. Then try a snubber network (series R-C
connected from the output to ground) in the range of 1 to 10
ohms and 0.1 to 1uF.
What about exceeding the capacitive load specifcation that
appears on most op amp data sheets? This refers to Cload
with the amplifer connected in a unity gain confguration. We
will examine means to circumvent this limitation.
THE GROUND RULES DEFINING THE PLAYING FIELD
With the above out of the way, we can attack the real sub-
ject of this article-taming oscillations caused by the non-ideal
characteristics of the amplifer and feedback elements. A few
more defnitions are in order:
Closed loop response is the relationship between the input
and output signals of the total amplifer (including feedback). We
will be looking at both the gain and the phase of this response.
Open loop response is the relationship between the input and
output signals of the amplifer without feedback. This response
does not go away when we close the loop. It is still the input to
output pin relationship and it does affect closed loop response.
Loop gain is the difference between the open and closed
loop gains. This is the magic of op amps allowing overall cir-
cuit function to be primarily a function of feedback elements.
It allows an op amp to be a general purpose building block.
More loop gain means the circuit will be more faithful to the
ideal closed loop response.
Beta is the fraction of the output signal fed back to the nega-
tive input of the op amp. We refer more often to the reciprocal
which is closely related to inverting signal gain. It is impera-
tive to note that stability analysis is treated as a non-inverting
circuit, just as when calculating the effects of voltage offset
on the output signal. This means gain, or 1/beta can never go
below one or 0db.
Intersection rate is the slope difference between the open
and closed loop roll-off at the point where they cross.
Closure frequency is the frequency where open loop gain is
0db. Above this frequency the circuit can not meet the defni-
tion of an oscillator.
Phase margin is the difference between the 360of the
oscillator defnition and the phase shift of the total circuit at
closure frequency. In practical circuits, it is recommended that
all frequencies below closure be examined as well. Note also
that by using negative feedback to close the loop we have the
frst 180 of phase shift needed to oscillate simply from the
inverting function of the op amp. The phase plots you will see
do not refect the inversion, only the change over frequency.
This further means that on all the phase plots to follow, phase
Vi
Ri Rf
'STAR'
GROUND
POINT
Rr
'GROUND'
Ri Rf
RL
Rr Rr
IL
Vi
FIGURE 1. GROUND LOOPS AND THEIR SOLUTIONS SIMPLIFIED
Loop Stability With Reactive Loads
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margin will be the difference between the curve and 180.
Phase margin is the buffer zone between the power amplifer
and the power oscillator. 45 is desirable, more is better, never
accept less than 30.
Straight line approximation is the technique used to plot most
of the response curves to follow. While real performance would
be represented by smooth curves, the straight segments make
it much easier to pinpoint corner frequencies. The penalty in
terms of phase accuracy is +/-6.
SNAP SHOT OF A CLASSIC AMPLIFIER POWER
DESIGN MECHANICS
The data entry screen of the Cload sheet is shown in Figure
2. Yellow cells are for data entry and their labels correspond to
component labels of the schematic. Entering actual, extremely
high or zero values can model the most common stabilization
techniques. Comment cells will instruct you how to enter data
for your own operational amplifer, but Apex Precision Power
hopes you will use the pull down to select one of theirs from
the built-in data base. The frst thing Power Design should
be able to do is duplicate the small signal response (or bode
plot) and the open loop phase response of the given amplifer.
For amplifer models featuring external compensation,
Power Design uses a three digit suffix to specify compensation
capacitor values detailed on the product data sheet. The Rcl
entry allows entry of the current limit setting used with most
power amplifers. Enter the remaining circuit values according
to your application. Setting up the PA85 (compensated for unity
gain) as a unity gain buffer (Rin=very high, Rf=very low) will
produce the graphs shown in Figure 3. Open loop response
should duplicate what is shown in the data sheet, or measured
values of your own amplifer.
Notice the frst smooth curves in the Phase Shift Graph.
The right most curve plots the closed loop phase shift of the
complete circuit. For example, phase shift at 40KHz is about
7. For those times when phase shift at lower frequencies is
of interest, factors of 10, 100 and 1000 scale the other three
curves. Phase shift at 400Hz would be about 0.007.
In the upper right corner of Figure 2, are some answers
that illustrate what this whole exercise is about. The most
important answer is phase margin where we like to see 45.
Closure (intersection) rate is a key indicator of health, where
20 is the desired number. The number is usually a multiple of
20 but as you see here, when the intersection and a corner
frequency are nearly coincident, it may
fall in between. The suggested maximum
bandwidth is the frequency where loop
gain is down to 20db. This is very much
a judgement call and will be application
dependent. Remember the basic op amp
theory where various internal errors
are reduced by the loop gain when the
circuit is closed. For example, open
loop output impedance (affecting gain
accuracy) of 10 ohms would be a killer
with a 1A output. If the circuit has 40db
of loop gain, this error drops from 10V to
0.1V. Demanding this 40db would reduce
the suggested maximum bandwidth by
a decade.
The unity gain stable op amp will have
its frst pole at a low frequency and the
second pole will not appear until open
loop gain has crossed 0db. The horizon-
tal line at 0db indicates closed loop unity
gain operation. Notice that pole 1 of the open loop response is
at roughly 25Hz, that phase started moving a decade before
this and within 2 decades has moved 90*. We fnd the second
pole at about 7MHz and again phase starts moving a decade
before. While the third pole does not show on the bode plot, a
corner in the phase plot around 7MHz tells us pole 3 is near
70MHz. The main point of interest for stability concerns is at
Fcl where intersection rate is 20db per decade and open loop
phase is about 135. This means the phase margin is about 45.
The R-C Pole Calculator is a convenience item having no effect
on any of the results. However, it does make it easy to translate
Intersection Rate
=20dB/decade
Slope=0
Slope=20dB/decade
Slope=40dB/decade
Open Loop
Phase Change
Fcl
Phase margin
Closed loop
Phase shift,
CL
CL*10
CL*100
CL*1000
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Closed Loop Gain
Phase Shift
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due to Pole 1
BODE PLOT
Frequency, Hz
Pole 1
Pole 2
1.E+08 1.E+07 1.E+06 1.E+05 1.E+04 1.E+03 1.E+02 1.E+01 1.E+00
1.E+08 1.E+07 1.E+06 1.E+05 1.E+04 1.E+03 1.E+02 1.E+01 1.E+00
100
120
80
60
40
20
0
-20
-45
0
-90
-130
-180
Frequency, Hz
FIGURE 3. UNITY GAIN STABLE AMPLIFIER CURVES
FIGURE 2. DATA ENTRY FOR CLOAD ANALYSIS
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graphic data to component values. Below this are listed many
of the operating points of the circuit. As experience is gained
using this tool, you will start using some of these numbers
directly to eliminate paging down to the graphs.
In contrast, Figure 4 shows the same amplifer compensated
for a gain of 100, but still confgured for unity gain. Pole 1 has
moved up in frequency giving us a greater gain-bandwidth
product, but notice that pole 2 is now well above 0db and the
intersection rate is 40db per decade. Our phase margin has
disappeared. This example is a little radical, but it does show
the dangers of improper compensation. There are also some
op amps having a minimum gain specifcation which would ft
this same general picture if used below the minimum gain spec.
In the following examples, we will frst attempt to obtain an
intersection rate of 20db per decade (a very good sign but not
a guarantee) by visualizing line segments and then checking
out the actual phase graph.

LARGE CAPACITIVE LOADS CAUSE PROBLEMS
Open loop output impedance of an amplifer forms a pole
with a capacitive load, which is modeled as an additional pole
in the small signal response as shown in Figure 5. This is our
same amplifer (compensation recommended for gain=20),
attempting to drive a heavy Cload with an inverting gain of 19.
Note that this pole introduced with the addition of an external
component is causing the same 90 shift of phase; 45 taking
place below the pole frequency and the other half above. Any
time the combination of Zout (sum of the amplifer output imped-
ance and any other resistance inside the loop) and Cload is
large enough to place this pole below closure frequency. The
intersection rate will no longer be 20db per decade and stability
will be in question.
It is now time to start the process of visualizing potential
solutions. We know good intersection rate is a key. Sometimes
we can change amplifer compensation to move the open loop
response, but usually not enough to cure this problem. One
thing we might do is increase the closed loop gain to 66db.
Entering Rin=.1 results in the data shown in Figure 6 (next
page) where the stability problem now looks fne with a phase
margin of ~45. There are several problems associated with
this solution. The most obvious is that we have changed the
closed loop transfer function which now requires other system
changes to compensate. Next, DC errors due to voltage offset
and drift are up by a factor of 100! Also notice that if we demand
the recommended 20db of loop gain, circuit bandwidth is only
~2.7KHz, about a factor of 30 reduction. This solution is rarely
acceptable.
USING AN ISOLATION RESISTOR
Go back to Figure 5 and imagine we have the power to grab
the segment modeling the effect of our Cload, just above the
intersection point (about 200KHz & 30db) and bend it back to
a minus 20db/decade slope. This would result in a new inter-
STABILITY FOR CAPACITIVE LOADS
MODEL PA85-100 Note/PBs Rn 999999999 Kohms Estimated Closure Frequency = 273.842 KHz
Rcl 3 Ohms Cn 0 nF Suggested maximum bandwidth 86.59643 KHz
Cload 0.1 uF Cf 0 pF Estimated Closure Rate = 40.0 db/decade
Rin 10 Kohms Riso 0 Ohms Estimated Phase Margin = 1.801972 Degrees
Rf 190 Kohms
Notes:
R-C Pole Calculator:
45 Kohms 2.5 Kohms 25 KHz
100 KHz 0.002 nF 0.1 uF
0.03537 nF 31830.989 KHz 63.66197724 Ohms
Total Rout 53 Ohms
1/Beta (DC) 26.0 db
Noise Gain 0.0 db
Pole Cf/Rf 837657595 KHz
Zero Rf/Cf 1.675E+10 KHz
-180
-135
-90
-45
0
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Shift due to
Pole 1
Shift due
to Cload
Phase Shift
Frequency, Hz
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-20
0
20
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60
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100
120
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
New slope
caused by
Cload
BODE PLOT
Frequency, Hz
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FIGURE 5. MODELING A LARGE CAPACITIVE LOAD
No Phase Margin
Frequency, Hz
Phase Shift
-180
-135
-90
-45
0
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
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Intersection
rate=40dB/decade
Pole 2
BODE PLOT
Frequency, Hz
-20
0
20
40
60
80
100
120
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
G
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FIGURE 4. ATTEMPTING TO USE AN AMPLIFIER BELOW
SPECIFIED MINIMUM GAIN
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0
20
40
60
80
100
120
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
-180
-135
-90
-45
0
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
20dB/decade
Phase
margin
FIGURE 6. INCREASED GAIN YIELDS ACCEPTABLE
PHASE MARGIN
BODE PLOT
Phase Shift
Frequency, Hz
Frequency, Hz
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section rate of 20db/decade. This is exactly what an isolation
resistor does for us! The R-C Pole calculator is pre-loaded
with the Cload value and prescribes 8 ohms when we enter
the corner frequency of 200KHz. Figure 7 shows the results
of entering 8.2 ohms as Riso.
What about larger values of Riso? They will produce stable
circuits but there are two things you need to know. Riso is outside
the feedback loop where voltage drops and phase shifts are
not corrected by loop gain. The curve labeled Signal at Cload
shows roll off of the signal at the actual load. Check Figure 8 to
see the effect of increasing Riso to 40 ohms. The load is now
rolled off at 40KHz cutting usable bandwidth to about half that
of the 8.2 ohm solution. The suggested maximum bandwidth
cell does not take this into account. Also, phase shift outside
the loop is not reported by Power Design.
Do not let these drawbacks to the isolation resistor technique
scare you off. It is the easest to visualize from the graph; gener-
ally not bothered by parasitics; works equally well for inverting
and non-inverting circuits; and it is very tolerant of variations in
Cload. This circuit remains stable even if the load capacitance
increases several orders of magnitude. This is true because
the singular value of Cload forms both a pole with the amplifer
output impedance and a zero with Riso. These tend to cancel
each other as they move up and down the frequency spectrum
together with changes in Cload. Obviously, huge values of
capacitance reduce bandwidth.
THE ROLL OFF CAPACITOR
We know a capacitor across the feedback resistor will
attenuate high frequency gain or roll off the circuit, changing
slope of the closed loop gain from zero to -20db/decade. If
we position the pole of this roll off correctly, it will cross the
open loop gain curve producing an intersection rate of 20db/
decade giving a good shot at stability. We also know that 1/beta
is the critical factor in stability analysis; it must be thought of
as non-inverting; and non-inverting gain (or 1/beta) can never
go below 0db. This means the desired segment of 1/beta will
have a -20db/decade slope, starting at 26db and stopping at
0db. Heres where the vision or feel of things comes in. Look
again at the graph of Figure 5, our problem statement. Picture
(maybe with the help of a straight edge) a line segment with a
-20db/decade slope crossing the open loop gain curve at half
the closed loop gain (13db in this case). At what frequency
will this segment cross the closed loop gain (26db)? With a
little practice, your vision will yield about 150KHz and the R-C
-20
0
20
40
60
80
100
120
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Pick Zero a
few dB>Acl
20dB/decade
-180
-135
-90
-45
0
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
~53 margin
Phase Shift
FIGURE 7. AN ISOLATION RESISTOR IS OFTEN THE BEST
STABILIZATION METHOD
Signal @C10Al
BODE PLOT
Frequency, Hz
Frequency, Hz
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-20
0
20
40
60
80
100
120
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Amplifier Output
Load Signal
FIGURE 8. THE BANDWIDTH PENALTY IMPOSED BY LARGE
ISOLATION RESISTORS
BODE PLOT
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Pole Calculator will tell you 5.6pF across the 190K ohms is
the place to be. See Figure 9 for the results.
We now have a paper circuit with ~54 phase margin, the
desired gain, acceptable DC accuracy and a recommended
bandwidth of 86KHz. The reason for the phrase paper circuit
has to do with parasitic capacitance, which can vary wildly with
quality of the physical layout. If the actual layout were to add
5pF to the feedback capacitor, we would loose almost 20 of
our phase margin. In addition to careful layout, consider using
lower values for the input and feedback resistors. Cutting the
resistors in half will double the value of Cf, making errors due
to parasitics less destructive.
Was this magic? No, just Power Design automation of Apex
Precision Power Application Note 25 on Driving Capacitive
Loads. Refer to this and Application Note 19 on Stability for
Power Operational Amplifers for theory and formulas. You will
learn that the closed loop phase shift curves we have been
looking at are the sum of effects of all the poles and zeros in
the circuit. The bottom curve of Figure 9 shows graphically
most of the individual phase shift components. Individual
phase shift relating to pole 1 is hidden under the total curve.
The only positive going curve is the result of the pole of the roll
off capacitor. Note the zero associated with Cf (-45 at 3MHz)
when 1/beta reaches 0db. Do not fall into the trap of thinking
that if a small capacitor is good, a bigger one must be better.
This capacitor will certainly roll off signal amplitude below 0db,
but it does not take 1/beta below 0db. A larger capacitor would
produce a fat high frequency 1/beta at 0db, a high intersection
rate and oscillation.
The roll off capacitor technique is very effective when closed
loop gain is 20db or more. With a slope of 20db/decade on
this segment, the frequency spacing of the pole and zero are
directly related to closed loop gain. As gain decreases the
pole and zero become closer together and cancel each other.
THE NOISE GAIN COMPENSATION NETWORK
The last technique requires two components and requires
the non-inverting input to be hard grounded. The hardware is
a series connected R-C from the summing junction to ground.
The Power Design schematic has them labeled Rn and Cn.
With this network grounded, it does not change gain of the
signal path. At high frequencies, where you would think of Cn
as appearing as a short, the noise of this circuit will increase
because it has two input resistors in parallel making the net
gain higher. The real objective, however, is to increase 1/beta
or to reduce the fraction of the output signal fed back to the
inverting input.
Please: Visualize, feel and refer to Figure 10 with a modi-
fed problem statement. The capacitive load is only 5nF this
time, but this is enough to yield a phase margin of ~8. Step
one is to imagine a new horizontal line located 20db above the
original closed loop gain. Note the frequency where the new
line crosses the open loop gain curve. Step two is dividing by
something between 3 and 10. For now, lets pick 10 and hope
your answer is somewhere in the area of 20KHz. This will be
the pole location of the noise gain network.
The 20db elevation of the new line segment is important; too
little does not help enough, too much gets to be just as bad.
Select the value of Rn such that when paralleled with Rin, the
non-inverting gain goes up by a factor of 10. An approximation
is simply Rin/10, which has already been entered in the R-C
Pole Calculator. Power Design tells us this approximation yields
20.4db. Entering the desired pole frequency of 20KHz yields
8nF. We will use 8.2nF and proceed to Figure 11 (next page).
Noise gain compensation works best when the pole formed
by output impedance and capacitive load is not more than 20db
above the closed loop gain.
-180
-135
-90
-45
0
45
90
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
-20
0
20
40
60
80
100
120
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Cf Pole
~1/2Acl
Op Amp Pole 1
Cl/Zout pole
Op Amp
Pole 2
Zero at
0dB
~54 margin
Open
Loop
Total
FIGURE 9. A CORRECTLY SIZED ROLL OFF CAPACITOR
ACHIEVES STABILITY
BODE PLOT
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Frequency, Hz
Frequency, Hz
-20
0
20
40
60
80
100
120
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
FIGURE 10. A NEW PROBLEM TO CONQUER
BODE PLOT
Frequency, Hz
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MODEL PA85-100 Note/PBs Rn 9999999999 Kohms
Rcl 3 Ohms Cn 0 nF
Rf 190 Kohms
Notes:
R-C Pole Calculator:
1 Kohms 2.5 Kohms 25 KHz
20 KHz 0.002 nF 0.005 uF
7.95775 nF 31830.989 KHz 1273.239545 Ohms
AN38
832 AN38U
A COMBO DEAL IS NOT ALWAYS FAST FOOD
We found that a minimum closed loop gain of 20db is desir-
able for the roll off capacitor to do a good job. Also, for the noise
gain compensation to produce good results, we want no more
than 20db between closed loop gain and the pole produced
by output impedance and the load capacitor. There are a fair
number of applications requiring a signal gain of -1, which is
a 1/beta of only 6db. See Figure 12 as our next problem state-
ment. This circuit is an ideal candidate for a combination of
both roll off capacitor and noise gain techniques.
As a frst step, select Rn for a 20db increase of 1/beta or
non-inverting gain (5K was used in this example). For a trial,
enter 1000nF for Cn and refer to Figure 13 showing our new
1/beta. Divide the frequency where 1/beta crosses open loop
gain (~250KH) by 2 and set the Cf pole accordingly. Set the
noise gain pole two decades lower yet. The R-C Pole Calculator
makes it easy to select 12pF for Cf and 27nF for Cn. Figure
14 shows the results.
COMPARING THE METHODS
Your Daddy probably avoided using the isolation resistor
technique because of the dreaded voltage drop outside the
loop. But being of the enlightened age, you will look at the roll
off error shown in Figure 15 and realize this error applies to
any feedback capacitor inside the loop as well! This means
that when pole frequencies are equal, gain errors introduced by
either an isolation resistor or a feedback capacitor are identical.
We also need to look at the phase shift issue. The lower
graph of Figure 15 shows the phase shift occurring outside
the loop; an error to be added to the closed loop phase shift
to fnd total phase shift applied to the actual load. Comparing
-20
0
20
40
60
80
100
120
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
1/2 to 1 Decade
20dB!
-180
-135
-90
-45
0
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
~44 margin
Phase Shift
FIGURE 11. THE NOISE GAIN COMPENSATION NETWORK
DOING ITS THING
BODE PLOT
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Frequency, Hz
Frequency, Hz
-20
0
20
40
60
80
100
120
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
PA85-100
Rin,Rf=100K
Cload=.1F
Rcl=3 ohms
FIGURE 12. LOW GAIN AMPLIFIERS PRESENT THE BIGGEST
CHALLENGE
BODE PLOT
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Frequency, Hz
-20
0
20
40
60
80
100
120
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Find this frequency
2 for Cf pole
200 for NG pole
20dB
1/
FIGURE 13. SETTING UP THE INITIAL NOISE GAIN CURVE
BODE PLOT
b
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Frequency, Hz
0 -2
0
20
40
60
80
100
120
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
1/Beta due to
noise gain
Roll off
due to Cf,
NEVER<0dB,
causes a Zero
at 0dB
Signal amplitude, does NOT increase,
can be<0dB
-180
-135
-90
-45
0
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
~50 margin
FIGURE 14. COMBINING NOISE GAIN WITH A ROLL OFF
CAPACITOR
BODE PLOT
Phase Shift
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Frequency, Hz
Frequency, Hz
AN38
AN38U 833
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A
the closed loop phase shift of Figure 7 (the isolation resistor
solution) to that of Figure 9 (the feedback capacitor solution)
reveals much better phase performance when the isolation
resistor is used. The key to this difference is that adding the
feedback capacitor introduces both a positive and a negative
component to open loop phase shift while adding an isolation
resistor introduces only a positive component. This difference
can be seen directly in the Phase Components graphs. For
an indirect indicator, notice that open loop phase beyond the
closure frequency falls off more rapidly with the Cf solution
than with the Riso solution. Table 1 shows gain errors and
total phase shift errors for the two circuits at the suggested
maximum bandwidth and several points below. With the pole
frequency of the isolation resistor solution a little higher than
the pole of the feedback capacitor solution, both gain and
phase performance of the isolation resistor solution is superior.
865KHz 43KHz 22KHz 8.6KHz 860HZ
Cf Gain 12.8% 4% 1.1% 0.17% 0.002%
Riso Gain 8.7% 2.4% 0.62% 0.1% 0.001%
Cf Phase 40 21 11 4.3 0.43
Riso Phase 37 19 9.5 3.9 0.39
TABLE 1. TOTAL GAIN AND PHASE ERRORS FOR Cf AND
RISO SOLUTIONS
WORKING WITH COMPOSITE AMPLIFIERS
Stability headaches seem to escalate exponentially with
the number of amplifers in the loop, so most designers tend
to avoid them. However, the composite is often worth the extra
trouble when large power levels and high DC accuracy are both
required. The techniques to achieve stability with the composite
are basically the same as we already covered; stabilize the
power stage frst, then repeat the job for the total circuit.
Figure 16 is the data entry screen for the second half of this
work. The frst half is represented by the Pwr symbol (accom-
plished as above), and those numerical results become input
data for this half. The schematic is showing that the closed loop
response of the power stage is in series with the host ampli-
fer, or is being added to the open loop response of the host
amplifer. Stability analysis for the composite performs exactly
that addition and a typical result and the classic problem with
the composite is shown in Figure 17 (next page).
The OP07 host amplifer has a well behaved open loop gain
curve with its second pole near 0db gain. If the small signal
amplifer you wish to use is not included in the built-in data
base, Power Design comments tell how to enter data extracted
from a data sheet. The model of the composite open loop gain
features the poles of both the host amplifer and the closed
loop power stage response. The pole at ~21KHz (due to the
roll off capacitor in the power stage) causes an intersection rate
of 40db/decade for any closed loop gain between 25db and
45db. Lower gains would yield 60db/decade because closure
frequency in the power stage places pole just over 70KHz. It
is quite possible to see this type stability problem even when
not driving a capacitive load..
Power Design provides two techniques to stabilize the com-
posite circuit. If an isolation resistor was used, it is modeled in
the power stage only and its effects are included in the closed
loop response data fed into the composite problem statement.
You may use the roll off capaci-
tor, the noise gain network or
both as shown in Figure 18
(next page). The same basics
on component selection apply
here, but you may fnd a little
more tweaking of compo-
nent values is required. Final
values for the solution shown
are Rn=3.4K, Cn=10nF and
Cf=22pF which yield a phase
margin of 50.
0
5
10
15
20
25
30
0
.
1
0
.
2
0
.
3
0
.
6
1
.
0
1
.
8
3
.
2
5
.
6
1
0
.
0
1
7
.
8
3
1
.
6
5
6
.
2
1
0
0
.
0
x1
x10
x100
x1000
0
5
10
15
20
25
30
35
40
45
0
.
1
0
.
2
0
.
3
0
.
6
1
.
0
1
.
8
3
.
2
5
.
6
1
0
.
0
1
7
.
8
3
1
.
6
5
6
.
2
1
0
0
.
0
x1
x10
x100
FIGURE 15. R-C ROLL OFF AMPLITUDE ERROR AND
UNCORRECTED PHASE SHIFT
R-C ROLL OFF ERROR
Percent of Pole Frequency
Percent of Pole Frequency
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UNCORRECTED R-C PHASE SHIFT
Composite Circuits
MODEL OP07 READ ME Estimated Closure Frequency = 86.59643 KHz
Aol = 135 dB Pole 1 = 0.1 Hz Suggested maximum bandwidth 27.3842 KHz
Pole 2 = 7.00E+05 Hz Pole 3 = 7.00E+06 Hz Estimated Closure Rate = 60.0 dB/decade
Rin 21 Kohms Rn 99999999999 Kohms Estimated Phase Margin = -35.95021 Degrees
Notes:
R-C Pole Calculator :
3.4 Kohms 47 Kohms
5 KHz 10 nF
9.36206 nF 0.338627538 KHz
1/Beta (DC) 24.7 dB
Noise Gain 0.0 dB
Pole Cf/Rf 4681027738 KHz
Zero Rf/Cf 80469095893 KHz
R
IN
R
F
C
F
R
N
C
N
HOST
PWR
R
ISO
C
LOAD
FIGURE 16. ENTERING HOST AMPLIFIER FOR THE COMPOSITE CIRCUIT
AN38
834 AN38U
DOES INDUCTANCE ALWAYS BRING STABILITY
PROBLEMS?
The answer is no. You can drive inductance all day long in
the voltage mode without waking the dragon. The problem is
current mode drive where inductive V-to-I phase shift is inside
the loop, courtesy of the current sense element. Figure 19
illustrates a combination of typical topologies on the data entry
screen. We will address the numbered boxes later.
The most simple real topology is realized by applying the
input signal to the non-inverting input and not using Rin. The
power op amp drives the load in phase with the input signal
to whatever amplitude is required to obtain voltage across Rs
equal to the input signal. Adding Rin (grounded) to the circuit
causes the voltage across Rs to be
greater than the input signal.
To achieve an inverting circuit,
ground the non-inverting pin and
apply the signal to Rin. The op amp
will drive the load out of phase at an
amplitude large enough to develop a
voltage on Rs equal to Rf/Rin. This
inverting setup has dual advantages
over the non-inverting circuit. Voltage
on the sense resistor can be larger
or smaller than the input signal, plus
there is no common mode voltage
on the amplifer.
Notice that in both circuits the load
impedance is inside the feedback
loop, meaning closed loop gain is
partially a function of load imped-
ance. This is exactly what we want
for current control; load impedance
goes up; gain goes up; output voltage goes up; and current
remains constant. Refer to Figure 20 (next page) for a picture
of the problem with the gain goes up. Open loop gain is falling
at 20db/deacade and closed loop gain is rising at 20db/decade
to produce an intersection rate of 40db/decade; an event of
which weve grown suspicious.
When it comes to adding all the phase shift elements to fnd
open loop phase shift (and phase margin), notice that the frst
pole in the open loop response of the op amp is nearly coincident
with a zero in the closed loop. This causes open loop phase to
drop like a rock to 180 (zero phase margin) at 100Hz. The key
to stabilizing this circuit will be to lower the frequency of the
-180
-135
-90
0
45
90
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Frequency, Hz
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Bode Plot
-20
0
20
40
60
80
100
120
140
160
1.E+00 1.E+01 1.E+02 1.E+03 1.E+05 1.E+06 1.E+07 1.E+08
Frequency, Hz
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Host
Noise
gain Zero
Host Noise
gain Pole
Host Cf
Pole
PWR Fcl
Pole
PWR Cf
Pole
~50 margin
FIGURE 18. THE FINISHED COMPOSITE AMPLIFIER
1
2
3
4
FIGURE 19. STEPS TO STABILITY FOR CURRENT CONTROL WITH INDUCTIVE LOADS
Bode Plot
-20
0
20
40
60
80
100
120
140
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Frequency, Hz
G
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Bode Plot
-20
0
20
40
60
80
100
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Frequency, Hz
First half of the job: The power stage,
PA241-150, Rcl-15, Cload=0.1,
Rin=34K, Rf=340K, Cf=22pF
Signal gain
Aol of
Host only
Power stage signal
gain + Host Aol =
composite Aol
Pole from power
stage Cf
Pole from power
stage Fcl
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FIGURE 17. A POWER STAGE RESPONSE INCORPORATED
INTO A COMPOSITE AMPLIFIER
AN38
AN38U 835
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A
closed loop pole (currently at the intersection point) by using
a second feedback path consisting of Cf and Rd.
This R-C network will introduce a second feedback path
doing practically nothing at low frequencies but providing
dominant voltage feedback at higher frequencies, without the
additional V-to-I phase shift of the inductor. Figure 21 shows a
typical solution where the fat portion of this feedback path is
usually positioned at least 20db above DC gain or 20db below
the intersection of open loop gain and the inductive feedback
path. If there is a confict between these to goals, start with
the higher db level. The corner frequency of the R-C network
is usually about 3/4 of a decade below the intersection of the
two feedback paths.
The circuit function of our example is an inverting amplifer with
an input signal of 10V and a transfer function of 0.167A/V. At
peak currents of 1.67A, power dissipation in the sense resistor
seemed acceptable and values of Rin and Rf were convenient.
Please note that these same component values could model a
non-inverting amplifer with a transfer function of 1A/V.
Refer to Figure 19 again to see that Power Design calculates
two values for Rd and then a value for Cf. To use these features:
1. Enter large values for both Cf and Rd.
2. Enter the larger recommendation for Rd.
3. If phase margin is well over 45, raise Rd, if less, lower Rd.
4. When satisfed with phase margin, enter recommendation
for Cf.
In this example, values of 82K ohms and 120nF were used.
As transfer functions and Q ratings of inductors change, the
curves Power Design draws for you will vary a lot. As in this
example, some will fall into place with suggested values; some
will require playing with the value of Rd; and a few may require
no network at all. When viewed as a single issue, stability for
these amplifers is simple. However, you will often fnd yourself
fghting for bandwidth. The good news is that re-running the
stability analysis for a dozen sets of gain and sense resistors
is an easy task. As a general rule, large sense resistors and
low gain settings will maximize bandwidth.
THEORY IS GREAT--------BUT
We have mentioned parasitics and layout concerns a couple
of times. Please pull from your memory the old phrase, too
broad a subject to cover..... True, so we will get right to Figure
22 (next page) and say the job is positively not fnished until the
hardware is tested. Use all components as close to production
version as possible; power supplies, cable harnesses, signal
sources, loads and any thing else you can think of.
Watch the 1KHz output signal for over/under shoot while
setting the very low frequency signal to exercise the amplifer
output (plus the supplies, cables and the load) over the entire
-20
0
20
40
60
80
100
120
140
1.E-01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
-180
-135
-90
-45
0
45
1.E-01 1 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
1.E-01 01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
-180
-135
-45
0
45
90
1.E+00 1.E+01
1/2 to 1 decade
~20dB
1.E+00 1.E+0
1.E+00 1.E+
~45 margin
Open loop
FIGURE 21. FINDING A STABILITY SOLUTION
Op amp pole 1
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~20dB
Vout
Iout
Phase Shift
BODE PLOT
Frequency, Hz
Frequency, Hz
Frequency, Hz
G
a
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b
-20
0
20
40
60
80
100
120
140
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
-180
-135
-9 0
-4 5
0
45
90
Increasing closed loop gain with inductance
40dB/decade
intersection
rate
Closed loop
Zero
Closed loop
Pole
No Phase
Margin
Op Amp
Pole 1
FIGURE 20. GAIN AND PHASE PROBLEMS CAUSED BY
INDUCTANCE IN THE FEEDBACK LOOP
Frequency, Hz
Frequency, Hz
b
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BODE PLOT
AN38
836 AN38U
dynamic range. Then estimate phase margin of the system
using the graph. A little time spent here now may keep you off
the production line in six months.
CONCLUSION
The next time you happen to be involved in a nightlong
argument about whether stability is a science or a black art,
just smile. You wont have to say anything, just keep smiling. It
would be good though, if you have your laptop along loaded
with Power Design. When you think the smiling is about to get
you smacked, tell the crowd both arguments are correct; arith-
metic is the science portion, but expecting anyone to remember
all the rules and formulas is the black art. With almost instant
calculations and graphic data presentation, arithmetic is a
snap and a lot of the rules can remain hidden. Power Designs
built-in documentation presents the most important procedures
and rules at the command of your mouse. The entire process
becomes so easy, tasks like checking worst case component
tolerances become bearable.
Youll be the hit of the party.
FIGURE 22. TESTING THE ENTIRE SYSTEM
HARDWARE FOR PHASE MARGIN
Open Loop Phase Margin
& Damping Factor
SQUARE WAVE TEST
0 1 2 3 4 5 6 7 8 9 10
n
t
*
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
VO
Relative
Output
to a
Step
Function
Input
13 0.2*
35 0.4*
40 0.6*
52 0.8*
64 1.0*
77 1.2*
90 1.4*
RI
RF
CF
Vout
Vin
LOAD
2Vpp
1kHZ
0.1HZ
+Vs
-Vs
SQUARE WAVE TEST
AN39
AN39U 837
G
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B
A
G
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A
AN39 Filters and Power
Dissipation for PWMs
itself. The A-B waveform represents this differential connection
of the load, and the fltered voltage of this waveform equals
zero. To examine the 95% duty cycle waveforms, lets assume
a supply voltage of 100V. The fltered A value will be 95V, B
will be 5V, and the load will see 90V; the same as the fltered
value of the A-B waveform.
Note that if S1 and S3 were to turn on simultaneously,
there is nothing to limit current. Self-destruction would be
only microseconds away. The fact that these transistors turn
on faster than they turn off, means a dead time needs to
be programmed into the controller if doing your own design.
When you buy the amplifer from Apex Precision Power, this
is all inside the package.
Changing duty cycle through 50% is a continuous function,
meaning there is no inherent discontinuity as exists in sign
magnitude modulation. This is analogous to the much improved
distortion levels of class AB linear stages versus class C linear
stages where zero current crossing brings a discontinuity or
dead spot usually referred to as crossover distortion.
National created their FAST and DAMN FAST buffers,
but they cant hold a candle to these guys. In fact, thats the
problem with switchers- -they move voltages and currents
around so fast its difficult to keep the noise down. From the
linear or analog world we borrow the equation relating slew
rate to power bandwidth. If your PWM amplifer switches 50V
in 25ns, the slew rate is 2000V/us. With a peak voltage of
50V, this equates to over 6MHz. With 5 or 10 amps fowing,
those transitions contain RF energy similar to a moderate
radio transmitter. Spending a few minutes thinking like an RF
designer may be worthwhile.
Refer to Figure 3 (next page) for a pictorial of the flters
job. The relatively fat portion of the curve is the pass band
of the flter. The signal frequency of the power drive to the
load must ft under this area. Desired attenuation in this area
is 0db and the corner frequency is Fc, the cutoff frequency.
We then go down the flter slope to the switching frequency,
Fsw. Allowing one decade between these two frequencies is
a good starting point. In this case, the graph tells us the worst
case peak ripple voltage at the switching frequency will be a
little under 1% of the supply voltage.
INTRODUCTION
Those of us who have ventured into high power linear circuits
with their massive and sometimes liquid cooled heatsinks have
a tendency to go ga-ga over the efficiency potentials of the Pulse
Width Modulation (PWM) amplifers. This is OK. But these little
switching miracles do bring a new set of challenges to the table.
The PWM amplifer with no fltering is NOT capable of ampli-
tude modulation. It can only change times and maybe polarity.
We get lucky once in a while and get a load which will do the
fltering for us. Much more often we must design the flter, a job
many of us do not place at the top of our list of most cherished
activities. In addition to this, the methods required to calculate
internal power dissipation and the heatsink size are quite dif-
ferent than those used in the linear world.
The Power Design CAD tool automates Butterworth flter
equations found in Apex Precision Power Applications Note 32
and expands on this base by graphing response with real world
components. It then goes on to automate internal power dissipa-
tion equations, plus draw a wide variety of graphs on amplifer
performance over frequency. As the overall process is usually
iterative, the beneft of computer analysis is indispensable.
SOME PWM BASICS
PWM circuits achieve high efficiency compared to their
linear counterparts in much the same manner as switching
power supplies do versus linear supplies. If the control block is
optimized for producing a wide output range rather than a fxed
output level, the power supply becomes an amplifer. Figure 1
illustrates a typical PWM amplifer output stage employing four
switches confgured as an H-bridge providing bipolar output from
a single supply. This does mandate that both load terminals are
driven and zero drive results in 50% of supply voltage on both
load terminals.
The H-bridge switches work in pairs to reverse polarity of the
drive, even though only one polarity supply is used. Figure 2
shows waveforms of locked anti-phase modulation where S1
and S4 are on during one portion of each cycle, and S2 and S3
are on during the remainder of the cycle.
To help understand the conversion of the time modulated
data to analog levels, visualize each waveform segment of
Figure 2 run through a low pass flter whose cutoff frequency
is at least 10 times lower than the switching frequency. The A
and B voltages of the 50% duty cycle waveforms will both be
equal to 50% of the supply voltage. With both terminals of the
load connected to the same voltage, the load sees 0V across
S1
S3
+Vs
S2
S4
+Vs
Load
S1
S3
+Vs
S2
S4
+Vs
Load
FIGURE 1. H-BRIDGE OUTPUTS WITH DIFFERENTIAL AND
SINGLE-ENDED FILTERING
95% Duty Cycle
or
+90% Output
50% Duty Cycle
or
0 Output
5% Duty Cycle
or
90% Output
A
B
A-B
Vs
0
Vs
0
+Vs
Vs
FIGURE 2. H-BRIDGE WAVEFORMS
Filters and Power Dissipation for PWMs
MAY 2009
APEX AN39UREVB
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reduced all the way to zero if we push modulation all the way
to steady state.
The need to squeeze the last ounce of bandwidth from our
designs, along with the physics limitations on switching frequen-
cies, makes it desirable to minimize the distance between signal
and switching frequency. Pure theory says adding more poles can
increase flter slope. This is true to a point. We would probably
question an eight-pole flter in the small signal world. Do you
really need that? Can you fnd high enough quality components
to make it work? Can you afford it in terms of size and cost?
In the PWM world these questions are not only valid but are
many orders of magnitude more important because power levels
have gone from mW to KW! Rule of thumb: Allow at least a
decade between switching and signal frequencies.
THE POWER DESIGN APPROACH TO SUCCESSFUL PWM
AMPLIFICATION
The usual process is:
1. Select an amplifer model (possibly with the Part Selector
sheet).
2. Load circuit data into the PWM Filters sheet.
3. Auto load components into the Filter/load model and sweep
the frequency.
4. Tune components and parasitics plus check load variations
and fault conditions.
5. Set sweep frequency band from Fmax to at least 10 times
Fsw to check high frequency attenuation.
6. Use the graphs to select the heatsink.
The Power Design, PWM Filters sheet data entry screen for
step 2 is shown in Figure 5. The pull down Model cell reads the
built-in database containing specifcations on supply voltage,
maximum switching frequency, current levels, and internal
resistance. Alternatively, comments in the database area provide
instructions to enter data for your own design.
Switching frequency, Fsw, is required because some models
are programmable, most can be run lower than the maximum
and many can be driven with digital signals. Immediately to
the right of this data entry cell is the maximum for the model
selected. Enter minimum
frequency to be amplifed
as Fmin. Use .001 for DC.
Consider using .001 even if
the application is a substan-
tially higher fxed frequency,
as this may simulate a lost
input signal condition and
some circuits will present
their lowest impedance at
DC. Enter the maximum
frequency to be amplifed in
Fmax. Fmin and Fmax set the
frequency end points of the
sweep that will be run later.
Fcutoff is the cutoff frequency
of the flter and will be the
-3db response point. The next
three cells describe three
series connected elements
forming the load. Vripple is
the maximum peak voltage
on the load at the switching
frequency, your way to specify
the attenuation of the flter at
Figure 4 (next page) illustrates how a zero output voltage
corresponds to a 50% duty cycle and produces maximum ripple
current. As expected, there is a linear relationship between
increased output voltage and increased duty cycle. Not quite
as obvious is the curve that indicates the ripple current is
FIGURE 5. PWM FILTER DESIGN DATA ENTRY SCREEN
0
0.2
0.4
0.6
0.8
1
0 0.5 1
Duty
Cycle
Ripple
Current
FIGURE 4. DUTY CYCLE AND RIPPLE CURRENT VARIATIONS
WITHOUT OUTPUT VOLTAGE
D
C

a
n
d

N
o
r
m
a
l
i
z
e
d
Vout as a Fraction of Vs
RIPPLE CURRENT AND DUTY CYCLE
VS. OUTPUT VOLTAGE
-80
-70
-60
-50
-40
-30
-20
-10
0
0.1 1 100 1000
Signal
Bandwidth
Fc, Cuttoff
Frequency
Fsw, Switching
Frequency
A
Decade
or more
Desired
Attenuation
FIGURE 3. PWM FREQUENCY RELATIONSHIPS
FILTER ATTENUATION
A
t
t
e
n
u
a
t
i
o
n
,

d
b
Frequency, KHz
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G
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I
F
E
D
C
B
A
G
H
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F
E
D
C
B
A
Fsw. The bottom two cells specify the magnitude and unit of
measure for the output signal.
The Order Calculation section frst converts your maximum
ripple and power supply ratings into db attenuation. Then by
examining the switching and cutoff frequencies, it calculates the
order, or number of poles needed. The integer recommendation
is rounded up. The matching
network that is calculated
will cause reactive loads to
appear resistive to the output
of the flter. Figure 6 shows
the actual flter components
for flter orders up to N=6,
plus expected ripple current
at the switching frequency.
Figure 7 shows the ideal
response graphed and an
area where attenuation at
specifc frequencies can be
checked in detail.
Ideal is a great word. Just
as we use the concept to
describe theoretical perfor-
mance of the linear op amp,
it will work equally well here.
To achieve the performance
shown in this graph, output
impedance of the amplifer
must be zero; the flter must
contain perfect components;
be terminated with the load
described; and the specifed
matching network must be in
place. If these conditions are
not true, ALL BETS ARE OFF.
A qui ck l ook at PWM
amplifer data sheets will tell
us actual output impedance
can cause small errors if left
unchecked. Use your knowl-
edge of op amp theory and
Figure 8 to see how closed
loop output impedance of the
PWM amplifer is extremely
low just as with a closed loop
op amp. On the left circuit we
know output impedance is
reduced by the loop gain. As
long as the op amp in the right
circuit has no direct DC feed-
back, and the PWM block with
its output impedance (typically
ranging from 0.1 to 1) is
inside the feedback loop,
closed loop output impedance
will be reduced in the same fashion. With PWM
amplifers being relatively slow compared to
op amps, it is easy to obtain high loop gains
over the power signal bandwidth to achieve
negligible errors in driving the flter. In actual
PWM systems, the feed back loop is often
much more complex than shown here.
Trying to approach the second ideal condi-
tion means most of the work still lies ahead
in fnding components which work as advertised in the MHz
range and whose losses wont radically change the pretty
graphs. An electrolytic capacitor may perform very well at 60Hz,
but rather poorly at 6MHz. If temperatures allow, switching to
tantalum should result in a noticeable high frequency improve-
Component Calculations Shading indicates values for Split Inductor topology
Dual Cap Filter Single-ended Filter Dual Cap Filter Single-ended Filter
N = 1 L = 0.3979 mH 0.7958 mH N = 2 L = 0.5627 mH 1.1254 mH
P-P Iripple = 2.5133 Amps out of the amplifier C = 11.254 uF 5.6269 uF
Avg. Iout for thermal calculations = 0.6283 P-P Iripple = 1.7772 Amps out of the amplifier
N = 3 L1 = 0.5968 mH 1.1937 mH
C = 21.22 uF 10.61 uF N = 4 L1 = 0.609 mH 1.2181 mH
L2 = 0.1989 mH 0.3979 mH C1 = 25.102 uF 12.551 uF
P-P Iripple = 1.6755 Amps out of the amplifier L2 = 0.4307 mH 0.8613 mH
Avg. Iout for thermal calculations = 0.4189 C2 = 6.0909 uF 3.0454 uF
N = 5 L1 = 0.6148 mH 1.2296 mH Avg. Iout for thermal calculations = 0.4105
C1 = 26.967 uF 13.484 uF
L2 = 0.5499 mH 1.0998 mH N = 6 L1 = 0.6179 mH 1.2358 mH
C2 = 14.235 uF 7.1174 uF C1 = 28 uF 14 uF
L3 = 0.1229 mH 0.2459 mH L2 = 0.6179 mH 1.2358 mH
P-P Iripple = 1.6266 Amps out of the amplifier C2 = 19.124 uF 9.562 uF
Avg. Iout for thermal calculations = 0.4067 L3 = 0.3016 mH 0.6031 mH
C3 = 4.1189 uF 2.0595 uF
FIGURE 6. COMPONENT VALUES FOR DIFFERENTIAL AND SINGLE ENDED FILTERS
FIGURE 7. THE IDEAL ATTENUATION GRAPH AND PRECISE CHECKING OF POINTS OF INTEREST
-120
-100
-80
-60
-40
-20
0
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
N
=
1
N
=
2
N
=
3
N
=
4
N
=
5
N
=
6
Attenuation in db Percent attenuation
500 -9.7E-01 -2.6E-01 -6.7E-02 -1.7E-02 -4.2E-03 -1.1E-03 5.0E+02 10.55728 2.98575 0.772212 0.194742 0.048792 0.012205
750 -1.9E+00 -1.2E+00 -7.1E-01 -4.1E-01 -2.4E-01 -1.4E-01 7.5E+02 20 12.84245 7.863584 4.658634 2.702074 1.547157
22500 -2.7E+01 -5.4E+01 -8.1E+01 -1.1E+02 -1.4E+02 -1.6E+02 2.3E+04 95.55994 99.80247 99.99122 99.99961 99.99998 100
225000 -4.7E+01 -9.4E+01 -1.4E+02 -1.9E+02 -2.4E+02 -2.8E+02 2.3E+05 99.55556 99.99802 99.99999 100 100 100
Hertz N=1 N=2 N=3 N=4 N=5 N=6 Hertz N=1 N=2 N=3 N=4 N=5 N=6
IDEAL COMPONENT ATTENUATION
G
a
i
n
,

d
b
Frequency, Hz
Z Z PWM
FIGURE 8. A PURE INTEGRATOR IS THE KEY TO ACCURACY
AN39
840 AN39U
ment. Moving to switching rated
plastic capacitors or ceramic
capacitors is usually an even
better choice.
Not many of us woul d
attempt using laminated steel
core inductors here, but please
note that not all high fre-
quency coils are created
equal. Air core inductors get
away from the magnetic satu-
ration problem and they have
fewer tendencies to become
dummy loads at high fre-
quency. The down side will be
more turns of wire and more
copper losses. When adding a
magnetic core, make sure the
material can handle the high
frequency components of the
square wave (manufacturers
often rate frequency capabil-
ity for only sine waves) at the
switching frequency and can
accommodate the fux density
of the peak currents to be
delivered.
Pressing one of the Load All
Data buttons on the PWM Filter
sheet transfers your applica-
tion to the PWM Power sheet.
Starting on the left of Figure 9
we fnd single-ended compo-
nents for up to a sixth order
flter have been entered. Next
we fnd the matching network.
On the far right you will fnd
the simple three-element load
specifed on the PWM Filters
sheet plus space to model a
more complex load. Parasitics
for the flter components have
all been zeroed.
The sweep function handles
only single ended flters, but
Figure 10 shows the area where these
component values can be translated
into values for either split-inductor or
dual-capacitor designs. While there is
absolutely no substitute for fnding real
parasitic values for flter components,
button 91 provides a default parasitic
calculator for frst pass design efforts.
Notice the cells where capacitor type
can be selected individually for all three
capacitors. Parasitics vary WILDLY from
part to part. The default calculator is
ONLY intended to get somewhere in the
ballpark. These defaults are reasonable
for parts suitable for switching applica-
tions. Your real parts could be better, but
could easily be much worse. Consult
manufactures data sheets or measure
FIGURE 9. LOADING APPLICATION DATA FROM THE FILTER SHEET TO THE POWER SHEET
FIGURE 10. TRANSLATION BETWEEN FILTER TOPOLOGIES AND DEFAULT PARASITIC CALCULATION
FIGURE 11. ATTENUATION WITHIN THE PASSBAND
A
t
t
e
n
u
a
t
i
o
n
,

d
b
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
0.001 0.01 0.1 10 1
Frequency, KHz
FILTER ATTENUATION (In Load Current If Lout)
AN39
AN39U 841
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
to the ideal except the entire
curve is about 0.3db lower than
expected. This drop is due to
inductor resistance. We learned
earlier that the extremely fast
transition times of the PWM
amplifers means high frequency
content is powerful well into
the megahertz range. To check
performance in this range; go
to the data input screen; enter
the cutoff frequency as Fmin;
and at least the tenth harmonic
of the switching frequency as
Fmax; and rerun the sweep. The
graph in Figure 12 tells us spike
content at the flter output is far
from ideal. An ideal second order
flter for this example has about
82db attenuation at 225KHz, but
parasitics reduce this fgure to
about 73db, or roughly a factor
of 3 less attenuation with elec-
trolytic capacitors in this dual-
capacitor design. Is this OK?
Or should we spend more time
looking for better flter compo-
nents? Or should we consider
one of the other two topologies
which will perform better at high
frequencies?
So, youre an old hand with
linear power circuits. You fre up
the prototype with a light load to
make sure everything is working
before connecting the real load.
While this procedure is com-
mendable for linear drives and
may work fne for a PWM drive,
watch out for tuned circuits
in the filter/match network/
load. Replacing a designed 10
ohm/1mH load with a 100 ohm
purely resistive load (matching
network removed), produces the
graphs of Figure 13. At the 2KHz cutoff frequency, impedance
presented to the amplifer drops to ~2.7 ohms, peak current
tops 30A, load voltage is ~313V and load current is 3.1A. 970W
delivered to the light 100 ohm load!
Be careful!
Deadly voltages easily generated.
The second order flter driven at the designed cutoff fre-
quency, with no load, is a series resonant circuit which presents
a theoretical zero impedance to the amplifer and develops
a theoretical infnite voltage at its center. Higher order flters
generally produce lower amplitude peaks at lower frequencies
relative to the cutoff frequency.
The very nature of PWM amplifers demands reactive ele-
ments be driven. Inductance is mandatory and capacitance
is very common, meaning resonance will exist. A properly
designed and terminated flter will yield a response close to
0
-80
-70
-60
-5
- 40
-30
-20
-10
1
0
100 1000
A
t
t
e
n
u
a
t
i
o
n
,

d
b
FIGURE 12. SMALL PARASITICS CAUSE A LARGE DEPARTURE FROM THE "IDEAL" PICTURE AT
HIGHER FREQUENCIES
10
Ideal
Parasitics
FILTER ATTENUATION(In Load Current if lout)
Frequency, KHz
With
0
0.5
1
1.5
2
2.5
3
3.5
0 0.5 1 1.5 2 2.5 3
0
5
10
15
20
25
30
35
0 0.5 1 1.5 2 2.5 3
0
50
100
150
200
250
300
350
0 0.5 1 1.5 2 2.5 3
0
1
2
3
4
5
6
7
8
9
0 0.5 1 1.5 2 2.5 3
FIGURE 13. A GOOD PROCEDURE FROM THE LINEAR WORLD MAY BE DANGEROUS IN THE PWM WORLD
LOAD CURRENT PEAK OUTPUT CURRENT INTO FILTER
IMPEDANCE LOADING THE AMPLIFIER FILTER OUTPUT VOLTAGE
Frequency, KHz
Frequency, KHz Frequency, KHz
Frequency, KHz
C
u
r
r
e
n
t
,

A
r
m
s
V
o
l
t
,

V
r
m
s
C
u
r
r
e
n
t
,

A
I
m
p
e
d
a
n
c
e
,

O
h
m
s
the parts to get accurate data for subsequent analysis. Values
of purchased components and their real parasitics should be
entered directly into the yellow cells and then be translated
with button 88, 89, or 90.
This picture is part of the result of loading our sample
application from the PWM Filter sheet (no auto sweep); going
to the Filter Component Work Area with button 92; translating
component values for a split-inductor design with button 85;
and calculating default parasitics with button 91. Button 88 will
translate prime component values and the parasitics back to
single-ended equivalents and then run the frequency sweep to
calculate critical voltages, currents, powers and phase angles
over the frequency range we specifed. 100 frequency points
will be examined. If this takes less than 10 seconds, you should
be proud of your computer. If it takes more than a minute ------.
Frequency sweep requires Analysis ToolPak. If you see cells
with #NAME? or a runtime error, try TOOLS, ADD-INS, Analysis
ToolPak and then do the sweep.
Figure 11 shows attenuation of signal frequencies is close
AN39
842 AN39U
the text book curve. The trick is to design
the circuit to accommodate load varia-
tions and possibly certain fault conditions
such that these conditions will not place
undue stress on components or produce
extreme high voltage hazards.
Figure 14 (next page) shows the well
behaved performance of this example
modifed for a 10 purely resistive load.
At DC, impedance loading the amplifer
is the sum of the load and the parasitic
0.36 ohms of the flter inductor(s). The
amplifer sees about a 3% impedance
dip at mid-band and drives a correspond-
ing peak output current. This is normal
and Power Design will search for these
peaks and dips when calculating heatsink
requirements.
While this operation is proper, is it what
you wanted? The cutoff frequency of the
flter is where the load voltage is down
3db. Does -3db equal .707 or .5? Both,
.707 applies to the voltage and the cur-
rent ratio but .5 is correct for the power ratio. In this example
output power drops form 337W at DC to 172W at 2KHz. Many
times half power at maximum frequency is not acceptable. This
is why some designers routinely start their flter calculations
using a cutoff frequency twice the required maximum signal
frequency of the application.
Doubling the design cutoff frequency of the flter enables
the circuit to deliver a lot more power at the desired 2KHz as
shown in Figure 15. This is still a 2 pole flter and power loss
is only about 6% at 2KHz. As an added beneft, inductors for
a 4KHz flter are half the value of those for a 2KHz flter and
likely will have substantially lower parasitic resistance.
Yes, you could double again to achieve an even fatter pass
band. No, there is no free lunch. Every time you move cutoff
frequency up, you allow more
switching frequency power in
the load. Yes, you can add
more poles to the flter. Ana-
lyze as many combinations
as you wish, it wont take long.
The question becomes one
of cost in terms of money,
extra loss in the flter, size
and weight.
Speaking of properly ter-
minated flters, we need to
look closely at the matching
network. While the conjugate
matching network performs
almost like magic in terms of
forcing the attenuation graph
to approach text book shape,
there is a cost involved. This
cost is slight when the load
is mostly resistive, but the
power dissipated in this
network approaches power
delivered to the load as
the load approaches pure
reactance.
325
330
335
340
345
350
2.5 2 1.5 1 0.5 0
FIGURE 15. DOUBLING Fc YIELDS INCREASED OUTPUT POWER
LOAD V-A
Frequency, KHz
V
-
A
r
m
s
0
50
100
150
200
250
0 5 10 15 20 25
-0.35
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
0
1 10 100 0
20
40
60
80
100
120
140
160
180
200
0 5 10 15 20 25
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25
FIGURE 16. PERFORMANCE OF THE PROPERLY TERMINATED FILTER
FILTER ATTENUATION(In Load Current If Lout) LOAD V-A
POWER IN RMATCH
OVERALL EFFICIENCY, AC CALCUALATIONS
Frequency, KHz
Frequency, KHz
Frequency, KHz
A
t
t
e
n
u
a
t
i
o
n
,

d
b
P
o
w
e
r
,

W
r
m
s
E
f
f
i
c
i
e
n
c
y
,

%
V
-
A
r
m
s
0
10
20
30
40
50
60
70
0 0.5 1 1.5 2 2.5
0
1
2
3
4
5
6
7
0 0.5 1 1.5 2 2.5
7
7.2
7.4
7.6
7.8
8
8.2
8.4
8.6
0 0.5 1 1.5 2 2.5
9.8
10
10.2
10.4
10.6
10.8
11
11.2
11.4
11.6
11.8
12
0 0.5 1 1.5 2 2.5
FIGURE 14. PERFORMANCE OF THE PROPERLY TERMINATED FILTER
PEAK OUTPUT CURRENT INTO FILTER LOAD CURRENT
FILTER OUTPUT VOLTAGE IMPEDANCE LOADING AMPLIFIER
Frequency, KHz
Frequency, KHz
Frequency, KHz
Frequency, KHz
C
u
r
r
e
n
t
,

A
C
u
r
r
e
n
t
,

A
r
m
s
V
o
l
t
,

V
r
m
s
I
m
p
e
d
a
n
c
e
,

O
h
m
s
AN39
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G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
0
50
100
150
200
250
300
350
400
450
500
0 5 10 15 20 25
Frequency, KHz
0
0.5
1
1.5
2
2.5
3
3.5
4
1 10 100
Frequency, KHz
FIGURE 17. THE BAD NEWS IF THE MATCHING NETWORK IS OMITTED
LOAD V-A
FILTER ATTENUATION (In Load Current If Lout)
A
t
t
e
n
u
a
t
i
o
n
,

d
b
V
-
A
r
m
s
The graphs of Figure
16 are for an application
driving a 1uF piezo
stack with 12 ohms
series resistance, to
75V peak from 1KHz
to 20KHz. The second
order flter cutoff fre-
quency was designed
for 40KHz providing
a quite fat response.
The V-A output falls at
low frequency because
the load impedance is
increasing. To keep flter ter-
mination impedance fat, the
matching network impedance
moves in the opposite direc-
tion, giving rise to large power
levels in the matching network
resistor, especially at low fre-
quencies. As this power is not
delivered to the load, efficiency
is far from the desired level.
Upon seeing this power loss,
some designers immediately
want to see what happens if
they simply remove the match-
ing network. With no matching
network we cannot lose this
power, but this leaves the flter
with an improper termination.
This would result in a unwanted
resonant circuit causing almost
4db peaking as shown in Figure
17 (next page). In terms of V-A in
the load near the upper end of
the band, power goes from ~180
to over 450V-A. If you wish to see more
on this subject, use the Filter Hazard
on the Power Design Examples sheet.
Comments explain each situation and
a macro sets up and runs the analysis.
Here lies part of the beauty of the
Power Design tool; investigating pos-
sible compromise circuits is a snap. See
Figure 18 for results of doubling the resis-
tor value in the matching network which
may provide a workable compromise.
Peaking at the load is down substantially
from not using any network and wasted
power is down substantially from using
the ideal network.
DETERMINING FILTER COMPO-
NENT STRESS LEVELS
This section uses the original coil
driver example, with the second
order fi l ter desi gned for cutoff
frequency=2KHz; load resistance=10;
and load inductance=1mH. However, we
are assuming the load has gotten hot
and the resistance has gone up to 15.
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1 10
100
0
20
40
60
80
100
120
140
160
0 5 10 15 20 25
0
50
100
150
200
250
0 5 10 15 20 25
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25
FIGURE 18. RESULTS OF A MODIFIED MATCHING NETWORK
OVERALL EFFICIENCY, AC CALCULATIONS
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Frequency, KHz
Frequency, KHz
Frequency, KHz
Frequency, KHz
POWER IN RMATCH
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FILTER ATTENUATION (In Load Current If Lout) LOAD V-A
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Max pk=
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MaxApk= 10.1092
Peak
Values
FIGURE 19. STRESS LEVELS ON L1
V
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V
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SIGNAL FREQUENCY VOLTAGE ON L1
Frequency, KHz
Frequency, KHz
L1 SIGNAL FREQUENCY CURRENT
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This change affects all the performance
graphs covered so far and they should
be checked. Power Design calculates
voltage and current stress levels on
L1 and L2, plus C1 and C2 for all
designs. Resonance of these flters
can produce voltages and currents
larger than the load levels. Button 84
will place the frst graph on the screen,
then scroll up and to the right to view
other graphs. The currents shown in
Figure 19 can be used directly for all
flter topologies. If L1 is actually two
inductors, half the voltage shown will
be across each individual inductor.
Note that our circuit example only has
a 90V supply; the drive signal is only
85Vpk; the load resistance is 15; but
L1 has current peaks of 10.1A and voltage peaks of 108V.
In Figure 20 (next page), we fnd that in addition to the
switching frequency current, C1 has 3A fowing at 1.6KHz.
Three peak voltages are given; 96Vpk for a differential capaci-
tor; a positive peak of 93V for a grounded capacitor; and a
negative peak of -3V. Any time the negative peak is below
ground, the warning to use bipolar capacitors also appears.
PHASE ANGLES AT THE LOAD
These flters are notorious for introducing large phase
shifts. This is usually not a problem when feedback is taken
directly at the output of the PWM amplifer. In applications
such a servo loops, feedback is taken after the flter
and any phase shift introduced here affects system
phase margin. Figure 21 shows both voltage and
current phase in the load for this example. This
phase shift is reduced as the ratio between Fmax
and Fcutoff frequencies widens, and is lower with
lower order flters.
CALCULATING INTERNAL POWER DISSIPA-
TION FOR PWM AMPLIFIERS
Heatsink selection for most PWM amplifers is
more complex than for a linear amplifer because
FET ON resistance (and hence voltage drop, inter-
nal power and dissipation) increases roughly 2:1
as junction temperature goes from 25C to 150C.
PWMs have the same concern over temperature
vs. life expectancy as linears, but changes of circuit
performance over temperature are much more
pronounced than with linear amplifers.
For a frst order estimation of power dissipation in the
PWM, simply multiply the output current (a given applica-
tion requirement) and the voltage drop at that current (read
from a graph on the product data sheet). This points out the
PWM advantage over linear power delivery; supply voltage
is not part of the equation. With a frst order approximation,
the voltage drop divided by supply voltage yields efficiency
(quiescent current of both Vcc and Vs will reduce this a little).
Unfortunately, frst order approximation is not good enough
unless you have the luxury of using overkill amplifers and
massive heatsinks.
Looking a little deeper, there are two points of confusion.
First, the voltage graph offers multiple curves based on various
case temperatures. We know cooler is better for life expec-
As Differential cap:
MaxVpk= 96.27327
Max as Grounded c
ap:
PosVpk= 93.13664
NegVpk= -3.136637
Use Bipolar Cap
0
10
20
30
40
50
60
70
80
0 0.5 1 1.5 2 2.5
MaxA = 2 . 993782
0
0.5
1
1.5
2
2.5
3
3.5
0 0.5 1 1.5 2 2.5
Peak
Values
Warning
Flag
FIGURE 20. STRESS LEVELS ON C1
Frequency, KHz
Frequency, KHz
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SIGNAL FREQUENCY VOLTAGE ON C1
C1 SIGNAL FREQUENCY CURRENT
-120
-100
-80
-60
-4 0
-20
0
0 0 .5 1 1 .5 2 2 .5
-160
-140
-120
-100
-8 0
-6 0
-4 0
-2 0
0 0 .5 1 1 .5 2 2 .5
FIGURE 21. VOLTAGE AND CURRENT PHASE IN THE LOAD
LOAD VOLTAGE PHASE
LOAD CURRENT PHASE
Frequency, KHz
Frequency, KHz
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tancy and efficiency, but there are no rules regarding which
one to choose. Something not presented in any direct way is
the second problem: methods to calculate junction temperature
are not given. This is a parameter every power designer should
know and it is often specifed by contract.
While the linear Power sheet simply provides you with a mini-
mum heatsink rating, the PWM Power sheet gives you graphs
of junction temperature, internal dissipation and efficiency. With
this data, you can make intelligent tradeoffs concerning circuit
operation vs. investment in the heat removal system.
Our exercises on flter design have already taken us to the
PWM Power sheet. From numerous locations you can use
command button 38 to see the Data Input screen as shown in
Figure 22. The green input cells are normally flled in with one
of the Load Data command buttons on the PWM Filter sheet.
These values may be changed at will but neither the graphs
nor circuit parameters in the blue cells will necessarily be valid
until a Frequency Sweep has been run.
In the center area, fnd data on quiescent current and result-
ing power dissipation. Data for these calculations comes from
application parameters and the built-in database containing
information on quiescent current variations with supply and
switching frequency. In the upper right, applying a sine wave
at the switching frequency and using a correction factor have
approximated ripple current. If the flter and load are close
to those entered in the Filter sheet, this ripple approximation
will be close to ripple predicted by the Filter sheet. Hotspot
frequency is the frequency where load current is producing
the highest junction temperature. This is not necessarily coin-
cident with the frequency producing the highest peak current.
Consider the case of a DC current of 10A rising to 11A peak at
1KHz. At 1KHz heat generation is alternating between pairs
of transistors fast enough to fnd them running cooler than at
a steady state level of 10A.
The Iout cell will report amplifer output current at signal
frequencies using peak values for hotspot frequencies below
60Hz or RMS values at higher frequencies. The Ifet cell is the
RMS addition of the ripple current (at the switching frequency)
and the output current. If hotspot frequency is 60Hz or more,
ripple current is reduced 30% because ripple decreases as
duty cycle increases (there is no ripple at 100%). The Minimum
Heatsink is the thermal rating which will keep both the case
temperature and the junction temperature within the boundar-
ies entered at the top of the
screen.
Continuing down on the
right side are On resistances
of the H-bridge switches
at the hotspot frequency.
The P channel number will
be for one FET if P chan-
nel devices are used in the
amplifer. If this is the case,
the N channel number will
also be for one FET. When
only N channel FETs are
used, this number will be for
two FETs. If you specify a
heatsink that will not keep
junction temperatures below
the specified maximum,
both FET resistances will
be forced to 10 ohms. Rwire
represents internal conductor
losses in the amplifer and Rtotal adds it all up. For amplifers
using IGBTs, all resistance cells will be blank.
Most PWM amplifers can hold their output switches in one
state. To rephrase, PWM amplifers can be driven to zero or
100% duty cycle; however, propagation delays and dead time
requirements limit the linear modulation range to less than
these levels. D.C.max is the maximum percentage of the power
supply voltage delivered before encountering the non-linear
jump to being latched in one state. Vpk out and Ipk out are
from anywhere between Fmin and Fmax.
Back on the left side under Actual HS, Approx. Power Out is
the power factor corrected VA output directly at the amplifer at
the hotspot frequency. If you really intend to look at DC or want
a peak value, multiply by two. Estimated Internal Pwr includes
losses due to driving the load and the quiescent power.
Efficiency of a DC power supply would compare DC, or
peak power out, to input power. Efficiency of an audio amplifer
would likely compare RMS power out to input power. These
two approaches to efficiency will produce different answers
for the same amplifer, driving the same peak current from
the same power supply. Power Design always calculates an
efficiency based on the AC thought process but will give you
a DC based answer only if both Fmin and Fmax are less than
0.003 (remember to Sweep before reading the answer). In both
cases, the numbers appearing here do not include flter loss.
Est. Vpk capability subtracts internal losses and duty cycle
limitations from the supply voltage.
Not shown in Figure 22 are four data dependent red warn-
ing fags. The frst warning appears if the Actual HS is too
small to maintain either specifed case temperature or junc-
tion temperature. If Est. Vpk capability is less than the signal
voltage, the next fag will become visible. The third fag warns
of output current beyond the peak rating of the amplifer. The
last fag concerns application supply voltage compared to
amplifer ratings.
We know many of these numbers are a moving target rela-
tive to selection of the actual heatsink rating. Refer to Figure
23 (next page) for this important step. All heatsink references
assume fresh thermal grease has been properly applied or an
Apex Precision Power thermal washer has been used.
In the upper left graph it looks like a quite small heatsink
will keep junction temperatures below the maximum of 150C
Enter, or
loaded from
PWM Filters
Sheet
Not valid until sweep has run
FIGURE 22. THE PWM POWER SHEET DATA INPUT SCREEN
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specifed by almost all PWM amplifers. However the graph
below says there is little difference between junction and case
temperature and we surely want to keep case temperature
much lower than 150C.
On the top right we see that internal power dissipation of the
amplifer changes with junction temperature. Settling for the
minimum heatsink size instead of investing in a 1C/W heatsink
(easy to do without a fan) will increase internal power almost
FIGURE 24. INCLUDING FILLER LOSSES IN THE BIG PICTURE
0 0.5 1 1.5 2 2.5
OVERALL EFFICIENCY, AC CALCULATIONS
E
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%
Frequency, KHz
96.5
96
95.5
95
94.5
94
93.5
93
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-25 0 25 50 75 100 125 150
0
5
10
15
20
25
30
-25 0 25 50 75 100 125 150
-50
-30
-10
10
30
50
70
90
110
130
150
-25 0 25 50 75 100 125 150
92.5
93
93.5
94
94.5
95
95.5
96
-25 0 25 50 75 100 125 150
FIGURE 23. SELECTING A MAXIMUM JUNCTION TEMPERATURE IS THE KEY STEP
Tj VS. HEATSINK Tj VS. INTERNAL POWER
Tj VS. EFFICIENCY
Tj VS. TCASE
T
h
e
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m
a
l

R
e
s
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a
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,

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Junction Temperature C
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T
e
m
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%
8W or nearly 40%. Below
we see this same effect
expressed in terms of
efficiency. At frst, moving
only a few percentage
points may not seem
like much, but remember
these points are relative to
a quite large power level.
Enter 100 as the Actual
HS if you plan to not use
a heatsink. More likely, a
rating will come from the
Heatsink sheet of Power
Design, a manufacturers
data sheet, or your own
design efforts.
The efficiency graphs
above refer to perfor-
mance only at the hotspot
frequency and do not
include flter losses. Figure
24 however, includes
losses in the flter and
matching network and
provides frequency data. The curve is based on the AC thought
pattern discussed earlier, input power compared to RMS power
delivered. If there is a glitch at 60Hz, it is due to the instant
change (mathematically) from peak power heating effect to
RMS power heating effect. Fig. 24. Including flter losses in
the big picture.
CONCLUSION
The Power Design tool is even more important to the
PWM designer than the linear designer. PWMs are not as
widely understood and worse yet, literature is not as widely
available. The comments and automated examples built
into this spreadsheet serve well as a text on the subject.
PWMs also tend to require more iteration to approach
an optimum design and are more frequency sensitive
than linears. Again, tackling all this with computer aided
design is the only way to go and the tasks of fltering and
heatsinking are better handled by Power Design than by
many Spice machines.
Not to harp on it, but do not let all this quick and easy
data lead you into the trap of accepting theory with a
smile while sticking your head in the sand when it comes
to the hardware world and parasitics. And one more time:
Without case temperature measurements, your design
effort is NOT complete!
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AN41 Stablility and Biasing
for PWM Amplifers
1.0 INTRODUCTION
PWM applications are complex systems with a highly non-
linear modulation/demodulation system at the heart of things.
This mandates a collection of poles and zeros plus high har-
monic and sub-harmonic content. This is further complicated by
the fact that gain of the PWM block varies with supply voltage.
These factors can make stability considerations a confusing
issue without a plan of attack, that includes test criteria and
some tools to obtain data. The successful design will arrange
all the break points in a manner to avoid oscillation while
maximizing bandwidth.
2.0 THE BASIC SYSTEM AND ITS CHALLENGES
Refer to Figure 1 showing the basic elements of a PWM ampli-
fer circuit. The integrator will drive the PWM block where ever
required to force feedback current to be equal and opposite of
the input current. We will discuss only analog implementations,
but computerized systems will function in a similar fashion. The
PWM block translates its input to time modulated pulses of full
supply amplitude. As of May 2001, all Apex Precision Power
PWM full-bridge amplifers utilize locked anti-phase modula-
tion (when one output is high, the other is always low; 50%
modulation means equal times high and low for each cycle of
switching frequency and after demodulation, 0V at the load).
For more detail, see APPLICATION NOTE 30, PWM BASICS.
The low pass power flter demodulates the PWM signal so the
load sees little of the switching frequency carrier. It is in these
modulation and demodulation stages that signal and carrier
frequencies are mixed, as well as sums and differences are
generated. The low pass signal flter has multiple input con-
nection options; however, in all options, it reduces the carrier
content that the feedback gain amplifer must deal with.
Notice that the low pass function in the feedback loop will
tend to make closed loop gain of the total system INCREASE
above its corner frequency. Or we could say the pole in the
feedback loop is going to cause the same stability problem as a
zero in the closed loop gain of the system. To better understand
the system, we will examine the various poles and zeros plus
other problem areas.
Knowing the gain of the PWM block will be critical to ana-
lyzing this system. Finding the exact gain of the PWM block,
including the effects of dead time, internal voltage loss and
reverse currents in the catch diodes would be a formidable
task. A suitable approximation is to compare full scale input
with ideal full scale output. Product data sheets will give analog
input voltages needed to generate modulation percentages.
Modulation extremes will correspond to the upper and lower
peaks of the ramp. Full scale input is then = VRAMPp-p. Full
scale output on a single pin is the voltage change from 0 to
100% modulation, which equals supply voltage. In the case
of a full bridge, we need to multiply this by two, because the
load is connected differentially, seeing two equal and opposite
drive voltages.
Gain of the PWM block = Vout p-p / Vramp p-p (1)
Where Vout p-p = Vs for half bridges and Vs * 2 for full
bridges and Vramp p-p is set by the specifc amplifer model,
generally between 2.5 and 5V p-p. A full bridge PWM with a
4V ramp, running on 40V, has a gain of 20.
As the ratio between ramp voltage and supply voltage in-
creases, the gain increases. Note that some PWM amplifers,
such as the SA50 and SA60, vary the modulation ramp voltage
as Vcc varies. It would be acceptable to think of this changing
gain as a changing gain-bandwidth product in an op amp cir-
cuit. The integrator and the PWM block are in series, so when
viewed together, the gains of the two stages are added. Just
as in linear circuits, achieving stable operation will be easier
when all gain blocks are low compared to a system having
higher gain blocks. In all cases, phase margin of the circuit will
decrease as PWM gain increases. This means stability must
be checked at maximum Vs, and minimum Vcc if appropriate.
On the other side of the coin, check bandwidth at minimum
Vs and maximum Vcc.
The job of the power flter is to attenuate the square, time
modulated carrier and deliver only (ideally) the low frequency
signal to the load. If the flter does a very good job, feedback
must be taken ahead of the flter. If the flter is designed to
have a minimum effect, feedback may be taken after the fl-
ter. In either case, the feedback signal will contain signifcant
amounts of high frequency energy.
Taking voltage feedback after the power flter can put a PWM
circuit well on the way to being a power oscillator. These flters
contain a minimum of one series inductor and often some
large capacitors on the load side of the inductor(s). If the flter
design is not proper, or the load impedance has shifted after
the flter was designed, the series L-C section(s) of the flter
can produce serious peaking at the output. Even properly
designed and terminated flters produce wild phase shift near
their cutoff frequency. The technique of taking voltage feed-
back after the power flter is usually reserved for very special
cases, the flter will be frst order (inductor only) and the load
is doing most of the fltering.
The low pass signal flter is used to attenuate the high fre-
quency content of square PWM wave forms which have very
short rise and fall times. Without this roll off, feedback gain
amplifers would need unrealistic bandwidth capability. The
down side here is that a pole in the feedback path equates to
a zero in the closed loop gain, a red fag for possible stability
concerns.
Even with this flter, op amps picked for this job should exhibit
superior high frequency common mode rejection. The non-linear
response of feedback amplifers can add extraneous signals to
the feedback. The problem comes from the fact that feeding an
op amp signals well above its bandwidth capability will often
force the input stage into non-linear operation, resulting in what
appears to be an offset error. This is compounded by the fact
Rin
FDBK Gain
Rf
PWM
Low
pass
power
filter
Load
Integrator
Low
pass
signal
filter
Iin
Ifdbk
FIGURE 1. A TYPICAL PWM SYSTEM
Stability and Biasing for PWM Amplifiers
MAY 2009
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the high frequency content (spikes) of PWM signals varies
with modulation percentage. Imagine trying to drive a sine
wave when an extra pulse is inserted every cycle between
150 and 180 and again between 330 and 360! This is a
path to distortion and in severe cases, to oscillation.
Along with R
F
, the feedback voltage provides current to
charge the integrator capacitor to the proper level. This ca-
pacitor should be the dominant frequency limiting element
of the entire system. So, just where is the pole created by
the integrator capacitor? As there is no resistor directly in
parallel with this capacitor, the traditional calculation for an
op amp roll off capacitor will not work. However, if such a
resistor were in place (rather than our complex feedback
loop), what would its value be? This fctitious value would
result in the same change of integrator output voltage for a
given change of input voltage, as occurs in the real system.
To re-phrase, if we know input current to the integrator,
and output voltage of the integrator, then Ohms law dictates
the effective feedback resistance must be VOUT/IIN. To
answer these questions we need to know the input signal,
the input resistor and how much the output of the integrator
will move in response to the input signal.
To fnd this fctitious feedback resistor, refer to Figure 2, and
assume a convenient input and use the given transfer function
to fnd the PWM output voltage. Now divide by PWM gain
(equation 1) to fnd the movement of the integrator voltage.
R
FICTITIOUS
= R
IN
* integrator / input (2)
Using this fctitious feedback resistor, the pole frequency
can be calculated just as if it were an op amp with parallel
R-C feedback. When powering the SA01 (full-bridge and 5V
p-p ramp) on 75V, gain of the PWM block is 30. If the circuit
is confgured for a gain of 10 (say, 5Vin, 50Vout) and the
input resistor is 5K, out =100, integrator =3.333, input =
10, and the fctitious resistor is 1.67K. Even though the real
RF maybe 5K, a 0.1F capacitor produces a pole at 953Hz.
If the overall system is controlling current rather than voltage,
the foregoing is still true, and we have a new concern. The load
is always inside the feedback loop for current control. Given
a constant output current, output voltage will be a function
of load impedance. This also means that load impedance
is a factor in the integrator output swing, thus affecting the
value of our fctitious feedback resistor, the pole frequency
set with the integrating capacitor, system bandwidth, and
stability. If load impedance changes only with factors other
than frequency, such as resistor element thermal variation,
the circuit can usually be checked at the two extremes and
no special measures are required.
More often the load contains signifcant inductance which
demands output voltage increase with frequency and it adds
the V-to-I phase shift of the inductor to the feedback loop. In
these cases, an additional voltage feedback path is usually
added. The objective is to have this path come into play at a
low enough frequency to avoid a stability problem, but high
enough to achieve desired bandwidth.
The most common topology for current control is to use
a differential amplifer, monitoring sense resistors in both
the lower legs of the H-bridge. This leads to non-textbook
flter design for current output circuits, especially when the
load is inductive. This current sense yields a combination of
load current, matching network current, plus flter capacitor
current. To minimize errors in the load current, the flter and
matching network need to be very light handed in the input
signal frequency band. Filters will often be frst order and
matching network impedance will be increased as high as
voltage peaking concerns will allow.
Servo loops are even more complex in that feedback is
usually taken from position or velocity sensors. In these cases,
power fltering is at an absolute minimum and additional com-
pensation networks are sometimes applied with or between
sensors, signal conditioners and the integrator.
Before proceeding, lets take notice of two items not included
in this list of problem areas: frequency domain performance
of the PWM block and the op amps used for feedback gain
and for the integrator. With the frequency relationships dis-
cussed below, it can be demonstrated how the PWM block
response is an insignifcant problem. Op amps selected to
meet the common mode rejection requirement at FSW, will
automatically have enough gain-bandwidth product to not
cause problems at the lower frequencies to be amplifed.
3.0 FREQUENCY RELATIONSHIPS
The PWM F
SW
, and required attenuation of F
SW
at the
load limit power flter the cutoff frequency, F
C.
A reasonable
starting place is to allow at least a decade between these
two frequencies. A second way to look at this is to say you
will allow at least ten segments or pulses to approximate
the waveform delivered to the load. If the load is sensitive
to high frequency components in the drive voltage, a larger
ratio between these two frequencies will help and adding
more poles to the flter will help. See APPLICATION NOTE
32 PWM LOW PASS FILTERING for additional information.
The low pass signal flter consists of one or more R-C
pairs. The corner frequency is usually a decade or more
below F
SW
. The common mode capability of op amps, Vs ,
and system bandwidth requirements all factor into the design.
If feedback is taken directly at the PWM output (by far the
most common method), this flter sees a square wave input
with peak-to-peak amplitude nearly equal to Vs. If feedback
is taken after the power flter, phase shift of the power flter
is added to the loop response. For this reason, a power flter
inside the loop will be low Q and low attenuation.
The integrator pole frequency will be a fraction of the
feedback pole(s). The higher the supply voltage, the smaller
the fraction that should be used.
4.0 THE TECHNIQUE: PLOT 1/SSETA AVOID PEAKING
While the fnal fltered output is the objective of the PWM
application, the best observation point is the integrator out-
put. This approach allows borrowing some software analysis
techniques from the op amp world. Even in the hardware
world, it is often easier to monitor the integrator output (non
switching and usually in the range of 0 to 10V) than monitor
the output (switching, often differential, and centered at half
the supply voltage).
The process of calculating the feedback factor of the inte-
Rin
Cf
Rf
Transfer
Function
f (x)
Rfict
V
V
V
FIGURE 2. REPLACING THE REAL FEEDBACK SYSTEM
WITH A FICTITIOUS RESISTOR
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A
grator is similar to that for a more traditional op amp circuit.
First, assign a value of 1V to the integrator swing, and then
calculate through all feedback paths back to the input(s). To
fnish the job, combine positive feedback (if it exists) with the
negative; invert the feedback factor to obtain 1/eta, convert
to dB, and plot the results. The objective will be to minimize
or avoid peaking in this curve to assure a stable circuit.
There is one major point we learned for op amps that we
must discard: Feedback factor is always between 0 and 1,
meaning feedback is limited from nothing to 100%. Because
the PWM circuit has a gain block between the integrator and
the feedback, it is possible to feed back more than 100% at
low frequencies! At high frequencies, the integrator capacitors
force 1/eta to 0dB, meaning there will be an increase in 1eta.
Refer to Figure 3 for examples of both peaking and non-
peaking performance. Plot A resembles an op amp circuit with
problems; low frequency 1/eta is positive, the peak spells
trouble, and 0dB is approached at high frequency. Plot B is
more what we want to see to insure stability. If bandwidth is
not a concern, no peaking is desirable. When speed is a sig-
nifcant concern, some peaking will help, but at the expense
of phase margin. For this case, peaking is defned as rise
above the low frequency value.
Plots C and D are again bad and good, except for the case
where low frequency 1/eta is negative. This will occur more
often with the higher voltage amplifers and it will be more
difficult to eliminate all peaking without a severe penalty in
bandwidth. The rise from the initial negative value to 0dB at
high frequency is not part of the peaking we are looking for. For
this case, peaking is defned as just the rise above 0dB.
Judgment criteria for PWM circuit stability will be taken
from hardware tests often used in the linear world. The
system response peaking curve as shown in Figure 4 is
the frst criteria used. This test can be applied to the 1/eta
curve mentioned earlier, to Spice simulations, or to actual
hardware. With the system running closed loop, plot the
frequency response of the integrator output. Then extract
the amount of peaking, using the above defnitions. Note
that this test is not defned over 50.
The square wave peaking test as shown in Figure 5
(next page) can be applied to either Spice simulations or to
hardware. Sum two input signals to produce a small square
wave riding on a much slower triangle (or sine). If a nominal
2Vp-p square wave displays a step peaking at 2.5V, phase
margin is about 35.
5.0 GENERAL TOPOLOGY SELECTION
10
0 5 10 15 20 25
0
20
30
50
40
FIGURE 4. CONVERTING SYSTEM RESPONSE TO
PHASE MARGIN
PEAKING, (dB)
)
S
E
E
R
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A
M
E
S
A
H
P
P
O
O
L
N
E
P
O
1/ETA
0
20
Frequency, Hz
b
d
,
n
i
a
G
A
1/ETA
0
20
Frequency, Hz
b
d
,
n
i
a
G
B
1/ETA
-20
0
20
Frequency, Hz
b
d
,
n
i
a
G
C
1/ETA
-20
0
20
Frequency, Hz
b
d
,
n
i
a
G
D
FIGURE 3. BASIC POSSIBILITIES FOR SHAPE OF THE 1/ETA CURVE
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+00
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+00
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+00
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+00
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Figure 6 illustrates the two most common topologies for
controlling output voltage. While the flter and load are part
of the system, they are outside the feedback loop in most
voltage control systems and can be ignored for the most
basic analysis. Type V1 requires an additional amplifer, but
this topology lends itself well to level shifting input signals
(unipolar input producing bipolar output) with a single resistor
because the summing junction does not move as the input
signal varies.
Type V2 is simpler, but does not go well with single resistor
level shifting because the summing junction moves as the
input signal varies. To level the shift, a reference capable of
sinking and sourcing current should be applied to the opposite
input signal location. This circuit then functions similar to a
four resistor difference amplifer, except a T-network of two
resistors and a capacitor replaces each single R
F
(add the
two resistors for DC gain calculations), and the pin normally
labeled reference is connected to the inverting PWM output.
The output is now differential rather than single ended and
DC circuit gain is simply R
Ftotal
/R
IN
. Extra components may
be required to meet common mode voltage restrictions of
the integrator op amp.
For common current control options, refer to Figure 7.
This time the load is central to stability issues because it is
inside the feedback loop. Load and flter must be specifed
right up front.
Type I1 mandates the PWM amplifer to have 2 Isense pins
(some models have only 1). This topology does not require
high voltage capability for the differential amplifer. For supply
voltages above 200V, this is probably the best choice.
Type I2 is required for PWM amplifers with only one sense
pin. This type should also be considered if the flter contains
a matching network (type I1 assumes matching network
current is delivered to the load). Note a MAJOR change for
the diff amp from type I1:
Differential voltage is still usually a volt or less, but Common
Mode Voltage (we need to reject this) is up to supply voltage!
FIGURE 6. BASIC VOLTAGE CONTROL TOPOLOGIES
Int PWM
Filter Load
Type V2
Int PWM
Diff
Amp
Type V1
Rin
Vin2
Rf
Rin
Rf
Vin1
Vref
Vout=(Vin1-Vin2)
* Rf/Rin + Vref
Four Resistor Diff Amp
Load Filter
FIGURE 7. BASIC CURRENT CONTROL TOPOLOGIES
Int PWM
Diff
Amp
Type I1
Load Filter
Int PWM
Diff
Amp
Type I1
Load Filter
VO
Relative
Output
to a
Step
Function
Input
n
t
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
35 0.4*
40 0.6*
52 0.8*
64 1.0*
77 1.2*
90 1.4*
Open Loop Phase Margin & Damping Factor
SQUARE WAVE TEST
0 1 2 3 4 5 6 7 8 9 10
13 0.2*
AMP
A
B
Vout
+Vs
-Vs
2Vp-p
FIGURE 5. THE SQUARE WAVE STABILITY TEST AND
RESULTS INTERPRETATION
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This means CMRR is VERY important and buying a pack-
aged instrumentation amplifer is almost always superior to
making one. Remember that the basic four-resistor differential
amplifer exhibits a common mode rejection error voltage of
common mode voltage times the ratio mismatch between
the two resistors on the plus input and the two on the minus
input. To achieve 80dB CMRR (even with a prefect op amp),
resistor mismatch between the plus and minus sides needs
to be limited to .01%!
6.0 TOOLS FOR DESIGN
PowerDesign.exe is a self-extracting spreadsheet for Excel
97 or later. The PWM Stability sheet automates much of this
application note, plus includes diagrams and macros for fast
execution of common tasks. The liberal use of comments
(place cursor in cells with the red triangles) helps the user
with both spreadsheet use and with hints and facts on PWM
operation. It is the fastest of all the design tools. Its limitations
include dedicated topologies, no square wave test, as well
as minimal data on maximum bandwidth.
Spice state average models are available for both Berkeley
based and Pspice based simulators. With no PWM switching,
these models run many times faster than the pulse by pulse
models and they can run an AC sweep, making the optimiz-
ing of feedback loops very quick once a schematic has been
captured. With a Spice platform, topologies are wide open.
Spice macro models are the closest to the hardware of all
the tools. Pulse by pulse switching will show some distortion
elements the faster tools cannot. They may also show you
some capacitors are working harder than you ever imagined,
but these additional capabilities may boost simulation time
more than two orders of magnitude. Also, these models are
not capable of an AC sweep.
So, all three of these software tools agree to your design.
This does NOT mean the design is done. There are some
things to check which should only be trusted to bench work
with real hardware. Signifcant problems may still exist relating
to a mix of high current, high voltage and high frequency all
at the same time. When using the fastest PWM amplifers,
one inch of wire in the wrong location can destroy perfor-
mance. Most readily available op amp models do a poor job
of predicting real errors when the input is overloaded with
high frequency garbage. While a pulse by pulse model, along
with modeling EVERY parasitic would be impressive (and
maybe even correct), who has the time and ability to fgure
size and location of each one?
Before going to the bench, here are a couple of cau-
tions:
1. Even though years of op amp experience may have taught
you to start with a reduced load, this can be dangerous
with PWM circuits. A reduced load means the flter you
designed is improperly terminated, and may produce
output voltages far in excess of the supply voltage.
2. Starting with a reduced power supply is fne, as long as
you realize bandwidth will increase and phase margin will
decrease when the higher design value is applied.
7.0 SIMPLE R-C VOLTAGE CONTROL
EXAMPLE 1
This frst example adds to Example 1 from APPLICATIONS
NOTE 32, PWM LOW PASS FILTERING. The design critera:
SA01 operating on a 70 to 85V supply
V
RAMPp-p
= 5V
CMV limits = 2V and 8V
Reference output = 7.5V
Op amp Vos = 10mV
Switching frequency = 42KHz
Output = up to 50V, from 10Hz to 2KHz
Input signal = 10V
As the drive system has 10V available, type V2 topology
will be used to yield a simple, low part count circuit. Figure 8
shows the PowerDesign screen after entering SA01, selecting
the topology, and the initial data entry. Use command button
100 to eliminate bias resistors and then enter known data in
the column of yellow input cells. The frst pass selection for
R
IN
was 5K, yielding a 2mA loading of the drive signal.
Suggestions for pole frequencies were used and the Load
Green Suggestion Values button was clicked.
The two feedback resistor suggestions are a convenient
split totaling the value (appears in the upper right corner)
FIGURE 8. INITIAL DATA ENTRY AND PRELIMINARY CHECKS FOR TYPE V2 CIRCUITS
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required to meet overall gain specifed, with the 5K input
resistor. The 1/11 split means the loading effects of the larger
resistor on the pole, created by the smaller resistor and the
capacitor, will be at a minimum. After a standard value is
entered for R
F2
, the suggestion for R
F1
is recalculated as the
ideal total minus R
F2
. The feedback pole frequency reported
here, is calculated as though the larger resistor did not exist.
It is perfectly acceptable to use both resistors equal to half
the R
F
total value given. The 1/eta plot, the peaking, and
phase margin will still be correct. Now is the time for two
preliminary checks.
First check the will be power ratings for the two feedback
resistors. The resistor connected directly to the PWM outputs
must be checked for AC power. With the associated pole fre-
quency being substantially less than the F
SW
, the impedance
of the capacitor will be much less than that of the resistor.
Assume a square wave of Vs/2 is applied to approximate the
reported power for this resistor. The second resistor power
rating is reported as a DC function, assuming the PWM output
pin is being held at Vs. Notice that with a 5K input resistor,
there is nearly 3/4W in the smaller resistor. It was decided to
change R
IN
= 15K, which will allow a 1/2W resistor to handle
the job with some margin. New values for R
F2
and R
F1
will be
68.1K and 6.9K. The second check to be made is to see
if the suggested capacitor values are in a convenient range.
Increasing R
IN
will decrease capacitor values.
After entering the new input resistor value and loading
suggestions, we need to turn our attention to biasing and
CMV. Refer to Figure 9A for the most important new numbers.
With no bias resistors, we have problems on both ends of the
CMV window. Lets attack the lower side by entering roughly
the suggested value, 33K for the high side bias resistor. This
suggestion is a DC calculation of the resistor required to pull
the combination of R
F
(assuming V
OUT
= 0) and R
IN
up to the
lower CMV limit when connected to VREF. In Figure 9B, the
lower CMV limit has been met but the upper is still too high.
The second suggestion appears and is 33K *CMV / sj
peak. To rephrase, the 19.1K is the 33K lowered by the
amount that the V
SJ p-p
is still too high. When the 19.1K is
entered as in section C, the reported VSJ peaks are both
too high. The 17K suggestion for the lower bias resistor
is a DC calculation of the resistor needed to pull down the
combination of R
F
(assumes V
OUT
= V
S
), R
BIAS HI
and R
IN
, to
the upper CMV limit. In section D, the 16.9K has been en-
tered, the summing junction voltages meet the CMV limits,
and voltage offset gain is ~14.3. Use this gain to calculate
Vos, NOT signal gain.
The process varies with application, but basics of selecting
bias resistors are:
The high bias resistor has the most affect on V
SJ
-peak.
The low bias resistor has the most affect on V
SJ
+peak.
Selection assumes PWM outputs reach 0 & V
S
(a safety
margin).
Selection is an iterative process.
A near perfect selection results in:
High bias actual = second suggestion (19K here).
Low bias suggestion = a large number of either polarity.
Summing junction voltages close to specifed limits.
Less than perfect selection results in increased Vos gain.
1/eta plot may change quite a bit at low frequencies.
With feedback resistor power levels and DC biasing out
of the way, we can turn to stability. There are only two deci-
sions to be made here, the T-network pole and the integrator
pole frequencies. The T-network pole placement relative to
F
SW
determines what fraction of the square wave output is
fed back to the integrator. A good place to be is 1/10 of F
SW
,
where coincidentally, the fraction is about 1/10. The second
decision is picking a fraction of the T-network pole to assign to
the integrator pole. The rule of thumb is 0.4. Smaller fractions
tend to yield more stable circuits at the expense of system
bandwidth. Capacitor values for the frequencies entered are
suggested automatically. Initial results of entering 4.2KHz for
the T-network and 2KHz for the integrator (this is our system
requirement), are shown in Figure 10.
The job now is to fnd standard values, which will maintain
or improve phase margin without reducing the integrator pole
below 2KHz. Figure 11 shows our choices.
Additional steps used to verify this design are shown
in Figures 12-14 (next page) . The frst two utilize the
state average spice models with each analysis requir-
ing only a few seconds simulation time. The AC sweep
indicates the circuit is only 0.85dB down at 2KHz.
The square wave test agrees with Power Design in
saying we have adequate phase margin. This model
could also show us that supply current is substantially
less than the ~7A delivered to the load. Next is the
pulse by pulse simulation which required 4 minutes
simulation time on a 750MHz PC. This model could
also provide vast quantities of switching waveform
data. Last is the hardware square wave test. This is
the only test verifying that the op amp is not getting
into trouble with high frequency common mode voltage.
Ctn nF 5.4919 5.491888996
Cf nF 36.075 36.07512043
Phase margin 39.438
Peaking, dB 2.0357 F @ peak Hz 3651.74
FIGURE 10. INITIAL STABILITY CHECK ON THE SHAKER
TABLE DRIVE.
Ctn nF 5.491888996
Cf nF 36.07512043
Phase margin
Peaking, dB F @ peak Hz 4216.97
4.7
33
39.935
1.9317
FIGURE 11. FITTING THE CIRCUIT TO STANDARD VALUE
COMPONENTS
CMV low, V 2 Sugges
R bias hi K 1E+12
R bias lo K 1E+12 16.
CMV low, V 2 Sugges
R bias hi K 33
CMV low, V 2 Sugges
R bias hi K 19.1
CMV low, V 2 Sugges
R bias hi K 19.1
R bias lo K 16.9 -
Tntwk pole KHz 4
A
B
C
D
tions: Rf2 watts 0.0875
34.375 sj +peak 14.167
21621622 sj -peak 9E-11
34.375 19.2706 sj +peak 12.335
73003802 sj -peak 2.0604
34.375 13.3835 sj +peak 11.53
12492528 sj -peak 2.9668
34.375 19.3668 sj +peak 7.9675
1861.9363 sj -peak 2.0502
Vos gain 14.365
FIGURE 9. CHANGES DUE TO THE 15K INPUT RESISTOR
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EXAMPLE 2
Heres the given data for this example:
MSA260, half bridge mode operation
Vcc = 15V, Vs ranges from 156V to 178V
Output = 10.2 to 53V, basically a DC amplifer
Load resistance = 3.7 at low output, 5.2 at high output
Makes use of the onboard error amplifer and voltage
reference
This example is extracted from Power Design, PWM Ex-
amples sheet where details of product selection, flter and
inductor design and heatsink selection are also covered. The
topology of Figure 15 will be used in this example. While the
flter and load are part of the system, the frst order stability
analysis is not affected by their values and you will enter
only load resistance which is used to approximate internal
voltage loss.
Type V3 is limited to half bridge operation and is easiest
to understand with non-inverting PWM operation from the
PWM input to the output (the percentage of time the output
is high increases as the analog input increases). Alternately,
the integrator can be used upside down (ground the -input
and connect the passive component to the +input) with an
inverting PWM function. Some applications may require
Rbh, some Rbl, and some do not require either bias resistor.
Initial data entry into Power Design is shown in Figure 16.
Here are some entries that may not be obvious:
1. Zload is the mid range of the load impedance.
2. Vref2 must be within the common mode range of the
integrator (0 to 4V for the MSA260), usually positive, and
a lower amplitude than Vref1.
3. Setting Ri to 5K just seemed a reasonable starting point.
4. The MSA260 provides a 5V reference.
5. The high bias resistor was left open because the suggested
value was negative.
6. The suggested value for the low bias resistor was entered.
7. Pole frequencies were more conservative than the sug-
gestions in the comments because we have virtually no
bandwidth concerns.
8. The command button to Load Green Suggestions was
used.
9. Rcf is normally only used in servo loops.
10. Rnf and Cnf put a noise flter pole at 15.9KHz, a good
design practice.
While the values in Figure 16 would produce a working
VDB(OUT)
-20
-10
0
10
20
A
C

R
E
S
P
O
N
S
E
S

(
d
B
)
10 10
1
10
2
10
3
10
4
10
5
FREQUENCY (Hz)
FIGURE 13. STATE AVERAGE SPICE MODEL AC
SWEEP TEST
Int
Cf
Ri
PWM
Rf1 Rf2
Ctn
Rbh
Rbl
Vref1
Vref2
Rcf
Rnf
Cnf
FIGURE 15. The simplest of all closed loop PWM systems is Type V3.
V
(
O
U
T
F
)

(
V
)
3.0 3.5
FIGURE 14. PULSE BY PULSE SPICE MODEL
SQUARE WAVE TEST
-75
-50
-25
0
25
50
75
0.5 1.0 1.5 2.0 2.5
TIME (ms)
V(OUTF)
V
(
O
U
T
)

(
V
)
FIGURE 12. STAGE AVERAGE SPICE MODEL
SQUARE WAVE TEST
-75
-50
-25
0
25
50
75
0.5 1.0 1.5 2.0 2.5 3.0 3.5
TIME (ms)
V(OUT)
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circuit, please check the 4W rating for Rf1 on the right and
the large Cf on the left. All component values in the lower half
for Figure 16 are scaled to the specifed value of Ri. Figure
17 shows all the rescaled values and operating parameters
when Rin is increased to 20K.
Power Design makes it easy to check component toler-
ances for both DC and dynamic performance, as shown in
Figure 18. The top group indicates our choice of standard
values places the output voltages within 167mV of nominal.
In the second group, reference voltage divider accuracy is
altered 1% (integrator voltage offset is also in series with
the reference voltage) to fnd maximum error to be 0.7V.
The next group pegs error at 0.45V for a 1% change in Ri.
The next two groups show similar errors for variations of
the bias resistor and the larger feedback resistor. As phase
margin decreases when the two pole frequencies get closer
1/ETA
-20
0
20
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
Frequency, Hz
G
a
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n
,

d
b
Desired Values: Operating points: Initial operating:
Zload 4.5 PWM gain 89 Rf total KW 85.6
Vout high, V 53 Vin ma p-p 0.5 Rf leg mA 1.6856
Vout low, V 10.2 Gain@1 pin 89 Vint p-p 0.4809
Vin high, V 0 DV @ 1pin 42.8 Overall gain 4.28
Vin low, V 10 I FDBK High 0.59
Vref2 (for Vin) 2.5 Rcf KW 0 I In High -0.125
Vs 178 Rnf KW 1 Delta Isj 0.465
Ri KW 20 Cnf nF 10 Actual operating:
Vref1 (for bias) 5 Eff PWM gain 85.486
Rf leg mA 2.0777
Suggestions: Rf1 watts 0.893
R bias hi KW 1E+12 -5.37688442 Rf2 watts 0.3315
R bias lo KW 5.36 5.376884422 Vos gain 21.267
Tntwk pole KHz 1 Vint p-p 0.5011
Int pole KHz 0.3 0.4 O/A gain 4.2835
Rf2 KW 76.8 77.81818182 Eff Rf 1.0022
Rf1 KW 8.87 8.8 Rcf zero KHz #DIV/0!
Ctn nF 18 17.9430601 NoisepoleKHz 15.915
Cf nF 470 529.3745216 TntwkpoleKHz 0.9968
Phase margin 41.242 Int pole KHz 0.3379
Peaking, dB 1.6625 F @ peak Hz 805.842 Vout hi, V 53.167
Vout lo, V 10.332
FIGURE 17. The final design values and operating parameters.
Vref2 (for Vin) 2.5
Ri KW 20 Vout hi, V 53.1668
R bias lo KW 5.36 Vout lo, V 10.3318
Rf2 KW 76.8
Ctn nF 18
Cf nF 470
Phase margin 41.242
Peaking, dB 1.6625
Vref2 (for Vin) 2.525
Rf2 KW 76.8
Vref2 (for Vin) 2.5
Ri KW 20.2 Vout hi, V 53.0607
Rf2 KW 76.8
Vref2 (for Vin) 2.5
Rf2 KW 76.8
Vref2 (for Vin) 2.5
Rf2 KW 77.57
Ctn nF 18.18
Cf nF 423
Phase margin 40.488
Peaking, dB 1.8171
FIGURE 18. Checking component tolerances.
Int
Cf
Ri
PWM
Diff
Amp
Rf
Rdi1
Rdi1
Rdi2
Rdi2
Cdf
Rdf
Cdi
Cdi
Rdf
Cdf
Vref1
Vref1
Vref2
Rbias
FIGURE 19. "ONE SIZE FITS ALL" VERSIONS OF
CONTROLLING VOLTAGE WITH A DIFF AMP.
FIGURE 16. Is this a complete design?
Vout high, V 53 Vin ma p-p 2 Rf leg mA 6.7424
Rf leg mA 8.3178
Rf2 KW 19.455 19.45454545 Eff Rf 0.2503
Ctn nF 81.809 81.80861561 NoisepoleKHz 15.915
Cf nF 2119.2 2119.229685 TntwkpoleKHz 1
Vout lo, V 10.207
Vout high, V 53 Vin ma p-p 2 Rf leg mA 6.7424
Rf leg mA 8.3178
Rf2 KW 19.455 19.45454545 Eff Rf 0.2503
Ctn nF 81.809 81.80861561 NoisepoleKHz 15.915
Cf nF 2119.2 2119.229685 TntwkpoleKHz 1
Vout lo, V 10.207
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together, the last group shows that the worst 10% changes
in capacitance have very little effect.
8.0 VOLTAGE CONTROL WITH A DIFFERENCE AM-
PLIFIER
Refer to Figure 19 (last page) for the general type V1
topology while various options are covered. The schematic
shown here may contain more parts than you actually need
because there are three options to cover.
Option 1: As drawn, this is a full-bridge PWM with the diff
Amp. For half-bridge applications, the diff amp becomes
a simple inverting op amp circuit with Vref1 tied to the
non-inverting input.
Option 2: Op amp supplies may be single or dual. If dual
supplies are used (usually only done when already avail-
able in the system), Vref1 becomes ground. This makes
for a clean circuit where voltages out of the diff amp
and into the integrator are proportional to and not level
shifted from the actual output voltage. If a single supply
is used, Vref1 as shown will allow the diff amp output to
swing negative with respect to Vref1 (required to close
the feedback loop).
Option 3: If the input signal needs shifting, Vref2 can be as-
signed a value higher than Vref1, or below ground, so that
Rbias will provide the proper shift. Consider:
A. The half- bridge output never goes negative, but the input
signal is bipolar with respect to Vref1. This would be the
case with bipolar input signals (single or dual supplies,
Vref1=ground or above) or when input signals range from
0 to a positive level and the op amps are on a single sup-
ply (Vref1 is above ground). If Vref2 is more positive than
Vref1, Rbias is capable of providing the shift. See Figure
20 for the half-bridge version of this circuit
B. The full-bridge output swing is bipolar, but the input signal
range is not spread equally above and below Vref1.
I. This could happen with bipolar input signals and
single supply operation (Vref1 is above ground). If Vref2
is more positive than Vref1, Rbias is capable of providing
the shift.
II. This could also occur when the input signal ranges
from 0 to a positive value and the op amps are running on
dual supplies (Vref1 = ground). If Vref2 is below ground,
Rbias is capable of providing the shift.
C. With this general technique, even a voltage derived
from a 4/20mA loop could be shifted to program a sym-
metric bipolar output or a unipolar output including zero.
The idea is to compute input current for an input signal
voltage where no current fows through R
F
, and make
current provided by RBIAS equal and opposite. For full
bridges, this input voltage corresponds to 0V output. For
half bridges, this input voltage corresponds to an output
voltage equal to Vref1.
This circuit in Figure 20 could be implemented using dual
supplies for the op amps, but additional circuitry must be
added to prevent integrator output swing below ground. Such
an event would be in violation of the Absolute Maximum Input
Voltage range of the PWM amplifer. Even if this caused no
damage, a swing below the lower ramp peak does not result
in any further voltage change at the output. It merely puts a
big non-linearity in the system.
9.0 WHATS DIFFERENT ABOUT CURRENT
CONTROL?
It's already been mentioned that the flter and the load are
inside the loop for a current control application, but here are
a few more handy-to-know details. In applications where the
load does most of the fltering, such as servos, the flter is
often far from that described in Application Note 32. Instead,
the flter only knocks off the sharp edges of the raw output,
and the load mainly does the job of demodulating the signal
from the carrier. The tricky part lies in the load that usually
contains moving parts and the mechanical factors need to
be equated to electrical parameters for a complete analysis
of the system.
Even when there is a flter in the more normal sense, it
often diverges from textbook design when it comes to the
matching network. The textbook flter includes this network if
the load has any reactive elements because a fat pass band
requires the load to appear resistive to the flter. One way to
think of the network/load relationship is that any frequency
change induced decrease of load current is accompanied by
an equal increase of network current making the total imped-
ance appear constant. A second way to view this situation
is the amplifer output current is never equal to load current.
Because monitoring amplifer output current is the easiest
way to implement current control, the network impedance
is often larger than ideal, the flter is not ideally terminated,
and the output voltage at the load peaks near F
C
. It would
be a good idea to keep this voltage mode peaking down to
no more than 10dB.
10.0 CURRENT CONTROL USING THE ISENSE PINS
EXAMPLE 3
This application provides current drive for a coil. Bandwidth
of the circuit needs to be DC to 2.5KHz. Heres the rest of the
given data for this example:
SA12 full bridge amplifer
Vcc = 15V
V
RAMPp-p
= 4V
Input signal = 2.5 to 7.5V
Load impedance = 0.3mH, 9
Load current = 10.2Apk
System does not have a negative supply
For a quick way to fnd required voltage drive, use the Power
Design, Power sheet. For this load to reach the required cur-
rent at maximum frequency, it will need 103.5V peak swing.
The answer explaining why a PWM was selected is also on
this sheet; a perfect linear solution for this drive will need to
Int
Cf
Ri
PWM
Op
Amp
Rf
Rdi1 Rdi2
Cdf
Rdf
Cdi
Vref1
Vref1
Vref2
Rbias
FIGURE 20. THE HALF-BRIDGE VERSION IS SIMPLER THAN
THE FULL BRIDGE
AN41
856 AN41U
dissipate 312W and most real op amps weigh in at 350 or
more watts. The next stop will be the PWM Filters sheet. F
C

was set at 20KHz, second order component values were
rounded off, except the resistive component of the matching
network was doubled. In the PWM Power
sheet, signal drive was set to voltage
control for a peaking test. See Figure 21
for the results.
With all the preliminaries out of the way,
(including selection of a 120V for the main
supply), the next stop is the PWM Stability
sheet. In the top left corner of this sheet,
SA12 in entered and the Type I1 confgu-
ration is selected. Figure 22 (next page)
shows the area where the flter, matching
network and load can be entered manually
or extracted from our previous work. For
frst pass analysis, leave the inductance of
the load equal to zero. If you started with
the PWM Filters sheet, this inductance will
be the lower right cell.
Figure 23 illustrates more circuit set up. Given data is entered
and the frst circuit choice is a value for the input resistor. A
range between 1 and 10K usually avoids both excessive
loading of the signal source and high impedance nodes that
tend to either kill bandwidth, pick up noise or oscillate.
There are two logical choices for sense resistor values; the
one that will develop the voltage required for activation of the
SA12 current limit function (100mV) and the value to develop
about 1V (a safe level which will not affect the switching ac-
tion of the lower MOSFETs). From both the accuracy and
bandwidth points of view, a higher voltage is better. Choices
of value for R
DF
cover a wide range and this choice will scale
values for the input resistors and the roll off capacitors. Very
low values can demand capacitors larger than practical and
very high values can bring on problems with op amp offset
current errors (bipolar input types) or can allow circuit para-
sitics too much infuence on pole frequencies. A good goal
would be make sure all capacitors used are at least 100pF.
The recommendation of F
SW
/10 was used for the diff amp
pole placement and a slightly more conservative entry for
the integrator pole was made. The diff amp will be LF353,
running on the 15V required for the SA12 Vcc supply and the
appropriate swing limitations were entered for Diff V high and
low. Vref1 was set at half the op amp supply to allow the diff
amp to swing symmetrically.
At this point, Vref2, the rest of the Actuals
and the suggestions are all left over from the
last circuit development. Even so, we have
useful information in the suggestion for Rbias;
it is negative and printed in red. This means
the bias reference, Vref2 is the wrong polarity
with respect to Vref1. The spreadsheet has
followed the guidelines above for level shifting:
fnd Vin (5V) for zero current out (no current in
R
F
); fnd input current at Vin=5V (2.5V/1K),
and calculated the resistor needed to provide an
equal but opposite current from Vref2 (7.5V/-
2.5mA). Entering an easily obtained 10V for
Vref2, results in a new Rbias suggestion of 1K.
The suggestion for R
F
will place diff amp
swing exactly at the limits specifed above.
Entering an Actual value higher than the sug-
gestion will demand greater diff amp swing.
The suggestion for Rdi2 will be 10/11 of the
total required to meet diff gain for the overall
transfer function. Entering a close standard
value will recalculate the suggestion for Rdi1
Desired Values: Operating points:
Type I1 Readme SA12 Iout high, A 10.2 Vramp p-p 4
Iout low, A -10.2 PWM gain 60
Vin high, V 7.5
Vin low, V 2.5 Vref1, V 7.5
Vs 120 Vref2, V 0
Ri K 1 diff V high, V 12
Rs 0.1 diff V low, V 3
Rdf K 10
Diff poles KHz 20 Suggestions
Int pole KHz 5 8
Actual
Rbias K 9.3 -3
Rf K 1 1.8
Rdi2 K 3.3 3.709090909
Rdi1 K 0.33 0.78
Cdi nF 100 24.11438532
Cdf nF 3.3 0.795774715
Vref2
Int
Cf
Ri
PWM
Diff
Amp
Rf
Rdi1
Rdi1
Rdi2
Rdi2
Cdf
Rdf
Cdi
Cdi
Rdf
Cdf
Filter
Rv Cv
Rs
Rs
Load
Vref1
Vref1
Rv
FIGURE 23. CIRCUIT SET UP FOR CURRENT CONTROL USING THE PWM ISENSE PINS.
Modeling the PWM Filter & Load
Pole 1 Matching Network Load CC 0 uF
L1 0.1 mH CM 3.3 uF LA 0 mH RC 0 ohms
Rl1 0.032 ohms RM 18 ohms RA 0 ohms LC 0 mH
LM 0 mH CA 1E+15 uF
CD 0 uF
Pole 2 LB 0 mH RD 0 ohms
C1 1 uF RB 0 ohms LD 0 mH
Rc1 0.05 ohms CB 1E+15 uF
CE 1E+15 uF
RE 9 ohms
LE 0.3 mH
L
1
Rl
1
C1
Rc1
C
M
L
M
R
M
CC
L
C
RC
CD
L
D
RD
C
E
L
E
R
E
Pole
1
Pole
2
Loa
d
M
LA RA CA
L
B
RB
CB
Extract Filter/Load values
from PWM Power sheet
108 Print Load Short the Load
FIGURE 22. SETTING UP THE FILTER, MATCHING NETWORK AND LOAD FOR
STABILITY
FIGURE 21. TESTING THE FILTER/LOAD FOR PEAKING
IN THE VOLTAGE MODE
1 10 100
Filter Attenuation
(In Load Current if lout)
B
d
,
n
o
i
t
a
u
n
e
t
t
A
5
-5
-10
-20
-25
-30
-35
-15
0
Frequency, KHz
AN41
AN41U 857
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
making up the remainder of the total input resistance. This
decade relationship between the two input resistors is not
mandatory, but is clean in that Rdi2 will have very little effect
on the pole of Rdi1 and Cdi. If you are happy with the high
and low output values in the lower right of Figure 24, this
completes setup of gain and biasing. If this is not the case,
check for standard values of better tolerance resistors (0.1%
instead of 1% or 5%), or consider adding adjustment networks
for offset and gain. While thinking of DC error budgets, move
up this column to fnd output current errors corresponding
to the voltage offset of the integrator and diff amp op amps.
Stabilizing the circuit will be an iterative process. The frst
step is to set up the circuit for about 10dB peaking with NO
inductive load. In Figure 24, note that Actuals have been
entered for the frst three capacitors using standard values
similar to the suggestions. It is important that Cv and Rv
have large values for this frst phase. Note that our entries
result in a little under 8dB peaking at about 8.7KHz. Peaking
below 10dB will not endanger the fnal stability solution but
will lower bandwidth. Higher values of peaking will make the
fnal stability solution very elusive. Increasing the integrator
capacitor, Cf will decrease peaking. Increasing the diff amp
capacitors will increase peaking. Another way to put all this
is that peaking will decrease as the ratio between integrator
and diff amp pole frequencies widens. Beware: decreasing
diff amp capacitors allows more high frequency energy to
reach the op amp. When satisfed with this step, use the
command button to Defne the Filter/Load, and reinsert the
correct value for load inductance. If your specifc application
has no load inductance, adjust Cf for a phase margin of at
least 30 (more is better, if you can afford the bandwidth),
and you are fnished.
Figure 25 shows the results of re-entering the load induc-
tance value; peaking is too high, phase margin is too low.
Start with the higher suggestion given for Rv and zero in on
a value range yielding 1 to 4dB peaking, and then enter the
suggested value for Cv. The upper suggestion is designed
to limit 1/eta to 10dB above the value calculated at 0.01Hz.
The lower suggestion is designed to limit to 3dB. Figure 25
shows our fnal component selection and the 1/eta plot
results. The circled area in both plots is the result of the volt-
age mode peaking in the flter/load because the matching
network impedance was doubled from design value. Figure
21 shows this peaking in the load. See Figure 26 for square
wave test results with both state average and macro models.
11.0 CURRENT CONTROL USING A SERIES LOAD
SENSE
EXAMPLE 4
This application provides current drive for a motor. Band-
width of the circuit needs to be DC to 100Hz. This circuit
is part of a DSP based system controlling elevation and
azimuth of an antenna. Heres the rest of the given data
for this example:
SA01 operating on 48VDC.
V
RAMPp-p
= 5V
Input signal = 4.2V
Load impedance = 0.3mH, 1.5
Load current = 16.7Apk
Diff amp is INA117 running on 15V
Op amp is LT1013 running on 15V
To avoid signifcant phase shift in the flter, its design ap-
proach was very different from the normal design for a volt-
age output circuit. The objective is to knock off the square
edges of the PWM waveform and reduce the peak to peak
amplitude to roughly a third of the 48V supply. At F
C,
motor
impedance will be very high, leaving the matching network
as the prime termination of the flter, and the prime factor in
determination of ripple current. It was decided that 1.5Ap-p
ripple current would be acceptable. With ripple voltage being
roughly 16Vp-p, 10 would be a reasonable impedance for
1.E+02 1.E+03 1.E+04
1.E+03 1.E+04
A
0dB
10dB
B
0dB
10dB
Cv nF 999 2.2878E-05
Rv K 1E+07 64.86209964
Phase margin 28.966 7.826086957
Cv nF 3.3 3.614914215
Rv K 51 64.8622161
Phase margin 40.046 7.826086957
FIGURE 25. FINAL STEPS OF COMPONENT SELECTION FOR TYPE l1 CIRCUITS
Actual Int Vos, A/V 10.419
Rbias K 1 1 Diff Vos, A/V 12.265
Rf K 1.8 1.8 Iout p-p 20.385
Rdi2 K 2.05 2.060606061 O/A Xfer, A/V 4.077
Rdi1 K 0.215 0.216666667 Eff Rf @.01Hz 0.6552
Cdi nF 33 37.01277746 Diff pole i KHz 22.432
Cdf nF 1 0.795774715 Diff pole f KHz 15.915
Cf nF 47 48.58403031 Int pole KHz 5.1685
Cv nF 999 1.28652E-05 RvCvpoleKHz 2E-08
Rv K 1E+07 64.86209964 Beta 0.01Hz 0.5973
Phase margin 18.379 7.826086957 Iout high, A 10.193
Peaking, dB 7.7364 F @ peak Hz 8659.64 Iout low, A -10.19
FIGURE 24. CHECK THE DC ERROR BUDGET AND START
STABILIZING THE CIRCUIT
AN41
858 AN41U
the matching network. Examination of ideal attenua-
tion graphs indicates a second order flter set at 1/2
F
SW
should yield a -10dB response (about a third).
Loading 21KHz, 10 and 300H into the PWM Filters
sheet yielded (adjusted to standard components)
47H and 1F to ground for each output, plus a
matching network of 3.3F and 10. A check with
the PWM Power sheet (voltage drive mode and the
real 1.5 motor resistance) reveals -10.5dB at 42KHz
and no peaking.
Refer to Figure 27 for data input in the PWM Stabil-
ity sheet. Parasitic values for pole 1 and 2 elements
were defaults calculated. Note that for the frst pass
stability calculations, the load inductance was set to
zero. At the second pass this will be re-entered as
0.3mH. All the given data is entered below this and
some circuit choices will be made. The input resistor
choice was arbitrary. The sense resistor value was a
trade off between voltage loss at high currents and
accuracy errors caused by the voltage offset of the INA117.
The INA117 data sheet also indicates 1K in series with its
inputs will not seriously degrade performance, and this value
will allow reasonable flter capacitor values in the few
KHertz range. The 400K input impedance was also
extracted from this data sheet. Pole frequency for the
feedback poles are set at 1/10 F
SW
and the suggestion
for the integrator pole frequency was used.
As no level shifting was required for this circuit, all
references were set to zero. Again, arbitrarily, inverting
gain for the op amp was entered. This could be changed
to non-inverting as long as the two inputs to the diff
amp were also reversed. The 1K/10K gain setting
for the op amp seemed convenient. The possibilities
for specifc component values have great latitude in
several areas as long as related components are scaled
in a similar fashion. When making specifc choices,
check effects of amplifer bias currents, voltage offset
effects on current output, and keep impedances low
enough such that a stray capacitance of 10pF will
have negligible effect on the circuit.
The A side of Figure 28 (last page) shows sugges-
tions, standard values entered and results for Step 1
where inductance has been removed from the load.
Desired Values: Operating points:
Type I2 Readme SA01 Iout high, A 16.7 Vramp p-p 5
Iout low, A -16.7 PWM gain 19.2
Vin high, V 4.2 Vref1, V 0
Vin low, V -4.2 Vref2, V 0
Vs 48 Vref3, V 0
Ri K 10 o/a gain: +/- -
Rs 0.01 Ropin K 1
Diff amp gain 1 Ropf K 10
Rdi K 1 Rfilt K 10
Rzin K 400
fdbk poles KHz 4 Suggestions
Int pole KHz 1.6 1.6
Actual
Rbias K 1E+12 1E+12
Pole 1 Matching Network Load CC 0 uF
L1 0.094 mH CM 3.3 uF LA 0 mH RC 0 ohms
Rl1 0.0482 ohms RM 10 ohms RA 0 ohms LC 0 mH
LM 0 mH CA 1E+15 uF
CD 0 uF
Pole 2 LB 0 mH RD 0 ohms
C1 0.5 uF RB 0 ohms LD 0 mH
Rc1 0.1 ohms CB 1E+15 uF
CE 1E+15 uF
RE 1.5 ohms
LE 0 mH
Int
Cf
Ri
PWM
Diff
Amp Rfilt
Rzin
Rzin
Copf
Ropin
Cdi
Cdi
Ropf
Cfilt
Filter
Rv Cv
Rdi
Rdi
Load Rs
Op
Amp
Ropin
Rf
Vref1
Vref2
Rbias
Vref3
FIGURE 27. SETTING UP EXAMPLE 4 FOR STABILITY ANALYSIS
Rbias K 10 1E+12
Rf K 3.97 3.966274789
Cdi nF 33 39.78873577
Cfilt nF 100
Copf nF 3.3 3.978873577
Cf nF 27 25.01684876
Cv nF 999 0.000673238
Rv K 999999 125.9623149
Phase margin 19.101 14.16276477
Cv nF 22 19.10162495
Rv K 47 125.9658199
Phase margin 32.422 14.16276477
LE 0.3 mH
Don't forget me!
1.E+03
0dB
5dB
10dB
15dB
A
1.E+01 1.E+02 1.E+03 1.E+04
0dB
5dB
10dB
FIGURE 28. STABILIZING THE TYPE I2 CURRENT OUTPUT CIRCUIT
B
V(INT)
4.88
4.92
4.96
5
5.04
5.08
5.12
V
(
I
N
T
)

(
V
)
I(L6)
-600
-400
-200
-0
200
400
600
I
(
L
6
)

(
m
A
)
4 6 8 10 12
TIME (ms)
V(INT)
4.84
4.88
4.92
4.96
5
5.04
V
(
I
N
T
)

(
V
)
I(L6)
-600
-400
-200
-0
200
400
600
I
(
L
6
)

(
m
A
)
4 6 8 10 12
TIME (m)
FIGURE 26. SQUARE WAVE TESTING EXAMPLE 3
AN41
AN41U 859
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Note that a bias resistor of 10K was entered. Rather than
biasing, this resistor serves as an auxiliary input for offset
adjust and a velocity loop input. As entered, this resistor
has no effect on DC output but it does change the feedback
factor, and consequently the stability solution. The 7.5dB
peaking level is a little on the conservative side. The frst
choice for Rv in the second step (inductance re-entered)
was 39. After running the square wave test with a state
average model, it was decided to change Rv to 47K as
shown in the B side.
By now, some of you have realized there are signifcant
details missing in the presentation of this circuit. The in-
tegrator was set up for 15V, the SA01 on-board op amp
is normally used as the integrator, and it is single supply
only and requires a reference voltage to avoid common
mode voltage violation. Refer to Figure 29 to see the actual
implementation. Here are some reasons for this approach:
1. The INA117 data sheet does not mention single supply
operation.
2. Reference voltage for the INA117 needs to be zero
impedance (requiring an op amp rather than a simple
voltage divider).
3. Voltage offset of the SA01 op amp is 10mV; drift is not
specifed.
4. Driving an SA01 input pin directly with negative voltage
violates Absolute Maximums.
With the INA117 on dual supplies and using ground as
the reference voltage, items 1 and 2 above are no problem.
By using the SA01 op amp as a level shifter, item 4 above
is taken care of. As long as the level shift function has a
gain of one, there will be no changes in AC performance.
This also places the offset and drift of the SA01 op amp
inside the loop of the actual LT1013 integrator with much
better accuracy (item 3).
During circuit development, several variations of the flter
and matching network system were evaluated. In addition
to the 1/eta plot and square wave test, voltages at the
input to the diff amp, on the wires leading to the motor
and across the motor, were analyzed with an input of 0V.
Refer to Figures 30 through 34 for the following points:
1. The only option causing a signifcant change in the 1/
eta plot or the square wave test is the use of large flter
capacitors and no matching network. The reason for
the dip below 0dB at 27KHz is very high voltage mode
peaking as shown in Figure 34. We already knew this
was something to avoid, but read on for other reasons
to stick with the original design.
V(DIFF)
22.0
22.4
22.8
23.2
23.6
24.0
24.4
V
(
D
I
F
F
)

(
V
)
V(WIRE)
16
20
24
28
32
36
V
(
W
I
R
E
)

(
V
)
V(MOTOR)
-20
-10
0
10
20
V
(
M
O
T
O
R
)

(
V
)
475 500 525 550 575 600
TIME (us)
I(R16)
-4
-2
0
2
4
6
I(R
1
6
) (A
)
V(INT)
-750
-500
-250
0
250
500
750
V
(IN
T
) (m
V
)
8 12 16 20 24 28
TIME (ms)
47U
47U
1U
1U
3.3U
10
1.E+02 1.E+03 1.E+04 1.E+05
FIGURE 30. RESPONSE AND WAVEFORMS
SA01
Bout
Aout
EAout
7.5V
5K 10K
10K 10K 47U
47U
1U
1U
3.3U
10
.01
1.5
300U
47K 22N
5K
4.7N
LT1013
LT1013
INA117
1K 1K
33N
33N
1K 10K
4.7N
3.97K
10K
MAIN
10K
AUX
FIGURE 29. SOLVING SEVERAL CIRCUIT LIMITATIONS WITH
UNUSUAL TOPOLOGY
47U
47U
1U
1U
V(DIFF)
12
15
18
21
24
27
30
V
(
D
I
F
F
)

(
V
)
V(WIRE)
-20
0
20
40
60
80
V
(
W
I
R
E
)

(
V
)
V(MOTOR)
-80
-40
0
40
80
120
V
(
M
O
T
O
R
)

(
V
)
100 200 300 400 500 600
TIME (us)
I(R16)
-4
-2
0
2
4
6
I(R
1
6
) (A
)
V(INT)
-750
-500
-250
0
250
500
750
V
(IN
T
) (m
V
)
8 12 16 20 24 28
TIME (ms)
FIGURE 31. RESPONSE AND WAVEFORMS WITHOUT THE MATCHING
NETWORK
AN41
860 AN41U
2. Omission of the matching network brings on high
harmonic content in both the motor waveform and on the
wires leading to the motor, plus it increases the peak-to-
peak amplitude of these two waveforms about 2.5 times.
Note the time scale difference on the motor waveforms in
Figure 31. A major frequency seen here is around 25KHz as
opposed to the 42KHz of the other fgures. If peak voltage
across the motor is 50V, ~0.75A will fow in the motor. This
means power loss and heating will be above optimum.
3. Using an undersized flter capacitor with the matching
network results in wire and motor waveforms with higher
than optimum amplitude and worse yet, they contain con-
siderable high frequency energy (read this as a radiation
problem).
12.0 CONCLUSION
While the typical PWM application is more involved (read
this as more work) than the typical power op amp application,
the additional steps required are in line with the additional
power the PWM can deliver to the load. Using the tools and
procedures presented here will bring out the best from the
very compact and cost effective PWM amplifer. These tools
are available free at www.Cirrus.com.
13.0 ADDENDUM-THE OP AMP INTEGRATOR
Any one for a slow comparator? Thats what we fnd in
Figure 35, where the feedback capacitor slows down the
transition time. During the transition, the op amp is likely
operating in a linear closed loop fashion. The input signal
sets a current in R
IN
because of the virtual ground property
of the inverting input. With no current in or out of the op amp
input pins, the input current path is through the feedback
capacitor to the op amp output. Voltage is developed across
a given capacitor, governed by the time and magnitude of
the input. Linear operation ceases when the output of the
op amp cannot meet the current requirement. This hap-
pens when the op amp slew rate, current capability or most
47U
47U
.01U
.01U
V(DIFF)
20
22
24
26
28
V
(
D
I
F
F
)

(
V
)
V(WIRE)
-50
-25
0
25
50
75
100
V
(
W
I
R
E
)

(
V
)
V(MOTOR)
-120
-80
-40
0
40
80
120
V
(
M
O
T
O
R
)

(
V
)
475 500 525 550 575 600
TIME (us)
I(R16)
-4
-2
0
2
4
6
I(R
1
6
) (A
)
V(INT)
-750
-500
-250
0
250
500
750
V
(IN
T
) (m
V
)
8
TIME (ms)
1.E+02 1.E+03 1.E+04 1.E+05
FIGURE 32. THE EFFECT OF SMALL CAPACITORS AND NO
MATCHING NETWORK
28 24 20 16 12
47U
47U
.01U
.01U
3.3U
10
V(DIFF)
22.0
22.5
23.0
23.5
24.0
24.5
25.0
)
V
(
)
F
F
I
D
(
V
V(WIRE)
10
20
30
40
)
V
(
)
E
R
I
W
(
V
V(MOTOR)
-40
-20
0
20
40
)
V
(
)
R
O
T
O
M
(
V
475 500 525 550 575 600
TIME (us)
I(R16)
-4
-2
0
2
4
6
)
A(
)
6
1
R(I
V(INT)
-750
-500
-250
0
250
500
750
)
V
m(
)
T
NI(
V
8 12 16
TIME (ms)
1.E+02 1.E+03 1.E+04
FIGURE 33. THE EFFECT OF SMALL CAPACITORS WITH THE
MATCHING NETWORK
20 24 28
-10
-5
0
5
10
15
20
25
30
35
0.01 0.1 1 10 100
Frequency, KHz
FIGURE 34. THE CAUSE OF THE FEEDBACK FACTOR DIP
IN FIGURE 31
Filter Attenuation
(In Load Current if lout)
A
t
t
e
n
u
a
t
i
o
n
,

d
B
Rin
Cf
FIGURE 35. WHY WOULD ANYONE WANT
A SLOW COMPARATOR?
AN41
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B
A
often, voltage swing capability is exceeded. This is fne, the
comparator has done its job of switching, with a controlled
transition rate.
With a little modifcation, we can transform this switching
circuit into a very useful linear tool. What is required is a form
of feedback to maintain operation in the transition area, or the
linear area. Figure 36 shows a generalized form of this idea
where (x) is non-inverting. This function is often non-linear,
but seldom contains step junctions.Confning our analysis to
linear operation, there is no current in the op amp input pins.
Looking at the summing junction with three connections, cur-
rent in any given path must equal the sum of the other two
paths. Therefore, capacitor current will be the algebraic sum
of the input and feedback currents:
If I
IN
and I
FDBK
are equal and opposite, the output
does not move.
Notice that our rule on movement of the output does NOT
predict absolute level, only direction and rate of movement.
This can be a magical elixir for many (x) functions. Assume
a simple (x) of V
OUT
= V
IN
- 3V as shown in Figure 37. Apply
+1V as an input signal and mentally apply power. Start the
analysis with the op amp output at zero, the non-powered state.
The battery provides a -3V feedback signal, meaning 2mA
will fow through the capacitor, causing the op amp to slew
positive. Positive slew will continue, though at a decreasing
rate, until input and feedback currents to the summing junc-
tion are equal and opposite. This condition will be reached
when the (x) output = -1V and the op amp output = +2V.
That was simple and may not qualify as magic, but we
get closer if we replace the battery with threshold voltage
of a power MOSFET (moves around part to part and over
temperature) and add a resistor to sense output current
(which we may have very little control over). As long as our
modifcations of (x) do not take the circuit out of the linear
operating range, the op amp still views its job as driving its
output where ever needed to make the sum of all currents
into the summing junction = zero.
Refer now to Figure 38 and assume the op amp output
saturation is 3V from the rails, and common mode voltage is
limited to 3V from the rails. Op amp output range is further
that the input signal = 5V (10Vp-p), R
IN
= 1K, and our 15V
supply is reference quality. Two resistors with a 2:1 ratio will
yield a convenient 5V reference for the op amp +IN, giving
a good safety margin on common mode voltage. Next, set
overall gain according to V
OUTp-p
/V
INp-p
.
R
F
= R
IN
* 9Vp-p / 10Vp-p = 900
Pick a convenient input voltage to compute the bias resistor
needed to satisfy the requirement of zero net current to the
summing junction. With the input signal = 5V, the circuit output
will be zero (the overall transfer function = -0.9V/V). At this
assumed point, current through R
IN
= 0 and current through
R
F
= 5.556mA. We need 5.556mA bias from a reference of
the opposite polarity of the feedback voltage with respect
to the summing junction. This may seem a waste of words,
but if (x) were +30V, the bias resistor would need to go to
ground instead of the 15V reference.
R
BIAS
= 10V / 5.556mA = 1.8K
If you care to check out operation at -5V input, current
through R
IN
= 10mA from a source negative with respect to
the summing junction and current through R
BIAS
= 5.556mA
from a source positive with respect to the summing junction.
For a net zero, current through R
F
must be from a source
positive (opposite that of the larger current) with respect to
the summing junction and be equal to the difference of our
frst two currents. Start with the summing junction voltage
and add I * R.
VOUT = 5V + (10mA - 5.556mA) * R
F
= 9V
Basic operation of the circuit shown in side A of Figure 39
(next page) is identical to the common op amp four-resistor
difference amplifer shown on the side B. Note that on the
difference amplifer, the voltage difference between the output
and Vref is always Vin (combined value) times the gain. Circuit
A is doing the same thing, except the B output connection
has been substituted for the reference input, meaning the
voltage difference between the A output and B output is
always Vin times the gain.
Next, assign circuit A input resistors of 1K and feedback
resistors of 10K, providing an overall gain of 10, and a
maximum supply voltage in the output stage of 50V. At 0V
in, both outputs will be at 25V; at either input extreme, one
output will move to 50V and the other will move to 0V. As-
sume the same op amp limitations and +15V supply as above.
Starting with the non-inverting input, we know the pin needs
to be pulled up at least 3V at all times; worst case is when
the B output is 0V. The 1K and the 10K are effectively in
parallel so we need enough current to pull 909 up to 3V or
3.3mA. With 12V across R
BIAS
, its value should be 3.64K.
As this is a balanced circuit; the two bias resistors MUST be
equal. A mismatch in these two resistors results in an offset.
Rin
Cf
Rf
3V
+5V
+15V
Rb
+15V
FIGURE 38. MOVING TO SINGLE SUPPLY OPERATION
Rin
Cf
Rf
Transfer
Function
(X)
Ifeedback
Iinput
FIGURE 36. THE INTEGRATOR IN A SYSTEM
V = (Iin + Ifdbk) t/C
Rin
1K
Cf
Rf
1K
3V
FIGURE 37. INCLUDING A SIMPLE TRANSFER FUNCTION
AN41
862 AN41U
Our last step is to check common mode voltage when the
B output is 50V.
Many of us could quickly fnd a node voltage fed with two
sources, through two resistors, but would be slowed down
considerably when three legs feed the node. Refer to Figure
40 for a simple way to solve this circuit question with iteration.
Start with the two legs having fxed voltage; fnd an equivalent
voltage and resistance doing the same job as the original
pair. V
EQ
will be the voltage present if you removed the 10K
resistor, or 3.23V. R
EQ
will be the parallel value of 3.64K and
3.64K
1K
10K Req
785
10K
Bout Bout
Veq
3.27V
+15V
? ?
FIGURE 40. EQUIVALENT ELEMENTS HELP SOLVE FOR NODE VOLTAGE
Rin
Cf
Rf
7.5V
+15V
Rb
+15V
*5
*-5
25V
25V
Rin
Cf
Rb
+15V
Rf
B
A
Rin
Vin2
Rf
Rin
Rf
B
Vin1
Vref
Vout=(Vin1-Vin2)
* Rf/Rin + Vref
A
FIGURE 39. WHY WOULD ANYONE THINK UP THIS?
1K, or 785. The equivalent
circuit for the +input can now
be quickly used for any value
of B output. With the B output
= 50V,
V+IN = 46.77V / 10.785K *
785 + 3.23V = 6.7V
This solution fnds common
mode voltage very safe with
respect to the 12V specifca-
tion on the upper end.
Congratulations! You have
set up an integrator to drive
a rudimentary stage average
model of an SA60 running on Vcc = 15V (7.5V battery) and
Vs = 50V (the 25V batteries).
Biasing integrators for common mode voltage, or to level
shift the input signal, is neither magic nor difficult. The overall
transfer function must be known and linear operating limits
must not be exceeded. The objective is then to reduce the
sum of all currents to the summing junction to zero. When
this is done, the charging rate of the capacitor is zero, and
the op amp does not move. We have a stable operating point.
IMPORTANT NOTICE
AN43U 863
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AN43 Heatsinks, Mating
Sockets, Washers, Vendors
RECOMMENDATIONS FOR THERMALLY
CONDUCTIVE WASHERS
Apex Precision Power thermal washers are also available
from Power Devices. Thermstrate is the material trade name
for these washers unless the model specifcation states oth-
erwise. These washers are pre-coated aluminum stampings
which provide better thermal conductivity than thermal grease,
easier use and freedom from application variables. Electrical
conductivity of these washers makes sleeving of at least two
opposing pins a requirement to achieve correct alignment. A
small number of Apex Precision Power washers are noted to
be electrically insulating or made of Kapton. These are made
of Isostrate material, type MT Kapton with over twice the
thermal conductivity of type HN Kapton. Thermal performance
is similar to a mica washer with thermal grease. Both types
are 3 mils thick and NON-COMPRESSIBLE.
HEATSINK THRU-HOLES
Custom heatsink manufacture or mounting of the Apex
Precision Power power amplifer to a bulkhead for heatsink-
ing, requires the use of individual heatsink thru-holes for the
external connection pins. For the 8-pin TO-3 package the main
path for heat fow occurs inside the circumference of 8 pins.
(Refer to Figure 1)
Therefore, a single large
hole, (to allow the 8 pins to
pass through), will remove
the critical heatsink material
from where it is most needed.
Instead, 8 separate holes
must be drilled. Refer to Table
1 for recommended drill sizes
for heatsink thru-holes for
Apex Precision Power power
amplifer packages.
PIN RECOMMENDED HOLE DIAMETER
DIAMETER DRILL SIZE INCHES mm
.025" #50 .070.002 1.781.051
.040" #46 .081.002 2.057.051
.060" #37 .104.002 2.642.051
Table 1: Heatsink thru-hole sizes.
TEFLON TUBING
Anodized heatsinks can be easily nicked or scratched,
exposing bare aluminum, which is an excellent electrical
conductor. When mounting the Apex Precision Power power
amplifer using a socket, it is recommended to sleeve, with
Tefon tubing, a minimum of two opposite pins. This centers
the external connection pins in the heatsink thru-holes and
prevents electrical shorts when tightening the power amplifer
down on a heatsink. When soldering directly to external con-
nection pins it is recommended to sleeve, with Tefon tubing,
all pins. Table 2 lists the recommended Tefon tubing and some
suggested manufacturers (for manufacturers phone numbers,
see Vendors for Power Op Amp Accessories).
Fig. 1: Main heat fow path,
8-pin to TO-3 package.
Tefon meets all known requirements but many other materi-
als will work fne in some applications if three requirements
are met. The tubing must ft the pin and the heatsink hole, it
must be rated for the maximum voltage of the application and
it must be rated for the temperature extremes of the applica-
tion. Simply stripping the insulation from #14, #18 or #22 wire
may be a viable tubing source.
HEATSINKS
A wide spectrum of applications can be satisfed with the
heatsinks stocked as accessories for Apex Precision Power
power amplifers. All are made of aluminum to provide high
levels of conduction. HS01 clamps over the TO-3 case using
virtually no additional space on a printed circuit board. Some
are suitable for chassis or printed circuit mounting. Some are
designed for chassis mounting only. The HS11 provides the
most protection for prototyping or for production of high power
products. All heatsinks are pre-drilled with hole patterns as
shown. Conservative calculations are recommended for pro-
totype work while performance graphs are included to enable
optimization for production runs. Due to calculation complexity
of thermal circuits and of power dissipation levels where reac-
tive loads are driven, it is often helpful to utilize temperature
measurements after the electrical design has been completed.
Heatsink ratings seen in the Apex Precision Power Application
Notes are thermal resistance from ambient fuid (usually air)
to the mounting area in the center of the hole pattern. Do not
forget to add the thermal resistance of the interface between
the heatsink and the amplifer (see model specifc Application
Notes). These ratings are for the heatsink with unobstructed
air fow with optimum mounting orientation (extrusions would
be suspended in mid-air with fns running vertically) and dis-
sipating enough power to raise the heatsink mounting surface
75C above ambient. While this convention seems to be
common among heatsink manufacturers, making it easy to
compare offerings, it often leaves the designer of an amplifer
circuit with considerable work to do.
Let us frst consider the 75C rise above ambient condition.
Apex Precision Power experience indicates this is a quite large
number. Our research has found substantially different graphs
for correcting thermal ratings for different temperature rises.
A conservative approach is to increase thermal resistance
0. 8%/C for lower temperature rise applications. A heatsink
rated at 1C but required to limit temperature rise to only 60C
would be expected to perform at about 1.12C/W.
TUBING DIMENSIONS
PIN
DIAMETER
Nominal I.D.
Nominal
O.D.
MFG.
MFG.
PART NO. Inches mm Inches mm
.025" .028 .711 .052 1.321
TSI-S22
TFT-250-22
.040" .042 1.067 .074 1.88
TSI-S18
TFT-250-18
.060" .056 1.676 .098 2.489
TSI-S14
TFT-250-14
Table 2: Tefon tubing. SPC Technology
Alpha Wire Corp.
Heatsinks, Mating Sockets, Washers, Vendors
MAY 2009
APEX AN43UREV1
864 AN43U
AN43
0 10 20 30 40 50
0
20
40
60
80
100
0 200 400 600 800 1000
0
0.4
0.8
1.2
1.6
2.0
HEAT DISSIPATED - WATTS
AIR VELOCITY - FEET PER MINUTE
M
O
U
N
T
I
N
G

S
U
R
F
A
C
E

T
E
M
P
E
R
A
T
U
R
E
R
I
S
E

A
B
O
V
E

A
M
B
I
E
N
T

C
T
H
E
R
M
A
L

R
E
S
I
S
T
A
N
C
E

F
R
O
M

M
O
U
N
T
I
N
G
S
U
R
F
A
C
E

T
O

A
M
B
I
E
N
T

C
/
W
A
T
T
HS03
0 5 10 15 20 25
0
20
40
60
80
100
0 200 400 600 800 1000
0
2
4
6
8
10
M
O
U
N
T
I
N
G

S
U
R
F
A
C
E

T
E
M
P
E
R
A
T
U
R
E
R
I
S
E

A
B
O
V
E

A
M
B
I
E
N
T

C
T
H
E
R
M
A
L

R
E
S
I
S
T
A
N
C
E

F
R
O
M

M
O
U
N
T
I
N
G
S
U
R
F
A
C
E

T
O

A
M
B
I
E
N
T

C
/
W
A
T
T
HS01
The conditions of optimum orientation and unobstructed
air fow are also elusive in many power amplifer applications.
Orientation and PC boards or cabinets obstructing air fow
sometimes reduce thermal performance; fans sometimes
enhance it. Calculating the improvement of adding a fan is
not a single step job. When a graph is provided for a heatsink,
the air fow is given in velocity, but most fans are rated in cubic
delivery, and this rating varies with pressure. The Heatsinks
sheet of the Apex Precision Power Power Design spreadsheet
(Excel) will help with the cubic to velocity conversion. The
degree of improvement in thermal performance achieved with
forced air cooling varies with physical features of the heatsink.
The following graph is a composite of known performance and
can be used as an approximation of improvement possible
with the addition of a fan when the specifc heatsink does not
have its own graph.
THERMAL INTERFACE
Both mounting surfaces of the heatsink and the amplifer
are rough and non-fat to a degree where thermal performance
will be compromised if a medium to fll voids is not included in
between these surfaces. Silicone based thermal compound
has a long track record of satisfactory performance when the
fuid base and the fller have not been allowed to separate and
are applied in a thin, even and complete layer. Apex Precision
Power thermal washers also have a proven track record showing
advantages of much lower process variability than manually
applied thermal grease. When using aluminum based washers,
installation must insure the washer does not touch the pins
of the amplifer. See the TEFLON TUBING paragraph above.
DO NOT USE COMPRESSIBLE THERMAL WASHERS.
The Apex Precision Power failure analysis team has seen
many cases where compressible pads lead to cracked ceramic
inside the amplifer when mounting screws are torqued down.
Many Apex Precision Power data sheets proclaim the product
warranty is void if these products are used.
HS02
THERMAL RESISTANCE
AIRFLOW, LFPM
M
U
L
T
I
P
L
I
E
R
,

x
0.9
0.8
0.7
0.6
0.5
0.4
0.9
0.2
0.1
0 1000 800 600 400 200
CAGE JACKS AND MATING SOCKETS
In addition to allowing amplifers to be replaced without
soldering (and potential PC board damage), cage jacks and
mating sockets prevent solder joint stress when the amplifer/
heatsink assembly is rigidly fastened to the PC board and
is subjected to wide temperature variations. Cage jacks are
inserted and soldered into PC boards for each individual pin
of an amplifer. The MS06 mating socket is used in the same
manner as cage jacks. Other mating sockets can be inserted
into PC boards, but also have turret terminals for direct wiring.
0 1 2 3 4 5
0
20
40
60
80
100
0 200 400 600 800 1000
0
4
8
12
16
20
M
O
U
N
T
I
N
G

S
U
R
F
A
C
E

T
E
M
P
E
R
A
T
U
R
E

R
I
S
E

A
B
O
V
E

A
M
B
I
E
N
T

C

T
H
E
R
M
A
L

R
E
S
I
S
T
A
N
C
E

F
R
O
M

M
O
U
N
T
I
N
G

S
U
R
F
A
C
E

T
O

A
M
B
I
E
N
T

C
/
W
A
T
T

AN43U 865
AN43
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
HS04
0 20 40 60 80 100
0
20
40
60
80
100
0 200 400 600 800 1000
0
0.1
0.2
0.3
0.4
0.5
M
O
U
N
T
I
N
G

S
U
R
F
A
C
E

T
E
M
P
E
R
A
T
U
R
E
R
I
S
E

A
B
O
V
E

A
M
B
I
E
N
T

C
T
H
E
R
M
A
L

R
E
S
I
S
T
A
N
C
E

F
R
O
M

M
O
U
N
T
I
N
G
S
U
R
F
A
C
E

T
O

A
M
B
I
E
N
T

C
/
W
A
T
T
0 200 800 1000
0
0.2
0.4
0.6
0.8
AIR FLOW (FT/MIN)
T
H
E
R
M
A
L

R
E
S
I
S
T
A
N
C
E

(
C
/
W
)

400 600 1200
AMBIENT AIR TEMPERATURE 25C
THERMAL RESISTANCE
0 20 40 60 80 100
0
20
40
60
80
100
0 200 400 600 800 1000
0
0.2
0.4
0.6
0.8
1.0
M
O
U
N
T
I
N
G

S
U
R
F
A
C
E

T
E
M
P
E
R
A
T
U
R
E
R
I
S
E

A
B
O
V
E

A
M
B
I
E
N
T

C
T
H
E
R
M
A
L

R
E
S
I
S
T
A
N
C
E

F
R
O
M

M
O
U
N
T
I
N
G
S
U
R
F
A
C
E

T
O

A
M
B
I
E
N
T

C
/
W
A
T
T
HS05
HS06
Thermal Resistance: .96C/W
HS09
HS11
HS13
Thermal Resistance: 1.48C/W
0 200 800 1000
0
0.2
0.8
1
1.6
AIR FLOW FT/MIN
T
H
E
R
M
A
L

R
E
S
I
S
T
A
N
C
E

(
C
/
W
)
400 600 1200
THERMAL RESISTANCE
0.4
0.6
1.2
1.4
HS14
Thermal Resistance: 2C/W
0 200 800 1000
0
0.2
0.8
1
1.6
AIR FLOW FT/MIN
T
H
E
R
M
A
L

R
E
S
I
S
T
A
N
C
E

(
C
/
W
)
400 600 1200
THERMAL RESISTANCE
0.4
0.6
1.2
1.4
HS16
Thermal Resistance: 2C/W
0 200 800 1000
0
0.2
0.8
1
1.6
AIR FLOW FT/MIN
T
H
E
R
M
A
L

R
E
S
I
S
T
A
N
C
E

(
C
/
W
)
400 600 1200
THERMAL RESISTANCE
0.4
0.6
1.2
1.4
0 4 8 12 16 20 24 28
0
20
40
60
80
100
C
A
S
E

T
E
M
P
.

R
I
S
E

A
B
O
V
E

A
M
B
I
E
N
T

(
C
)
POWER DISSIPATED (WATTS)
FREE
AIR
N.C. Horiz. & Vert with
Dissipator (Free Air)
200 FPM w/ Dissipator
500 FPM w/ Dissipator
1000 FPM with Dissipator
32 36
0
.09
FLOW RATE (GPM PER CHANNEL)*
R
S
W

(
C
/
W
)
*
*
1 2 3 4
.10
.11
.12
.13
.14
.15
.16
R
SW
=.675 C/W (Free air vertical)
R
SW
=.102 C/W (Water cooled
@ 1 GPM per channel)
Additional mounting loss (with thermal grease):
PD12: .008 - .017 C/W
TO-3: .05 - .1 C/W
* Both channels fed in parallel
using clean water
** R
SW
=Thermal resistance from
heatsink to water
866 AN43U
AN43
HS21
R
SA
= 5.6C/W
0 200 800 1000
0
0.2
0.8
1
1.6
AIR FLOW FT/MIN
T
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L

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(
C
/
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400 600 1200
THERMAL RESISTANCE
0.4
0.6
1.2
1.4
HS31
Thermal Resistance: 1.48C/W
A
D
C
B
6 42 36 30 24 0 12 18
100
80
60
40
20
0
POWER DISSIPATED, (WATTS)
C
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.

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A
B
O
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E

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(
C
)

A. Free air
B. 200FPM forced air
C. 500FPM forced air
D. 1000FPM forced air
HK26/HARDWARE KIT
FOR DX (SIP12) PACKAGE
4-40 X 7/16 Screw (2)
Heatsink (not supplied)
Customer PCB
TW12 Thermal Washer (1)
Shoulder Washer (2)
No. 4 Lockwasher (2)
4-40 Hex Nut (2)
SIP Package Product
(not supplied)
.218
.115
Thru
.135 .031
.040
Shoulder Washer Dimensions
Keystone Part No. 3049
Nylon 6/6 per ASTM D4066
ACCESSORIES VENDORS FOR POWER AMPLIFIER
The following list answers the most common requests received
on the Apex Precision Power Design Support Request. It is
by no means a complete list of sources, but can save you
valuable time locating requirements not found in the Apex
Precision Power data book.
CAGE JACKS
Mill-Max Manfacturing Corp.
516-922-6000 Fax 516-922-9253
http://www.mill-max.com
CHIP CAPACITORS
NOVACAP
800-227-2447 Fax 661-295-5928
http://www.novacap.com
CORES
Magnetics
800-245-3984 Fax 412-696-0333
http://www.mag-inc.com
Micrometals, Inc.
714-970-9400, 800-356-5977 Fax 714-970-0400
http://www.micrometals.com
FAST DIODES
Intersil Corp.
888-468-3774 Fax 321-724-7000
http://www.intersil.com
MicroSemi
800-713-4113 Fax 949-756-0308
http://www.microsemi.com
Philips Components
800-447-1500
http://www.semiconductors.philips.com
Semtech
805-498-2111 Fax 805-498-3804
http://www.semtech.com
Vishay
610-407-4800 Fax 610-640-9081
http://www.vishay.com
HEATSINKS
AAVID Thermalloy Technologies, Inc
603-224-9988 Fax 603-223-1790
http://www.aavidthermalloy.com
Wakefeld Engineering
603-635-2800 Fax 603-635-1900
http://www.wakefeld.com
International Electronic Research Corp.
818-842-7277 Fax 818-848-8872
AN43U 867
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HIGH VOLTAGE SUPPLIES
International Power
805-981-1188 Fax 805-981-1184
http://www.internationalpower.com
Power-One Inc.
805-987-8741 Fax 805-388-0476
http://www.power-one.com
UltraVolt, Inc. DC/DC Converters
800-876-7693 Fax 631-471-4696
http://www.ultravolt.com
Emco High Voltage
209-223-3626 Fax 209-223-2779
http://www.emcohighvoltage.com
HIGH WATTAGE SUPPLIES
DYNA Power Corp.
248-471-1800
http://www.dynapower.com
Elgar Electornics Corp.
800-733-5427 Fax 858-458-0267
http://www.elgar.com
LOW VALUE RESISTORS
Caddock Electronics, Inc.
951-788-1700 Fax 951-369-1151
http://www.caddock.com
ISOTEK
800-569-6467 Fax 508-676-0855
http://www.isotekcorp.com
Vishay Dale Electronics
402-564-3131 Fax 402-563-6418
Riedon, Inc.
626-284-9901 Fax 626-282-1704
http://www.riedon.com
Vishay
610-407-4800 Fax 610-640-9081
RESISTANCE WIRE
MWS Wire Industries
818-991-8553 Fax 818-706-0911
http://www.mwswire.com
TEFLON TUBING
Alpha Wire Corp.
800-522-5742 Fax 908-925-6923
http://www.alphawire.com
THERMAL GREASE
AAVID Thermalloy Technologies, Inc
603-224-9988 Fax 603-223-1790
http://www.aavidthermalloy.com
VOLTAGE TRANSIENT SUPPRESSORS
MicroSemi Corp./Santa Ana Division
800-713-4113 Fax 949-756-0308
http://www.microsemi.com
Semtech Corp.
805-498-2111 Fax 805-498-3804
http://www.semtech.com
Vishay
610-407-4800 Fax 610-640-9081
NOTE:
Many of the above items can be purchased in small quantities
through distributors such as:
Allied Electronics
800-433-5700
http://www.alliedelec.com
DigiKey Corporation
800-344-4539 Fax 218-681-3380
http://www.digikey.com
Mouser Electronics
800-346-6873 Fax 817-804-3899
http://www.mouser.com
Newark InOne
800-463-9275 Fax 773-907-5339
http://www.newark.com
AN44
868 AN44U
AN44 Driving Piezo-
electric Actuators
1.1 INTRODUCTION
The word Piezoelectricity is derived from the Greek and
means 'electricity by pressure'. Piezoelectricity is a classical
discipline dating back to the research of Jacques and Pierre
Curie in the 1880s. The phenomenon, piezoelectricity, describes
the interrelationship between mechanical strain upon a solid
and its electrical behavior. One can create an electrical output
by applying a force to the material sometimes called the direct
piezoelectric effect, thereby transforming mechanical energy
into electrical energy. Conversely, a distortion can be devel-
oped by applying an electric feld, the reverse electric effect,
which transforms electrical energy into mechanical energy. If
the applied voltage is an alternating feld, then it will cause the
substance to vibrate, thereby generating mechanical waves at
the same frequency as the applied feld.
From this classical discipline an extraordinary number of
applications have been developed, particularly, over the last
20 years. A list, by no means complete, appears in Table 1.
The piezoelectric phenomenon is relatively complex and
the reader is referred to the book listed in the 'References'
for a more rigorous treatment
1
. However, in this Application
Note we shall confne ourselves to information relating to
piezoelectric actuators and to the electronics that is essential
to drive them.
1.2 PIEZOELECTRIC CRYSTALS
Piezoelectric actuators are fabricated from materials that
exhibit the piezoelectric effect. These include a number of
naturally-occurring crystals such as quartz, tourmaline and
sodium potassium tartrate. In addition there are piezoelectric
ceramics which include lead titanate and lead zirconate which
are often identifed as PZT. These materials exhibit certain
advantages over single-crystal quartz including higher piezo-
electric coefficients, ease of fabrication into components of
any size and shape, mechanically hard and robust, as well
as chemically inert. PZT devices are manufactured from their
respective oxides and carbonates of Pb, Zr, Ti, rare earths,
and alkaline metals.
Above what is known as the Curie Temperature (T
C
) piezo-
electric materials exhibit a simple cubic symmetry as shown in
Figure 1a, and the unit cell contains a central cation, denoted
by the black dot, which has no dipole moment or in other
words, the negative and positive charge sites coincide so
there are no dipoles present in the material. However, below
T
C
, these lattice structures shift to a tetragonal symmetry, as
illustrated in Figure 1b, in which the positive and negative
charge sites are no longer coincident. This is denoted by the
fact that the central cation is displaced from the center of the
unit cell. These materials are now termed ferroelectric because
their behavior is analogous to the behavior of ferromagnetic
materials. As depicted in Figure 2a, the dipoles are randomly
oriented in each of the various Weiss Domains (see glossary,
pg. 13) in the material above T
C
.
A ferroelectric material can be transformed into a piezoelectric
material if it is subjected to a strong electric feld at a tempera-
ture slightly below T
C
along any chosen axis, as depicted in
Figure 2b. This is called Poling. The infuence of the feld will
also elongate the material along the poling axis.
When the feld is removed, the dipoles remain locked in an
approximate alignment, as shown in Figure 2c. It is this align-
ment of the dipole moments within the various Weiss Domains
that enables the crystal to behave as a piezoelectric material.
Central
cation
Central
cation
(a) (b)
Figure 1. (a) A PZT elementary cell showing the cubic lattice above the Curie temperature; (b) The cell becomes a tetragonal
lattice below the Curie temperature, after it has been poled. Note that the central cation has shifted upwards.
Driving Piezoelectric Actuators
MAY 2009
APEX AN44UREV2
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(a) (b) (c)
Poling
voltage
Poling
axis
Weiss
domain
Figure 2. How the electric dipole moments align before polarization (a), during polarization (b) and after polarization (c).
Their benefts
No moving parts makes motion in the sub-nanometer
range possible. Because there are no moving parts in
contact, there is virtually no limit on resolution.
Fast response - piezoelectric actuators respond in a
matter of microseconds. Acceleration rates of more than
10,000 g can be realized.
High force generation - capable of moving loads of
several tons. Piezoelectric actuators can cover travel
ranges of several 100 m with resolutions in the sub-
nanometer range.
No magnetic felds - because the piezoelectric effect is
related to electric felds, piezoelectric actuators produce
no magnetic felds nor are they affected by them. Therefore
such devices are especially well suited for applications
where magnetic felds cannot be tolerated.
Low power consumption - static operation, even hold-
ing heavy loads for long periods, consumes virtually no
power. A piezoelectric actuator behaves very much like
an electrical capacitor. When at rest, no heat is gener-
ated.
No wear - no moving parts such as gears or bearings.
The displacement is based upon solid-state dynamics
and therefore exhibits no wear. Endurance tests have
been conducted on piezoelectric actuators that have
exhibited no measurable change in performance over
several billion cycles.
Vacuum and clean room compatible - piezoelectric
actuators cause no wear nor require lubricants.

Operates at cryogenic temperatures - the piezoelectric
effect continues to operate even at temperatures ap-
proaching zero degrees Kelvin.
TABLE 1. PIEZOELECTRIC ACTUATORS BENEFITS AND APPLICATIONS
Their applications
Data Storage
Magnetic recording head testing
Spin stands
Disk testing
Active vibration cancellation
Pole-tip recession test
Semiconductors, Microelectronics
Nano & Microlithography
Ultrasonic soldering
Wafer and mask positioning
Ultrasonic wirebonders
Inspection systems
Precision Mechanics
Fast tool servos
Ultrasonic drilling
Structural deformation
Tool adjustment
Wear compensation
Needle-valve actuation
Micropumps
Linear drives
Knife-edge control in extrusion tools
Micro-engraving systems
Medical and Dental Technologies
Brain scanners
Ultrasonic cataract removal
Ultrasonic scalpels
Plaque scalers
Lithotripters
Cell penetration
Microdispensers
Optics, Photonics
Scanning mirrors
Image stabilization, pixel multiplication
Scanning microscopy
Auto-focus systems
Fiber-optic alignment
Fiber-optic switching
Adaptive and active optics
Laser tuning
Vibration stimulation
AN44
870 AN44U
1.3 PIEZOELECTRICS ACTUATORS SOME BASICS
Within the cylindrical piezoelectric actuator illustrated
in Figure 3a, when a voltage is applied longitudinally, a
deformation occurs along the axis of the device causing a
displacement L, as depicted in the illustration. Typically a
piezoelectric material can withstand a strain, or change in
length, of 0.1%. This means that an actuator that is 100-mil-
limeters long that is poled (energized) along its axis can be
expanded by 0.1 mm.
The displacement, or change in length of an unloaded
single-layer piezoelectric actuator can be closely approxi-
mated by:
(1)
Where:
L = the change in length (meters)
S = strain-per-unit length or relative length change
(meters/meter, and therefore, dimensionless)
E = the electric feld strength (volts/meter)
L
O
= the length of the actuator (meters)
d
33
= piezoelectric coefficient (meters-per-volt) where
the frst subscript identities the axis of the feld
and the second subscript identifes the axis of
the displacement.
The maximum electric feld that most ceramic piezoelectric
actuators can withstand is on the order of 1 to 2 kV/millimeter.
To extend the travel beyond the approximately 0.1% maximum
of a single slice and to avoid applying too large an applied
feld, a multilayer piezoelectric actuator can be fabricated
by gluing thin layers of the piezo material together to form a
stack. A voltage is then applied to each layer individually, as
depicted in Figure 3b, so that each is powered, independently.
Now the applied voltage applied to each slice is still the
same, but the total displacement is simply the sum of the
individual displacements, or:
(2)

1.4 DRIVING AT FREQUENCIES BELOW RESONANCE
When a piezoelectric actuator is driven by an AC voltage,
the equivalent circuit is quite complex
2
. However, when a
piezoelectric actuator is driven by a periodic voltage source
with a frequency below the resonant frequency of the piezo-
electric actuator, which is often the case in inkjet applications,
then the device can be modeled by a single capacitor. In this
case the impedance presented to the driving source is, to a
close approximation, simply:
(3)
Where: f = the frequency of the driving source
C
PA
= the equivalent capacitance of the piezoelectric
actuator
2.1 GUIDELINES FOR DESIGNING DRIVER CIRCUITS
Some essentials to keep in mind when designing systems
that employ piezoelectric actuators are these:
Limited strength in tension - The tensile strength of a
cylindrical piezoelectric actuator is approximately 10%
of its strength in compression. It is essential to abide by
these values to avoid fracturing the piezoelectric actuator.
Specifc values can be obtained from data sheets supplied
by piezoelectric actuator manufacturers.
Boundaries on acceleration - When driven by a periodic
waveform the acceleration will increase exponentially
with frequency. So it is important to identify the upper
limit of the device's ability to withstand high acceleration
forces. In particular, multilayer piezoelectric actuators are
vulnerable to delamination should their acceleration limits
be exceeded.
Driver circuits do consume power - Piezoelectric actuators
consume virtually no power when static, other than the
quiescent power consumed by the electronics. However,
the power dissipation demands upon the operational
power amplifer circuits when the actuator is driven are
signifcant, indeed.
Follow sound principles in designing the driving circuits
Make sure the driving power operational amplifers are
operating in their safe operating region and current limit-
ing is provided to protect the circuitry from an inadvertent
short circuit. Other essential design tasks include selecting
a satisfactory heatsink, fyback diodes and compensation
capacitors. Many of these issues are covered in the dis-
cussion of the sample circuits described in the following
sections.
L = SL
O
Ed
33
L
O
L
TOT
= NL
Z
LOAD
=
1
2fC
PA
L
V
+
L
V+
L
(a) (b)
Figure 3. Two Linear Piezoelectric Actuators A single stack in (a) and a multilayer (b) in which the displacement is amplifed
by the number of slices.
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2.2 A BRIDGE-CONNECTED DRIVER CIRCUIT
The circuit that appears in Figure 4 was developed to drive
a piezoelectric actuator that requires 300 Vp-p at 80 kHz.
However, it will function at any frequency down to and includ-
ing DC. The sinusoidal source applies 15 Vp-p at 80 kHz to
drive the amplifer pair which, in turn, drives the piezoelectric
actuator. In this case the actuator can be represented by a
1-nanofarad capacitance in series with a 1-Ohm resistance,
as depicted in the fgure.
Two PA78 power operational amplifers are confgured in
this bridge circuit
3
. In this confguration the amplifers provide
an output voltage swing that is twice that of a single power
operational amp. This confguration also doubles the slew rate
of a single device. Any nonlinearities become symmetrical,
thereby reducing second-harmonic distortion when compared
with a single-ended amplifer circuit.
A Floating Load - In this application, the load is foating,
which is to say it is not ground-connected at all. When the
left output V
OUTA
swings from 10 to 160V (Figure 5a) and the
right output V
OUTB
descends from 160V to 10V (Figure 5b),
a voltage swing of 300V (-150V to +150V) develops across
the load, as depicted in Figure 5c.
The outputs of the two amplifers are now out of phase. The
overall gain of the bridge-confgured PA78s is +20 so that 300
Vp-p is delivered to the piezoelectric actuator, as required.
The feedback circuit comprising resistors R3 and R4 center
the outputs of both of the PA78 amplifers at about 85V. As
shown in Figure 4, a dual-source, asymmetric power supply
delivers +175V and -5V to the two amplifer modules
4
.
Establishing the +V
S
and -V
S
headroom - The values of
+V
S
and -V
S
must be chosen so there will be sufficient head-
room during the positive and negative excursions of both V
OUTA

and V
OUTB
. Though the output (V
OUTA
V
OUTB
) shown in Figure
5c, will swing from +150V to -150V, it is actually the Common
Mode Input Range (CMR) positive and negative values of
the amplifer and specifed in the PA78 data sheet that will
play a signifcant role in governing the values of +V
S
and -V
S

employed in this asymmetrical sourcing arrangement.
In the case of the PA78, the specifed value of the CMR
negative is -V
S
+ 3V. This means the input should approach
the negative rail no closer than 3V. So by choosing -V
S
equal
to -5V, both V
OUTA
and V
OUTB
, will exhibit negative excursions
of 10V and will thereby approach the negative rail no closer
than 15V.
The CMR positive is +V
S
- 2V. This means the most posi-
tive-going excursion of both V
OUTA
and V
OUTB
must stay at
least 2V below +V
S
. A second issue with regard to the +V
S

rail is the voltage drop at the output when the amplifers are
delivering peak current and in this application the peak
current is approximately 75mA. There is a graph in the PA78
data sheet called "Output Voltage Swing" which discloses
that the drive current is 75mA, the loss will be approximately
8 volts. The sum of the two, 2V and 8V, is 10V, which means
that the +V
S
must be at least 10V above the maximum volt-
age swing of 150V. By choosing a +V
S
of 175V an additional
headroom margin of 15V is established.
+
V
1
15V
P-P
0 to 80 kHz
R
F
20K
R
C
3K
R
LIMA
8.2
R
F
10K
R
C
3K
R
LIMB
6.8
R
INB
10K
R
B
3K
R
B
3K
R
LOAD
1
R
5
10K
R
6
10K
R
4
20K
R
3
1K
C
B
6.8pF
C
B
6.8pF
C
C
6.8pF
C
C
6.8pF
C
LOAD
1nF
CR
1
MUR160
CR
3
MUR160
CR
4
MUR160
CR
2
MUR160
+175V +175V
+175V
5V
5V
5V
Piezoelectric
Actuator
V
OUTA
C
C+
C
R+
V
S
I
LIM
C
R
C
C
+V
S
+IN
IN
PA78-A
V
OUTB
C
C+
C
R+
V
S
I
LIM
C
R
C
C
+V
S
+IN
IN
PA78-B
Figure 4. Bridge Connected A pair of PA78s drive the piezoelectric actuator and are powered by asymmetric power supplies
at +175V and -5V.
AN44
872 AN44U
In any piezoelectric actuator circuit it is essential to prevent
signals from inadvertently feeding back to the amplifer. A
piezoelectric transducer can just as easily convert mechanical
into electrical energy and vice-versa. So if something were
to inadvertently bump the transducer, it could create a lot
of energy that would travel backwards into the output of the
amplifer. This could be destructive. However, by simply con-
necting several ultra-fast, MUR160 diodes (CR
1
CR
4
) from
the output of each amplifer to its corresponding power supply
rails, as shown in Figure 4, each amplifer is protected.
Computing the maximum dissipated power per module
- The load impedance of the piezoelectric cartridge is given
by the expression:
(4)
To compute the maximum power per module we can
devise the equivalent circuit shown in Figure 6. This is done
by splitting Figure 4 into two parts with each part comprising
a 2-nF capacitor and a 0.5-Ohm resistor, while assuming a
Vout
A
a)
+160V
10V
Vout
A
b)
+160V
10V
Vout
A
- Vout
B
c)
+150V
0V
-150V
300V
P-P
Figure 5. Output Waveforms a) Left module output; b) Right module output; C) Waveform appearing across the piezoelectric
actuator.
1
j2(80x10
3
)(1x10
9
)
1
jC
R+ =1+
= 1 j1989 j1989 Ohms
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It is essential to confrm that the junction temperatures of
the MOSFET devices in the PA78 amplifers will not exceed
a safe value.
The familiar thermal resistance equation is:
(7)
This equation can be modifed by substituting the thermal
resistance of the heatsink
HS
for
CA
:
(8)
Next the equation is solved to confrm that the anticipated
junction temperature (T
J
) will not exceed the maximum allow-
able junction temperature.
By rearranging the terms equation (8) becomes:
(9)
In this design the power per device is 5.18 watts and the
JC
according to the PA78 data sheet, is 5.5C/W. The
HS

for the heatsink is 7.8C/W, as determined from Figure 7a,
and the rise in temperature above the ambient is determined
from fgure 7b is 40.4C.
So the maximum junction temperature will be:
(10)
Therefore the actual T
J
will never rise above 93.9C. This
is far below the maximum permissible value of 150 C speci-
fed in the PA78 data sheet.
Finally, it is essential when applying high power to a highly-
reactive load, such as a piezoelectric actuator, to check the
device's power dissipation rating and the safe operating
area. The former is discussed in reference 5 and the latter
is covered in the PA78 data sheet.
virtual ground denoted by the dotted line and symbol. Since
the real part of the impedance (1 Ohm) is negligible com-
pared with the total capacitive reactance of 1989 Ohms, it
can be neglected.
In the equivalent circuit the applied voltage will be one half
the total potential applied to each module:
(5)
The circuit for each half will drive half the capacitive reac-
tance which is 1989 divided by 2 or 994.5 ohms.
The key to determining power dissipation begins with
knowing the phase difference between V & I in the load. In
this case it is quite simple because we have modeled our
load as a pure capacitor, so the phase angle is simply 90
degrees. The formula for determining the maximum power
dissipated in the case of a reactive load for a phase angle
greater than 40 is given by
5
:
(6)
Where: V
S
= the magnitude of each supply
Z
L
= the magnitude of the load
impedance magnitude
So:

Since the load is totally reactive, the 5.18 watts is dissi-
pated by each of the PA78 amplifers and none by the load.
We can then go on to select a heatsink and confrm that the
maximum allowable junction temperature of each PA78 will
not be exceeded.
Dealing with the heat - An Apex Precision Power HS27
heatsink has been selected for mounting each PA78. The
thermal resistance of each amplifer is 5.5C/W and as
previously determined, the dissipation of each amplifer will
be 5.18 watts.
0.5[(+V
S
) (-V
S
)] = 0.5[(175V) (-5V)] = 90V
P
D
(MAX) =
2V
S
2
Z
L
P
D
(MAX) =
2(90)
2
(994.5)
= 5.18 watts
P
JA
= T
J
T
A
P(
JC
+
CA
) = T
J
T
A
P(
JC
+
HS
) = T
J
T
A
T
J
= P(
JC
+
HS
) + T
A
T
J
= P(
JC
+
HS
) + T
A
= 5.18(5.5 + 7.8) + 25C
= 68.9C + 25C = 93.9C
1 1nF
0.5 0.5
2nF 2nF
[(+V
S
) (-V
S
)]/2 [(+V
S
) (-V
S
)]/2
Virtual
Ground
Figure 6. Equivalent circuit for computing the maximum power dissipation
AN44
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selected, at any instant. If so, they are all driven at once by
the piezo transducer.
Different Waveforms for Different Inks - To success-
fully develop the inkjet printer just described requires that
electrical, mechanical, and chemical expertise be brought
together to achieve the right combination of parameters for
each specifc inkjet printing requirement.
In early, large-scale ink jet printers, the high-voltage signal
was simply a huge square wave such as a 48-volt drive
signal which was either on or off. That was fne up to a
point, but it did not provide satisfactory control over the size
and shape of the droplets dispensed by the jet nozzle. Also,
the square corners of the waveform caused ringing and
hindered the delivery of well-formed ink droplets.
At lower resolutions such aberrations seldom matter.
However, at higher resolutions, precise control of the size
and shape of the ink droplet becomes essential. Based on
this, various waveforms have been devised for printing vari-
ous kinds of inks.
The simplest is a trapezoidal waveform which exhibits a
controlled ramp on the up slope and a ramp with a slightly dif-
ferent slope on the down sideas depicted in Figure 9. Though
these slopes are well controlled, they are not necessarily
symmetric. The rise on the up slope is likely to be faster.
Whereas on the down slope a longer fall time is necessary
to make sure ink will have sufficient time to fow from the ink
magazine to the nozzle chamber.
The slower speed also ensures sufficient ink will be avail-
able when the next droplet is dispensed. A representative
wave form is shown in Figure 9. For some inks it may be
necessary to double-pulse the piezo transducer to overcome
oscillations which might hinder satisfactory ink delivery.
Depending on the ink employed, such double-pulsing can
counteract oscillations that would otherwise occur when the
droplet leaves the jet.
2.3 MULTIPLEXING PRINTHEAD ACTUATORS
Piezoelectric nozzle assemblies for drop-on-demand
printing look very much like an old-fashion hair comb where
each of set of tines is an ensemble of jet nozzles. These
nozzles are very thin and can therefore be stacked quite
close together, one above the other.
A representative drop-on-demand printing head confgu-
ration might employ a single power operational amplifer to
drive 128 nozzles. A variation of time-division multiplexing
is employed. It departs from a conventional system of time-
division multiplexing which normally connects to just one
node at a time. Because in this case the power amplifer
may be connected to any number of ports at any one instant
from 0 to 128.
Depicted in Figure 8 is a simplifed diagram illustrating
128 MOSFET switches which connect each piezoelectric jet
nozzle in the printhead to the power operational amplifer.
Consequently, at any instant, the voltage on each piezo-
electric driver is either zero volts or full voltage, depending
on whether that nozzle is on or off. As shown in the fgure,
each nozzle is turned on by grounding the piezoelectric
transducer via the MOSFET switch element corresponding
to the nozzle it drives.
However, the high-voltage piezoelectric driver remains
connected at all times to all of the high sides of the 128
nozzles via a bus.
The MOSFET switches enable controlling the entire en-
semble, digitally. The switches allow the negative return of
each piezo transducer to either foat in which case the
companion nozzle does not dispense a droplet of ink or
to be grounded, so as to dispense a droplet of ink. At any
instant, the printhead carrying all 128 nozzles is emitting
anywhere from 0 to 128 ink droplets as governed by the
program instructions delivered to the bank of MOSFET
switches. Perhaps numbers 12, 84 and 128 nozzles are
1.0 3.0 5.0 7.0 9.0
1.0 3.0 5.0 7.0 9.0
17.00
12.75
8.5
4.25
0.00
65.0
48.8
32.5
16.2
0.0
Power dissipated (W) Power dissipated (W)
T
h
e
r
m
a
l

R
e
s
i
s
t
a
n
c
e

(
C
/

W
a
t
t
)
T
e
m
p
e
r
a
t
u
r
e

(
C
)
(a) (b)
Figure 7. Heatsink Behavior for the Apex Precision Power HS27 heatsink. The thermal resistance as a function of power dis-
sipated is shown in (a); the temperature rise at the interface with the power module is plotted in (b).
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1 s
2 s
0 V
+48 V
Pulse Repetition Rate = 33 s
1 s
1 s
2 s
4 s
5 s
Dispense ink
Refill nozzles
Figure 9. This tailored waveform was devised to optimize performance for a specifc printhead.
R
S
power operational
amplifier
Piezo
transducers
1 2 128
Piezo
print
command
voltage
Nozzle
1
Nozzle
128
Nozzle
2
Print head
R
IN
Figure 8. Simplifed diagram using MOSFETs to multiplex the piezo transducers which form the printhead and is fabricated from
a single piece ceramic endowed with piezoelectric characteristics.
Avoiding Pitfalls - Because piezoelectric elements are
almost purely capacitive and therefore dissipate virtually no
power, disposing of the heat is of paramount importance.
Almost all the build-up of power is dissipated in the power
amplifer module. This must be safely transferred from the
power operational amplifer module via thermally-efficient
heatsinking in such a way that the operating temperatures
within the power operational amplifer remain safely below
its rated safe operating temperature.
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There is no single circuit which will fulfll all piezoelectric,
ink-driver design objectives. That is why understanding all the
design issues is so essential to developing driver circuits.
In one application a user intended to drive four piezoelectric
printheads in parallel with each head driving 256 nozzles. In
this case the pulse currents were fairly high because of the
need to drive 1000 nozzles in parallel.
Assuming that the individual piezoelectric tranducers ex-
hibit a capacitance of one nanofarad, 1000 nozzles present
a capacitance of approximately 1 microfarad as the load for
the power operational amplifer. That is a lot of capacitance.
Now let's say you want to apply a 50 volt, 1 microsecond
pulse. Given that I = C x dV/dt, then I = 10
-6
x 50/10
-6
= 50
amps. This design will require a power amplifer that will be
able to deliver 50 amps such as the Apex Precision Power
Logic MP111FD.
This calculation assumes the worst case when the load is
100 percent capacitive. However, this is never going to be true
since there will always be some stray resistances including
the wiring. In some cases there may be a discrete resistor in
series with each channel. This would completely change the
assumption above, thereby reducing the current to a level
much less than this calculation would indicate.
In another application a design group wanted to employ
a 50 volt pulse and was planning to apply +/-100 volts to
the amplifer. Whenever current is applied to a capacitor, of
course, there will be a reverse current fow during each pulse
cycle, which discharges the capacitor. While the capacitor is
charged, one side of the amplifer delivers the entire current
pulse, but the capacitor will momentarily have a 100 volt
potential across it. However, the voltage will never go below
zero. So there is no reason to have a 100 volt symetrical
supply. Having one would raise power dissipation within the
amplifer, while serving no useful purpose.
Tailoring waveforms - Common to all designs is a wave-
form tailored to the specifc characteristics of the ink to be
dispensed. Principal governing factors are the viscosity of
the ink and the shape and size of the droplet to be delivered
to the printing surface and the mechanism of the printhead
itself.
In some cases a double pulse is the optimal wave shape.
The rise and decay of each pulse may have to be different.
These wave shapes are developed empirically and are then
stored in a computer so that the optimal waveshape for each
ink and its specifc application can be retrieved at a later
time. The power amplifer must be designed to deal with
any arbitrary wave shape that may be required for a given
printing solution.
Here are some of the essential steps in designing the
piezo transducer circuit:
Determining design parameters - The Apex Precision Power
MP111FD power operational amplifer is particularly well
suited for driving piezoelectric transducer arrays. It is a
100 volt device with a 500 KHz power bandwidth and a
50 amp pulse capability. Shown in Figure 10 is a simplifed
drawing of the MP111FD power operational amplifer in an
inkjet transducer application with the companion passive
components identifed.
R
SH
R
F
R
I
R
S
MP111FD
power operational
amplifier
Piezo
print
command
voltage
Transducer
array
-I
LIM
+
C
C
1
OUT
+I
LIM
C
C
2
C
SH
C
BP
C
C
C
BP
-V
S
+V
S
Figure 10. A simplifed diagram using a power amplifer and companion passive components.
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Minimizing distortion - As the amplifer slews, it forces
energy back into the signal source (the piezo print com-
mad voltage). To minimize distortion that might otherwise
occur, it is essential the signal source exhibit a low dynamic
impedance of 1 ohm or less.
Determining power dissipation - Once the waveform for
a particular ink is determined, a simplifed circuit can be
devised to perform a SPICE simulation and thereby deter-
mine the power that will be dissipated within the amplifer.
Selecting a heatsink - It is essential to hold the junction
temperatures within the power amplifer module below
175C. Determining the proper heatsink is a three-step
procedure. First, the average power consumption is deter-
mined. Then the thermal resistivity in degrees C per watt of
the heatsink is calculated. Finally, the thermal resistivity of
the heatsink selected is checked to make sure it provides
sufficient margin, holding the junction temperatures to a
value well below 175 C.
Shown in Figure 11 is a simplifed SPICE circuit that rep-
resents the MP111FD power operational amplifer circuit.
In this example the amplifer is assumed to be driving four
inkjet printheads simultaneously. Each printhead will be as-
sumed to have 256 nozzles for a total of 1024 nozzles. The
total capacitance of the four heads is 1F. If we assume only
every third nozzle is driven at any instant, then the maximum
capacitance in this analysis is reduced to 0.33F. This is the
load capacitance identifed as C1 in Figure 11. A piece-wise
linear waveform is developed by V8 that duplicates the selected
waveform, as illustrated in Figure 9. The results of the SPICE
simulation are depicted by the three graphs in Figure 12.
Plot (1) depicts the amplifed output voltage waveform V(1).
Plot (2) is the current pulse train I(C1) applied to the load
capacitor C1. Whereas Plot (3) shows the average power
dissipated in the amplifer vs. time:
(11) AVG {[(V1)-V(6)] [I(V6)]+[(V(1)-V(4)] [I(V7)]}
Figure 11. Spice representation of the transducer drive circuit. Note that capacitor C1 represents the printhead transducer.
+
+
+
+
+
C2
3pF
R4
1K
R3
10K
R5
10K
C1
0.33F
X2
IRF954ON
V7
-12
X3
IRF540
E1
10K
V6
60
V8
0 PWL
0,0 5,-4.8 9,-4.8 ...
1
4
3
5
2
6
Choosing power supply voltages An unbalanced source
voltage would be best. Assume that a 50 volt pulse is to
be delivered by the power amplifer. Then a +62 volt and
a 12 volt source would be appropriate. This will assist
the charge-discharge cycle because the capacitive load
presented by the array of tranducers must be driven back
to zero volts during each pulse cycle. As the capacitor
approaches zero volts, the 12 volt potential will make
sure that the output transistor of the power amplifer will
still have sufficient potential to drive the capacitor back
to zero volts. This minimizes the power dissipation in the
amplifer and also contributes to signal fdelity.
Selecting passive component values Assuming a gain
of 10, the value of R
I
would be 100 ohms, R
F
is 1 kilohm
and capacitor C
C
is 33 to 47pF.
Dealing with stability issues Because the load is highly
capacitive, a resistance R
S
may need to be placed in
series with the transducer array to improve the stability of
the amplifer circuit. It may be necessary to experiment,
but typical values for R
S
will range from 0.1 to 0.5 ohms
depending on the capacitance of the printhead. Without
R
S
there may be considerable overshoot in the output
waveform that could adversely affect the droplet shape
and the overall performance of the system.
Bypassing the power supply terminals Because the slew
rate of the power amplifer is quite high, there would be
a tendency for the power supply to droop if no precau-
tions are taken. It is recommended that two, 1 microfarad
ceramic capacitors of the leadless, surface-mount type,
CBP, be connected directly to the +V
S
and V
S
pins of the
power amplifer.
Enhancing dynamic response This is achieved by con-
necting a series network comprising a 10pf capacitor C
SH

and a 1kilohm R
SH
in shunt with resistor R
F
, as shown in
Figure 10. This will improve the dynamic response of the
power amplifer. Adjust these values slightly to optimize
the response.
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Plot (3), as governed by this equation, is the average of
the voltage across each output transistor multiplied by the
current through each transistor at each instant in time. The
result at the end of the period is the average power that the
heatsink must dissipate due to the load. It is this average
power, 68 watts, that is of interest in determining the heatsink
requirement.
The pulse rate frequency is 30 kHz and the period of the
pulse is 33.33 microseconds. Notice that in Plot (2) in
Figure 12 the current pulses end after 16 microseconds.
The remainder of the period is dead time. Therefore the
time interval for the average is greater than the time over
which instantaneous energy is being delivered. Conse-
quently, 68 watts is indeed the average power that must
be dissipated by the amplifer over the full period.
Determining heatsink requirements - By referring to the
data sheet for the MP111FD, the AC thermal resistance is
determined to be 0.65C /W. To calculate the temperature
rise of the junctions of the output transistors above the
case temperature multiply the thermal resistance of the
MP111FD by the average power dissipated:
(12)

To determine the permissible case temperature assume
that a normal ambient temperature within the printer will
be 30C. The maximum operating case temperature of
the MP111FD is 85C. Therefore subtract the ambient
from the maximum operating temperature to determine
the permissible case temperature rise:
(13)
Therefore the permissible case temperature rise is
55C.
Though the load, C1, dissipates 68W of power in the
amplifer, the heatsink will have to dissipate the quiescent
power dissipation of the amplifer, as well as the power
delivered by the pulse. The quiescent power dissipation
of the MP111FD with the operating conditions given is
approximately 11W. The quiescent power is due to the
operating power supply voltages and the quiescent current
in the amplifer.
Therefore the actual amount of power that must be dis-
sipated is the sum of the two or 79 watts. The thermal
resistance of the heatsink required is then:
(14)
Where:
X = the required heatsink thermal resistance in C /W
79 = the total amplifer dissipation in watts
55 C = the permitted temperature rise of the amplifer
0 10 20 30 40
Time (s)
A
v
e
r
a
g
e

p
o
w
e
r

(
W
)
I
(
C
1
)

(
A
)
V
(
1
)

(
V
)
0
68 W
(1)
(2)
(3)
10
20
30
40
50
-20
-10
0
10
20
0
40
80
120
160
200
Figure 12. Spice (1) amplifed output voltage V(1), (2) Current pulses I(C1) applied to capacitor C1, (3) average power dissipated
in the amplifer versus time.
0.65C/W 68W = 44.2C
85C 30C = 55C
XC/W 79W = 55C
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REFERENCES
1. "Piezoelectric Transducers and Applications," Antonio Arnau,
Editor, Springer-Verlag, 2004
2. "Piezoceramic Properties & Applications," Chapter 2,
Physical Basics, paragraph 2.9, www.morganelectroc-
eramics.com
3. Cirrus Logic Corp, Application Note 20 Bridge Mode Op-
eration of Power Operational Amplifers, www.Cirrus.com
4. Cirrus Logic Corp, Application Note 21, Section 3.1 Single
Supply Operation of Power Operational Amplifers, www.
Cirrus.com
5. Cirrus Logic Corp, Application Note 1, Section 7.2 General
Operating Considerations, www.Cirrus.com
Solving equation 14 for X yields a thermal resistance of
0.696 C/W. Therefore, any heatsink that exhibits a thermal
resistance of 0.696 C/W or less will be acceptable in this
application.
Confrming the maximum junction temperature - Although
a maximum junction temperature of 175C is allowed, for
long-term reliability a lower temperature would be better.
Check that a heatsink with a thermal resistance of 0.696
C/W will hold the junction temperature of the output
transistors below 175C:
As previously mentioned, the 68 watts of power dissipation
due to the load causes a temperature rise of 44.2C in
the output transistors. The total junction temperature with
the selected heatsink is then the sum of the maximum
case temperature and the temperature rise in the output
transistors:
(15)
Where:
85C = the case temperature with the selected heatsink
44.2C = the temperature rise of the output transistors
due to the load.
Since a junction temperature of 175C is allowed, there
will be a margin of 45.8C acceptable for the heatsink
in this application.
If the power module is to be located near the printhead
and the ink is heated, the operating ambient will be well
above room temperature of the traditional 25C. In this
case liquid cooling or forced air may be required.
Note that for illustration purposes the quiescent current in
the output stage and some other fne details have been
neglected. However, Apex Precision Power has an online
Power Design spread sheet software tool which can eas-
ily help you with all the details of arriving at a heatsink
thermal resistance for your particular application. Log on
to www.Cirrus.com and look for "Circuit Design Software"
under the "Support" icon.
Conclusions - As we have shown, devising a driver circuit
for inkjet circuits requires tailoring a waveform that will optimize
the delivery of the ink droplets by a particular printhead. Then
by following the sequence of steps described, the designer
will be able to confgure a driver circuit that will provide the
necessary current pulse train and preserve the fdelity of the
waveform delivered to the printhead, while addressing the
resulting thermal issues.
85C + 44.2C = 129.2C
GLOSSARY
Cation An atom or a group of atoms carrying a positive
charge. The charge results because there are more
protons than electrons in the cation.
Curie Temperature The Curie temperature (T
C
) is the
temperature below which a ferroelectric material
can be transformed into a piezoelectric material. In
the disordered state above the Curie temperature,
thermal energy overrides any interactions between
the local moments of ions. However, below the Curie
temperature, these interactions are predominant and
enable the electric dipole moments to align so that the
piezoelectric transformation occurs.
Ferroelectric materials So called because their behavior
is analogous to the behavior of ferromagnetic materials.
Poling The transformation of a ferroelectric material into
the piezoelectric state by applying a strong electric feld
along a chosen axis at a temperature slightly below the
Curie temperature (T
C
). The material will also become
elongated along the axis of the feld.
Weiss Domains Regions in a ferroelectric material, with
spans on the order of 0.1 to several mm, in which the
electric-dipole moments, upon being poled, align so
they all face in the same direction.
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AN45 Driving 3-Phase
Brushless Motors
1.1 INTRODUCTION
NOTE: Apex Precision Power has developed a MCU
program with a soft start algorithm for driving motors with
the Apex Precision Power SA305. Download it free from the
SA305 product page at www.Cirrus.com.
When comparing the attributes of a brushless motor with
those of its brush motor equivalent, the most notable differ-
ence is the reduction in size and weight for the brushless
motor offering the same horsepower. What is less obvious is
the absence of the familiar brushcommutator arrangement
that has been at the heart of single-phase DC brush motors
for over a century. The lack of a brush-commutator interface
means brushless motors also exhibit lower acoustic noise, are
virtually maintenance free and they simply last longer.
Despite their many advantages, price points for brushless
motors have been the single greatest detractor from their
gaining wide-spread acceptance. That is until recently. Like
all new technology, it was only a matter of time until gradual
price reductions reached a level where demand would begin
to increase. Today the price differential between brushless
versus brush can be as little as 10 percent.
Adding to the appeal of the brushless motor is the widen-
ing availability of microcontrollers with the special functions
(routines) necessary to control the three-phase operation of
brushless motors. Equally important, and more readily avail-
able, are IC drivers that deliver power to the motor and form
the interface between the microcontroller and the brushless
motor itself.
This application note is intended to help guide the develop-
ment of brushless motor drive boxes and motor drive cards.
These specialized designs include the microcontroller, the
programmability and the driver all in a single assembly.
Lets begin this discussion by looking at the primary differ-
ence between motors with brushes and those without
the use of commutation. Commutation refers to an
on-going sequence of steps that specifes the applica-
tion of voltages to the proper motor phases and imparts
the desired motor rotation throughout each successive
360-degree revolution.
Brush-type DC motors use electromechanical com-
mutation that is achieved via graphite brushes that
contact a circular commutator mounted on the rotor.
The motor is designed so that torque is maximized as
the motor shaft rotates throughout each full 360-degree
rotation. However, in a brushless motor, although there
is sensorless commutation, it is usually performed by
switching electronics that rely on devices such as Hall
sensors. This arrangement is depicted in Figures 1 and
2. The Hall sensors feed back the position of the rotor
at known instants to the control electronics.
Brushless motors use what is commonly referred
to as inside out commutation because their design
is essentially that of a brush motor turned inside out.
Although the stators in the motor are wound, the rotor
is not. Instead it employs a permanent magnet rotor.
The magnetic attraction of the rotor to the revolving
magnetic feld is induced in the wound stator poles and
develops the torque necessary to rotate the motor and
drive the attached load. This scenario is depicted in Figure 1.
Also brushless motors are synchronous in behavior because
the rotor rotates at the same frequency as the magnetic feld
developed by the stator windings. Thus they differ from single-
phase, AC squirrel-cage motors in which 'slip' develops, causing
the rotor to rotate at a slightly lower frequency than the rotating
AC feld, depending on the load.
Thanks to the Hall sensors, the control circuitry always
knows the exact moment to commutate. Most brushless mo-
tor manufacturers supply motors with three Hall-effect position
sensors. Each sensor delivers an alternating binary high and
a binary low as the rotor turns. The three sensors are offset,
as illustrated in Figure 1. Each sensor aligns with one of the
felds developed by one of the wound stator poles. Note that
as depicted in Figure 3, two windings are always energized
while one winding is not.
1.2 A BRIEF OVERVIEW OF PWM
The frst Pulse Width Modulation (PWM) ICs appeared on
the market some 40 years ago, so the concept of switching
electronics is at least as old. Though the earliest applications
were in switching power supplies, it was not much later that
the technique was employed in brushless motors.
The principal beneft of PWM as a control technique becomes
clear by examining Figure 4. The traditional linear power de-
livery technique for limiting power simply employs a variable
resistance as depicted in Figure 4a. When maximum output
is commanded, the driver reduces resistance of the pass ele-
ment to a minimum. At this output level, losses in the linear
circuit are relatively low. When zero output is commanded, the
pass element resistance again approaches infnity and losses
again approach zero.
STATOR WINDINGS
INTERCONNECTIONS
STATOR
WINDING
HALL
SENSORS
DRIVE
SHAFT
ROTOR
SECTION AA'
A
A'
N
S
N
S
N
S
COM
COM
COM
a
c
b
COM
a
c
b
Driving 3-Phase Brushless Motors
MAY 2009
APEX AN45UREV4
Figure 1. A Brushless Motor Differs from a motor with brushes in that com-
mutation is provided by sensors rather than the familiar bush-commutator
arrangement found in a conventional DC motor with brushes.
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The disadvantage of the linear circuit becomes clear in the
midrange when the output level is in the vicinity of 50%. At
these levels the resistance of the pass element is equal to
the load resistance which means the heat generated in the
amplifer is equal to the power delivered to the load! In other
words, a linear control circuit exhibits a worst case efficiency
of 50% when driving resistive loads at midrange power levels.
What's more, when the load is reactive, this efficiency drops
even further.
Now consider the efficiencies of the switching PWM op-
eration as illustrated in Figure 4b. In a PWM control system,
an analog input level is converted into a variable-duty-cycle
switch drive signal, as depicted in the fgure. The process of
switching from one electrical state to another, which in this
case is simply between OFF and ON, is called modulation
thus the phrase Pulse Width Modulation or PWM.
Beginning at zero duty cycle, which is to say OFF all the
time, the duty cycle is often advanced as the motor begins
to rotate until it is running at the speed and/or the torque
required by the application.
In the case of a PWM control circuit, the losses are primarily
due to the ON resistance of the switching FET and the fyback
diode which is why efficiencies as high as 80% to 95% are
routine. However, at high switching frequencies, the energy
required to turn the FETs on and off can become signifcant.
In addition to enhanced efficiency, PWM can provide ad-
ditional benefts which include limiting the start-up current,
controlling speed and controlling torque. The optimum switch-
ing frequency will depend on inertia and inductance of the
brushless motor chosen, as well as the application.
The choice of switching frequency affects both the losses
and the magnitude of the ripple current. A good rule of thumb
is that in general, raising the switching frequency increases
the PWM losses. On the other hand, lowering the switching
frequency limits the bandwidth of the system and can raise the
heights of the ripple current pulses to the point they become
PWM
SIGNALS
CURRENT
MONITOR
SIGNALS
HALL SENSOR SIGNALS
SA305 BRUSHLESS MOTOR DRIVER
MICROCONTROLLER
GATE DRIVER
CURRENT
SENSE
PROTECTION FEATURES
OVERCURRENT
SHORT CIRCUIT
THERMAL
SHOOT THROUGH
BRUSHLESS
MOTOR
HALL
SENSORS
V
PWR
P
GND
COM
a
c
b
N
S
COM
a
c
b
N
S
COM
a
c
b
N
S
COM
a
c
b
N
S
COM
a
c
b
N
S
COM
a
c
b
N
S
Figure 2. Block Diagram A microcontroller and an Apex Precision Power SA305
Brushless Motor Driver provide the necessary functions to drive a brushless motor.
Figure 3. Six Connections By monitoring the Hall sensors, the stator winding felds can be made to rotate so that the resultant
feld of the two energized stator windings and the pole of the permanent magnet rotor remain at right angles, thereby maximizing
the instantaneous torque.
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destructive or shut down the brushless motor driver
IC. The ripple current pulses are depicted in Figure
5 and discussed in more detail later.
1.3 INTEGRATED DRIVERS
Until the introduction of off-the-shelf brushless mo-
tor drivers, such as the Apex Precision Power SA305,
the development of three-phase driver circuits had
to be confgured discretely using three gate drivers
and six FETs. Devices like the SA305 provide an
integrated, fully-protected, three-phase brushless
motor IC solution capable of delivering power levels
of up to 300 watts
1
. The SA305 is fabricated using a
multi-technology process that employs CMOS logic
control together with DMOS output power devices.
This brushless motor driver includes protection fea-
tures such as overcurrent, short-circuit and thermal
shutdown. For instance, the SA305 will shut down
if the instantaneous current reaches approximately
12 amperes.
Operation of the SA305 is shown in Figure 2. The
device features three independent, DMOS FET half
bridges that provide up to 10 amperes PEAK output
current under microcontroller or DSP control. As the
motor rotor revolves in operation, the controller causes
one motor terminal to be driven high, a second low
and the third to foat, as depicted in Figure 3. Proper synchro-
nization of this sequence is assured by the feedback from
the Hall sensors which keeps the microcontroller informed
of the position of the rotor with regard to the stator windings
at known instants.
Shoot through protection is included in this brushless
motor driver IC. Shoot through identifes the state in which
both the upper and lower portions of two half bridges are
on at the same time. This must be avoided, for if it were to
occur, it would overload the circuit and destroy the FETs.
Consequently, a dead time is programmed to allow the
FETs to fully commutate to the next state before power is
applied to the ON FETs.
Fault status indication
and current level monitors
are provided directly to the
SA305 controller. Output
currents are measured us-
ing an innovative low-loss
technique. The SA305 also
offers superior thermal per-
formance with a flexible
footprint.
All brushless motors are
driven by microcontrollers
or some other intelligent
system. A number of manu-
facturers including Analog
Devices, Freescale, Micro-
chip, and Texas Instruments
market microcontrollers for
motion control and more
specifcally for driving brush-
less motors. For example,
the Microchip PIC18F2331
includes a 14-bit resolution
power control PWM module
with programmable dead-time insertion to prevent shoot
through. A brushless motor control algorithm employing this
IC appears in Figure 6.
Although there are a number of sources which you can
turn to for assistance in choosing a motor, brushless or
otherwise, a good starting point is shared in Reference 2.
As the author points out, choosing a motor requires looking
at a whole list of issues including efficiency, torque, power
reliability, and cost. (We also add motor inductance to this
check list. As we shall examine shortly, it plays a vital role
in how the motor will perform.)
95%
50%
5% ON
ON
ON OFF
OFF
V
t
V
t
V
t
OFF
PASS ELEMENT
LOAD
PULSE WIDTH CONTROL
V
S
DRIVER
LINEAR CONTROL
(a) (b)
I
OFF
I =
V
R
1 e
R
L
I =
V
R
t
OFF
I
MAX
I

(
A
M
P
E
R
E
S
)
I =
V
R
I =
V
R
t
t
V
OFF ON ON
t
V
ON
t
( )
1 e ( )
R
L
t
Figure 4. PWM versus Linear Control PWM control in (b) exhibits far lower
losses than the traditional linear control technique in (a).
Figure 5. a) Current behavior with a steady-state excitation
b) Current behavior with PWM excitation
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Initialization
Disable
Start?
Hall Sensor
Inputs
Hanged?
Load Reverse Table Load Forward Table
Reverse Forward
Direction?
Read Value from
Table + Hall (Offset)
Speed
Reference
Change?
Frequency
Reference
Change?
Recalculate
PWM Duty
Cycle
Recalculate
PWM Frequency
Cycle
Fault?
No
Yes
Yes
Yes
Yes
No
No No
No
Yes
Figure 6. Brushless Motor Microcontroller Algorithm
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What can be said categorically is that a brushless perma-
nent magnet motor is the highest performing motor in terms
of torque versus efficiency. Brushless motors allow you to
consider a wide variety of performance options in designing
your application. As we have explained prior, with a brushless
motor you have control of all three stator windings, which is
not the case with a traditional DC motor and its brush com-
mutation. If your decision is to follow the brushless route,
some important guidelines are outlined below.
2.1 BRUSHLESS MOTOR BEHAVIOR
AN OVERVIEW
One of the most critical operations for a brushless mo-
tor also true for a brush motor is when power is frst
applied to the motor while at rest. At that time the rotor is
stationary and is delivering no back EMF or V
BEMF
. V
BEMF

can be expressed as:
V
BEMF
= (K
b
)(Speed) (1)
Where:
K
b
= voltage constant (volts/1000 RPM)
Speed = revolutions per minute (expressed in
thousands)
Once a voltage is applied to the motor, the rotor begins
turning, generating a V
BEMF
governed by Equation (1).
If we ignore for the moment that we plan to drive the mo-
tor with a PWM source and assume the motor is driven by
a steady-state voltage, then we can express the current by
this equation:
I = [(V-V
BEMF
)/R
m
][1-e
-Rt/Lm
] (2)
Where:
V = the applied voltage
V
BEMF
= back EMF
R
m
= stator resistance (winding pair)
L
m
= stator inductance (winding pair)
Note that in Equation (2) the current (I) at any moment is
a function of both the back EMF (V
BEMF
) and the time (t). The
current when the motor is stopped (V
BEMF
= 0) is illustrated in
Figure 5a and is a familiar waveform for characterizing the
current in any L-R circuit with its rise time governed by the
time constant L/R.
Now let's exchange the steady-state
excitation voltage for a PWM source, as
shown in Figure 5b. The current rises
until the frst ON pulse ends. When the
voltage abruptly falls to zero at the end
of the frst applied voltage pulse, the
current begins to decay towards zero.
However, the next pulse will again drive
the current upwards, and so forth, so
that the current continues to rise. As the
motor accelerates, the current wave-
form will exhibit a sawtooth profle. This
sawtooth characteristic is also known
as ripple. Because torque is directly
proportional to current, the sequence
of rising current pulses drives the motor
and develops a corresponding torque
that accelerates the motor.
The applied voltage, the switching
frequency and the PWM duty cycle are
three crucial parameters that can be
programmed independently. How these variables are selected
will effect the behavior of the motor with regard to how fast it
will accelerate, and how fast its speed and torque will develop.
2.2 A SPECIFIC EXAMPLE
This example begins by choosing a motor that will exhibit
the mechanical performance required which is to say the
torque, the efficiency and the other specifcations already
discussed, are sufficient to meet the motor drive requirements
of the end system. For this example a low-inertia, brushless
motor will be used that delivers 55 oz-in of torque at 5000 rpm.
The selected motor is a Galil Motion Control BLM-N23-50-
1000-B (www.galilmc.com). The winding characteristics of this
motor include a stator-winding pair that exhibits a resistance
(Rm) of 1.2 ohms and an inductance (Lm) of 2.6 millihenries.
The torque constant (Kt) of the motor is 12.1 oz-in/A and
the voltage constant Kb of the motor is 8.9 volts/1000 RPM.
First make certain that the maximum current capability
of the IC driver in this case the SA305 with an output of
12 amperes -- is not reached. Should this happen, the drive
circuit will shut down.
If V/R 12 amperes, then regardless of the other parameters,
the current can never reach this value. This can be seen in
fgures 5a and 5b where both the frst and all succeeding
pulses approach the value of V/R. Another way of looking
at it is the current in any L-R circuit can never exceed V/R.
Consequently, voltage which includes any instantaneous
ripple will never shut down the SA305.
If V/R > 12 amperes, then consideration must be given to
several factors in the design. In this example, the Rm is 1.2
ohms. Assuming a 60 volt drive voltage, then V/R = 60/1.2 =
50 amperes. When the initial voltage is applied to the motor,
the current ramps up as explained in equation (2). As the back
EMF builds up, the current will taper off as shown in Figure 7.
Maximum current may never be reached in normal operation
because of the back EMF. The torque constant of the motor
and the inertial load will govern the rate at which the motor
comes up to speed. If the motor has a particularly low L/R
time constant relative to the mechanical time constant, the
current can reach the maximum well before the motor builds
any back EMF.
Figure 7. A graphical approach to determining maximum motor current here the
dynamic simulation of the Galil BLM-N23-50-1000-B brushless motor is illustrated.
50
-2
0
2
4
6
8
0
10
20
30
40
1 0 5 4 3 2
TIME (mS)
V
O
L
T
S
A
M
P
S
100 kHz
95% Duty Cycle
Motor Back EMF
Motor Current
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Note that in this example the simulation depicted in Figure 7
discloses that the current will never rise above 8 amperes
well below the 12 amperes limit. If the current were to exceed
the limit of the driver, adding external series resistance or
inductance would limit the peak current and di/dt respectively,
but each will adversely effect the performance of the system.
If the start-up current is controlled with a PWM drive by
limiting the duty cycle of each pulse and not to exceed the
maximum peak current rating of the driver, the motor can
safely accelerate. The current monitor feature of the SA305
makes this type of feedback relatively simple to implement.
By employing a microcontroller and monitoring the instan-
taneous currents in all three phases, a closed-loop algorithm
can be developed for start-up purposes which would hold the
peak current near 12 amperes without actually exceeding it. A
small amount of headroom makes good sense so program-
ming for an 11 ampere motor current would be best. The
advantage of this approach is that it optimizes the run up and
keeps the current and the acceleration as high as possible.
In this approach the duty cycle would be modulated, based
upon the current sensed in the three phases, as depicted in
Figure 2. Further discussion on the use of microcontrollers to
drive brushless motors is available in References 3, 4, and 5.
A soft-start algorithm can be developed as an open
loop software solution to maintain a low duty cycle, as well
as slowly up the required speed. Programming the start-up
duty also ensures that the overcurrent limit of the SA305 is
not exceeded. A soft-start algorithm is covered in Section 3
of this Application Note.
3.1 GUIDELINES FOR DESIGNING A MOTOR DRIVE
CONTROL PROTOTYPE
The use of the Apex Precision Power DB62 Demonstra-
tion Board is recommended as the frst step in assembling a
prototype. The DB62 is designed to demonstrate the capabili-
ties of the SA305 as a three phase
brushless DC motor driver IC.
The PWM inputs to the SA305
are controlled by an on-board
microcontroller. The supporting
document is the DB62U data
sheet, "Demonstration Board for
SA305EX". The EVAL49 board which
is described in DB62 is pre-wired
for all required and recommended
external components. The Micro-
chip PIC18F2332 which has been
selected to control the SA305 is
pre-programmed for motor control
applications. It is covered in Refer-
ence 6.
By utilizing the on-board Micro-
chip PIC18F2331 microcontroller
with the SA305, PWM input control
is achieved. The resulting circuit of
the DB62 can be easily converted
into the circuit shown in Figure 9
and serve as the base circuit for a
production version. The sequence
table for commutation (obtained
from the motor data sheet) is en-
tered in the program memory of the
microcontroller.
Hall Sensors Hall sensors A, B and C are connected to
the IC pins of the Input Capture (IC) module in the PIC18F2331.
This module interrupts on every transition on any of the IC
pins. Upon interrupt, the interrupt service routine reads all
three inputs and loads the correct sequence for commutation.
Soft Start Algorithm The use of a soft start algorithm
enables controlling the rate of acceleration and consequently
the maximum current. As depicted in Figure 8, there are two
parameters to be programmed: the increment and the delay.
The delay is the time interval between the successive incre-
mental changes in the duty cycle. Whereas the increment is
the percent increase in duty cycle which is implemented at
the end of each delay.
After each increase in duty cycle that is slightly higher than
the last one, there is a delay, or time interval, until the next
incremental change occurs. The effect of the soft start is to
ramp up the motor speed without exceeding the maximum
allowable current until the specifed speed is reached. This
also serves to hold the speed until the motor is shut off.
NOTE: Apex Precision Power has developed a MCU
program with a soft start algorithm for driving motors with
the SA305. Download it free from the SA305 product page
at www.Cirrus.com.
Handling Reversals When the motor is to be reversed, it
is essential that the soft start algorithm is once again initiated,
causing the motor to gradually accelerate in the opposite direc-
tion. Likewise, during development, it is essential to reduce
the duty cycle, holding the duty-cycle start-up current before
attempting to rotate the motor in the opposite direction. Once
the motor begins to rotate in the opposite direction, and the
back EMF begins to build up, the duty cycle may be increased
SPEED
RPM
T
T
V
Increment Increment Increment Increment Increment
Delay Delay Delay Delay Delay Delay
Figure 8. Increment and Delay Principal parameters in the slow start algorithm.
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Maximum Current If the current exceeds 12 amperes,
the SA305 will shutdown at start. Consequently, it is essential
to determine the maximum current which the motor and the
SA305 Drive IC will carry during the start up cycle. If the L
and R are low, the current will ramp up quickly. The use of
back EMF to counteract a high current will not be able to
ramp up so quickly due to the inertia of the rotor. This is dis-
cussed in detail in Section 2.2 of this Application Note. The
maximum start up current can be easily determined by using
Cadence's PSpice simulator which has a built-in brushless
motor simulation program. Also refer back to the soft start
algorithm discussion in Section 3.1.
Three Separate Ground Planes As discussed in detail
in the DB62 document, noise immunity can be enhanced by
three separate ground planes tooled in a multilayer board:
DGND (microcontroller ground), SGND and PGND. The
DGND ground is the most sensitive. The ground planes
should be inter-connected by jumpers as depicted in Figure
9, so that no current fows between the three independent
grounds. These jumpers are located in the center of the
evaluation board at the right of the SA305.
Do NOT connect grounds at any other points. Make sure
there is no direct connection between the P ground and the
S ground. The connections must be made in a manner that
keeps current from fowing through one ground plane to
another via the jumpers.
3.2 PARAMETERS APPLIED TO THE
MICROCONTROLLER
Here are parameters to address as they apply to the opera-
tion of the microcontroller:
V
FREQ
- The PWM frequency can be varied from 4 KHz to
118 KHz by varying the voltage applied between V
FREQ
and
microcontroller ground.
V
DUC
- The duty cycle can be varied from 0 % to 98 % by
varying the applied voltage between V
DD
and ground.
Forward/Reverse - The Forward (High)/Reverse (Low) pin
is provided to control the direction of the motor. Depending
upon the direction, the corresponding Hall sensor com-
mutation sequence shown in the DB62 document is used
and the PWM signals are generated accordingly.
Run/Stop - The Run(Low)/Stop(High) enables starting and
stopping the motor by shifting the applied binary voltage
between V
DD
and ground.
Monitoring Current The SA305 data sheet specifes the
ratio of the sensed current to output (motor) current for
each of the three outputs.
3.3 SPECIFIC DESIGN TIPS
The following is a discussion of key design tips that will
assist in prototype design:
Figure 9. A specifc example Combining the SA305 brushless motor IC with a Microchip PIC18F2331 microcontroller
VPWR
IMON_B
IMON_C
OUT_C
OUT_B
OUT_A
DISABLE
IMON_A
C1
1F
C2
100F
+
C4
1F
C12
100F
C11
1F
+
R23
1K
R24
1K
R25
1K
S
G
N
D
P
G
N
D
D
G
N
D
Vdd
PGND
SGND
OUT_C OUT_A OUT_B
D4 D1 D5
D1 D3 D2
WARNING
OFF
RB7
RC1
PWM4
PWM5
PWM2
PWM3
PWM0
PWM1
RB6
AN0
Vss
Vdd
CAP3
CAP2
CAP1
AN1
VDUC
DGND
Vdd
HALL_C
HALL_B
HALL_A
VFREQ
F/R
R/S
PWM-LC
PWM-HC
PWM-LB
PWM-HB
PWM-LA
PWM-HA
VPWR
OUT_C
OUT_B
OUT_A
I
M
O
N
_
B
I
M
O
N
_
C
I
M
O
N
_
A
O
F
F
W
A
R
N
I
N
G
F
A
U
L
T
P
G
N
D
D
I
S
A
B
L
E
V
P
W
R
S
G
N
D
V
d
d
P
G
N
D
R8
20K
R7
1K
R12
R14
C15
R29 R15
C14
C13
R28
R27
Microchip PIC18F2331
Microcontroller
SA305
3-Phase Brushless Motor IC
22
21
2
13
11
9
1
0
1
1
1
7
2
3
1
84 3
2
0 9 8
12
26
25
23
24
21
22
28
27
16
5
7
14
12
15
2
8,19
7,20
6
4
5
3
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Heat Sinking Refer to the SA305U datasheet for maxi-
mum power dissipation and power derating specifcations.
Heat sinking requirements can be determined based upon
the power calculations. If a heatsink is required, please refer
to the Apex Precision Power website for available options.
References 7 and 8 provide information on power dissipation
and thermal calculations. Incidentally, the DB62 demonstra-
tion board comes with an HS32 heatsink.
External Flyback Diodes In high current applications it is
recommended that external fyback diodes be connected as
shown in Figure 9. This is because the internal body diodes
cannot sustain high currents for long periods of time. Low
voltage drop, high current Schottky diodes, such as Interna-
tional Rectifer's part number 50SQ100, are recommended.
Bypass Capacitors The 1-F ceramic capacitors sup-
plied with the DB62 kit are for high frequency bypassing of
the V
S
and V
DD
supplies (C1, C11, C4 and C7 on the EVAL49
schematic). Two additional 100-F bypass capacitors are
provided with the kit for the V
S
supplies (C2 and C12 on the
EVAL49 schematic). Please refer to Application Note 30 for
guidelines on power supply terminal bypassing.
Hall Sensor Filters In order to make sure that the MCU
is receiving a clean signal from the Hall sensors enclosed
within the noisy motor environment, RC flters must be con-
nected in each of the three Hall sensor leads, as depicted in
Figure 8. A Schmitt trigger circuit can also be added to each
leg to provide additional noise immunity.
Resistors R12 and R27, in conjunction with capacitor C13
and the comparable components of the other two Hall diodes,
comprise low pass flters that can suppress the noise.
The values of these components will depend on the switch-
ing frequency of the PWM source and how fast the Hall
sensors respond. The flter time constant should be much
smaller than the rise times of the Hall sensors to make sure
that the switching of the sensors is not affected. Please refer
to Application Note 32.
Optional External RC Snubber Circuits (for high
switching noise scenarios) R13 and C5, R16 and C8, R19
and C10 in the EVAL49 schematic in DB62 can provide noise
immunity especially in high-load-current scenarios. With
the DB62 Evaluation Kit a 4.7 nanofarad, 100 volt capacitor
in series with a 50 ohm 5W resistor is provided for each OUT-
A, OUT-B and OUT-C line, and they should be connected in
series between the SA305 outputs and P
GND
. Depending on
the PWM frequency and the resistances and inductance of
the motor being driven, other values may be more effective.
The power dissipated in the snubber components can be
estimated by:
P = V
2
C(F
SW
) (3)
Where:
P = power dissipated
V = V
S
supply voltage
C = Snubber capacitor value
F
SW
= Switching frequency
4.1 OPEN AND CLOSED LOOP OPTIONS
The motor may be operated in an open-loop confguration
with a specifed speed reference. As depicted in Figure 10a,
a voltage can be applied to the V
DUC
input of the PIC18F2331
microcontroller that is set to a value that will maintain the
motor rotation at the required number of RPMs for the load
it is driving once the soft start algorithm has brought the
rotor up to full speed. Though not shown in Figure 10a, the
Hall sensors are still employed to make sure that the applied
rotating magnetic feld is always positioned so as to maximize
the torque applied to the rotor of the brushless motor.
However, this open-loop method of speed control is not
recommended. Instead, it is best that the motor be operated
in a closed-loop confguration as depicted in Figure 10b, for
reasons explained immediately below.
Closed-loop speed control is the preferred method for speed
control because the microcontroller is actually measuring
the true RPM based upon input from the Hall sensors and
minimizing the error from the speed reference using PID
control in real time. As shown in Figure 10b, the designer
needs to determine the voltage corresponding to the speed
and apply it to the A/D pin 2 or 3. (Employing Hall sensors
in closed-loop speed control confguration is also discussed
on page 12 of Reference 4.)
Closed-loop torque control is depicted in Figure 10c. The
outputs of the three current sense pins IMON_A, IMON_B
and IMON_C of the SA305 Driver IC are added as voltages in
an operational amplifer and then fed to one of the A/D inputs
pins 2 or 3 of the microcontroller. Note that the SA305 data
sheet (Reference 2) supplies the information as to the current
sense outputs. It is important to note that the current sense
ratios (I
LOAD
/I
SENSE
) are not the same for the three outputs. So
it is important to scale each of them properly by selecting the
appropriate summing resistors so as to obtain an output from
the op amp that is a true representation of the instantaneous
current fow to the brushless motor.
The two values within the microcontroller one receiving
the reference value of the torque and the other the measured
value obtained from the SA305 current sense outputs are
compared and applied to an PID control algorithm. This serves
to change the duty cycle of the PWM outputs as necessary, to
maintain a constant brushless motor torque. (This is discussed
in more detail on page 13 of Reference 4.) PIC controllers
are discussed in the Appendix of this document.
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SA305
3-Phase Brushless Motor Driver IC
Microcontroller
T
REF
TORQUE
REFERENCE
1
c. CLOSED LOOP TORQUE CONTROL
2
R33
R25 R24 R23
R32
R31
R30
I
M
O
N
_
A
I
M
O
N
_
C
I
M
O
N
_
B
V
DUC
SA305
Microcontroller
V
DUC
SPEED
REFERENCE
2
b. CLOSED LOOP SPEED CONTROL
5
6
4
HALL_A
HALL_C
HALL_B
HALL SENSORS
NOTE
T Networks have
been ommitted for clarity
SA305
Microcontroller
V
DUC
SPEED
REFERENCE
2
a. OPEN LOOP SPEED CONTROL
Figure 10. Open and Closed Loop Control Options
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5. APPENDIX
Proportional integral derivative controller A Proportional-
integral-derivative controller (PID controller) is a feedback loop
technique employed in control systems. It can be thought of
as an extreme form of a phase lead-lag compensator. A PID
controller has one pole at the origin and the other at infn-
ity
9
. It is used to compare a measured value with a reference
value. As employed in motor control the values may be either
speed or torque. The difference value is then employed to
calculate a new value to restore the value be it speed or
torque to the setpoint value. A PID loop produces accurate,
stable control in cases, whereas a simple proportional control
would be likely to induce a steady-state error or would induce
oscillation. Unlike more complicated control algorithms based
on optimal control theory, PID controllers do not require
advanced mathematics to develop a design.
A standard PID controller is also known as a "three-term"
controller and can be expressed in the parallel form by
Equation (4) or the "ideal form" by Equation (5):
(4)
(5)
Where:
K
P
is the proportional gain
K
I
the integral gain
K
D
the derivative gain
T
I
the integral time constant
T
D
the derivative time constant.
The proportional term provides an overall control re-
sponse that is proportional to the error signal through
the all-pass gain factor.
The integral term reduces steady-state errors through
low-frequency compensation by an integrator.
The derivative term improves the transient response
through high-frequency compensation by a differentiator.
The effects of each of these three terms on closed-loop
performance are summarized in Table 1.
G(s) = K
P
+ K
I
+ K
D
s
1
s
= K
P
(1+ + T
D
s)
1
T
I
s
6. REFERENCES
1. SA305 Pulse Width Modulation Amplifer Data Sheet, www.Cirrus.com
2. Motion Control Primer by David Palombo, www.aveox.com
3. Brushless DC Motor Fundamentals, AN885, www.microchip.com
4. Brushless DC Motor Control Using PIC18FXX31 MCUs, AN899, www.microchip.com
5. Sensored BLDC Motor Control Using dsPIC30F2010, AN957, www.microchip.com
6. DB62 Demonstration Board For SA305EX, www.Cirrus.com
7. Application Note 22, SOA (Safe Operating Area) and Load Lines, www.Cirrus.com
8. Application Note 11, Thermal Techniques, www.Cirrus.com
9. PID Control System Analysis, Design, and Technology, by Kiam Heong Ang, Gregory Chong and Yun Li, IEEE Transactions on Con-
trol Systems Technology, Vol. 13, No. 4, July 2005, pages 559 - 576
7. BIBLIOGRAPHY
"Modeling, Simulation, and Analysis of Permanent-Magnet Motor Drives, Part II: The Brushless DC Motor Drive" by Pragasen and Ramu
Krishnan, IEEE Transactions on Industry Applications, Vol. 25, No. 2, March/April 1989, pages 274-279
"A New Simulation Model of BLDC Motor with Real Back EMF Waveform" by Y.S. Jeon, H.S. Mok, G.H. Choe, D.K. Kim, J.S. Ryu, 7th
Workshop on Computers in Power Electronics, 2000; pages 217-220
Table 1. The Effects of Independent P, I and D Tuning
Closed-Loop
Response Rise Time Overshoot Settling Time
Steady-State
Error Stability
Increasing K
P
Decrease Increase Small Increase Decrease Degrade
Increasing K
I
Small Decrease Increase Increase Large Decrease Degrade
Increasing K
D
Small Decrease Decrease Decrease Minor Change Improve
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AN46 3-Phase Switching
Amplifer - SA306-IHZ
INTRODUCTION
The SA306-IHZ is a fully-integrated switching amplifer designed primarily to drive three-phase brushless DC
(BLDC) motors. Three independent half bridges, each comprising a P-FET and a N-FET in a confguration, provide
more than 15 A of PEAK output current under digital control. Thermal and short circuit monitoring is provided, which
generates fault signals for the microcontroller to take appropriate action. A block diagram of this IC is provided in
Figure 1.
Figure 1. Polarity is Easily Switched DC-to-DC converter, three terminal module can be switched from a posi-
tive to a negative converter by simply interchanging the jumpers identifed by Note 2.
DRIVING BRUSHLESS MOTORS
Brushless motors of the same horsepower as their brush counterparts are smaller and lighter. What is absent in the
former is the familiar brushcommutator arrangement that has been at the heart of single-phase DC brush motors
for more than a century. Because they lack this brush-commutator interface, brushless motors exhibit lower acous-
tic noise; are virtually maintenance free; and a brushless motor will exhibit a longer life cycle. As recently as 2004,
brushless motors were considered to be signifcantly more expensive than brush motors. At the time of this writing
in 2008, brushless motors have benefted from a decrease in cost so that today the price differential is as little as a
10% when shopped against an equivalent brush motor.
CYCLE-BY-CYCLE CURRENT LIMIT THE BENEFITS
Traditionally, in applications where the current fow to a brushless motor is not otherwise directly controlled, the in-
rush current had to be considered when selecting a proper driver amplifer. This is in addition to the average current
that will fow. As an example, a 1 A continuous motor might require a drive that can deliver well over 10 A PEAK in
order to deliver the initial inrush current that fows during startup. Many discrete motor drives use over-sized FETs
to withstand startup conditions which results in higher system costs and larger package sizes.
However with the unique and robust cycle-by-cycle current limit scheme designed into the SA306-IHZ, the inrush
current requirements of the motor are no longer an issue when selecting the drive. Current limit schemes inherently
reduce acceleration of the motor; however, the average current delivered by the SA306-IHZ during start up is higher
Gate
Control
Control
Logic
Brushless
Motor
V
S
+
V
S
-
SA306-IHZ Switching Amplifier
Out A
Out B
Out C
A
B
C
Vs (phase A)
PGND(A&B) PGND(C)
Vs (phase B&C)
Fault
Logic
Microcontroller
or
DSC
SC
Temp
I
LIM
/DIS1
Current Ia
Monitor Ib
Signals Ic
GND
DIS1
PWM
Signals
SGND
Sensing Circuits
Sensor Hall Sensors
or
SGND
At
Ab
Bt
Bb
Ct
Cb
3-Phase Switching Amplifier - SA306-IHZ
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than would be delivered by other current limit schemes. By using the SA306-IHZ, the motor will reach its operating
RPM faster. Thus the SA306-IHZ is able to safely and easily drive virtually any brushless motor which requires 5 A
continuously or less, through its startup interval without regard to what its in-rush requirements are. (Up to 8 A
continuously in the case of the SA306A-FHZ).
SA306-IHZ APPLICATIONS
The SA306-IHZ is designed primarily to drive three-phase motors. However, it can be used for any application
requiring three high current outputs. The signal set of the SA306-IHZ is designed specifcally to interface with a
DSP or microcontroller. A typical system block diagram is shown in Figure 1. As explained below, over-temperature,
short-circuit and current limit fault signals provide important feedback to the system controller that can safely disable
the output drivers in the presence of a fault condition. High-side current sensors monitor the output current of all
three phases, providing performance information that can be used to regulate or limit torque.
A SYSTEM OVERVIEW OF THE SA306-IHZ
With the introduction of the SA306-IHZ, designers now have an off-the-shelf solution for driving BLDC motors ver-
sus developing driver circuits by confguring three discrete gate drivers and six FETs. The performance specifca-
tions for the SA306-IHZ are unusual in that it can deliver over 15 A PEAK with up to 60 V applied to its FETs
1
.
Imparting Rotation Three independent DMOS FET half bridges provide the output current. In operation, as the
motor rotor revolves, the controller causes one motor terminal to be driven HIGH, a second LOW and the third to
FLOAT in a high impedance state, as depicted in Figure 2. This causes the magnetic feld to rotate in six steps per
electrical revolution in the simplest case, imparting rotation to the permanent magnets in the rotor. Proper synchro-
nization of this sequence is assured by the feedback from either Hall sensors or a sensorless control system that
keeps the microcontroller continuously informed of the position of the rotor with regard to the stator windings.
Figure 2. Imparting Rotation By monitoring the Hall sensors or by monitoring Back EMF in a sensorless con-
fguration the stator winding felds can be made to rotate so that the resultant feld of the two energized stator
windings and the pole of the permanent magnet rotor remain at right angles, thereby maximizing the instantaneous
torque.
Shoot-Through Protection The shoot-through protection feature of this IC identifes the state in which both the
upper and lower portions of a half bridge are ON at the same time. Shoot through must be avoided, for if it were to
occur, it would short the supply to ground, overload the circuit and destroy the FETs. Consequently, a dead time
is programmed to allow a FET to turn fully off before its companion FET is turned on. During dead time, inductive
winding currents continue to fow, or commutate, through internal or external reverse biased diodes. Fault status
COM
N
S
COM
N
S
COM
N
S
COM
N
S
COM
N
S
COM
Low
High
Float
N
S
Float
High
Low
High
Float
Low
High
Low
Float Float
Low
High High
Float
Low
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indication and current level monitors are provided directly to the controller. Output currents are measured using an
innovative low-loss technique discussed in a later section. The SA306-IHZ also offers superior thermal performance
with a fexible footprint.
Controlling Brushless Motor Drivers Most brushless motor drivers are controlled by microcontrollers or some
other intelligent system. A number of manufacturers including Analog Devices, Freescale, Microchip and Texas In-
struments market microcontrollers for motion control and more specifcally for driving brushless motors.
Choosing a Brushless Motor Although there are a number of sources for assistance in choosing a motor, brush-
less or otherwise, a good starting point is Reference 2. As the author points out, choosing a motor requires looking
at a whole list of issues including effciency, torque, power reliability and cost.
What can be said categorically is that a brushless permanent magnet motor is the highest performing motor in terms
of torque versus effciency. Also all three stator windings can be controlled which is not the case in a traditional DC
motor where commutation relies on brushes.
SENSOR VERSUS SENSORLESS COMMUTATION
Hall Sensors are not required in sensorless commutation. Instead the instantaneous position of the rotor relative to
the stator is determined by the Back EMF (BEMF) developed in the stator windings. The absence of both the Hall
Sensors and the attendant wiring lowers the motors cost and increases reliability, though deriving the lost informa-
tion from the BEMF requires somewhat more complex control. This approach is attractive in applications such as
refrigeration or HVAC systems which generate heat that could accelerate failures of the Hall Sensors.
On the other hand, starting presents a problem in sensorless commutation simply because there is no BEMF when
the motor is at rest. Secondly, abrupt changes in the motor load can cause a BEMF drive loop to go out of synchro-
nization. Central to both sensorless- and sensor-based control systems is the presence of pulse width modulation
(PWM) which is discussed in the Appendix.
CYCLE BY CYCLE CURRENT LIMITING THE FUNDAMENTALS
and the in-rush current must be considered when selecting a proper drive. For example, a motor that requires 1 A
when running at constant speed, might require a drive that can deliver well over 10 A PEAK in order to survive the
inrush condition at startup. But as this discussion will make clear, this is not the case when using the SA306-IHZ.
Depicted in Figure 3a is the behavior in a traditional motor where there is no cycle-by-cycle current limit. (This is
discussed in more detail in the Appendix)
In this case, when the rotor is not turning (no BEMF), the current is limited only by the resistance of the rotor of the
motor plus any series resistance that may be present. As the motor accelerates, the back EMF builds up, gradually
reducing the current so that it diminishes to the steady-state current.
Figure 3 illustrates motor behavior when cycle-by-cycle current limit is applied at start-up. In this case, the current is
limited by circuitry within the SA306-IHZ not by the impedance of the rotor. As the motor reaches its steady-state
speed, the current tails off.
Figure 3. Motor Current Behavior at Startup (a) Without cycle-by-cycle current limit. (b) With cycle-by-cycle
current limit.
Time -milliseconds
Non-limited back EMF
Non-limited motor current
C
u
r
r
e
n
t

-

A
m
p
e
r
e
s
(a)
Time - Milliseconds
Limited back EMF
Limited motor current
C
u
r
r
e
n
t

-

A
m
p
e
r
e
s
(b)
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CYCLE-BY-CYCLE CURRENT LIMIT BEHAVIOR
Shown along the top of Figure 4 is the cycle-by-cycle behavior of the PWM pulse train applied to the SA306-IHZ by
the microcontroller. The motor current is shown in blue at the bottom of the illustration. Outlined in red, and superim-
posed over the current waveform, is the actual PWM pulse train (PWM output) delivered by the FETs which has, in
effect, been modulated by the current fow. It shuts off the output pulse should the current exceed the current limit
set externally by the user.
1st Pulse In the case of the 1st PWM pulse, no current limiting occurs because the pulse ends before the rising
current reaches the current limit threshold. At the end of the 1st pulse there is a short decay before the PWM pulse
turns on once more and the current resumes its rise. Note that because current cannot change instantaneously in
an inductive reactance, which is, in fact, what the rotor of the brushless motor is, the current value, unlike the PWM
voltage, is always continuous.
2nd Pulse In the case of the second PWM pulse, the current reaches the limit value before the PWM input pulse
ends. Consequently, the PWM output pulse is shut off early in its cycle. Then the motor current decays until the third
pulse is applied which once again causes the current to rise.
Subsequent pulses The behavior just described continues until the back EMF rises to the point where the current
falls below the current limit threshold. This occurs as the motor approaches its operating speed and the current de-
scends to its steady state value, as depicted in Figure 3b. The ratio of the peak-to-average motor current depends
on the inductance of the motor winding, the back EMF developed in the motor, mechanical loading of the systems
and the width of the pulse.
Figure 4. Cycle by Cycle Current Limit
Time (milliseconds)
PWM input
Motor current
PWM output
V
o
l
t
a
g
e
Current
Limit
1 2 3
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CONTROL AND SENSE ARCHITECTURE
As depicted in Figure 5, the output current of the upper output FET U14 for OUT A is continually measured, (The
same occurs for the corresponding output FETs for OUT B and OUT C). The output of the current sense circuit is
applied to a current mirror comprising U1, U2 and U3 which develops a voltage across the external current limit
resistor. This voltage is compared with the current limit threshold by Comparator U6.
Figure 5. Control and Sense Architecture
Disabling Circuitry If the voltage applied to the plus terminal of comparator U6 exceeds the current limit threshold
voltage (Vth), all three outputs OUT A, OUT B and OUT C are disabled. The disabling path is via gates U7 and U8
and gates U12 and U13. Once the voltage applied to Comparator U6 falls below the Vth threshold voltage, and the
disabled top side input to the gate control goes low, the output stage will return to an active state on the rising edge
of any top side input command signal (At, Bt, or Ct). Note that the corresponding disable signals from phases B and
C are also applied via gate U7 and their behavior is exactly the same as is the case for OUT A. Also the ILIM/DIS1
goes HIGH when any of the three current sense circuits detects an overcurrent situation. The cycle-by-cycle current
limit feature of the SA306-IHZ will reset each PWM cycle. Thus the PEAK current is limited in each phase during
each PWM cycle, as illustrated in Figure 4. Notice also that the moment at which the current sense signal exceeds
the Vth threshold is asynchronous with respect to the input PWM signal because this event is governed by the inter-
section of the rising current with the current limit not the PWM duty cycle. The difference between the PWM period
and the motor winding L/R time constant will often result in an audible beat frequency sometimes called a sub-cycle
oscillation. This oscillation can be viewed with an oscilloscope by applying a probe to pin 7, I
LIM
/DIS1.
Undervoltage Lockout See Table 1 and Page 7.
Limitations at High and Low Speeds Input signals applied to the PWM and commanding a 0%- or a 100%-duty
cycle, may be incompatible with the current limit feature due to the absence of rising edges of At, Bt, and Ct except
at instances when the rotation of the motor requires the output FETs to change states. At high motor speeds, this
may result in poor performance and signifcantly increased torque ripple. Whereas at low motor speeds the motor
may stall if the current limit trips and the motor current reaches zero without a commutation edge that would change
the state of the output FETs and normally reset the current limit latch.
SGND
Gate
Control
Vs
OUT A
PGND
At
Ab
Sc
TEMP
SC
Logic
Temp
Sense
Ref
Ia
DIS2
I
LIM
/DIS1
UVLO
Ia'
+
_
Lim b
Lim c
+
_
Vdd
Lim a
Current
Sense
12k
12k
12k
12k
Vth
U1 U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
R
LIM
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Disabling Cycle-by-Cycle Current Limit The current limit feature may be disabled by pulling the I
LIM
/DIS1 pin to
GND. The current sense circuitry identifed in Figure 5, will continue to provide top FET output current information.
External Current Control Options Typically the current sense pins source current into grounded resistors which
provide voltages to the current limit comparators, as shown in Figure 1. If instead the current limit resistors are
connected to a voltage output DAC, the current limit can be controlled dynamically by the system controller. This
technique essentially reduces the current limit threshold voltage to (Vth-VDAC). During expected conditions of high
torque demand, such as start-up or reversal, the DAC can adjust the current limit dynamically to allow periods of
high current. In normal operation when a low current is expected, the DAC output voltage can increase, reducing the
current limit setting to provide more conservative fault protection. This is discussed in detail under Current Sense
An Advantage.
Three Degrees of Freedom The applied voltage, the switching frequency and the PWM duty cycle are three cru-
cial parameters that can be programmed independently. How these variables are selected will affect the behavior of
the motor with regard to how fast it will accelerate, and consequently how fast its speed and torque will rise.
CONTROL AND SENSE PINS
A summary of the control and sense pins, and their functions, is supplied in Table 1.
Table 1. Control and Sense Features
Nomenclature Pin # Function Description Remarks
DIS2 23 Control
When a HIGH is applied to this
Schmitt triggered logic level, it plac-
es OUT A, OUT B, and OUT C in a
high impedance state.
Pin DIS2 (23) has an internal
12k pull-down resistor connect-
ed to ground and therefore may
be left unconnected. (See Figure
5.)
I
LIM
/DIS1 7 Control/Sense
Control: Pulling this pin to logic
HIGH places OUT A, OUT B, and
OUT C in a high impedance state.
Pulling this pin to a logic LOW ef-
fectively disables the cycle-by-cycle
current limit feature.
Sense: This pin is also connected
internally to the output of the current
limit latch through a 12k resistor
and can be monitored to observe
the function of the cycle-by-cycle
current limit feature.
SC 3 Sense
Goes HIGH if a short circuit is de-
tected or an output occurs that is
not in accordance with the input
commands,
The SC signal is blanked for ap-
proximately 200 ns during switch-
ing transitions but in high current
applications, short glitches may
appear on the SC pin. A high
state on the SC output will not
automatically disable the device.
The SC pin includes an internal
12k series resistor, as shown in
Figure 5.
TEMP 25 Sense
Goes HIGH if the SA306 die tem-
perature reaches approximately
135C.
This pin WILL NOT automatically
disable the device. The TEMP pin
includes a 12k series resistor.
See Figure 5.
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Nomenclature Pin # Function Description Remarks
UVLO (Under-
voltage Lock
Out)
None Control/Sense
Disables all output FETs until V
S
is
above the UVLO threshold voltage
which is typically 8.3 V.
See discussion in Section 3.4.
Vth None Control
If the voltage of any of the three cur-
rent sense pins exceeds the current
limit threshold voltage (Vth),which is
typically 3.75 volts, all outputs are
disabled. After all current sense pins
fall below the Vth threshold voltage
and the offending phases top side
input goes low, the output stage will
return to an active state on the ris-
ing edge of ANY top side input com-
mand signal (At, Bt, or Ct).
FAULT INDICATIONS
In the case of either an over-temperature or short-circuit fault, the SA306-IHZ will take no action to disable the
outputs. However, the SC and TEMP signals can be fed to an external controller, as depicted in Figure 6, where a
determination can be made regarding the appropriate course of action. In most cases, the SC pin would be con-
nected to a FAULT input on the processor, which would immediately disable its PWM outputs. The TEMP fault does
not require such an immediate response, and would typically be connected to a GPIO, or Keyboard Interrupt pin
of the processor. In this case, the processor would recognize the condition as an external interrupt, which could be
processed in software via an Interrupt Service Routine. The processor could optionally bring all inputs low, or assert
a high level to either of the disable inputs on the SA306-IHZ. Figure 6 depicts an external SR fip-fop which provides
a hard wired shutdown of all outputs in response to a fault indication. An SC or TEMP fault sets the latch, pulling the
DIS2 pin HIGH. The processor clears the latched condition with a GPIO. This circuit can be used in safety critical
applications to remove software from the fault-shutdown loop, or simply to reduce processor overhead. In applica-
tions which may not have available GPIO, the TEMP pin may be externally connected to the adjacent I
LIM
/DIS1 pin.
If the device temperature reaches ~135C all outputs will be disabled, de-energizing the motor. The SA306-IHZ will
re-energize the motor when the device temperature falls below approximately 95C. The TEMP pin hysteresis is
wide to reduce the likelihood of thermal oscillations that can greatly reduce the life of the device.
Figure 6. External Latch Circuit
Gate
Control
Control
Logic
A
B
C
Fault
Logic
Microcontroller
or
DSC
SC
Latched Fault
TEMP
Fault Reset
Interrupt
GPIO
DIS2
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UNDER-VOLTAGE LOCKOUT
Without suffcient supply voltage, the SA306-IHZ control circuit cannot suffciently drive the gates of the output
FETs. The undervoltage lockout condition results in the SA306-IHZ unilaterally disabling all output FETs until V
S
is above the UVLO threshold indicated in the specifcation table in the Data Sheet
1
. There is no external signal
indicating that an undervoltage lock-out condition is in progress. The SA306-IHZ has two V
S
connections: one for
phase A, and another for phases B & C. The supply voltages on these pins need not be the same, but the UVLO
will engage if either is below the threshold. Hysteresis on the UVLO circuit prevents oscillations with typical power
supply variations.
CURRENT SENSE AN ALTERNATIVE
External power shunt resistors are not required with the SA306-IHZ. Forward current in each top, P-channel output
FET is measured and mirrored to the respective current sense output pin, Ia, Ib and Ic, as depicted in Figures 1 and
5. By connecting a resistor between each current sense pin and a reference, such as ground, a voltage develops
across the resistor that is proportional to the output current for that phase. As an alternative the currents Ia, Ib,
and Ic can be fed to a single resistor and the voltage developed monitored by a high-impedance A/D converter, as
shown in Figure 7.
As depicted in the Current Sense plot on page 4 of the SA306-IHZ product data sheet, the maximum current per
phase is slightly less than 2 milliamperes. Consequently, choose a resistor that will develop the voltage appropriate
for the A/D Converter chosen. The full scale voltage will be the voltage developed across the resistor by the sum of
the three currents 6 milliamperes. Also allow a headroom of approximately 0.5 V.
Figure 7. Current Monitoring Circuit
EXTERNAL FLYBACK DIODES
External fy-back diodes (D1 through D6), depicted in Figure 8, will offer superior reverse recovery characteristics
and lower forward voltage drop than the internal back-body diodes. In high current applications, external fyback
diodes can reduce power dissipation and heating during commutation of the motor current. Reverse recovery time
and capacitance are the most important parameters to consider when selecting these diodes. Ultra-fast rectifers
offer better reverse recovery time and Schottky diodes typically have low capacitance. Individual application re-
quirements will be the guide when determining the need for these diodes and for selecting the component which is
most suitable.
SA306-IHZ
Brushless Motor Driver
A
B
C
Microcontroller
High Impedance
A/D Module R*
* See discussion in the text.
Ia Ic Ib
21 1 5
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Figure 8. Three-Phase Motor Drive Circuit
A SPECIFIC EXAMPLE
Begin by choosing a motor that will exhibit the mechanical performance required which is to say the torque, the
effciency, and other issues that will fulfll the motor drive requirements of your system. We have chosen as our
example a low-inertia, brushless motor that delivers 557 mNm of torque at 2000 rpm. We selected a Maxon EC
Flat motor www.maxonmotor.com. The characteristics of the windings of this motor are that any stator-winding pair
exhibits a resistance (Rm) of 2.3 ohms and an inductance (Lm) of 2.5 millihenries. The torque constant (Kt) of the
motor is 217 mMm oz-in/A.
DEMONSTRATION BOARD FOR THE SA306-IHZ
It is recommended that the designer acquire the DB64 Demonstration Board
3
and assemble a prototype. In the
DB64 the SA306-IHZ input PWM control is achieved by means of a Texas Instrument on-board UCC3626 PW
microcontroller
4
. The DB64 is designed to demonstrate the capabilities of the SA306-IHZ as a 3-phase brushless
DC motor driver IC. From there one can easily convert the circuit developed with the DB64 Demonstration Board
into a circuit similar to the one shown in Figure 8 which can serve as the base circuit for a production version.
GND
VREF
TACH-OUT
R-TACH
C-TACH
CT
SYNCH
-IN
SNS_NI
SNS_I
I-OUT
OC-REF
PWM_I
PWM_NI
TI
Motor Controller
UCC3626
VDD
AHI
ALOW
BHI
BLOW
CHI
CLOW
DIR_IN
QUAD
BRAKE
COAST
HALLC
HALLB
HALLA
SA306-IHZ
3 Phase Switching
Amplifier
OUT C
V
DD
PGND C
PGND A & B
OUT A
V
S
B&C
V
S
A
OUT B
At
Bt
Bb
Ct
CHI
Cb
HS HS
I
LIM
/DIS1
57
56
55
53
52
51
49
48
47
46
35
34
33
40
39
38
37
31
30
29
44
43
42
D1
D2
U1
D3
C3 C4 C6
D4
D5
C2 C5
+VS
61
63
13
11
15
17
Hall
Sensors
19 58 59
7
D6
C16
U3
2 3 6 7
C1
8 1
+12V
+5V
R4 R5
R3
R1
R2
0 1 C 1 1 C C9
+5V
-Vs
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C8
U2
P
g
n
d
S
g
n
d
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+12V
C7
+5V
DIR_IN
I
LIM
/DIS1
C14
R8
+12V
Speed
Control
LM78L05
R6
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A simple two-layer printed circuit board construction is suffcient because of the convenient pinout of the SA306-IHZ
PowerQuad package. Input signals are routed into one side of the SA306-IHZ package and high-power output sig-
nals are routed from the other side in 2 ounce copper. This eliminates the need to route control signals near motor
connections where noise might corrupt the signals. Filling top and bottom layers with copper reduces inductive cou-
pling from the high current outputs. Use 1 nF capacitors with excellent high frequency characteristics to bypass the
V
S
motor supplies at each phase as well as switching grade electrolytic capacitors. The six 100 V Schottky diodes
(D1 D6) conduct the commutation current via low forward voltage paths which reduces the power dissipation in
the SA306-IHZ. These diodes are rated for 5 A continuous. Mount them close to the SA306-IHZ to reduce induc-
tance in the commutating current loop. For applications with continuous currents less than 5 A, the Schottky diodes
may not be necessary, but one must consider the higher forward voltage internal body diodes and the associated
power dissipation that results.
Output Traces Output traces carry signals with very high dV/dt and dI/dt. Proper routing and adequate power
supply bypassing ensures normal operation. Poor routing and bypassing can cause erratic and low effciency op-
eration as well as ringing at the outputs.
Bypassing The V
S
supply should be bypassed with a surface mount ceramic capacitor mounted as close as
possible to the V
S
S
and GND pins must be kept to
a minimum to prevent noise from contaminating the logic control signals. A low ESR capacitor of at least 25 F per
ampere of output current should be placed near the SA306-IHZ as well. Capacitor types rated for switching applica-
tions are the only types that should be considered. Note that phases B & C share a V
S
connection and the bypass
recommendation should refect the sum of B & C phase current. The bypassing requirements of the V
DD
supply are
less stringent, but still necessary. A 0.1 F to 0.47 F surface mount ceramic capacitor (X7R or NPO) connected
directly to the V
DD
pin is suffcient.
Ground Connections and Ground Planes S
GND
and P
GND
pins are connected internally. However, these pins
must be connected externally in such a way that there is no motor current fowing in the logic and signal ground
traces as parasitic resistances in the small signal routing can develop suffcient voltage drops to erroneously trig-
ger input transitions. Alternatively, a ground plane may be separated into power and logic sections connected by
a pair of back-to-back Schottky diodes. This isolates noise between signal and power ground traces and prevents
high currents from passing between the plane sections. Unused area on the top and bottom PCB planes should be
flled with solid or hatched copper to minimize inductive coupling between signals. The copper fll may be left uncon-
nected, although a ground plane is recommended.
Table 2. Parts List for Figure 7
Reference
Designation Description
R1, R2, R3 470
R4, R5, R6 1 k
R8 20 k potentiometer (to control the PWM duty cycle)
R9, R10, R14, R15, R16, R17 5 k
C1, C7, C8 1 F
C2, C3, C4, C5, C6 1 nF
C9, C10, C11 2.2 nF
C14, C16 0.1 F
D1, D2, D3, D4, D5, D6 PDS5100
U1 Apex Precision Power SA306-IHZ or SA306A-FHZ
U2 Texas Instrument UCC3626
U3 LM78L05
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POWER DISSIPATION
The thermally-enhanced package of the SA306-IHZ allows for several options for managing the power dissipated
in the three output stages. Power dissipation in traditional PWM applications is a combination of output power dis-
sipation and switching losses. Output power dissipation depends on the quadrant of operation and whether external
fyback diodes are used to carry the reverse or commutating currents.
Switching losses are dependent on the frequency of the PWM cycle as described in the typical performance graphs.
The size and orientation of the heatsink must be selected to manage the average power dissipation of the SA306-
IHZ. Applications vary widely and various thermal techniques are available to match the required performance.
The patent pending mounting technique shown in Figure 9, with the SA306-IHZ inverted and suspended through a
cutout in the PCB, is adequate for power dissipation up to 17 W with the HS33 (a 1.5-inch long aluminum extrusion
with four fns). In free air, mounting the PCB perpendicular to the ground, so that the heated air fows upward along
the channels of the fns can provide a total
J -A
of less than 14 C/W (9 W max average PD). Mounting the PCB
parallel to the ground impedes the fow of heated air and provides a
J -A
of 16.66 C/W (7.5 W max average PD).
For applications in which higher power dissipation is expected or lower junction or case temperatures are required,
a larger heatsink or circulated air can signifcantly improve the performance. Also see References 5 and 6.
Figure 9. HS33 Heatsink
Appendix
A Brief Overview of PWM
The frst pulse width modulation (PWM) ICs appeared on the market some 40 years ago. So the concept of PWM
is at least as old. Though the earliest applications were in switching power supplies, it was not much later that the
technique was frst employed to drive brushless motors. The principal beneft of PWM as a control technique be-
comes clear by examining Figure A1. The traditional linear power delivery technique for limiting power simply em-
ploys a variable resistance as depicted in Figure A1(a). When maximum output is commanded, the driver reduces
resistance of the pass element to a minimum. At this output level, losses in the linear circuit are relatively low. When
zero output is commanded the pass element resistance again approaches infnity and losses again approach zero.
However, the disadvantage of the linear circuit becomes clear in the midrange when the output level is in the vicin-
ity of 50%. At these levels the resistance of the pass element is equal to the load resistance which means the heat
generated in the amplifer is equal to the power delivered to the load! In other words, a linear control circuit exhibits
a worst case effciency of 50% when driving resistive loads at midrange power levels. Whats more, when the load
is reactive, this effciency drops even further.
Patent Pending
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Figure A1. PWM versus Linear Control PWM control in (b) exhibits far lower losses than
the traditional linear control technique in (a)
Now consider PWM operation as depicted in fgure A1(b). In a PWM control system an analog input level is con-
verted into a variable-duty-cycle switch drive signal, The process of switching from one electrical state to another,
which in this case is simply between OFF and ON, is called modulation, which accounts for why this technique is
called pulse width modulation. Beginning at zero duty cycle, which is to say OFF all the time, the duty cycle is often
advanced as the motor begins to rotate, until it is running at the speed and/or the torque required by the applica-
tion. In the case of a PWM control circuit, the rather negligible losses are primarily due to the ON resistance of the
switching FET and the fyback diode which is why effciencies as high as 80% to 95% are routine. However, at high
switching frequencies the energy required to turn the FETs on and off can become signifcant.
Figure A2. Linear versus PWM Current behavior with a steady-state excitation in (a);
Current behavior with PWM excitation in (b)
Pulse width control
Linear control
(a)
V
S
Driver
Load
Pass element
95%
50%
5%
On
(b)
Off
Off
Off
V
t
t
V
t
V
On
On
Off On On
V
t t
V
On
I
max. I =
V
R
V
R
Rt
L
I =
(
1 - e
)
I

(
a
m
p
e
r
e
s
)
t
(a)
I =
V
R
I
off
t
off
(b)
-
V
R
Rt
L
I =
(
1 - e
)
-
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In addition to enhanced effciency, PWM can play additional roles which include limiting the start-up current, control-
ling speed and controlling torque. The optimum switching frequency will depend on inertia and inductance of the
brushless motor chosen and the application. The choice of the switching frequency affects both losses and the mag-
nitude of the ripple current. A good rule of thumb is that raising the switching frequency increases the PWM losses.
On the other hand, lowering the switching frequency limits the bandwidth of the system and can raise the heights of
the ripple current pulses to the point that they become destructive or shut down the brushless motor driver IC. The
ripple current pulses are depicted in Figure A2(a) and are discussed below.
BRUSHLESS MOTOR BEHAVIOR AN OVERVIEW
One of the most critical moments with regard to a brushless motor also true for a motor with brushes is when
power is frst applied while the motor is at rest. At this time the rotor is stationary and is delivering no back EMF
(V
BEMF
). V
BEMF
can be expressed as:
V
BEMF
= (K
b
)(Speed) (Equation1)
Where: K
b
= voltage constant (volts/1000 RPM)
Speed = revolutions per minute (expressed in thousands)
Once a voltage is applied to the motor, the rotor begins turning, generating a V
BEMF
governed by (Equation 1).
Ignore for the moment that the plan is to drive the motor with a PWM source, and assume the motor is driven by a
steady-state voltage, then we can express the current by this equation:
I = [(V-V
BEMF
)/R
m
][1-e
-Rmt/Lm
] (Equation 2)
Where: V = the applied voltage
V
BEMF
= back EMF
R
m
= stator resistance (winding pair)
L
m
= stator inductance (winding pair)
Note that in (Equation 2), the current (I) at any moment is a function of both the back EMF (V
EMF
) and the time (t).
The current when the motor is stopped (V
BEMF
= 0) is illustrated in Figure A2(a) and is a familiar waveform for char-
acterizing the current in any L-R circuit with its rise time governed by the time constant L/R.
Now lets exchange the steady-state excitation voltage for a PWM source, as shown in Figure A2(b). The current
rises until the frst ON pulse ends; when the voltage abruptly falls to zero at the end of the frst applied voltage pulse,
the current begins to decay towards zero. However, the next pulse will again drive the current upwards, and so
forth, so that the current continues to rise. As the motor accelerates, the current waveform will exhibit a sawtooth
profle. This sawtooth characteristic is also known as ripple. Because torque is directly proportional to current, the
sequence of rising current pulses drive the motor, which develops a corresponding torque that accelerates the
motor. But this is not so in the case of cycle-by-cycle current limit. Because in this case the current rise ceases im-
mediately if the current reaches the limit value during any PWM pulse interval.
REFERENCES
1. SA306-IHZ Pulse Width Modulation Amplifer Data Sheet, www.cirrus.com
2. Motion Control Primer by David Palombo, www.aveox.com
3. DB64 Demonstration Board For SA306EX, www.cirrus.com
4. UCC2626, UCC3626 Brushless DC Motor Controller, www.ti.com
5. Application Note 22, SOA (Safe Operating Area) and Load Lines, www.cirrus.com
6. Application Note 11, Thermal Techniques, www.cirrus.com
BIBLIOGRAPHY
Modeling, Simulation, and Analysis of Permanent-Magnet Motor Drives, Part II: The Brushless DC Motor Drive by
Pragasen and Ramu Krishnan, IEEE Transactions on Industry Applications, Vol. 25, No. 2, March/April 1989, pages
274-279
A New Simulation Model of BLDC Motor with Real Back EMF Waveform by Y.S. Jeon, H.S. Mok, G.H. Choe, D.K.
Kim, J.S. Ryu, 7th Workshop on Computers in Power Electronics, 2000; pages 217-220
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AN47 Techniques for Stabilizing
1.0 INTRODUCTION
It is unlikely that a power op amp would always be employed to drive a purely resistive load. For if that were the
case, stability would never become a problem. On the other hand, a load which is largely capacitive does present
stability issues as will become clear in this Application Note. In a pure capacitor, the voltage lags the charging cur-
rent by 90 degrees, so there is a large phase delay in the loop response of a feedback circuit. Such a phase delay
can be a signifcant contributor to instability.
Let's get started by considering any multistage amplifer. It will begin to exhibit a roll off in open loop gain (A
OL
), as
well as an increase in phase delay at higher frequencies because of the low-pass flters that are formed by nodes
with fnite source impedances driving capacitive loads within the amplifer stage
1
. So a load that is largely capacitive,
together with the capacitance within a multistage amplifer, can bring about instability since the phase lag may be
approaching, and perhaps exceed 180 degrees. It is this phase delay that is a key contributor to instability. When
instability occurs, it can transform a power amplifer into an oscillator, inadvertently, and the device is likely to be-
come quite hot and fail in as little as one second.
In the discussion that follows, there are some simple techniques for managing phase and gain relationships to
maintain a stable circuit.
1.1 LOOP STABILITY VERSUS NON-LOOP STABILITY
In this Application Note we discuss Loop Stability. Whereas 'Non-Loop Stability' that denotes issues such as lay-
out, power-supply bypassing and proper grounding are discussed in Reference 2. In this Application Note we will
examine:
Why capacitive loads create stability problems in standard op amp circuits.
Closed loop gain (1/) and open loop gain (AOL) and their relationships to stability.
How capacitors impact the open loop gain (AOL) curve
Three ways to adjust the closed loop gain (1) and the open loop gain (AOL) responses to regain phase mar-
gin and stability, along with the advantages and disadvantages of each technique.
Unstable Stable
100
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40
60
80
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OL
1/
1
1/
2
Techniques for Stabilizing Power Operational Amplifiers
MAY 2009
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Figure 1. Stable or Unstable? As we explain in this Application Note, modifying the closed
loop gain (1/) is one of several effective ways of achieving stable operation.
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o
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A

(
D
b
)
Log F
-3.01 dB
A Bode Plot
2fRC =much smaller than 1
Corner
Frequency
2fRC =much larger than 1
R
V
OUT
(t)
V
IN
(t)
C
1
(1 +j2fRC)
1
j2fC
1
j2fC
V
OUT
(t) = V
IN
(t)
V
OUT
(t) = V
IN
(t) f =
= Corner Frequency or Pole
1
2RC
+R
Bode Plots in a nutshell
A Bode Plot of a power amplifer open loop gain (A
OL
) response is usually a graph of the log of the magnitude
plotted as a function of the log of the frequency, as depicted below. The magnitude axis is usually expressed
in decibels. This transforms multiplication into a matter of simply adding vertical distances on the plot.
With this examination of the multistage amplifer, as discussed in Section 1.0, the open loop gain (A
OL
) re-
sponse is comparable to a single-pole low pass flter, as depicted in Figure 1.
The Bode Plot of amplitude can be approximated by straight lines, as shown at the lower right. Note that as
the straight-line approximation approaches the corner frequency the true value, shown by the dotted line,
departs from the straight-line approximation and is actually 3.01 dB below the junction of the two intersecting
straight line segments.
Note that for corner frequencies much lower than 1, the approximation is a straight line which covers the por-
tion where the capacitive reactance is large. For frequencies much larger than the corner frequency the curve
is approximated by the straight line descending at rate of 20 dB per decade. This is due to the diminishing
capacitance reactance at higher frequencies.
One could also prepare a Bode Plot for the log of the phase relationship between the input and output, but this
is dispensed with for the analysis employed in this Application Note.
Op amps often exhibit more than one pole in their open loop gain (A
OL
) Bode Plots.
Note that at the frst corner frequency or pole there is a 90-degree phase shift. If there is a second pole the
phase shift becomes 180 degrees above that frequency.
2.0 EVOLUTION OF AN OPERATIONAL AMPLIFIER
Reviewing the evolution of an op amp is useful because it aids the understanding of the stability techniques.
This example begins with an open loop amplifer (A
OL
), with a gain as depicted in Figure 2(a).
So the open loop gain is simply:
V
OUT
=A
OL
V
IN
(1)
Then add a summing point at the input as shown in Figure 2(b).
To convert the open loop amplifer into an operational amplifer we feed back a portion of the output which is V
OUT
,
as shown in Figure 2(c). Then label the inputs and outputs so that the equation for V
OUT
can be written by inspection:
V
OUT
=A
OL
(V
IN
V
OUT
) (2)
or:
V
OUT
(1 + A
OL
) = A
OL
V
IN

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A
OL
A
OL
A
OL
V
IN
V
OUT
(a)
V
IN
V
OUT
(b)
Summing
Point
V
IN
V
OUT
(c)
V
IN
- V
OUT
V
OUT
A
OL
(V
IN
- V
OUT
)
+
so that the closed loop gain A

CL
is :
V
OUT
V
IN
A
OL
1 + A
OL
A
CL
= = (3)
Because A
OL
is large compared with 1 therefore A
OL
will also be
large compared with 1. Then the denominator 1 + A
OL
is equal,
approximately, to A
OL
and equation (3) becomes simply:
A
CL
1/ Closed loop gain (4)
Key relationships . . .
A
OL
= Open Loop Gain
1/ = Closed Loop Gain
A
OL
1/ = Loop Gain the signal propagating around
the loop and available to reduce errors and
non-linearities.
2.1 A CLOSER LOOK AT
Beta () is the fraction of the output that is fed back to the input.
In Figure 3(a) it is thereby given as:
R
1
R
1
+ R
F
V
FB
= V
OUT
(5)
V
FB
= V
OUT
(6)
Where:
R
1
R
1
+ R
F
=
Or the non-inverting closed loop gain 1/ is:
R
1
+ R
F
R
1
= = 1 +
1
R
F
R
1
(7)

(Keep in mind that the current fowing into the two inputs is virtually zero.) If comprises solely resistors R
I
and R
F

then the closed loop gain (1/) line will plot as a horizontal straight line on a bode plot.
This is depicted in Figure 1 in which the 1/
1
and 1/
2
lines, which are the closed loop small signal gains, are de-
picted as a constant and frequency independent.
However, if Z
I
and Z
F
are capacitors or inductors or some combination of capacitors, inductors and resistors then
Z
I
and Z
F
are functions of frequency:
Z
I
(f)
Z
I
(f) + Z
F
(f)
V
FB
= V
OUT

(8)
This means the Closed loop gain (1/) line does not plot as a straight line on a bode plot.
2.2 HOW AN OP AMP BEHAVES AS THE SIGNAL FREQUENCY RISES
This section depicts the fact that if there is a critical frequency (F
CL
) at which the loop gain (A
OL
- 1/) becomes zero,
then the operational amplifer simply degenerates into an open loop amplifer with an open loop gain of A
OL
. If that
occurs the amplifer no longer behaves as an operational amplifer and its benefts simply vanish.
This is depicted in Figure 4 in which the closed loop (1/) line is a constant which means the components of are
independent of the frequency or purely resistive. Note how the 1/ value subtracts from the open loop gain (A
OL
)
at low frequencie. But once the A
OL
line reaches the frequency F
CL
, the loop gain (A
OL
- 1/) becomes zero. So for
frequencies above F
CL
, the op amp becomes an open loop amplifer with a gain of A
OL
.
Is the power amplifer unstable? That depends on the phase relationship between the input and output for the ampli-
fer for frequencies of F
CL
and above, as discussed in Section 2.3 that follows.
Figure 2. Evolution of an Op Amp
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I
R
F
V
FB
V
OUT
V
IN
(a)
V
OUT
(b)
V
FB
V
IN
Z
I
(f)
Z
F
(f)
A
O
L

-

1
/
A
O
L

-

1
/
A
O
L

-

1
/
A
O
L

-

1
/
A
O
L

-

1
/
A
O
L

-

1
/
A
O
L

-

1
/
A
O
L

-

1
/
A
O
L

-

1
/
A
O
L

-

1
/
A
O
L

-

1
/
A
O
L

-

1
/
1/ Line
Loop Gain
(A
OL
- 1/)
becomes zero
F
CL
A
OL
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A
I
N

-

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B
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40
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80
FREQUENCY, Hz
1 10M 1M 100K 10K 1K 100 10
2.3 PHASE MARGIN
Oscillation can occur if at a phase shift of 180 degrees the loop gain (1/) is one (0dB), or more. Consequently,
the 'Phase Margin' is defned as how close the phase shift is to a full 180 degrees when the loop gain is 0dB, also
called "The Point Of Intersection". A good rule of thumb is to design for 135 degrees of phase shift which constitutes
a phase margin of 45 degrees. This will allow for events that occur during power up and power down as well as
other transient conditions which may cause changes in the open loop gain (A
OL
) curve that could initiate transient
oscillations.
Note that it is the included angle formed at the Point Of Intersection (closed loop gain = 0dB) which denotes stability
(20dB/decade) or instability (40dB/decade, or more).
2.4 USABLE BANDWIDTH
The usable bandwidth is usually defned as the frequency at which the closed loop gain (A
OL
-1/) falls to 20dB. The
reason is that above this frequency the error rises above 10% so that the performance of the op amp is degraded
signifcantly.
2.5 A FIRST ORDER CHECK FOR STABILITY
As we have explained, the loop gain (1/) is the amount of signal available for feedback to reduce errors and non-linearities. A
frst-order check for stability is to make sure that when the closed loop gain (1/) reaches the open loop gain (A
OL
) line the phase
shift is less than 180 degrees.
Figure 3. Beta Frequency Independent (a) and Frequency Dependent (b)
Figure 4. Closed Loop Constant When the Loop Gain runs out of gas
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Shown in Figure 5 is a plot of an open
loop gain A
OL
which displays a de-
scent rate of 20dB per decade at fre-
quencies of approximately 100Hz to
80kHz. This denotes a phase shift of
90 degrees. At approximately 80kHz
the descent rate changes to 40dB per
decade. So above this frequency, the
phase shift is 180 degrees.
Note that for a loop gain (1/
1
) the
plot intersects the open loop gain
(A
OL
) plot where its descent rate is 20
dB per decade. So this curve passes
the frst check for stability.
For a complete analysis we will need
to check the phase shift of the open
loop gain (A
OL
) response over fre-
quency. This is discussed in Section
4.
Note that the loop gain (1/
2
) plot intersects the
open loop gain (A
OL
) plot where its rate of inter-
section is 40dB per decade. So this curve fails
the frst check for stability.
3.0 FOUR COMPENSATING
TECHNIQUES PHASE COM-
PENSATION
In most treatments of stability, phase compen-
sation will never come up because most small
signal amplifers are internally compensated and
therefore there is nothing that can be done exter-
nally to modify the amplifer. However, in almost
every Apex Precision Power amplifer the phase
compensation can be controlled by an external
capacitance C
C
that the user can select. This en-
ables moving the frst pole of the open loop gain
(A
OL
) plot left or right in frequency, as depicted
in Figure 6. By raising the value of C
C
, the open
loop gain (A
OL
) plot can be moved to the left and
down so that what would otherwise be a problem
pole a descent at 40dB per decade moves
below 0dB. Therefore it is no longer a problem
with regard to stability.
3.1 FEEDBACK ZERO COM-
PENSATION
As depicted in Figure 7, feedback zero compen-
sation is a method of tailoring the op amps per-
formance for a given application. The goal is to
alter the loop gain (1/) by adding a feedback capacitor C
F
, placing a pole in the 1/ plot so that it intersects the
open loop gain (A
OL
) line at 20db per decade instead of at 40dB per decade. The included angle of the intersection
is now 20dB/decade. Hence it is stable. The usable bandwidth is approximately 10kHz.
This technique is very sensitive to the tolerances of the feedback because the loop gain (1/) plot is governed by
the RC response of the feedback. Therefore the power amplifer is very susceptible to going in and out of stability
C
C
largest C
C
Smallest
100
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1 1M 100K 10K 1K 100 10
FREQUENCY, Hz
O
P
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N

L
O
O
P

G
A
I
N
,

A
O
L

(
d
B
)
A
OL
R
IN
R
F
V
FB
V
OUT
C
C
Decending at
40 dB/decade
Decending at
20 dB/decade
100
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40
60
80
1 100M 10M 1M 100K 10K 1K 100 10
FREQUENCY, Hz
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A
I
N
,

d
B
A
OL
1/
1
1/
2
F
CL1
F
CL2
Figure 5. Stability Check A frst order check of stability
Figure 6. Phase Compensation
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based on capacitor C
F
, which may change in value
with changes in temperature
To summarize, this compensation technique is easy
to implement when the loop gain (1/) value is large.
But the technique is somewhat sensitive to variations
in component tolerances.
3.2 NOISE GAIN COMPENSATION
Figure 8 illustrates how noise gain compensation func-
tions. This technique adds a parallel Z
I
path through
R
I
and C
I
, as shown in Figure 8. The objective with
this technique is to close the loop gain early.
One way to view noise gain circuits is to view the am-
plifer as a summing amplifer. Consequently, there are
two input signals into this inverting summing amplifer.
One is V
IN
and the other is a noise source summed
via ground through the series combination of R
I
and
C
I
. Since this is a summing amplifer, V
OUT
/V
IN
will be
unaffected if we sum zero via the R
I
-C
I
network. How-
ever, in the small signal AC domain, we will be chang-
ing the loop gain (1/) plot of the feedback. Conse-
quently, as C
I
becomes a short as the frequency rises,
and if R
I
<<R
IN
, the signal gain will be set by R
F
/R
I
.
Notice in Figure 9 that when the capacitive reactance
of C
I
is large, the loop gain (1/
1
) line is governed by
R
IN
. However, when the capacitive reactance of C
I
be-
comes small, then R
I

supplants R
IN
as the input resis-
tor accounting for the shift to the loop gain (1/
2
) line
crosses the open loop (A
OL
) line at 20dB per decade.
The usable bandwidth is approximately 8kHz.
The noise gain technique is largely immune to com-
ponent tolerance variations. However, it is only ap-
propriate for non-inverting amplifers, i.e., summing
confgurations, and it does sacrifce closed loop gain,
and therefore loop bandwidth at higher frequencies.
3.3 ISOLATION RESISTOR COM-
PENSATION
Figure 10 illustrates isolation resistor compensation
with resistor R
ISO
connected in series with the load C
L
.
As depicted in Figure 11, the loop gain (1/) line, if
uncompensated, would intersect the open loop gain
(A
OL
) line where the phase shift is 40dB per decade
so that the circuit would be unstable. The resistor iso-
lation compensation technique restores the 20dB per
decade slope to the Bode Plot amplifer gain plot, as
depicted by the red line in Figure 11, by inserting a
resistor between the output of the amplifer and the
capacitive load.
Note that resistor R
ISO
adds a corner frequency or zero
in the open loop (A
OL
) plot, restoring a 20dB per de-
cade slope before the 1/ line intercepts it. The se-
ries impedance diminishes as the frequency rises so
that at approximately 11kHz, the resistive load pre-
100
0
20
40
60
80
1 1M 100K 10K 1K 100 10
FREQUENCY, Hz
O
P
E
N

L
O
O
P

G
A
I
N
,

A
O
L

(
d
B
)
A
OL
R
IN
R
F
V
FB
V
OUT
C
F
1/
Figure 7. Feedback Zero Compensation
R
F
V
OUT
R
IN
V
IN
C
I
R
I
C
L
100
0
20
40
60
80
1 1M 100K 10K 1K 100 10
FREQUENCY, Hz
G
A
I
N
,

(
d
B
)
1/
1
1/
2
Figure 8. Noise Gain Compensation - Circuitry
Figure 9. Noise Gain Compensation - Plots
AN47
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B
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B
A
dominates as the series load. This technique does not sacrifce any
loop gain because the open loop gain (A
OL
) line remains stationary.
However, the power loss in the resistor can be signifcant. The usable
bandwidth is approximately 3kHz.
It is worth noting that there is virtually no loss in the peak voltage
across the capacitive load because the current and voltage are out of
phase. Consequently, when the peak voltage is maximum, the applied
current is low, minimizing the voltage loss across the isolation resistor.
This isolation resistor compensation technique is relatively immune to
variations in component values.
4.0 STABILITY TESTS
The following tests describe test techniques for ascertaining whether a design will indeed perform in a stable way.
4.1 SQUARE WAVE TESTING
In this test, a small-amplitude square wave is injected into the closed loop op amp circuit as the V
IN
source, as de-
picted in Figure 12. This example uses components as close to the production version as possible including power
supplies, cables and circuit boards.
A frequency should be chosen that is well within the loop gain bandwidth, but high enough to make triggering of
an oscilloscope easy. For most applications, 1kHz is a good test frequency. Since we are interested in the small
signal AC behavior, adjust V
IN
so that the output is 200mV
P-P
or less. This is to avoid large signal limitations such as
slew rate, output current limitations and output voltage saturation. Check the 1kHz output (V
OUT
) for overshoot and
undershoot while exercising the circuitry, including the power supply with low-frequency variations.
Phase margin for a given step response can be estimated from Figure 13.
R
F
R
IN
V
IN
C
L
R
ISO
100
0
20
40
60
80
1 1M 100K 10K 1K 100 10
FREQUENCY, Hz
G
A
I
N
,

(
d
B
)
1/
Effect of
isolation
resistor
A
OL
Figure 10. Isolation Resistor Circuitry
Figure 11. Isolation Resistor - Plot
R
F
R
IN
C
F
LOAD
V
IN
1KHz
V
OUT
2V
P-P
Figure 12. Square Wave Testing
Figure 13. Phase Margin Versus Step
Response
40 0.6*
90 1.4*
77 1.2*
64 1.0*
52 0.8*
35 0.4*
13 0.2*
V
O
U
T

r
e
l
a
t
i
v
e

o
u
t
p
u
t

t
o

a

s
t
e
p

f
u
n
c
t
i
o
n

i
n
p
u
t
1.6
0
0.2
1.4
0.6
0.8
1.0
1.2
1.4
10 0 1 2 3 4 5 6 7 8 9
n
t
Open loop phase margin & damping factor
AN47
910 AN47U
4.2 DYNAMIC STABILITY
TEST
This is an expansion of the square wave test
described in Section 4.1. The dynamic stabil-
ity test is depicted in Figure 14. In this test a
small-signal AC square wave is imposed on a
low-frequency, large signal AC sine wave to
dynamically test the power op amplifer un-
der all operating point conditions. The square
wave impressed on the slow moving 10-Hz
sweep is depicted in Figure 15. Note that the
value of R
1
in parallel with R
2
in Figure 14
must be much greater than R
I
. Otherwise, the
input test impedances will adversely affect the
compensation of the op amp undergoing test.
5.0 EXAMPLES
Shown in Figure 16 is an uncompensat-
ed op amp. Its Bode Plot is depicted in
Figure 17. In the following sections we
shall show how this circuit can be stabi-
lized using the various stabilization tech-
niques initially described in Section 3.
Note that the 50k pole in the open loop
gain (A
OL
) is due to the capacitive load
impedance. This circuit is unstable be-
cause the closed loop gain 1/ intersects
the open loop gain at a rate of 40dB per
decade.
Figure 14. Dynamic Stability Test
Figure 15. Square Wave Imposed on the Waveform
R
F
R
I
C
F
LOAD
V
IN
to sweep V
OUT
V
OUT
10 Hz
-V
S
+V
S
V
IN
R
1
R
2
100 Hz
V
IN
for 100mV V
OUT
R
1
/R
2
>R
I
Added for stability testing
R
F
AMPLIFIER = PA241
V
OUT
C
LOAD
R
IN
V
IN
C
LOAD
=20nF
R
IN
=2.5K
R
F
=22.5K
1/ =20dB
A
OL
1/
Frequency - Hz
100
80
60
40
20
0
-20
1 10 100 1K 10K 100K 1M 10M 100M
G
a
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-

d
B
Figure 16. Uncompensated Op Amp Figure 17. Uncompensated Op Amp Bode Plot
-V
S
+V
S
10K, 100mV
P-P
square wave
On 10Hz sinusoidal V
IN
to sweep V
O
t
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A
R
F
AMPLIFIER = PA241
V
OUT
C
LOAD
R
IN
V
IN
C
LOAD
=20nF
R
IN
=2.5K
R
F
=22.5K
1/ =20dB
C
F
C
F
=820pF
A
OL
1/
Frequency - Hz
100
80
60
40
20
0
-20
1 10 100 1K 10K 100K 1M 10M 100M
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a
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d
B
X
R
F
AMPLIFIER = PA241
V
OUT
C
LOAD
R
IN
V
IN
C
LOAD
=20nF
R
IN
=2.5K
R
F
=22.5K
1/ =20dB
C
N
=33pF
R
N
= 250
R
N
C
N
A
OL
1/
Frequency - Hz
100
80
60
40
20
0
-20
1 10 100 1K 10K 100K 1M 10M 100M
G
a
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n

-

d
B
Figure 18. Compensated Capacitive Load
Schematic
Figure 19. Compensated Capacitive Load Bode Plot
Figure 20. Noise Gain Compensated
Schematic
Figure 21. Noise Gain Compensated Bode Plot
5.1 FEEDBACK ZERO COMPENSATION
By adding a compensating capacitor C
F
, to the circuit shown in Figure 16, the circuit becomes the one shown in
Figure 18, and its corresponding bode response in Figure 19. By adding a feedback capacitor C
F
to alter the 1/
line, and placing a pole in the 1/ plot so that it intersects the red line at an angle corresponding to less than 40db
per decade, which happens to be just under 200kHz, the usable bandwidth is approximately 30KHz. This technique
is very sensitive to the tolerances of the feedback capacitor. Note in the plot that the 20% capacitor moves that pole
over a 100kHz range, so it is very susceptible to going in and out of stability based on that capacitor (which may
change in value with changes in temperature).
5.2 CAPACITIVE LOAD NOISE GAIN COMPENSATED
Shown in Figures 20 and 21 is a circuit and its corresponding Bode amplitude plot for an op amp employing noise
gain compensation. The impact of adding C
N
is to bump up the 1/ (the green line) so that it intersects the A
OL
line
above the pole where the plot shifts from 20dB per decade (stable) to 40dB per decade (unstable).
The usable bandwidth is approximately 3kHz.
AN47
912 AN47U
5.3 CAPACITIVE LOAD ISOLATION RESISTOR
Shown in Figures 22 and 23 is a circuit and its corresponding Bode amplitude plot for an op amp employing an
isolation resistor R
ISO
. The isolation resistor reduces the phase angle of the load so that it doesn't appear capacitive
at higher frequencies. The usable bandwidth is approximately 30kHz.
With the isolation resistor, we sacrifce virtually no bandwidth. This can be a signifcant trade off. In this case, with
an 80 V
P-P
output at 25kHz, we are dissipating 0.75 watts in the resistor. Because the loss is load current related, it
may or may not be a problem.
R
F
AMPLIFIER = PA241
C
LOAD
R
IN
V
IN
C
LOAD
=20nF
R
IN
=2.5K
R
F
=22.5K
1/ =20dB R
ISO
= 100
R
ISO
A
OL
1/
Frequency - Hz
100
80
60
40
20
0
-20
1 10 100 1K 10K 100K 1M 10M 100M
G
a
i
n

-

d
B
R
F
AMPLIFIER = PA241
V
OUT
C
LOAD
R
IN
V
IN
C
LOAD
=20nF
R
IN
=2.5K
R
F
=22.5K
1/ =20dB
C
N
=33pF
R
N
= 250
C
F
=820pF
R
N
C
N
C
F
A
OL
1/
Frequency - Hz
100
80
60
40
20
0
-20
1 10 100 1K 10K 100K 1M 10M 100M
G
a
i
n

-

d
B
5.4 FEEDBACK ZERO AND NOISE GAIN COMPENSATED
Shown in Figures 24 and 25 is a circuit and its corresponding Bode amplitude plot for an op amp employing both
feedback zero and noise gain compensation. The goal here is to use multiple techniques to lessen the impact of
the trade offs. So with noise gain compensation bandwidth sacrifced, but with feedback zero compensation, circuit
is quite sensitive to noise; however, with this combination we realize a usable bandwidth. It is back up in the neigh-
borhood of 30kHz. The circuit is pretty much immune to component tolerance issues and fnally there is good bit of
phase margin.
Figure 22. Isolation Resistor Compensated
Schematic
Figure 23. Isolation Resistor Compensated
Bode Plot
Figure 24. Capacitive & Noise Gain
compensated Schematic
Figure 25. Capacitive & Noise Gain
compensated Bode Plot
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REFERENCES
1. The Art of Electronics, Second Edition, Paul Horowitz and Winfeld Hill, Cambridge University Press, 1989, p.
242
2. Apex Precision Power Application Note 19, Stability For Power Operational Amplifers, Cirrus Logic, www.cirrus.
com
BIBLIOGRAPHY
Network Analysis And Feedback Amplifer Design, H.W. Bode, D. Van Nostrand., 1945
Intuitive Operational Amplifers, Thomas M. Fredericksen, McGraw-Hill Book Co., 1988
REVISION HISTORY
Release Date Changes
REVA APR 2008 Initial Release
IMPORTANT NOTICE
AN48
914 AN48U
AN48 Increasing Output Swing
in Power Operational Amplifers
INTRODUCTION
Due to the typical circuit topologies used in the output stages of power operational amplifers, the output voltage
swing may be limited by as much as 12V less than the applied power supply voltage. The goal of this application
note is to illustrate several practical techniques to drive the amplifer output closer to the rail voltages, which enables
power output to increase signifcantly. In some applications, the output power can be increased by as much as 50%.
Certain power operational amplifers allow the user to apply a separate higher voltage supply to the input stage of
the amplifer while the output stage is set to a lower voltage. This arrangement achieves close-to-rail voltage swing
since the output devices, usually Enhancement Mode MOSFETs, are driven close to saturation by the higher volt-
age available to drive the gates. Another method to improve output voltage swing is to modify the amplifer's output
stage by adding some external output components. This application note explores these approaches through the
discussion of typical examples with the hope that users will create and develop circuits to meet their own specifc
requirements based on the techniques shown here.
GENERATING THE BOOST VOLTAGE
Many power operational amplifers provide separate power supply pins for the input stage and output stage. This
allows the user to apply a higher power supply voltage to the input circuitry than the supply voltage applied to the
output stage. The voltage difference is usually between 5V and 15V. This enables the output devices to be driven
close to their saturation. If this increased voltage swing is not needed, then the input and output power supply pins
are connected together providing equal supply voltage to the input and output stages. As an example, the Apex
Precision Power MP39 power operational amplifer
1
, depicted in Figure 1, has separate pins for V
B
, the input
stage supply voltage, and V
S
, the output stage supply voltage, so that the designer can tie them together or power
them separately, as outlined below.
Figure 1. V
B
and V
S
are Separate Because the DC power inputs for the input stage (V
B
) are separated from the
output stage (V
S
) in the MP39, the designer has the option of applying higher potential to each V
B
terminal, thereby
allowing the output voltage to swing closer to the rail potentials (V
S
).
The Q4 and Q12 MOSFETs deliver a maximum output current of 10A to the load. In most applications, +V
B
and +V
S

are connected together. Since Q4 is an enhancement mode device, the gate voltage must be at least 10V higher
than the source voltage to achieve the lowest source to drain voltage. In the case of Q12, the gate voltage must be
10V lower. This means the maximum output voltage, at full output current, will be at least 10V lower than V
S
. By ap-
plying a higher voltage to V
B
, the Q4 gate voltage is driven to a higher potential than V
S
, forcing a higher Q4 source
voltage. As indicated in the MP39 data sheet, the absolute maximum boost voltage, V
B
, is specifed at 20V higher
than V
S
and the maximum boost supply current is 22mA.
+V
B
+V
S
-V
B
-V
S
-IN
+IN
OUT
MP39
POWER OPERATIONAL
AMPLIFIER
Input
Stages
Output Stages
Q3
Q14
Q12 Q8
Q4
1
30
29
12 14 13
15 17 16
18 20 19
26
Increasing Output Swing in Power Operational Amplifiers
JUN 2009
APEX AN48UREV3
AN48
AN48U 915
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For applications requiring an output current of less than 500mA, a 10V to 15V zener diode placed between V
B
and
V
S
may be adequate. In this confguration the power supply voltage would be connected to the V
B
pin. This will au-
tomatically force the V
S
input 10V to 15V lower than V
B
. If this approach is followed, all of the output current would
fow through the zener diode which would have to dissipate the resulting power. This is a simple solution, but not
very practical because the MP39 can deliver output currents of up to 10A.
EMPLOYING ISOLATED DC-TO-DC CONVERTERS
Isolated DC-to-DC converters may be used to supply the boost voltage. There are many commercially available
converters that are suitable for providing the boost voltage. A pair of CALEX 3W modules have been selected (avail-
able in either surface mount or through-hole confgurations). The 48V input version offers an input voltage range
from 36V to 72V and an isolated, regulated output of 12V. Two modules are required, one for the +V
B
and one for
the V
B
. Our testing was performed with V
S
set at 40V. One module was powered from the +40V supply (+V
S
) and
the other module was powered from the -40V supply (-V
S
). Since the outputs are isolated, other input power supply
arrangements could be used, as long as the supply voltages are within the modules operating input range. In the
confguration depicted in Figure 2, the voltage potential between the +V
B
and the V
B
terminals is 52V.
Figure 2. Obtaining the Boost
A pair of DC-to-DC converters connected as shown in Figure 2, are powered by the 40V power supplies that also
provide the V
S
voltages. The output of the DC-to-DC converters is connected between the V
S
and V
B
of the power
operational amplifer terminals providing the required boost voltage. To maintain a balanced load across the power
supplies, the output of one converter is connected in series with +V
S
supply and common, and the second converter
between V
B
and V
S
. The outputs are isolated so any convenient power sources can be applied as long as the total
voltage applied to V
B
and +V
B
does not exceed the specifed input range.
DC-TO-DC CONVERTERS FROM OFF-THE-SHELF COMPONENTS
A low cost DC-to-DC converter can be assembled using off-the-shelf components commonly available through
common catalog distributors. The schematic circuit diagram is shown in Figure 3. This converter was designed for
the specifc purpose of providing the V
BOOST
for any Apex Precision Power power operational amplifer featuring
separate power pins for the input and the power stages.
Note that the transformers T1, T2 and Inductor L1 are Coiltronics part numbers available from Cooper Bussman.
Because the two outputs are totally independent, a single converter will supply both the plus and minus V
BOOST
. The
input voltage range is specifed from 20V to 100V allowing additional fexibility. The converters switching frequency
is approximately 20kHz and exhibits very low radiated and conducted noise components, assuming the circuit lay-
POWER
SUPPLY
40V
POWER
SUPPLY
40V
DC-TO-DC
CONVERTER
12V
DC-TO-DC
CONVERTER
12V
IN
IN
-IN
+IN
OUT OUT
OUT OUT
OUT COM
+V
B
+V
S
-V
S
-V
B
+
+
+
+
+
+
+
MP39
AN48
916 AN48U
out and ground scheme are given careful attention. Transformer L1 is a common mode flter that rejects common
mode noise due to the switching that occurs in the Timer X1, preventing it from feeding back to the V
S
source volt-
age. The snubber circuit, consisting of Capacitor C13 and Resistor R11, counteracts ringing that would other wise
occur in Transformers T1 and T2.
Figure 3. A Low-Cost DC-to-DC Converter This converter can be employed to supply the boost voltages (+V
B

and V
B
) necessary to increase the output swing.
Table 1. Parts List for DC to DC Converter Circuit Shown in Figure 3
REFERENCE
DESIGNATION DESCRIPTION
PART NUMBER
(DIGI-KEY)
C11, C12,C6,C7 CAPACITOR, X7R CERAMIC, 4.7F, 25V, TDK 445-2886-ND
C1 CAPACITOR, COG CERAMIC, 330pF, 50V, MURATA 490-3724-ND
C2, C3 CAPACITOR, TANTALUM, 47F, 25V, AVX, TAP476K025CCS 478-4181-ND
C8 CAPACITOR, X7R CERAMIC, 0.01F, 100V, MURATA 490-3813-ND
C9 CAPACITOR, X7R CERAMIC, 1.0F, 50V, TDK 445-2884-ND
C10 CAPACITOR, POLY FILM, 4.7F, 250V, PANASONIC EF2475-ND
C13 CAPACITOR, X7R CERAMIC, 1000pF, 200V, KEMET 399-4323-ND
C14 CAPACITOR, X7R CERAMIC, 0.1F, 200V, KEMET 399-4387-ND
D1, D2 1N4148, DIODE, OR EQUIVALENT
D3, D4 1N5350, 13V ZENER DIODE, 5W, ON SEMI 1N5350BRLGOSCT-ND
D5 1N4739, 9.1V ZENER DIODE, 1W, ON SEMI 1N4739ADICT-ND
D6, D7 MUR120, ULTRA FAST RECOVERY, RECTIFIER, ON SEMI MUR120RLGOSCT-ND
D5 1N4739, 9.1V ZENER DIODE, 1W, ON SEMI 1N4739ADICT-ND
L1 100 H CHOKE, COILTRONICS, DRQ-73-101-R 513-1251-1-ND
M1 IRF620PBF, MOSFET, 200V, 5.2A, VISHAY, IR IRF620PBF-ND
R1,R3,R8,R9,R10 RESISTOR, FILM, 1.0, 1W
R2 RESISTOR, FILM, 249K, 1%, 0.25W
TLC555
TIMER
+V
S
IN
-V
S
IN
+V
B
1 OUT
-V
B
2 OUT
+V
B
2 OUT
-V
B
1 OUT
T1
D3
C2 C6 C12
R10
R1
D6
MUR120
1.0
1N5350B
4.7F
1.0
47F 4.7F
+
T2
D4
C3 C7 C11
R9
R8
D7
MUR120
1.0
1N5350B
4.7F
1.0
47F 4.7F
+ C13
1000pF
C9
1F
R11
301 D5
1N4739A
C10
4.7F
R7
15K
R6
113K
L1
D2
1N4148
D1
1N4148
C8
0.01F
C1
330pF
R2
249K
R3
1.0
R4
301
M1
IRF620PBF
(HEATSINK REQUIRED)
3
X1
7
6
5
4
2
1
8
C14
0.1F
AN48
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REFERENCE
DESIGNATION DESCRIPTION
PART NUMBER
(DIGI-KEY)
R4, R11 RESISTOR, FILM, 301, 1%. 0.25W
R6 RESISTOR, FILM, 113K, 1%, 0.25W
R7 RESISTOR, FILM, 15K, 1W
T1, T2 100 H CHOKE, COILTRONICS, DRQ-127-101-R 513-1314-1-ND
X1 TLC555 TIMER, I.C., TI 296-1857-5-ND
SAMPLE TEST CIRCUIT A 200W POWER OPERATIONAL AMPLIFIER DRIVING
AN 8 RESISTIVE LOAD
In this example an MP39 power operational amplifer is confgured as an inverting amplifer with a gain of 5 and
driving a resistive load of 8, as depicted in Figure 4. The value of the compensation capacitor C
C
, 220pf, complies
with the recommendation specifed in the MP39 data sheet for a gain of 3 or more, and less than 10. The power
supply voltage, V
S
, is set to 40V. The boost voltages, +V
B
and V
B
, are set at 12V. The power delivered to the load
is 200W PEAK with the boost voltage applied, and 144W PEAK with no boost voltage. This signifcant increase in
realized power can be important in high-effciency applications. The MP39 datasheet limit for output voltage swing
is V
S
8.8V. This means clipping could occur at 31.2V without the boost voltage.
Figure 4. Test Circuit This circuit with an inverting gain of 5, V
B
of 12V and V
S
of 40V, was used to obtain the
plots in Figures 5 and Figures 6.
The waveforms shown below in Figure 5 depict the output without the boost circuits the V
B
terminals are tied
to the V
S
terminals. Note that clipping of the output waveform occurs at +34V and 34V respectively, because the
output can be driven no higher. However, with the addition of boost circuits with potentials of 12V, the output is able
to swing all the way to the supply rails, as depicted in Figure 6.
R
F
50K
R
CL
0.05
R
L
8
R
I
10K
+V
B
-V
B
+V
S
-I
LIM
-V
S
+I
LIM
C
C
1
C
C
2
OUT
V
B
V
S
V
B
V
S
V
IN
V
S
COMMON
C
C
220pF
18-20
4
24
26
6
23
29
30
15-17
12-14
1
+
+ +
+
-
- -
-
-IN
+IN
MP39
AN48
918 AN48U
Figure 5. Without a Boost Circuit With the V
B
boost terminals tied to the V
S
terminals the output voltages are
clipped at 34V. Consequently, the output swing is unable to reach the supply rails at +40V and 40V, respectively.
In this confguration the amplifer can only deliver 144W PEAK.
Figure 6. With a Boost Circuit With the addition of +V
B
and -V
B
boost circuits, the output is able to swing all the
way to the rail potentials at V
S
and -V
S
, respectively. The amplifer in this confguration is able to deliver 200W PEAK
approximately 39% more power than when the amplifer operates without the boost circuits.
20 210 200 180 160 140 120 100 80 60 40
20 210 200 180 160 140 120 100 80 60 40
OUTPUT, S
INPUT, S
10
0
-10
40
20
0
-20
-40
C1
C2
+V
S
-V
S
V
O
L
T
S
V
O
L
T
S
20 210 200 180 160 140 120 100 80 60 40
20 210 200 180 160 140 120 100 80 60 40
OUTPUT, S
INPUT, S
10
0
-10
40
20
0
-20
-40
C1
C2
+V
S
-V
S
V
O
L
T
S
V
O
L
T
S
AN48
AN48U 919
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A
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B
A
MODIFICATION OF THE OUTPUT STAGE CAN IMPROVE OUTPUT VOLTAGE SWING
Shown in Figure 7 is a circuit based on the Apex Precision Power PA96 power operational amplifer
2
operating with
power supply voltages of 40V. Resistors R3 and R4 are selected so that the maximum quiescent current creates
a voltage drop of approximately 0.5V to 0.6V across the base-to-emitter junctions of Q1 and Q2. This keeps the
output transistors from turning on and conducting collector current when the output voltage is near zero. Resistors
R5 and R6 are selected to provide suffcient base current to Q1 and Q2 as the output voltage approaches the rail
allowing Q1 and Q2 to pull the output closer to the supplies. A note of caution: although the power operational ampli-
fer is current limit protected, the output transistors (Q1 and Q2) have no overcurrent protection and will be damaged
if their SOA (Safe Operating Area) requirements are exceeded.
Figure 7. Composite Power Amplifer A PA96 operational amplifer with additional output transistors, Q1 and
Q2, and resistors R3, R4, R5, and R6. This modifcation creates a composite operational amplifer with extended
output voltage swing.
Figure 8 below depicts how the circuit in Figure 7 reacts when resistors R3, R4, R5, and R6 are not used showing
the circuit's output clipping. Figure 9 illustrates how the same circuit behaves when the three resistors have been
added. Clipping no longer occurs.
R3
25
R4
25
R5
150
V1
40VDC
V2
40VDC
Q1
MJ E15031
Q2
MJ E15030
R
CL
C
COMP
R
LOAD
R6
200
R10
1K
R9
10K
C1
22pF
V3
3.5V
P-P
10K
100pF
+
+
4
6
7
8
1
2
3
5
+IN
+V
S
U1
PA96
-V
S
OUT
C
L
-IN
AN48
920 AN48U
Figure 8. Composite Amplifer without Modifcations
Figure 9. Composite Amplifer with Modifcations
20 210 200 180 160 140 120 100 80 60 40
20 210 200 180 160 140 120 100 80 60 40
OUTPUT, S
INPUT, S
4
0
-4
40
20
0
-20
-40
C1
C2
+V
S
-V
S
V
O
L
T
S
V
O
L
T
S
20 210 200 180 160 140 120 100 80 60 40
20 210 200 180 160 140 120 100 80 60 40
OUTPUT, S
INPUT, S
4
0
-4
40
20
0
-20
-40
C1
C2
+V
S
-V
S
V
O
L
T
S
V
O
L
T
S
AN48
AN48U 921
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B
A
MAINTAINING LINEAR PERFORMANCE WITH OUTPUT VOLTAGES
APPROACHING THE NEGATIVE RAIL
The circuit shown in Figure 10 accepts input voltage levels, including zero, and can deliver output voltages from
zero to 10V with a single ended 18V power supply. The Apex Precision Power PA75 dual power operational ampli-
fer
3
is used because the input voltage range includes the negative supply voltage. However, the PA75 output volt-
age does not swing very near to the rails. The PA75 consists of two operational amplifers. One is pre-confgured
as a unity gain buffer, while the other can have its gain programmed and is employed in this circuit. This example
enables the output voltage to drive a grounded load to zero volts. Diode D2 must be a low leakage zener diode for
the circuit to function. Since the output voltage of the PA75 never reaches zero volts, any leakage current fows
through the load resistor causing a non-zero voltage at the load. The feedback loop cannot correct for this once the
output reaches it's minimum voltage. Notice the plot of Figure 11. The output response is quite linear with respect
to the input from zero to 10V.
Figure 10. Single Ended Operation Delivering Output from Zero to 10V
Figure 11. Output Response of the Circuit in Figure 10
R
LOAD
Q1
MJ E15030
V
IN
C1
1F
VS
18V
+
R5
1K
R3
2K
R4
18K
R2
4.99K
D2
1N4622
D1
1N4148
+IN AMP A
-IN AMP A
OUT AMP A
+V
-V
PA75
+
-
12
10
8
6
4
2
0
O
U
T
P
U
T

V
O
L
T
A
G
E
INPUT VOLTAGE
0 1.2 1.0 0.8 0.6 0.4 0.2
AN48
922 AN48U
CONCLUSIONS
Several methods for extending the output voltage swing of power operational amplifers have been described. The
circuits included in this application note have been developed and tested. The schematics may not include all com-
ponents such as by-pass capacitors, resistors and diodes needed for a complete design. Circuit layout has not been
addressed and is critical for all circuit confgurations using Apex Precision Power products. The test results shown
are based on the typical performance of a specifc device used in each application. The differences in performance
shown, with and without the modifcations, will be more dramatic when compared to minimum voltage swing data
sheet limits. For additional information concerning the use of power operational amplifers with regard to stability,
thermal management, device protection, and other topics, please refer to the relevant Application Note
4
.
References
1. MP39 Power Operational Amplifer Data Sheet, Cirrus Logic, Apex Precision Power.
2. PA96 Power Operational Amplifer Data Sheet, Cirrus Logic, Apex Precision Power.
3. PA75 Dual Power Amplifers Data Sheet, Cirrus Logic, Apex Precision Power.
4. Techniques for Stabilizing Power Operational Amplifers, Application Note 47, Cirrus Logic, Apex Precision Pow-
er
IMPORTANT NOTICE
AN49
AN49U 923
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B
A
AN49 Jumper Confgurable 100 Watt+ DC-to-DC
Converter Fulflls Buck-Boost & Motor Drive Roles
INTRODUCTION
This Application Note describes a novel DC converter design concept that uses the SA306-IHZ monolithic three-
phase switching amplifer
1,2
. The converter is depicted schematically in Figure 1. It can be thought of as a black
box module that is suitable for a variety of applications such as converting +28 volts to -48 volts (relative to the +28
volt input) and -20 volts (relative to the -28 volt input), and able to deliver a minimum of 8.5 amperes of combined
output. The module is jumper confgurable as a positive or negative input converter. A minor circuit change (Figure
1, Note 5) allows the module to convert +48 volts to +20 volts at 15 amperes of output (representing 91% effciency),
or -48 volts converted to -28 volts with 14 amperes (a 93% effciency). For simplicitys sake, the design is limited in
scope but has proven to be quite usable and robust despite the limitations listed below, and in the section entitled
Miscellaneous Design Notes on page 9. This design assumes a well regulated voltage input because of limited loop
gain. The output voltage regulation is 1% to 3% over the full output load range with an input voltage delta of 300
mV. There is no boost mode current limit circuit included for a number of reasons, one of which is that the input is
diode coupled to the output output currents in excess of 15 A will exceed the diode current/wire bond ratings.
Transient load response is quite good with full recovery in about 3 milliseconds. Effciencies of approximately 94%
are realized with a 48 V output and approximately 85% with the 20 V output, as depicted in the application illustra-
tions that follow.
U1
U2
U3
100 pf
133k
1k
R1
R2
45 kHz
C1
TLC555
TLC555
3
6
2
7
4 8
1
3
6
2
7
4 8
1
3
6
2
7
4 8
1
19k
(Note 1)
R3
200
R4
330 pf
C2
200
R6
330 pf
C3
74HC4049
U4A
5
5
Bb
Bt
At
Ct
Ab
Cb
19.1k
R5
500k
R7
1 meg
R8
15k
R10
R11
499
R12
499
R13
499
R14
1.3k
500k
R15
74HC4049
U4B
74HC4049
U4C
Ia
Ib
Ic
OUT B
OUT A
OUT C
B
L1
L2
L3
100 H
100 H
100 H
DIS2
Pgnd
R9
20k
Vs
+
+Vs
-Vs
+
Soft
Start
+Vdd
+5 VDC
-Vdd
To Ext. 5 VDC For initial testing
+
C
R16
R17
C4
C5
C8
C9
C11 C10
SA306-IHZ
2 F
+Vdd
+Vdd
+Vdd
TEMP
(Note 3)
D1
1N4148
D2
1N4148
D4
1N4148
D5
D6
5 A
100 V
D7
5 A
100 V
D8
5 A
100 V
D9
5 A
100 V
D10
5 A
100 V
U5
1 F
470 F
50 V
470 F
50 V
2 F 200 F
V Adj.
(Note 2)
D3
100k
1.2k, 3 W
(Note 2)
I
LIM
/DIS1
5.6V
30V
Vdd
Sgnd
+Vdd
1
5
21
23
25
11
13
19
15
61
17
63
29, 30, 31
42, 43 ,44
33, 34 ,35
51, 52 ,53
7 9
(Note 4)
46, 47, 48, 49
TLC555
A
D11
5 A
100 V
+
Notes:
1. Nominal B phase balance
2. J umper dashed lines for positive converter;
jumper solid lines for negative converter.
3. To optional over-temperature shutdown switch.
4. PGND (phase A & B): 37,38,39,40; PGND (phase C): 55, 56, 57
5. For 48V
IN
buck, move jumper from X-Y to X-Z, change D3 to a jumper, remove C4.
R11, R12 and R13 may be changed to 1.8K to provide current limiting with SA306 pin 7 unconnected.
(Note 5)
(Note 5)
(Note 5)
Z
Y
X
Figure 1. Polarity is Easily Switched DC-to-DC converter, three terminal module can be switched
from a positive to a negative converter by simply interchanging the jumpers identifed by Note 2.
(Caution: Make sure the A,B,C terminal connections correspond to the new confguration, otherwise
the SA306-IHZ will be destroyed when power is applied.)
Jumper Configurable 400 Watt+ DC-to-DC Converter
Fulfills Buck-Boost & Motor Drive Roles
OCT 2008
APEX AN49UREV1
AN49
924 AN49U
28 VDC
Negative
Converter
48 VDC > 6 A
~ 94% efficiency
+
A
C
Buck-Boost Appli cations
B
28 VDC
Positive
Converter
48 VDC > 6 A
~ 94% efficiency
+
A
C
B
28 VDC
Negative
Converter
20 VDC > 6 A
~ 85% efficiency
+
A
C
B
28 VDC
Positive
Converter
20 VDC > 6 A
~ 85% efficiency
+
A
C
B
48 VDC
Buck Negative
Converter
28 VDC, 14 A
~ 93% efficiency
+
A
C
B
48 VDC
Buck Negative
Converter
20 VDC, 15 A
~ 91% efficiency
+
A
C
B
X
Z
Y
D3
X
Z
Y
D3
APPLICATIONS
In the following panel are shown a number of buck, boost and motor applications.
AN49
AN49U 925
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B
A
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C
B
A
SYSTEM
SUPPLY
28 VDC
Negative
Converter
A
C
Motor Drive Appli cations
B
MOTOR
DRIVE
BOARD
SA306-IHZ
5 VDC
LINEAR
REGULATOR
48 VDC
MOTOR
SYSTEM
SUPPLY
15 VDC
Positive
Converter
A
C
B
MOTOR
DRIVE
BOARD
SA306-IHZ
5 VDC
LINEAR
REGULATOR
48 VDC
MOTOR
U1, U2, U3, U4 and much of the associated circuitry could be replaced with an inexpensive micro-controller to
provide other functions and voltage ranges than those shown above for all applications resulting in a low cost, low
parts count converter module.
Theory of Operation PWM Circuitry
The drive circuit shown in Figure 1 comprises three Texas Instruments TLC555 CMOS Timers, as well as the left
block in Figure 2. In Figure 1, U1 serves as a 45 kHz oscillator. It, in turn, drives U2 and U3 which can be thought of
as pulse width modulators (PWMs). As can be seen in Figure 1, U4A inverts the input to U3 so that it operates out of
phase with its companion, U2. Even though the SA306-IHZ is a three-phase device with three sets of MOSFET half
bridges, A, B and C operate in this application as a two-phase switch. Notice at the bottom of Figure 2 that Ab and
Cb, as well as At and Ct are tied together, transforming the operation of the SA306-IHZ in to a two-phase operation.
The two waveforms shown in Figure 2 are there to underscore the fact that the B phase (Bt and Bb) and the A & C
phases (Ab, Cb) and (At, Ct), are always driven out of phase with each other. These out-of-phase signals toggle the
inputs to the MOSFETs in the switching amplifer SA306-IHZ (U5). This alternating toggle arrangement distributes
the power properly within the SA306-IHZ die, allowing maximum current throughput and reducing ripple current.
Maximum On Time Because the Oscillator U1 is set at 45 kHz by timing components R1, R2 and C1, the period
of the oscillator is 22 microseconds. The maximum ON time is 50%. Raising the voltage on U2 and U3 would pro-
vide a slight variation. This is employed in the Slow Start circuitry discussed in the Charge Dynamics section that
follows. Raising the voltage applied to pin 5 of U2 and U3 raises the deadtime by increasing the threshold of these
devices so the OFF time is extended. As the voltage applied through R7 and R15 goes up, the OFF time becomes
longer.
Battery Appli cations
+48
Buck Negative Converter
A
C
B
+48 VDC
Buck Negative Converter
A
C
B
X
Z
Y
D3
X
Z
Y
D3
-48
-48 VDC
-28 VDC
+20 VDC
+48
-48
APPLICATION
LOADS UP TO
14 AMPERES MIN.
(COMBINED CURRENT)
APPLICATION
LOADS UP TO
14 AMPERES MIN.
(COMBINED CURRENT)
Note: Converters are adjustable via
the R8 potentiometer - C to B voltage
Adjusts from 16 to 22 V while B to A
voltage adjusts from 32 to 26 V
Simultaneously (48 V total). The
maximum output per module is the
lesser of 400 watts combined output
power or 15 amperes combined
output current. It should be noted
that the series loads shown above
will divide the input voltage if a
converter shuts down (thermal limit,
etc). See Figure 1, Note 5 for
reccommended current limiter.
AN49
926 AN49U
Figure 2. PWM Circuitry Interface with the SA306-IHZ Inputs Simplifed
Boost Circuitry
The voltage change technique employed in this converter is often called Boost Circuitry. Each input inductor is
charged through one SA306-IHZ output switch during a PWM charge interval and then is synchronously rectifed
by the alternate MOSFET output switch during the PWM discharge interval. Or to put it another way, energy is
loaded into inductor L1, L2, or L3 and is then, during the discharge interval, delivered as a current to the output ca-
pacitors and/or the load. Because the PWM ON time is limited by design to 50% maximum, the voltage delivered at
the output of the converter is limited to approximately twice Vs which is the voltage delivered by the source. This
inherent voltage limiting occurs because the synchronous rectifer remains on during the entire PWM discharge
time and then transfers the current back from the output capacitor into the input capacitor. Note that in both the
positive and negative versions of this converter, the current exits the SA306-IHZ, at either Vs+ or Vs-, entering the
attached load.
A Soft Start circuit is required to confne turn on input current transients to safe levels and occurs any time the output
capacitors ramp up. This is discussed in detail in the Soft Start section, below. The jumpers in the circuit ensure
that the correct MOSFET switches are used for charging and discharging, thereby programming either positive or
negative polarity input operation. The two jumpers must match which is to say they must both be straight through
or crossed.
U1, U2, U3
Vs (phase A)
PGND(A&B)
A
B
C
Out A
Out B
Out C
PGND(C)
Vs-
Vs (phase B&C)
Vs +
DIS2
Bt
Bb
PWM Circuitry
&
Square Wave
Generator
45kHz
Ab
Ct
Cb
At
Note:
Dashed jumper lines for Positive Converter;
solid jumper lines for negative converter
CAUTION
Both jumpers must be reversed, at the same time, otherwise
serious damage may occur. Also make sure that the A,B,C ter-
minal connections correspond to the new confguration, other-
wise the SA306-IHZ will be destroyed when power is applied.
Charge Dynamics
Positive Converter For the positive converter confguration shown in Figure 3, inductor L1 is charged during the
ON interval through the bottom MOSFET (Bb) switch. Inductor L1 sees Vs- on the left side and Vbat plus on the
right; therefore, the current is essentially a ramp, as depicted in the fgure because the voltage across the inductor
is essentially constant and current is the integral of voltage. Then during the OFF interval the inductor discharges
through the top MOSFET switch (Bt), exiting through terminal A to the attached load. Again, the same occurs for the
A and C MOSFET switches during alternate cycles except their inputs are tied together, as shown in Figure 2, and
therefore the At-Ct and Ab-Cb pairs are driven in unison.
Negative Converter For the negative converter confguration shown below in Figure 4, inductor L1 is charged
during the ON interval through the MOSFET (Bt) switch. When the Switch transfers to the charge mode, inductor
L1 discharges through the bottom MOSFET switch (Bb) into the power ground. The same occurs for the A and C
MOSFET switches during the alternate cycle except their inputs are tied together, as shown in Figure 2, and there-
fore At and Ct and Ab and Cb pairs are driven in unison.
Buck Negative Converter This converter mode has the same charge dynamics as the negative converter. The
difference is that power is applied via terminals A and C and removed via terminal B.
AN49
AN49U 927
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B
A
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B
A
Soft Start (Boost Only)
If there were no constraint when start up occurs, the input current would become very high because the circuit would
attempt to immediately restore the low output voltage. In order to manage this scenario, the PWM, which behaves,
in effect, as an error amplifer, is prevented from overreacting and instead the duty cycle is controlled so that the
duty cycle rises slowly. As Vs comes up, it would normally pass through the 30 V zener diode D3 and adjustment
potentiometer R8 to the junction or duty cycle node between Resistors R7 and R15. Instead the Soft Start node
is connected directly to the output through D1 C4 to Vs+, thereby bypassing the output of the converter sensed
by the R8 D3 network until the Vs potential is reached.
Figure 3 Charge Dynamics Positive Converter
Figure 4 Charge Dynamics Negative Converter
SA306-IHZ
Switching Amplifier
Vs (phase A)
PGND(A&B)
A
B
C
Out A
Out B
Out C
PGND(C)
Vs-
Vs (phase B&C)
Vs +
ON (Bt)
ON (Bb)
D10
D11
D9
D6
D8
D7
L1
100 H
L3
100 H
L2
100 H
A
C
B
C11
200 F
C10
2 F
C9
470 F
35 V
C8
470 F
35 V
+
+ +
+
ON (At)
ON (Ab)
ON (Ct)
ON (Cb)
Charge
Path
Discharge
Path
SA306-IHZ
Switching Amplifier
Vs (phase A)
PGND(A&B)
A
B
C
Out A
Out B
Out C
PGND(C)
Vs-
Vs (phase B&C)
Vs+
ON (Bt)
ON (Bb)
D10
D11
D9
D6
D8
D7
L3
100 H
L2
100 H
A
C
B
C11
200 F
C10
2 F
C9
470 F
35 V
C8
470 F
35 V
+
+ +
+
L1
100 H
Discharge
Path
Charge
Path
AN49
928 AN49U
Steady-State Waveforms
As shown in Figure 5a, when the signal
from the PWM turns on Bt, the current
contribution to L1 during the previous
cycle starts to decay (Iout waveform).
When Bt goes OFF, and Bb goes ON,
the current fows into inductor L1, rising
in a linear fashion as depicted. By ex-
amining the actual composite waveform
resulting from the contributions of both
the B phase and the A-C phase (which
behaves as a single-phase switch driv-
ing one half the inductance of 100 mi-
crohenries), ripple current is reduced.
This is true because during the A and C
discharge interval, the two inductances,
L1 and L3, are connected in parallel.
So the effective inductance becomes
50 microhenries. This accounts for the
fact that the two currents rising and fall-
ing out of phase with each other, only
partially wash each other out. So that
the delivered current is a fairly steady
4 amperes, but with a slight ripple, as
depicted in Figure 6.
Vs-
Out B
Bt
22 S
On Off
t
Iout
(a)
(b)
Shutdown interval to
prevent shoot through
Bb On Off
t
Vs+ t
Vs-
Out A & Out C
Ab & Ct
22 S
On Off
t
Iout
At & Ct On Off
t
Vs+ t
t
t
Figure 5 (a) Phase B Discharge/Charge; (b) Phase A-C Charge/Discharge
Figure 6 Composite Waveforms Phases A and B-C both delivering current
(b)
Vs-
Out C
Iout
Vs+ t
t
22 S
AN49
AN49U 929
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B
A
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B
A
Thermal Protection
Shown in Shown in Figure 7 is a circuit that could be added to burp the SA306-IHZ via DIS2 (no external latch) if
a thermal overload is detected at TEMP pin 25.
Figure 7 Thermal Protection Circuit
An optional latch may be driven by the SA306-IHZ at TEMP pin 25 and its output could be used to shut down the
converter via the DIS 1 pin 7, and/or shut down the 28 V supply in the event of a cooling failure. External current
monitoring could also be gated to the same DIS1 pin 7 latch to protect the Boost Converter from load faults, etc.
Note that pin 7 should be driven through a diode when current limiting is used (Buck mode only).
Overvoltage Protection (Boost Only)
Over voltage protection is set by Potentiometer R9 so that limiting begins when the output reaches 57 V.
This is essential because if there is no load connected, and the Boost Circuit is run off a 30 V power supply, it would
be possible to obtain a 2 to 1 output voltage plus, a small potential due to the inductance. This could destroy the
SA306-IHZ. R9 should be set to maximum resistance when confgured for Buck mode (Figure 1, Note 5).
Miscellaneous Design Notes
Capacitors C10 and C11 Capacitors C10 and C11 are shown as bulk values in Figures 1, 3 and 4. These may be
distributed between the Vs and the power ground terminals of the IC to provide adequate bypass.
Overvoltage Shutdown - The DIS2 pin 23 is employed to shut down the SA306-IHZ if a 1.7 V threshold at the pin
is exceeded.
Voltage Trimming the Output voltage Adjusting Potentiometer R8 enables trimming the output voltage slightly.
The range is small because the shift in the duty cycle of the PWM (U2, U3) is small. The output voltage should be
set to nominal with the output load set to one-half of its rated value to minimize the deviation from nominal under
all load conditions.
Measuring the Phase Currents Any of the phase currents can be measured by monitoring the voltage at the
Ia, Ib, and Ic pins using a scope while the Boost Circuitry is confgured as a negative converter and with the output
loaded.
Input Voltage is Limited to 30 V An input voltage above 30 V is not recommended without full characterization of
the application. This is due to the fact the maximum duty factor is 50% and the output could conceivably rise above
the 60 V rating of the SA306-IHZ under transient conditions.
Other Voltage and Current Options It should be noted that the 30 V zener D3 could be changed to a 12 V zener
(approximately) to confgure a 20 V to 32 V and a 12 V, 8.5 A converter, for example.
Buck Negative Converter Application of power should be done via inrush limiting circuitry due to the nominal 450
F input capacitance (input transient LC "ringing" 60V maximum).
References
2. 3-Phase Switching Amplifer Application Note #46, www.cirrus.com
3. TLC555 LinCMOS Timer, www.ti.com
1 f
7.5k
2meg
12k
2N7000
from Vs+
to SA306-IHZ DIS2
from SA306-IHZ TEMP
1N4148
.001 f
NOTE: Figure 1, Note 5
current limiter is required
for Buck Negative
Converter only to limit
restart current.
AN50
930 AN50U
AN50 Optimizing Power Delivery
in PWM Motor Driver ICs
Thermal Behavior of Single-Phase, Three-Phase Single-Chip
PWM Amplifers SA57-IHZ, SA306-IHZ
Contents
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Device Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Optimizing Thermal Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Optimizing Motor Commutation Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Balancing the Electrical Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Defning a Movement Profle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Cooling Options and Results with the 64-pin QFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SMT Mounting without Heatsink in Low-Power Applications . . . . . . . . . . . . . . . . . . . . . . . . . 7
SMT Mounting with Thermal Pad and Heatsink for Mid-Range Power Applications . . . . . . . 9
Flipped-Over SMT Mounting with Heatsink for High-Power Applications. . . . . . . . . . . . . . . 11
Comparisons of Low-Power, Mid-Range Power and High-Power Test Boards . . . . . . . . . . 13
High Power Heat Sinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Dissipation Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Appendix Derivation of Maximum Power and Thermal Dynamic Values . . . . . . . . . . . . . . . 22
SMT Mounting Without Heatsink in Low-Power Applications. . . . . . . . . . . . . . . . . . . . . . . . 22
SMT Mounting with a Thermal Pad and Heatsink for Mid-Range Power Applications. . . . . 23
Flipped-Over SMT Mounting with Heatsink for High-Power Applications. . . . . . . . . . . . . . . 24
JUL 2009
APEX AN50UREVA
Optimizing Power Delivery in PWM Motor Driver ICs
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Introduction
The Apex SA306-IHZ is an advanced 3-phase single chip amplifer, designed for use as an independent power
stage to drive 3-phase brushless DC motors. It incorporates a 3-phase PWM amplifer that accepts six independent
control signals. This enables a designer to choose from a wide variety of control signals as appropriate for the com-
mutation method chosen.
This Application Note discusses differences in the thermal behavior of the device relating to mounting techniques,
methods of modulation of the power stage and examines some techniques to improve system performance and
overall effciency.
In order to choose the appropriate thermal design for a particular application and for the basic dimensioning of the
heatsink, the calculation of the frst-order thermal approximation is a good starting point. There are some applica-
tion specifc aspects to be taken into account before starting the basic system design. This Application Note covers
some of these basic design steps, data and ideas to carry forward so the design can achieve the best results.
Device Overview
Both the SA306-IHZ and SA57-IHZ devices incorporate all of the sub-systems necessary to drive a brushed or
brushless DC motor under the control of an MCU or DSP. At maximum output these devices are capable of safely
operating motors approaching 0.5 hp. Like many traditional motor drive products, SA devices integrate control, pow-
er supply, gate drive and power stage into a single IC. Unlike competing devices, this series is specifcally designed
for MCU or DSP control and integrate features that enable implementation of modern commutation techniques, re-
sulting in higher effciency drive stages. Both SA306-IHZ and SA57-IHZ devices consist of major blocks, as shown
in Figure 1. The primary difference between the two devices is the number of phases supported; the SA306-IHZ
supports three phases while the SA57-IHZ supports two.
A key feature of this series is the ability to directly control the output FETs. This enables modern commutation
schemes such as feld-oriented, vector-oriented, and sinusoidal to be implemented within the controller with no in-
BRUSHLESS
MOTOR
Vs (phase A)
PGND (A&B)
Current
monitor
Signals
Sensor Hall Sensors
or
A
B
C
OUT A
OUT B
OUT C
PGND (C)
GND
Vs (phase B&C)
Vs +
Sensing
circuits
GND
SGND
Gate
Control
Control
Logic
Fault
Logic
TEMP
I
LIM
/DIS1
SC
Ia
Ic
Ib
V
DD
PWM
Signals
DIS2
SGND
At
Ab
Bt
Bb
Ct
Cb
Microcontroller
or DSC
Figure 1. System Block Diagram using the 3-Phase SA306-IHZ Device
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tervening circuitry. This architecture simplifes circuit design and reduces EMC/EMI. These devices take the inputs
for each gate and provides buffering and drive to the companion FET.
Another signifcant feature is built-in current sense. Current sense is available for each of the phases from a sepa-
rate output pin. The output current of the sense pins is ~1/5000th of the phase current. The current sense pins
provide direct, real-time feedback to the controller. Current sense is performed at the high-side only. Sensing of
low-side currents under braking or fyback conditions is not supported.
Over-temperature, short-circuit and current limit are also implemented. These fault signals provide important feed-
back to the system controller which can safely disable the output drivers in the event of a fault condition. These
topics are discussed in greater detail in Reference 3.
Both the SA306-IHZ and SA57-IHZ implement a cycle-by-cycle current limit scheme. This allows variable user-
defned current limit thresholds without damage to the device. However, even in this mode, the user must consider
and plan for excessive current excursions which could result in excessive power dissipation.
The architecture of the SA306-IHZ and SA57-IHZ devices enables the designer to confgure dynamically-changing
current limiting in the device in response to changing system operating conditions. The SA306-IHZ or SA57-IHZ
data sheets specify a peak current of 17 amperes. However, if desired the designer can choose to lower this limit
or to disable the feature altogether.
and the inrush current must be considered. For example, a 1 A continuous motor might require a drive amplifer that
can deliver well over 10 A PEAK in order to provide the required start-up torque. The cycle-by-cycle current limit
feature enables the SA57-IHZ/SA306-IHZ to safely and easily drive a wide range of brush and brushless motors
through a startup inrush condition. With limited current, the starting torque and acceleration are also limited. The
plots in Figure 2 illustrate starting current and back EMF with and without current limit enabled.
More information on these and other features of the SA306-IHZ and SA57-IHZ can be found in the product data
sheets, as well as any associated Application Notes listed in the Reference section found at the end of this docu-
ment.
Optimizing Thermal Performance
All power devices, from FETs and IGBTs to large microprocessors, dissipate power in the form of heat. For devices
whose primary purpose is power conversion or power transmission appropriate management of heat is the key to
determining how much power can be safely processed by the device. This fact applies to specifcation limits as well.
A device may be rated for 5 A continuous but the system designer must always take care that the power lost in the
form of heat does not result in damage to the device.
It must be noted that total output power and total power dissipation are dependent on both the output current and
operating voltage. For all mounting techniques discussed in this Application Note the effect of voltage and current
levels will produce variations in power dissipation. For example, graphs of low power operation show heat dissipa-
tion for a given output power. Because power dissipation follows the formula P=I
2
R, increasing operating voltage
to the highest practical limit will result in greater output power at a given current (internal power dissipation). Con-
versely power dissipation can be reduced for a given output power by increasing voltage and reducing current.
Time, Milliseconds
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Time, Milliseconds
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LIMITED BACK EMF
(a) (b)
Figure 2. Motor Current Behavior at Startup (a) Without cycle-by-cycle current limit.
(b) With cycle-by-cycle current limit
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Graphs are generally not provided for multiple combinations of
current and voltage. Rather the emphasis is on the calculation of
power dissipation and thermal resistance, thus enabling the de-
signer to calculate die temperature for the system's combination
of voltage, current, and heat sinking.
Shown in Figure 3 is an infrared image of a SA57-IHZ driving a
brushed DC motor with a continuous current of 3 A at a supply
voltage of 24 V. The numbers mark the local temperatures of the
design. The high and low-side FETs of the active half-bridge can
clearly be seen as white dots, representing a temperature of ap-
proximately 110C. This picture shows the temperature gradients
across the silicon.
The heat generated at the two hot-spots spreads over the silicon
area. The result is a core temperature of approximately 90C.
The red area represents the heat slug of the IC. This temperature
is nearly equal to the core temperature of the silicon. The heat is
transferred to the heatsink on the backside (yellow) and in this
case to the top and bottom layer (green) of the PCB, then dis-
sipated into the ambient air. (Note that the apparent temperature
difference of the screws is the result of emissivity differences be-
tween the screws and the rest of the test system. In steady-state
operation the screws are approximately the same temperature as the heatsink).
Optimized Motor Commutation Methods
The ON-resistance of the power FETs is the primary contributor to heat generation within a motor drive. In calculat-
ing the power lost to the ON resistance we use the standard power formula P=I
2
R, where I =the current flowing
through the motor and R =the ON-resistance of the IC. As the SA57-IHZ and SA306-IHZ offer direct access to
each single FET, it is possible to use alternative commutation techniques to increase the system performance and
to reduce thermal loads.
The best example for a simple system optimization is sinusoidal commutation of a 3-phase brushless DC motor.
This method offers increased efficiency and reduced power dissipation. Alternate types of commutation are more
feasible now that virtually every motor control system has some type of micro-controller or DSP/DSC available.
4.608
4.096
3.584
3.072
2.560
2.048
1.536
1.024
.512
0
-.512
-1.024
-1.536
-2.048
-2.560
-3.072
-3.584
-4.096
-4.608
Single FET Control
Phase B
Dual FET Control
Phase B/C
Single FET Control
Phase C
Dual FET Control
Phase C/A
Single FET Control
Phase A
Dual FET Control
Phase A/B
Dual FET Control
Phase C/A
Single FET Control
Phase A
Dual FET Control
Phase A/B
Single FET Control
Phase B
Dual FET Control
Phase B/C
Single FET Control
Phase C
P
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D
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C
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a
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1
2
-
B
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V
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(
B
I
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)
60 120 180 240 300 360
Low-Side MOSFETS
High-Side MOSFETS
Rotor Angle
Figure 3. Infrared picture of a SA57 running
at 3 amperes at 24 volts.
Figure 4. Power and voltage behavior in the case of 3-phase sinusoidal commutation.
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Sinusoidal commutation of a 3-phase BLDC motor spreads the generated heat over a wider area of the silicon
than with block commutation. This reduces localized heating in the die. During sinusoidal commutation the current
through the motor is delivered by two high-side FETs and a single low-side FET or, in the next step, by using a
single high-side FET and two low-side FETs. This means that there are always two active FETs in parallel which
decreases the ON resistance of the two parallel conducting FETs. The resulting resistance is not linear because
the on-time of each PWM signal of the two FETs connected in parallel follows a sint/cost relation. (See yellow
areas in Figure 4)
The effective ON resistance across an electric commutation cycle can be calculated by dividing the ON-resistance
value of the parallel high or low side FETs by 2. Using this commutation technique can, in addition to several other
advantages, reduce the thermal load by approximately 10% to15%.
The undissipated power can be used to drive the motor or to reduce the total power consumption. In either case the
overall effciency of the system is increased.
Balancing the Electrical Load
As we have just discussed, the main heat generating contributor is the current fowing through the power FETs.
Because the SA57-IHZ and the SA306-IHZ are high-voltage devices suitable for supply voltages up to 60 V, an in-
crease in the supply voltage can lead to a decrease of the continuous current for a given power level and therefore
to a decrease of the thermal load.
From this point of view, the basic idea is to increase the supply voltage while keeping the continuous current con-
stant to reduce the thermal load. In a pulse-driven system with an inductive load, the relation between voltage and
current is not linear so we have to take a closer look at switching losses and the current characteristics under vari-
ous operation conditions.
An application is balanced when the for-
ward and backward magnetization of the in-
ductor is fully realized within a single PWM
cycle. This should be the normal operating
condition in applications with constant rota-
tion speed and low dynamics, such as fans,
pumps or unidirectional drives. In these ap-
plications, once accelerated, the motor runs
at a constant speed with a constant me-
chanical load.
Shown in Figure 5 are the characteristics
of the voltage and current during a PWM
pulse in a balanced operating situation. The
rising and falling edges of the voltage are
nearly linear within the period given by the
time value for the raising and falling edges
typically 200 nanoseconds. The current
characteristic depends on the technical pa-
rameters of the motor winding. The wind-
ings produce a reverse voltage when the
rising edge occurs. The current reaches its
maximum when the supply voltage and the reverse voltage are more or less equal. The resulting phase shift is
represented by t
VI
. When the supply voltage v
3
is being increased, the phase shift t
VI
becomes wider as shown by
arrow v
1
and the rising edge of the current v
2
appears later. The termination of the duty cycle shuts down the current
immediately and always at the same point in time. So when the supply voltage increases, both curves change in the
directions indicated by the arrows labeled v
1
, and v
2
.
Shown in Figures 6 and 7 are voltage and current (overshoot not visible) plots resulting from a PWM pulse applied
to phase A. Both 10 V and 30 V supply voltages are shown.
When we look at the falling edge of the PWM pulse, we see that the current drops with the same slew rate at a sup-
ply voltage of both 10 V and 30 V, but for a longer time interval because of the higher peak current. This means that
the switching losses increase on the falling edge. At the rising edge of the PWM pulse the current is less, so that the
switching losses on this side have decreased.
Voltage
Current t
(ri se)
t
(fall )
t
(VI)
Time
v
1
v
2
v
3
CycleTermination
Figure 5: Characteristic of voltage and current during a PWM
pulse in a balanced system
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When we compare the total average current over time, we fnd similar values at a supply voltage of 10V and 30V.
Although the peak current at 30 V is approximately 30% higher, the pulse width is 20% shorter and the slope of the
pulse top is steeper than at 10 V. In an overall comparison the average current of both pulses is nearly constant with
slightly increased switching losses.
Because the average current remains similar, the average temperature due to I
2
R losses within the FETs is also
similar. However, because voltage delivered to the motor does increase, there is greater power available to the mo-
tor windings. This fact results in increased effciency by driving motors at higher voltages.
Defning a Movement Profle
In some applications, such as servo drives for positioning or robotics, we fnd a wide variety of specifc operation
modes, including periodic acceleration or stalled motor operation with high torque and low rotational speed. In
these operating modes the system is not balanced since the motor windings are not allowed to achieve complete
forward and backward magnetization within a single PWM cycle.
In these conditions the motor windings can become over energized, or saturated with power. As this begins to occur,
increased motor current no longer produces proportional increases in torque and increased heating can occur in the
FETs of the device. In some cases the motor windings are over energized to obtain the torque required to brake the
mechanical load, resulting in a major change of the current waveform characteristic.
20
10
0
-10
V
D
C
0 10 20 30 40 50 60 70 80 90 100
Microseconds
A
m
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30
20
10
0
-10
0 10 20 30 40 50 60 70 80 90 100
Microseconds
V
D
C
A
m
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s
40
Figure 6. Voltage (green) and current (blue) during a PWM pulse on phase A at a
supply voltage of 10 V DC, a 25 kHz switching frequency and a 50% duty cycle.
Figure 7. Voltage (green) and current (blue) during a PWM pulse on phase A at a sup-
ply voltage of 30 V DC, a 25 kHz switching frequency and a 50% duty cycle.
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In these modes of operation, t
VI
becomes smaller and a high
current peak appears at the raising edge of the PWM pulse as
shown in Figure 8. The more the supply voltage v
3
increases the
higher the current peak v
2
will be. This current peak can reach
multiples of the continuous current.
The plots in Figure 9 depict the relationship between duty cycle,
continuous current and temperature at a supply voltage of 20 V
DC.
By separating the performance graph in Figure 9 into two parts,
the balanced operation (A) and the over energized operation (B)
can be better analyzed. During balanced operation, the current
and voltage waveforms follow the relationships shown in Figure
5. The phase shift t
VI
increases so that the continuous current
and temperature increase only slightly. When the motor winding
starts being over energized (B), t
VI
decreases rapidly as shown
in Figure 8. The current peak at the rising edge of the PWM
cycle increases the total average current and the thermal load.
Over energized conditions normally happen in the 60-70% duty
cycle range. This range corresponds with the knee of the curves
in Figure 9. The exact point is dependent on both the quality of
the motor and the operating condition. The operating condition
with the expected maximal thermal load and its maximal time
interval is the basis for the selection of the best mounting tech-
nique and heat sinking method.
The 64-pin Power QFP package used for the SA306-IHZ and
SA57-IHZ lends itself to different kinds of mounting and heat
sinking options which can be used under different operating
conditions to realize the best results according to performance
and total system cost. In the following sections suggestions are
provided on how to select the best solution for your application.
Cooling Options and Results with the
64-pin QFP Package
The size and orientation of the heatsink must be selected to
manage the average power dissipation of the driver ICs. Applica-
tions vary widely and various thermal techniques are available to
match the required performance. This section discusses several
techniques that are appropriate for different power levels.
The following examples were developed to evaluate different mounting and cooling options and to defne their basic
capabilities. Derivation of maximum power and thermal system dynamics is shown in Appendix A.
Two different sets of tests were conducted on the SA306-IHZ. For the frst set of tests the power devices were
mounted on a PCB with a Digital Signal Controller (DSC). This DSC offers an enhanced motion control interface
and allows a designer to commutate the motor in different ways. For the second set of tests a power test bench was
used to show the effect of steady state currents on power dissipation and thermal performance.
SMT Mounting without Heatsink in Low-Power Applications
The most cost effective way of mounting either of the SA306-IHZ or SA57-IHZ devices is to solder them directly
on a PCB without any further heat sinking components. The heat slug of the 64-pin QFP package offers optimized
heat transfer to the PCB (as shown in Figure 10). The IC package, including the heat slug, can be soldered to the
top layer of the PCB. Beneath the heat slug, several vias can be used to optimize heat transfer to the backside of
the board. The copper area used for the power ground is also used for better thermal coupling to the ambient air.
As part of the tests, semiconductor temperature sensor was placed in the middle of the heat slug area to measure
the backside (maximum) heat slug temperature. At an output power of 20 W, a temperature gradient of 99.6K was
obtained. This indicates that the junction temperature will be approximately 130C at an ambient temperature of
30C. The plots in Figure 11 denote a value of 136C at an ambient temperature of 27C with a total thermal resis-
tance for the system of approximately 5.343 K/W.
Voltage
v
1
v
3
Current
t
(ri se)
t
(fall)
t
(VI)
Cycle
Termination
v
2
v
1
Time
) )
Duty Cycle @ 20V DC [%]
T
e
m
p
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r
a
t
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e
[
C
]
C
o
n
t
i
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o
u
s
C
u
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n
t

[
A
]
Temperature[C]
Continuous Current [A]
A
B
Figure 8. Voltage (green) and current (blue)
during a PWM pulse over energizing a mo-
tor winding
Figure 9. Temperature and continuous cur-
rent vs. PWM duty cycle during a stalled
motor operation
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Using the thermal resistance value, the maxi-
mum output power can be calculated for an appli-
cation covering the industrial temperature range
up to +85C at approximately 9 W. This result is
valid for static operation under the specifc set
of voltage and current conditions. In applications
with frequent accelerations and decelerations it
is important to know the thermal response time.
This value provides an indication for the time re-
quired to transfer a specifc amount of heat from
the die to the backside of the board. Derivations
for calculating thermal resistance and maximum
power dissipation can be found in Appendix A.
Shown in Figure 12 is the temperature character-
istic of the ground plane from the ambient to the
maximum temperature when the motor is driven
continuously at an output power of 9 W.
Conclusion
Although the maximum output power rating of
8 W to 9 W seems low, these devices are still
capable of delivering PEAK currents up to 15 A
for several seconds. In addition, increased voltage or reduced ambient temperature may result in increased power
capability. This makes the SA57-IHZ and SA306-IHZ unusually well suited for applications using gears with high
transmission rates where large mechanical loads have to be accelerated through start-up phase and end at high
speeds with lower power requirements.
This mounting technique is appropriate for smaller, low-power or high-speed drives in cost sensitive applications
such as fans, pumps, scanners, surveillance cameras, labeling machines or paper feeders all where size and
production costs are crucial.
SMT Mounting with Thermal Pad and Heatsink for Mid-Range Power Applications
For applications where higher output power is required for a longer period of time, but ease of production is still a
main design issue, an additional test board was designed where the SA306-IHZ is still mounted in the conventional
manner. However, beneath the IC is a 100mm cut out. A thermal pad is used to transfer the heat from the heat slug
directly to the HS33 heatsink.
The thermal pad is made from a polymer that contains materials chosen for low thermal resistance, such as silver. These
pads remain soft for years and therefore can accommodate any shifting that may occur to equalize between materials
Thermal Response Time at MAX. Output Power
100
120
140
H
e
a
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S
l
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T
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m
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a
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[
C
]
- Common SMT Mounting Technique -
0
20
40
60
80
Time [sec]
t
30
T
30
T
90
t
90
0 160 140 120 100 80 60 40 20
Ground
Plane
Heat
Slug
Temperature
Sensor
HEAT SLUG TEMPERATURE VS.
ELECTRICAL OUTPUT POWER
- COMMON SMT MOUNTING TECHNIQUE -
0
20
40
60
80
100
120
140
160
0 5 10 15 20
Total Electrical Power [W]
H
e
a
t

S
l
u
g

T
e
m
p
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r
a
t
u
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e

[
C
]
Block Commutation
Sinusoidal Commutation
Figure 10. Bottom layer of the PICtail plus test board for
low power applications
Figure 11. Temperature characteristic of the
SA306-IHZ mounted on test board for low-power
applications
Figure 12. Thermal response time at MAX output
power of 9 W
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938 AN50U
with different coeffcients of expansion that is likely to occur due to temperature changes. On the mid-power test board a
2mm thermal pad is used to fll the gap between the heat slug and the heatsink (see Figure 13). The thermal pad chosen
is a Berquist
TM
Gap Pad 5000S35.The cutout area is 10mm x 10mm.
This board design provides three advantages:
The SA306-IHZ is still mounted like a conventional SMT part, including the side-wings of the heat slug.
Thermal coupling is always constant, even if the thickness of the PCBs varies from 1.5mm to 1.7mm.
Accurate placement of the heatsink is not required.
Shown in Figure 14 is the back of the mid-power test board. The 100mm heat slug area (red) has been cut out to accom-
modate the thermal pad. The temperature sensor has been moved to a natural cut out of the HS33 heatsink. The height
of the sensor package is exactly the height of the cut out. The thermal coupling comes about due to the intimate contact
of the package top with the heatsink.
The heatsink is mounted with two screws. Note that the light green area of the heatsink has direct contact with the dark-
green ground plane area. With this mounting technique the total thermal resistance is reduced while the contact area is
increased to ambient air. Although the HS33 heatsink is used on this test board, it is not essential. A thermal pad could
also be used to couple the heat slug to the enclosure to improve the thermal path. The 100mm x 1.5mm thick thermal
pad with its thermal conductivity of 86 W/mK has a thermal resistance of 0.174 K/W. When this value is compared to the
Silicon
Heat Slug
Package Lid
Power FETs
PCB
Dissipated Heat Q
EM
Thermal Pad
HS33 Heatsink
Silicon
Heat Slug
Thermal Pad
Figure 13. Simplifed cross sectional view of the
thermal system of the mid-power test board
Ground
Plane
Heat
Slug
Temperature
Sensor
Figure 14. Bottom layer of the test board for mid-
range power applications
Heat Slug Temperature vs
Electrical Output Power
-
0.
20
40
60
80
100
120
140
160
H
e
a
t

S
l
u
g

T
e
m
p
e
r
a
t
u
r
e

[
C
]
Common SMT with Heatsink and Thermal Pad -
0
.0
.0
.0
.0
.0
.0
.0
.0
0 10 20 30 40 50 60
Block Commutation
0.
Thermal Response Time at MAX Output Power
0
0 20 40 60 80 100 120 140 160
Time [sec]
20
40
60
80
100
120
140
H
e
a
t

S
l
u
g

T
e
m
p
e
r
a
t
u
r
e
[
C
]t
90
T
90
T
30
t
30
Figure 15. Temperature characteristic of the SA306-
IHZ mounted on the test board for mid-range power
applications using a thermal pad and the HS33
heatsink
Figure 16. Thermal response time at output power of
20 W
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previous model with vias, this solution provides less than a 10th of
the thermal resistance.
Using the thermal pad, approximately 51 W of continuous output
power is achieved with die temperatures of approximately +155C
at an ambient temperature of +26C using block commutation. The
maximum power output, up to +85C for this confguration is ap-
proximately 20 W at the chosen voltage and current. With this so-
lution it is possible to double the output power at similar system
temperatures. What is most important is the improved performance
over the short heat path to the heatsink due in part to the low ther-
mal resistance through the thermal pad.
Conclusion
The thermal pad offers easy system assembly and good thermal
performance at moderate power ratings. The short thermal path af-
fords benefts in accelerating heavy mechanical loads for a longer
time. This is an appropriate solution for a wide variety of industrial
applications using gears and with production runs in mid-range vol-
umes.
Flipped-Over SMT Mounting with Heatsink for
High-Power Applications
The third test board uses the same heat sinking method as the Cir-
rus Logic Evaluation Boards DB63R and DB64R. This technique
is also described in the High-Power Heatsinking section.
This time the SA306-IHZ is fipped over and mounted. The
heatsink is then mounted directly onto the heat slug of the IC.
This shortens the thermal path from the IC to the ambient air
and reduces the total thermal resistance of the system to a min-
imum of 1.674 K/W.
Shown in Figure 17 is the assembly of the IC and heatsink on
the test board for high-power applications. The position of the
temperature sensor, the mounting method of the heatsink and
the thermal coupling to the ground plane are still the same. The
only difference is that the SA306-IHZ is fipped over and sol-
dered in a precise cutout from the backside of the board. A pic-
ture of the actual mounting technique can be seen in Figure 20.
As a result of this mounting technique, the characteristics of
the temperatures in Figure 18 become quite linear across the
whole power range. The output power at a die temperature of
135C is approximately 52 W at +25C and approximately 29
W at +85C. This solution provides only a slightly higher maxi-
mum output power than the thermal pad. However, the short
thermal path has its advantages in dynamic applications. The
fast response time between the die and the heat slug provides
benefts in applications where multiple accelerations occur over
short time spans (see Figure 19).
Conclusion
The principal advantage of the fipped-over mounting is that it
provides a short heat path for supporting high dynamic applica-
tions. The free access to the heat slug offers a wide variety of
heat sinking methods and more effective cooling options.
Ground
Plane
Heat
Slug
Temperature
Sensor
Heat Slug Temperature vs
Electrical Output Power
0
20
40
60
80
100
120
140
160
180
H
e
a
t

S
l
u
g

T
e
m
p
e
r
a
t
u
r
e

[
C
]
- Flipped-Over SMT w. Heatsink HS33 -
0 10 20 30 40 50 60 70
Block Commutation
Figure 17. Bottom layer of the test board for
high-power applications
Figure 18. Temperature characteristic of the
SA306-IHZ mounted fipped over on the test
board for high power applications using the
HS33 heatsink
Figure 19. Thermal response time at a output
power of 25 W
Thermal Response Time at MAX Output Power
0
0 20 40 60 80 100 120 140 160
Time [sec]
20
40
60
80
100
120
140
H
e
a
t

S
l
u
g

T
e
m
p
e
r
a
t
u
r
e
[
C
]t
90
T
90
T
30
t
30
AN50
940 AN50U
Comparisons of the Low-Power, Mid-Range Power and High-Power Test Board
The following table compares the benchmark values for each mounting technique in a side-by-side comparison.
Please note that the columns for the maximum output power are rated for ambient temperatures of +25C and
+85C. There is a more detailed chart for the power dissipation derating across ambient temperatures in the Power
Dissipation Derating section.
Table 1. Temperature characteristics of the SA306-IHZ mounted fipped over on the PICtail Plus test
board for high-power applications using the HS33 heatsink
Mounting
Technique
Calculated MAX
Output Power
@ +85C (W)
MAX Output
Power at
Test Voltage
@ +25C (W)
MAX Continuous
Current at Test
Voltage
@ +25C (A)
Total Thermal
Resistance
R
TH
(K/W)
Average Ther-
mal Response
Time k90(K/sec)
Common SMT 9.0 19 0.93 2.789-5.343 1.323
Common SMT with
Pad & Heatsink
19.8 38 2.73 0.628-2.529 1.869
Flipped Over with
Heatsink
23.9 52 4.12 0.801-1.726 2.637
All values in this Section are the result of actual tests under laboratory conditions and should provide an indication
of the capabilities of several design variants. The behavior of these ICs may differ under different design and opera-
tion conditions.
High-Power Heat Sinking
Since the SA306-IHZ is designed for higher power applications, it is also necessary to determine heat sinking fac-
tors that allow for higher power dissipation. Because of the concentration of heat as a result of power density, it is
important to use heatsink types that provide short thermal paths. For this reason large extrusions with fns on wide
centers have not been included in this evaluation.
Dissipation capacity with two types of aluminum extrusions were evaluated. The HS33 is a small heatsink, 0.4" x
0.4" x 1.5", that has four fns on 0.118-inch centers. This confguration places all four fns directly under the heat
slug of the SA306-IHZ package. The HS33 heatsink is shown in Figure 20. This heatsink is used on the Cirrus Logic
DB64R evaluation board for the SA306-IHZ.
The second heatsink in Figure 21 is a pin confguration with dimensions of 1" x 2" x 2". The pins are 0.070" in
diameter on 0.137" centers. This highly effective heatsink provides multiple heat paths directly under the silicon.
Because of its size, it is capable of safely dissipating much higher power levels than the HS33.
The test set-up for the HS33 used the Cirrus Logic DB64R evaluation board with an 8 resistive load. To increase
power, the DC voltage across the board and load were increased. This set-up does not fully simulate the operation
of a motor. However, it does allow stable temperatures to be achieved, thus facilitating measurement. This set-up
met the goal of allowing power dissipation and die temperature measurements with varying heatsinks.
Figure 20. HS33 Finned Heatsink with SA306-IHZ Figure 21. Pin Heatsink with SA306-IHZ
AN50
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Table 2. Results of Thermal Testing
Confguration Orientation Convection
Dissipated
Power (W)
Output
Power @
85% Eff-
ciency (W)
Heatsink
Temp MAX
(C)
Junction
Temp MAX
(C)
Thermal
Resis-
tance
(C/W)
HS33 and
PCB
Horizontal,
HS down
Natural 7.5 42.5 139 145 16
HS33 and
PCB
Vertical,
HS vertical
Natural 9 51 138 146 13
HS33 and
PCB
Horizontal,
HS down
Forced 17 96.3 127 140 6.8
Pin Heatsink
Horizontal,
HS up
Natural 16 90.7 125 141 7.3
Pin Heatsink
Horizontal,
HS down
Forced 39 221.0 79 113 2.3
Five different thermal confgurations were tested, and the results are shown in Table 2. Note that consistent with real
world applications, the differences in test set-up and measurement techniques between this test and the previous
section produce different test results and power capabilities. This is to be expected and shows that designers must
take into account their specifc operating environment when evaluating thermal performance.
Three rows of HS33 data are shown in Table 2. The frst two used convection cooling only. As one might assume,
placing the heatsink in a horizontal position does not produce as effective a cooling surface as placing the heatsink
vertically. With a vertical heatsink under convection conditions the heatsink dissipates 9 W, allowing 50 W of motor
power at a +140C junction temperature. Thermal resistance results with the vertical heatsink measured 13C/W
junction to air.
The third HS33 test was performed using a small fan blowing across the board. The object was to simulate an
enclosed housing with a fan providing outside air, similar to a PC. In this case, dissipation improved to 17 W and
allowing almost 100 W at the motor at 85% effciency. Thermal resistance junction-to-case also improved dramati-
cally to 6.8C/W.
Subsequent testing with this confguration suggests that use of a small fan, in this case a 1" Sunon unit (PN
GM0502PFV1-8, similar to MPU or graphics chip FAN), directed onto the HS33, allows heatsink dissipation in ex-
cess of 21 W and suggesting motor power of approximately 120 W. Under these conditions, die temperature should
not exceed +140C.
For full-power applications, the pin heatsink was tested. The pin heatsink was tested under both convection
and forced-air conditions. The test board and fan can be seen in Figure 22. The fan used was a 2" Sunon (PN
KDE1205PHV2) capable of 595 linear feet per minute of air fow. The retaining screws for the fan also hold the
heatsink and the device in place on the board. The test confguration for the pin heatsink used a modifed PCB
layout and a 4 resistive load.
Under normal convection conditions, this heatsink was able to dissipate 16 W of power, allowing motor power of 91
W, similar to the HS33 with airfow. However, when using forced air with this heatsink, power dissipation within the
heatsink increased to almost 40 W, allowing for greater than 220 W of power
to the motor. In addition, the junction temperature dropped to +113C, sug-
gesting this is a high reliability confguration with room for increased power
output. The junction to air thermal resistance also improved dramatically,
measuring 2.3C/W. With some increase in die temperature and a well de-
signed system, the pin heatsink in a forced air confguration will allow the full
48 W and 5 A rating of the device.
Use of a heatsink does increase system cost. In some cases, the designer
may fnd that a small amount of airfow across an HS33-type heatsink pro-
vides suffcient dissipation and lower costs versus a larger heatsink. How-
ever, for full power dissipation, use of a large heatsink with forced air may
be necessary.
Figure 22. Pin heatsink and test
board with fan attached
AN50
942 AN50U
Power Dissipation Derating
To provide high-reliability operation, the die temperature must be kept to a safe level. The designer must consider
total power, heatsink capability and ambient temperature in order to make appropriate system choices. The graph
in Figure 23 shows derating curves for power. Curves are given for load power versus heatsink and ambient tem-
peratures. In addition, curves are given for single-sided and double layer PCBs.
Figure 23 also shows that below +25C the SA306-IHZ can operate above 300 W, assuming die temperatures are
held to a reliable level. Above +30C improved heat sinking must be employed or the device may need to be de-
rated. Again, actual power capability is a function of operating voltage, effciency, ambient temperature and heatsink
capability. Actual derating will vary based on these factors. It should also be noted that the derating of heatsinks
themselves change with temperature and therefore with power dissipation. As shown in Figure 24 for the HS33,
both airfow and ambient temperature play a role in accurately modeling the dissipation capability of the heatsink.
Conclusion
Applications vary widely and various thermal techniques are avail-
able to match the required performance. The size and orientation
of the heatsink must be selected to manage the average power dis-
sipation of the IC. Standard PCB mounting techniques enable these
devices to dissipate as much as 9 W. The use of a heat pad or the
patent-pending mounting technique shown in Figure 20, with the
SA306-IHZ inverted and suspended through a cutout in the PCB, is
adequate for power dissipation exceeding 20 W.
In free air, mounting the PCB perpendicular to the ground, so that the
heated air fows upward along the channels of the fns, can provide
improved cooling. In applications in which higher power dissipation
or lower junction or case temperatures are required, a larger heat-
sink or circulated air can signifcantly improve performance. A pin
heatsink can successfully dissipate the thermal energy generated
when driving motors in excess of 200 W. By using the techniques
in this Application Note, the SA57-IHZ and SA306-IHZ can provide
long-term, reliable motor control in a very compact package.
References
3. 3-Phase Switching Amplifer Application Note SA306-IHZ, AN46, www.cirrus.com
SA306-IHZ Output Power Dissipation Derating
0
50
100
150
200
250
300
350
0 20 40 60 80 100 120 140
Ambient Temperature, Ta (C)
L
o
a
d

P
o
w
e
r
,

P

(
W
)
HS33 and PCB Horizontal/HS
down - Natural
HS33 and PCB Vertical/HS
vertical - Natural
down - Forced
PIN Heatsink Horizontal/HS
down - Forced
Note: Careful consideration of operating current is
required so not to exceed maximum wire temp of +150 C.
0
50
100
150
200
250
300
350
down - Natural
HS33 and PCB Vertical/HS
vertical - Natural
down - Forced
up - Natural
down - Forced
Typical SMT device on a
Double-Sided Board
Typical SMT device on a
Single-Sided Board
T
H
E
R
M
A
L

R
E
S
I
S
T
A
N
C
E

(
C
/
W
)
AIR FLOW (LFM)
200 1000 800 600 400
0.00
20.00
15.00
10.00
5.00
1.0 5.1 4.1 3.0 2.0
AIR FLOW (m/s)
Figure 23. Load power derating curves for ambient temperature, Ta (C)
Figure 24. Heatsink thermal resistance
versus air fow
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Appendix A Derivation of Maximum Power and Thermal Dynamics Values for
PCB Based Tests
Section A.1 Result for Common SMT Mounting with Heatsink in Low-Power Applications
The total thermal resistance of the common SMT model for a SA306-IHZ is 4.98 K/W (Kelvin per watt). To calculate
the maximum output power for this mounting technique without specifc values for voltage or current, we have to
transform the equation:
(12)
Where:
T
0
= SA306-IHZ or SA57-IHZ junction temperature
T
2
=ambient air temperature
P
E
=electrical output power
The plots in Figure 7 denote a value of +136C at an ambient temperature of +27C with a thermal resistance of
approximately 5.343 K/W. The difference is due to the fact that the factor includes the thermal resistance into the
ambient air and is therefore a combined value for (A)
-1
+R
th
.
When we use the value for the thermal resistance of the PICtail
TM
Plus Test Board to calculate the maximum output
power for an application covering the whole industrial ambient temperature range up to +85C, the maximum con-
tinuous output power is approximately 9 W:
(13)
Where:
T
0
= SA306-IHZ orSA57-IHZ junction temperature
T
2
R
T
=total thermal conductivity
P
MAX
=MAX electrical output power
Shown in Figure 12 is the temperature characteristic of the ground plane from the ambient to the maximum tem-
perature, when the motor is driven continuously at a maximum power of 9 W. For later comparisons the focus is on
the transfer ratio T
30
/t
30
and T
90
/t
90
, described by a quotient K for the slew rate from the cold state to 30% and
90%, respectively, of the maximum temperature.
The slew rate quotient k is an indication for the quality of the dynamic behaviour of the thermal system:
(14a)
(14b)
Where:
k =slew rate quotient in Kelvin per second
= temperature difference in Kelvin
t = duration in seconds
T
0
=temperature at time t
0
T
1
1
T
0
- T
2
=( +R
th
) R
DS(ON)
I
C
2
1
A
T
0
- T
2
=( +R
th
) P
E
1
A
P
MAX
=
T
0
- T
2
R
t
P
MAX
= =9.4W
135C - 85C
5.343
K
W
k = =
T
1
- T
0
t t
1
- t
0
k
30
= =1.317
54.5C - 26.8C
21 sec
K
sec
k
90
= =0.988
109.7C - 26.8C
84 sec
K
sec
AN50
944 AN50U
Section A.2 SMT Mounting with a Thermal Pad and Heatsink for Mid-Range Power Applications
The frst order approximation of the thermal model gives a thermal resistance of 2.678 K/W. The following equation
is used to verify the real value of the complete system:
(15)
Where:
T
0
T
2
P
E
=electrical output power
R
t
Next is to fnd the maximum power rating to cover the total industrial range for ambient temperatures up to +85C
at a maximum die temperature of +135C.

(16)
Where:
T
0
T
2
R
t
P
MAX
=Max. electrical output power
The chart in Figure 12 shows the improvements of the thermal dynamics. The slew rate quotients k
30
and k
90
are:
(17a)
(17b)
Where:
k = slew rate quotient in K/s
T
0
0
T
1
1
=( +R
th
)
1
A
T
0
- T
2
=( +R
th
) P
E
1
A
T
0
- T
2
P
E
R
t
= =2.529
155C - 26C
51W
K
W
P
MAX
=
T
0
- T
2
R
t
P
MAX
= =19.8W
135C - 85C
2.529
K
W
k = =
T
1
- T
0
t t
1
- t
0
k
30
= =1.938
55.8C - 26.8C
15 sec
K
sec
k
90
= =1.407
114.7C - 26.8C
63 sec
K
sec
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Section A.3 Flipped Over SMT Mounting with Heatsink for High-Power Applications
The following equations are used to calculate the estimated maximum output power for ambient temperatures of
+85C:
(18)
Where:
T
0
= SA306-IHZ/SA57-IHZ junction temperature
T
2
R
t
P
MAX
=MAX electrical output power
Using this mounting technique, the following values are obtained for k
30
and k
90
:
(19a)

(19b)
Where:
k = slew rate quotient in K/s
T
0
0
T
1
1
k = =
T
1
- T
0
t t
1
- t
0
k
30
= =2.638
58.5C - 26.8C
12 sec
K
sec
k
90
= =1.792
121.8C - 26.8C
53 sec
K
sec
IMPORTANT NOTICE
All other brand and product names in this document may be trademarks or service marks of their respective owners. Berquist is a trademark of the Berquist Company.
PICtail is a trademark of Microchip Technology, Inc.
P
MAX
=
T
0
- T
2
R
t
P
MAX
= =28.97W
135C - 85C
2.096
K
W
=( +R
th
)
1
A
T
0
- T
2
P
E
R
t
= =2.096
135C - 26C
52W
K
W
AN51
946 AN51U
AN51 Thermal Modeling of Power Devices
in a Surface Mount Confguration
Introduction
This Application Note demonstrates how to develop a thermal model for power ICs. It then explains how the model-
ing of power ICs can be used to calculate the maximum power delivery possible during normal operation.
The Basic Model
Shown in Figure 1 is the cross-section of a power IC with the heat generating sources identifed in red. The heat
passes through the silicon substrate, a copper heat slug, and then into the foil layer on top of the printed circuit
board. The heat transfers through the copper-plated vias which pass through the board transversely. The heat f-
nally exits the assembly through the copper foil layer on the bottom of the printed circuit board. The frst step is to
defne the heat source and represent the various paths by thermal resistance values and then calculate the power
losses inside the power stage. The power loss over a time interval of t represents the amount of heat power fed
into the system.
Figure 1: A Cross-sectional view of an IC thermal system
The copper foil directly beneath the heat slug serves as the thermal junction between the heat slug and the PCB.
The PCB laminate itself is essentially a thermal isolator because of its high thermal resistance; therefore several
vias are used to improve the heat transfer through the PCB. The bottom of the PCB features a large copper area
(ground plane) because of its excellent thermal conductivity and the ability to optimize the heat dissipation into
the air. This assembly can be depicted by the simple equivalent circuit shown in Figure 2. The Ohms Law of heat
transfer is similar to the Ohms law for an electric circuit. Therefore we use familiar electrical symbols to describe
the relations, as depicted in Figure 2.
Defning the Heat Source
The heat generated and depicted as Q
O
in Figure 1 is attributed to three sources:
Heat due to the current fow in the active devices of the logic circuit
Heat generated as the result of switching losses
Heat caused by the ON-resistance of each of the power FETs
Thermal Modeling of Power Devices in a
Surface Mount Configuration
AUG 2009
APEX AN51UREVA
Silicon
Heat Sl ug
Package Lid
Ground
Plane
PCB
Vias
Dissipated Heat Q
EM
Generated Heat Q
O
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The heat expressed as power developed in the logic circuit is more or less stable at 0.025 W. This is less than
one hundredth of the power caused by the power FETs and therefore can be neglected in our analysis. The switch-
ing losses depend on the switching frequency, duty cycle and the supply voltage and will not be discussed in the
following examples. However, in some applications it may be necessary to account for these losses in the heat
source model.
The third source of heat is the most signifcant: The power FETs exhibit an ON resistance (RDS
ON
)when turned on.
Therefore a voltage drop occurs across the FETs, caused by the current fowing through them. The amount of heat
expressed as power dissipated by this process can be expressed by the familiar relationship:
P
L
=V
D
x I
C
(1)
Where:
P
L
=power loss
V
D
= voltage drop across the power FETs
I
C
=continuous current
In normal block commutation, two of the FET switches one high-side FET and one low-side FET are ON dur-
ing each commutation step in the rotation sequence. To calculate the voltage drop, use the sum of the two ON-
resistances the one high-side and one low-side FET:
V
D
= (R
DS(ON)High Side
+ R
DS(ON)Low Side
) x I
C
(2)
Where:
V
D
= voltage drop across the two ON power FETs
R
DS
= ON-resistance of a single ON power FET
I
C
=continuous current
Silicon R
SL
Heat Slug R
HS
Copper Layer (Lid) R
CLT
Copper Layer (Bottom) R
CLB
Vias R
Vi
to R
VN
PCB R
PCB
Total
Thermal
Resistance
R
TH
Figure 2: Equivalent thermal circuit for the power IC circuit board confguration
AN51
948 AN51U
When these two terms are combined, it is possible to calculate the complete power loss:
P
L
=(I
C
)
2
(R
DS(ON)High Side
+ R
DS(ON)Low Side
)
P
L
=(I
C
)2 R
DS(ON)
(3)
The values for the ON-resistance can be found in the product data sheets of the SA306-IHZ and SA57-IHZ. The typ-
ical data given for the high-side (300 milliohms) and low-side (250 milliohms) power FETs is used for the calculation.
To be able to use this equation for the defnition of the heat source, power must be transformed into energy. The
energy is defned by:
Q
0
=P
L
x t (4)
Where:
Q
0
=dissipated energy
P
L
=power losses
t = time interval
The equivalent term for the thermal energy of the heat source is:
Q
th
=
th
x t (5)
Where:

th
=heat energy

th
=heat current
t = time
With the defnition given for the heat current
th
= T/R
th
we obtain:
(6)
Where:
Q
th
=heat energy
T = temperature gradient
R
th
=total thermal resistance
t = time
The last thing to do is to set these two increments of energy equal so that the dissipated electric energy becomes
the input to the thermal system:
(7)
Taking a closer look at equation (7), there is a term for the temperature gradient T as a function of the continu-
ous current fowing through the power FETs. Both terms in the brackets are constant because neither the electric
(R
DS(ON)
) nor the thermal resistance (R
th
) of the FET changes during operation. Also note that the temperature gradi-
ent will increase as the square of the continuous current. Equation (7) can be used to calculate the temperature
gradient between the junction and ground-plane temperature that will be caused by a specifc continuous current,
or conversely as the maximum continuous current as a function of a specifc temperature difference.
Q
th
= t
T
R
th
P
L
t = t
T
R
th
Q
0
= Q
th
I
C
2
R
DS(ON)
=
T
R
th
T = (R
DS(ON)
R
th
) I
C
2
AN51
AN51U 949
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Calculating Total Thermal Resistance
Before using equation (7), the total thermal resistance of the system layers needs to be calculated. The thermal
resistance depends on the layers and materials used. The thermal resistance of a solid state body is defned as:
(8)
Where:
R
th
= total thermal resistance
s = length of the thermal path
= thermal conductivity of the material

th
= thermal density of the material
A = cross-section of the object
For further calculations, the middle term will be used containing the thermal conductivity to calculate the thermal
resistance. According to the Ohms law of heat transfer theory the complete equation for the model shown in Figure
1 is:
(9)
Where:
R
th
= total thermal resistance
R
SL
= resistance from the FETs into the silicon
R
HS
= resistance from silicon into the heat slug
R
CLT
= resistance from the heat slug into the top layer of the PCB
R
Vi
= resistance from the top layer of the PCB into a single via
R
PCB
= resistance from the top layer of the PCB into the PCB
R
CLT
= resistance from the PCB via into the bottom layer of the PCB
Shown in Table 1 are the parameters used for the calculation of the total resistance:
Table 1. Parameters for the Calculation of the Total Thermal Resistance
Component Length (x10
-3
meter) Cross-Section A(x 10
-6
m
2
) Thermal Conductivity (W/mK)
Silicon 0.38 15.8/23.7 148
Heat Slug 1 100 220
Top Layer 0.035 100 384
PCB 1.5 100 0.26
Via 1.5 6.28x10
-8
384
Bottom Layer 0.035 2160 384

Shown in Table 2 are the results for the thermal resistance of each component in the heat fow path. Note that in
Table 2, the value for the thermal resistance for the SA57-IHZ and the SA306-IHZ differ.
Table 2. Total Thermal Resistance
Component
Thermal Resistance R
th
(K/W)
SA57-IHZ SA306-IHZ
Silicon 0.405 2.264
Heat Slug 0.045
Top Layer 0.912 x 10
-3
PCB +Vias 2.479
Bottom Layer 0.140 x 10
-3
Total 2.913 K/W 2.789 K/W
R
th
= =
th
s
A
s
A
R
th
=R
SL
+R
HS
+R
CLT
+
(
+
)
-1
+R
CLB
1
R
PCB
1
R
Vi
n
i=1
AN51
950 AN51U
Why Heat Spread Depends on the Number of Active FETS
When a brushed DC motor is driven, only a single pair of FETs is in use continuously. In this case the area for heat
transfer into the silicon is simply twice the area of a single FET structure. However, in the case of a 3-Phase BLDC
motor application, the pairs of FETs change in accordance with the electric angle of the rotor. This means that all
six FETs become active in an alternating sequence. Although only two FETs are active at any instant, the heat is
spread over three times the area. However, in practical tests it has been determined that the effective heat transfer
has the value of the single half-bridge operation divided by 2.
Active and Passive Heat Dissipation
A model is now in place that transfers the heat from the power FETs through several layers into a ground plane on
the backside of the PCB. An additional step is required to calculate the heat that dissipates into the ambient air. This
heat transfer from a solid state body into air is defned by:
Q
EM
= A T t (10)
Where:
Q
EM
=dissipated heat energy
= heat transfer coeffcient
A =heat dissipating area
T = temperature gradient between air and dissipating ground plane area
t = time
To calculate the results for a static operation, it makes sense to eliminate time. The equation for the heat energy can
be easily transformed into an equation for heat power by eliminating the time factor:
P
H
= A T (11)
The value for the heat power is given by equation (11). The thermal current multiplied by the input power (=electric
power losses) gives the amount of power in watts that has to be dissipated into air.
Therefore:
T
1
= (R
DS(ON)
x R
th
) I
C
2

with T
1
=temperature gradient between the junction temperature and the temperature of the backside of the PCB
and:

with T
2
=temperature gradient between the temperature of the backside of the PCB and the ambient air.
The thermal system is in balance, when the dissipated heat power P
H
is equal to the electrical power losses P
L
:
Where:
T
1
= (R
DS(ON)
x R
th
) x I
C
2
T
0
- T
1
= (R
DS(ON)
x R
th
) x I
C
2
These two equations can be combined into:
(12)
Where:
T
0
T
2
With this equation it is possible to calculate the temperature offset as a function of a specifc continuous current,
and vice versa.
T
2
= P
H
1
A
1
A
P
H
= P
L
A T
2
= R
DS(ON)
I
C
2
T
2
= R
DS(ON)
I
C
2
T
1
T
2
= R
DS(ON)
I
C
2
1
A
T
0
- T
2
=
(
+R
th

)
R
DS(ON)
I
C
2
1
A
AN51
AN51U 951
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Calculating the Maximum Continuous Current
To calculate the maximum continuous current, transform equation (11) into:
(13)
The absolute maximum current can be calculated for a maximum continuous junction temperature T
0
of +135C and
a maximum ambient temperature T
2
of +85C. At these operating conditions, a maximum temperature gradient can
be set of 50K into equation (13).
When the temperature gradient is set, the value for the absolute maximum continuous current depends only on
the heat-transfer coeffcient . The other parameters such as the size of the heatsink, the thermal resistance and
the ON-resistance, are fxed by the system design. However, the heat transfer coeffcient is not a fxed constant
and can vary according to the air movement. Commonly there are three main ranges for defned for different fow
speeds along a metal area:
Static (still air): 3.5 to 35 (inside a case)
Passive cooling: 23 to 70 (convection)
Active cooling: 58 to 290 (fan)
For valid dimensioning it makes sense to calculate the frst-order approximation for a worst case scenario; there-
fore, the lower value should be used for each cooling alternative.
5. References
1. SA57 Pulse Width Modulation Amplifer Data Sheet, www.cirrus.com
2. SA306 Pulse Width Modulation Amplifer Data Sheet, www.cirrus.com
3. 3-Phase Switching Amplifer Application Note SA306, www.cirrus.com
3. Optimizing Power Delivery in PWM Driver ICs, Application Note AN50, www.cirrus.com
IMPORTANT NOTICE
I
C
=
(T
0
- T
2
)
(
+R
th

)
R
DS(ON)

-1
1
A
952
Technical Seminar
Precision Power Analog Technical Seminar
Written by the dedicated team of Apex Precision Power
TM
applications engineers at Cirrus Logic,
this technical seminar puts a wealth of precision power analog circuit design expertise right on
your desktop. This how to seminar is a powerful learning tool when used in combination with the
Apex Precision Power design software tool. Download the entire workbook content, or select by
individual topic, at www.cirrus.com/ts.
Simplify Your
Circuit Design
Simplify Your
Circuit Design
LEARN MORE AT
www.cirrus.com/ts
innovation
innovation
Real World Issues
El ectri cal Li mi tati ons
Slew Rate Saturation
Current Limit Common Mode
Amplifier Protection
Input Output
Power Supply
Safe Operating Area
Thermal
Second Breakdown
Output/Voltage Limits
Stability and Compensation
Gnd-Loop: supply lines,
output stage, grounding
Loop Stability
Open Loop Phase Margin
Rate-of-closure 1/b Techniques
Real World Stability Tests
Where Theory Meets Reality
High Speed Techniques
Speed Versus Bandwidth
Real World Applications
(Single Supply, Bipolar Supply,
Asymmetrical Supply)
Motion Control
ATE: programmable
power supplies
Sources: AC/DC
Deflection: electromagnetic,
electrostatic
Piezo Drives
Pulse Width Modulation
Amplifiers
Theory
Applications
Precision Voltage References
Understanding the Subtleties
How to Select
953
G
H
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F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Power Design Software Tools,
Spice Models
Precision Power Design
Software Tool and SPICE Models
Simplify the Power Analog Circuit Design Process
The Apex Precision Power
TM
Design Software Tool utilizes Microsoft
TM
Excel to create a self-documenting
spreadsheet program to help you simplify and automate the many painstaking calculations and graphical
interpretations required to design power analog circuits. You can use Power Design to address a number of
electrical considerations including power levels, loop stability, current limit, and frequency sweeps for PWM
filters and loads.
Power Design is available as a linear tool, a PWM tool or in combination. Highlights include an Inductor Design
sheet and an analysis tool for PWM filter components with a default parasitic calculator. The PWM tool also
provides biasing and stability covering both voltage and current control topologies.
Need help specifying an amplifier or a heatsink? Use Power Designs product selector tool by entering the de-
sired volts, amps and frequency. This tool can also be used for heatsink selection and for determining air flow
calculations based on thermal resistance and package requirements.
Download these tools in their entirety, or select by topic of interest:
1. Entire software tool program
2. Linear software tool only
3. PWM software tool only
4. SPICE models for linear amplifiers
5. SPICE models for PWM amplifiers
EE Friend, a supplement to Power Design
This software combines lookup tables and formulas with the ability to calculate the specifics of your job. A wire
table is fine, entering size, distance and amps to get voltage drop is better. This idea is carried over to circuit
analysis, material properties, conversion of units, geometry and math solutions, and working with resistors,
capacitors and inductors. It also has a few items for the model shop.
LEARN MORE AT
www.cirrus.com/ts
innovation
innovation
954
Power Design Technical Library
Precision Power Design Library
The Apex Precision Power product library of technical articles and white papers provides in-
depth design knowledge on a broad list of precision power analog design topics. Available on-
line, this library represents more than two decades of engineering expertise developed through
interaction with customers and their product applications. Sample topics include:
Tame Your High-Speed Switching Amplifer Circuit Designs:
Learn How to Use PWM Switching Amplifers in Motor Control and Audio Applications
Thermal Issues Count in High-Power Amplifer Design:
Designers can make sound decisions for dissipating the heat by choosing devices, heatsinks and
circuits that will realize the smallest, best-performing design.
Power Op Amps Solve Defection-Yoke Drive Problems:
Power op amps provide the ability to position beams in any desired position as well as the ability to
retain a steady-state position. Putting both the power and signal stages in one compact package af-
fords space/weight savings, and the lower parts count contributes to reliability.
Design Techniques for MOSFET Power Op Amps:
Simple circuit design techniques applied to new MOSFET power op amps product high linearity and
bandwidth without sacrifcing accuracy and stability
Modify Power Supply to Enhance Performance
Even low cost, high quality power supplies can achieve improved performance
LEARN MORE AT
www.cirrus.com/ts
innovation
innovation
Index 955
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Subject Index
A
Absolute Maximum Specifcations ................................................................................................................ 680
AC Power Dissipation ....................................................................................................................684, 710, 819
Accessories Vendors .................................................................................................................................... 866
Accessories .................................................................................................................................................. 629
Accuracy of Current Limit ..................................................................................................................... 681, 714
Active Loads ................................................................................................................................................. 708
Amplifer Mounting ..........................................................................................................................687, 717, 792
Amplifer Stability ........................................................................................... 689, 731, 733, 753, 770, 827, 847
Analog Construction Techniques .................................................................................................................. 792
Apex Quality ....................................................................................................................................................11
Application Note Subject Reference ............................................................................................................. 678
Asymmetric Supply Operation .............................................................................................................. 709, 757
Audio Amplifer ...................................................................................................................................... 755, 829
Automating Design Tasks .......................................................................................................819, 827, 837, 847
B
Balncing Electrical Loads ............................................................................................................................. 934
Bandwidth-Gain Trade-offs ................................................................................................................... 730, 736
Beat the Discrete Circuit ............................................................................................................................... 215
Bias Current Matching Resistor .................................................................................................................... 733
Biasing PWM Amplifers................................................................................................................................ 851
Bidirectional Control on a Single Supply ............................................................................................... 694, 757
Boost Voltage ................................................................................................................................................ 914
Bridge Circuit Basics, Linear ................................................................................................................ 694, 753
Bridge Circuit Basics, PWM .......................................................................................................................... 794
Bridge Circuit with a Single Supply ....................................................................................... 694, 701, 755, 758
Bridge Circuits Increase Output Power ..........................................................................................................711
Bridge for Audio .............................................................................................................................696, 711, 755
Bridge with Unipolar Output.......................................................................................................................... 754
Bridge, Efficient use of Power Supplies .........................................................................................................711
Bridge, Transimpedance ....................................................................................................................... 695, 699
Buck-Boost Applications ............................................................................................................................... 923
Brushless Motor Drivers ............................................................................................................... 880, 890, 902
Butterworth PWM Filtering .................................................................................................................... 804, 837
C
Cable Capacitance .......................................................................................................................................741
CAD Coordinates of the TO-3 Package ........................................................................................................ 660
Cage Code ..................................................................................................................................................... 17
Cagejacks ..................................................................................................................................................... 644
Capacitive Loads ...........................................................................................................................741, 770, 829
Common Mode Voltage Biasing Resistors ............................................................................................ 688, 758
Compensating V to I Circuits ................................................................................................................ 738, 832
Composite Amplifers ..................................................................................................................... 745, 777, 831
Subject Index Subject Index
956 Index
Subject Index
Construction Techniques .............................................................................................................................. 792
Contact Information ...................................................................................................................... 2, Back Cover
Converting PWM to Analog .......................................................................................................... 794, 804, 837
Corporate Directory .......................................................................................................................................... 2
Current Control .............................................................................................. 695, 697, 708, 721, 725, 754, 855
Current Limit ................................................................................................................................................. 713
Current Mirrors .............................................................................................................................................. 723
Current Output Bridge .......................................................................................................................... 695, 699
Current to Voltage Conversion .............................................................................................................. 702. 707
Customer Service ............................................................................................................................................. 8
Cycle by Cycle Current Limit ......................................................................................................................... 892
D
Data Sheet Explanations .............................................................................................................................. 680
DC Power Dissipation ............................................................................................................683, 710, 819, 844
Defection Circuits .................................................................................................................. 697, 722, 725, 737
Design Aids.....................................................................................................................678, 819, 827, 837, 847
Die Form Products ........................................................................................................................................ 503
Dont Go Discrete .......................................................................................................................................... 215
Driving Capacitive Loads ...............................................................................................................741, 770, 829
DSP Interface ............................................................................................................................................... 886
E
EE Friend ...................................................................................................................................................... 953
Efficient Power Supplies with a Bridge ..........................................................................................696, 711, 757
Efficient Step Down With High Delta V.......................................................................................................... 853
Electromagnetic Defection .................................................................................................... 695, 697, 725, 754
Electrostatic Defection ................................................................................................................................. 695
Evaluation Kits .............................................................................................................................................. 521
External Phase Compensation ..................................................................................................... 689, 730, 736
F
Fault Latching High Power PPS .................................................................................................................... 702
FAX Numbers ................................................................................................................................................... 2
Feedback Zero Compensation ......................................................................................................................742
Filter Design for PWMs ......................................................................................................................... 804, 837
Flyback Diodes and Motors .......................................................................................................................... 769
Foldover Current Limiting ..................................................................................................................... 714, 728
G
Gain Switching .............................................................................................................................................. 780
General Operating Considerations ............................................................................................................... 679
Grade Comparison and Availability ................................................................................................................. 13
Ground Loops ....................................................................................................................................... 689, 734
H
Half Bridge PWM Opertion ........................................................................................................................... 853
H-Bridge Driver ............................................................................................................................................. 794
Heads-up-Display Defection ........................................................................................................................ 698
Heatsink Holes ...................................................................................................................................... 687, 863
Heatsinking Amplifers ............................................................................................ 686, 717, 792, 819, 837, 863
Heatsinking, High Power............................................................................................................................... 940
Heatsinks .............................................................................................................................................. 632, 863
High Delta V Step Down .............................................................................................................................. 853
High Voltage Power Supplies ........................................................................................................................ 867
High Voltage Support Components .............................................................................................................. 775
How the PA03 Works .................................................................................................................................... 701
Howland Current Pump in a Bridge ...................................................................................................... 695, 699
Index 957
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Subject Index
I
Improving DC Accuracy .........................................................................................................744, 780, 784, 831
Increasing Output Power ...................................................................................................................... 709, 794
Initial Power-up, op amp Prototyping ............................................................................................................ 679
Initial Power-up, PWM Prototyping ................................................................................................................ 841
Ink Jet Piezo Drivers ......................................................................................................................................874
Integrator with an Op Amp ............................................................................................................................ 860
Isolation Resistor for Stability ............................................................................................................... 779, 829
K
Kelvin Sensing Programmable Power Supply ............................................................................................... 707
L
Liability ............................................................................................................................................................. 2
Linear Motor Drive .........................................................................................................................................811
Load Lines ............................................................................................................................................ 763, 820
Loop Stability vs Non-Loop Stability ............................................................................................................. 733
Low Pass PWM Filtering ....................................................................................................................... 804, 837
M
Magnetic Bearing Drive ................................................................................................................................ 812
Magnetic Defection ............................................................................................................... 695, 697, 725, 754
Marking information ...................................................................................................................................... 652
Mating Sockets ............................................................................................................................................. 644
Maximum Power Rating ................................................................................................................................ 717
MCU Interface............................................................................................................................................... 886
Military/Industrial Screening Comparison ....................................................................................................... 13
Mission Stament ............................................................................................................................................... 9
MOSFETs Ease SOA Limitations ................................................................................................................. 727
Motor Commutation .............................................................................................................................. 892, 933
Motor Drive Power Dissipation ...............................................................................................................711, 768
Motor Drive with PWM .................................................................................................................................. 800
Motor Drive, High Speed, High Power .......................................................................................................... 701
Motor Drive .................................................................................................................................... 115, 768, 855
Motor Position Control .................................................................................................................................. 692
Motor Reversal .......................................................................................................................................711, 768
Mounting Power Amplifers .............................................................................................................687, 717, 792
N
Noise Gain Compensation .............................................................................................................744, 773, 831
O
Op Amp as an Integrator ............................................................................................................................... 860
Op Amp Basics ............................................................................................................................................. 802
Optimizing the Power Supply ........................................................................................................................ 709
Optoelectronic Position Control .................................................................................................................... 692
Ordering Information ......................................................................................................................................... 8
Output Impedance of Power Amplifers ..................................................................................................716, 741
Output Stage Oscillations ..................................................................................................................... 689, 734
P
PA02 Design Ideas ....................................................................................................................................... 272
PA03-Inside the Package .............................................................................................................................. 701
PA75 Design Ideas ....................................................................................................................................... 371
Parallel Operation ......................................................................................................................................... 789
Patents .............................................................................................................................................................. 2
PCB Layout Considerations .......................................................................................................... 689, 735, 792
PIC18F2331 Microcontroller ........................................................................................................................ 885
Piezo Drive ........................................................................................................................................... 754, 770
958 Index
Subject Index
Piezoelectric Actuators ................................................................................................................................. 869
Pin 1 Location ............................................................................................................................................... 652
Plotting Load Lines ............................................................................................................................... 763, 820
Position Control ............................................................................................................................................ 692
Power Booster Applications .................................................................................................................. 724, 777
Power Derating ............................................................................................................................................. 942
Power Design Tool ..................................................................................................................819, 827, 837, 847
Power Dissipation Driving Motors ..........................................................................................................711, 768
Power Dissipation with PWMs .............................................................................................................. 798, 844
Power Dissipation with Reactive Loads .........................................................................................684, 710, 819
Power Dissipation ..................................................................................................................682, 710, 819, 844
Power Supplies, High Voltage ................................................................................................................ 867, 776
Power Supply Bypassing ...................................................................................................................... 680, 733
Power Supply Efficiency of the Bridge ...........................................................................................696, 711, 757
Power Supply Optimum Voltage ................................................................................................................... 709
Product Index ................................................................................................................................................ 955
Programmable Active Loads ......................................................................................................................... 708
Programmable Power Supply......................................................................................................... 702, 707, 724
Protection and SOA in Bridge Circuits .......................................................................................................... 753
PWM Audio ................................................................................................................................................... 146
PWM Basics ................................................................................................................................................. 794
PWM Half Bridge Operation ......................................................................................................................... 853
PWM Motor Drive ......................................................................................................................................... 800
PWM Noise Reduction ......................................................................................................................... 804, 837
PWM Topologies ........................................................................................................................................... 849
PZT Drive ............................................................................................................................. 754, 726, 770, 772
Q
QML-PRF-38534 Qualifcation ........................................................................................................................ 12
Quality at Apex ................................................................................................................................................11
R
Rate of Closure & Stability .................................................................................................................... 735, 772
Reactance Chart............................................................................................................................................. 22
Reactive Load Lines ..................................................................................................................... 684, 763, 820
Reactive Loads Increase Power Dissipation ................................................................................................. 710
Read this Prior to Designing ................................................................................................................ 678, 679
Reducing PWM Noise .......................................................................................................................... 804, 837
Reliability and Mean-Time-to-Failure .................................................................................................... 685, 717
Remote Sensing Programmable Power Supply ............................................................................................ 707
Resistive Load Lines..................................................................................................................... 684, 765, 820
Resistor Isolation for Capacitive Loads ................................................................................................. 779, 829
RoHS Compliance .......................................................................................................................................... 15
S
Sales Support ................................................................................................................................................... 8
Saturation Voltage and Boost Pins ............................................................................................................... 728
Second Sourcing .......................................................................................................................................... 216
Selectable Gain PZT Drive ........................................................................................................................... 782
Sensorless Commutation ............................................................................................................................. 892
Single Supply Bridge .................................................................................................................... 694, 755, 758
Single Supply Operation ........................................................................................................ 709, 755, 757, 785
Sleeving Pins ........................................................................................................................................ 716, 863
SOA and MOSFETs ..................................................................................................................................... 727
SOA and Motors ....................................................................................................................................711, 768
SOA Graph Meaning ............................................................................................................................ 681, 763
SOA Testing and Measuring ................................................................................................................. 683, 765
Sockets ......................................................................................................................................................... 644
Soft Start ....................................................................................................................................................... 927
Software for Design ................................................................................................ 678, 819, 827, 837, 847, 953
Solar Panel Tester ......................................................................................................................................... 708
Index 959
G
H
I
F
E
D
C
B
A
G
H
I
F
E
D
C
B
A
Subject Index
Speed Control ....................................................................................................................................... 695, 800
Spice Models ................................................................................................................................................ 953
Stability Considerations, Linear ............................................................................. 689, 731, 733, 770, 827, 903
Stability Considerations, PWM ..................................................................................................................... 847
Stability Tests ..........................................................................................................................................747, 774
Step Down Regulation .................................................................................................................................. 853
Switching Amplifer, 3-Phase ........................................................................................................................ 890
Switching Gain .............................................................................................................................................. 689
T
Table of Contents .............................................................................................................................................. 3
Tachometer Feedback .......................................................................................................................... 694, 801
Technical Seminar ........................................................................................................................................ 952
Technical Support ..................................................................................................................................... 8, 678
Telephone and Fax Numbers ............................................................................................................................ 2
Temperature and Current Limit ............................................................................................................. 681, 719
Temperature and Reliability .................................................................................................................. 685, 733
Thermal Behavior ......................................................................................................................................... 930
Thermal Capacity ......................................................................................................................................... 719
Thermal Management .................................................................................................................................. 717
Thermal Modeling .................................................................................................................................. 717. 946
Thermal Shutdown can Help ........................................................................................................................ 946
Thermal Washers or Grease................................................................................................................. 686, 717
Thermal Washers ...........................................................................................................................647, 687, 863
TO-3 Pin Coordinates ................................................................................................................................... 660
Topologies for PWM Amplifers ..................................................................................................................... 849
Torque Motor Drive ....................................................................................................................................... 855
Torque Specifcations for Mounting ............................................................................................................... 687
Trademarks ....................................................................................................................................................... 2
Transient Voltage Protection ......................................................................................................... 680, 688, 775
Transimpedance Bridge ........................................................................................................................ 695, 699
Tutorial on Op Amp Basics ........................................................................................................................... 802
Tutorial on PWM Basics ................................................................................................................................ 794
U
Unipolar Output Bridge ................................................................................................................................. 754
Unsymmetrical Power Supplies ............................................................................................................ 709, 757
V
Vboost Improves Saturation Voltage ............................................................................................................. 728
Vendors of Accessories ................................................................................................................................ 866
Voice Coil Motor Drive ...................................................................................................................................811
Voltage Boosters ........................................................................................................................................... 914
Voltage to Current Conversion ....................................................................... 695, 697, 708, 721, 725, 754, 855
Voltages Required for Magnetic Defection ................................................................................................... 698
W
Washers, Thermal...................................................................................................................647, 696, 687, 863
Waveforms Typical of Magnetic Defection ................................................................................................... 698
Where is Pin 1? ............................................................................................................................................ 652
Where to fnd support components ............................................................................................................... 866
White Papers ................................................................................................................................................ 954
Product
Data Book
Volume
15
POWER ANALOG ICs,
MODULES AND HYBRIDS
LEARN MORE AT
www.cirrus.com
Accessories, Product Marking,
Packaging Outlines
Evaluation Kits
G
Applications Notes
H H H
Subject Index, Application Note
Cross Reference
I H I
Linear Ampliers, Power Boosters
F
F
F
G
G
E
E
E
D
D
D
C C C
PWM Ampliers
C CC
Voltage References
C
B
B
B
General Information, Customer Service,
Table of Contents
A
G
H
I
F
E
D
C
B
A
A A
.15
.09
.1
.075
.01
.02
.03
.04
.05
.06
.07
10
1
4
5
8
50
40
30
20
15
.2
.9
6
7
9
3
1.5
2
2.5
3.5
.8
.3
.4
.5
.6
.7
38 50 44 56 700 7280 90 100 200 150 300 350 450 600 900 1200
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Supply Voltage
.015
11
38 50 44 56 700 7280 90 100 200 150 300 350 450 600 900 1200
MSA240
MSA260
MP39
MP103
MP108
MP230
MP240
MP111
MP38A
MP39A MP108A
MP38
MP400
SA08
SA60
SA01
SA09
SA50
SA03
SA12
SA57
SA306
SA57A
SA306A
SA53
SA303
PA51A
PA16
PA02
PA73
PA01
PA74
PA76
PA09
PA51
PB50
PA04
PA12A
PA93
PA92
PB51A
PB58A
PA74A
PA76A
PA61
PA61A
PA13
PA12
PA13A
PA10
PA05
PA50
PA50A
PA52
PA52A
PA03
PA89
PA94
PA95
PA84
PA90
PA88
PA83
PA08
PA08V
PA78
PA79
PA81J
PA82J
PA97
PA96
PB51
PB58
PA15
PA15A
PA85
PA91
PA98
PA07
PA10A
PA119
PA12H
PA60
PA75
PA69
PA86
PA162
PA240/PA241/PA243
PA107
Linear Switching Open Frame
Linear
Open Frame
Switching
LEARN MORE AT
www.cirrus.com/ts
PRECI SION POWER ANALOG DESIGN TOOLS
Cirrus Logic provides customers with dedicated technical support for its family of Apex Precision Power

products. Our team of power analog applications engineers has developed a comprehensive set of design
tools that put a wealth of circuit design expertise right on your desktop.
PRECI SION POWER ANALOG TECHNI CAL SEMINAR
A how to learning tool addressing real world power analog technical issues and product applications.
PRECI SION POWER DESIGN SOFTWARE
A self-documenting spreadsheet program simplifies and automates painstaking calculations and graphical
interpretations required to design power analog circuits.
EE FRIEND DESIGN SOFTWARE
A supplement to the Precision Power Design Software, this tool combines lookup tables and formulas
with the ability to calculate values for a specific application.
SPI CE MODELS
SPICE models available for both linear and PWM amplifiers.
PRECI SION POWER DESIGN LIBRARY
An in depth library of technical articles
and white papers covering a broad list of
design topics based on more than two
decades of customer and product applica-
tions support.
CONTACT US
For product selection assistance or techni-
cal support with Apex Precision Power
products, call 800-546-2739 (in the US
and Canada), via email at apex.support@
cirrus.com, or contact the Cirrus Logic
office in your region. For a complete list of
Cirrus Logic sales representatives and dis-
tributors, please visit the Contacts page at
www.cirrus.com.
PRODUCT SELECTOR MATRI X AMPLIFIERS
LEARN MORE AT
www.cirrus.com
CONTACT US
For product selection assistance
or technical support with Apex
Precision Power products
call 800-546-2739, email
apex.support@cirrus.com,
or contact the Cirrus Logic
office in your region.
For a complete list of Cirrus Logics
sales representatives and
distributors, please visit the
Contacts page at www.cirrus.com.
CIRRUS LOGI C
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0 2 3 5 - V15 - DB - AP P
Product Data Book
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VOLTAGE REFERENCES
PWM AMPLI FI ERS
LI NEAR AMPLI FI ERS
HI GH SPEED LI NEAR AMPLI FI ERS
EVALUATI ON KI TS
ACCESSORI ES
PACKAGI NG
APPLI CATI ON NOTES
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POWER ANALOG ICs,
MODULES AND HYBRIDS
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COMMON MODE VOLTAGE RANGE, pos. +V

COMMON MODE VOLTAGE RANGE, pos. +V

COMMON MODE VOLTAGE RANGE, pos. +V

COMMON MODE VOLTAGE RANGE, pos. +V

COMMON MODE VOLTAGE RANGE, pos. +V

HC PACKAGE (14-pin HERMETIC DIP)

FIGURE 6. COMPENSATING THE AMPLIFIER

so that the closed loop gain A

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