ADC_nalin

# define TB_DIV3 0x3

#include "DSP28x_Project.h"
#include "math.h"
void InitEPwm1Example(void);
void InitADC_curr(void);
interrupt void adc_isr(void);
Uint16 VO;
Uint16 CC;
float VO_ref=2.2000, DCout, err[2]={0, 0}, Duty[2]={0, 0}, a=0.05, d=0.0;
void main(void)
{
InitSysCtrl();
EALLOW;
SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK=1;
SysCtrlRegs.HISPCP.all = 0x3;
EDIS;
//InitEPwm1Gpio();
EALLOW;

/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pull-up on GPIO0 (EPWM1A)
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (EPWM1B)

/* Configure ePWM-1 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be ePWM1 functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B

EDIS;
DINT;
InitPieCtrl();
IER=0x0000;
IFR=0x0000;
InitPieVectTable();
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EALLOW;
PieVectTable.SEQ1INT = &adc_isr;
EDIS;
InitAdc();
InitADC_curr();
IER |= M_INT1;
//IER |= M_INT3;
PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
EINT;
ERTM;
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // synchronize the clocks
EDIS;
InitEPwm1Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;
EDIS;



for(;;)
{
asm("NOP");
}
}
void InitADC_curr(void)
{
AdcRegs.ADCTRL1.bit.ACQ_PS = 0x1;
AdcRegs.ADCTRL1.bit.CPS = 0;
AdcRegs.ADCTRL3.bit.ADCCLKPS = 0;
AdcRegs.ADCMAXCONV.all=0x0000;
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1;
}
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = 1499;
EPwm1Regs.TBPHS.half.TBPHS = 0x0000;
EPwm1Regs.TBCTR = 0x0000;

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
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ADC_nalin
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
//EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV3;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

EPwm1Regs.CMPA.half.CMPA =300;

EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET;
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable Interrupt Generation
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Generate interrupt when counter
equals zero
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_PRD; // Select SOC from from CPMA on
upcount
EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST; // Generate pulse on 1st event

}
interrupt void adc_isr(void)
{
VO = AdcRegs.ADCRESULT0>>4;
DCout = (((float32) VO * 3.0)/4096.0 - 0);
err[1]=VO_ref-DCout;
Duty[1]=Duty[0]+a*(err[1]+err[0]);
// d=Duty[1];

if(Duty[1]<150)
{Duty[1]=150;
}
else if(Duty[1]>1185)
{Duty[1]=1185;
}
d=Duty[1];
EPwm1Regs.CMPA.half.CMPA =d;
CC++;
if(CC>1000)
{ CC=0;
}
err[0] = err[1];
Duty[0] = Duty[1];
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// Reinitialize for next ADC sequence
EPwm1Regs.ETCLR.bit.SOCA = 1;
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;
EPwm1Regs.ETCLR.bit.INT=1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Clear INT SEQ1 bit
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; // Acknowledge interrupt to PIE
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1;
return;
}
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