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  • Codigo VHD

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    Joel Cotrina Sangay
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    codigo vhd

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    3 views7 pages

    Codigo VHD

    Uploaded by

    Joel Cotrina Sangay

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 7

    library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;

    entity detec is
    Port ( CLK,Xin : in std_logic;
    Zout : out std_logic
    );
    end detec;

    architecture
    Behavioral of detec is

    type estado is (s0,s1,s2,s3);
    signal pr : estado := s0 ;
    signal sg : estado;

    begin
    -- parte secuencial

    process (clk)
    begin
    if clk'event and clk='1' then
    pr<=sg;
    end if;
    end process;

    -- fin parte secuencial

    --parte combinacional

    process (pr,Xin)
    begin
    case pr is
    when s0 =>
    IF Xin = '0' THEN
    sg <= s1;
    Zout <= '0';
    ELSE
    sg <= s0;
    Zout <= '0';
    END IF;
    when s1 =>
    IF Xin = '0' THEN
    sg <= s2;
    Zout <= '0';
    ELSE
    sg <= s0;
    Zout <= '0';
    END IF;
    when s2 =>
    IF Xin = '0' THEN
    sg <= s2;
    Zout <= '0';
    ELSE
    sg <= s3;
    Zout <= '0';
    END IF;
    when s3 =>
    IF Xin = '0' THEN
    sg <= s1;
    Zout <= '1';
    ELSE
    sg <= s0;
    Zout <= '0';
    END IF;
    end case;
    end process;
    end Behavioral;








    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity detec is
    Port ( CLK,Xin : in std_logic;
    Zout : out std_logic
    );
    end detec;

    architecture Behavioral of detec is

    type estado is (s0,s1,s2,s3,s4);
    signal pr : estado := s0 ;
    signal sg : estado;


    begin
    -- parte secuencial

    process (clk)
    begin
    if clk'event and clk='1' then
    pr<=sg;
    end if;
    end process;

    -- fin parte secuencial

    --parte combinacional

    process (pr,Xin)
    begin
    case pr is
    when s0 =>
    Zout <= '0';
    IF Xin = '1' THEN
    sg <= s0;
    Zout <= '0';
    ELSE
    sg <= s1;
    END IF;
    when s1 =>
    Zout <= '0';
    IF Xin = '1' THEN
    sg <= s0;
    ELSE
    sg <= s2;
    END IF;
    when s2 =>
    Zout <= '0';
    IF Xin = '0' THEN
    sg <= s2;
    ELSE
    sg <= s3;
    END IF;
    when s3 =>
    Zout <= '0';
    IF Xin = '0' THEN
    sg <= s4;
    ELSE
    sg <= s0;
    END IF;
    when s4 =>
    Zout <= '1';
    IF Xin = '0' THEN
    sg <= s2;
    ELSE
    sg <= s0;
    END IF;
    end case;
    end process;
    end Behavioral;

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