1.

18*18 sequential multiplier

module multipler (clk, rst, A, B, final);
parameter WID! " 18;
input clk;
input rst;
input #WID!$1%&' A, B;
output #(*WID!$1%&' final;
re) #WID!$1%&' mA, mB;
re) #(*WID!$1%&' multipl*, add;
al+a*s ,(posed)e clk)
-e)in
if (rst) -e)in
mA ." /WID!/10-&11;
mB ." /WID!/10-&11;
multipl* ." /(*WID!/10-&11;
add ." /(*WID!/10-&11;
end
else -e)in
mA ." A;
mB ." B;
multipl* ." mA * mB;
add." add 2 multipl*;
end
end
assi)n final " add;
endmodule
It infers Dsp processor alon) +it3 flops.
2. seril in serial out shift register for 32 clock delays
Rtl code
44
//////////////////////////////////////////////////////////////////////////////////
module v_shift_registers_0 (select,si,clk, clken,SO!
"arameter #$%&' ( 32!
"arameter )idth*(+,-0.!
in"ut clk, clken,si!
in"ut +)idth*/*-0.select!
out"ut SO!
reg +#$%&'/*-0. shreg!
al)ays 0("osedge clk
1egin
if (clken
shreg ( 2shreg+#$%&'/2-0.,si3!
end
assign SO ( shreg+select.!
endmodule
//for this shift register tool is inferring O45 SR6(S6$75 8
44ec3 sc3ematic for t3e s3ift re)ister
445. 6ne flop is +orkin) on posed)e and one flop is +orkin) on neded)e +3ic3 is
capturin) t3e noted output of first flop
4444444444444444444444444444444444444444444444444444444444444444444444444444444444
module posed)ene)ed)e(clk,out,d
);
input d,clk;
output re) out;
re) middle;
+ire notmiddle ;
assi)n notmiddle"7middle;
al+a*s,(posed)e clk )
-e)in
middle ."d;
end
al+a*s,(ne)ed)e clk)
-e)in
out."notmiddle;
end
endmodule
ec3nolo)* sc3ematic%
It requires t+o slices alon) +it3 one 89 -ecause all t3e flops in a sin)le slice
are connected +it3 same +ire to t3eir pins and to con:ert from posed)e to ne)ed)e
it requres one lut
;. <;*1 =am +it3 s*nc3ronous read and s*nc3ronous +rite
44=8 code
module ram
(input +rite,read,clk,input datain,input#>%&'address,output re) dataout
);
re) memor*#<5%&'
al+a*s,(posed)e clk)
-e)in
if(+rite )
memor*#address'."datain;
if(read)
dataout."memor*#address';
end
endmodule
44-lock ram
module :?rams?&1 (clk,+e,re,en,addr, di, do);
input clk;
input +e,re;
input en;
input #>%&' addr;
input #51%&' di;
output #51%&' do;
re) #51%&' =A@ #<5%&';
re) #51%&' do;
al+a*s ,(posed)e clk)
-e)in
if (en)
-e)in
if(+e)
=A@#addr'."di;
end
end
al+a*s,(ne)ed)e clk)
-e)in
if(en)
-e)in
if(re)
do ." =A@#addr';
end
end
endmodule
44Block ram
module ram1 (clk,+e,re,en,addr, di, do);
input clk;
input +e,re;
input en;
input #>%&' addr;
input #51%&' di;
output #51%&' do;
re) #51%&' =A@ #<5%&';
re) #51%&' do;
re) readaddress;
al+a*s ,(posed)e clk)
-e)in
readaddress."addr;
if (en)
-e)in
if(+e)
=A@#addr'."di;
if(re)
do."=A@#readaddress';
end
end
endmodule
44tec3sc3ematic
44Distri-uted =A@
module ram1 (clk,+e,re,en,addr, di, do);
input clk;
input +e,re;
input en;
input #>%&' addr;
input #51%&' di;
output #51%&' do;
re) #51%&' =A@ #<5%&';
re) #51%&' do;
al+a*s ,(posed)e clk)
-e)in
if (en)
-e)in
if(+e)
=A@#addr'."di;
if(re)
do."=A@#addr';
end
end
endmodule
44tec3nolo)* sc3ematic
B86AB =A@
1. It is dedicated =A@ on fp)a
(. Cince it is dedicated ,all connections inside it are 3ard+ired, so dela* +ill -e
less, area is less, po+er consumption is also less.
5. Block =A@0s are used for storin) lar)e amount of data.
;. We can )et Block =A@ into our desi)n in t+o +a*s
a. B* Instantiatin) Block =am usin) core )enerator.
-. Inferin) -* +ritin) appropriate !D8 code -* follo+in) codin) )uidelines.
>. Block =A@ is -* default s*nc3ronous read and +rite.
<. If +e use Block =A@ to store small amount of data, remainin) memor* )et
+asted, so +e use Block =A@ for storin) lar)e amount of data.
Distri-uted =A@%
1. It is optional =A@ in fp)a(C8IAD @ in A8B)
(. 9sed to store small amount of data, If +e use Distri-uted =A@ for storin)
lar)e amount of data, t3en more resources (C8IAD @0s) are required as
compared to Block =A@.
5. B* default Distri-uted =A@ is C*nc3ronous +rite and As*nc3ronous
=ead.
;. Cince +e are pro)rammin) t3e Distri-uted =A@(C8IAD @), area is
occupied, dela*s and po+er consumption is more.
>. We can infer t3e Distri-uted =A@ into our desi)n -* follo+in) t3e
appropriate !D8 codin) )uideslines.