Write a VHDL code for a 2x4 Decoder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dec24 is
port ( i : in std_logic_vector(1 downto 0);
o : out std_logic_vector(3 downto 0));
end dec24;
architecture arch24dec of dec24 is
begin
process(i)
begin
case (i) is
when "00" => o<="0001";
when "01" => o<="0010";
when "10" => o<="0100";
when "11" => o<="1000";
when others => o<="0000";
end case;
end process;
end arch24dec;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tb is
end tb;
architecture tb_arch of tb is
component dec24 port ( i : in std_logic_vector(1
downto 0); o : out std_logic_vector(3 downto 0));
end component;
signal i : std_logic_vector(1 downto 0):="00" ;
signal o : std_logic_vector(3 downto 0);

begin
INST1: dec24 port map (i,o);
process
begin
i<=i+"01"; wait for 10 ns;
end process;
end tb_arch;
ENCODER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder55 is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
Enable : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR (1 downto 0));
end encoder55;
architecture Behavioral of encoder55 is
begin
Output(0)<=A(3) or A(1)when Enable='1' else '0';
Output(1)<=A(2) or A(3) when Enable='1' else '0';
end Behavioral;
















Write a VHDL code to convert binary to grey code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bin2grey is
port ( i : in std_logic_vector(3 downto 0);
o : out std_logic_vector(3 downto 0));
end entity;
architecture archb2g of bin2grey is
begin
process(i)
begin
case (i) is
when "0000" => o<="0000";
when "0001" => o<="0001";
when "0010" => o<="0011";
when "0011" => o<="0010";
when "0100" => o<="0111";
when "0101" => o<="0110";
when "0110" => o<="0100";
when "0111" => o<="0101";
when "1000" => o<="1111";
when "1001" => o<="1110";
when "1010" => o<="1100";
when "1011" => o<="1101";
when "1100" => o<="1000";
when "1101" => o<="1001";
when "1110" => o<="1011";
when "1111" => o<="1010";
when others => o<="0000";
end case;
end process;
end archb2g;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity tb is
end entity;
architecture tb_arch of tb is
signal i, o : std_logic_vector(3 downto 0) :="0000";
component bin2grey is
port ( i : in std_logic_vector(3 downto 0);
o : out std_logic_vector(3 downto 0));
end component;
begin
INST1: bin2grey port map(i, o);
process
begin
i<=i+"01"; wait for 10 ns;
end process;
end tb_arch;



FLIPFLOP
D-Flip Flop
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
Port ( d : in STD_LOGIC;
res : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC);
end dff;
architecture Behavioral of dff is
begin
process(clk,res)
begin
if(res='1') then
q<='0';
else if(clk'event and clk='0') then
q<=d;
end if;
end if;
end process;
end Behavioral;

4-bit Register
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg is
Port ( myin : in STD_LOGIC_VECTOR (3 downto 0);
clk1 : in STD_LOGIC;
res1 : in STD_LOGIC;
myout : out STD_LOGIC_VECTOR (3 downto 0));
end reg;
architecture Behavioral of reg is
component dff is
Port ( d : in STD_LOGIC;
res : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC);
end component;
begin
if res1=0 then
myout<=myin;
else
myout<=0000;
end Behavioral;






Experiment No. 5
Write a VHDL code to check whether the Input stream of bits are
divisible by 5

----------------------------------------------------
----------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity div5 is
port (i, clk : in std_logic;
o : out std_logic);
end div5;
architecture arch_div5 of div5 is
signal ns: std_logic_vector (2 downto 0) := "000";
begin
process (clk)
begin
if (clk='1' and clk'event) then
case (ns) is
when "000" => if i='0' then ns<="000";
elsif i='1' then ns<="001";
end if;
when "001" => if i='0' then ns<="010";
elsif i='1' then ns<="011";
end if;
when "010" => if i='0' then ns<="100";
elsif i='1' then ns<="000";
end if;
when "011" => if i='0' then ns<="001";
elsif i='1' then ns<="010";
end if;
when "100" => if i='0' then ns<="011";
elsif i='1' then ns<="100";
end if;
when others => ns<="000";
end case;
end if;
end process;

process (ns)
begin
case (ns) is
when "000" => o<='1';
when "001" => o<='0';
when "010" => o<='0';
when "011" => o<='0';
when "100" => o<='0';
when others=> o<='0';
end case;
end process;
end arch_div5;


-----------------------------------------------------
-----------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tb is
end tb;

architecture arch_tb of tb is
signal i : std_logic;
signal o : std_logic;
signal clk : std_logic := '0';
component div5 is
port (i, clk : in std_logic;
o : out std_logic);
end component;
begin
inst : div5 port map(i,clk,o);
process
begin
i<='1'; wait for 10 ns;
i<='0'; wait for 10 ns;
i<='1'; wait for 10 ns;
i<='1'; wait for 10 ns;
i<='0'; wait for 10 ns;
i<='1'; wait for 10 ns;
end process;

process
begin
clk <= not clk;
wait for 9 ns;
end process;
end arch_tb;
-----------------------------------------------------
-----------------------------------------------------

Output