VHDL

- VHDL la ngon ng mo ta phan cng.

- VHDL viet tat cua VHSIC (Very High Speed Integrated Circuit) Hardware Description
Language
- VHDL khong phan biet ch viet hoa va ch thng.
databus Databus DataBus DATABUS
- VHDL la ngon ng nh dang t do.
if (a=b) then
if (a=b) then
if (a =
b) then
NguyenTrongLuat 1
Thuat ng COMPONENT:
- La khai niem trung tam mo ta phan cng bang VHDL e bieu dien cac cap thiet
ke t cong n gian en 1 he thong phc tap.
- Mo ta component bao gom ENTITY va ARCHITECTURE.
- Mot component co the s dung cac component khac.
d0
d1
y
sel
mux2to1
a
b
z
nand2
NguyenTrongLuat 2
Ma VHDL c ban
LIBRARY
khai bao th vien
ENTITY
thc the
ARCHITECTURE
kien truc
NguyenTrongLuat 3
V du: Ma VHDL mo ta component NAND 2 ngo vao
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;

ARCHITECTURE model OF nand_gate IS
BEGIN
z <= a NAND b;
END model;
a
b
z
NguyenTrongLuat 4
LIBRARY
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- LIBRARY: khai bao th vien ieee
- USE: s dung cac nh ngha goi (package) std_logic_1164
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
ENTITY
- ENTITY: at ten cho entity (nand_gate)
- PORT: khai bao cac chan xuat/nhap
* Ten port (portname): a, b, z
* Kieu port (mode): IN, OUT
* Kieu tn hieu (type): STD_LOGIC
a
b
z
Mo ta cac tn hieu xuat/nhap cua khoi component
NguyenTrongLuat 5
* Cac kieu chan PORT I/0
IN: d lieu i vao entity qua port va co the c oc trong entity.
OUT: d lieu xuat ra ngoai entity qua chan port.
Port OUT khong the oc ve lai entity.
INOUT: la port 2 chieu, cho phep d lieu i vao hoac ra.
BUFFER: tng t port OUT, nhng c phep oc lai bi entity.
IN
IN
IN
OUT
BUFFER
OUT
INOUT
NguyenTrongLuat 6
ARCHITECTURE
ARCHITECTURE model OF nand_gate IS
BEGIN
z <= a NAND b;
END model;
- ARCHITECTURE: at ten cho architecture (model)
Mo ta thiet ke ben trong cua khoi, ch ro moi quan he gia cac ngo
vao va ngo ra.
- Co 3 loai mo ta architecture
* Mo ta cau truc (Structural)
* Mo ta luong d lieu (Dataflow)
* Mo ta hanh vi (Behavioral)
a
b
z
NguyenTrongLuat 7
OI TNG D LIEU (Data object)
* Tn hieu (signal): bieu dien cho cac day ket noi cua mach. No c khai
bao trong phan PORT cua khai bao entity hoac trong phan au trong architecture
(trc BEGIN).
SIGNAL signal_name : signal_type;
* Bien (Variable): c khai bao va s dung trong process. Bien khong phai la
tn hieu logic that.
VARIABLE variable_name : variable_type;
* Hang so (Constant): gi mot gia tr khong c thay oi
CONSTANT constant_name : constant_type;
SIGNAL a : std_logic;
VARIABLE b : std_logic;
CONSTANT max : integer;
Cac oi tng d lieu co the c at gia tr au, khai bao sau phan khai
bao kieu d lieu _type:= value;
CONSTANT max : integer : = 25;
NguyenTrongLuat 8
- Lenh gan tn hieu:
signal_name <= expression;
a <= NOT b AND c;
variable_name := expression;
y := NOT a;
- Lenh gan bien:

- Bien (Variable) la cuc bo trong process.
- Phep gan bien (Variable) cho gia tr tc thi, phep gan cua tn hieu
(signal) b tre (delay)
- Tn hieu (Signal) co the quan sat dang song (waveform), nhng bien (Variable)
th khong.
* S khac nhau gia Tn hieu (Signal) va Bien (Variable)
NguyenTrongLuat 9
KIEU D LIEU (Data type)
- Cac kieu d lieu la ac tnh cua signal, variable,
- Co the tao ra cac kieu d lieu mi bang lenh TYPE hoac SUBTYPE
- Cac d lieu cung kieu mi c gan hoac ket noi vi nhau
* Kieu BIT va BIT_VECTOR:
- BIT co gia tr 0 va 1.
- BIT_VECTOR la day (array) cua BIT.
* Kieu INTEGER
* Kieu BOOLEAN: co gia tr TRUE va FALSE.
* Kieu liet ke (ENUMERATION) do ngi s dung nh ngha.
* Kieu CHARACTER
* . . .
NguyenTrongLuat 10
SIGNAL a: STD_LOGIC;
SIGNAL b: STD_LOGIC_VECTOR(7 DOWNTO 0);
a la tn hieu STD_LOGIC kieu 1 bit
b,c la tn hieu STD_LOGIC kieu bus co 8 bit
* STD_LOGIC:
Value Meaning
X Forcing (Strong driven) Unknown
0 Forcing (Strong driven) 0
1 Forcing (Strong driven) 1
Z High Impedance
W Weak (Weakly driven) Unknown
L
Weak (Weakly driven) 0.
Models a pull down.
H
Weak (Weakly driven) 1.
Models a pull up.
- Don't Care
U Uninitialized
- Co 9 gia tr
- Hu ch khi mo phong
- Ch co 3 gia tr 0, 1, Z la
co the tong hp
SIGNAL c: STD_LOGIC_VECTOR(0 TO 7);
- La kieu tn hieu quyet nh
(co the c lai bang 2 ngo
vao)
NguyenTrongLuat 11
SIGNAL a: STD_LOGIC;
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c: STD_LOGIC_VECTOR(0 TO 3);
SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL e: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL f: STD_LOGIC_VECTOR(8 DOWNTO 0);
a <= 1; -- gia tr gan at gia 1 dau nhay n
a <= b(2); -- a <= b(2),
b <= "0000; -- gia tr gan at gia 1 dau nhay kep
c <= B0000; -- B la ky hieu c so 2 (co the bo)
d <= 0110_0111; -- bieu dien tng nhom 4 bit phan cach _
e <= XAF67; -- X la ky hieu c so 16 (Hex)
f <= O723; -- O la ky hieu c so 8 (Octal)
b <= c; -- b(3) <= c(0), b(2) <= c(1),
-- b(1) <= c(2), b(0) <= c(3)
d(7 downto 6)<= 11;
c(0 to 2)<= e(7 downto 5);
Phep gan tn hieu kieu STD_LOGIC
NguyenTrongLuat 12
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);


a <= 0000;
b <= 1111;
c <= a & b; -- c = 00001111
d <= 0 & 0001111; -- d = 00001111
e <= 0 & 0 & 0 & 0 & 1 & 1 &
1 & 1; -- e = 00001111
Ghep noi chuoi (Concatenation)
NguyenTrongLuat 13
PHEP TOAN (Operator)
* Phep toan Logic (Logical Operator):
NOT AND OR NAND NOR XOR XNOR
S dung cho kieu: bit, bit_vector, boolean, std_logic, std_logic_vector.
* Phep toan quan he (Relationship Operator):
= /= < <= > >=
So sanh 2 toan hang cung kieu va ket qua tra ve kieu boolean
* Phep toan dch (Shift Operator):
SLL SRL SLA SRA ROL ROR
* Phep toan cong (Adding Operator):
+ -
NguyenTrongLuat 14
* Phep toan nhan (Multiplying Operator):
* / MOD REM
* Phep toan dau (Sign Operator):
- +
* Phep toan khac (Operator):
** ABS
* Th t u tien thc hien cac phep toan
** ABS NOT
* / MOD REM
+ - (Dau)
+ - &
= /= < <= > >=
AND OR NAND NOR XOR XNOR
Cac phep toan cung loai khong co u tien, neu can s dung ( )
NguyenTrongLuat 15
MO TA THIET KE (Design description)
MO TA THIET KE
(Design description)
CAU TRUC
(Structural)
LUONG D LIEU
(Dataflow)
HANH VI
(Behavioral)
NguyenTrongLuat 16
MO TA CAU TRUC (Structural description)
- S dung cac khoi component co cap thap hn.
- Cac khoi component nay c ket noi theo th bac.
- Cac component cap thap c khai bao bang lenh COMPONENT, at phan
ARCHITECTURE (trc BEGIN).
- e ket noi component cap thap, thc hien lenh thay the tr so component
(component instantiation) PORT MAP.
COMPONENT and2
PORT (x1,x2:IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
x1
y
x2
* Ket hp v tr (positional association)
* Ket hp theo ten (named association)
Co 2 cach:
NguyenTrongLuat 17
COMPONENT and2
PORT (x1,x2:IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
BEGIN
user1: and2 PORT MAP ( x1 => a, x2 => b,
y => c );
...
* Ket hp theo ten (named association)

COMPONENT component_name
port declarations;
END COMPONENT;
...
Label: component_name PORT MAP (
port_name1 => sig_name1,
port_name2 => sig_name2 );
NguyenTrongLuat 18
COMPONENT and2
PORT (x1,x2:IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
BEGIN
user1: and2 PORT MAP ( a, b, c );
...
* Ket hp v tr (positional association)

COMPONENT component_name
port declarations;
END COMPONENT;
...
Label: component_name PORT MAP (
sig_name1, sig_name2, ... );
NguyenTrongLuat 19
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xor3 IS
PORT ( a, b, c : IN STD_LOGIC;
result : OUT STD_LOGIC);
END xor3;
ARCHITECTURE structural OF xor3 IS
SIGNAL u1_out: STD_LOGIC;
COMPONENT xor2
PORT ( i1, i2 : IN STD_LOGIC;
y : OUT STD_LOGIC );
END COMPONENT;
BEGIN
u1: xor2 PORT MAP ( i1 => a, i2 => b,
y => u1_out);
u2: xor2 PORT MAP ( i1 => u1_out, i2 => c,
y => result);
END structural;
a
b
c
result
VD: Thiet ke XOR 3 ngo vao u1_out
NguyenTrongLuat 20
MO TA LUONG D LIEU (Dataflow description)
- Mo ta luong d lieu di chuyen t ngo vao en ngo ra.
- S dung cac phat bieu ong thi (Concurrent statement):
* Phep gan bang phep toan
- Cac phat bieu nay c thc thi cung thi iem, v vay th t cac phat bieu
la nh nhau
* Phep gan WHEN - ELSE
* Phep gan WITH SELECT - WHEN
* Phep tao GENERATE
NguyenTrongLuat 21
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xor3 IS
PORT ( a, b, c : IN STD_LOGIC;
result : OUT STD_LOGIC);
END xor3;
ARCHITECTURE dataflow OF xor3 IS
SIGNAL u1_out: STD_LOGIC;
BEGIN
u1_out <= a XOR b;
Result <= u1_out XOR c;
END dataflow;
Result <= u1_out XOR c;
u1_out <= a XOR b;
a
b
c
result
u1_out
Phep gan bang phep toan (OPERATOR)
NguyenTrongLuat 22
Phep gan tn hieu theo ieu kien (Condition Signal Assigment)
WHEN - ELSE
signal_name <= value1 WHEN condition1 ELSE
{value2 WHEN condition2 ELSE}
valueN ;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux2to1 IS
PORT ( d0, d1 : IN STD_LOGIC;
sel : IN STD_LOGIC;
y : OUT STD_LOGIC);
END mux2to1;
ARCHITECTURE dataflow1 OF mux2to1 IS
BEGIN
y <= d0 WHEN sel = 0 ELSE d1;
END dataflow1;
d0
d1
y
sel
mux2to1
sel y
0
1
d0
d1
y <= d0 WHEN sel = 0 ELSE
d1 WHEN OTHERS;
VD: Mux2to1
NguyenTrongLuat 23
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xnor2 IS
PORT ( a, b : IN STD_LOGIC;
c : OUT STD_LOGIC);
END xnor2;
ARCHITECTURE dataflow1 OF xnor2 IS
BEGIN
c <= 1 WHEN a = 0 AND b = 0 ELSE
0 WHEN a = 0 AND b = 1 ELSE
0 WHEN a = 1 AND b = 0 ELSE
1 WHEN a = 1 AND b = 1 ELSE
0 WHEN OTHERS;
END dataflow1;
xnor2 a b c
0 0
0 1
1 0
1 1
1
0
0
1
VD: xnor2
a
b
c
NguyenTrongLuat 24
Phep gan tn hieu co chon loc (Select Signal Assigment)
WITH SELECT - WHEN
WITH select_signal SELECT
signal_name <= value1 WHEN const1_of_select_signal,
{value2 WHEN const2_of_select_signal,}
valueN WHEN OTHERS;
d0
d1
y
sel
mux2to1
sel y
0
1
d0
d1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux2to1 IS
PORT ( d0, d1 : IN STD_LOGIC;
sel : IN STD_LOGIC;
y : OUT STD_LOGIC);
END mux2to1;
ARCHITECTURE dataflow2 OF mux2to1 IS
BEGIN
WITH sel SELECT
y <= d0 WHEN 0,
d1 WHEN OTHERS;
END dataflow2;
NguyenTrongLuat 25
WITH select_signal SELECT
signal_name <= value1 WHEN const1_of_select_signal,
{value2 WHEN const2_of_select_signal,}
valueN WHEN OTHERS;
Tham so const_of_select_signal co the bieu dien nhieu
gia tr rieng biet hoac 1 dai gia tr lien tiep.
PORT ( d0, d1, d2, d3 : IN STD_LOGIC;
sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
y : OUT STD_LOGIC );
...
...

WITH sel SELECT
y <= d0 WHEN 001,
d1 WHEN 011 to 101,
d2 WHEN 000 | 111,
d3 WHEN OTHERS;
NguyenTrongLuat 26
xnor2 a b c
0 0
0 1
1 0
1 1
1
0
0
1
VD: xnor2
a
b
c
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xnor2 IS
PORT ( a, b : IN STD_LOGIC;
c : OUT STD_LOGIC);
END xnor2;
ARCHITECTURE dataflow2 OF xnor2 IS
SIGNAL ab : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
ab <= a & b;
WITH ab SELECT
c <= 1 WHEN 00 | 11,
0 WHEN OTHERS;
END dataflow2;
NguyenTrongLuat 27
Phat bieu FOR - GENERATE
GENERATE la cach e tao ra nhieu tnh huong (instance) cho cac phat bieu ong
thi, thng dung cho cac phep gan thay the tr so tng ng component
(component instantitation).
[Name:] FOR index_variable IN range GENERATE
concurent_statements;
END GENERATE [name] ;
g0: FOR i IN 0 to 3 GENERATE
z(i) <= x(i) and y(i+8);
END GENERATE;
xor_array: FOR i IN 7 downto 0 GENERATE
user: xor2 PORT MAP (
x(i), y(i), z(i) );
END GENERATE;
NguyenTrongLuat 28
GENERIC
- La cau truc e a 1 hang so vao trong entity giong khai bao CONSTANT.
- Tien li cua generic la co the s dung no trong phep gan thay the tr so
tng ng component (component instantitation), e s dung cac gia tr hang so
khac nhau khi tham chieu component.
ENTITY entity_name IS
GENERIC (
generic_name1: data_type := default_values;
generic_name2: data_type := default_values;
)
PORT (
port_name: mode data_type;
... )
END entity_name;
NguyenTrongLuat 29
* Phep gan thay the tr so component co GENERIC

Label: component_name
GENERIC MAP (
generic_name1 => sig_name1,
gereric_name2 => sig_name2 );
PORT MAP (
port_name => sig_name);
* Khai bao component co GENERIC
COMPONENT component_name
GENERIC (
generic_name1: data_type := default_values;
...)
PORT (
port_name: mode data_type;
...)
END COMPONENT;
NguyenTrongLuat 30
MO TA HANH VI ( Behavioral description)
- Mo ta s ap ng cua ngo ra theo ngo vao.
- Cac phat bieu tuan t (Sequential statement): cho phep mo ta hoat ong tuan
t cua cac tn hieu
* Phat bieu IF
* Phat bieu CASE
* Phat bieu LOOP
- S dung phat bieu PROCESS cha cac lenh c thc thi tuan t, phu thuoc
vao th t cua no
NguyenTrongLuat 31
PROCESS
- Process thc hien cac lenh ben trong no 1 cach tuan t. V vay th t cua
cac lenh rat quan trong.
- Mot Architecture co nhieu Process. Cac Process la cac phat bieu ong thi
- Process c kch hoat khi co s thay oi cua 1 tn hieu.

[Name:] PROCESS (sensitivity list)
variable declarations
BEGIN
sequential statements
END PROCESS [Name];
Sensitivity list: danh sach cam nhan
Variable declarations: khai bao bien
NguyenTrongLuat 32
* Danh sach cam nhan (sensitivity list):
- Khai bao cac tn hieu dung e kch hoat Process khi tn hieu thay oi (thng
goi la s kien event). Thng la cac tn hieu ngo vao.
- Khi Process c kch hoat th cac phat bieu ben trong process c thc hien
tuan t. Khi thc hien xong phat bieu cuoi cung th Process vao trang thai ch
(suspend).
* Khai bao bien (variable declaration):
Khai bao cac bien cuc bo s dung trong Process
* Phat bieu tuan t :
- at gia BEGIN va END cua Process.
- Gom cac phep gan tn hieu va bien, cac phat bieu tuan t IF, CASE,
LOOP
NguyenTrongLuat 33
Phat bieu IF - THEN - ELSE
IF condition1 THEN sequential_statements_1;
{ELSIF condition2 THEN sequential_statements_1;}
{ELSE sequential_statements_1;}
END IF;
d0
d1
y
sel
mux2to1
sel y
0
1
d0
d1
VD: Mux2to1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux2to1 IS
PORT ( d0, d1 , sel : IN STD_LOGIC;
y : OUT STD_LOGIC);
END mux2to1;
ARCHITECTURE behavior1 OF mux2to1 IS
BEGIN
PROCESS (d0, d1, sel)
BEGIN
IF sel = 0 THEN y <= d0 ;
ELSE y <= d1 ;
END IF;
END PROCESS;
END behavior1;
NguyenTrongLuat 34
Phat bieu CASE - WHEN
CASE select_signal IS
WHEN value1 => sequential_statements_1;
WHEN value2 => sequential_statements_2;
WHEN OTHERS => sequential_statements_N;
END CASE;
d0
d1
y
sel
mux2to1
sel y
0
1
d0
d1
VD: Mux2to1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux2to1 IS
PORT ( d0, d1 , sel : IN STD_LOGIC;
y : OUT STD_LOGIC);
END mux2to1;
ARCHITECTURE behavior2 OF mux2to1 IS
BEGIN
PROCESS (d0, d1, sel)
BEGIN
CASE sel IS
WHEN 0 => y <= d0 ;
WHEN OTHERS => y <= d1 ;
END CASE;
END PROCESS;
END behavior2;
NguyenTrongLuat 35
Phat bieu FOR - LOOP
[Name:] FOR variable_name IN range LOOP
sequential_statements;
END LOOP [name] ;
sqr: FOR i IN 1 to 10 LOOP
a(i) := i*i;
END LOOP sqr;
FOR j IN 3 downto 0 LOOP
IF reset(j) = 1 THEN data(j) := 0;
END IF;
END LOOP;
Tng t nh phat bieu ong thi FOR_GENERATE.
NguyenTrongLuat 36
Phat bieu WHILE - LOOP
i:=0;
WHILE (i<10) LOOP
s <= i;
i := i+1;
END LOOP;
[Name:] WHILE condition LOOP
sequential_statements;
END LOOP [name] ;
NguyenTrongLuat 37
THIET KE HE TO HP BANG VHDL
- He to hp co the c thc hien bang cac phat bieu ong thi (concurent
statement) va tuan t (sequential statement).
- Phat bieu ong thi (concurent staement) c dung trong mo ta cau truc
(structural description) va luong d lieu (dataflow description)
- Phat bieu tuan t (sequent statement) c dung trong mo ta hanh vi (dataflow
description)
NguyenTrongLuat 38
BO CONG
A
D
D
E
R
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY fulladder IS
PORT ( x , y , z : IN STD_LOGIC;
s , c : OUT STD_LOGIC);
END fulladder;

ARCHITECTURE Function OF fulladder IS
BEGIN
s <= x XOR y XOR z ;
C <= (x AND y) OR (y AND z) OR (x AND z);
END Function;
fulladder
x
y
s
z
c
NguyenTrongLuat 39
s = x y z
c = x y + y z + x z
adder4
a3
Cout
Cin
a2
a1
a0
b3
b2
b1
b0
s3
s2
s1
s0
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY adder4 IS
PORT ( Cin : IN STD_LOGIC;
a, b : IN STD_LOGIC_VECTOR(3 downto 0);
s : OUT STD_LOGIC_VECTOR(3 downto 0);
Cout : OUT STD_LOGIC);
END adder4;
ARCHITECTURE Structure OF adder4 IS
SIGNAL c : STD_LOGIC_VECTOR(1 to 3);
COMPONENT fulladder
PORT ( x , y , z : IN STD_LOGIC;
s , c : OUT STD_LOGIC);
END COMPONENT;
BEGIN
stage0: fulladder PORT MAP(a(0),b(0),Cin,s(0),c(1)) ;
stage1: fulladder PORT MAP(a(1),b(1),c(1),s(1),c(2)) ;
stage2: fulladder PORT MAP(a(2),b(2),c(2),s(2),c(3)) ;
stage3: fulladder PORT MAP(a(3),b(3),c(3),s(3),Cout) ;
END Structure;
Thiet ke bo cong 4 bit adder4 s dung fulladder
NguyenTrongLuat 40
Lenh USE ieee.std_logic_signed.all cho phep s dung goi
(package) std_logic_signed, e thc hien phep toan so hoc tren cac tn
hieu std_logic.
Bo cong 4 bit adder4 s dung phep cong so hoc
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
ENTITY adder4 IS
PORT ( Cin : IN STD_LOGIC;
a, b : IN STD_LOGIC_VECTOR(3 downto 0);
s : OUT STD_LOGIC_VECTOR(3 downto 0);
Cout : OUT STD_LOGIC);
END adder4;
ARCHITECTURE Arithmetic OF fulladder IS
SIGNAL sum : STD_LOGIC_VECTOR(4 downto 0);
BEGIN
sum <= (0& a ) + b + Cin ;
s <= sum(3 downto 0) ;
Cout <= sum(4) ;
END Arithmetic;
NguyenTrongLuat 41
BO DON KENH
M
U
X
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux4 IS
PORT (
d0 , d1 , d2 , d3 : IN STD_LOGIC;
s : IN STD_LOGIC_VECTOR(1 downto 0);
y : OUT STD_LOGIC);
END mux4;
ARCHITECTURE Function OF mux4 IS
BEGIN
y <= (NOT s(1) AND NOT s(0) AND d0) OR
(NOT s(1) AND s(0) AND d1) OR
(s(1) AND NOT s(0) AND d2) OR
(s(1) AND s(0) AND d3 );
END Function;
MUX4
d0
d1
d2
d3
s1
s0
y
s1 s0 y
0 0
0 1
1 0
1 1
d0
d1
d2
d3
NguyenTrongLuat 42
ARCHITECTURE Dataflow OF mux4 IS
BEGIN
y <= d0 WHEN s = 00 ELSE
d1 WHEN s = 01 ELSE
d2 WHEN s = 10 ELSE
d3 WHEN OTHERS;
END Dataflow;
WITH s SELECT
y <= d0 WHEN 00,
d1 WHEN 01,
d2 WHEN 10,
d3 WHEN OTHERS;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux16 IS
PORT (
d : IN STD_LOGIC_VECTOR(15 downto 0);
c : IN STD_LOGIC_VECTOR(3 downto 0);
f : OUT STD_LOGIC);
END mux16;
ARCHITECTURE Structure OF mux16 IS
SIGNAL w : STD_LOGIC_VECTOR(0 to 3);
COMPONENT mux4
PORT (
d0 , d1 , d2 , d3 : IN STD_LOGIC;
s : IN STD_LOGIC_VECTOR(1 downto 0);
y : OUT STD_LOGIC);
END COMPONENT;
BEGIN
M0: mux4 PORT MAP (d(0),d(1),d(2),d(3),c(1 downto 0),w(0));
M1: mux4 PORT MAP (d(4),d(5),d(6),d(7),c(1 downto 0),w(1));
M2: mux4 PORT MAP (d(8),d(9),d(10),d(11),c(1 downto 0),w(2));
M3: mux4 PORT MAP (d(12),d(13),d(14),d(15),c(1 downto 0),w(3));
M4: mux4 PORT MAP (w(0),w(1),w(2),w(3),c(3 downto 2),f);
END Structure;
NguyenTrongLuat 43
c3 c2 c1 c0 f
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
d0
d1
d2
d3
d4
d5
d6
d7
d8
d9
d10
d11
d12
d13
d14
d15
Thiet ke MUX 16 1 s dung MUX 4 1
mux16
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux16 IS
PORT (
d : IN STD_LOGIC_VECTOR(15 downto 0);
c : IN STD_LOGIC_VECTOR(3 downto 0);
f : OUT STD_LOGIC);
END mux16;
ARCHITECTURE Structure2 OF mux16 IS
SIGNAL w : STD_LOGIC_VECTOR(0 to 3);
COMPONENT mux4
PORT (
d0 , d1 , d2 , d3 : IN STD_LOGIC;
s : IN STD_LOGIC_VECTOR(1 downto 0);
y : OUT STD_LOGIC);
END COMPONENT;
BEGIN
G0: FOR i IN 0 to 3 GENERATE
MUXES: mux4 PORT MAP (
d(4*i),d(4*i+1),d(4*i+2),d(4*i+3),c(1 downto 0),w(i));
END GENERATE;
M4: mux4 PORT MAP (w(0),w(1),w(2),w(3),c(3 downto 2),f);
END Structure2;
NguyenTrongLuat 44
S dung
GENERATE
BO GIAI MA
D
E
C
O
D
E
R
en x1 x0 y3 y2 y1 y0
0 X X
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 1 0 0
1 0 0 0
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dec2x4 IS
PORT ( en : IN STD_LOGIC;
x : IN STD_LOGIC_VECTOR(1 downto 0);
y : OUT STD_LOGIC_VECTOR(3 downto 0));
END dec2x4;
ARCHITECTURE flow OF dec2x4 IS
SIGNAL
temp: STD_LOGIC_VECTOR(3 downto 0);
BEGIN
WITH x SELECT
temp <= 0001 WHEN 00 ,
0010 WHEN 01 ,
0100 WHEN 10 ,
1000 WHEN 11 ,
0000 WHEN OTHERS;
y <= temp WHEN en = 1
ELSE 0000;
END flow;
NguyenTrongLuat 45
y0
y1
y2
y3
x0
x1
en
dec2x4
ARCHITECTURE flow2 OF
dec2x4 IS
SIGNAL
en_x: STD_LOGIC_VECTOR(
2 downto 0);
BEGIN
en_x <= en & x;
WITH en_x SELECT
f <= 0001 WHEN 100 ,
0010 WHEN 101 ,
0100 WHEN 110 ,
1000 WHEN 111 ,
0000 WHEN OTHERS;
END flow2;
Thiet ke IC DECCODER 74138
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dec138 IS
PORT ( c, b, a : IN STD_LOGIC;
g1,g2a,g2b: IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR(7 downto 0));
END dec138;
ARCHITECTURE flow OF dec138 IS
SIGNAL
data: STD_LOGIC_VECTOR(2 downto 0);
temp: STD_LOGIC_VECTOR(7 downto 0);
BEGIN
data <= c & b & a;
WITH data SELECT temp <= 11111110 WHEN 000 ,
11111101 WHEN 001 ,
11111011 WHEN 010 ,
11110111 WHEN 011 ,
11101111 WHEN 100 ,
11011111 WHEN 101 ,
10111111 WHEN 110 ,
01111111 WHEN 111 ,
11111111 WHEN OTHERS;
y <= temp WHEN (g1 AND NOT g2a AND NOT g2b) = 1
ELSE 11111111;
END flow;
NguyenTrongLuat 46
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dec3to8 IS
PORT (x : IN STD_LOGIC_VECTOR(2 downto 0);
en: IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR(7 downto 0));
END dec3to8;
ARCHITECTURE behavior OF dec3to8 IS
BEGIN
PROCESS (x, en)
BEGIN
y <= 11111111;
IF (en = 1) THEN
CASE x IS WHEN 000 => y(0) <= 0;
WHEN 001 => y(1) <= 0;
WHEN 010 => y(2) <= 0;
WHEN 011 => y(3) <= 0;
WHEN 100 => y(4) <= 0;
WHEN 101 => y(5) <= 0;
WHEN 110 => y(6) <= 0;
WHEN 111 => y(7) <= 0;
END CASE;
END IF;
END PROCESS;
END behavior;
S dung
PROCESS
NguyenTrongLuat 47
Phat bieu
If .
Case .
BO GIAI MA
3 8
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY decode38 IS
PORT ( x : IN STD_LOGIC_VECTOR(2 downto 0);
y : OUT STD_LOGIC_VECTOR(0 to 7));
END decode38;
ARCHITECTURE behavior OF decode38 IS
BEGIN
PROCESS(x)
VARIABLE j: integer;
BEGIN
j := CONV_INTEGER(x);
FOR i IN 0 to 7 LOOP
IF (i = j) THEN
y(i) <= 0;
ELSE y(i) <= 1;
END IF;
END LOOP;
END PROCESS;
END behavior;
S dung
PROCESS
Phat bieu
For . loop
NguyenTrongLuat 48
S dung ham CONV_INTEGER e oi d lieu kieu
STD_LOGIC_VECTOR thanh kieu INTEGER.
e s dung ham nay, trong phan LIBRARY can phai
khai bao goi (package)
- STD_LOGIC_ARITH
- STD_LOGIC_UNSIGNED
BO GIAI MA
3 8
NguyenTrongLuat 49
BO MA HOA U TIEN
E
N
C
O
D
E
R
i3 i2 i1 i0 x1 x0 v
0 0 0 0
0 0 0 1
0 0 1 X
0 1 X X
1 X X X
d d 0
0 0 1
0 1 1
1 0 1
1 1 1
i0
i1
i2
i3
x0
x1
v
encoder
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY encoder IS
PORT ( i : IN STD_LOGIC_VECTOR(3 downto 0);
x : OUT STD_LOGIC_VECTOR(1 downto 0);
v : OUT STD_LOGIC);
END encoder;
ARCHITECTURE flow OF encoder IS
BEGIN
x <= 11 WHEN i(3) = 1 ELSE
10 WHEN i(2) = 1 ELSE
01 WHEN i(1) = 1 ELSE
00 ;
v <= 0 WHEN i = 0000
ELSE 1;
END flow;
WITH i SELECT
x <=00 WHEN 0001 ,
01 WHEN 0010|0011,
10 WHEN 0100
to 0111,
11 WHEN OTHERS;
WITH i SELECT
V <=0 WHEN 0000,
1 WHEN OTHERS;
NguyenTrongLuat 50
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY encoder2 IS
PORT ( i : IN STD_LOGIC_VECTOR(3 downto 0);
x : OUT STD_LOGIC_VECTOR(1 downto 0);
v : OUT STD_LOGIC);
END encoder2;
ARCHITECTURE behavior OF encoder2 IS
BEGIN
PROCESS (i)
BEGIN
IF i(3) = 1 THEN x <= 11;
ELSIF i(2) = 1THEN
x <= 10;
ELSIF i(1) = 1THEN
x <= 01;
ELSIF x <= 00;
END IF;
END PROCESS;
v <= 0 WHEN i = 0000
ELSE 1;
END behavior;
PROCESS (i)
BEGIN
x <= 00;
IF i(1)=1 THEN x <=01;
END IF;
IF i(2)=1 THEN x <=10;
END IF;
IF i(3)=1 THEN x <=11;
END IF;
v <= 1;
IF i=0000 THEN v <=0;
END IF;
END PROCESS;
S dung
PROCESS
NguyenTrongLuat 51
BO SO SANH
C
O
M
P
A
R
A
T
O
R
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY compare IS
PORT (a, b : IN STD_LOGIC_VECTOR(3 downto 0);
aeqb, agtb, altb : OUT STD_LOGIC);
END compare;
ARCHITECTURE behavior1 OF compare IS
BEGIN
aeqb <= 1 WHEN a = b ELSE 0;
agtb <= 1 WHEN a > b ELSE 0;
altb <= 1 WHEN a < b ELSE 0;
END behavior1;
ARCHITECTURE behavior2 OF compare IS
BEGIN
PROCESS (a, b)
BEGIN
aeqb <= 0; agtb <= 0; altb <= 0;
IF a = b THEN aeqb <= 1; END IF;
IF a > b THEN agtb <= 1; END IF;
IF a < b THEN altb <= 1; END IF;
END PROCESS;
END behavior2;
BO SO SANH 4 BIT

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY led IS
PORT ( bcd : IN STD_LOGIC_VECTOR(3 downto 0);
segs : OUT STD_LOGIC_VECTOR(6 downto 0);
END led;
ARCHITECTURE Behavioral OF led IS
BEGIN
PROCESS(bcd)
BEGIN
CASE bcd IS -- abcdefg
WHEN "0000" => segs <= "1111110";
WHEN "0001" => segs <= "0110000";
WHEN "0010" => segs <= "1101101";
WHEN "0011" => segs <= "1111001";
WHEN "0100" => segs <= "0110011";
WHEN "0101" => segs <= "1011011";
WHEN "0110" => segs <= "1011111";
WHEN "0111" => segs <= "1110000";
WHEN "1000" => segs <= "1111111";
WHEN "1001" => segs <= "1111011";
WHEN OTHERS => segs <= "0000000";-- ALL OFF
END CASE;
END PROCESS;
END Behavioral;
BO GIAI MA
LED 7 OAN
B
C
D
T
O
7
S
E
G
S
NguyenTrongLuat 52
THIET KE HE TUAN T BANG VHDL
- He tuan t ch c thc hien bang cac phat bieu tuan t (sequential
statement).
- Thc hien: mach chot, FF, thanh ghi, bo em, may trang thai.
- Bien (Variable) ch ton tai cuc bo trong Process, v vay muon lay gia tr cua
bien ra ngoai Process th ta phai gan bien cho tn hieu (Signal).
NguyenTrongLuat 53
- Trong Process, bien c cap nhat gia tr sau moi phat bieu; con tn hieu ch
c cap nhat cuoi Process.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Dlatch IS
PORT (D, Clk : IN STD_LOGIC;
Q, Qn : OUT STD_LOGIC);
END Dlatch;
ARCHITECTURE behavior OF Dlatch IS
BEGIN
PROCESS (D, Clk)
BEGIN
IF Clk = 1 THEN
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
D
Clk
Q
Q
Dlatch
clk

D

Q
+
Q
+

0 X Q Q
1 0
1 1
0 1
1 0
NguyenTrongLuat 54
MACH CHOT
NguyenTrongLuat 55
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Dflipflop IS
PORT (D, Clk : IN STD_LOGIC;
Q, Qn : OUT STD_LOGIC);
END Dflipflop;
ARCHITECTURE behavior OF Dflipflop IS
BEGIN
PROCESS (Clk)
BEGIN
IF Clkevent AND Clk = 1 THEN
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
D
clk
Q
Q
Dflipflop
FLIP - FLOP
- clkevent phat hien s thay oi tn hieu clk t 0 len 1 hoac t 1 ve 0.
- Goi std_logic_1164 co nh ngha 2 ham (function): rising_edge e phat hien canh len va
falling_edge e phat hien canh xuong cua tn hieu.
IF rising_edge(clk) THEN
NguyenTrongLuat 56
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY DFF IS
PORT (D, Clk, Pr, Cl : IN STD_LOGIC;
Q, Qn : OUT STD_LOGIC);
END DFF;
ARCHITECTURE behavior OF DFF IS
BEGIN
PROCESS (Clk, Pr, Cl)
BEGIN
IF Pr = 0 THEN Q <= 1;
Qn <= 0;
ELSIF Cl = 0 THEN Q <= 0;
Qn <= 1;
ELSIF Clkevent AND Clk = 0 THEN
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
D
Clk
Q
Q
DFF
Pr
Cl
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY regn IS
GENRERIC (n : NATURAL := 4);
PORT (D : IN STD_LOGIC_VECTOR(n-1 downto 0);
Clk, Reset : _VECTORIN STD_LOGIC;
Q : OUT STD_LOGIC(n-1 downto 0));
END regn;
ARCHITECTURE behavioral OF regn IS
BEGIN
PROCESS (Clk, Reset, D)
BEGIN
IF (Reset = '0') THEN
Q <= (others => '0');
ELSIF rising_edge(Clock) THEN
Q <= D;
END IF;
END PROCESS;
END behavioral;
Q <= (Others=> 0) tng ng vi Q <= 0000
GENRERIC (n : NATURAL := 4)
Khai bao generic n la natural (so nguyen dng)
NguyenTrongLuat 57
D
Clk
Q
regn
Reset
n n
Thanh ghi (register)
NguyenTrongLuat 58
BO EM (COUNTER)
S dung bien count e thc hien chc nang bo em
LIBRARY ieee;
USE ieee.std_logic_1164.all
USE ieee.std_logic_unsigned.all;
ENTITY Upcnt4 IS
PORT (Clk, Rst : IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(3 downto 0));
END Upcnt4;
ARCHITECTURE Behavioral OF Upcnt4 IS
BEGIN
PROCESS (Clk, Rst)
VARIABLE count: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
IF Rst ='1' THEN
count := (others=>'0');
ELSIF rising_edge(clk) THEN
count := count + "0001";
END IF;
Q <= count;
END PROCESS;
END Behavioral;
BO EM LEN 4 BIT
co Reset bat ong bo
Bien count c gan cho ngo ra Q cuoi Process,
v bien la gia tr cuc bo trong Process
Rst
Clk
Q0
Upcnt4
Q1
Q2
Q3
LIBRARY ieee;
USE ieee.std_logic_1164.all
USE ieee.std_logic_unsigned.all;
ENTITY Upcnt4 IS
PORT ( Clk, Rst : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 downto 0));
END Upcnt4;
ARCHITECTURE Behavioral OF Upcnt4 IS
SIGNAL count: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
PROCESS (Clk, Rst)
BEGIN
IF rising_edge(clk) THEN
IF Rst ='1' THEN
count <= (others=>'0');
ELSE
count <= count + "0001";
END IF;
END IF;
END PROCESS;
Q <= count;
END Behavioral;
NguyenTrongLuat 59
Bo em co
reset ong
bo
S dung tn hieu count thay cho bien count.
Tn hieu count c gan cho ngo ra Q ben
ngoai Process.
LIBRARY ieee;
USE ieee.std_logic_1164.all
USE ieee.std_logic_unsigned.all;
ENTITY Upcnt10 IS
PORT ( Clk, Rst : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 downto 0));
END Upcnt10;
ARCHITECTURE Behavioral OF Upcnt10 IS
BEGIN
PROCESS (Clk, Rst)
VARIABLE count: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
IF Rst ='1' THEN
count := (others=>'0');
ELSIF rising_edge(clk) THEN
IF count = "1001" then
count := (others=>'0');
ELSE count := count + "0001";
END IF;
END IF;
Q <= count;
END PROCESS;
END Behavioral;
NguyenTrongLuat 60
BO EM LEN
THAP PHAN
NguyenTrongLuat 61
LIBRARY ieee;
USE ieee.std_logic_1164.all
USE ieee.std_logic_unsigned.all;
ENTITY Updncnt4 IS
PORT ( Clk, Rst, Updn: IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 downto 0));
END Updncnt4;
ARCHITECTURE Behavioral OF Updncnt4 IS
SIGNAL count: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
PROCESS (Clk, Rst)
BEGIN
IF Rst = 1 THEN
count <= (others =>0);
ELSIF rising_edge(Clk) THEN
IF Updn = 1 THEN
count <= count + 0001;
ELSE count <= count - 0001;
END IF;
END IF;
END PROCESS;
Q <= count;
END Behavioral;
BO EM 4 bit
LEN / XUONG
Updn
Clk
Q0
Updncnt4
Rst
Q1
Q2
Q3
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sipo IS
GENERIC (n: NATURAL := 8);
PORT (Serin, Clk : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(
n-1 downto 0));
END sipo;
ARCHITECTURE shiftreg OF sipo IS
SIGNAL reg : STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS (Clk)
BEGIN
IF rising_edge(Clk) THEN
reg <= reg(n-2 downto 0) & Serin;
END IF;
END PROCESS;
Q <= reg;
END shiftreg;
Thanh ghi dch (shift reg.)
NguyenTrongLuat 62
S
I
P
O
Serin
Clk
Q
sipo
n
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY siso IS
GENERIC (n : NATURAL := 8);
PORT (Clk, Serin : IN STD_LOGIC;
Serout : OUT STD_LOGIC);
END siso;
ARCHITECTURE shiftreg OF siso IS
SIGNAL reg : STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS (Clk)
BEGIN
IF rising_edge(Clk) THEN
reg <= reg(n-2 downto 0) & Serin;
END IF;
END PROCESS;
Serout <= reg(n-1);
END shiftreg;
NguyenTrongLuat 63
S
I
S
O
Serin
Clk
siso
Serout
O
NguyenTrongLuat 64
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY piso IS
GENERIC (n: NATURAL := 8);
PORT (Serin, Clk, ShLd : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(n-1 downto 0);
Serout : OUT STD_LOGIC);
END piso;
ARCHITECTURE shiftreg OF piso IS
SIGNAL reg : STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS (Clk)
BEGIN
IF rising_edge(Clk) THEN
IF ShLd = 0 THEN
reg <= D;
ELSE reg <= reg(n-2 downto 0) & Serin;
END IF;
END PROCESS;
Serout <= reg(n-1);
END shiftreg;
S
I
P
D
Clk
Serout
piso
n
ShLd
Serin
- May trang thai hu han c thiet ke de dang bang phat bieu PROCESS.
- Viec chuyen trang thai c mo ta trong Process vi danh sach cam nhan
(sensitivity list) la clock va tn hieu reset bat ong bo.
- Ngo ra co the c mo ta bang cac phat bieu ong thi (concurrenrt) nam
ngoai process.
- Co 2 kieu FSM: MOORE va MEALY
NguyenTrongLuat 65
MAY TRANG THAI
FSM
MOORE
FSM
Present State
Register
Next State
function
Output
function
Inputs
Present State
Next State
Outputs
clock
reset
Next state function: ham trang thai ke tiep la mach to hp phu thuoc vao ngo vao
va trang thai hien tai
Output function: ham ngo ra la mach to hp phu thuoc vao trang thai hien tai
Present State Register: thanh ghi trang thai hien tai lu gi 1 trang thai hien tai, se
chuyen trang thai khi co xung clock.
NguyenTrongLuat 66
Present State
Register
Next State
function
Output
function
Inputs
Present State
Next State
Outputs
clock
reset
Process Thanh ghi trang thai:
PROCESS (reset, clock)
Process Ham trang thai ke tiep:
PROCESS (input, present_state)
Process Ham ngo ra:
PROCESS (present_state)
Concurrent Statements
FSM kieu MOORE c mo ta bang 3 PROCESS
- Process Ham ngo ra co the thay the bang cac phat bieu ong thi (concurrent
statement)
NguyenTrongLuat 67
- Process 2 va 3 co the ket hp thanh 1 Process.
LIBRARY ieee;
USE iee.std_logic_1164.all;
ENTITY Moore_FSM IS
PORT (clock, rerset, input: IN std_logic;
output: OUT std_logic);
END Moore_FSM;
ARCHITECTURE behavior OF Moore_FSM IS
TYPE state IS (list of states);
SIGNAL pr_state, nx_state: state;
BEGIN
PROCESS(clk, reset)
BEGIN
IF reset = 1 THEN
pr_state <= reset state;
ELSIF (clock = 1 and clockevent) THEN
pr_state <= nx_state;
END IF;
END PROCESS;
TYPE state IS (list of states): khai bao state la d lieu kieu liet ke
NguyenTrongLuat 68
Process Thanh ghi trang thai:
PROCESS (reset, clock)
PROCESS (input, ps_state )
CASE ps_state IS
WHEN state_1 =>
IF input = THEN
nx_state <= state_2;
ELSIF nx_state <= state_3;
END IF;
WHEN state_2 =>
IF input = THEN
nx_state <= state_1;
ELSIF nx_state <= state_3;
END IF;
. . .
END CASE;
END PROCESS;
NguyenTrongLuat 69
Process Ham trang thai ke tiep:
PROCESS (input, present_state)
PROCESS(ps_state )
CASE ps_state IS
WHEN state_1 =>
output <= ...;
WHEN state_2 =>
output <= ...;
...
END CASE;
END PROCESS;
Co the dung phat bieu IF THEN

NguyenTrongLuat 70
Process Ham ngo ra:
PROCESS (present_state)
Co the thay the process nay bang phat bieu ong thi
output <= ... ;
TT
hien tai
TT ke tiep Ngo ra
(z)
x = 0 x = 1
LIBRARY ieee;
USE iee.std_logic_1164.all;
ENTITY Moore_FSM IS
PORT (
clock, rerset, x: IN std_logic;
z: OUT std_logic);
END Moore_FSM;
ARCHITECTURE behavior OF Moore_FSM IS
TYPE state IS (S0, S1, S2, S3);
SIGNAL pr_state, nx_state: state;
BEGIN
regst: PROCESS(clk, reset)
BEGIN
IF reset = 1 THEN pr_state <= S0;
ELSIF (clock = 1 and clockevent) THEN
pr_state <= nx_state;
END IF;
END PROCESS;
S0
S1
S2
S3
S0
S2
S0
S2
S1
S1
S3
S1
0
0
0
1
NguyenTrongLuat 71
nxst: PROCESS (x, ps_state )
CASE ps_state IS
WHEN S0 =>
IF x = 0 THEN
nx_state <= S0;
ELSIF nx_state <= S1;
END IF;
WHEN S1 =>
IF x = 0 THEN nx_state <= S2;
ELSIF nx_state <= S1;
END IF;
WHEN S2 =>
IF x = 0 THEN nx_state <= S0;
ELSIF nx_state <= S3;
END IF;
WHEN S3 =>
IF x = 0 THEN nx_state <= S2;
ELSIF nx_state <= S1;
END IF;
END CASE;
END PROCESS;
TT
hien tai
TT ke tiep Ngo ra
(z)
x = 0 x = 1
S0
S1
S2
S3
S0
S2
S0
S2
S1
S1
S3
S1
0
0
0
1
NguyenTrongLuat 72
TT
hien tai
TT ke tiep Ngo ra
(z)
x = 0 x = 1
S0
S1
S2
S3
S0
S2
S0
S2
S1
S1
S3
S1
0
0
0
1
Output: PROCESS(ps_state )
CASE ps_state IS
WHEN S3 =>
z <= 1;
WHEN OTHERS =>
z <= 0;
END CASE;
END PROCESS;
END behavior;
Output: PROCESS(ps_state )
IF ps_state = S3 THEN z <= 1;
ELSE 0;
END IF;
z <= 1 WHEN ps_state = S3 ELSE 0;
NguyenTrongLuat 73
NguyenTrongLuat 74
Ket hp Process 2 va 3 thanh 1 Process
TT
hien tai
TT ke tiep Ngo ra
(z)
x = 0 x = 1
S0
S1
S2
S3
S0
S2
S0
S2
S1
S1
S3
S1
0
0
0
1
nx_out: PROCESS (x, ps_state )
CASE ps_state IS
WHEN S0 =>
z <= 0;
IF x = 0 THEN
nx_state <= S0;
ELSIF nx_state <= S1;
END IF;
WHEN S1 =>
z <= 0;
IF x = 0 THEN nx_state <= S2;
ELSIF nx_state <= S1; END IF;
WHEN S2 =>
z <= 0;
IF x = 0 THEN nx_state <= S0;
ELSIF nx_state <= S3; END IF;
WHEN S3 =>
z <= 1;
IF x = 0 THEN nx_state <= S2;
ELSIF nx_state <= S1; END IF;
END CASE;
END PROCESS;
END behavior;
Present State
Present State
Register
Next State
function
Output
function
Inputs
Next State
Outputs
clock
reset
Process Thanh ghi trang thai:
PROCESS (reset, clock)
Process Ham trang thai ke tiep
va Ngo ra:
PROCESS (input, present_state)
FSM kieu MEALY c mo ta bang 2 PROCESS
NguyenTrongLuat 75
MEALY
FSM
PROCESS (input, ps_state )
CASE ps_state IS
WHEN state_1 =>
IF input = THEN
output <= ...;
nx_state <= state_2;
ELSIF
output <= ...;
nx_state <= state_3;
END IF;
. . .
END CASE;
END PROCESS;
NguyenTrongLuat 76
Process Ham trang thai ke tiep va Ngo ra:
PROCESS (input, present_state)
nx_out: PROCESS (x, ps_state )
CASE ps_state IS
WHEN S0 =>
IF x = 0 THEN
z <= 0;
nx_state <= S0;
ELSIF
z <= 0;
nx_state <= S1;
END IF;
WHEN S1 =>
IF x = 0 THEN
z <= 0;
nx_state <= S2;
ELSIF
z <= 0;
nx_state <= S1;
END IF;
WHEN S2 =>
IF x = 0 THEN
z <= 0;
nx_state <= S2;
ELSIF
z <= 0;
nx_state <= S1;
END IF;
END CASE;
END PROCESS;
TT
HT
TT ke tiep Ngo ra (Z)
X = 0 1 X = 0 1
S0
S1
S2
S0
S2
S2
S1
S1
S1
0
0
0
0
0
1
NguyenTrongLuat 77
- Viec gan trang thai thng la t ong.
- Ta co 2 cach e gan cho moi trang thai bang 1 to hp nh phan:
TYPE state IS (S0, S1, S2);
SIGNAL pr_state, nx_state: state;
TYPE state IS STD_LOGIC_VECTOR(1 downto 0);
CONSTANT S0: state:= 00;
CONSTANT S1: state:= 01;
CONSTANT S2: state:= 11;
SIGNAL pr_state, nx_state: state;
* S dung thuoc tnh (attribute) enum_encoding:
TYPE state IS (S0, S1, S2);
ATTRIBUTE ENUM_ENCODING: STRING;
ATTRIBUTE ENUM_ENCODING OF state: TYPE IS 00 01 11;
SIGNAL pr_state, nx_state: state;
Gn trng thi
* Khai bao constant
NguyenTrongLuat 78
Phat bieu WAIT
- WAIT la phat bieu tuan t (sequential statement).
- Neu Process khong co danh sach cam nhan (sensitivity list) th phat bieu WAIT
la phat bieu au tien cua Process
WAIT UNTIL condition_signal;
WAIT ON sensitivity_list;
WAIT FOR time;
Process c thc thi khi co s thay oi gia tr cua 1 hoac nhieu tn hieu
trong danh sach cam nhan
Process c thc thi khi co ieu kien cua 1 tn hieu xay ra (true)
Ch dung trong mo phong (testbench). Tam dng thc hien Process trong 1
khoang thi gian (time).
NguyenTrongLuat 79
NguyenTrongLuat 80
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Dlatch IS
PORT (D, Clk : IN STD_LOGIC;
Q, Qn : OUT STD_LOGIC);
END Dlatch;
ARCHITECTURE behavior OF Dlatch IS
BEGIN
PROCESS (D, Clk)
BEGIN
IF Clk = 1 THEN
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
ARCHITECTURE behavior OF Dlatch IS
BEGIN
PROCESS
BEGIN
WAIT ON Clk, D;
IF Clk = 1 THEN
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
D
Clk
Q
Q
Dlatch
NguyenTrongLuat 81
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Dflipflop IS
PORT (D, Clk : IN STD_LOGIC;
Q, Qn : OUT STD_LOGIC);
END Dflipflop;
ARCHITECTURE behavior OF Dflipflop IS
BEGIN
PROCESS (Clk)
BEGIN
IF Clkevent AND Clk = 1 THEN
Q <= D;
Qn <= NOT Q;
END IF;
END PROCESS;
END behavior;
ARCHITECTURE behavior OF Dflipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clkevent AND Clk = 1;
Q <= D; Qn <= NOT Q;
END PROCESS;
END behavior;
D
clk
Q
Q
Dflipflop