IC APPLICATIONS

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VBIT ECE Dept.

CONTENTS
Ex.No List of Experiments: Page No.
Part1: TO VERIFY THE FOLLOWING FUNCTIONS. 2
1. Adder, Subtractor and Comparator using IC 741 Op-Amp. 2
2. Integrator and differentiator using IC 741 Op-Amp. 9
3. Active Lowpass and Highpass Butterworth (second order). 16
4. RC Phase Shift and Wien Bridge Oscillators using IC 741Op-Amp. 26
5. IC 555 Timer in Monostable operation. 31
6. Schmitt Trigger Circuit using IC 741 & IC 555. 35
Part2: TO VERIFY THE FUNCTONALITY of the following 74
series TTL ICs.
41
1. D Flip-Flop (74LS74) and JK Master Slave Flip-Flop (74LS73). 41
2. Decade Counter (74LS90) and UP-Down Counter (74LS192). 47
3. Universal Shift Registers-74LS194/195. 54
4. 3-8 Decoder-74LS138. 58
5. 4 Bit Comparator-74LS85. 62
6. 8X1 Multiplexer- 2X4 Demultiplexer -74155. 66
ADDITIONAL EXPERIMENTS 75
1. Function Generator Using IC 741. 76
2. Inverting and Non inverting Operational amplifiers: 79
DESIGN EXPERIMENT 83
1. Synchronous 4bit up/down Counter (ic 74193) 84
OPEN -ENDED EXPERIMENT 87
REFERENCES 88







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PART1:

EXPERIMENT NO: 1
ADDER, SUBTRACTOR AND COMPARATOR USING IC 741 OP-AMP

I. Aim: -
To study the working of op amp as adder, subtractor and comparator.
II. Apparatus: -
Digital trainer kit - 1
Regulated power supply - 1
CRO - 1
IC 741 - 2
Resistors
1K - 2
4.7K - 5
III. THEORY:-

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VBIT ECE Dept.
ADDER:
Let V
1
and V
2
are two inputs applied to the inverting terminal of op-amp through R
1
and R
2

resistors as shown in fig.1. A feedback resistor R
f
is connected between o/p and inverting i/p.
Then the o/p will be the summation of i/p voltages.
Vo =- 4.7(V
1
+V
2
)
SUBTRACTOR:
Let V
1
and V
2
are two inputs applied to the inverting terminals of the two op -amps through
R
1
and R
4
resistors as shown in the subtractor circuit diagram. Feedback resistors are
connected between o/p and inverting i/ps. Then the o/p will be the difference of two i/p
voltages.
V
O
= V
1
V
2
OP- AMP as COMPARATOR:
Comparator is a non-linear application of in open loop configuration. A Comparator circuit
compares the input signal voltage with a reference voltage at the terminals of an open loop op
amp. A non inverting comparator circuit shown in fig 3 with input voltage applied to non
inverting terminal and V
ref
to inverting input terminal.
The output voltage will be V
sat
(= V
cc
) and its transfer characteristics as shown in fig.4. The
transfer characteristics for a practical comparator is shown.
When V
i
< V
ref
; V
o
= -V
sat

When V
i
>V
ref
; V
o
= +V
sat





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VBIT ECE Dept.

IV CIRCUIT DIAGRAMS:
ADDER:


Figure1. OP-AMP ADDER







U1
741
3
2
4
7
6
5 1
R
1
1.0kOhm_5%
R
2
1.0kOhm_5%
V1
12V
V2
12V
R
f
4.7kOhm_5%
v
1
v
2
v
o
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VBIT ECE Dept.

SUBTRACTOR:

Figure2. OP-AMP SUBTRACTOR









V
1
V
2
V
o
U1
741
3
2
4
7
6
5 1
U2
741
3
2
4
7
6
5 1
V1
12V
V2
12V
V3
12V
V4
12V
R1
4.7kOhm_5%
R2
4.7kOhm_5%
R3
4.7kOhm_5%
R4
4.7kOhm_5%
R5
4.7kOhm_5%
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COMPARATOR:

Fig ure3: Comparator

IV. PROCEDURE:-
ADDER
1. Connect the circuit as shown in the adder circuit diagram.
2. Apply DC voltage from regulated power supply to inputs V
1
and V
2
.
3. Increase input voltages from 0.1V to 0.5V in steps of 0.1V
4. Note down the Vo corresponding inputs (CRO in DC mode).
5. Compare theoretical and practical values.
SUBTRACTOR
1. Connect the circuit as shown in the adder circuit diagram.
2. Apply DC voltage from regulated power supply to inputs V
1
and V
2
.
3. Keep the 5V at V
1
, slowly decrease V
2
from 5V to 3V with five readings
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4. Note down the Vo corresponding inputs (CRO in DC mode).
5. Compare theoretical and practical values
COMPARATOR
1. Connect the circuit as shown in the figure.
2. Set the reference voltage as 1V DC.
3. Apply a sine wave of 5V p-p with 1 KHz frequency from the function generator.
4. Check the output on CRO.
5. Plot the waveforms on graph sheets.

V. MODEL WAVEFOMS
COMPARATOR

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VBIT ECE Dept.
VI. RESULT: -
Successfully constructed and studied the adder, subtractor and comparator circuits using Op-
Amp 741.

VII. VIVA QUESTIONS:

1. What are the applications of op-amp?
2. Write down output voltage formula for the adder in inverting mode.
3. Write down output voltage formula for the adder in non-inverting mode.
4. Write short notes on inverting and non-inverting amplifier.
5. What are ideal characteristics of an ideal op-amp?
6. Write the comparator circuit diagram.












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VBIT ECE Dept.
EXPERIMENT NO: 2
INTEGRATOR AND DIFFERENTIATOR USING IC 741 OP-AMP

I. Aim: -
To study the working of op amp as differentiator and integrator.
II. Apparatus: -
Digital trainer kit - 1.
Regulated power supply - 1.
CRO - 1.
IC 741 - 1.
Resistors
10K - 1.
Capacitor 0.01F - 1.

III. THEORY
DIFFERENTIATOR
An Op-Amp for differentiation is shown in Fig3. The circuit performs the mathematical
operation of differentiation. The non-inverting terminal is grounded. A resistor RF is connected
in feedback path and a Capacitor C1 is connected between the input signal source and the
inverting terminal of the Op-Amp.
Let V
i
= input voltage
V
g
= the voltage at the inverting input
V
o
= output voltage.
A = Open-loop Gain of the Op-Amp
The current equation at the node A is I
c
= I
b
+ I
F

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VBIT ECE Dept.
But I
b
=0, So I
c
= I
F

I
c
= C
1
d/dt [V
i
V
g
]
And I
i
= [V
g
-V
o
]/R
F

Therefore C
1
d/dt[V
i
-V
g
] = [V
g
-V
o
]/R
F

But V
o
= A/V
g

As gain A is very high, V
g
should be very small.
Hence V
g
= 0.
So C
1
dV
i
/dt = -V
o
/RF
V
o
= -R
F
C
1
d/dt [V
i
]
or
V
o
(t) = -R
F
C
1
d/dt [V
i
(t)]
I.e., the output voltage is a derivative of the input voltage.

INTEGRATOR
An OP-Amp circuit for integration is shown in Fig4. The output voltage waveform of this
circuit is the integral of input voltage. A Capacitor C
F
is connected in feed back path and a
Resistor R
1
is connected as the input element. The non- inverting input is grounded.
Let V
i
= input voltage
V
g
= the voltage at the inverting input
V
o
= output voltage.
A = Open-loop Gain of the Op-Amp
The current equation at the node A is I
c
= I
b
+ I
f

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VBIT ECE Dept.
But I
b
=0, so I
c
= I
f

I
i
= [V
i
-V
g
]/R1
I
f
= C
F
d/dt [V
g
-V
o
]

Therefore C
F
d/dt[Vg-V
o
] = [V
i
-V
g
]/R1
But V
o
= A/V
g

As A is very high, V
g
should be very small.
Hence V
g
= 0.
Vi/R1 = -C
F
d/dt[V
o
]
V
i
/R1 = C
F
d/dt[V
o
]
[V
i
/R1] dt = -C
F
V
o

Therefore V
o
= -1/R
1
C
F
V
i
dt.
or
V
o
(t)

= -1/R
1
C
F
V
i
(t) dt.
The equation shows that the output voltage is an integral of the input voltage.








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VBIT ECE Dept.
CIRCUIT DIAGRAMS:-
DIFFERENTIATOR












U1
741
3
2
4
7
6
5 1
V1
12V
V3
12V
XFG1
R
F
10kOhm_5%
C
1
10nF
Vi(t)
Vo(t)
Figure 3. OP-AMP DIFFERENTIATOR
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INTEGRATOR

Figure 4. OP-AMP INTEGRATOR
IV. PROCEDURE:-
DIFFERENTIATOR
1. Connect the circuit as shown in the differentiator circuit diagram.
2. Apply a bipolar symmetrical squrare wave of 5V amplitude peak to peak and 1ms
time period.
3. Connect the input and output of the circuit to channel 1and channel 2 of the CRO
respectively and observe the waveforms.
4. Draw the waveforms along with the levels on a graph.
5. Compare the practical values with theoretical values.
U2
741
3
2
4
7
6
5 1
V1
12V
V2
12V
XFG1
C
F
10nF
R1
10kOhm_5%
Vi(t)
Vo(t)
U2
741
3
2
4
7
6
5 1
V1
12V
V2
12V
XFG1
C
F
10nF
R1
10kOhm_5%
Vi(t)
Vo(t)
U2
741
3
2
4
7
6
5 1
V1
12V
V2
12V
XFG1
C
F
10nF
R1
10kOhm_5%
Vi(t)
Vo(t)
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VBIT ECE Dept.
INTEGRATOR
1. Connect the circuit as shown in the differentiator circuit diagram.
2. Apply a bipolar symmetrical squrare wave of 5V amplitude peak to peak and 1ms
time period.
3. Connect the input and output of the circuit to channel 1and channel 2 of the CRO
respectively and observe the waveforms.
4. Draw the waveforms along with the levels on a graph.
5. Compare the practical values with theoretical values.
V MODEL WAVEFORMS:-

DIFFERENTIATOR AND INTEGRATOR













V
i

t
t
V
o

V
i

t
t
V
o

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VBIT ECE Dept.
VI. RESULT: - Successfully studied and observed differentiator and integrator circuits
using Op-Amp 741.
VII. VIVA QUESTIONS -
1. Define integrator.
2. Define differentiator.
3. What is the difference between integrator and differentiator?
4. Write down output voltage formula for the integrator.
5. Write down output voltage formula for the differentiator.














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VBIT ECE Dept.
EXPERIMENT NO: 3
ACTIVE LOWPASS AND HIGHPASS BUTTERWORTH
(SECOND ORDER).

I. Aim: -
To design a second order lowpass and highpass filters of gain 1.586 with cutoff frequency of
1 kHz.
II. Apparatus: -
Digital trainer kit - 1.
Regulated power supply - 1.
CRO - 1.
IC 741 - 1.
Resistors
1K - 1.
15.8K - 1.
27K - 1.
33K - 2.
10K - 1
Capacitors 0.0047F - 2.
III. Theory:-
LOW PASS FILTER:
An Op-Amp Low pass filter is shown in Fig1. The circuit allows the low frequency signals
freely through it and attenuates the signals above a cut off frequency called Higher cut off
frequency ( f
H
). The inverting terminal is grounded through a resistor R
1
. A resistor R
F
is
connected in feedback path. A Resistor R
2
is connected between the input signal source and
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VBIT ECE Dept.
the inverting terminal of the Op-Amp and a Capacitor C
2
is connected between the inverting
terminal and ground
Let V
i
= input voltage
V
g
= the voltage at the Non-inverting input
V
o
= output voltage.
A = Gain of the Op-Amp = 1+R
F
/R
1

X
c
= Capacitive Reactance = 1/jC
2






But V
o
= AV
g







But = 2 f

X
c
V
g
= V
i
R
2
+ X
c

1/jC
2
V
g
= V
i
R + 1/jC
2

1/j C
2
V
o
= [1+R
f
/R
i
] V
i
R
2
+ 1/jC
2

1/jC
2
V
o
= A V
i
R
2
+ 1/j C
2

1

V
o
= A V
i
j2 f C R + 1
A

V
o
= V
i
1 + jf / 2 R
2
C
2

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Where f
H
is the Higher cut off frequency of the Low pass filter = 1/2 R
2
C
2
.
Transfer function of Low pass filter is given as H (s) = V
o
/ V
i












For second order filter



1

V
o
= A V
i
jC
2
R
2
+ 1
A

V
o
= V
i
1 + Jf / f
H

A

H (s) =

1 + j f
/
f
H

A

H (s) =

1 + j f
/
f
H


Magnitude is given by

H (s) =20 log A dB

1 +{f
/
f
H
}
2


Magnitude is given by

H (s) =20 log A dB

1 +{f
/
f
H
}
4

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VBIT ECE Dept.



HIGH PASS FILTER:
An Op-Amp High pass filter is shown in Fig 2. The circuit allows the high frequency
signals freely through it and attenuates the signals below a cut off frequency called Lower cut off
frequency (f
L
). The inverting terminal is grounded through a resistor R
1
. A resistor R
F
is
connected in feedback path. A Capacitor C
2
is connected between the input signal source and the
inverting terminal of the Op-Amp and a Resistor R
2
is connected between the inverting terminal
and ground.

Let V
i =
Input voltage
V
g
= Voltage at the Non-inverting input
V
o
= output voltage.
A = Gain of the Op-Amp








R
2
V
g
= V
i
R
2
+ X
c

R
2
V
o
= A V
i
R
2
+ 1/jC
2

1

V
o
= A V
i
1 + 1/j R
2
C
2

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Where f
L
is the Lower cut off frequency of the High pass filter = 1/2 R
2
C
2
.

Transfer function of High pass filter is given as H (s) = V
o
/ V
i












For second order filter



1

V
o
= A V
i
1 + 1/j2 f R
2
C
2

A

V
o
= V
i
1 j f
L /
f
A

H (s) =

1 j f
L /
f
A

H (s) =

1 j f
L /
f

Magnitude is given by

H (s) =20 log A dB

1 +{f
L /
f}
2


Magnitude is given by

H (s) =20 log A dB

1 +{f
L /
f}
4

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VBIT ECE Dept.

Designing part:-
Gain=2 and cutoff frequency f
H
=1 kHz
Gain=1+R
F
/R
1
then 1+R
F
/R
1
=1.586
R
F
/R
1
=0.586
R
F
=0.586R
1
Let R
1
=27k then R
F
=15.8k
And higher cutoff frequency f
H
=1/2 R2C2R3C3 = 1 kHz
Let C
2=
C
3 =
0.0047F
For design simplifications set R2=R3.
then R2=R3=33.86k
IV CIRCUIT DIAGRAMS:-
LOWPASS FILTER:

Figure 1. ACTIVE LOW PASS FILTER

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HIGH PASS FILTER:



Figure2. ACTIVE HIGHPASS FILTER

V. PROCEDURE:-
LOW PASS FILTER:
1. Connect the circuit as shown in the lowpass filter circuit diagram.
2. Apply 5V p-p sine wave input to the resistor R
2
.
3. Keep the input constant and take any 10 readings of output voltage with 10 different
frequencies.
4. Observe the theoretical and practical voltage gains.
5. Draw the graph between voltage gain and frequency.


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VBIT ECE Dept.


S.No. Input frequency (KHz)
Input Amplitude
(V
p-p
)
Output
Amplitude
(V
p-p
)
1.
2.
3.
4.
5.
6.
7
8
9
10
HIGHPASS FILTER:
1. Connect the circuit as shown in the lowpass filter circuit diagram.
2. Apply 5V p-p sine wave input to the capacitor C
2
.
3. Keep the input constant and take any 10 readings of output voltage with 10 different
frequencies.
4. Observe the theoretical and practical voltage gains.
5. Draw the graph between voltage gain and frequency.


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VBIT ECE Dept.
S.No. Input frequency (KHz)
Input Amplitude
(V
pp
)
Output
Amplitude (V
pp
)
1.
2.
3.
4.
5.
6.
7
8
9
10

IV. EXPECTEC GRAPHS:-
LOW PASS FILTER









gain






3 dB
F requency in KHz
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HIGHPASS FILTER









VI . RESULT:-
Designed and observed the second order highpass and lowpass filters for the given
specifications.
VII. VIVA QUESTIONS:
1. Define an electrical filter.
2. Classify filters.
3. Discuss the disadvantage of passive filters.
4. Why we preferred active filters?
5. Define passband and stopband of a filter.
6. Give some notes on first order filter.
7. Discuss the differences between Butterworth and Chebyshev filters.
8. Give high cutoff frequency formula for the lowpass filter.
9. What is the difference between analog filter and digital filter?
10. Give low cutoff frequency formula for the highpass filter.

gain






3 dB
F requency in KHz
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VBIT ECE Dept.

EXPERIMENT NO: 4
RC PHASE SHIFT AND WIEN BRIDGE OSCILLATORS USING
IC 741OP-AMP

I. AIM:-
To study the working of RC phase shift and Wien bridge oscillator.
II. APPARATUS
Digital trainer kit - 1
CRO - 1
Connecting wires and probes
IC 741 - 1
Resistors
10k - 1
470k - 1
1.5k - 3
15k - 1
50k - 1
Capacitors
0.01F - 3
III THEORY
RC Phase shift oscillator:-
The circuit diagram for a Phase shift oscillator using an OP-AMP IC-741 is shown in
fig 1.The OP-AMP provides a phase shift of 180
0
as its used in the Inverting mode/ The
additional 180
0
phase shift is provided by the feed back RC network. By using OP-AMP low
frequency signals of frequency around 1 K Hz can be achieved.
The frequency of oscillations is given by

FIG 1. PHASE SHIFT OSCILLATOR
1
f
O
=
6 (2 RC)
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VBIT ECE Dept.
The Gain of the OP-AMP when loop gain A
V
=1 should be at least 29.
i.e., A
V
29, for this choose R
f
29 R
1
.
Wien bridge oscillator:-
The circuit diagram for a Wein Bridge oscillator using an OP-AMP IC-741 is shown in
fig 2.The feedback signal from circuit is connected to the Non-Inverting terminal of the OP-
AMP. A bridge is formed by four arms in which a series RC network in one arm and a parallel
RC network in adjoining arm and the remaining two arms consisting of R
1
and

R
F
of the OP-A
MP as shown in fig.2.
The frequency of oscillations is given by


The Gain of the OP-AMP when loop gain A
V
=1 should be at least 3.
i.e., A
V
3, for this choose R
f
2 R
1
.
IV.CIRCUIT DIAGRAMS

Figure1. RC phase shift oscillator
1
f
O
=
2 RC
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VBIT ECE Dept.
Wien bridge oscillator:-

Figure2. Wien bridge oscillator
V. PROCEDURE:
RC Phase shift oscillator:-
1. Construct the Phase shift oscillator as shown in the circuit.
2. Also connect the Power supply and CRO to the circuit.
3. Observe the output waveform on CRO taken at pin no.6 of the OP-AMP.
4. Calculate the frequency and amplitude of the waveform, draw the waveform on graph
sheet.
Wien bridge oscillator:-
1. Construct the Wein Bridge oscillator as shown in the circuit.
2. Also connect the Power supply and CRO to the circuit.
3. Observe the output waveform on CRO taken at pin no.6 of the OP-AMP.
4. Calculate the frequency and amplitude of the waveform, draw the waveform on graph
sheet.

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VBIT ECE Dept.
VI.EXPECTED WAVEFORM


VII. RESULT:-
Designed and observed the waveforms of RC phase shift and Wien bridge oscillator.
VIII. VIVA QUESTIONS-
RC phase shift oscillator
1. Classify the oscillators.
2. What is the range of the frequency oscillations in case of the phase shift oscillator?
3. In phase shift oscillator what phase shift does the op - amp provide?
4. What phase shift is provided by the feedback network in phase shift oscillator?
5. Write down the frequency oscillations formula for the phase shift oscillator.
6. What is the relation between R
F
and R
1
in op -amp phase shift oscillator?
7. Discuss about LC oscillators and RC oscillators.
8. Define oscillator.
9. In what mode op - amp is used in phase shift oscillator?
10. Explain how to measure the phase difference of two signals?
Wien bridge oscillator
1. Classify the oscillators.
2. What is the range frequency oscillation in case of the Wien bridge oscillator?
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VBIT ECE Dept.
3. In Wien bridge oscillator what phase shift does the op - amp provide?
4. What phase shift is provided by the feedback network in Wien oscillator?
5. Write down the frequency oscillations formula for the Wien bridge oscillator.
6. What is the relation between R
F
and R
1
in op - amp Wien bridge oscillator?
7. Discuss about LC oscillators and RC oscillators.
8. Define oscillator.
9. In what mode op - amp is used in Wien oscillator?
10. Explain how to measure the phase difference of two signals





























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VBIT ECE Dept.
EXPERIMENT NO: 5
IC 555 TIMER IN MONOSTABLE OPERATION
I. AIM
To design a monostable multivibrator having an output pulse width of 1ms using 555 timer.
II. APPARATUS: -
Digital trainer kit - 1.
CRO - 1 .
IC 555 - 1.
Resistor
10K - 2 .
Capacitors 0.1F - 1.
0.01F - 1.
III. THEORY:-

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VBIT ECE Dept.
IC 555 Timer
IC-555 Timer is a versatile Monolithic timing circuit that can produce accurate and highly stable
time delays or oscillations. It can be used as an Astable and Monostable multivibrators. It is
available as an 8- pin mini DIP-package
Monostable multivibrator:-Monostable Multivibrator has only one stable state. We can change
the stable state by applying a trigger pulse. The capacitor charges through R
A
. The larger the
time constant R
A
C, the longer it takes the capacitor voltage to reach 1/3 V
CC
. The time constant
controls the pulse width. After the time period given by R
A
and C elements the circuit goes back
to its stable state. Even the trigger pulse is removed in between still the circuit will not comeback
to its stable state until its time period is reached.The time period of stable state is given by
T=1.1R
A
C
IV CIRCUIT DIAGRAM:-

U
1
1
DI
S
7
OU
T
3
RS
T
4
8
TH
R
6
CO
N
5
TR
I
2
GN
D
VC
C
LM555C
H
V
1
5
V
R
A

10kOhm_5
%
C
3 10n
F
C
2
100nF
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VBIT ECE Dept.
Designing part:-
T=1ms then
T

= 1.1R
A
C=1ms
Let C=100nF then
R
A=
9k
V. PROCEDURE:-
Monostable multivibrator:-
1. Design astable multivibrator with the pulse width of T
1
= 1.1R
A
C.
2. Connect the circuit as shown in the monostable multivibrator circuit diagram.
3. Compare theoretical and practical time periods.
VI. Model waveforms:-
Monostable multivibrator:-
Trigger input:-

Capacitor and monostable output

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VII. RESULT:-
Successfully designed and verified the waveforms of monostable multivibrator using
555 timer.
VIII. VIVA QUESTIONS:
1. Explain the functional block diagram of a 555 timer.
2. What are the modes of operation of timer?
3. Define duty cycle.
4. What are the applications of 555 timers in astable mode?
5. Draw the pin diagram of 555 timers.
6. Explain the function of reset.
7. What are the applications of 555 timers in monostable mode?
8. What is the expression of %duty cycle in monostable mode?
9. Explain capacitor output waveform in monostable mode.
10. Write down the expression for output pulse width in monostable mode.








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EXPERIMENT NO: 6
SCHMITT TRIGGER USING IC 741 AND IC 555
I. Aim: - to construct a Schmitt trigger circuit using IC 741 and IC 555, verify the output
wave forms.
II. APPARATUS
Digital trainer kit - 1 No.
Regulated power supply - 1 No.
Function generator - 1 No.
CRO - 1 No.
IC 741 - 1 No.
Resistors
1K - 2 No.
9.1K - 1 No.
Capacitor 0.01F - 1 No.
III. Theory:-
When a positive feedback is added to an ideal comparator then the circuit acts as a
Schmitt trigger. The input voltage is applied at the inverting (-ve )terminal and feedback voltage
is at non-inverting (+ ve) terminal of op-amp as shown.
This positive feedback loop gain = -A
o2
when it is equal to unity then feedback gain A
vf

is infinity - A
OL
= 1; A
f

Then output changes arbitrarily between extreem values of output voltage. This circuit
exhibits hysterisis or backslash. When input voltage triggers Vo every time it exceeds certain
voltage levels. These levels are called (UTP) upper trigger point and (LTP) lower trigger point.
The hysteresis width is the difference between UTP and LTP voltages i.e.,
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V
H
= V
UTP
V
LTP
.
Let Vo = V
sat
the threshold voltage can be calculated as
( R
2
/(R
1
+R
2
) )(V
sat
V
ref
) + V
ref
= V
UTP
.
As long as Vi < V
UTP
then Vo is at +V
sat
. If Vi is just greater than V
UTP
the output switches to
Vsat until Vi >V
UTP
as shown in fig.2. For Vo = - V
sat
the terminal V
LTP

CIRCUIT DIAGRAM:-



Figure 1. Schmitt trigger using IC 741
Vo(t)
U1
741
3
2
4
7
6
5 1
V1
12V
V3
12V
V2 1V
V
i

10V
7.07V_rms
1000Hz
0Deg
R3
1.0kOhm_5%
R
1

1.0kOhm_5%
R
2

9.1kOhm_5%
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SCHMITT TRIGGER USING IC 555.
CIRCUIT DIARAM:







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IV. PROCEDURE:-
USING IC 741:-
1. Connect the circuit as shown in the Schmitt trigger using

IC 741.
2. Use a 5V p-p sinewave of 1 kHz as input.
3. Rectangular wave displays on CRO and measure UTP and LTP.
4. Use x-y mode in CRO and observe hysteresis curve on CRO.
USING IC 555:-
1. Apply a sine wave of 1 KHz frequency of 5 V peak to peak.
2. The output changes from - V
sat
to + V
sat
when the input crosses 2/3 V
cc
it is the Upper
Trigger Point (UTP).
3. The output changes from +V
sat
to - V
sat
when the input crosses 1/3 V
cc
it is the Lower
Trigger Point (LTP).
4. Observe the output waveform on CRO and draw the relevant waveforms on graph
Sheet and note down the UTP and LTP values.
V. Model waveforms:- Using IC 741:-










+ V
UTP

- V
sat

Vi - Vref
V
i
< V
ref

+ V
sat

- V
sat

Vi - Vref
V
i
> V
ref

V
o

V
i

V
m

t
t


+ V
LTP

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Using IC 555.

V
o

+ V
cc

t
2/3 V
cc

V
cc

3

V
cc

2

V
i

t


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VI. RESULT: -
Constructed a Schmitt trigger circuit using IC 741 and IC 555 and verified the output
waveforms.
VII. VIVA QUESTIONS :
1. What type of feedback we use in Schmitt trigger circuit?
2. Short notes on UTP.
3. Short notes on LTP.
4. What are the circuits we used to generate square?
5. Short notes on zero crossing detector.
6. Define hysteresis width.
7. Write pin diagram of IC 741.
8. Write pin diagram of 555 IC.
9. What is the supply voltage rang for IC 741?
10. What is the supply voltage range for IC 555?










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PART 2
EXPERIMENT NO: 1
D Flip-Flop (74LS74) and JK Master Slave Flip-Flop (74LS73)

A) D Flip-Flop (74LS74)
AIM: To Verify the functionality of the IC 74LS74 D Flip Flop.
APPARATUS:
1) Digital Trainer kit
2) IC 74LS74
3) Connecting probes & Wires
THEORY: The D ip-op is the most common flip-flop in use today. It is better known as data
or delay flip-flop (as its output Q looks like a delay of input D).IC 74LS74 contains two
independent positive edge-triggered D flip- flops withcomplementary outputs. The information
on the D input is accepted by the flip-flops onthe positive going edge of the clock pulses. The
triggering occurs at a voltage level and is not directly related to the transition time of the rising
edge of the clock. The data on the D may be changed while the clock is low or high without
affecting the outputs as long as the data setup and hold times are not violated. A LOW logic level
on the preset or clear inputs will set or reset the outputs regardless of the logic levels on the other
inputs.
PIN LAYOUT:


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Pin Description
Pin Number Description
1 Clear 1 Input
2 D1 Input
3 Clock 1 Input
4 Preset 1 Input
5 Q1 Output
6 Complement Q1 Output
7 Ground
8 Complement Q2 Output
9 Q2 Output
10 Preset 2 Input
11 Clock 2 Input
12 D2 Input
13 Clear 2 Input
14 Positive Supply

LOGIC DIAGRAM:


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TRUTH TABLE:


PROCEDURE:
1. Connections are made as per the pin diagram.
2. Verify the Truth table for all the combinations of inputs.

RESULT: The functionality of the IC 74LS74 D Flip Flop is verified.










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B) JK Master Slave Flip-Flop (74LS73)
AIM: To Verify the functionality of the IC 74LS73 JK Master slave Flip Flop.
APPARATUS:
1) Digital Trainer kit
2) IC 74LS73
3) Connecting probes & Wires

THEORY:
For JK flip-flop When J=1 and K=1, there is a restriction on pulse width due to toggle
operation (where output complements again and again until clock pulse goes to 0). This
restriction is called as Race-Around condition and it can be bumped off using the Master-Slave
Flip-flop.
A master-slave flip-flop is normally constructed from two flip-flops: one is the Master flip-flop
and the other is the Slave. In addition to these two flip-flops, the circuit also includes an inverter.
The inverter is connected to clock pulse in such a way that the inverted Clock Pulse is given to
the slave flip-flop. For example, if the CP=0 for a master flip-flop, then the output of the inverter
is 1, and this value is assigned to the slave flip-flop. In other words if CP=0 for a master flip-
flop, then CP=1 for a slave flip-flop.The master-slave flip-flops are widely used in Memory
Rgisters.
The 74LS74 IC contain two independent negative edge triggered J-K Flip-flops with individual
J,K,Clock , direct Clear inputs & two Complimentary inputs.. The J & K inputs must be stable
one setup time prior to the high to low clock transition for predictable operation.






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PIN LAYOUT:

Pin Description
Pin Number Description
1 Clock 1
2 Clear 1
3 K1 Input
4 Positive Supply
5 Clock 2
6 Clear 2
7 J2 Input
8 Complement Q2 Output
9 Q2 Output
10 K2 Input
11 Ground
12 Q1 Output
13 Complement Q1 Output
14 J1 Input



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LOGIC DIAGRAM:


TRUTH TABLE:

PROCEDURE:
1. Connections are made as per the pin diagram.
2. Verify the Truth table for all the combinations of inputs.
RESULT: The functionality of the IC 74LS73 JK Master Slave Flip Flop is verified.
VIVA QUESTIONS:
1. What is D-FF?
2. Define a latch?
3. Define a FF?
4. What is the difference b/w latch & FF?
5. In flip-flop how many stable states are there?
6. What is edge triggering?

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EXPERIMENT NO: 2
Decade Counter (74LS90) and UP-Down Counter (74LS192)
A) Decade Counter (74LS90)
AIM: To Verify the functionality of the IC 74LS90 Decade Counter.
APPARATUS:
1) Digital Trainer kit
2) IC 74LS90
3) Connecting probes & Wires
THEORY: The binary counters previously introduced have two to the power n states. But
counters with states less than this number are also possible. They are designed to have the
number of states in their sequences, which are called truncated sequences. These sequences are
achieved by forcing the counter to recycle before going through all of its normal states. A
common modulus for counters with truncated sequences is ten. A counter with ten states in its
sequence is called a decade counter. The circuit below is an implementation of a decade counter.


Once the counter counts to ten (1010), all the flip-flops are being cleared. Notice that
only Q1 and Q3 are used to decode the count of ten. This is called partial decoding, as
none of the other states (zero to nine) have both Q1 and Q3 HIGH at the same time.


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The sequence of the decade counter is shown in the table below:

The 74LS (Low-power Schottky) family uses TTL (Transistor-Transistor Logic) circuitry which
is fast but requires more power than later families. The 74LS90 IC counts the number of pulses
arriving at its input. The number of pulses counted (up to 9) appears in binary form on four pins
of the IC. When the tenth pulse arrives at the input, the binary output is reset to zero (0000) and a
single pulse appears at another output pin. So for ten pulses in there is one pulse out of this pin.
The 7490 therefore divides the frequency of the input by ten.
We can also set the chip up to count up to other maximum numbers and then return to zero. We
can "set it up" by changing the wiring of the R01, R02, R91 and R92 lines. If both R01 and R02
are 1 (5 volts) and either R91 or R92 are 0 (ground), then the chip will reset QA, QB, QC and
QD to 0. If both R91 and R92 are 1 (5 volts), then the count on QA, QB, QC and QD goes to
1001 (5).
PIN LAYOUT:

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LOGIC DIAGRAM:




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TRUTH TABLE:


PROCEDURE:
1. Connections are made as per the Logic diagram.
2. Connect pin 5 to Vcc (+5v) & pin 10 to ground to power the chip.
3. The counter is in two sections : clockA-QA and clockB-QB-QC-QD. For normal use
connect QA to clockB to link the two sections, and connect the external clock signal
(1 HZ clock input or pulser input) to clockA.
4. Connect pin numbers (reset) 2,3,6 & 7 to the ground.
5. Verify the Truth table for all the combinations of inputs.

RESULT: The functionality of the IC 74LS90 Decade Counter is verified.






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B) UP-Down Counter (74LS192)
AIM: To Verify the functionality of the IC 74LS192 Up/Down Counter.
APPARATUS:
1) Digital Trainer kit
2) IC 74LS192
3) Connecting probes & Wires
THEORY:
The 74LS192 is a high speed CMOS synchronous up/down Decade counter integrated
circuit. Counting up and counting down is performed by two count inputs, one being held high
while the other is clocked. The outputs change on the positive-going transition of this clock. The
counters also have carry and borrow outputs so that they can be cascaded using no external
circuitry.

The counter may be preset by entering the desired data on the DATA A, DATA B, DATA C, and
DATA D inputs .When the LOAD input is taken low the data is loaded independently of either
clock input. This feature allows the counters to be used as divide-by-n counters by modifying the
count length with the preset inputs. In addition the counter can also be cleared. This
is accomplished by inputting a high on the CLEAR input. Both BORROW and CARRY outputs
are provided to enable cascading of both up and down counting functions. The BORROW output
produces a negative going pulse when the counter underflows and the CARRY outputs a pulse
when the counter overflows. The counter can be cascaded by connecting the CARRY and
BORROW outputs of one device to the COUNT UP and COUNTDOWN inputs, respectively, of
the next device. All inputs are equipped with protection circuits against static discharge and
transient excess voltage.









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PIN LAYOUT:





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TRUTH TABLE:


PROCEDURE:
1. Connections are made as per the pin diagram.
2. Connect count up or count down pins to the 1HZ clock input or pulsar input on digital
trainer kit.
3. Verify the Truth table for all the combinations of inputs.
RESULT: The functionality of the IC 74LS192 Up/Down Counter is verified.

VIVA QUESTIONS:
1. What is a counter?
2. What are the asynchronous inputs?
3. To restrict the count value of a counter, if takes the help of inputs.
4. To restrict the count value of a counter, if takes the help of inputs.
5. Define mod up counter.
6. Define mod down counter.
7. Difference b/w mod-up counter and mod-down counter.








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EXPERIMENT NO: 3
Universal Shift Registers-74LS194/195
AIM: To Verify the functionality of the IC 74LS194 Universal Shift Register.

APPARATUS:
1) Digital Trainer kit
2) IC 74LS194
3) Connecting probes & Wires

THEORY:
Shift Registers consists of a number of single bit "D-Type Data Latches" connected
to gather in a chain arrangement so that the output from one data latch becomes the input of the
next latch and so on, thereby moving the stored data serially from either the left or the right
direction. The number of individual Data Latches used to make up Shift registers are determined
by the number of bits to be stored. Shift Registers are mainly used to store data and to convert
data from either a serial to parallel or parallel to serial format with all the latches being driven by
a common clock (Clk) signal making them Synchronous devices. They are generally provided
with a Clear or Reset connection so that they can be "SET" or "RESET" as required.

Generally, Shift Registers operate in one of four different modes:
Serial-in to Parallel-out (SIPO)
Serial-in to Serial-out (SISO)
Parallel-in to Parallel-out (PIPO)
Parallel-in to Serial-out (PISO)
Today, high speed bi-directional universal type Shift Registers such as the TTL74LS194,
74LS195 or the CMOS 4035 are available as a 4-bit multi-function devices that can be used in
serial-serial, shift left, shift right, serial-parallel, parallel-serial, and as a parallel-parallel Data
Registers, hence the name "Universal".

The 74LS194 is a High Speed 4-Bit Bidirectional Universal Shift Register. The 74LS194 is
similar in operation to the 74LS195 Universal Shift Register, with added features of shift left
without external connections and hold (do nothing) modes of operation. All data and mode
control inputs are edge-triggered, responding only to the LOW to HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode control and selected data inputs
must be stable one set-up time prior to the positive transition of the clock pulse. The register is
fully synchronous, with all operations taking place in less than 15 ns (typical) making the device
especially useful for implementing very high speed CPUs, or the memory buffer registers.
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The four parallel data inputs (P0, P1, P2, P3) are D-type inputs. When both S0 and S1 are HIGH,
the data appearing on P0, P1, P2, and P3 inputs is transferred to the Q0, Q1, Q2, andQ3 outputs
respectively following the next LOW to HIGH transition of the clock. The asynchronous Master
Reset (MR), when LOW, overrides all other input conditions and forces the Q outputs LOW.

PIN LAYOUT:









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LOGIC SYMBOL:

LOGIC DIAGRAM:





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TRUTH TABLE:

PROCEDURE:
1. Connections are made as per the pin diagram.
2. Connect Clock (CP) to the 1HZ clock input or pulsar input on digital trainer kit.
3. Verify the Truth table for all the combinations of inputs.
RESULT: The functionality of the IC 74LS194 Universal Shift Register is verified.
VIVA QUESTIONS:
1.What is a register?
2. What is a shift register?
3. What are the operations performed by a shift register?
4. Applications of SISO shift register.
5. Applications of PISO shift register.
6. Applications of SIPO shift register.
7. Applications of PIPO shift register.
8. What is the IC package?
9. What is a universal shift register?
10. What are the operations performed by a universal shift register?
11. Applications of SISO universal shift register.
12. Applications of PISO universal shift register.
13. Applications of SIPO universal shift register.
14. Applications of PIPO universal shift register.
15. What is the IC package?
16. Difference b/w shift register and universal shift?
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EXPERIMENT NO: 4
3-8 Decoder-74LS138
AIM: To Verify the functionality of the IC 74LS138 3-8 Decoder.

APPARATUS:
1) Digital Trainer kit
2) IC 74LS138
3) Connecting probes & Wires

THEORY:
A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs
into coded outputs, where the input and output codes are different. The input code generally has
fewer bits than the output code, and there is a one-to- one mapping from input code words into
output code words. In a one-to-one mapping, each input code word produces a different output
code word. A decoder is similar to demultiplexer except that there is no input line. It is a circuit
with many inputs & many outputs. An n x m decoder means that there are n inputs and m
outputs. Out of the m outputs, only one of the output line will be in state 1 and remaining m - 1
outputs will be 0. Some decoders have one or more enable inputs that are useful for expanding
decoders.

The 74LS138 is a high-speed Silicon-gate CMOS device and pin compatible with low power
Schottky TTL (LSTTL). This device is ideally suited for high speed bipolar memory chip select
address decoding. It accept three binary weighted address inputs (A0, A1 and A2) and when
enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). The 138 features three
enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be
HIGH unless E1 and E2 are LOW and E3 is HIGH. It reduces the need for external gates or
inverters when expanding. A 24-line decoder can be implemented with no external inverters, and
a 32-line decoder requires only one inverter. This multiple enable function allows easy parallel
expansion of the 138 to a 1-of-32 (5 to 32 lines) decoder with just four 138 ICs and one
inverter. The 138 can be used as an eight output demultiplexer by using one of the active LOW
enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs
must be permanently tied to their appropriate active HIGH or LOW state.
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PIN LAYOUT:





PIN NAMES





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LOGIC SYMBOL:





LOGIC DIAGRAM:



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TRUTH TABLE:

PROCEDURE:
1. Connections are made as per the pin diagram.
2. Verify the Truth table for all the combinations of inputs.
RESULT: The functionality of the IC 74LS138 3-8 Decoder is verified.
VIVA QUESTIONS
1. What is decoder?
2. What is a encoder?
3. For a 2- I/P decoder how many O/Ps are produced
4. A decoder with n input produces max. of __ no.of minterms.
5. The general representation of an encoder is
6. Draw the 2 to 4 line decoder with only nor gates.
7. Difference b/w de multiplexer and decoder
8. The general representation of an encoder is for economical realization, decoder is used to
realize afunction which contain ( Less no. of dont cares)
9. A 16 to 64 decoder can be obtained by cascading of-----
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EXPERIMENT NO: 5
4 Bit Comparator-74LS85
AIM: To Verify the functionality of the IC 74LS85 4 Bit Comparator.

APPARATUS:
1) Digital Trainer kit
2) IC 74LS85
3) Connecting probes & Wires

THEORY:

The 74LS85 is a 4-Bit Magnitude Camparator which compares two 4-bit words (A, B),
each word having four Parallel Inputs (A0A3, B0B3); A3, B3 being the most significant
inputs. Three Outputs are provided: A greater than B (OA>B), A less than B (OA<B), A
equal to B (OA=B). Three Expander Inputs, IA>B, IA<B, IA=B, allow cascading without
external gates. For proper compare operation, the Expander Inputs to the least significant
position must be connected as follows: IA<B= IA>B = L, IA=B = H. For serial (ripple)
expansion, the OA>B, OA<B and OA=B Outputs are connected respectively to the IA>B, IA<B,
and IA=B Inputs of the next most significant comparator.










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PIN LAYOUT:


PIN NAMES


LOGIC SYMBOL:


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LOGIC DIAGRAM:








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TRUTH TABLE:


PROCEDURE:
1. Connections are made as per the logic symbol.
2. Verify the Truth table for all the combinations of inputs.
RESULT: The functionality of the IC 74LS85 4 Bit Comparator is verified.
VIVA QUESTIONS
1.What is Magnitude Comparator?
2. To form a 12 bit comparator how many 4-bit comparators are connected in cascaded form.
3. The IC 7485 is a package and is a ____ comparator.
4. How many cascaded input are there for a 4-bit comparator.


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EXPERIMENT NO: 6
8X1 Multiplexer - 74151 - 2X4 Demultiplexer - 74155

A) 8X1 Multiplexer - 74151
AIM: To Verify the functionality of the IC 74151 8X1 Multiplexer.
APPARATUS:
4) Digital Trainer kit
5) IC 74151
6) Connecting probes & Wires

THEORY: The multiplexers contains full on-chip decoding unit to select desired data source.
The multiplexer also called as Many to One Circuit. Multiplexers which sometimes are simply
called "Mux" or "Muxes", are devices that act like a very fast acting rotary switch. They connect
multiple input lines 2, 4, 8, 16 etc one at a time to a common output line and are used as one
method of reducing the number of logic gates required in a circuit. Multiplexers are individual
Analogue Switches as opposed to the "mechanical" types such as normal conventional switches
and relays. They are usually made from MOSFETs devices encased in a single package and are
controlled using standard logic gates.


4-to-1 Channel Multiplexer






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The Boolean expression for this 4 to 1 Multiplexer is given as:
Q = abA + abB + abC + abD. In this example at any instant in time only one of the four analogue
switches is closed, connecting only one of the input lines A to D to the single output at Q. As to
which switch is closed depends upon the addressing input code on lines "a" and "b", so for this
example to select input B to the output at Q, the binary input address would need to be "a" =
logic "0" and "b" = logic "1". Adding more control address lines will allow the multiplexer to
control more inputs. Multiplexers can be used to switch either analog, digital or video signals,
with the switching current in analogue circuits limited to below 10mA to 20mA per channel to
reduce heat dissipation.

The 74151 IC selects one-of-eight data sources. These data selectors perform parallel-to-
serial conversion. The 74151 IC is a high-speed Si-gate CMOS device and are pin compatible
with low power Schottky TTL (LSTTL). The 74151 has a strobe input which must be at a low
logic level to enable these devices. A high level at the strobe forces the Y output low and
compliment of Y output high.





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PIN LAYOUT:












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LOGIC SYMBOL :

LOGIC DIAGRAM :


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TRUTH TABLE :


PROCEDURE:
1. Connections are made as per the logic symbol.
2. Verify the Truth table for all the combinations of inputs.

RESULT: The functionality of the IC 74151 8X1 Multiplexer is verified.



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B) 2X4 Demultiplexer - 74155
AIM: To Verify the functionality of the IC 74155 2X4 Demultiplexer.
APPARATUS:
1) Digital Trainer kit
2) IC 74155
3) Connecting probes & Wires
THEORY: De-multiplexers or "De-muxes", are the exact opposite of the Multiplexers. They
have one single input data line and then switch it to any one of their individual multiple output
lines one at a time. The De-multiplexer converts the serial data signal at the input to a parallel
data at its output lines as shown below.
1-to-4 Channel De-multiplexer



The Boolean expression for this De-multiplexer is given as: F = ab A + abB + abC + abD
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The function of the De-multiplexer is to switch one common data input line to any one
of the 4 output data lines A to D in our example above. As with the multiplexer the individual
solid state switches are selected by the binary input address code on the output select pins "a"
and "b" and by adding more address line inputs it is possible to switch more outputs giving a 1-
to-2n data lines output. Some standard De-multiplexer ICs also have an "enable output" input
pin which disables or prevents the input from being passed to the selected output. Also some
have latches built into their outputs to maintain the output logic level after the address inputs
have been changed. However, in standard decoder type circuits the address input will determine
which single data output will have the same value as the data input with all other data outputs
having the value of logic "0".

The 74155 is a high speed Dual 1-of-4 Decoder/Demultiplexer. The LS155 and LS156 are
fabricated with the Schottky barrier diode process for high speed This device has two decoders
with common 2-bit Address inputs and separate gated Enable inputs. Decoder a has an Enable
gate with one active HIGH and one active LOW input. Decoder b has two active LOW Enable
inputs. If the Enable functions are satisfied, one output of each decoder will be LOW as selected
by the address inputs.


PIN LAYOUT:

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LOGIC SYMBOL:



LOGIC DIAGRAM:


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TRUTH TABLE:


PROCEDURE:
1. Connections are made as per the logic symbol.
2. Verify the Truth table for all the combinations of inputs.

RESULT: The functionality of the IC 74155 2X4 Demultiplexer is verified.
VIVA QUESTIONS:
1) What is a multiplexer?
2) What is a de-multiplexer?
3) What are the applications of multiplexer and de-
multiplexer?
4) Derive the Boolean expression for multiplexer an
d de-multiplexer.
5) How do you realize a given function using multip
lexer
6) What is the difference between multiplexer & dem
ultiplexer?
7) In 2n to 1 multiplexer how many selection lines
are there?
8) How to get higher order multiplexers?
9) Implement an 8:1 mux using 4:1 muxes?
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ADDITIONAL EXPERIMENTS












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EXPERIMENT NO: 1
FUNCTION GENERATOR USING 741 OP-AMP

I. AIM:
To generate triangular and square wave forms and to determine the time period
and frequency of the waveforms.

II. EQUIPMENTS AND COMPONENTS:


III. THEORY:
Function generator is a signal generator that produces various specific waveforms
for testpurposes over a wide range of frequencies. In laboratory type function generator
generally one of the functions (sine, triangle, etc.) is generated using dedicated chips or
standard circuits and converts it in to required signal.

Integrator (square to triangle converter):
Figure shows integrator-using op-amp. Square wave from the zero crossing detector is
fed to the integrator using op-amp. RC time constant of the integrator has been chosen in
such a way it is a small value compared to time period of the incoming square wave. As
you knew the operation of integrator, the output of the integrator is a triangle wave we
feed square wave input.
The triangular wave output of the second op amp is then fed into the third op amp, which
is also configured as an integrator. The output of the third op amp is a sine wave (the
integral of a triangular wave).

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IV. CIRCUIT DIAGRAM:


V. PROCEDURE:

1. The circuit is connected as shown in the figure.
2. The output of the comparator is connected to the CRO through chennal1, to generate a
square wave.
3. The output of the comparator is applied to integrator and is connected to the
CRO through chennal2, to generate a triangular wave.
4. The time periods of the square wave and triangular waves are noted and they are found
to be equal.

VI. THEORITICAL CALCULATIONS:
T=4R1R2C1/R3
T=4x15Kx10Kx0.1f
T=0.6ms
f = R3/4R1R2C1
(OR) 1/T
= 1.6 KHz

Vsat =Vcc-2v
=15-2v
13V

+Vramp=R2/R3Vsat
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=10k/1kx13v
=1.3v

-Vramp= - R2/R3Vsat
=-1.3v
VII. Theoretical Values:

Frequency of triangular wave =1.6KHZ
Positive peak ramp =1.2v

VIII. GRAPH:-


IX. RESULT:

The obtained value Time period of triangular wave = _________ms
Frequency of triangular wave = __________Hz
Positive peak ramp Vramp =__________V
Voltage of square wave = __________V
The theoretical and practical values of time periods are found to be equal and graphs are
drawn.

X. VIVA QUESTIONS

1. Define integrator?
2. Write about triangular wave generator?
3. Derive equation for output frequency of triangular wave?
4 . De f i n e f u n c t i o n g e n e r a t o r ?
5. Write some applications of function generator?
6. What is the function of function generator?
7. Draw the block diagram of function generator?





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EXPERIMENT NO: 2
INVERTING AND NON INVERTING OPEARATIONAL AMPLIFIERS

I. AIM: Design Inverting and Non Inverting Operational Amplifiers using 741 op amp

II. APPARATUS: 1.741 op-Amp
2. Connecting wires
III. CIRCUIT DIAGRAM:
Inverting op amp:

Non inverting op amp

IV. THEORY:
INVERTING OP AMP:
An inverting amplifier inverts and scales the input signal. As long as the op-amp gain is
very large, the amplifier gain is determined by two stable external resistors (the feedback
resistor R
f
and the input resistor R
in
) and not by op-amp parameters which are highly temperature
dependent. In particular, the R
in
R
f
resistor network acts as an electronic seesaw (i.e., a class-
1 lever) where the inverting (i.e., ) input of the operational amplifier is like a fulcrum about
which the seesaw pivots. That is, because the operational amplifier is in a negative-feedback
configuration, its internal high gain effectively fixes the inverting (i.e., ) input at the same 0 V
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(ground) voltage of the non-inverting (i.e., +) input, which is similar to the stiff mechanical
support provided by the fulcrum of the seesaw. Continuing the analogy,
Just as the movement of one end of the seesaw is opposite the movement of the other end of
the seesaw, positive movement away from 0 V at the input of the R
in
R
f
network is matched
by negative movement away from 0 V at the output of the network; thus, the amplifier is said
to be inverting.
In the seesaw analogy, the mechanical moment or torque from the force on one side of the
fulcrum is balanced exactly by the force on the other side of the fulcrum; consequently,
asymmetric lengths in the seesaw allow for small forces on one side of the seesaw to
generate large forces on the other side of the seesaw. In the inverting amplifier, electrical
current, like torque, is conserved across the R
in
R
f
network and relative differences between
the R
in
and R
f
resistors allow small voltages on one side of the network to generate large
voltages (with opposite sign) on the other side of the network. Thus, the
device amplifies (and inverts) the input voltage. However, in this analogy, it is
the reciprocals of the resistances (i.e., the conductances or admittances) that play the role of
lengths in the seesaw. Hence, the amplifier output is related to the input as in
.
So the voltage gain of the amplifier is where the negative sign is a
convention indicating that the output is negated. For example, if R
f
is 10 k and R
in
is 1 k,
then the gain is 10 k/1 k, or 10 (or 10 V/V).
[2]
Moreover, the input impedance of the
device is because the operational amplifier's inverting (i.e., ) input is a virtual ground.
In a real operational amplifier, the current into its two inputs is small but non-zero (e.g., due
to input bias currents). The current into the inverting (i.e., ) input of the operational
amplifier is drawn across the R
in
and R
f
resistors in parallel, which appears like a small
parasitic voltage difference between the inverting (i.e., ) and non-inverting (i.e., +) inputs of
the operational amplifier. To mitigate this practical problem, a third resistor of
value can be added between the non-inverting (i.e., +)
input and the true ground.
[3]
This resistor does not affect the idealized operation of the device
because no current enters the ideal non-inverting input.
NON INVERTING OP AMP:
Amplifies a voltage (multiplies by a constant greater than 1)

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The input impedance is at least the impedance between non-inverting ( ) and
inverting ( ) inputs, which is typically 1 M to 10 T, plus the impedance of the
path from the inverting ( ) input to ground (i.e., in parallel with ).
Because negative feedback ensures that the non-inverting and inverting inputs match,
the input impedance is actually much higher.
[dubious discuss]

The non-inverting ( ) and inverting ( ) inputs draw small leakage currents into the
operational amplifier.
These input currents generate voltages that act like unmodeled input offsets. These
unmodeled effects can lead to noise on the output (e.g., offsets or drift).
Assuming that the two leaking currents are matched, their effect can be mitigated by
ensuring the DC impedance looking out of each input is the same.
The voltage produced by each bias current is equal to the product of the bias current
with the equivalent DC impedance looking out of each input. Making those
impedances equal makes the offset voltage at each input equal, and so the non-zero
bias currents will have no impact on the difference between the two inputs.
A resistor of value

Which is the equivalent resistance of in parallel with , between
source and the non-inverting ( ) input will ensure the impedances looking out of
each input will be matched.
The matched bias currents will then generate matched offset voltages, and their effect
will be hidden to the operational amplifier (which acts on the difference between its
inputs) so long as the CMRR is good.
Very often, the input currents are not matched.
Most operational amplifiers provide some method of balancing the two input
currents (e.g., by way of an external potentiometer).
Alternatively, an external offset can be added to the operational amplifier input
to nullify the effect.
Another solution is to insert a variable resistor between the source and the
non-inverting ( ) input. The resistance can be tuned until the offset voltages at
each input are matched.
Operational amplifiers with MOSFET-based input stages have input currents that
are so small that they often can be neglected.


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V. PROCEDURE:
Inverting Amp
a) Construct an inverting amplifier with R
1
=2k, R
2
=39k (Figure 9-1). Calculate numerically
value of inverting amplifier gain.
b) Power the op-amp with +15V and -15V as in last experiment and apply a 1 Vp-p, 1 kHz
sinusoidal input signal to the amplifier.
c) Increase the input voltage until distortion occurs at the output. Display V
in
and V
out
at the
same time on the scope. Measure the input voltages V
in
and V
out
. From this, calculate the gain
of the inverting amplifier. Is this value close to what you have calculated in step a?
d) Capture the input, output waveforms for your lab report.
e) Measure the input resistance of the amplifier. In order to do this use 5k resistor (only use
the wiper and one end) and put it in series with the R
1
resistor at the input. Adjust the wiper
such that the gain reduces to the 50% of the value you measured in step 1-c. When this occurs,
remove the pot from the circuit and measure its resistance using a multimeter. This isthe value
of your input resistance.
Non Inverting Amp
a) Construct an inverting amplifier with R
1
=2k, R
2
=39k (Figure 9-1). Calculate numerically
value of inverting amplifier gain.
b) Power the op-amp with +15V and -15V as in last experiment and apply a 1 Vp-p, 1 kHz
sinusoidal input signal to the amplifier.
c) Increase the input voltage until distortion occurs at the output. Display V
in
and V
out
at the
same time on the scope. Measure the input voltages V
in
and V
out
. From this, calculate the gain
of the inverting amplifier. Is this value close to what you have calculated in step a Capture the
input, output waveforms for your lab report


VI. RESULT: Inverting and Non Inverting Operational Amplifiers using 741 op amp is don

VIVA QUESTIONS:
1. What is op-amp?
2. What is inverting type op-amp?
3. What is non-inverting op-amp?
4. What are the ideal characteristics of op-amp?

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DESIGN EXPIREMENTS























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EXPERIMENT NO: 1

SYNCHRONOUS 4BIT UP/DOWN COUNTER (IC 74193)

I. AIM:
To verify the truth table of counter using IC 74193.

II. APPARATUS:
1) Digital Trainer kit
2) IC 74LS192
3) Connecting probes & Wires.

III. THEORY:

IC 74193 is 4-bit binary counter. Synchronous operation is provided by having all Flip-
Flops clocked simultaneously so that output change coincident with each other when so
instructed by steering logic All four counters are fully programmable. A clear input has been
provided which forces all outputs to low level when a high level is applied. The clear function is
independent of count and load inputs. Both borrow and carry outputs are available to cascade
both up and down counting function. he DM74LS193 circuit is a synchronous up/down 4-bit
binary counter. Synchronous operation is provided by having all flip-flops clocked
simultaneously, so that the outputs change together when so instructed by the steering logic. This
mode of operation eliminates the output counting spikes normally associated with asynchronous
(ripple-clock) counters. The outputs of the four master-slave flip-flops are triggered by a LOW-
to-HIGH level transition of either count (clock) input. The direction of counting is determined by
which count input is pulsed while the other count input is held HIGH.
The counter is fully programmable; that is, each output may be preset to either level by
entering the desired data at the inputs while the load input is LOW. The output will change
independently of the count pulses. This feature allows the counters to be used as modulo-N
dividers by simply modi- fying the count length with the preset inputs. A clear input has been
provided which, when taken to a high level, forces all outputs to the low level; independent of
the count and load inputs. The clear, count, and load inputs are buffered to lower the drive
requirements of clock drivers, etc., required for long words. These counters were designed to be
cascaded without the need for external circuitry. Both borrow and carry outputs are available to
cascade both the up and down counting functions. The borrow output produces a pulse equal in
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width to the count down input when the counter underflows. Similarly, the carry output produces
a pulse equal in width to the count down input when an overflow condition exists. The counters
can then be easily cascaded by feeding the borrow and carry outputs to the count down and count
up inputs respectively of the succeeding counter

IV. PIN LAYOUT:






V. FUNCTION TABLE

CLK UP CLK DOWN LOAD CLR OPERATION

H H 0 COUNT UP
H H 0 COUNT DOWN
X X 0 0 PRESET
X X X H RESET





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VI. PROCEDURE:

1. Connect the inputs as shown in function table to the logic switches provided.
2. Connect clock to the clock input if required.
3. Connect the outputs (Carry and borrow) to the LEDS provided on the board.
4. Connect the Q
A
, Q
B
, Q
C
, and Q
D
outputs to decoder provided on panel.
5. Switch ON the trainer.
6. Note down the outputs and compare with the function table.



PRECAUTIONS:

1. All the pins should be identified properly.
2. Supply voltage should not exceed +5v.
3. Avoid loose connections on the bread board.

VII. RESULT: The truth table of counter using IC 74193 is verified.

VIII. VIVA QUESTIONS:
1. What is a counter?
2. What are the asynchronous inputs?
3. To restrict the count value of a counter, if takes the help of inputs.
4. To restrict the count value of a counter, if takes the help of inputs.
5. Define mod up counter.
6. Define mod down counter.
7. Difference b/w mod-up counter and mod-down counter











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OPEN-ENDED EXPERIMENTS







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REFERENCES


1. Anand Kumar, Pulse and Digital Circuits, PHI
2. David A. Bell, Solid State Pulse circuits, PHI
3. D.Roy Choudhury and Shail B.Jain, Linear Integrated Circuits, 2nd edition, New Age
International.
4. James M. Fiore, Operational Amplifiers and Linear Integrated Circuits: Theory and
Application, WEST.
5. J.Milliman and H.Taub, Pulse and digital circuits, McGraw-Hill.
6. Ramakant A. Gayakwad, Operational and Linear Integrated Circuits, 4th edition, PHI.
7. Roy Mancini, OPAMPs for Everyone, 2nd edition, Newnes.
8. S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits, 3rd edition,
TMH.
9. William D. Stanley, Operational Amplifiers with Linear Integrated Circuits, 4th edition,
Pearson.
10. www.analog.com.
11. www.datasheetarchive.com
12. www.ti.com