Timing conditions

Clock period should be long enough to satisfy

flip-flop setup time.
The clock period should be long enough to
allow the flip-flop outputs to change and the
combinational circuitry to change while still
leaving enough time to satisfy the setup time.
t
ck
(t
pmax
+t
cmax
+t
su
)
The difference between them is called setup
time margin.

Clock period should be long enough to satisfy
flip-flop hold time.
A hold-time violation could occur if the
change in Q fed back through the
combinational circuit and caused D to change
too soon after the clock edge.
t
pmin
+t
cmin
t
h

External input changes to the circuit should
satisfy flip-flop setup time.
A setup time violation could occur if the X
input to the circuit changes too close to the
active edge of the clock.
t
x
t
cxmax
+ t
su


External input changes to the circuit should
satisfy flip-flop hold times.
A hold-time violation could occur if the X input
to the circuit changes too close to the active
edge of the clock.
t
y
t
h
- t
cxmin


Glitches in sequential circuits
Sequential circuits often have external inputs
that are asynchronous.
Input changes can cause temporary false
values called glitches at the outputs and next
states.
Synchronous digital system
Modern microprocessors are clocked at
several gigahertz.
Wire delays are significant in these devices
compared to the clock period.
If unequal amounts of combinational circuitry
are used in the clock path to different devices,
clock skew can occur.

Control signal gating for falling edge
With clock enable
For rising edge
Tristate logic and busses
If the outputs of two gates or flip-flops are
connected together, the circuit will not
operate properly.
Multiple gate outputs should be connected to
the same wire or channel using tristate
buffers.
Tristate buffers re gates with a high
impedance state (hi-Z) in addition to high and
low logic states.

In digital systems, transferring data back and
forth between several systems components is
often necessary.
Tristate busses can be used to facilitate data
transfers between registers.
At any point, one of the gates is going to
actually drive the wire, and the other gates
should behave as if they are not connected to
the wire.
Tristate buffers
Tristate bus
8