ABSTRACT

As the number of components on a given chip increase in this billion transistor

era, System on Chip (SoC) architectures become ever more powerful. Key to this
architecture is the ability to integrate multiple heterogeneous components into a single
architecture, which requires modularity and abstraction. An integral part of this
architectural design is the methods by which the various components communicate with
one another. Network on Chip (NoC) architectures attempt to address these concerns by
providing various component level architectures with specific interconnection network
topologies and routing techniques. The design of scalable Network-on-Chip (NoC)
architectures calls for new implementations that achieve high throughput and low-latency
operation, without exceeding the stringent area-energy constraints of modern Systems-on-
Chip (SoC). Network-on-Chip (NoC) introduces the design methodology of
interconnection network into System-on-Chip (SoC). It overcomes the main
disadvantages of traditional bus based SoC, for example, large delay, small link
bandwidth and poor scalability, etc. It is widely believed that NoC will replace bus-based
architecture to become the mainstream of SoC design methodology. In NoC architecture
the processing elements (PEs) communicate with each other by exchanging messages
over the network and these messages go through buffers in each router.
On Single chip integration of storage and computational block has becoming
feasible due to continuous shrinkage of CMOS technology. Field programmable gate
arrays (FPGAs) are power efficient devices support more complex design with good
performance and low cost. For effective global on-chip communication, on-chip routers
provide essential routing functionality with low complexity and relatively high
performance. Routers implemented within FPGA can give better performance with
reduced area and hence reduced power consumption