GLCD Zle12864a Ffsswe Naa

www.zolentech.
com
13510701529
Email: contact@zolentech.com
1.0
ZLE12864A-FFSSWE-NAA
1.0
2008-9-19
PAGE
NEW RELEASE
==================================================================
A 3
TEL86-755-27457158
FAX86-755-89479734
Http://www.zolentech.com
zolentech (QQ:99563870)
ZLE12864A
E-mail:contact@zolentech.com
MSN:zolen.yang@hotmail.com
128X64 DOTS GRAPHICS MODULE
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13510701529
LCD MODULE NUMBERING SYSTEM
ZLE12864A- -
ZL
E
12864
A

ZOLEN TECHNOLOGY
COG TYPE GRAPHIC TYPE
SERIALS NUMBER FOR SM 128 COLUMNS Vs. 64 ROWS
VERSION OF PCB
N0
Remark
LCD Type
Polarizer Type
Viewing Angel
Backlight Type
Backlight Colour
LCM Temperation
Type
DC-DC Converter
Circuit
Power Supply For
Logic
Power Supply For
Backlight
ZLE12864A
Code Value
Y
B
G
F
N
P
E
R
F
T
S
T
N
E
C
D
S
N
Y
W
G
B
A
0
N
E
S
N
Y
A
B
A
B
C
Description
STN yellow/green type LCD
STN blue type LCD
STN gray type LCD
FSTN positive type LCD
FSTN negative type LCD
TN positive type LCD
TN negative type LCD
Reflecive type
Transflecive type
Transmissive type
Six oclock
Twelve oclock
Without backlight
EL backlight
CCFL backlight
Bottom LED backlight
Side LED backlight
Without backlight
Yellow/green
White
Green
Blue
Amber
Orange
Normal
Extended
Super extended
Without
With
5.0V
3.3V
5.0V
4.2V
3.3V
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1.
2.
3.
1.
2.
1.
2.
3.
ZLE12864A
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1. VDD= +5V 5% DC-DC , 5.0V

2. 128X64
3. 1/64 DUTY , 1/9 BIAS
4. FSNT ,
5. LED DC+5V
6. ST7565P
7. 6
8. -20--+70
9. -30--+80
10. MCU INTEL 8080 ( PCB 6800 )
11. MCU 8 PCB SPI
54.0 X 50.0 X 7.0T

44.0 X 29.0
128 X 64
0.32 X 0.39
0.29 X 0.36
MM
MM
DOTS
MM
MM
ZLE12864A
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ZLE12864A
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

DB0
DB1
DB2
DB3
DB4
DB5
DB6(SCL)
DB7(SI)
VDD
VSS
LEDA
/CS
/RES
A0
/WR(R/W)
/RD(E)
ZLE12864A

H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
5.0V 3.3V
0V
5.0V 3.3V
L
L
H/L
L
L
DB0DB7
DB0DB5
DB6(SCL):
DB7(SI):
LED
HL:
80 68 /
80 68
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1.
1.1
Vdd Vss
-0.3
7.0
LCD
V0 - VSS
20.0
Vi
-0.3
Vdd +0.3
1.2
Humidity
Endurance
Topr
Ttsg
RH
-20
70
-Normal temp.
version-30
80
no ondensation
95
Ta<=40 deg
100-300Hz, X/Y/Z
4.9m/ss
directions, 1 hour
0.5g
10 mS X/Y/Z
29.4m/ss
direction 1 time
3.0g
each
deg C
deg C
%
-
2.
2.1
at Ta=25 deg C, Vdd = 5V + / - 5%
Vdd-Vss
4.5
5.0
5.5
LCD
V0-VSS
Vdd = 5V
9.0
V-ih
H level
2.2
Vdd
(forD/I,
V-il
L level
0
0.6
DB0-7,RD,/E)
Icc
8
9.2
LCD
Io
0.15 0.22 0.27
V
V
V
V
mA
mA
2.2
18080
ZLE12864A
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VDD=3.3V, TA=25
Address hold time

Address setup time
System cycle time
Control L pulse width (WR)
Control L pulse width (RD)
Control H pulse width (WR)
Control H pulse width (RD)
WRITE Data set-up time
WRITE Data hold time
READ access time
READ Output disable time
A0
WR
RD
WR
RD
D0
D7
TAH8
TAS8
TCYC8
TCCLW
TCCLR
TCCHW
TCCHR
TDS8
TDH8
TACC8
TCH8
0
0
240
80
140
80
80
40
0
5.0
70
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. The input signal rise time and fall time (Tr, Tf) is specified at 15 ns or less. When the system
cycle time is extremely fast, (Tr+Tf) (TCYC8-TCCLW-TCCHW) for (Tr+Tf)
(TCYC8-TCCLR-TCCHR) are specified.
2. All timing is specified using 20% and 80% of VDD as the reference.
3. TCCLW and TCCLR are specified as the overlap between /CS1 being L (CS2=H) and
/WRand /RD being at the L level.
26800
ZLE12864A
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VDD=3.3V, TA=25
Address hold time

Address setup time
System cycle time
Control L pulse width (WR)
Control L pulse width (RD)
Control H pulse width (WR)
Control H pulse width (RD)
WRITE Data set-up time
WRITE Data hold time
READ access time
READ Output disable time
A0
WR
RD
WR
RD
D0
D7
TAH6
TAS6
TCYC6
TCCLW
TCCLR
TCCHW
TCCHR
TDS6
TDH6
TACC6
TCH6
0
0
240
80
140
80
80
40
0
5.0
70
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.The input signal rise time and fall time (Tr, Tf) is specified at 15 ns or less. When the system cycle
time is extremely fast, (Tr+Tf) (TCYC6-TEWLW-TEWHW) for (Tr+Tf)
(TCYC6-TEWLR-TEWHR)are specified.
2.All timing is specified using 20% and 80% of VDD as the reference.
3.TEWLW and TEWLR are specified as the overlap between /CS1 being L (CS2=H) and E.
3
1. The input signal rise time and fall time (Tr, Tf) is specified at 15 ns or less.
2. All timing is specified using 20% and 80% of VDD as the reference.
ZLE12864A
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13510701529
CR
tr
25
25
---
tf
25
1-2
1, 2
Ff
25
25
160
-240
ms
1
2
--
100
150
ms
--
--
60
-40
--
40
DEG
--
70
--
Hz
12
(1): :
CR=
(a). ------------25C
(b). ------64Hz
ZLE12864A
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(c). ----------=0, =0
(d). ---5.0V
(2): :
+ Vop
1 /f F
-V o p
1-brightness
9 0%
1 0%
tr
:
(a).
(b).
(c).
(d).
tf
------------25C
------64Hz
----------=0, =0
---5.0V
(3): :
TOP-BOTTOM DIRECTION
RIGHT-LEFT DIRECTION
TOP
1
2
BOTTOM
LEFT
RIGHT
ZLE12864A
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1
Command
(1) Display
ON/OFF
(2) Display start
line set
(3) Page address
set
(4) Column
address set
upper bit
Column address
set
lower bit
(5) Status read
Command Code
A0
RD
W
R
0
0
0
Function
D7 D6
D5
D4
Display start address
Page address
Most significant
Sets the most significant 4 bits of
column address
Least significant
the display RAM column address.

Sets the least significant 4 bits of
column address
the display RAM column address.
Reads the status data
0
1
LCD display ON/OFF 0: OFF, 1: ON
Write data
Writes to the display RAM
Read data
Reads from the display RAM
(8) ADC select
(9) Display normal/

reverse
(10) Display all

points ON/OFF
(11) LCD bias set
Sets the display RAM display start line

address
Sets the display RAM page address
(6) Display data

write
(7) Display data
read
Status
D3 D2 D1 D0
0
1
0
1
0
1
0
1
Sets the display RAM address SEG output

correspondence 0: normal, 1: reverse
Sets the LCD display normal/ reverse 0:
normal, 1: reverse
Display all points 0: normal display 1: all
points ON
Sets the LCD drive voltage bias ratio 0: 1/9,
1: 1/7
Column address increment
(12)
Read/modify/write
At write: +1
At read: 0
(13) End
Clear read/modify/write
(14) Reset
Internal reset
(15) Common
output mode select
Select COM output scan direction 0: normal

direction 1: reverse direction
1
*
0
*
0 0 0 0 0 1 Electronic
volume value
Set the V5output voltage electronic volume

register
1
*
0
*
1
*
0: OFF, 1: ON Set the flashing mode
(16) Power control

set
(17) V5voltage
regulator internal
resistor ratio set
(18) Electronic
volume
mode set
Electronic volume
register set
(19) Static indicator
ON/OFF Static
indicator register
set
0
*
0
1
1
*
Operating
mode
Select internal power supply operating mode
Resistor
ratio
1
*
Select internal resistor ratio(Rb/Ra) mode
00
1Mode
Display OFF and display all points ON

compound command
(20) Power saver

(21) NOP
(22) Test
ZLE12864A
Command for non-operation

Command for IC test. Do not use this
command
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2.
(1) Display ON/OFF
A0
E(RD)
R/W(WR)
D7
D6
D5
D4
D3
D2
D1
D0
Function
1
0
Display All Points ON 10Display OFF

Power Save display off
(2)
Display Start line Set
RAM (line address)

A0
E(RD)
R/W(WR) D7 D6 D5 D4
0
D3
D2
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D1 D0
0
0
1
Line address
0
1
0
0
1
2
1
1
0
1
62
63
06362 21
8 PAGE0 1 063 0X40
(3)
Page Address Set
page address(column address) RAM
0 4-1
A0
E(RD)
R/W(WR)
0
D7
D6
D5
D4
D3
D2
D1 D0
Page address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
2
1
1
1
1
1
1
1
1
1
1
0
1
62
63
(4) Column Address Set

RAM Column Address.
. RAM 131
. 128 131 0
.
A0
0
E(RD) R/W(WR)
0
ZLE12864A
D7
D6
D5
D4
BUSY ADC ON/OFF RESET
D3
0
D2 D1
0
D0
0
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(5)
13510701529
Status Read
BUSY
BUSY=1
BUSY=0
ADC
ADC
0: ( 131-n ---SEG n)
1: ( n---SEG n)
(ADC
ADC 1
8)
ON/OFF
0:
1:
1,/.
/RESET
/reset
0:
1:
(6) Display Data Write

RAMcolumn address 1
RAM
A0
E(RD)
R/W(WR)
D7
D6
D5
D4
D3
D2
D1
D0
1
(7)
Write data
Display Data Read
RAM
A0
E(RD)
R/W(WR)
D7
D6
D5
D4
D3
D2
D1
1
D0
Read data
(8) ADC Select (Segment Driver Direction Select)

RAM ADC
0127 ADC 1314 ADC
15
ADC0xa0Common Output Mode Select0xc8 0632
1 0127ADC0xa1Common Output Mode Select

0xc0 06321
4131
(9)
A0
E(RD)
R/W(WR)
0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
Function
Display Normal/Reverse
ZLE12864A
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RAM RAM
A0
E(RD)
R/W(WR)
D7
D6
D5
D4
D3
D2
D1
D0
Function
0
1
(10) Display All Points ON/OFF

RAM RAM
RAM
Display Normal/Reverse Normal mode
A0
E(RD) R/W(WR) D7
(11)
D6 D5
D4 D3
D2 D1
D0
0
1
Function
Normal mode
Dislay all points on
LCD Bias Set
LCD 1/9. 1/9
A0
E(RD) R/W(WR) D7
D6 D5
D4 D3
D2 D1
D0
Function
0
1
1/9 bias
1/7 bias
(12) Read/Modify/Write
END RAM ,
columnaddressEND
END Read/Modify/Write
MPU
A0
E(RD)
R/W(WR)
D7
D6
column address set
D5
D4
D3
D2
D1
D0
(13) END
read/modify/write Column address read/modify/write
A0
E(RD)
R/W(WR)
0
D7
1
D6
1
D5
D4
D3
D2
D1
D0
(14) RESET
ADCread/modify/write
test RAM
ZLE12864A
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A0
E(RD)
R/W(WR)
D7
D6
D5
D4
D3
D2
D1
D0
/RESET
(15) Common Output Mode Select

15Common Output Mode Select normal 0
636221Common Output Mode Select reverse , 0
636221 15 reverse
8 8
A0
E(RD) R/W(WR) D7
D6 D5
D4 D3
D2 D1
0
1
D0
Function
Normal:C1C63---C0
Reverse:C0C63C1
(16) Power Controller Set

0X2F
A0
E(RD) R/W(WR) D7
D6 D5
D4 D3
D2 D1
D0
0
1
Function
Booster circuit: OFF
Booster circuit: ON
0
1
0
1
Voltage regulator circuit:OFF

Voltage regulator circuit: ON
Voltage follower circuit: OFF
Voltage follower circuit: ON
(17) V0 Voltage Regulator Internal Resistor Ration Set

LCD LCD
5V 0X24 18
18
A0
E(RD)
R/W(WR)
0
D7
D6
D5
D4
D3
D2
0
0
0
D1 D0
0
0
1
0
1
0
1
1
1
1
0
1
Page address
Small
Large
(18)
The Electronic Volume (Double Byte Command)
LCD Electronic Volume Mode
0X81
18-1 The Electronic Volume Mode Set
Electronic Volume Register Set Electronic
Volume Register Set The Electronic Volume Mode Set
A0
E(RD)
R/W(WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
ZLE12864A
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18-2 Electronic Volume Register Set

6 electronic volume register 64 5V
0X20
A0
E(RD)
R/W(WR)
0
D7
D6
D5
D4
D3
D2
0
0
0
D1 D0
0
0
1
Page address
0
1
0
1
1
1
1
0
1
Small
Large
(19)
Static Indicator ()
Static Indicator ON/OFF
A0
E(RD)
R/W(WR) D7
0
(20)
D6
D5
D4
D3
D2
D1
D0
0
1
V0
OFF
ON
The Booster Ratio (Double Byte Command)
internal booster circuit Booster Ratio Select Mode Set

Booster Ratio Register Set
20-1 Booster Ratio Select Mode Set

A0
E(RD)
R/W(WR)
D7
D6
D5
D4
D3
D2
D1
D0
0
20-2Booster Ratio Register Set

A0
E(RD)
R/W(WR) D7
0
D6
D5
D4
D3
D2
D1
D0
Blinking
Page
0
0
1
0
1
1
2x,3x,4x
5x
6x
(21) Power Save (Compound Command)

display all points ON display OFF 19
STATIC NDICATOR ON Standby Mode,
19
STATIC INDICATOR
OFFSleep Mode
STATICINDICATOR 19 OFF
display all points OFF
display ON
(22)
NOP
A0
E(RD)
R/W(WR)
0
D7
D6
D5
D4
D3
D2
D1
D0
ZLE12864A
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13510701529
/*
**128X64(KS0108)
**: 0755-33875670,33875671
**E-mail: contact@zolentech.com
*/
#include <reg52.h>
#include <intrins.h>
//************************
sbit cs =P2^4;
sbit rst =P2^3;
sbit a0 =P2^2;
sbit wr =P2^0;
sbit rd =P2^1;
//******************************************************
#define dataport P0
#define nop() _nop_()
unsigned char code tab1[]=
{/*-- x=128x64 --*/
0xFF,0xFF,0xFF,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,
0x07,0x07,0x07,0x87,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x87,0x87,
0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0xFF,0xFF,0xFF,
0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFC,0x03,0x00,0x00,
0x00,0x01,0x86,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x03,0xFC,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x0F,0xF0,0x00,0xF0,0x0F,0xFF,0x00,0x00,
0xFE,0x01,0x00,0x00,0x00,0x01,0xFE,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x03,0xFC,
0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0xFF,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x07,0x04,0x04,0xC4,0xC4,0xC4,0xC4,0xC0,0x00,0x01,0xC2,0xC4,0xC4,
ZLE12864A
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13510701529
0xC4,0xC2,0x01,0x00,0x00,0x07,0x04,0x04,0x84,0xC4,0xC3,0xC0,0x00,0x00,0xC0,0xC0,
0xC0,0x80,0x80,0x00,0x00,0x00,0xC0,0xC7,0xC0,0xC1,0xC6,0xC1,0xC0,0x47,0x00,0x00,
0x01,0x02,0x04,0x04,0x04,0x02,0x01,0xC0,0xC0,0xC7,0xC4,0xC4,0xC4,0xC4,0x03,0x00,
0xC0,0xC0,0xC1,0xC2,0xC4,0x04,0x04,0x42,0xC1,0xC0,0xC0,0xC7,0xC4,0x84,0x04,0x04,
0x04,0x44,0xC0,0xC0,0xC7,0x44,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x01,0x80,0xE0,0xF0,0xFC,0xFF,0x7F,0x1F,0x07,
0x03,0x00,0xC0,0x00,0x00,0x00,0xFC,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x01,
0x8F,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0x1F,0x00,0x30,
0x38,0xFC,0x00,0x87,0x8F,0x00,0x00,0x00,0xF8,0xF1,0x03,0x0F,0x1F,0x3F,0xFF,0xFE,
0xF8,0xF0,0xE3,0x87,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x80,0x00,0x80,0x00,0x8C,0x8E,0x0F,0x8F,0x0F,0x83,0x80,0x08,0x8C,0x0C,
0x8E,0x0F,0x0F,0x00,0x00,0x00,0x80,0x83,0x87,0x87,0x0F,0x0E,0x8C,0x80,0x0C,0x0E,
0x0F,0x07,0xF7,0x03,0x00,0x00,0x8C,0x8F,0x8F,0x0F,0x8F,0x8F,0x80,0x80,0x00,0x8C,
0xEC,0x8C,0x8F,0x0F,0x00,0x80,0x80,0x88,0x0F,0x0F,0x8F,0x8F,0x8F,0x00,0xF0,0x88,
0x8C,0x8C,0x0C,0x0F,0x0F,0x00,0x08,0x0C,0x0F,0x8F,0x8C,0x88,0x00,0x00,0x80,0x81,
0x03,0x07,0x8F,0x8F,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x80,0xC1,0x07,0x00,0x07,0x01,0x01,0x07,0x80,0x47,0x41,0x41,0x87,0x00,0x07,
0xC7,0xC4,0x04,0x00,0x03,0x05,0x05,0x05,0x00,0x03,0x04,0x04,0x02,0x00,0xC7,0x40,
0x43,0x40,0x47,0xC0,0x47,0x40,0x47,0x00,0x00,0x80,0x40,0x40,0x40,0x40,0x80,0x00,
0x01,0x01,0xFF,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x40,0x20,0x10,0x08,0x07,0x00,
0x00,0xE3,0x14,0x08,0x08,0x08,0x14,0xE3,0x00,0x00,0x00,0xC3,0x24,0x18,0x24,0xC3,
0x00,0x00,0x00,0xFE,0x09,0x04,0x04,0x04,0x08,0xF1,0x00,0x00,0x60,0x58,0x44,0x43,
0x40,0xFF,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,
0x00,0x00,0x00,0x81,0x7E,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,
0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0xC3,0x04,0x08,0x08,0x10,0x10,0x10,0xE1,
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0xFF,0xFF,0xFF,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,
0xE0,0xE0,0xE3,0xE0,0xE0,0xE0,0xE0,0xE0,0xE3,0xE2,0xE2,0xE2,0xE2,0xE2,0xE2,0xE0,
0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xFF,0xFF,0xFF,
};
//**************delay************************************
void delay_nms(unsigned int n)
{
unsigned int i,j;
for(i=n;i>0;i--)
{
for(j=125;j>0;j--)
{
}
}
}
//***************write command*****************************
void wr_com(unsigned char com)
{
a0=0;
cs=0;
rd=1;
wr=0;
nop();
dataport=com;
nop();
wr=1;
cs=1;
}
//***************write data********************************
void wr_data(unsigned char dat)
{
a0=1;
cs=0;
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rd=1;
wr=0;
nop();
dataport=dat;
nop();
wr=1;
cs=1;
}
//**********************************************************
void display_kuang()
{
unsigned char seg;
unsigned char page;
for(page=0xb0;page<0xb8;page++)
{
if(page==0xb0)
{
wr_com(page);
wr_com(0x10);
wr_com(0x00);
for(seg=0;seg<128;seg++)
{
if(seg==0) wr_data(0xff);
else if(seg==127) wr_data(0xff);
else
wr_data(0x01);
}
}
else
{
if(page==0xb7)
{
wr_com(page);
wr_com(0x10);
wr_com(0x00);
{
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else
13510701529
wr_data(0x80);
}
}
else
{
wr_com(page);
wr_com(0x10);
wr_com(0x00);
{
else
wr_data(0x00);
}
}
}
}
}
//**********************************************************
void display_lattice(unsigned char dat1,unsigned char dat2)
{
unsigned char seg;
unsigned char page;
{
wr_com(page);
wr_com(0x10);
wr_com(0x00);
{ wr_data(dat1);
wr_data(dat2);
}
}
}
//**********************************************************
void display_map(unsigned char *p)
{
unsigned char seg;
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unsigned char page;

{
wr_com(page);
wr_com(0x10);
wr_com(0x00);
{ wr_data(*p);
++p;
}
}
}
//**********************************************************
void main()
{
delay_nms(100);
rst=0;
delay_nms(100);
rst=1;
delay_nms(100);
//**********lcd inintial************
wr_com(0xa0);
//ADC normal
wr_com(0xc8);
//com normal
wr_com(0xa3);
//set partial display duty 1/65
wr_com(0x2c);
//vc on
delay_nms(100);
wr_com(0x2e);
//vr on
delay_nms(100);
wr_com(0x2f);
//internal booster,follower,divided on
wr_com(0x24);
//set rb/ra=5.29
wr_com(0x81);
//set reference voltage select
wr_com(0x15);
delay_nms(100);
wr_com(0xaf);
wr_com(0x40);
//set start line 00
//************************************
while(1)
{
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display_lattice(0xff,0xff);
delay_nms(1000);
display_kuang();
delay_nms(1000);
display_lattice(0x55,0x55);
delay_nms(1000);
display_lattice(0x00,0xff);
delay_nms(1000);
display_lattice(0x55,0xaa);
delay_nms(1000);
display_map(tab1);
delay_nms(2000);
}
}
**********************************************************************
//************************************
#include <reg52.h>
#include <intrins.h>
//******************************************************
sbit cs =P2^4;
sbit rst =P2^3;
sbit a0 =P2^2;
sbit di =P2^0;
sbit scl =P2^1;
//******************************************************
#define nop() _nop_()
unsigned char code tab1[]=
{/*-- x=128x64 --*/
ZLE12864A
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0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFC,0x03,0x00,0x00,
0x00,0x01,0x86,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x03,0xFC,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x0F,0xF0,0x00,0xF0,0x0F,0xFF,0x00,0x00,
0xFE,0x01,0x00,0x00,0x00,0x01,0xFE,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x03,0xFC,
0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0xFF,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x07,0x04,0x04,0xC4,0xC4,0xC4,0xC4,0xC0,0x00,0x01,0xC2,0xC4,0xC4,
0xC4,0xC2,0x01,0x00,0x00,0x07,0x04,0x04,0x84,0xC4,0xC3,0xC0,0x00,0x00,0xC0,0xC0,
0xC0,0x80,0x80,0x00,0x00,0x00,0xC0,0xC7,0xC0,0xC1,0xC6,0xC1,0xC0,0x47,0x00,0x00,
0x01,0x02,0x04,0x04,0x04,0x02,0x01,0xC0,0xC0,0xC7,0xC4,0xC4,0xC4,0xC4,0x03,0x00,
0xC0,0xC0,0xC1,0xC2,0xC4,0x04,0x04,0x42,0xC1,0xC0,0xC0,0xC7,0xC4,0x84,0x04,0x04,
0x04,0x44,0xC0,0xC0,0xC7,0x44,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x01,0x80,0xE0,0xF0,0xFC,0xFF,0x7F,0x1F,0x07,
0x03,0x00,0xC0,0x00,0x00,0x00,0xFC,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x01,
0x8F,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0x1F,0x00,0x30,
0x38,0xFC,0x00,0x87,0x8F,0x00,0x00,0x00,0xF8,0xF1,0x03,0x0F,0x1F,0x3F,0xFF,0xFE,
0xF8,0xF0,0xE3,0x87,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x80,0x00,0x80,0x00,0x8C,0x8E,0x0F,0x8F,0x0F,0x83,0x80,0x08,0x8C,0x0C,
0x8E,0x0F,0x0F,0x00,0x00,0x00,0x80,0x83,0x87,0x87,0x0F,0x0E,0x8C,0x80,0x0C,0x0E,
0x0F,0x07,0xF7,0x03,0x00,0x00,0x8C,0x8F,0x8F,0x0F,0x8F,0x8F,0x80,0x80,0x00,0x8C,
0xEC,0x8C,0x8F,0x0F,0x00,0x80,0x80,0x88,0x0F,0x0F,0x8F,0x8F,0x8F,0x00,0xF0,0x88,
0x8C,0x8C,0x0C,0x0F,0x0F,0x00,0x08,0x0C,0x0F,0x8F,0x8C,0x88,0x00,0x00,0x80,0x81,
0x03,0x07,0x8F,0x8F,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x80,0xC1,0x07,0x00,0x07,0x01,0x01,0x07,0x80,0x47,0x41,0x41,0x87,0x00,0x07,
0xC7,0xC4,0x04,0x00,0x03,0x05,0x05,0x05,0x00,0x03,0x04,0x04,0x02,0x00,0xC7,0x40,
ZLE12864A
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0x43,0x40,0x47,0xC0,0x47,0x40,0x47,0x00,0x00,0x80,0x40,0x40,0x40,0x40,0x80,0x00,
0x01,0x01,0xFF,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x40,0x20,0x10,0x08,0x07,0x00,
0x00,0xE3,0x14,0x08,0x08,0x08,0x14,0xE3,0x00,0x00,0x00,0xC3,0x24,0x18,0x24,0xC3,
0x00,0x00,0x00,0xFE,0x09,0x04,0x04,0x04,0x08,0xF1,0x00,0x00,0x60,0x58,0x44,0x43,
0x40,0xFF,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,
0x00,0x00,0x00,0x81,0x7E,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,
0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0xC3,0x04,0x08,0x08,0x10,0x10,0x10,0xE1,
0xFF,0xFF,0xFF,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,
0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xE0,0xFF,0xFF,0xFF,
};
//**************delay************************************
void delay_nms(unsigned int n)
{
unsigned int i,j;
for(i=n;i>0;i--)
{
for(j=125;j>0;j--)
{
}
}
}
//***************send_data********************************
void data_send(unsigned char dat)
{
unsigned char s,temp;
int i;
scl=0;
s=dat;
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for(i=8;i>0;i--)
{ scl=0;
nop();
nop();
temp=s&0x80;
if(temp)
{di=1;
}
else
{di=0;
}
scl=1;
s=s<<1;
}
}
//***************write command*****************************
void wr_com(unsigned char com)
{
a0=0;
cs=0;
data_send(com);
cs=1;
}
//***************write data********************************
void wr_data(unsigned char dat)
{
a0=1;
cs=0;
data_send(dat);
cs=1;
}
//**********************************************************
void display_kuang()
{
unsigned char seg;
unsigned char page;
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{
if(page==0xb0)
{
wr_com(page);
wr_com(0x10);
wr_com(0x00);
{
else
wr_data(0x01);
}
}
else
{
if(page==0xb7)
{
wr_com(page);
wr_com(0x10);
wr_com(0x00);
{
else
wr_data(0x80);
}
}
else
{
wr_com(page);
wr_com(0x10);
wr_com(0x00);
{
else
wr_data(0x00);
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13510701529
}
}
}
}
//**********************************************************
void display_lattice(unsigned char dat1,unsigned char dat2)
{
unsigned char seg;
unsigned char page;
{
wr_com(page);
wr_com(0x10);
wr_com(0x00);
{ wr_data(dat1);
wr_data(dat2);
}
}
}
//**********************************************************
//**********************************************************
void display_map(unsigned char *p)
{
unsigned char seg;
unsigned char page;
{
wr_com(page);
wr_com(0x10);
wr_com(0x00);
{ wr_data(*p);
++p;
}
}
}
//**********************************************************
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void main()
{
delay_nms(100);
rst=0;
delay_nms(100);
rst=1;
delay_nms(100);
//**********lcd inintial************
wr_com(0xa0);
//ADC normal
wr_com(0xc8);
//com normal
wr_com(0xa3);
//set partial display duty 1/65
wr_com(0x2c);
//vc on
delay_nms(100);
wr_com(0x2e);
//vr on
delay_nms(100);
wr_com(0x2f);
//internal booster,follower,divided on
wr_com(0x24);
//set rb/ra=5.29
wr_com(0x81);
//set reference voltage select
wr_com(0x15);
delay_nms(100);
wr_com(0xaf);
wr_com(0x40);
//set start line 00
//************************************
while(1)
{
display_lattice(0xff,0xff);
delay_nms(1000);
display_kuang();
delay_nms(1000);
display_lattice(0x55,0x55);
delay_nms(1000);
display_lattice(0x00,0xff);
delay_nms(1000);
display_lattice(0x55,0xaa);
delay_nms(1000);
display_map(tab1);
delay_nms(2000);
}
ZLE12864A
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9.1
40W 30cm
45
9.2
A
B
C
A
ZLE12864A
Zone:
Zone:
Zone:
Zone +
B Zone=
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9.3
13510701529
Zone
DIMENSION(MM)
D0.1
0.1<D0.2
0.2<D0.3
0.3<D
D=(+)/2
*
5
0
0
*
5
1
0
C
*
*
*
*
Acceptable Number
Zone
X(mm)
Y(mm)
A
B
0.02W
*
*
2.0L
0.03W
3
3
1.0L
0.04W
1
2
1.0L
0.05W
0
2
0.05<W
Not acceptable
X: Y: *
Dimension(mm)
(
)
*:
Zone
D0.1
0.1<D0.2
0.2<D0.3
0.3<D
A
*
5
0
0
B
*
5
1
0
C
*
*
*
*
C
*
*
*
*
(1)
(2)
ZLE12864A
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13510701529
.
(3)
(X+Y)/2<0.2mm ( 0.1mm )
4
5
6
ZLE12864A
.
LCD .
.
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13510701529
2
0.1
3
CMOS
1
2
3
4
5 RH60%
6
4
1
2
3 PCB
4
5
6
5
1 280
2 4
3
4
5 5
6
1
ZLE12864A
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2
IC
3
4
10 1
8
7
1
2 -10C --- +35C
3
4
5 /
1
2
3
4
5
6
ZLE12864A
PAGE: 35 OF35

GLCD Zle12864a Ffsswe Naa

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128X64 DOTS GRAPHICS MODULE

LCD MODULE NUMBERING SYSTEM

128X64 DOTS GRAPHICS MODULE

128X64 DOTS GRAPHICS MODULE

1. VDD= +5V 5% DC-DC , 5.0V

54.0 X 50.0 X 7.0T

128X64 DOTS GRAPHICS MODULE

128X64 DOTS GRAPHICS MODULE

128X64 DOTS GRAPHICS MODULE

128X64 DOTS GRAPHICS MODULE

Address hold time

128X64 DOTS GRAPHICS MODULE

Address hold time

128X64 DOTS GRAPHICS MODULE

128X64 DOTS GRAPHICS MODULE

128X64 DOTS GRAPHICS MODULE

Display start address

Sets the most significant 4 bits of

the display RAM column address.

the display RAM column address.

Reads the status data

LCD display ON/OFF 0: OFF, 1: ON

Writes to the display RAM

Reads from the display RAM

(8) ADC select

(9) Display normal/

(10) Display all

(11) LCD bias set

Sets the display RAM display start line

(6) Display data

Sets the display RAM address SEG output

Select COM output scan direction 0: normal

Set the V5output voltage electronic volume

0: OFF, 1: ON Set the flashing mode

(16) Power control

Select internal power supply operating mode

Select internal resistor ratio(Rb/Ra) mode

Display OFF and display all points ON

(20) Power saver

Command for non-operation

128X64 DOTS GRAPHICS MODULE

Display All Points ON 10Display OFF

Display Start line Set

RAM (line address)

(4) Column Address Set

BUSY ADC ON/OFF RESET

128X64 DOTS GRAPHICS MODULE

(6) Display Data Write

Display Data Read

(8) ADC Select (Segment Driver Direction Select)

1 0127ADC0xa1Common Output Mode Select

128X64 DOTS GRAPHICS MODULE

(10) Display All Points ON/OFF

LCD Bias Set

LCD 1/9. 1/9

column address set

128X64 DOTS GRAPHICS MODULE

(15) Common Output Mode Select

(16) Power Controller Set

Voltage regulator circuit:OFF

(17) V0 Voltage Regulator Internal Resistor Ration Set

128X64 DOTS GRAPHICS MODULE