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Quad 2-input NAND gate (Y = A nand B)
14: X 13: IN 12: IN 11: OUT 10: IN 9: IN 8: OUT
7400 Vcc A4 B4 Y4 A3 B3 Y3
1: IN 2: IN 3: OUT 4: IN 5: IN 6: OUT 7: X
A1 B1 Y1 A2 B2 Y2 GND
Quad 2-input NOR gate (Y = A nor B)
14: X 13: OUT 12: IN 11: IN 10: OUT 9: IN 8: IN
7402 Vcc Y4 A4 B4 Y3 A3 B3
1: OUT 2: IN 3: IN 4: OUT 5: IN 6: IN 7: X
Y1 A1 B1 Y2 A2 B2 GND
Quad 2-input NAND gate with Open Collector Outputs (Y = A nand B)
14: X 13: IN 12: IN 11: OUT 10: IN 9: IN 8: OUT
7403 Vcc A4 B4 Y4 A3 B3 Y3
1: IN 2: IN 3: OUT 4: IN 5: IN 6: OUT 7: X
A1 B1 Y1 A2 B2 Y2 GND
Hex Inverter
14: X 13: IN 12: OUT 11: IN 10: OUT 9: IN 8: OUT
7404 Vcc A6 A6’ A5 A5’ A4 A4’
1: IN 2: OUT 3: IN 4: OUT 5: IN 6: OUT 7: X
A1 A1’ A2 A2’ A3 A3’ GND
Quad 2-input AND gate (Y = A and B)
14: X 13: IN 12: IN 11: OUT 10: IN 9: IN 8: OUT
7408 Vcc A4 B4 Y4 A3 B3 Y3
1: IN 2: IN 3: OUT 4: IN 5: IN 6: OUT 7: X
A1 B1 Y1 A2 B2 Y2 GND
Quad 2-input NAND gate with Open Collector Outputs (Y = A and B)
14: X 13: IN 12: IN 11: OUT 10: IN 9: IN 8: OUT
7409 Vcc A4 B4 Y4 A3 B3 Y3
1: IN 2: IN 3: OUT 4: IN 5: IN 6: OUT 7: X
A1 B1 Y1 A2 B2 Y2 GND
Quad 2-input OR gate (Y = A or B)
14: X 13: IN 12: IN 11: OUT 10: IN 9: IN 8: OUT
7432 Vcc A4 B4 Y4 A3 B3 Y3
1: IN 2: IN 3: OUT 4: IN 5: IN 6: OUT 7: X
A1 B1 Y1 A2 B2 Y2 GND
Dual 2-wide 2-input AND-OR-INVERT gate (Y = (A1·A2+B1·B2)’)
14: X 13: IN2 12: - 11: - 10: IN2 9: IN2 8: OUT2
7451 Vcc A2 B1 B2 Y
1: IN2 2: IN1 3: IN1 4: IN1 5: IN1 6: OUT1 7: X
A1 A1 A2 B1 B2 Y GND
Quad 2-input XOR gate (Y = A xor B)
14: X 13: IN 12: IN 11: OUT 10: IN 9: IN 8: OUT
7486 Vcc A4 B4 Y4 A3 B3 Y3
1: IN 2: IN 3: OUT 4: IN 5: IN 6: OUT 7: X
A1 B1 Y1 A2 B2 Y2 GND