Verilog Codes of Project

Rs 232 module:
module test_module(
input clk,
input rst,
input serial_in,
output [7:0] data_out,
output serial_out
);
wire
[7:0]
connect;
transmitter_frame uut1 (.clk(clk), .rst(rst),.tx_out(serial_out));

receiver_frame uut2 (.clk(clk),.rst(rst),.rx(serial_in),.data_out(data_out));
endmodule
Internal modules of RS232:

Module 1:
module transmitter_frame(
input clk,
input rst,
output tx_out
);
wire
[7:0]
connection;
transmitter_1 uut1 (.clk(clk),.rst(rst),.tx(connection));

transmitter_2 uut2 (.in(connection),.clk(clk),.out(tx_out));
endmodule
Module 1.1:
module transmitter_1(
input clk,
input rst,
output
reg
[7:0]
tx
);
reg
[20:0] count=21'b0;
reg
[15:0] rx_count=16'b0;
reg
present=1'b0,next=1'b0;
parameter
[7:0]
parameter
A=1'b0,B=1'b1;
always@(posedge
F=8'h46;
clk)
begin
if(rst)
begin
tx<=8'b0;
end
else
begin
present<=next;
begin
case(present)
A:
begin
tx<=F;
count<=0;
if(rx_count==52484)
begin
next<=B;
end
else
begin
rx_count<=rx_count+1;
end
end
B:
begin
tx<=8'b11111111;
rx_count<=0;
if(count==1999998)
begin
next<=A;
end
else
begin
count<=count+1;
end
end
default:
begin
next<=A;
rx_count<=0;
tx<=1;
count<=0;
end
endcase
end
end
end
endmodule
Module 1.2:
module transmitter_2(
input clk,
input [7:0] in,
output out
);
reg [7:0] temp1=8'b0;

reg [9:0] temp2=10'b0;
reg [3:0] value=4'd9;
reg [12:0] count=13'b0;
reg out_reg=1'b1;
always@(posedge clk)
begin
if(in==8'h46)
begin
temp1<=in;
temp2[9]<=0;
temp2[8]<=temp1[0];
temp2[7]<=temp1[1];
temp2[6]<=temp1[2];
temp2[5]<=temp1[3];
temp2[4]<=temp1[4];
temp2[3]<=temp1[5];
temp2[2]<=temp1[6];
temp2[1]<=temp1[7];
temp2[0]<=1;
out_reg<=temp2[value];
if(count==5244)
begin
count<=0;
value<=value-1;
if(value==0)
begin
value<=4'd9;
end
end
else
begin
count<=count+1;
end
end
else
begin
out_reg<=1'b1;
value<=0;
end
end
assign out=out_reg;
endmodule
Module 2:
module receiver_frame(
input clk,
input rst,
input rx,
output [7:0] data_out
);
wire
[7:0]
data;
RX
r_x(.clk(clk),.rst(rst),.rx(rx),.seven_segment(data));
rcv r (.din(data),.clk(clk),.rst(rst),.dout(data_out));
endmodule
Module 2.1:
module RX(
input clk,
input rst,
input rx,
//output led1,
// output led2,
output [7:0] seven_segment
// output pulse_out
);
wire
sampling_signal;
baud_generator
b_g(.clk(clk),.sampling_clk(sampling_signal)/*,.baud_clk(baud_clk)*/);
receiver_module
r_m(.sampling_clk(sampling_signal),.rst(rst),.rx(rx)/*,.led1(led1),.led2(led2)*/,.seven_segme
nt(seven_segment)/*,.pulse_out(pulse_out)*/);
endmodule
Module 2.1.1:
module baud_generator(
input clk,
// output
output
reg baud_clk,
reg sampling_clk
);
//
reg
[51:0] count;
reg
[12:0] sample_count;
initial
begin
//
baud_clk<=0;
sampling_clk<=0;
//
count<=0;
sample_count<=0;
end
always@(posedge
clk)
begin
//
count<=count+1;
sample_count<=sample_count+1;
//
//
if(count==2603)
begin
//
count<=0;
//
baud_clk<=baud_clk+1;
//
end
if(sample_count==162)
begin
sample_count<=0;
sampling_clk<=sampling_clk+1;
end
end
endmodule
Module 2.1.2:
module receiver_module(
input sampling_clk,
input rst,
input rx,
//output led1,
// output led2,
output tx,
output [7:0] seven_segment
// output pulse_out
);
//
reg
[20:0] pulse_count=21'bz;
reg
[3:0]
sample_count=4'b0;
reg
[2:0]
bit_count=3'b0;
reg
[7:0]
rxout_reg=8'b0;
reg
[7:0]
data_reg=8'b0;
reg
[7:0]
ssreg=8'hz;
reg
[3:0]
present=4'h0,next=4'b0;
//
reg
led_1,led_2;
//
reg
pulse_out_reg;
parameter
[3:0]
parameter
data_bit=8,stop_bit_tick=15;
always@(posedge
begin
if(rst)
idle=4'b0000,start=4'b0001,data=4'b0010,stop=4'b0100,error=4'b1000;
sampling_clk)
begin
next<=idle;
//
led_1<=0;
//
led_2<=0;
sample_count<=0;
bit_count<=0;
rxout_reg<=0;
//
pulse_out_reg<=1'b0;
//
pulse_count<=0;
end
else
begin
present<=next;
data_reg<=rxout_reg;
//
begin
//
pulse_count==21'd153541)
if(pulse_out_reg==1
//
&&
begin
//
pulse_out_reg<=0;
//
pulse_count<=0;
//
end
//
else
//
begin
//
pulse_count<=pulse_count+1;
//
//
end
end
begin
case(present)
idle:
begin
if(~rx)
begin
next<=start;
end
end
start:
begin
//
//
led_2<=0;
begin
//
if(sample_count==6)
//
begin
//
led_1<=0;
//
end
//
end
if(sample_count==7)
begin
if(~rx)
begin
next<=data;
sample_count<=0;
bit_count<=0;
end
end
else
begin
end
end
data:
begin
begin
rxout_reg<={rx,data_reg[7:1]};
sample_count<=0;
if(bit_count==(data_bit-1))
begin
next<=stop;
bit_count<=0;
end
else
begin
bit_count<=bit_count+1;
end
end
else
begin
end
end
stop:
begin
if(sample_count==stop_bit_tick)
begin
if(rx)
//
begin
begin
next<=idle;
//
led_1<=1;
//
led_2<=0;
//
ssreg<=data_reg;
//
pulse_count<=0;
end
//
end
else
begin
//
led_1<=0;
//
led_2<=1;
next<=error;
//
pulse_count<=0;
end
end
else
begin
end
end
error:
begin
if(rx)
begin
next<=idle;
end
end
default:
begin
next<=idle;
end
endcase
end
end
end
//
assign pulse_out=pulse_out_reg;
//assignled1=led_1;
//assignled2=led_2;
assign seven_segment=ssreg;
assign tx=rx;
endmodule
Module 2.2:
module rcv(
input [7:0] din,
input rst,
input clk,
output [7:0] dout
);
reg
[1:0]
reg
[7:0]
din_reg[0:8];
reg
[7:0]
dout_reg;
reg
[7:0]
data_reg;
reg
[15:0] count=16'b0;
reg
[3:0]
count1=4'b0;
parameter
[1:0]
idle=2'b00,start=2'b01,data=2'b10,stop=2'b11;
parameter
[7:0]
F=8'h46,T=8'h54;
always@(posedge
clk)
begin
if(rst)
begin
dout_reg<=8'b11111111;
count<=0;
count1<=0;
data_reg<=0;
present<=0;
next<=0;
end
else
begin
present<=next;
begin
case(present)
idle:
begin
dout_reg<=8'b11111111;
data_reg<=0;
if(din==F)
begin
next<=start;
end
end
start:
begin
count<=0;
data_reg<=din;
dout_reg<=8'b11111111;
next<=data;
end
data:
begin
if(count==52484)
begin
count<=0;
if(din==F)
begin
next<=start;
end
else
if(din==8'h20)
begin
next<=data;
dout_reg<=8'b11111111;
end
else
begin
count<=0;
data_reg<=din;
din_reg[8]<=data_reg;
din_reg[7]<=din_reg[8];
dout_reg<=din;
if(count1==8)
begin
count1<=0;
next<=stop;
end
else
begin
count1<=count1+1;
end
end
end
else
begin
count<=count+1;
end
end
stop:
begin
if(din==T)
begin
data_reg<=din;
dout_reg<=8'b11111111;
next<=idle;
end
/*
else
begin
data_reg<=data_reg;
end
*/
end
default:
begin
next<=idle;
end
endcase
end
end
end
assign dout=dout_reg;
endmodule
RS 485 module:
module rs_485(
input clk,
input rst,
//
input [7:0]
reading,
input Rx,
output out,
output DE,
output Tx
);
wire
[63:0] connect0;
wire
connect1,connect3;
wire
[31:0] connect2;
check uut0
.clk(clk),
//
.in(reading),
.out(connect0)
);
rs_485_receiver uut1 (
.clk(clk),
.rst(rst),
.serial_in(Rx),
.ack_signal(connect1),
.signal(connect3),
.command_type_out(connect2)
);
rs_485_tx2 uut2 (
.clk(clk),
.rst(rst),
.reading(connect0),
.signal(connect3),
.ack_signal(connect1),
.command_type_out(connect2),
.out(Tx),
.de(DE)
);
watchdog_timer
.clk(clk),
.rst(rst),
.out(out)
);
endmodule
uut3(
Internal modules of RS 485:

Module - 1
module check(
input clk,
output reg [63:0] out
);
reg
[4:0]
count1=5'b0;
reg [15:0] count=16'b0;

reg
[7:0]
temp1=8'b0,temp2=8'b0,temp3=8'b0,temp4=8'b0,temp5=8'b0,temp6=8'b0,temp7=8'b0,te
mp8=8'b0;
reg
[7:0]
temp1a=8'h30,temp2a=8'h2E,temp3a=8'h31,temp4a=8'h32,temp5a=8'h33,temp6a=8'h34,te
mp7a=8'h35,temp8a=8'h36;
always@(posedge
clk)
begin
if(count==26080)
begin
count<=0;
begin
case(count1)
5'd2:
begin
temp1<=temp1a;
end
5'd4:
begin
temp2<=temp2a;
end
5'd6:
begin
temp3<=temp3a;
end
5'd8:
begin
temp4<=temp4a;
end
5'd10:
begin
temp5<=temp5a;
end
5'd12:
begin
temp6<=temp6a;
end
5'd14:
begin
temp7<=temp7a;
end
5'd16:
begin
temp8<=temp8a;
end
endcase
end
begin
case(count1)
5'd16:
begin
count1<=0;
out<={temp1,temp2,temp3,temp4,temp5,temp6,temp7,temp8};
end
default:
begin
count1<=count1+1;
end
endcase
end
end
else
begin
count<=count+1;
end
end
endmodule
Module 2:
module rs_485_receiver(
input clk,
input rst,
input serial_in,
output [31:0] command_type_out,
output ack_signal,
output signal
);
wire
[7:0]
connect1,connect4;
wire
[3:0]
connect2;
wire
connect3;
RX uut1 (
.clk(clk),
.rst(rst),
.pulse_out(connect3),
.rx(serial_in),
.seven_segment(connect1));
rs_485_rx1
uut2
.pulse_out(connect3),
.rx_in(connect1),
.rx_out(connect4),
.command_type_out(command_type_out));
Ascii2Nibble
uut3
.ascii(connect4),
.nibble(connect2));
receiver_2 uut4 (
.clk(clk),
.rst(rst),
.rx_in(connect2),
.ack_signal(ack_signal),
.signal(signal));
endmodule
Module 2.1:
module RX(
input clk,
input rst,
input rx,
//output led1,
// output led2,
output [7:0] seven_segment,
output pulse_out
);
wire
sampling_signal;
baud_generator
b_g(.clk(clk),.sampling_clk(sampling_signal)/*,.baud_clk(baud_clk)*/);
receiver_module
r_m(.sampling_clk(sampling_signal),.rst(rst),.rx(rx)/*,.led1(led1),.led2(led2)*/,.seven_segme
nt(seven_segment),.pulse_out(pulse_out));
endmodule
Module 2.1.1:
module baud_generator(
input clk,
// output
output
reg baud_clk,
reg sampling_clk
);
//
reg
[11:0] count=12'b0;
reg
[7:0]
sample_count=8'b0;
initial
begin
sampling_clk<=0;
end
always@(posedge
clk)
begin
//
count<=count+1;
//
//
if(count==2603)
begin
//
count<=0;
//
baud_clk<=baud_clk+1;
//
end
begin
sample_count<=0;
sampling_clk<=sampling_clk+1;
end
end
endmodule
Module 2.1.2:
module receiver_module(
input sampling_clk,
input rst,
input rx,
//output led1,
// output led2,
output [7:0] seven_segment,
output pulse_out
);
//
//
reg
[20:0] pulse_count=21'bz;
reg
[3:0]
sample_count=4'b0;
reg
[2:0]
bit_count=3'b0;
reg
[7:0]
rxout_reg=8'b0;
reg
[7:0]
data_reg=8'b0;
reg
[7:0]
ssreg=8'hz;
reg
[2:0]
reg
led_1,led_2;
reg
pulse_out_reg;
parameter
[2:0]
parameter
data_bit=8,stop_bit_tick=15;
always@(posedge
idle=3'b000,start=3'b001,data=3'b010,stop=3'b100,error=3'b101;
sampling_clk)
begin
if(rst)
begin
next<=idle;
//
led_1<=0;
//
led_2<=0;
sample_count<=0;
bit_count<=0;
rxout_reg<=0;
//
pulse_count<=0;
end
else
begin
present<=next;
//
begin
//
pulse_count==21'd153541)
if(pulse_out_reg==1
//
&&
begin
//
pulse_out_reg<=0;
//
pulse_count<=0;
//
end
//
else
//
begin
//
pulse_count<=pulse_count+1;
//
//
end
end
begin
case(present)
idle:
begin
pulse_out_reg<=0;
if(~rx)
begin
next<=start;
end
end
start:
begin
//
//
led_2<=0;
begin
//
if(sample_count==6)
//
begin
//
led_1<=0;
//
end
//
end
if(sample_count==7)
begin
if(~rx)
begin
next<=data;
sample_count<=0;
bit_count<=0;
end
end
else
begin
end
end
data:
begin
begin
rxout_reg<={rx,data_reg[7:1]};
sample_count<=0;
if(bit_count==(data_bit-1))
begin
next<=stop;
bit_count<=0;
end
else
begin
bit_count<=bit_count+1;
end
end
else
begin
end
end
stop:
begin
if(sample_count==stop_bit_tick)
begin
if(rx)
//
begin
begin
next<=idle;
//
led_1<=1;
//
led_2<=0;
ssreg<=data_reg;
//
pulse_count<=0;
end
//
end
else
begin
//
led_1<=0;
//
led_2<=1;
next<=error;
//
pulse_count<=0;
end
end
else
begin
end
end
error:
begin
if(rx)
begin
next<=idle;
end
end
default:
begin
next<=idle;
end
endcase
end
end
end
assign pulse_out=pulse_out_reg;
//assignled1=led_1;
//assignled2=led_2;
assign seven_segment=ssreg;
endmodule
Module 2.2:
module rs_485_rx1(
input pulse_out,
input [7:0] rx_in,
output [7:0]
rx_out,
output [31:0] command_type_out

);
reg
[7:0]
temp[0:55];
reg
[5:0]
addr=6'b0;
parameter
a=1'b0,b=1'b1;
always@(posedge
pulse_out)
begin
addr<=addr+1;
if(addr==0)
begin
temp[13]<=0;
temp[14]<=0;
temp[15]<=0;
temp[16]<=0;
end
else
if(addr==13)
begin
temp[addr]<=rx_in;
end
else
if(addr==14)
begin
temp[addr]<=rx_in;
end
else
if(addr==15)
begin
temp[addr]<=rx_in;
end
else
if(addr==16)
begin
temp[addr]<=rx_in;
end
else
if(addr==60)
begin
addr<=0;
end
end
assign command_type_out={temp[13],temp[14],temp[15],temp[16]};
assign rx_out=rx_in;
endmodule
Module 2.3:
module Ascii2Nibble(nibble, ascii);
parameter LO = 1'b0, HI = 1'b1;
output [3:0] nibble;

input [7:0] ascii;
wire IsDecimal;
assign IsDecimal = ((ascii[7:4] == 4'b0011)? HI : LO);
assign nibble = ascii[3:0] + ((IsDecimal == HI)? 4'd0:4'd9);
endmodule
Module 2.4:
module receiver_2(
input clk,
input rst,
input [3:0] rx_in,
output signal,
output ack_signal
);
reg
[15:0]
da_reg=16'b0,sa_reg=16'b0,rb_reg=16'b0,number_reg=16'b0,command_type_reg=16'b0,no
_of_cycles_reg=16'b0,imax_reg=16'b0,imin_reg=16'b0,rise_slope_reg=16'b0,fall_slope_reg=16'b0,to
p_flat_time_reg=16'b0,bottom_flat_time_reg=16'b0,final_current_value_reg=16'b0,checksum_reg=
16'b0;
reg
[7:0]
rn_reg=8'b0;
reg
[3:0]
sd_reg=4'b0,ed_reg=4'b0,da_reg1=4'b0,da_reg2=4'b0,da_reg3=4'b0,da_reg4=4'b0,sa_reg1=
4'b0,sa_reg2=4'b0,sa_reg3=4'b0,sa_reg4=4'b0,rb_reg1=4'b0,rb_reg2=4'b0,rb_reg3=4'b0,rb_reg4=4'
b0,command_type_reg1=4'b0,command_type_reg2=4'b0,command_type_reg3=4'b0,command_typ
e_reg4=4'b0,command_type_reg5=4'b0,command_type_reg6=4'b0,command_type_reg7=4'b0,com
mand_type_reg8=4'b0,number_reg1=4'b0,number_reg2=4'b0,number_reg3=4'b0,number_reg4=4'b
0,no_of_cycles_reg1=4'b0,no_of_cycles_reg2=4'b0,no_of_cycles_reg3=4'b0,no_of_cycles_reg4=4'b0
,imax_reg1=4'b0,imax_reg2=4'b0,imax_reg3=4'b0,imax_reg4=4'b0,imin_reg1=4'b0,imin_reg2=4'b0,i
min_reg3=4'b0,imin_reg4=4'b0,rise_slope_reg1=4'b0,rise_slope_reg2=4'b0,rise_slope_reg3=4'b0,ris
e_slope_reg4=4'b0,fall_slope_reg1=4'b0,fall_slope_reg2=4'b0,fall_slope_reg3=4'b0,fall_slope_reg4=
4'b0,top_flat_time_reg1=4'b0,top_flat_time_reg2=4'b0,top_flat_time_reg3=4'b0,top_flat_time_reg
4=4'b0,bottom_flat_time_reg1=4'b0,bottom_flat_time_reg2=4'b0,bottom_flat_time_reg3=4'b0,bott
om_flat_time_reg4=4'b0,final_current_value_reg1=4'b0,final_current_value_reg2=4'b0,final_curren
t_value_reg3=4'b0,final_current_value_reg4=4'b0,checksum_reg1=4'b0,checksum_reg2=4'b0,check
sum_reg3=4'b0,checksum_reg4=4'b0,rn_reg1=4'b0,rn_reg2=4'b0;
reg
[4:0]
reg
[15:0] count=16'b0;
reg
[1:0]
reg
[15:0] sum=16'b0;
count1=2'b0;
reg
[3:0]
temp=4'b0;
reg
signal_reg=1'b0,ack_signal_reg=1'b0;
parameter
[4:0]
sd=5'b00000,da=5'b00001,sa=5'b00010,rb=5'b00011,command_type=5'b00100,number=5'b
00101,no_of_cycles=5'b00110,imax=5'b00111,imin=5'b01000,rise_slope=5'b01001,fall_slope=5'b01
010,top_flat_time=5'b01011,bottom_flat_time=5'b01100,final_current_value=5'b01101,checksum=
5'b01110,ed=5'b01111,rn=5'b10000,state=5'b10001,finish=5'b10010;
always@(posedge
clk
or
posedge
rst)
begin
if(rst)
begin
temp<=0;
count<=0;
count1<=0;
end
else
begin
present<=next;
temp<=rx_in;
case(present)
sd:
begin
signal_reg<=1'b0;
ack_signal_reg<=1'b0;
da_reg<=0;
da_reg1<=0;
da_reg2<=0;
da_reg3<=0;
da_reg4<=0;
count<=0;
case(temp)
4'hd:
begin
next<=da;
sd_reg<=temp;
end
default:
begin
next<=sd;
sd_reg<=sd_reg;
end
endcase
end
da:
begin
da_reg<={da_reg1,da_reg2,da_reg3,da_reg4};
sa_reg<=0;
sa_reg1<=0;
sa_reg2<=0;
sa_reg3<=0;
sa_reg4<=0;
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
da_reg1<=temp;
end
else
if(count1==1)
begin
da_reg2<=temp;
end
else
if(count1==2)
begin
da_reg3<=temp;
end
else
if(count1==3)
begin
da_reg4<=temp;
end
end
begin
case(count1)
2'd3:
begin
next<=sa;
count1<=0;
end
default:
begin
count1<=count1+1;
next<=da;
end
endcase
end
end
else
begin
count<=count+1;
end
end
sa:
begin
sa_reg<={sa_reg1,sa_reg2,sa_reg3,sa_reg4};
rb_reg<=0;
rb_reg1<=0;
rb_reg2<=0;
rb_reg3<=0;
rb_reg4<=0;
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
sa_reg1<=temp;
end
else
if(count1==1)
begin
sa_reg2<=temp;
end
else
if(count1==2)
begin
sa_reg3<=temp;
end
else
if(count1==3)
begin
sa_reg4<=temp;
end
end
begin
case(count1)
2'd3:
begin
next<=rb;
count1<=0;
end
default:
begin
count1<=count1+1;
next<=sa;
end
endcase
end
end
else
begin
count<=count+1;
end
end
rb:
begin
rb_reg<={rb_reg1,rb_reg2,rb_reg3,rb_reg4};
command_type_reg<=0;
command_type_reg1<=0;
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
rb_reg1<=temp;
end
else
if(count1==1)
begin
rb_reg2<=temp;
end
else
if(count1==2)
begin
rb_reg3<=temp;
end
else
if(count1==3)
begin
rb_reg4<=temp;
end
end
begin
case(count1)
2'd3:
begin
next<=command_type;
count1<=0;
end
default:
begin
count1<=count1+1;
next<=rb;
end
endcase
end
end
else
begin
count<=count+1;
end
end
command_type:
begin
command_type_reg<={command_type_reg1,command_type_reg2,command_type_reg3,co
mmand_type_reg4};
number_reg<=0;
number_reg1<=0;
number_reg2<=0;
number_reg3<=0;
number_reg4<=0;
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
command_type_reg1<=temp;
end
else
if(count1==1)
begin
end
else
if(count1==2)
begin
end
else
if(count1==3)
begin
end
end
begin
case(count1)
2'd3:
begin
next<=number;
count1<=0;
end
default:
begin
count1<=count1+1;
next<=command_type;
end
endcase
end
end
else
begin
count<=count+1;
end
end
number:
begin
number_reg<={number_reg1,number_reg2,number_reg3,number_reg4};
no_of_cycles_reg<=0;
no_of_cycles_reg1<=0;
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
number_reg1<=temp;
end
else
if(count1==1)
begin
number_reg2<=temp;
end
else
if(count1==2)
begin
number_reg3<=temp;
end
else
if(count1==3)
begin
number_reg4<=temp;
end
end
begin
case(count1)
2'd3:
begin
next<=no_of_cycles;
count1<=0;
end
default:
begin
count1<=count1+1;
next<=number;
end
endcase
end
end
else
begin
count<=count+1;
end
end
no_of_cycles:
begin
no_of_cycles_reg<={no_of_cycles_reg1,no_of_cycles_reg2,no_of_cycles_reg3,no_of_cycles
_reg4};
imax_reg<=0;
imax_reg1<=0;
imax_reg2<=0;
imax_reg3<=0;
imax_reg4<=0;
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
no_of_cycles_reg1<=temp;
end
else
if(count1==1)
begin
end
else
if(count1==2)
begin
end
else
if(count1==3)
begin
end
end
begin
case(count1)
2'd3:
begin
next<=imax;
count1<=0;
end
default:
begin
count1<=count1+1;
next<=no_of_cycles;
end
endcase
end
end
else
begin
count<=count+1;
end
end
imax:
begin
imax_reg<={imax_reg1,imax_reg2,imax_reg3,imax_reg4};
imin_reg<=0;
imin_reg1<=0;
imin_reg2<=0;
imin_reg3<=0;
imin_reg4<=0;
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
imax_reg1<=temp;
end
else
if(count1==1)
begin
imax_reg2<=temp;
end
else
if(count1==2)
begin
imax_reg3<=temp;
end
else
if(count1==3)
begin
imax_reg4<=temp;
end
end
begin
case(count1)
2'd3:
begin
next<=imin;
count1<=0;
end
default:
begin
count1<=count1+1;
next<=imax;
end
endcase
end
end
else
begin
count<=count+1;
end
end
imin:
begin
imin_reg<={imin_reg1,imin_reg2,imin_reg3,imin_reg4};
rise_slope_reg<=0;
rise_slope_reg1<=0;
rise_slope_reg2<=0;
rise_slope_reg3<=0;
rise_slope_reg4<=0;
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
imin_reg1<=temp;
end
else
if(count1==1)
begin
imin_reg2<=temp;
end
else
if(count1==2)
begin
imin_reg3<=temp;
end
else
if(count1==3)
begin
imin_reg4<=temp;
end
end
begin
case(count1)
2'd3:
begin
next<=rise_slope;
count1<=0;
end
default:
begin
count1<=count1+1;
next<=imin;
end
endcase
end
end
else
begin
count<=count+1;
end
end
rise_slope:
begin
rise_slope_reg<={rise_slope_reg1,rise_slope_reg2,rise_slope_reg3,rise_slope_reg4};
fall_slope_reg<=0;
fall_slope_reg1<=0;
fall_slope_reg2<=0;
fall_slope_reg3<=0;
fall_slope_reg4<=0;
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
rise_slope_reg1<=temp;
end
else
if(count1==1)
begin
end
else
if(count1==2)
begin
end
else
if(count1==3)
begin
end
end
begin
case(count1)
2'd3:
begin
next<=fall_slope;
count1<=0;
end
default:
begin
count1<=count1+1;
next<=rise_slope;
end
endcase
end
end
else
begin
count<=count+1;
end
end
fall_slope:
begin
fall_slope_reg<={fall_slope_reg1,fall_slope_reg2,fall_slope_reg3,fall_slope_reg4};
top_flat_time_reg<=0;
top_flat_time_reg1<=0;
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
fall_slope_reg1<=temp;
end
else
if(count1==1)
begin
end
else
if(count1==2)
begin
end
else
if(count1==3)
begin
end
end
begin
case(count1)
2'd3:
begin
next<=top_flat_time;
count1<=0;
end
default:
begin
count1<=count1+1;
next<=fall_slope;
end
endcase
end
end
else
begin
count<=count+1;
end
end
top_flat_time:
begin
top_flat_time_reg<={top_flat_time_reg1,top_flat_time_reg2,top_flat_time_reg3,top_flat_ti
me_reg4};
bottom_flat_time_reg<=0;
bottom_flat_time_reg1<=0;
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
top_flat_time_reg1<=temp;
end
else
if(count1==1)
begin
end
else
if(count1==2)
begin
end
else
if(count1==3)
begin
end
end
begin
case(count1)
2'd3:
begin
next<=bottom_flat_time;
count1<=0;
end
default:
begin
count1<=count1+1;
next<=top_flat_time;
end
endcase
end
end
else
begin
count<=count+1;
end
end
bottom_flat_time:
begin
bottom_flat_time_reg<={bottom_flat_time_reg1,bottom_flat_time_reg2,bottom_flat_time
_reg3,bottom_flat_time_reg4};
final_current_value_reg<=0;
final_current_value_reg1<=0;
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
bottom_flat_time_reg1<=temp;
end
else
if(count1==1)
begin
end
else
if(count1==2)
begin
end
else
if(count1==3)
begin
end
end
begin
case(count1)
2'd3:
begin
next<=final_current_value;
count1<=0;
end
default:
begin
count1<=count1+1;
next<=bottom_flat_time;
end
endcase
end
end
else
begin
count<=count+1;
end
end
final_current_value:
begin
final_current_value_reg<={final_current_value_reg1,final_current_value_reg2,final_current
_value_reg3,final_current_value_reg4};
checksum_reg<=0;
checksum_reg1<=0;
checksum_reg2<=0;
checksum_reg3<=0;
checksum_reg4<=0;
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
final_current_value_reg1<=temp;
end
else
if(count1==1)
begin
end
else
if(count1==2)
begin
end
else
if(count1==3)
begin
end
end
begin
case(count1)
2'd3:
begin
next<=checksum;
count1<=0;
end
default:
begin
count1<=count1+1;
next<=final_current_value;
end
endcase
end
end
else
begin
count<=count+1;
end
end
checksum:
begin
checksum_reg<={checksum_reg1,checksum_reg2,checksum_reg3,checksum_reg4};
sum<=da_reg+sa_reg+rb_reg+command_type_reg+number_reg+no_of_cycles_reg+imax_re
g+imin_reg+rise_slope_reg+fall_slope_reg+top_flat_time_reg+bottom_flat_time_reg+final_current_
value_reg;
ed_reg<=0;
begin
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
checksum_reg1<=temp;
end
else
if(count1==1)
begin
end
else
if(count1==2)
begin
end
else
if(count1==3)
begin
end
end
begin
case(count1)
2'd3:
begin
next<=ed;
count1<=0;
end
default:
begin
count1<=count1+1;
next<=checksum;
end
endcase
end
end
else
begin
count<=count+1;
end
end
end
ed:
begin
rn_reg<=0;
rn_reg1<=0;
rn_reg2<=0;
if(temp==4'h3)
begin
ed_reg<=temp;
next<=rn;
end
else
begin
next<=ed;
end
end
rn:
begin
sd_reg<=0;
rn_reg<={rn_reg1,rn_reg2};
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
rn_reg1<=temp;
end
else
if(count1==1)
begin
rn_reg2<=temp;
end
end
begin
case(count1)
2'd1:
begin
next<=state;
count1<=0;
end
default:
begin
count1<=count1+1;
next<=rn;
end
endcase
end
end
else
begin
count<=count+1;
end
end
state:
begin
signal_reg<=1'b0;
if(count==52160)
begin
rn_reg2<=temp;
next<=finish;
count<=0;
count1<=0;
end
else
begin
count<=count+1;
end
end
finish:
begin
if(sum==checksum_reg)
begin
signal_reg<=1'b1;
next<=sd;
end
else
begin
signal_reg<=1'b1;
next<=sd;
end
end
default:
begin
next<=sd;
ack_signal_reg<=0;
temp<=0;
end
endcase
end
end
assign signal=signal_reg;
assign ack_signal=ack_signal_reg;
endmodule
Module 3:
module rs_485_tx2(
input clk,
input rst,
input
signal,
input ack_signal,
input
[31:0] command_type_out,
input
[63:0] reading,
output de,
output out
);
wire
[7:0]
connect1;
wire
connect2;
rs_485_tx1 uut1 (
.clk(clk),
.rst(rst),
.signal(signal),
.ack_signal(ack_signal),
.command_type_out(command_type_out),
.reading(reading),
.de(de),
.frame(connect1),
.no_frame(connect2)
);
piso
uut2 (
.clk(clk),
.in(connect1),
.out(out),
.no_frame(connect2)
);
endmodule
Module 3.1:
module rs_485_tx1(
input clk,
input rst,
input signal,
input ack_signal,
input [31:0] command_type_out,
input [63:0] reading,
output [7:0] frame,
output no_frame,
output de
);
//frame
reg [7:0]
sd_reg=8'h24,ed_reg=8'h2A,frame_reg=8'b0,da_reg1=8'h30,da_reg2=8'h30,da_reg3=8'h30,da_reg4
=8'h30,sa_reg1=8'h30,sa_reg2=8'h30,sa_reg3=8'h30,sa_reg4=8'h31,frame_type_reg1=8'h41,frame_
type_reg2=8'h43,frame_type_reg3=8'h4B,frame_type_reg4=8'h57,last_frame_received_reg1=8'b0,l
ast_frame_received_reg2=8'b0,last_frame_received_reg3=8'b0,last_frame_received_reg4=8'b0,ack
_reg1=8'h46,ack_reg2_1=8'h59,ack_reg2_2=8'h4E,ack_reg3=8'h4F,ack_reg4=8'h4B,rn_reg1=8'h0D,r
n_reg2=8'h0A;
reg [15:0] count=16'b0;
reg [2:0] count1=3'b0;
reg
[4:0]
reg
de1_reg=1'b0,no_frame_reg=1'b0,ack_signal_next=1'b0;
reg
[31:0] command_type_reg=32'b0;
parameter
[4:0]
sd=5'd0,da=5'd1,sa=5'd2,frame_type=5'd3,last_frame_received=5'd4,ack=5'd5,ed=5'd6,rn=5
'd7,state=5'd8,finish=5'd9;
//
response_frame
reg
[7:0]
sd_reg_r=8'h24,da_reg_r1=8'h30,da_reg_r2=8'h30,da_reg_r3=8'h30,da_reg_r4=8'h30,sa_re
g_r1=8'h30,sa_reg_r2=8'h30,sa_reg_r3=8'h30,sa_reg_r4=8'h31,readback_reg_r1=8'h44,readback_re
g_r2=8'h52,readback_reg_r3=8'h54,readback_reg_r4=8'h4D,setting_value_reg_r1=8'b0,setting_valu
e_reg_r2=8'b0,setting_value_reg_r3=8'b0,setting_value_reg_r4=8'b0,setting_value_reg_r5=8'b0,set
ting_value_reg_r6=8'b0,setting_value_reg_r7=8'b0,setting_value_reg_r8=8'b0,interlocks_reg_r1=8'
h30,interlocks_reg_r2=8'h30,data_reg_r1=8'h30,data_reg_r2=8'h30,ed_reg_r=8'h2A,rn_reg_r1=8'h0
D,rn_reg_r2=8'h0A;
reg
[63:0] reading_reg=64'b0;
parameter
[4:0]
sd_r=5'd10,da_r=5'd11,sa_r=5'd12,readback_r=5'd13,setting_value_r=5'd14,interlocks_and
_data_r=5'd15,ed_r=5'd16,rn_r=5'd17,state_r=5'd18,finish_r=5'd19;
always@(posedge
clk
or
posedge
rst)
begin
if(rst)
begin
frame_reg<=8'b0;
no_frame_reg<=1'b1;
de1_reg<=1'b0;
end
else
begin
present<=next;
case(present)
sd:
begin
case(signal)
1'b1:
begin
frame_reg<=sd_reg;
de1_reg<=1'b1;
next<=da;
no_frame_reg<=1'b0;
count1<=0;
end
default:
begin
frame_reg<=8'bz;
next<=sd;
de1_reg<=0;
no_frame_reg<=1'b1;
end
endcase
end
da:
begin
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
frame_reg<=da_reg1;
end
else
if(count1==1)
begin
frame_reg<=da_reg2;
end
else
if(count1==2)
begin
frame_reg<=da_reg3;
end
else
if(count1==3)
begin
frame_reg<=da_reg4;
end
end
begin
case(count1)
3'd3:
begin
next<=sa;
count1<=0;
end
default:
begin
next<=da;
count1<=count1+1;
end
endcase
end
end
else
begin
count<=count+1;
end
end
sa:
begin
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
frame_reg<=sa_reg1;
end
else
if(count1==1)
begin
frame_reg<=sa_reg2;
end
else
if(count1==2)
begin
frame_reg<=sa_reg3;
end
else
if(count1==3)
begin
frame_reg<=sa_reg4;
end
end
begin
case(count1)
3'd3:
begin
next<=frame_type;
count1<=0;
end
default:
begin
next<=sa;
count1<=count1+1;
end
endcase
end
end
else
begin
count<=count+1;
end
end
frame_type:
begin
command_type_reg<=0;
last_frame_received_reg4<=0;
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
frame_reg<=frame_type_reg1;
end
else
if(count1==1)
begin
end
else
if(count1==2)
begin
end
else
if(count1==3)
begin
end
end
begin
case(count1)
3'd3:
begin
next<=last_frame_received;
count1<=0;
end
default:
begin
next<=frame_type;
count1<=count1+1;
end
endcase
end
end
else
begin
count<=count+1;
end
end
last_frame_received:
begin
command_type_reg<=command_type_out;
last_frame_received_reg4<={command_type_reg[7:0]};
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
frame_reg<=last_frame_received_reg1;
end
else
if(count1==1)
begin
end
else
if(count1==2)
begin
end
else
if(count1==3)
begin
end
end
begin
case(count1)
3'd3:
begin
next<=ack;
count1<=0;
end
default:
begin
next<=last_frame_received;
count1<=count1+1;
end
endcase
end
end
else
begin
count<=count+1;
end
end
ack:
begin
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
frame_reg<=ack_reg1;
end
else
if(count1==1)
begin
if(ack_signal_next==1'b1)
begin
frame_reg<=ack_reg2_1;
end
else
begin
frame_reg<=ack_reg2_2;
end
end
else
if(count1==2)
begin
end
else
if(count1==3)
begin
end
end
begin
case(count1)
3'd3:
begin
next<=ed;
count1<=0;
end
default:
begin
next<=ack;
count1<=count1+1;
end
endcase
end
end
else
begin
count<=count+1;
end
end
ed:
begin
if(count==52160)
begin
frame_reg<=ed_reg;
count<=0;
next<=rn;
end
else
begin
count<=count+1;
end
end
rn:
begin
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
frame_reg<=rn_reg1;
end
else
if(count1==1)
begin
frame_reg<=rn_reg2;
end
end
begin
case(count1)
3'd1:
begin
count1<=0;
next<=state;
end
default
begin
count1<=count1+1;
next<=rn;
end
endcase
end
end
else
begin
count<=count+1;
end
end
state:
begin
no_frame_reg<=1'b0;
if(count==52160)
begin
frame_reg<=rn_reg2;
next<=finish;
count<=0;
end
else
begin
count<=count+1;
end
end
finish:
begin
if(ack_signal_next==1'b1)
begin
next<=sd_r;
end
else
if(ack_signal==1'b0)
begin
next<=sd;
de1_reg<=1'b0;
no_frame_reg<=1'b1;
end
end
//response_frame
sd_r:
begin
frame_reg<=sd_reg_r;
next<=da_r;
count1<=0;
end
da_r:
begin
if(count==52160)
begin
count<=0;
begin
if(count1==0)
begin
frame_reg<=da_reg_r1;
end
else
if(count1==1)
begin
end
else
if(count1==2)
begin
end
else
if(count1==3)
begin
end
end
begin
case(count1)
3'd3:
begin
next<=sa_r;
count1<=0;
end
default:
begin
next<=da_r;
count1<=count1+1;
end
endcase
end
end
else
begin
count<=count+1;
end
end
sa_r:
begin
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
frame_reg<=sa_reg_r1;
end
else
if(count1==1)
begin
end
else
if(count1==2)
begin
end
else
if(count1==3)
begin
end
end
begin
case(count1)
3'd3:
begin
next<=readback_r;
count1<=0;
end
default:
begin
next<=sa_r;
count1<=count1+1;
end
endcase
end
end
else
begin
count<=count+1;
end
end
readback_r:
begin
reading_reg<=0;
setting_value_reg_r8<=0;
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
frame_reg<=readback_reg_r1;
end
else
if(count1==1)
begin
end
else
if(count1==2)
begin
end
else
if(count1==3)
begin
end
end
begin
case(count1)
3'd3:
begin
next<=setting_value_r;
count1<=0;
end
default:
begin
next<=readback_r;
count1<=count1+1;
end
endcase
end
end
else
begin
count<=count+1;
end
end
setting_value_r:
begin
reading_reg<=reading;
setting_value_reg_r8<={reading[7:0]};
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
frame_reg<=setting_value_reg_r1;
end
else
if(count1==1)
begin
end
else
if(count1==2)
begin
end
else
if(count1==3)
begin
end
else
if(count1==4)
begin
end
else
if(count1==5)
begin
end
else
if(count1==6)
begin
end
else
if(count1==7)
begin
end
end
begin
case(count1)
3'd7:
begin
next<=interlocks_and_data_r;
count1<=0;
end
default:
begin
next<=setting_value_r;
count1<=count1+1;
end
endcase
end
end
else
begin
count<=count+1;
end
end
interlocks_and_data_r:
begin
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
frame_reg<=interlocks_reg_r1;
end
else
if(count1==1)
begin
frame_reg<=interlocks_reg_r2;
end
else
if(count1==2)
begin
frame_reg<=data_reg_r1;
end
else
if(count1==3)
begin
frame_reg<=data_reg_r2;
end
end
begin
case(count1)
3'd3:
begin
next<=ed_r;
count1<=0;
end
default:
begin
count1<=count1+1;
next<=interlocks_and_data_r;
end
endcase
end
end
else
begin
count<=count+1;
end
end
ed_r:
begin
if(count==52160)
begin
frame_reg<=ed_reg_r;
next<=rn_r;
count<=0;
end
else
begin
count<=count+1;
end
end
rn_r:
begin
if(count==52160)
begin
begin
count<=0;
if(count1==0)
begin
frame_reg<=rn_reg_r1;
end
else
if(count1==1)
begin
end
end
begin
case(count1)
3'd1:
begin
next<=state_r;
count1<=0;
end
default:
begin
count1<=count1+1;
end
endcase
end
end
else
begin
count<=count+1;
end
end
state_r:
begin
no_frame_reg<=1'b0;
if(count==52160)
begin
next<=finish_r;
count<=0;
end
else
begin
count<=count+1;
end
end
finish_r:
begin
frame_reg<=8'bz;
no_frame_reg<=1'b1;
next<=sd;
de1_reg<=1'b0;
end
default:
begin
next<=finish;
end
endcase
end
end
assign frame=frame_reg;
assign de=de1_reg;
assign no_frame=no_frame_reg;
always@(posedge
clk)
begin
if(ack_signal)
begin
ack_signal_next<=1'b1;
end
end
endmodule
Module 3.2:
module piso(
input clk,
input
no_frame,
input [7:0] in,

output out
);
reg [7:0] temp1=8'b0;

reg [9:0] temp2=10'b0;
reg [3:0] value=4'd9;
reg [12:0] count=13'b0;
reg out_reg=1'bz;
always@(posedge clk)
begin
temp1<=0;
if(no_frame)
begin
out_reg<=1'bz;
//
count<=0;
end
else
begin
temp1<=in;
temp2[9]<=0;
temp2[8]<=temp1[0];
temp2[7]<=temp1[1];
temp2[6]<=temp1[2];
temp2[5]<=temp1[3];
temp2[4]<=temp1[4];
temp2[3]<=temp1[5];
temp2[2]<=temp1[6];
temp2[1]<=temp1[7];
temp2[0]<=1;
out_reg<=temp2[value];
end
//
end
end
always@(posedge
clk)
begin
if(no_frame==1'b0)
begin
if(count==5216)
begin
count<=0;
value<=value-1;
if(value==0)
begin
value<=4'd9;
end
end
else
begin
count<=count+1;
end
end
end
assign out=out_reg;
endmodule
Module 4:
module watchdog_timer(
input
clk,
input
rst,
output out
);
reg
[15:0] count=16'b0;
reg
out_reg=1'b0;
initial begin
count<=0;
out_reg<=0;
end
always@(posedge
clk)
begin
if(rst)
begin
count<=0;
out_reg<=0;
end
else
begin
count<=count+1;
if(count==50000)
begin
count<=0;
out_reg<=out_reg+1;
end
end
end
assign out=out_reg;
endmodule

Verilog Codes of Project

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Verilog Codes of Project

Uploaded by

Copyright:

Available Formats

Rs 232 module:

transmitter_frame uut1 (.clk(clk), .rst(rst),.tx_out(serial_out));

Internal modules of RS232:

transmitter_1 uut1 (.clk(clk),.rst(rst),.tx(connection));

reg [7:0] temp1=8'b0;

Internal modules of RS 485:

reg [15:0] count=16'b0;

output [31:0] command_type_out

parameter LO = 1'b0, HI = 1'b1;

output [3:0] nibble;

assign IsDecimal = ((ascii[7:4] == 4'b0011)? HI : LO);

assign nibble = ascii[3:0] + ((IsDecimal == HI)? 4'd0:4'd9);

input [7:0] in,

reg [7:0] temp1=8'b0;

You might also like