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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity T_FF_VHDL is
port( T: in
std_logic;
Reset: in std_logic;
Clock_enable: in std_logic;
Clock: in std_logic;
Output: out std_logic);
end T_FF_VHDL;
architecture Behavioral of T_FF_VHDL is
signal temp: std_logic;
begin
process (Clock)
begin
if Clock'event and Clock='1' then
if Reset='1' then
temp <= '0';
elsif Clock_enable ='1' then
if T='0' then
temp <= temp;
elsif T='1' then
temp <= not (temp);
end if;
end if;
end if;
end process;
Output <= temp;
end Behavioral;
when "001"
when "010"
when "011"
when "100"
when "101"
when "110"
Priority Encoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Priority_Encoder_VHDL is
port ( Sel : in std_logic_vector(3 downto 0);
encoded_data : out std_logic_vector(1 downto 0);
D : out std_logic);
end entity Priority_Encoder_VHDL;
architecture Behavioral of Priority_Encoder_VHDL is
begin
encoded_data <= "11" when Sel(3)='1' else
"10" when Sel(2)='1' else
"01" when Sel(1)='1' else
"00";
D <= '0' when Sel="0000" else '1';
end architecture Behavioral;
: in std_logic;
d : in std_logic;
q : out std_logic
);
end entity D_FF_VHDL;
architecture Behavioral of D_FF_VHDL is
begin
process (clk) is
begin
if rising_edge(clk) then
if (rst='1') then
q <= '0';
elsif (pre='1') then
q <= '1';
elsif (ce='1') then
q <= d;
end if;
end if;
end process;
end architecture Behavioral;
std_logic;
Reset: in std_logic;
Clock_enable: in std_logic;
Clock: in std_logic;
Output: out std_logic);
end T_FF_VHDL;
architecture Behavioral of T_FF_VHDL is
signal temp: std_logic;
begin
process (Clock)
begin
if Clock'event and Clock='1' then
if Reset='1' then
temp <= '0';
elsif Clock_enable ='1' then
if T='0' then
temp <= temp;
elsif T='1' then
temp <= not (temp);
end if;
end if;
end if;
end process;
Output <= temp;
end Behavioral;
std_logic;
Reset: in std_logic;
Clock_enable: in std_logic;
Clock: in std_logic;
Output: out std_logic);
end JK_FF_VHDL;
architecture Behavioral of JK_FF_VHDL is
signal temp: std_logic;
begin
process (Clock)
begin
if (Clock'event and Clock='1') then
if Reset='1' then
temp <= '0';
elsif Clock_enable ='1' then
if (J='0' and K='0') then
temp <= temp;
elsif (J='0' and K='1') then
temp <= '0';
elsif (J='1' and K='0') then
temp <= '1';
elsif (J='1' and K='1') then
temp <= not (temp);
end if;
end if;
end if;
end process;
Output <= temp;
end Behavioral;
process(Clock,Reset)
begin
if Reset='1' then
temp <= "0000";
elsif(Clock'event and Clock='1') then
if Clock_enable='0' then
if temp="1001" then
temp<="0000";
else
temp <= temp + 1;
end if;
else
temp <= temp;
end if;
end if;
end process;
Output <= temp;
end Behavioral;