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LM324 DIP
LMC6294
MAX4240
APEX PA03
LINEAR MODEL
OUTPUT RESISTANCE
INPUT RESISTANCE
TYPICAL VALUES
Ri : 10 10
5
RO : 1 50
A : 105 107
12
VIN
IN
VO
IN
GAIN
DRIVING CIRCUIT
LINEAR
REGION
SATURATION
REGION
OP-AMP IN SATURATION
KVL : Vs Ri I RO I AOVin 0
KVL : - Vout RO I AOVin 0
CONTROLLIN G VARIABLE : Vin Ri I
SOLVING
1
BUFFER Vout
GAIN
Ri
Vs 1
RO AO Ri
V
AO out 1
VS
IDEAL RO 0, Ri , A
i
i
RO 0 vO A(v v )
Ri
A
vOUT vS
v v s
v v
vOUT
vOUT v
vOUT
1
vS
Vout
Vs
1
Ri
1
RO AO Ri
vO v S
v v s
v v
vO v
vO v S
THE SOURCE SUPPLIES NO POWER
THE SOURCE SUPPLIES POWER
LEARNING EXAMPLE
0
R1
R2
G
Vout
R
2
Vs
R1
Ao v v v 0
Ri i i 0
Vout
Vs
v 0
i 0
v 0
1.
v
vo
v
vo
Ri
RO
A(v v )
4. Redraw as needed
v
R2
v
vo
v
v
NODE ANALYSIS
R1 1k, R2 5k
vO
v
4.9996994 A O 5.000
vS
vS
v 0
i 0
v 0
IDEAL OP-AMP ASSUMPTIONS
Ri i i 0
A v v
KCL @ INVERTING TERMINAL
NON-IDEAL CASE
REPLACE OP-AMP BY LINEAR MODEL
SOLVE THE RESULTING CIRCUIT WITH
DEPENDENT SOURCES
GAIN FOR NON-IDEAL CASE
0 v S 0 vO
v
R
0 O 2
R1
R2
vs
R1
THE IDEAL OP-AMP ASSUMPTION PROVIDES EXCELLENT APPROXIMATION.
(UNLESS FORCED OTHERWISE WE WILL ALWAYS USE IT!)
THINK NODES!
R4
R4
v2 v
v2
R3 R4
R3 R4
R
R
R
R
vO 1 2 v 2 v1 2 1 1 v v1
R1
R1
R1 R2
i 0 v
R4 R2 , R3 R1 vO
R2
(v2 v1 )
R1
v1
FIND vO
vo1
v1
vm1
v2
v 1 v m 1
v 2 v m 2
FINISH WITH INPUT NODE EQUATIONS
USE INFINTE GAIN ASSUMPTION
v1 v1
v 2
vo 2
vm 1 v1
v 2 v 2
vm 2 v2
v 2
@ vm1 :
vm 2
v 1 v 1
v 2 v 2
v1 v01 v1 v 2 v1 vo 2
00
R2
RG
R1
v 2 v o 2 v 2 v1 v 2
@ vm 2 :
00
R1
RG
R2
LEARNING EXTENSION
AO v 12V
v 12V
Ri i 0
12 Vo 12
0 Vo 84V
12k
2k
V
IO o 8.4mA
10k
KCL@ v :
LEARNING EXTENSION
v0
v
v_
vo
R2
v vi
i 0
R1
v v1
v v1 v v1
INFINITE GAIN ASSUMPTION
INFINITE INPUT RESISTANCE
R1
R1 R2
vi
v0 v0
vi
R1 R2
R1
vO
vi v v
COMPLETE EQUIVALENT
FOR MESH ANALYSIS
Ri
RO
vO
A(v v )
MESH 2
vO R2i2 R1 (i1 i2 )
THE SOLUTIONS
MATHEMATICAL MODEL
R1 v1
i1 1 ( R1 R2 RO )
i ( AR R ) ( R R ) 0
2
i
1
1
2
MESH 1
MESH 2
i1
R1 R2 RO
v1
i2
( ARi R1 )
vO R2i2 R1 (i1 i2 )
INPUT RESISTANCE
Rin
v1
i1
GAIN
vO
vi
R1
( R1 R2 )
i1 v1
AR R ( R R R ) i 0
i
1
1
2
O 2
THE FORMAL SOLUTION
1
R1
v1
i1 ( R1 R2 )
i AR R ( R R R ) 0
2 i
1
1
2
O
( R1 R2 RO )( R1 R2 ) R1 ( ARi R1 )
R1
( R R2 RO )
Adj 1
( ARi R1 ) ( R1 R2 )
vO R1i1 ( R1 R2 )i2
R1 ( R1 R2 RO )
( R R2 )( ARi R1 )
v1 1
v1
A ???
A AR1Ri
Rin
vO
R R2
1
v1
R1
Ri , RO 0, A AO i i 0 v v !!
v
Replacement Equation
ve vin
vO AO ve AO (v v )
v v S
vO
R2 R1
v (as before)
R1
vO
AO
R1
;
v S 1 AO
R! R2
1
1 AO
Sample Problem
Set voltages?
i 0
vO
iS
+
-
vS
v v S
v v S
vo v
iS
0
R
vo vS RiS
Sample Problem
DRAW THE LINEAR EQUIVALENT CIRCUIT AND WRITE THE LOOP EQUATIONS
4. Redraw if necessary
Ri
iS
RO
vO
A(v v )
i2
i1
iS
vo
RO
Ri
+
-
A(v + - v -)
1. Locate nodes
2. Erase Op-Amp
3. Place linear model
is
MESH 2
LEARNING EXTENSION
v _ VS
i 0
VS
INVERSE VOLTAGE DIVIDER
100k 1k
VO
VS
1k
V
G O 101
VS
VS 1mV VO 0.101V
VO
VS
R2
R1
LEARNING EXAMPLE
VO 8V1 4V2
If 1V V1 2V , 2V V2 3V
dc supplis are 10V
VX 2V1 V2
1V V1 2V , 2V V2 3V 1V VX 2V VX OK!
VO 4VX
1V VX 2V 4V VO 8V VO OK !
VY 8V1
1V V1 2V 16V VY 8V
EXCEEDS SUPPLY VALUE.
THIS OP-AMP SATURATES!
POOR IMPLEMENTATION
COMPARATOR CIRCUITS
ZERO-CROSSING DETECTOR
LEARNING BY APPLICATION
G 1
R2
R1
VI RI I
R
VO GVI 1 2 RI I
R1
LEARNING EXAMPLE
1
Constraints: VM
RB
4 (design eq.)
RA
20V
Power dissipation
in amplifier 100mW
Significant power losses
Simplifying assumptions: Ri , RO 0 Occur only in Ra, Rb
(20V )2
PMX
100mW RA RB 4000
RA RB
RB
3
RA
One solution: RB 3k , RA 1k
V1
DESIGN EXAMPLE: INSTRUMENTATION AMPLIFIER
V2
DESIGN SPECIFICATIONS
VO
VO
10
V1 V2
VO VX VY
ANALISIS OF PROPOSED CONFIGURATION
VA V1 ; VB V2
Infinite gain
V1 V2 V1 VX
0
R
R1
V V1 V2 VY
@B: 2
0
R
R2
@ A:
R
R
R
R
VO V1 1 1 V2 1 2 V1 2 V2 1
R
R
R
R
O
2
R 1
DESIGN EQUATION: 2 R1 9 R
USE LARGE RESISTORS FOR LOW POWER e. g., R 100k, R1 R2 450k
DESIGN EXAMPLE
DESIGN SPECIFICATION
VO
10
Vin
VO
R2
1
10
equationS:
Vin
R1
PR R
1
R2 9 R1
(20V )2
100mW R R 4k
R1 R2
R1 400
DESIGN EXAMPLE
DESIGN CONSTRAINTS
AS FEW COMPONENTS AS POSSIBLE
MINIMIZE POWER DISSIPATED
USE RESISTORS NO LARGER THAN 10K
Given the function (weighted sum
with sign change) a basic weighted
adder may work
V 0
R
R
VO V1 V2
V V
V
@V :
0
R1
R2
O
R1 1
R2
R2 9 R1
DESIGN
EQUATIONS
R
0.1
R2
R2 R1 R
DESIGN EXAMPLE
VI RI
CANNOT GIVE DESIRED RANGE!
2. CHOOSE RESISTOR TO PROVIDE THE 5V CHANGE
AND SHIFT LEVELS DOWN!
VMAX VMIN
50
312.5
I MAX I MIN 0.020 0.004
1.25 VI 6.25
R2
VI
R1 R2
R1
V
(VO VSHIFT ) VSHIFT
R1 R2
V V VO R2 VI VSHIFT
R1
LEARNING BY DESIGN
DETERMINE R2 , R1 SO THAT
IT PROVIDES AN AMPLIFICA TION OF 1000
VO
R
(1)(1 2 )
V1
R1
LEARNING EXAMPLE
RT 57.45e 0.0227 T
UNITY GAIN
BUFFER
v v1
i 0
v v1
OUTPUT CANNOT
EXCEED SUPPLY
(10V)
KCL @ v_
IN LINEAR RANGE
OFFSET