Aging-Aware Reliable Multiplier Design with Adaptive Hold Logic

AIM:
To design an aging aware reliable multiplier circuit based on variable-latency technique
using with Adaptive Hold Logic circuit to reduce the effect of NTBI.

EXISTING SYSTEM:

Guard-banding and gate oversizing

Joint logic restructuring and pin reordering method
NBTI optimization method

DISADVANTAGES:

High power consumption.

Requires circuit modification
No optimization on specific circuits.

PROPOSED SYSTEM:

An aging-aware reliable multiplier design with a novel adaptive hold logic

(AHL) circuit. The multiplier is based on the variable-latency technique and can
adjust the AHL circuit to achieve reliable operation under the influence of NBTI
and PBTI effects.

ADVANTAGES:

Reduced Area delay

Minimizing timing waste of critical paths
Low power consumption

Circuit Diagram:

Tools used:

Tanner EDA
Applications:
Used in
o Memory cells.
o SRAM
o Submicron Devices