FPGA IMPLEMENTATION OF DSSS-CDMA TRANSCEIVER FOR

PERFORMANCE ANALYSIS OF DEMODULATORS WITH DIFFERENT

PN SEQUENCE GENERATORS

ABSTRACT:
CDMA stands for Code Division Multiple Access. It is a wireless communication technology
that allows multiple people to use a single radio channel at the same time with little interference
and very high security. The CDMA exclusively uses Direct Sequence Spread Spectrum so that a
single channel is shared by multiple users and less background noise is experienced. DSSS uses
Pseudo Noise sequence to spread the data all over the frequency spectrum available for
communication. PN sequence or Pseudo Noise sequence is a periodic binary code which is
random in nature generated by the use of shift registers, but generated with taking into
considerations some generator polynomials. Practically, PN sequences can be generated by
digital pseudo random signal generators, and the properties of these signals highly affect the
reconstruction quality of the receiver.
Thus, a DSSS CDMA transceiver will be developed so that performance analysis of
demodulators with different PN sequence generators based on m-sequence, Kasami sequence,
Walsh matrix and Pseudo chaotic sequence can be done.

REFERENCES:
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5)

FPGA Implementation of DSSS-CDMA Transmitter and Receiver for ADHOC networks.

FPGA Implementation of CDMA Trans-Receiver
Digital Design of DS-CDMA transmitter using VHDL and FPGA
Performance Analysis of Random Demodulators with M-sequence and Kasami sequences
A soft Fast Estimation Method of PN Sequence based on Weighting Walsh Hadamard
Transform
6) Design and FPGA Realization of MC-CDMA system using Pseudo Chaotic sequence
generator