Realization of All Logic Gates With HDL Code

HDL LAB MANUAL
1. REALIZATION
CODE
OF
ALL
2012
LOGIC
GATES
WITH
HDL
1, AND GATE:USING VHDL:

library ieee;
use ieee . std_logic_1164.all;
entity and2 is
port (a,b:in std_logic
; c:out std_logic);
end and2;
architecture behave of and2 is
begin
c<=a and b;
end behave;
USING VERILOG:
module and2(a,b,c);
input a,b;
output c;
assign
c=a&b;
endmodule
2, OR GATE :USING VHDL:

library ieee;
entity or2 is
port (a,b:in std_logic ; c:out std_logic);
end or2;
architecture behave of or2 is
begin
c<=a or b;
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end behave;
USING VERILOG:
module or2(a,b,c);
input a,b;
output c;
assign
c=a!b;
endmodule
3, XOR GATE:USING VHDL:

library ieee;
use ieee.std_logic_1164.all;
entity xor2 is
port (a,b:in std_logic ;c:out std_logic);
end xor2;
architecture behave of xor2 is
begin
c<=a xor b;
end behave;
USING VERILOG:
module xor2(a,b,c);
input a,b;
output c;
assign
c=a^b;
endmodule
4, XNOR :USING VHDL:

library ieee;
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entity xnor2 is
end xnor2;
architecture behave of xnor2 is
begin
c<=a xnor b;
end behave;
USING VERILOG:
module xnor2(a,b,c);
input a,b;
output c;
assign
c=~(a^b);
endmodule
5, NOT:USING VHDL:
library ieee;
entity not2 is
port (a:in std_logic ; c:out std_logic);
end not2;
architecture behave of not2 is
begin
c<= not a;
end behave;
USING VERILOG:
module not2(a,c);
input a;
output c;
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assign
c=~a;
endmodule
6, NAND:USING VHDL:
library ieee;
entity nand2 is
port (a,b:in std_logic;c:out std_logic);
end nand2;
architecture behave of nand2 is
begin
c<=a nand b;
end behave;
USING VERILOG:
module nand2(a,b,c);
input a,b;
output c;
assign
c=~(a&b);
endmodule
7, NOR:USING VHDL:
library ieee;
entity nor2 is
end nor2;
architecture behave of nor2 is
begin
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c<=a nor b;
end behave;
USING VERILOG:
module nor2(a,b,c);
input a,b;
output c;
assign
c=~(a!b);
endmodule
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2..(a) FULL ADDER IN DATA FLOW MODELLING :VHDL:

library ieee;
entity F_A is
port (a,b,c : in std_logic; sum,carry :out std_logic);
end F_A;
architecture behave of F_A is
begin
sum<=a xor b xor c ;
carry<=(a and b)or(b and c)or(a and c);
end behave;
USING VERILOG:
module full_add(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum=(a^b^c);
assign carry=((a&b)!(b&c)!(a&c));
endmodule
(b )FULL ADDER IN BEHAVIORAL MODELLING:VHDL:

library ieee;
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entity F_A is
port (a,b,c : in std_logic ; sum,carry :out std_logic );
end F_A;
architecture behave of F_A is
begin
process(a,b,c)
begin
if(a=0 and b=0 and c=0)then
sum<=0;
carry<=0;
elsif(a=0 and b=0 and c=1)then
sum<=1;
carry<=0;
sum<=1;
carry<=0;
sum<=0;
carry<=1;
sum<=1;
carry<=0;
sum<=0;
carry<=1;
sum<=0;
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carry<=1;
sum<=1;
carry<=1;
end if;
end process;
end behave;
USING VERILOG:
module full_add(a,b,c,sum,carry);
input a,b,c;
output reg sum,carry;
always @(a,b,c)
if (a==0 & b==0 & c==0)
begin
sum=0;
carry=0;
end
else if(a==0 & b==0 & c==1)
begin
sum=1;
carry=0;
end
else if(a==0 & b==1 & c==0)
begin
sum=1;
carry=0;
end
else if(a==0 & b==1 & c==1)
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begin
sum=0;
carry=1;
end
else if(a==1 & b==0 & c==0)
begin
sum=1;
carry=0;
end
else if(a==1 & b==0 & c==1)
begin
sum=0;
carry=1;
end
else if(a==1 & b==1 & c==0)
begin
sum=0;
carry=1;
end
else
sum=1;
carry=1;
endmodule
(c) FULL ADDER IN STRUCTURAL:VHDL:

library ieee;
entity F_A is
port (a,b,c : in std_logic ; sum, carry :out std_logic);
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end F_A;
architecture structure of F_A is
component xor2 is
port(a,b:in bit; c:out bit);
end component;
component and2
port(a,b:in bit;c:out bit)
end component;
component or2
port(a,b:in bit;c:out bit);
end component;
signal s1,s2,s3,s4,s5 : bit;
begin
X1 : xor2 port map(a,b,s1);
X2 : xor2 port map(s, c, sum );
A1 : and2 port map(a,b,s2);
A2 : and2 port map(b,c,s3);
A3 : and2 port map(a,c,s4);
O1 : or2 port map(s2,s3,s5);
O2 : or2 port map(s4,s5,carry);
end structure;
IN VERILOG:
module full_add_struct(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire s1,s2,s3,s4,s5;
XOR X1(s1,a,b);
XOR X2(sum,s1,c);
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AND A1(s2,a,b);
AND A2(s3,b,c);
AND A3(s4,a,c);
OR O1(s5,s2,s3);
OR O2(carry,s4,s5);
endmodule
3.. 2 TO 4 DECODER WITH ACTIVE HIGH ENABLE USING CASE

[BEHAVIOURAL]:VHDL:
entity decoder _24 is
port ( xy : in bit _vector (1 down to 0); e:in bit;
d:out bit _vector (3 down to 0));
end decoder_24;
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architecture behave of decoder_24 is

begin
process (xy,e)
begin
if (e=0) then
d<=0000;
else
case (xy) is
when 00 =>d<=0001;
when 01=>d<=0010;
when 10 =>d<=0100;
when others =>d<=1000;
end case;
end if;
end process;
end behave;
VERILOG :
module decode_24 (xy,e,d);
input xy ,e;
output [3:0]d;
reg [3:0]d;
always @ (xy ,e)
if (e==0)
d=4b0000;
else
case ({x ,y})
2b00:d=4b0001;
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2b01:d=4b0010;
2b10:d=4b0100;
default : d=4b1000;
endcase
endmodule
4.. 8 TO 3 ENCODER WITHOUT PRIORITY :- VHDL :

entity enc_83 is
port (i: in bit _vector (7 downto o); x: out bit_vector (2 downto 0));
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end enc_83;
architecture without _priority of enc_83 is
begin
process (i)
begin
case i is
when 10000000=>x<=111;
when 01000000=>x<=110;
when 00100000=>x<=101;
when 00010000=>x<=100;
when 00001000=>x<=011;
when 000000100=>x<=010;
when 00000010=>x<=001;
when others=>x<=000;
end case;
end process;
end without _priority;
VERILOG :
module encoder_83 (i,x);
input [7:0] i ;
output reg [2:0] x ;
always @ (i)
case (i)
8b10000000: x=3b111;
8b01000000: x=3b110;
8b00100000: x=3b101;
8b00010000: x=3b100;
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8b00001000: x=3b011;
8b00000100: x=3b010;
8b00000010: x=3b001;
default
: x=3b000;
endcase
endmodule
5.. 8 TO 3 ENCODER WITH ACTIVE HIGH PRIORITY:

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VHDL:
library ieee;
entity enc_83 is
port (i: in std_logic _vector (7 downto 0); x:out std_logic _vector (2
downto 0));
end enc_83;
architecture priority of enc_83 is
begin
process (i,x)
begin
if ( i (7)=1)then
x< =111;
elsif (i(6)=1) then
x<=110;
elsif (i(5)=1) then
x<=101;
elsif (i(4)=1) then
x<=100;
elsif (i(3)=1) then
x<=011;
elsif (i(2)=1) then
x<=010;
elsif (i(1)=1) then
x<=001;
else
x<=000;
end if;
end process;
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end priority;
VERILOG :
module encoder _83 (i ,x);
input [7:0] i ;
output reg [2:0] x;
always @(i)
if (i[7]==1)
x=3b111;
else if (i[6]==1)
x=3b110;
else if (i[5]==1)
x=3b101;
else if (i[4]==1)
x=3b100;
else if (i[3]==1)
x=3b011;
else if (i[2]==1)
x=3b010;
else if (i[1]==1)
x=3b001;
else
x=3b000;
endmodule
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6.. 2:1 MULTIPLEXERS :VHDL:

entity mux_21 is
port (a ,b ,s: in bit; c : out bit);
end mux_21;
architecture behave of mux_21 is
begin
process (a ,b ,s)
begin
if (s=0) then
c<=a;
else
c<=b;
end if;
end process;
end behave;
VERILOG:
module mux_21 (a ,b ,s ,c);
input a, b , s ;
output reg c;
always @ (a ,b , s)
begin
if (s==0)
c=a;
else
c=b;
end
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endmodule
7.. 4:1 MUX:VHDL:

entity mux_41 is
port (i1,i2,i3,i4,s1,s0: in bit; z : out bit);
end mux_41;
component mux_21 is
port (a,b,s:in bit; c:out bit);
end component;
signal x,y: bit;
begin
M1:mux_21 port map(i1,i2,s1,x);
M2:mux_21 port map (i3,i4,s1,y);
M3:mux_21 port map(x,y,s0,z)
end behave;
VERILOG:
module mux_41(i1,i2,i3,i4,s1,s0,z);
input i1,i2,i3,i4,s1,s0;
output z;
wire x,y;
mux_21 m1(i1,i3,s1,x);
mux_21 m2(i2,i4,s1,y);
mux_21 m3 (x,y,s0,z);
endmodule
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8.. 8:1 MUX:-VHDL:

entity mux_81 is
port (i1,i2,i3,i4,i5,i6,i7,i8:in bit ; s2,s1,s0:in bit; z :out bit);
end mux_81;
component mux_41 is ;
port (i1,i2,i3,i4,s1,s0:in bit;z:out bit);
end component;
component mux_21 is
port (a ,b ,s :in bit ;c :out bit);
end component;
signal x,y:bit;
M1:mux_41 port map (i1,i2,i3,i4,s2,s1,x);
M2:mux_41 port map (i5,i6,i7,i8,s2,s1,y);
M3:mux_21 port map (x,y,s0,z);
end behave;
VERILOG:
module mux_81 (i0,i1,i2,i3,i4,i5,i6,i7,s2,s1,s0,z);
input i0,i1,i2,i3,i4,i5,i6,i7,s2,s1,s0;
output z;
wire x,y;
mux_41 m1(x,i0,i1,i2,i3,s1,s2);
mux_41 m2(y,i4,i5,i6,i7,s1,s2);
mux_21 m3(z,x,y,s0);
endmodule
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9.. 1 TO 4 DE-MULTIPLEXERS :VHDL:

entity demux_14 is
port(x,s0,s1:in bit; y:out bit_vector(3 downto 0));
end demux_14;
architecture behave of demux_14 is
begin
process(x,s0,s1)
begin
if (s0=0 and s1=0)then
y(0)<=x;
elsif(s0=0 and s1=1)then
y(1)<=x;
elsif(s0=1 and s1=0)then
y(2)<=x;
else
y(3)<=x;
end if;
end process;
end behave;
VERILOG:
module dm_14(x,s0,s1,y);
input x, s0,s1;
output reg[3:0]y;
always @(x,s0,s1)
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case({s0,s1})
2b00:y[0]=x;
2b01:y[1]=x;
2b10:y[2]=x;
2b11:y[3]=x;
endcase
endmodule
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10.. 4-BIT COMPARATOR: VHDL:

entity compare_4 is
port (a,b: in bit_vector (3 downto 0);aeqb,agtb,altb:out bit);
end compare_4;
architecture behave of comparator is
begin
process (a,b)
begin
if(a=b)then
aeqb<=1;
altb<=0;
agtb<=0;
elsif (a>b)then
aeqb<=0;
altb<=0;
agtb<=1;
elsif (a<b)then
aeqb<=0;
altb<=1;
agtb<=0;
end if;
end process;
end behave;
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4-BIT COMPARATOR IN VERILOG:

module comparator (a,b,aeqb,altb,agtb);
input [3:0]a,b;
output aeqb,altb,agtb;
reg aeqb,altb,agtb;
always @ (a,b)
begin
if (a==b)
begin
aeqb=1;
agtb=0;
altb=0;
end
else if(a>b)
begin
aeqb=0;
agtb=1;
altb=0;
end
else if(a<b)
begin
aeqb=0;
agtb=0;
altb=1;
end
endmodule
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11.. BINARY TO GRAY CONVERSION:- VHDL:

entity b to g is
port (b:in bit _vector (3 downto 0);
g:out bit _vector (3 downto 0));
end b to g;
architecture dataflow of b to g is
begin
g(3)<=b(3);
g(2)<=b(3) xor b(2);
g(1)<=b(2) xor b(1);
g(0)<=b(1) xor b(0);
end dataflow;
VERILOG:
module b_to_g (b,g);
input [3:0]b;
output [3:0]g;
assign g[3]=b[3];
assign g[2]=b[3]^b[2];
assign g[1]=b[2] ^b[1];
assign g[0]=b[1] ^b[0];
endmodule
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12.. GRAY TO BINARY CONVERSION: VHDL:

entity g to b is
port (g: in bit _vector(3 downto 0); b :out bit _vector (3 downto 0));
end g to b;
architecture behave of g to b is
begin
b[3]<=g(3);
b[2]<=g(3) xor g(2);
b[1]<=g(3) xor g(2) xor g(1);
b[2]<=g(3) xor g(2) xor g(1) xor g(0);
end behave;
VERILOG:
module g_to_b (g,b)
input [3:0]g;
output [3:0]b;
assign b[3]=g[3];
assign b[2]=g[3]^g[2];
assign b[1]=g[3]^g[2]^g[1];
assign b[0]=g[3]^g[2]^g[1]^g[0];
endmodule
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13.. HDL CODE FOR 4-BIT ALU : VHDL:

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity alu is
port (a,b,opcode:in std_logic _vector (3 downto 0);en:in std_logic ;
o:out std_logic _vector (3 downto 0);o1:out std_logic _vector (7 downto
0));
end alu;
architecture behave of alu is
begin
process (a,b,opcode,en)
begin
if (en=0)then
o<=0000;
o1<=00000000;
else
case opcode is
when 0000=>o<=a+b;
when 0001=>o<=a-b;
when 0010=>o<=not a;
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when 0011=>o1<=a*b;
when 0100=>o<=a and b;
when 0101=>o<=a or b;
when 0110=>o<=a nand b;
when 0111=>o<=a xor b;
when others =>null;
end case;
end if;
end process;
end behave;
ALU IN VEILOG:module alu(a,b,en,opcode,o,o1);

input [3:0]a,b,opcode;
input en;
output [3:0]o;
reg o;
output reg [7:0]o1;
always @[a,b,en,opcode]
if (en==0)
begin
o=4b0000;
o1=8b00000000;
end
else
case opcode
4b0000:o=a+b;
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4b0001:o=a-b;
4b0010:o=~a;
4b0011:o1=a*b;
4b0100:o=a&b;
4b0101:o=a!b;
4b0110:o=~(a&b);
4b0111:o=a^b;
default :=4b0000;
endcase
endmodule
15.. D- FLIP FLOP:- VHDL:

library ieee;
usse ieee.std_logic_1164.all;
entity d_ff is
port (clk,d:in std_logic: q: out std_logic);
end d_ff;
architecture behave of d_ff is
begin
process (clk,d)
variable temp: std_logic;
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begin
if rising_edge (clk)then
temp:=d;
end if;
q<=temp;
end process;
end behave;
VERILOG:
module dflipflop (clk,d,q);
input clk,d;
output reg q;
always @ (posedge clk)
q=d;
end module
16.. T-FLIP FLOP:- VHDL:

library ieee;
entity t _ff is
port (clk,t :in std_logic: q: out std_logic);
end t_ff;
architecture behave of t_ff is
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begin
process (clk,t)
variable temp: std_logic:=0;
begin
if (clk=1 and clk event)then
if (t=1)then
temp:=not temp;
end if;
q<=temp;
end if;
end process;
end behave;
VERILOG:
module t_ff (clk,t,q);
input clk,t;
output q;
reg q=1b0;
if (t==1)
q=~q;
end module
17.. VHDL CODE FOR J-K FLIPFLOP

library ieee;
use ieee.std_logic_1164.a11;
entity jk_ff is
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port (jk:in std_logic_vector(1 downto 0); clk:in std_logic; q,qb:out

std_logic);
end jk_ff;
architecture behave of jk_ff is
begin
process(clk)
variable temp1:std_logic:=0;
variable temp2:std_logic;
begin
if rising_edge(clk) then
case jk is
when 00=> temp 1 :=temp 1;
when 01=> temp 1 :=0;
when 10=> temp 1 :=1;
when 11=> temp 1 :=not temp 1;
when other =>null;
end case;
q<=temp 1;
temp 2<=not temp1;
qb<=temp2;
end if;
end process;
end behave;
IN VERILOG:module jk_ff(j,k,clk,q,qb);
input j,k,clk;
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output reg q,qb;

always @(posedge clk)
begin
case({j,k})
2d0 :q=q;
2d1 :q=0;
2d2 :q=1;
2d3 :q=~q;
endcase
qb=~q;
end
endmodule;
18.. SR FILP FLOP:-VHDL:library ieee

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entity sr_ff is
port(clk,sr:in std_logic:q,qbar:out std_logic);
end sr_ff;
architecture behave of sr_ff is
begin
process(sr,clk)
variable temp1,temp2:std_logic:=0;
begin
if rising_edge(clk) then
case sr is
when 00=> temp 1 :=temp 1;
when 01=> temp 1 :=0;
when 10=> temp 1 :=1;
when 11=> temp 1 :=x;
when other =>null;
end case;
q<=temp 1;
temp2:=not temp1;
qb<=temp 2:
end if;
end process;
end behave;
IN VERILOG:module sr_ff(s,r,clk,q,qb);
input s,r,clk;
output reg q,qb;
begin
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case({s,r})
2d0 :q=q;
2d1 :q=0;
2d2 :q=1;
default:q=1bx;
endcase
qb=~q;
end
endmodule
19.. SYNCHRONOUS RESET BCD COUNTER:-VHDL:IV SEM

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entity sy_rst is
port(clk,rst:in std_logic ;q:out std_logic_vector(3 downto 0));
end sy_rst;
architecture behave of sy_rst is
begin
process (clk,rst)
variable temp:std_logic_vector(3 downto 0):=1001;
begin
if(rising_edge(clk) then
if (rst=1) then
temp:=0000;
elsif(temp=1001)then
temp:=0000;
else
temp:=temp+1;
end if;
end if;
q<=temp;
end process;
end behave;
VERILOG:module syn_rst(clk,rst,q);
input clk,rst;
output[3:0]q;
reg[3:0]q=4d9;
begin
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if(rst==1)
q=4do;
else
begin
if(q==4d9)
q=4do;
else
q=q+1;
end
end
endmodule
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20.. ASYNCHRONOUS RESET BCD COUNTER:VHDL:

entity asy_rst is
end asy_rst;
architecture behave of asy_rst is
begin
process (clk,rst)
begin
if (rst=1) then
temp:=0000;
else
temp:=temp+1;
elsif(temp=1001)then
temp:=0000;
end if;
end if;
q<=temp;
end process;
end behave;
VERILOG:module asyn_rst(clk,rst,q);
input clk,rst;
output[3:0]q;
reg[3:0]q=4d9;
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always @(rst, clk)

begin
if(rst==1)
q=4do;
else
if(clk)
begin
if(q==4d9)
q=4d0;
else
q=q+1;
end
end
endmodule
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21.. 4 BIT ASYNCHRONOUS BINARY COUNTER :VHDL:entity asy_count is

end asy_count;
architecture behave of asy_count is
begin
process (clk,rst)
begin
if (rst=1) then
temp:=0000;
else
temp:=temp+1;
end if;
q<=temp;
end if;
end process;
end behave;
VERILOG:module asyn_count(clk,rst,q);
input clk,rst;
ssoutput[3:0]q;
reg[3:0]q=4d0;
always @(rst, clk)
begin
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if(rst)
q=4do;
else if(clk)
q=q+1;
endmodule
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22.. SYNCHRONOUS BINARY COUNTER:-VHDL:library ieee;

entity sy_bin is
port (clk:in std_logic;clr:in std_logic;q:out std_logic_vector (3 downto
0));
end sy-bin;
architecture behave of sy-bin is
begin
process (clk,clr)
variable temp : std_logic_vector(3 downto 0) :=0000;
begin
if(rising_edge (clk))then
if (clr =0)then
temp :=0000;
else
temp:=temp +1;
end if;
end if;
q<=temp;
end process;
end behave;
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VERILOG:module count-sy(clk,clr,q);
input clk,clr;
output reg[3:0]q;
begin
if (clr==0)
q=q+1;
else
q =4b0;
end
endmodule
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23.. VHDL CODE FOR DOWN COUNTER : 4 :BIT ASYNCHRONOUS

COUNTER USING T-FF
library ieee;
entity T_FF is
port (clk, T :in std_logic ;q :out std_logic);
end T_FF;
architecture behave of T_FF is
begin
procecc (clk)
variable temp : std_logic : =0;
begin
if (falling_edge (clk) then
if (T =1)then
temp : = not temp;
end if;
end if;
q<=temp;
end process;
end behave;
entity asy_count is
port (clk,reset : in std_logic; q : inout std_logic _vector (3 downto 0));
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end asy_count;
architecture structure of asy_count is
component T_FF
port (clk,T ,reset: in std_logic; q : out std_logic);
end component;
signal x,y:std_logic;
begin
y<=q(0) and q(1);
x<=y and q(2);
T0 :T_FF port map(clk,1,reset,q(0));
T1 :T_FF port map(clk,q(0),reset,q(1));
T2 :T_FF port map(clk,y,reset,q(2));
T3 :T_FF port map(clk,x,reset,q(3));
end structure;
VERILOG :- SYNCHRONOUS COUNTER USING T FLIP FLOP:module T_FF (clk,t,q);

input clk,T;
output q;
reg q=1b0;
if (T==1)
q=~q;
end module
module counter_sy(clk,rst,q);
input clk,rst;
output [3:0]q;
wire x,y ;
assign x=q[0] & q[1];
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assign y=x & q[2];

T-FF T1(q[0],clk,y,1,rst);
T-FF T2(q[1],clk,q[0],rst);
T-FF T3(q[2],clk,y,rst);
T-FF T4(q[3],clk,x,rst);
endmodule
24.. BCD COUNTER:VHDL:

library ieee;
entity decade_counter is
port (clk,rst: in std_logic ; q:out std _logic_vector(3 downto 0));
end decade_counter;
architecher behave of decade_counter is
singal clk1 :std_logic vector (20 downto o);
begin
process (clk)
begin
it rising_edge (clk) then
clk1 <=clk1+1;
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end if;
end process;
process (clk1(17))
variable temp:std_logic_vector (3 downto o):=0000;
begin
if rising_edge(clk_div(17))then
if (rst=1)then
temp:=0000;
else
if(temp:=1001)then
temp:=0000;
else
temp1:=temp1+1;
end if;
end if;
q<=temp;
end process;
end behave;
VERILOG:00 TO 99 COUNTER:
module dec_count(clk,rst,q1,q2);
input clk,rst;
output reg[3:0] q1,q2;
reg [20:0] clk_div;
always @(posedge (clk))
begin
clk_div=clk_div+1;
end
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aiways @(posedge clk_div[17])

begin
if(rst==1)
begin
q1=4do;
q2=4do;
end
else
begin
q1=q1+1;
if(q1=4d10)
begin
q2=q2+1;
q1=4do;
end
if(q2==4d10)
q2=4do;
end
end
endmodule
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25.. INTERFACING PROGRAMS ONLY IN VHDL:1..SEVEN SEGMENT DISPLAY

library ieee;
entity seven_seg is
port (clk:in std_logic;q;out std_logic_vector (6 downto 0));
end seven_seg ;
architecture behave of seven_seg is
signal clk1:std_logic_vector(20 downto 0);
signal count:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if rising_edge(clk)then
clk1<=clk1+1;
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end if;
end process;
process(clk1(17))
begin
if rising_edge(clk1(17))then
count <=count+1;
end if;
end process;
processs (count)
begin
case count is
when 0000=>q<=0111111;
when 0001=>q<=0000110;
when 0010=>q<=1011011;
when 0011=>q<=1001111;
when 0100=>q<=1100110;
when 0101=>q<=1101101;
when 0110=>q<=1111101;
when 0111=>q<=0000111;
when 1000=>q<=1111111;
when 1001=>q<=1101111;
when 1010=>q<=1110111;
when 1011=>q<=1111100;
when 1100=>q<=0111001;
when 1101=>q<=1011110;
when 1110=>q<=1111001;
when 1111=>q<=1110001;
when others=>null;
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end case;
end process;
end behave;
2...STEPPER MOTOR:library ieee;

entity step_motor is
port (clk,clk_wise:in std_logic;q:out std_logic_vector (3 downto 0));
end step_motor ;
architecture behave of step_motor is
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signal count:std_logic_vector(1 downto 0);
begin
process(clk)
begin
if rising_edge(clk)then
clk1<=clk1+1;
end if;
end process;
process(clk1(15))
begin
if (clk_wise=1)then
count <=count+1;
else
count<=count-1;
end if;
end if;
end process;
processs (count)
begin
case count is
when 00=>q<=0001;
when 01=>q<=1000;
when 10=>q<=0100;
when 11=>q<=0010;
when others=>null;
end case;
end process;
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end behave;
3...TO GENERATE TRIANGULAR WAVEFORMS USING DAC:library ieee;

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entity tri_wave is
port (clk;in std_logic;q:out std_logic_vector(7 downto 0));
end tri_wave;
architecture behave of tri_wave is
signal s1,s2:std_logic_vector(7 downto 0);
begin
process (clk)
begin
if rising_edge (ckl)then
if (s2=00000000)then
s1<=s1+1;
elsif(s2=11111111)then
s1<=s1-1;
end if;
end if;
end process;
process(s1)
begin
if(s1=11111111)then
s2=11111111;
s2=00000000;
end if;
end process;
q<=s1;
end behave;
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4...CODE FOR GENERATING WAVEFORMS OF SQUARE WAVE:library ieee;

entity squ_wave is
end squ_wave;
architecture behave of squ_wave is
begin
process (clk)
begin
if (s2=00000000)then
s1<=s1+1;
s1<=s1-1;
end if;
end process;
process(s1)
begin
if(s1=11111111)then
s2=11111111;
s2=00000000;
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end if;
end process;
q<=s2;
end behave;
5...CODE FOR GENERATING WAVEFORMS OF RAMP WAVE:library ieee;

entity ramp_wave is
end ramp_wave;
architecture behave of ramp_wave is
begin
process (clk)
begin
if (s2=00000000)then
s1<=s1+1;
s1<=00000000;
end if;
end process;
process(s1)
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begin
if(s1=11111111)then
s2=11111111;
s2=00000000;
end if;
end process;
q<=s1;
end behave;
6...CODE FOR GENERATING WAVEFORMS OF STAIRCASE WAVE:

library ieee;
entity stair_case is
end stair_case;
architecture behave of stair_case is
signal s1:std_logic_vector(7 downto 0);
begin
process (clk)
begin
clk<=clk+1;
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end if;
end process;
process(clk1(18))
begin
s1<=s1+51;
if (s1=11111111)
s1<=00000000;
end if;
end process;
q<=s1;
end behave;
THE END
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Realization of All Logic Gates With HDL Code

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Realization of All Logic Gates With HDL Code

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HDL LAB MANUAL

1, AND GATE:USING VHDL:

2, OR GATE :USING VHDL:

HDL LAB MANUAL

3, XOR GATE:USING VHDL:

4, XNOR :USING VHDL:

HDL LAB MANUAL

HDL LAB MANUAL

HDL LAB MANUAL

HDL LAB MANUAL

2..(a) FULL ADDER IN DATA FLOW MODELLING :VHDL:

(b )FULL ADDER IN BEHAVIORAL MODELLING:VHDL:

HDL LAB MANUAL

use ieee . std_logic_1164.all;

HDL LAB MANUAL

HDL LAB MANUAL

(c) FULL ADDER IN STRUCTURAL:VHDL:

HDL LAB MANUAL

HDL LAB MANUAL

3.. 2 TO 4 DECODER WITH ACTIVE HIGH ENABLE USING CASE

HDL LAB MANUAL

architecture behave of decoder_24 is

HDL LAB MANUAL

4.. 8 TO 3 ENCODER WITHOUT PRIORITY :- VHDL :

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end without _priority;

HDL LAB MANUAL

5.. 8 TO 3 ENCODER WITH ACTIVE HIGH PRIORITY:

HDL LAB MANUAL

HDL LAB MANUAL

HDL LAB MANUAL

6.. 2:1 MULTIPLEXERS :VHDL:

HDL LAB MANUAL

7.. 4:1 MUX:VHDL:

HDL LAB MANUAL

8.. 8:1 MUX:-VHDL:

HDL LAB MANUAL

9.. 1 TO 4 DE-MULTIPLEXERS :VHDL:

HDL LAB MANUAL

HDL LAB MANUAL

10.. 4-BIT COMPARATOR: VHDL:

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4-BIT COMPARATOR IN VERILOG:

HDL LAB MANUAL

11.. BINARY TO GRAY CONVERSION:- VHDL:

HDL LAB MANUAL

12.. GRAY TO BINARY CONVERSION: VHDL:

HDL LAB MANUAL

13.. HDL CODE FOR 4-BIT ALU : VHDL:

HDL LAB MANUAL

ALU IN VEILOG:module alu(a,b,en,opcode,o,o1);

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15.. D- FLIP FLOP:- VHDL:

HDL LAB MANUAL

16.. T-FLIP FLOP:- VHDL:

HDL LAB MANUAL

17.. VHDL CODE FOR J-K FLIPFLOP

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port (jk:in std_logic_vector(1 downto 0); clk:in std_logic; q,qb:out

HDL LAB MANUAL

output reg q,qb;

18.. SR FILP FLOP:-VHDL:library ieee

HDL LAB MANUAL